1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU102 RevA
4 *
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19	model = "ZynqMP ZCU102 RevA";
20	compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		i2c0 = &i2c0;
25		i2c1 = &i2c1;
26		mmc0 = &sdhci1;
27		rtc0 = &rtc;
28		serial0 = &uart0;
29		serial1 = &uart1;
30		serial2 = &dcc;
31	};
32
33	chosen {
34		bootargs = "earlycon";
35		stdout-path = "serial0:115200n8";
36	};
37
38	memory@0 {
39		device_type = "memory";
40		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
41	};
42
43	gpio-keys {
44		compatible = "gpio-keys";
45		autorepeat;
46		sw19 {
47			label = "sw19";
48			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
49			linux,code = <KEY_DOWN>;
50			wakeup-source;
51			autorepeat;
52		};
53	};
54
55	leds {
56		compatible = "gpio-leds";
57		heartbeat-led {
58			label = "heartbeat";
59			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
60			linux,default-trigger = "heartbeat";
61		};
62	};
63
64	ina226-u76 {
65		compatible = "iio-hwmon";
66		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
67	};
68	ina226-u77 {
69		compatible = "iio-hwmon";
70		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
71	};
72	ina226-u78 {
73		compatible = "iio-hwmon";
74		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
75	};
76	ina226-u87 {
77		compatible = "iio-hwmon";
78		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
79	};
80	ina226-u85 {
81		compatible = "iio-hwmon";
82		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
83	};
84	ina226-u86 {
85		compatible = "iio-hwmon";
86		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
87	};
88	ina226-u93 {
89		compatible = "iio-hwmon";
90		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
91	};
92	ina226-u88 {
93		compatible = "iio-hwmon";
94		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
95	};
96	ina226-u15 {
97		compatible = "iio-hwmon";
98		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
99	};
100	ina226-u92 {
101		compatible = "iio-hwmon";
102		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
103	};
104	ina226-u79 {
105		compatible = "iio-hwmon";
106		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
107	};
108	ina226-u81 {
109		compatible = "iio-hwmon";
110		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
111	};
112	ina226-u80 {
113		compatible = "iio-hwmon";
114		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
115	};
116	ina226-u84 {
117		compatible = "iio-hwmon";
118		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
119	};
120	ina226-u16 {
121		compatible = "iio-hwmon";
122		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
123	};
124	ina226-u65 {
125		compatible = "iio-hwmon";
126		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
127	};
128	ina226-u74 {
129		compatible = "iio-hwmon";
130		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
131	};
132	ina226-u75 {
133		compatible = "iio-hwmon";
134		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
135	};
136
137	/* 48MHz reference crystal */
138	ref48: ref48M {
139		compatible = "fixed-clock";
140		#clock-cells = <0>;
141		clock-frequency = <48000000>;
142	};
143
144	refhdmi: refhdmi {
145		compatible = "fixed-clock";
146		#clock-cells = <0>;
147		clock-frequency = <114285000>;
148	};
149};
150
151&can1 {
152	status = "okay";
153};
154
155&dcc {
156	status = "okay";
157};
158
159&fpd_dma_chan1 {
160	status = "okay";
161};
162
163&fpd_dma_chan2 {
164	status = "okay";
165};
166
167&fpd_dma_chan3 {
168	status = "okay";
169};
170
171&fpd_dma_chan4 {
172	status = "okay";
173};
174
175&fpd_dma_chan5 {
176	status = "okay";
177};
178
179&fpd_dma_chan6 {
180	status = "okay";
181};
182
183&fpd_dma_chan7 {
184	status = "okay";
185};
186
187&fpd_dma_chan8 {
188	status = "okay";
189};
190
191&gem3 {
192	status = "okay";
193	phy-handle = <&phy0>;
194	phy-mode = "rgmii-id";
195	phy0: ethernet-phy@21 {
196		reg = <21>;
197		ti,rx-internal-delay = <0x8>;
198		ti,tx-internal-delay = <0xa>;
199		ti,fifo-depth = <0x1>;
200		ti,dp83867-rxctrl-strap-quirk;
201	};
202};
203
204&gpio {
205	status = "okay";
206};
207
208&i2c0 {
209	status = "okay";
210	clock-frequency = <400000>;
211
212	tca6416_u97: gpio@20 {
213		compatible = "ti,tca6416";
214		reg = <0x20>;
215		gpio-controller; /* IRQ not connected */
216		#gpio-cells = <2>;
217		gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
218				"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
219				"", "", "", "", "", "", "", "", "";
220		gtr-sel0-hog {
221			gpio-hog;
222			gpios = <0 0>;
223			output-low; /* PCIE = 0, DP = 1 */
224			line-name = "sel0";
225		};
226		gtr-sel1-hog {
227			gpio-hog;
228			gpios = <1 0>;
229			output-high; /* PCIE = 0, DP = 1 */
230			line-name = "sel1";
231		};
232		gtr-sel2-hog {
233			gpio-hog;
234			gpios = <2 0>;
235			output-high; /* PCIE = 0, USB0 = 1 */
236			line-name = "sel2";
237		};
238		gtr-sel3-hog {
239			gpio-hog;
240			gpios = <3 0>;
241			output-high; /* PCIE = 0, SATA = 1 */
242			line-name = "sel3";
243		};
244	};
245
246	tca6416_u61: gpio@21 {
247		compatible = "ti,tca6416";
248		reg = <0x21>;
249		gpio-controller; /* IRQ not connected */
250		#gpio-cells = <2>;
251		gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
252				"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
253				"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
254				"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
255	};
256
257	i2c-mux@75 { /* u60 */
258		compatible = "nxp,pca9544";
259		#address-cells = <1>;
260		#size-cells = <0>;
261		reg = <0x75>;
262		i2c@0 {
263			#address-cells = <1>;
264			#size-cells = <0>;
265			reg = <0>;
266			/* PS_PMBUS */
267			u76: ina226@40 { /* u76 */
268				compatible = "ti,ina226";
269				#io-channel-cells = <1>;
270				label = "ina226-u76";
271				reg = <0x40>;
272				shunt-resistor = <5000>;
273			};
274			u77: ina226@41 { /* u77 */
275				compatible = "ti,ina226";
276				#io-channel-cells = <1>;
277				label = "ina226-u77";
278				reg = <0x41>;
279				shunt-resistor = <5000>;
280			};
281			u78: ina226@42 { /* u78 */
282				compatible = "ti,ina226";
283				#io-channel-cells = <1>;
284				label = "ina226-u78";
285				reg = <0x42>;
286				shunt-resistor = <5000>;
287			};
288			u87: ina226@43 { /* u87 */
289				compatible = "ti,ina226";
290				#io-channel-cells = <1>;
291				label = "ina226-u87";
292				reg = <0x43>;
293				shunt-resistor = <5000>;
294			};
295			u85: ina226@44 { /* u85 */
296				compatible = "ti,ina226";
297				#io-channel-cells = <1>;
298				label = "ina226-u85";
299				reg = <0x44>;
300				shunt-resistor = <5000>;
301			};
302			u86: ina226@45 { /* u86 */
303				compatible = "ti,ina226";
304				#io-channel-cells = <1>;
305				label = "ina226-u86";
306				reg = <0x45>;
307				shunt-resistor = <5000>;
308			};
309			u93: ina226@46 { /* u93 */
310				compatible = "ti,ina226";
311				#io-channel-cells = <1>;
312				label = "ina226-u93";
313				reg = <0x46>;
314				shunt-resistor = <5000>;
315			};
316			u88: ina226@47 { /* u88 */
317				compatible = "ti,ina226";
318				#io-channel-cells = <1>;
319				label = "ina226-u88";
320				reg = <0x47>;
321				shunt-resistor = <5000>;
322			};
323			u15: ina226@4a { /* u15 */
324				compatible = "ti,ina226";
325				#io-channel-cells = <1>;
326				label = "ina226-u15";
327				reg = <0x4a>;
328				shunt-resistor = <5000>;
329			};
330			u92: ina226@4b { /* u92 */
331				compatible = "ti,ina226";
332				#io-channel-cells = <1>;
333				label = "ina226-u92";
334				reg = <0x4b>;
335				shunt-resistor = <5000>;
336			};
337		};
338		i2c@1 {
339			#address-cells = <1>;
340			#size-cells = <0>;
341			reg = <1>;
342			/* PL_PMBUS */
343			u79: ina226@40 { /* u79 */
344				compatible = "ti,ina226";
345				#io-channel-cells = <1>;
346				label = "ina226-u79";
347				reg = <0x40>;
348				shunt-resistor = <2000>;
349			};
350			u81: ina226@41 { /* u81 */
351				compatible = "ti,ina226";
352				#io-channel-cells = <1>;
353				label = "ina226-u81";
354				reg = <0x41>;
355				shunt-resistor = <5000>;
356			};
357			u80: ina226@42 { /* u80 */
358				compatible = "ti,ina226";
359				#io-channel-cells = <1>;
360				label = "ina226-u80";
361				reg = <0x42>;
362				shunt-resistor = <5000>;
363			};
364			u84: ina226@43 { /* u84 */
365				compatible = "ti,ina226";
366				#io-channel-cells = <1>;
367				label = "ina226-u84";
368				reg = <0x43>;
369				shunt-resistor = <5000>;
370			};
371			u16: ina226@44 { /* u16 */
372				compatible = "ti,ina226";
373				#io-channel-cells = <1>;
374				label = "ina226-u16";
375				reg = <0x44>;
376				shunt-resistor = <5000>;
377			};
378			u65: ina226@45 { /* u65 */
379				compatible = "ti,ina226";
380				#io-channel-cells = <1>;
381				label = "ina226-u65";
382				reg = <0x45>;
383				shunt-resistor = <5000>;
384			};
385			u74: ina226@46 { /* u74 */
386				compatible = "ti,ina226";
387				#io-channel-cells = <1>;
388				label = "ina226-u74";
389				reg = <0x46>;
390				shunt-resistor = <5000>;
391			};
392			u75: ina226@47 { /* u75 */
393				compatible = "ti,ina226";
394				#io-channel-cells = <1>;
395				label = "ina226-u75";
396				reg = <0x47>;
397				shunt-resistor = <5000>;
398			};
399		};
400		i2c@2 {
401			#address-cells = <1>;
402			#size-cells = <0>;
403			reg = <2>;
404			/* MAXIM_PMBUS - 00 */
405			max15301@a { /* u46 */
406				compatible = "maxim,max15301";
407				reg = <0xa>;
408			};
409			max15303@b { /* u4 */
410				compatible = "maxim,max15303";
411				reg = <0xb>;
412			};
413			max15303@10 { /* u13 */
414				compatible = "maxim,max15303";
415				reg = <0x10>;
416			};
417			max15301@13 { /* u47 */
418				compatible = "maxim,max15301";
419				reg = <0x13>;
420			};
421			max15303@14 { /* u7 */
422				compatible = "maxim,max15303";
423				reg = <0x14>;
424			};
425			max15303@15 { /* u6 */
426				compatible = "maxim,max15303";
427				reg = <0x15>;
428			};
429			max15303@16 { /* u10 */
430				compatible = "maxim,max15303";
431				reg = <0x16>;
432			};
433			max15303@17 { /* u9 */
434				compatible = "maxim,max15303";
435				reg = <0x17>;
436			};
437			max15301@18 { /* u63 */
438				compatible = "maxim,max15301";
439				reg = <0x18>;
440			};
441			max15303@1a { /* u49 */
442				compatible = "maxim,max15303";
443				reg = <0x1a>;
444			};
445			max15303@1d { /* u18 */
446				compatible = "maxim,max15303";
447				reg = <0x1d>;
448			};
449			max15303@20 { /* u8 */
450				compatible = "maxim,max15303";
451				status = "disabled"; /* unreachable */
452				reg = <0x20>;
453			};
454
455			max20751@72 { /* u95 */
456				compatible = "maxim,max20751";
457				reg = <0x72>;
458			};
459			max20751@73 { /* u96 */
460				compatible = "maxim,max20751";
461				reg = <0x73>;
462			};
463		};
464		/* Bus 3 is not connected */
465	};
466};
467
468&i2c1 {
469	status = "okay";
470	clock-frequency = <400000>;
471
472	/* PL i2c via PCA9306 - u45 */
473	i2c-mux@74 { /* u34 */
474		compatible = "nxp,pca9548";
475		#address-cells = <1>;
476		#size-cells = <0>;
477		reg = <0x74>;
478		i2c@0 {
479			#address-cells = <1>;
480			#size-cells = <0>;
481			reg = <0>;
482			/*
483			 * IIC_EEPROM 1kB memory which uses 256B blocks
484			 * where every block has different address.
485			 *    0 - 256B address 0x54
486			 * 256B - 512B address 0x55
487			 * 512B - 768B address 0x56
488			 * 768B - 1024B address 0x57
489			 */
490			eeprom: eeprom@54 { /* u23 */
491				compatible = "atmel,24c08";
492				reg = <0x54>;
493			};
494		};
495		i2c@1 {
496			#address-cells = <1>;
497			#size-cells = <0>;
498			reg = <1>;
499			si5341: clock-generator@36 { /* SI5341 - u69 */
500				compatible = "silabs,si5341";
501				reg = <0x36>;
502				#clock-cells = <2>;
503				#address-cells = <1>;
504				#size-cells = <0>;
505				clocks = <&ref48>;
506				clock-names = "xtal";
507				clock-output-names = "si5341";
508
509				si5341_0: out@0 {
510					/* refclk0 for PS-GT, used for DP */
511					reg = <0>;
512					always-on;
513				};
514				si5341_2: out@2 {
515					/* refclk2 for PS-GT, used for USB3 */
516					reg = <2>;
517					always-on;
518				};
519				si5341_3: out@3 {
520					/* refclk3 for PS-GT, used for SATA */
521					reg = <3>;
522					always-on;
523				};
524				si5341_4: out@4 {
525					/* refclk4 for PS-GT, used for PCIE slot */
526					reg = <4>;
527					always-on;
528				};
529				si5341_5: out@5 {
530					/* refclk5 for PS-GT, used for PCIE */
531					reg = <5>;
532					always-on;
533				};
534				si5341_6: out@6 {
535					/* refclk6 PL CLK125 */
536					reg = <6>;
537					always-on;
538				};
539				si5341_7: out@7 {
540					/* refclk7 PL CLK74 */
541					reg = <7>;
542					always-on;
543				};
544				si5341_9: out@9 {
545					/* refclk9 used for PS_REF_CLK 33.3 MHz */
546					reg = <9>;
547					always-on;
548				};
549			};
550		};
551		i2c@2 {
552			#address-cells = <1>;
553			#size-cells = <0>;
554			reg = <2>;
555			si570_1: clock-generator@5d { /* USER SI570 - u42 */
556				#clock-cells = <0>;
557				compatible = "silabs,si570";
558				reg = <0x5d>;
559				temperature-stability = <50>;
560				factory-fout = <300000000>;
561				clock-frequency = <300000000>;
562				clock-output-names = "si570_user";
563			};
564		};
565		i2c@3 {
566			#address-cells = <1>;
567			#size-cells = <0>;
568			reg = <3>;
569			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
570				#clock-cells = <0>;
571				compatible = "silabs,si570";
572				reg = <0x5d>;
573				temperature-stability = <50>; /* copy from zc702 */
574				factory-fout = <156250000>;
575				clock-frequency = <148500000>;
576				clock-output-names = "si570_mgt";
577			};
578		};
579		i2c@4 {
580			#address-cells = <1>;
581			#size-cells = <0>;
582			reg = <4>;
583			/* SI5328 - u20 */
584		};
585		/* 5 - 7 unconnected */
586	};
587
588	i2c-mux@75 {
589		compatible = "nxp,pca9548"; /* u135 */
590		#address-cells = <1>;
591		#size-cells = <0>;
592		reg = <0x75>;
593
594		i2c@0 {
595			#address-cells = <1>;
596			#size-cells = <0>;
597			reg = <0>;
598			/* HPC0_IIC */
599		};
600		i2c@1 {
601			#address-cells = <1>;
602			#size-cells = <0>;
603			reg = <1>;
604			/* HPC1_IIC */
605		};
606		i2c@2 {
607			#address-cells = <1>;
608			#size-cells = <0>;
609			reg = <2>;
610			/* SYSMON */
611		};
612		i2c@3 {
613			#address-cells = <1>;
614			#size-cells = <0>;
615			reg = <3>;
616			/* DDR4 SODIMM */
617		};
618		i2c@4 {
619			#address-cells = <1>;
620			#size-cells = <0>;
621			reg = <4>;
622			/* SEP 3 */
623		};
624		i2c@5 {
625			#address-cells = <1>;
626			#size-cells = <0>;
627			reg = <5>;
628			/* SEP 2 */
629		};
630		i2c@6 {
631			#address-cells = <1>;
632			#size-cells = <0>;
633			reg = <6>;
634			/* SEP 1 */
635		};
636		i2c@7 {
637			#address-cells = <1>;
638			#size-cells = <0>;
639			reg = <7>;
640			/* SEP 0 */
641		};
642	};
643};
644
645&pcie {
646	status = "okay";
647};
648
649&psgtr {
650	status = "okay";
651	/* pcie, sata, usb3, dp */
652	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
653	clock-names = "ref0", "ref1", "ref2", "ref3";
654};
655
656&rtc {
657	status = "okay";
658};
659
660&sata {
661	status = "okay";
662	/* SATA OOB timing settings */
663	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
664	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
665	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
666	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
667	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
668	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
669	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
670	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
671	phy-names = "sata-phy";
672	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
673};
674
675/* SD1 with level shifter */
676&sdhci1 {
677	status = "okay";
678	no-1-8-v;
679	xlnx,mio-bank = <1>;
680};
681
682&uart0 {
683	status = "okay";
684};
685
686&uart1 {
687	status = "okay";
688};
689
690/* ULPI SMSC USB3320 */
691&usb0 {
692	status = "okay";
693	dr_mode = "host";
694};
695
696&watchdog0 {
697	status = "okay";
698};
699
700&zynqmp_dpdma {
701	status = "okay";
702};
703
704&zynqmp_dpsub {
705	status = "okay";
706	phy-names = "dp-phy0";
707	phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
708};
709