1/*
2 * Device Tree Source for UniPhier LD11 SoC
3 *
4 * Copyright (C) 2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10/memreserve/ 0x80000000 0x02000000;
11
12/ {
13	compatible = "socionext,uniphier-ld11";
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&gic>;
17
18	cpus {
19		#address-cells = <2>;
20		#size-cells = <0>;
21
22		cpu-map {
23			cluster0 {
24				core0 {
25					cpu = <&cpu0>;
26				};
27				core1 {
28					cpu = <&cpu1>;
29				};
30			};
31		};
32
33		cpu0: cpu@0 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53", "arm,armv8";
36			reg = <0 0x000>;
37			clocks = <&sys_clk 33>;
38			enable-method = "psci";
39			operating-points-v2 = <&cluster0_opp>;
40		};
41
42		cpu1: cpu@1 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a53", "arm,armv8";
45			reg = <0 0x001>;
46			clocks = <&sys_clk 33>;
47			enable-method = "psci";
48			operating-points-v2 = <&cluster0_opp>;
49		};
50	};
51
52	cluster0_opp: opp_table {
53		compatible = "operating-points-v2";
54		opp-shared;
55
56		opp-245000000 {
57			opp-hz = /bits/ 64 <245000000>;
58			clock-latency-ns = <300>;
59		};
60		opp-250000000 {
61			opp-hz = /bits/ 64 <250000000>;
62			clock-latency-ns = <300>;
63		};
64		opp-490000000 {
65			opp-hz = /bits/ 64 <490000000>;
66			clock-latency-ns = <300>;
67		};
68		opp-500000000 {
69			opp-hz = /bits/ 64 <500000000>;
70			clock-latency-ns = <300>;
71		};
72		opp-653334000 {
73			opp-hz = /bits/ 64 <653334000>;
74			clock-latency-ns = <300>;
75		};
76		opp-666667000 {
77			opp-hz = /bits/ 64 <666667000>;
78			clock-latency-ns = <300>;
79		};
80		opp-980000000 {
81			opp-hz = /bits/ 64 <980000000>;
82			clock-latency-ns = <300>;
83		};
84	};
85
86	psci {
87		compatible = "arm,psci-1.0";
88		method = "smc";
89	};
90
91	clocks {
92		refclk: ref {
93			compatible = "fixed-clock";
94			#clock-cells = <0>;
95			clock-frequency = <25000000>;
96		};
97	};
98
99	timer {
100		compatible = "arm,armv8-timer";
101		interrupts = <1 13 4>,
102			     <1 14 4>,
103			     <1 11 4>,
104			     <1 10 4>;
105	};
106
107	soc@0 {
108		compatible = "simple-bus";
109		#address-cells = <1>;
110		#size-cells = <1>;
111		ranges = <0 0 0 0xffffffff>;
112
113		serial0: serial@54006800 {
114			compatible = "socionext,uniphier-uart";
115			status = "disabled";
116			reg = <0x54006800 0x40>;
117			interrupts = <0 33 4>;
118			pinctrl-names = "default";
119			pinctrl-0 = <&pinctrl_uart0>;
120			clocks = <&peri_clk 0>;
121		};
122
123		serial1: serial@54006900 {
124			compatible = "socionext,uniphier-uart";
125			status = "disabled";
126			reg = <0x54006900 0x40>;
127			interrupts = <0 35 4>;
128			pinctrl-names = "default";
129			pinctrl-0 = <&pinctrl_uart1>;
130			clocks = <&peri_clk 1>;
131		};
132
133		serial2: serial@54006a00 {
134			compatible = "socionext,uniphier-uart";
135			status = "disabled";
136			reg = <0x54006a00 0x40>;
137			interrupts = <0 37 4>;
138			pinctrl-names = "default";
139			pinctrl-0 = <&pinctrl_uart2>;
140			clocks = <&peri_clk 2>;
141		};
142
143		serial3: serial@54006b00 {
144			compatible = "socionext,uniphier-uart";
145			status = "disabled";
146			reg = <0x54006b00 0x40>;
147			interrupts = <0 177 4>;
148			pinctrl-names = "default";
149			pinctrl-0 = <&pinctrl_uart3>;
150			clocks = <&peri_clk 3>;
151		};
152
153		i2c0: i2c@58780000 {
154			compatible = "socionext,uniphier-fi2c";
155			status = "disabled";
156			reg = <0x58780000 0x80>;
157			#address-cells = <1>;
158			#size-cells = <0>;
159			interrupts = <0 41 4>;
160			pinctrl-names = "default";
161			pinctrl-0 = <&pinctrl_i2c0>;
162			clocks = <&peri_clk 4>;
163			clock-frequency = <100000>;
164		};
165
166		i2c1: i2c@58781000 {
167			compatible = "socionext,uniphier-fi2c";
168			status = "disabled";
169			reg = <0x58781000 0x80>;
170			#address-cells = <1>;
171			#size-cells = <0>;
172			interrupts = <0 42 4>;
173			pinctrl-names = "default";
174			pinctrl-0 = <&pinctrl_i2c1>;
175			clocks = <&peri_clk 5>;
176			clock-frequency = <100000>;
177		};
178
179		i2c2: i2c@58782000 {
180			compatible = "socionext,uniphier-fi2c";
181			reg = <0x58782000 0x80>;
182			#address-cells = <1>;
183			#size-cells = <0>;
184			interrupts = <0 43 4>;
185			clocks = <&peri_clk 6>;
186			clock-frequency = <400000>;
187		};
188
189		i2c3: i2c@58783000 {
190			compatible = "socionext,uniphier-fi2c";
191			status = "disabled";
192			reg = <0x58783000 0x80>;
193			#address-cells = <1>;
194			#size-cells = <0>;
195			interrupts = <0 44 4>;
196			pinctrl-names = "default";
197			pinctrl-0 = <&pinctrl_i2c3>;
198			clocks = <&peri_clk 7>;
199			clock-frequency = <100000>;
200		};
201
202		i2c4: i2c@58784000 {
203			compatible = "socionext,uniphier-fi2c";
204			status = "disabled";
205			reg = <0x58784000 0x80>;
206			#address-cells = <1>;
207			#size-cells = <0>;
208			interrupts = <0 45 4>;
209			pinctrl-names = "default";
210			pinctrl-0 = <&pinctrl_i2c4>;
211			clocks = <&peri_clk 8>;
212			clock-frequency = <100000>;
213		};
214
215		i2c5: i2c@58785000 {
216			compatible = "socionext,uniphier-fi2c";
217			reg = <0x58785000 0x80>;
218			#address-cells = <1>;
219			#size-cells = <0>;
220			interrupts = <0 25 4>;
221			clocks = <&peri_clk 9>;
222			clock-frequency = <400000>;
223		};
224
225		system_bus: system-bus@58c00000 {
226			compatible = "socionext,uniphier-system-bus";
227			status = "disabled";
228			reg = <0x58c00000 0x400>;
229			#address-cells = <2>;
230			#size-cells = <1>;
231			pinctrl-names = "default";
232			pinctrl-0 = <&pinctrl_system_bus>;
233		};
234
235		smpctrl@59801000 {
236			compatible = "socionext,uniphier-smpctrl";
237			reg = <0x59801000 0x400>;
238		};
239
240		sdctrl@59810000 {
241			compatible = "socionext,uniphier-ld11-sdctrl",
242				     "simple-mfd", "syscon";
243			reg = <0x59810000 0x400>;
244
245			sd_rst: reset {
246				compatible = "socionext,uniphier-ld11-sd-reset";
247				#reset-cells = <1>;
248			};
249		};
250
251		perictrl@59820000 {
252			compatible = "socionext,uniphier-ld11-perictrl",
253				     "simple-mfd", "syscon";
254			reg = <0x59820000 0x200>;
255
256			peri_clk: clock {
257				compatible = "socionext,uniphier-ld11-peri-clock";
258				#clock-cells = <1>;
259			};
260
261			peri_rst: reset {
262				compatible = "socionext,uniphier-ld11-peri-reset";
263				#reset-cells = <1>;
264			};
265		};
266
267		emmc: sdhc@5a000000 {
268			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
269			reg = <0x5a000000 0x400>;
270			interrupts = <0 78 4>;
271			pinctrl-names = "default";
272			pinctrl-0 = <&pinctrl_emmc>;
273			clocks = <&sys_clk 4>;
274			bus-width = <8>;
275			mmc-ddr-1_8v;
276			mmc-hs200-1_8v;
277			cdns,phy-input-delay-legacy = <4>;
278			cdns,phy-input-delay-mmc-highspeed = <2>;
279			cdns,phy-input-delay-mmc-ddr = <3>;
280			cdns,phy-dll-delay-sdclk = <21>;
281			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
282		};
283
284		usb0: usb@5a800100 {
285			compatible = "socionext,uniphier-ehci", "generic-ehci";
286			status = "disabled";
287			reg = <0x5a800100 0x100>;
288			interrupts = <0 243 4>;
289			pinctrl-names = "default";
290			pinctrl-0 = <&pinctrl_usb0>;
291			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
292			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
293				 <&mio_rst 12>;
294		};
295
296		usb1: usb@5a810100 {
297			compatible = "socionext,uniphier-ehci", "generic-ehci";
298			status = "disabled";
299			reg = <0x5a810100 0x100>;
300			interrupts = <0 244 4>;
301			pinctrl-names = "default";
302			pinctrl-0 = <&pinctrl_usb1>;
303			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
304			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
305				 <&mio_rst 13>;
306		};
307
308		usb2: usb@5a820100 {
309			compatible = "socionext,uniphier-ehci", "generic-ehci";
310			status = "disabled";
311			reg = <0x5a820100 0x100>;
312			interrupts = <0 245 4>;
313			pinctrl-names = "default";
314			pinctrl-0 = <&pinctrl_usb2>;
315			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
316			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
317				 <&mio_rst 14>;
318		};
319
320		mioctrl@5b3e0000 {
321			compatible = "socionext,uniphier-ld11-mioctrl",
322				     "simple-mfd", "syscon";
323			reg = <0x5b3e0000 0x800>;
324
325			mio_clk: clock {
326				compatible = "socionext,uniphier-ld11-mio-clock";
327				#clock-cells = <1>;
328			};
329
330			mio_rst: reset {
331				compatible = "socionext,uniphier-ld11-mio-reset";
332				#reset-cells = <1>;
333				resets = <&sys_rst 7>;
334			};
335		};
336
337		soc-glue@5f800000 {
338			compatible = "socionext,uniphier-ld11-soc-glue",
339				     "simple-mfd", "syscon";
340			reg = <0x5f800000 0x2000>;
341
342			pinctrl: pinctrl {
343				compatible = "socionext,uniphier-ld11-pinctrl";
344			};
345		};
346
347		gic: interrupt-controller@5fe00000 {
348			compatible = "arm,gic-v3";
349			reg = <0x5fe00000 0x10000>,	/* GICD */
350			      <0x5fe40000 0x80000>;	/* GICR */
351			interrupt-controller;
352			#interrupt-cells = <3>;
353			interrupts = <1 9 4>;
354		};
355
356		sysctrl@61840000 {
357			compatible = "socionext,uniphier-ld11-sysctrl",
358				     "simple-mfd", "syscon";
359			reg = <0x61840000 0x10000>;
360
361			sys_clk: clock {
362				compatible = "socionext,uniphier-ld11-clock";
363				#clock-cells = <1>;
364			};
365
366			sys_rst: reset {
367				compatible = "socionext,uniphier-ld11-reset";
368				#reset-cells = <1>;
369			};
370
371			watchdog {
372				compatible = "socionext,uniphier-wdt";
373			};
374		};
375
376		nand: nand@68000000 {
377			compatible = "socionext,uniphier-denali-nand-v5b";
378			status = "disabled";
379			reg-names = "nand_data", "denali_reg";
380			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
381			interrupts = <0 65 4>;
382			pinctrl-names = "default";
383			pinctrl-0 = <&pinctrl_nand>;
384			clocks = <&sys_clk 2>;
385		};
386	};
387};
388
389#include "uniphier-pinctrl.dtsi"
390