1/*
2 * Device Tree Source for UniPhier LD11 SoC
3 *
4 * Copyright (C) 2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11
12/memreserve/ 0x80000000 0x02000000;
13
14/ {
15	compatible = "socionext,uniphier-ld11";
16	#address-cells = <2>;
17	#size-cells = <2>;
18	interrupt-parent = <&gic>;
19
20	cpus {
21		#address-cells = <2>;
22		#size-cells = <0>;
23
24		cpu-map {
25			cluster0 {
26				core0 {
27					cpu = <&cpu0>;
28				};
29				core1 {
30					cpu = <&cpu1>;
31				};
32			};
33		};
34
35		cpu0: cpu@0 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53", "arm,armv8";
38			reg = <0 0x000>;
39			clocks = <&sys_clk 33>;
40			enable-method = "psci";
41			operating-points-v2 = <&cluster0_opp>;
42		};
43
44		cpu1: cpu@1 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53", "arm,armv8";
47			reg = <0 0x001>;
48			clocks = <&sys_clk 33>;
49			enable-method = "psci";
50			operating-points-v2 = <&cluster0_opp>;
51		};
52	};
53
54	cluster0_opp: opp-table {
55		compatible = "operating-points-v2";
56		opp-shared;
57
58		opp-245000000 {
59			opp-hz = /bits/ 64 <245000000>;
60			clock-latency-ns = <300>;
61		};
62		opp-250000000 {
63			opp-hz = /bits/ 64 <250000000>;
64			clock-latency-ns = <300>;
65		};
66		opp-490000000 {
67			opp-hz = /bits/ 64 <490000000>;
68			clock-latency-ns = <300>;
69		};
70		opp-500000000 {
71			opp-hz = /bits/ 64 <500000000>;
72			clock-latency-ns = <300>;
73		};
74		opp-653334000 {
75			opp-hz = /bits/ 64 <653334000>;
76			clock-latency-ns = <300>;
77		};
78		opp-666667000 {
79			opp-hz = /bits/ 64 <666667000>;
80			clock-latency-ns = <300>;
81		};
82		opp-980000000 {
83			opp-hz = /bits/ 64 <980000000>;
84			clock-latency-ns = <300>;
85		};
86	};
87
88	psci {
89		compatible = "arm,psci-1.0";
90		method = "smc";
91	};
92
93	clocks {
94		refclk: ref {
95			compatible = "fixed-clock";
96			#clock-cells = <0>;
97			clock-frequency = <25000000>;
98		};
99	};
100
101	emmc_pwrseq: emmc-pwrseq {
102		compatible = "mmc-pwrseq-emmc";
103		reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
104	};
105
106	timer {
107		compatible = "arm,armv8-timer";
108		interrupts = <1 13 4>,
109			     <1 14 4>,
110			     <1 11 4>,
111			     <1 10 4>;
112	};
113
114	soc@0 {
115		compatible = "simple-bus";
116		#address-cells = <1>;
117		#size-cells = <1>;
118		ranges = <0 0 0 0xffffffff>;
119
120		serial0: serial@54006800 {
121			compatible = "socionext,uniphier-uart";
122			status = "disabled";
123			reg = <0x54006800 0x40>;
124			interrupts = <0 33 4>;
125			pinctrl-names = "default";
126			pinctrl-0 = <&pinctrl_uart0>;
127			clocks = <&peri_clk 0>;
128		};
129
130		serial1: serial@54006900 {
131			compatible = "socionext,uniphier-uart";
132			status = "disabled";
133			reg = <0x54006900 0x40>;
134			interrupts = <0 35 4>;
135			pinctrl-names = "default";
136			pinctrl-0 = <&pinctrl_uart1>;
137			clocks = <&peri_clk 1>;
138		};
139
140		serial2: serial@54006a00 {
141			compatible = "socionext,uniphier-uart";
142			status = "disabled";
143			reg = <0x54006a00 0x40>;
144			interrupts = <0 37 4>;
145			pinctrl-names = "default";
146			pinctrl-0 = <&pinctrl_uart2>;
147			clocks = <&peri_clk 2>;
148		};
149
150		serial3: serial@54006b00 {
151			compatible = "socionext,uniphier-uart";
152			status = "disabled";
153			reg = <0x54006b00 0x40>;
154			interrupts = <0 177 4>;
155			pinctrl-names = "default";
156			pinctrl-0 = <&pinctrl_uart3>;
157			clocks = <&peri_clk 3>;
158		};
159
160		gpio: gpio@55000000 {
161			compatible = "socionext,uniphier-gpio";
162			reg = <0x55000000 0x200>;
163			interrupt-parent = <&aidet>;
164			interrupt-controller;
165			#interrupt-cells = <2>;
166			gpio-controller;
167			#gpio-cells = <2>;
168			gpio-ranges = <&pinctrl 0 0 0>,
169				      <&pinctrl 43 0 0>,
170				      <&pinctrl 51 0 0>,
171				      <&pinctrl 96 0 0>,
172				      <&pinctrl 160 0 0>,
173				      <&pinctrl 184 0 0>;
174			gpio-ranges-group-names = "gpio_range0",
175						  "gpio_range1",
176						  "gpio_range2",
177						  "gpio_range3",
178						  "gpio_range4",
179						  "gpio_range5";
180			ngpios = <200>;
181			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
182						     <21 217 3>;
183		};
184
185		adamv@57920000 {
186			compatible = "socionext,uniphier-ld11-adamv",
187				     "simple-mfd", "syscon";
188			reg = <0x57920000 0x1000>;
189
190			adamv_rst: reset {
191				compatible = "socionext,uniphier-ld11-adamv-reset";
192				#reset-cells = <1>;
193			};
194		};
195
196		i2c0: i2c@58780000 {
197			compatible = "socionext,uniphier-fi2c";
198			status = "disabled";
199			reg = <0x58780000 0x80>;
200			#address-cells = <1>;
201			#size-cells = <0>;
202			interrupts = <0 41 4>;
203			pinctrl-names = "default";
204			pinctrl-0 = <&pinctrl_i2c0>;
205			clocks = <&peri_clk 4>;
206			clock-frequency = <100000>;
207		};
208
209		i2c1: i2c@58781000 {
210			compatible = "socionext,uniphier-fi2c";
211			status = "disabled";
212			reg = <0x58781000 0x80>;
213			#address-cells = <1>;
214			#size-cells = <0>;
215			interrupts = <0 42 4>;
216			pinctrl-names = "default";
217			pinctrl-0 = <&pinctrl_i2c1>;
218			clocks = <&peri_clk 5>;
219			clock-frequency = <100000>;
220		};
221
222		i2c2: i2c@58782000 {
223			compatible = "socionext,uniphier-fi2c";
224			reg = <0x58782000 0x80>;
225			#address-cells = <1>;
226			#size-cells = <0>;
227			interrupts = <0 43 4>;
228			clocks = <&peri_clk 6>;
229			clock-frequency = <400000>;
230		};
231
232		i2c3: i2c@58783000 {
233			compatible = "socionext,uniphier-fi2c";
234			status = "disabled";
235			reg = <0x58783000 0x80>;
236			#address-cells = <1>;
237			#size-cells = <0>;
238			interrupts = <0 44 4>;
239			pinctrl-names = "default";
240			pinctrl-0 = <&pinctrl_i2c3>;
241			clocks = <&peri_clk 7>;
242			clock-frequency = <100000>;
243		};
244
245		i2c4: i2c@58784000 {
246			compatible = "socionext,uniphier-fi2c";
247			status = "disabled";
248			reg = <0x58784000 0x80>;
249			#address-cells = <1>;
250			#size-cells = <0>;
251			interrupts = <0 45 4>;
252			pinctrl-names = "default";
253			pinctrl-0 = <&pinctrl_i2c4>;
254			clocks = <&peri_clk 8>;
255			clock-frequency = <100000>;
256		};
257
258		i2c5: i2c@58785000 {
259			compatible = "socionext,uniphier-fi2c";
260			reg = <0x58785000 0x80>;
261			#address-cells = <1>;
262			#size-cells = <0>;
263			interrupts = <0 25 4>;
264			clocks = <&peri_clk 9>;
265			clock-frequency = <400000>;
266		};
267
268		system_bus: system-bus@58c00000 {
269			compatible = "socionext,uniphier-system-bus";
270			status = "disabled";
271			reg = <0x58c00000 0x400>;
272			#address-cells = <2>;
273			#size-cells = <1>;
274			pinctrl-names = "default";
275			pinctrl-0 = <&pinctrl_system_bus>;
276		};
277
278		smpctrl@59801000 {
279			compatible = "socionext,uniphier-smpctrl";
280			reg = <0x59801000 0x400>;
281		};
282
283		sdctrl@59810000 {
284			compatible = "socionext,uniphier-ld11-sdctrl",
285				     "simple-mfd", "syscon";
286			reg = <0x59810000 0x400>;
287
288			sd_rst: reset {
289				compatible = "socionext,uniphier-ld11-sd-reset";
290				#reset-cells = <1>;
291			};
292		};
293
294		perictrl@59820000 {
295			compatible = "socionext,uniphier-ld11-perictrl",
296				     "simple-mfd", "syscon";
297			reg = <0x59820000 0x200>;
298
299			peri_clk: clock {
300				compatible = "socionext,uniphier-ld11-peri-clock";
301				#clock-cells = <1>;
302			};
303
304			peri_rst: reset {
305				compatible = "socionext,uniphier-ld11-peri-reset";
306				#reset-cells = <1>;
307			};
308		};
309
310		emmc: sdhc@5a000000 {
311			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
312			reg = <0x5a000000 0x400>;
313			interrupts = <0 78 4>;
314			pinctrl-names = "default";
315			pinctrl-0 = <&pinctrl_emmc>;
316			clocks = <&sys_clk 4>;
317			bus-width = <8>;
318			mmc-ddr-1_8v;
319			mmc-hs200-1_8v;
320			mmc-pwrseq = <&emmc_pwrseq>;
321			cdns,phy-input-delay-legacy = <4>;
322			cdns,phy-input-delay-mmc-highspeed = <2>;
323			cdns,phy-input-delay-mmc-ddr = <3>;
324			cdns,phy-dll-delay-sdclk = <21>;
325			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
326		};
327
328		usb0: usb@5a800100 {
329			compatible = "socionext,uniphier-ehci", "generic-ehci";
330			status = "disabled";
331			reg = <0x5a800100 0x100>;
332			interrupts = <0 243 4>;
333			pinctrl-names = "default";
334			pinctrl-0 = <&pinctrl_usb0>;
335			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
336			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
337				 <&mio_rst 12>;
338		};
339
340		usb1: usb@5a810100 {
341			compatible = "socionext,uniphier-ehci", "generic-ehci";
342			status = "disabled";
343			reg = <0x5a810100 0x100>;
344			interrupts = <0 244 4>;
345			pinctrl-names = "default";
346			pinctrl-0 = <&pinctrl_usb1>;
347			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
348			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
349				 <&mio_rst 13>;
350		};
351
352		usb2: usb@5a820100 {
353			compatible = "socionext,uniphier-ehci", "generic-ehci";
354			status = "disabled";
355			reg = <0x5a820100 0x100>;
356			interrupts = <0 245 4>;
357			pinctrl-names = "default";
358			pinctrl-0 = <&pinctrl_usb2>;
359			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
360			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
361				 <&mio_rst 14>;
362		};
363
364		mioctrl@5b3e0000 {
365			compatible = "socionext,uniphier-ld11-mioctrl",
366				     "simple-mfd", "syscon";
367			reg = <0x5b3e0000 0x800>;
368
369			mio_clk: clock {
370				compatible = "socionext,uniphier-ld11-mio-clock";
371				#clock-cells = <1>;
372			};
373
374			mio_rst: reset {
375				compatible = "socionext,uniphier-ld11-mio-reset";
376				#reset-cells = <1>;
377				resets = <&sys_rst 7>;
378			};
379		};
380
381		soc-glue@5f800000 {
382			compatible = "socionext,uniphier-ld11-soc-glue",
383				     "simple-mfd", "syscon";
384			reg = <0x5f800000 0x2000>;
385
386			pinctrl: pinctrl {
387				compatible = "socionext,uniphier-ld11-pinctrl";
388			};
389		};
390
391		soc-glue@5f900000 {
392			compatible = "socionext,uniphier-ld11-soc-glue-debug",
393				     "simple-mfd";
394			#address-cells = <1>;
395			#size-cells = <1>;
396			ranges = <0 0x5f900000 0x2000>;
397
398			efuse@100 {
399				compatible = "socionext,uniphier-efuse";
400				reg = <0x100 0x28>;
401			};
402
403			efuse@200 {
404				compatible = "socionext,uniphier-efuse";
405				reg = <0x200 0x68>;
406			};
407		};
408
409		aidet: aidet@5fc20000 {
410			compatible = "socionext,uniphier-ld11-aidet";
411			reg = <0x5fc20000 0x200>;
412			interrupt-controller;
413			#interrupt-cells = <2>;
414		};
415
416		gic: interrupt-controller@5fe00000 {
417			compatible = "arm,gic-v3";
418			reg = <0x5fe00000 0x10000>,	/* GICD */
419			      <0x5fe40000 0x80000>;	/* GICR */
420			interrupt-controller;
421			#interrupt-cells = <3>;
422			interrupts = <1 9 4>;
423		};
424
425		sysctrl@61840000 {
426			compatible = "socionext,uniphier-ld11-sysctrl",
427				     "simple-mfd", "syscon";
428			reg = <0x61840000 0x10000>;
429
430			sys_clk: clock {
431				compatible = "socionext,uniphier-ld11-clock";
432				#clock-cells = <1>;
433			};
434
435			sys_rst: reset {
436				compatible = "socionext,uniphier-ld11-reset";
437				#reset-cells = <1>;
438			};
439
440			watchdog {
441				compatible = "socionext,uniphier-wdt";
442			};
443		};
444
445		nand: nand@68000000 {
446			compatible = "socionext,uniphier-denali-nand-v5b";
447			status = "disabled";
448			reg-names = "nand_data", "denali_reg";
449			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
450			interrupts = <0 65 4>;
451			pinctrl-names = "default";
452			pinctrl-0 = <&pinctrl_nand>;
453			clocks = <&sys_clk 2>;
454		};
455	};
456};
457
458#include "uniphier-pinctrl.dtsi"
459