1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ 47 48/ { 49 compatible = "socionext,uniphier-ld11"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 }; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0 0x000>; 73 enable-method = "spin-table"; 74 cpu-release-addr = <0 0x80000000>; 75 }; 76 77 cpu1: cpu@1 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53", "arm,armv8"; 80 reg = <0 0x001>; 81 enable-method = "spin-table"; 82 cpu-release-addr = <0 0x80000000>; 83 }; 84 }; 85 86 clocks { 87 refclk: ref { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <25000000>; 91 }; 92 }; 93 94 timer { 95 compatible = "arm,armv8-timer"; 96 interrupts = <1 13 4>, 97 <1 14 4>, 98 <1 11 4>, 99 <1 10 4>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0 0 0xffffffff>; 107 108 serial0: serial@54006800 { 109 compatible = "socionext,uniphier-uart"; 110 status = "disabled"; 111 reg = <0x54006800 0x40>; 112 interrupts = <0 33 4>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_uart0>; 115 clocks = <&peri_clk 0>; 116 }; 117 118 serial1: serial@54006900 { 119 compatible = "socionext,uniphier-uart"; 120 status = "disabled"; 121 reg = <0x54006900 0x40>; 122 interrupts = <0 35 4>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_uart1>; 125 clocks = <&peri_clk 1>; 126 }; 127 128 serial2: serial@54006a00 { 129 compatible = "socionext,uniphier-uart"; 130 status = "disabled"; 131 reg = <0x54006a00 0x40>; 132 interrupts = <0 37 4>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_uart2>; 135 clocks = <&peri_clk 2>; 136 }; 137 138 serial3: serial@54006b00 { 139 compatible = "socionext,uniphier-uart"; 140 status = "disabled"; 141 reg = <0x54006b00 0x40>; 142 interrupts = <0 177 4>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_uart3>; 145 clocks = <&peri_clk 3>; 146 }; 147 148 i2c0: i2c@58780000 { 149 compatible = "socionext,uniphier-fi2c"; 150 status = "disabled"; 151 reg = <0x58780000 0x80>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 interrupts = <0 41 4>; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_i2c0>; 157 clocks = <&peri_clk 4>; 158 clock-frequency = <100000>; 159 }; 160 161 i2c1: i2c@58781000 { 162 compatible = "socionext,uniphier-fi2c"; 163 status = "disabled"; 164 reg = <0x58781000 0x80>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 interrupts = <0 42 4>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_i2c1>; 170 clocks = <&peri_clk 5>; 171 clock-frequency = <100000>; 172 }; 173 174 i2c2: i2c@58782000 { 175 compatible = "socionext,uniphier-fi2c"; 176 reg = <0x58782000 0x80>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 interrupts = <0 43 4>; 180 clocks = <&peri_clk 6>; 181 clock-frequency = <400000>; 182 }; 183 184 i2c3: i2c@58783000 { 185 compatible = "socionext,uniphier-fi2c"; 186 status = "disabled"; 187 reg = <0x58783000 0x80>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 interrupts = <0 44 4>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_i2c3>; 193 clocks = <&peri_clk 7>; 194 clock-frequency = <100000>; 195 }; 196 197 i2c4: i2c@58784000 { 198 compatible = "socionext,uniphier-fi2c"; 199 status = "disabled"; 200 reg = <0x58784000 0x80>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 interrupts = <0 45 4>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_i2c4>; 206 clocks = <&peri_clk 8>; 207 clock-frequency = <100000>; 208 }; 209 210 i2c5: i2c@58785000 { 211 compatible = "socionext,uniphier-fi2c"; 212 reg = <0x58785000 0x80>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 interrupts = <0 25 4>; 216 clocks = <&peri_clk 9>; 217 clock-frequency = <400000>; 218 }; 219 220 system_bus: system-bus@58c00000 { 221 compatible = "socionext,uniphier-system-bus"; 222 status = "disabled"; 223 reg = <0x58c00000 0x400>; 224 #address-cells = <2>; 225 #size-cells = <1>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_system_bus>; 228 }; 229 230 smpctrl@59800000 { 231 compatible = "socionext,uniphier-smpctrl"; 232 reg = <0x59801000 0x400>; 233 }; 234 235 perictrl@59820000 { 236 compatible = "socionext,uniphier-perictrl", 237 "simple-mfd", "syscon"; 238 reg = <0x59820000 0x200>; 239 240 peri_clk: clock { 241 compatible = "socionext,uniphier-ld11-peri-clock"; 242 #clock-cells = <1>; 243 }; 244 245 peri_rst: reset { 246 compatible = "socionext,uniphier-ld11-peri-reset"; 247 #reset-cells = <1>; 248 }; 249 }; 250 251 usb0: usb@5a800100 { 252 compatible = "socionext,uniphier-ehci", "generic-ehci"; 253 status = "disabled"; 254 reg = <0x5a800100 0x100>; 255 interrupts = <0 243 4>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_usb0>; 258 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 259 resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; 260 }; 261 262 usb1: usb@5a810100 { 263 compatible = "socionext,uniphier-ehci", "generic-ehci"; 264 status = "disabled"; 265 reg = <0x5a810100 0x100>; 266 interrupts = <0 244 4>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_usb1>; 269 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 270 resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; 271 }; 272 273 usb2: usb@5a820100 { 274 compatible = "socionext,uniphier-ehci", "generic-ehci"; 275 status = "disabled"; 276 reg = <0x5a820100 0x100>; 277 interrupts = <0 245 4>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_usb2>; 280 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 281 resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; 282 }; 283 284 mioctrl@5b3e0000 { 285 compatible = "socionext,uniphier-mioctrl", 286 "simple-mfd", "syscon"; 287 reg = <0x5b3e0000 0x800>; 288 289 mio_clk: clock { 290 compatible = "socionext,uniphier-ld11-mio-clock"; 291 #clock-cells = <1>; 292 }; 293 294 mio_rst: reset { 295 compatible = "socionext,uniphier-ld11-mio-reset"; 296 #reset-cells = <1>; 297 resets = <&sys_rst 7>; 298 }; 299 }; 300 301 soc-glue@5f800000 { 302 compatible = "socionext,uniphier-soc-glue", 303 "simple-mfd", "syscon"; 304 reg = <0x5f800000 0x2000>; 305 306 pinctrl: pinctrl { 307 compatible = "socionext,uniphier-ld11-pinctrl"; 308 }; 309 }; 310 311 gic: interrupt-controller@5fe00000 { 312 compatible = "arm,gic-v3"; 313 reg = <0x5fe00000 0x10000>, /* GICD */ 314 <0x5fe40000 0x80000>; /* GICR */ 315 interrupt-controller; 316 #interrupt-cells = <3>; 317 interrupts = <1 9 4>; 318 }; 319 320 sysctrl@61840000 { 321 compatible = "socionext,uniphier-ld11-sysctrl", 322 "simple-mfd", "syscon"; 323 reg = <0x61840000 0x4000>; 324 325 sys_clk: clock { 326 compatible = "socionext,uniphier-ld11-clock"; 327 #clock-cells = <1>; 328 }; 329 330 sys_rst: reset { 331 compatible = "socionext,uniphier-ld11-reset"; 332 #reset-cells = <1>; 333 }; 334 }; 335 }; 336}; 337 338/include/ "uniphier-pinctrl.dtsi" 339