1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x02000000; 47 48/ { 49 compatible = "socionext,uniphier-ld11"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 }; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0 0x000>; 73 clocks = <&sys_clk 33>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cluster0_opp>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 reg = <0 0x001>; 82 clocks = <&sys_clk 33>; 83 enable-method = "psci"; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 }; 87 88 cluster0_opp: opp_table { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-245000000 { 93 opp-hz = /bits/ 64 <245000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-250000000 { 97 opp-hz = /bits/ 64 <250000000>; 98 clock-latency-ns = <300>; 99 }; 100 opp-490000000 { 101 opp-hz = /bits/ 64 <490000000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-500000000 { 105 opp-hz = /bits/ 64 <500000000>; 106 clock-latency-ns = <300>; 107 }; 108 opp-653334000 { 109 opp-hz = /bits/ 64 <653334000>; 110 clock-latency-ns = <300>; 111 }; 112 opp-666667000 { 113 opp-hz = /bits/ 64 <666667000>; 114 clock-latency-ns = <300>; 115 }; 116 opp-980000000 { 117 opp-hz = /bits/ 64 <980000000>; 118 clock-latency-ns = <300>; 119 }; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0"; 124 method = "smc"; 125 }; 126 127 clocks { 128 refclk: ref { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <25000000>; 132 }; 133 }; 134 135 timer { 136 compatible = "arm,armv8-timer"; 137 interrupts = <1 13 4>, 138 <1 14 4>, 139 <1 11 4>, 140 <1 10 4>; 141 }; 142 143 soc@0 { 144 compatible = "simple-bus"; 145 #address-cells = <1>; 146 #size-cells = <1>; 147 ranges = <0 0 0 0xffffffff>; 148 149 serial0: serial@54006800 { 150 compatible = "socionext,uniphier-uart"; 151 status = "disabled"; 152 reg = <0x54006800 0x40>; 153 interrupts = <0 33 4>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_uart0>; 156 clocks = <&peri_clk 0>; 157 }; 158 159 serial1: serial@54006900 { 160 compatible = "socionext,uniphier-uart"; 161 status = "disabled"; 162 reg = <0x54006900 0x40>; 163 interrupts = <0 35 4>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_uart1>; 166 clocks = <&peri_clk 1>; 167 }; 168 169 serial2: serial@54006a00 { 170 compatible = "socionext,uniphier-uart"; 171 status = "disabled"; 172 reg = <0x54006a00 0x40>; 173 interrupts = <0 37 4>; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_uart2>; 176 clocks = <&peri_clk 2>; 177 }; 178 179 serial3: serial@54006b00 { 180 compatible = "socionext,uniphier-uart"; 181 status = "disabled"; 182 reg = <0x54006b00 0x40>; 183 interrupts = <0 177 4>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_uart3>; 186 clocks = <&peri_clk 3>; 187 }; 188 189 i2c0: i2c@58780000 { 190 compatible = "socionext,uniphier-fi2c"; 191 status = "disabled"; 192 reg = <0x58780000 0x80>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 interrupts = <0 41 4>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_i2c0>; 198 clocks = <&peri_clk 4>; 199 clock-frequency = <100000>; 200 }; 201 202 i2c1: i2c@58781000 { 203 compatible = "socionext,uniphier-fi2c"; 204 status = "disabled"; 205 reg = <0x58781000 0x80>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 interrupts = <0 42 4>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_i2c1>; 211 clocks = <&peri_clk 5>; 212 clock-frequency = <100000>; 213 }; 214 215 i2c2: i2c@58782000 { 216 compatible = "socionext,uniphier-fi2c"; 217 reg = <0x58782000 0x80>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 interrupts = <0 43 4>; 221 clocks = <&peri_clk 6>; 222 clock-frequency = <400000>; 223 }; 224 225 i2c3: i2c@58783000 { 226 compatible = "socionext,uniphier-fi2c"; 227 status = "disabled"; 228 reg = <0x58783000 0x80>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <0 44 4>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_i2c3>; 234 clocks = <&peri_clk 7>; 235 clock-frequency = <100000>; 236 }; 237 238 i2c4: i2c@58784000 { 239 compatible = "socionext,uniphier-fi2c"; 240 status = "disabled"; 241 reg = <0x58784000 0x80>; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 interrupts = <0 45 4>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_i2c4>; 247 clocks = <&peri_clk 8>; 248 clock-frequency = <100000>; 249 }; 250 251 i2c5: i2c@58785000 { 252 compatible = "socionext,uniphier-fi2c"; 253 reg = <0x58785000 0x80>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 interrupts = <0 25 4>; 257 clocks = <&peri_clk 9>; 258 clock-frequency = <400000>; 259 }; 260 261 system_bus: system-bus@58c00000 { 262 compatible = "socionext,uniphier-system-bus"; 263 status = "disabled"; 264 reg = <0x58c00000 0x400>; 265 #address-cells = <2>; 266 #size-cells = <1>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_system_bus>; 269 }; 270 271 smpctrl@59801000 { 272 compatible = "socionext,uniphier-smpctrl"; 273 reg = <0x59801000 0x400>; 274 }; 275 276 sdctrl@59810000 { 277 compatible = "socionext,uniphier-ld11-sdctrl", 278 "simple-mfd", "syscon"; 279 reg = <0x59810000 0x400>; 280 281 sd_rst: reset { 282 compatible = "socionext,uniphier-ld11-sd-reset"; 283 #reset-cells = <1>; 284 }; 285 }; 286 287 perictrl@59820000 { 288 compatible = "socionext,uniphier-ld11-perictrl", 289 "simple-mfd", "syscon"; 290 reg = <0x59820000 0x200>; 291 292 peri_clk: clock { 293 compatible = "socionext,uniphier-ld11-peri-clock"; 294 #clock-cells = <1>; 295 }; 296 297 peri_rst: reset { 298 compatible = "socionext,uniphier-ld11-peri-reset"; 299 #reset-cells = <1>; 300 }; 301 }; 302 303 emmc: sdhc@5a000000 { 304 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 305 reg = <0x5a000000 0x400>; 306 interrupts = <0 78 4>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_emmc>; 309 clocks = <&sys_clk 4>; 310 bus-width = <8>; 311 mmc-ddr-1_8v; 312 mmc-hs200-1_8v; 313 cdns,phy-input-delay-legacy = <4>; 314 cdns,phy-input-delay-mmc-highspeed = <2>; 315 cdns,phy-input-delay-mmc-ddr = <3>; 316 cdns,phy-dll-delay-sdclk = <21>; 317 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 318 }; 319 320 usb0: usb@5a800100 { 321 compatible = "socionext,uniphier-ehci", "generic-ehci"; 322 status = "disabled"; 323 reg = <0x5a800100 0x100>; 324 interrupts = <0 243 4>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_usb0>; 327 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 328 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 329 <&mio_rst 12>; 330 }; 331 332 usb1: usb@5a810100 { 333 compatible = "socionext,uniphier-ehci", "generic-ehci"; 334 status = "disabled"; 335 reg = <0x5a810100 0x100>; 336 interrupts = <0 244 4>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_usb1>; 339 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 340 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 341 <&mio_rst 13>; 342 }; 343 344 usb2: usb@5a820100 { 345 compatible = "socionext,uniphier-ehci", "generic-ehci"; 346 status = "disabled"; 347 reg = <0x5a820100 0x100>; 348 interrupts = <0 245 4>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_usb2>; 351 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 352 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 353 <&mio_rst 14>; 354 }; 355 356 mioctrl@5b3e0000 { 357 compatible = "socionext,uniphier-ld11-mioctrl", 358 "simple-mfd", "syscon"; 359 reg = <0x5b3e0000 0x800>; 360 361 mio_clk: clock { 362 compatible = "socionext,uniphier-ld11-mio-clock"; 363 #clock-cells = <1>; 364 }; 365 366 mio_rst: reset { 367 compatible = "socionext,uniphier-ld11-mio-reset"; 368 #reset-cells = <1>; 369 resets = <&sys_rst 7>; 370 }; 371 }; 372 373 soc-glue@5f800000 { 374 compatible = "socionext,uniphier-ld11-soc-glue", 375 "simple-mfd", "syscon"; 376 reg = <0x5f800000 0x2000>; 377 378 pinctrl: pinctrl { 379 compatible = "socionext,uniphier-ld11-pinctrl"; 380 }; 381 }; 382 383 gic: interrupt-controller@5fe00000 { 384 compatible = "arm,gic-v3"; 385 reg = <0x5fe00000 0x10000>, /* GICD */ 386 <0x5fe40000 0x80000>; /* GICR */ 387 interrupt-controller; 388 #interrupt-cells = <3>; 389 interrupts = <1 9 4>; 390 }; 391 392 sysctrl@61840000 { 393 compatible = "socionext,uniphier-ld11-sysctrl", 394 "simple-mfd", "syscon"; 395 reg = <0x61840000 0x10000>; 396 397 sys_clk: clock { 398 compatible = "socionext,uniphier-ld11-clock"; 399 #clock-cells = <1>; 400 }; 401 402 sys_rst: reset { 403 compatible = "socionext,uniphier-ld11-reset"; 404 #reset-cells = <1>; 405 }; 406 }; 407 }; 408}; 409 410/include/ "uniphier-pinctrl.dtsi" 411