1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD11 SoC 4// 5// Copyright (C) 2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "socionext,uniphier-ld11"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 }; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0 0x000>; 37 clocks = <&sys_clk 33>; 38 enable-method = "psci"; 39 operating-points-v2 = <&cluster0_opp>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53"; 45 reg = <0 0x001>; 46 clocks = <&sys_clk 33>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 }; 51 52 cluster0_opp: opp-table { 53 compatible = "operating-points-v2"; 54 opp-shared; 55 56 opp-245000000 { 57 opp-hz = /bits/ 64 <245000000>; 58 clock-latency-ns = <300>; 59 }; 60 opp-250000000 { 61 opp-hz = /bits/ 64 <250000000>; 62 clock-latency-ns = <300>; 63 }; 64 opp-490000000 { 65 opp-hz = /bits/ 64 <490000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-500000000 { 69 opp-hz = /bits/ 64 <500000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-653334000 { 73 opp-hz = /bits/ 64 <653334000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-666667000 { 77 opp-hz = /bits/ 64 <666667000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-980000000 { 81 opp-hz = /bits/ 64 <980000000>; 82 clock-latency-ns = <300>; 83 }; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 clocks { 92 refclk: ref { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <25000000>; 96 }; 97 }; 98 99 emmc_pwrseq: emmc-pwrseq { 100 compatible = "mmc-pwrseq-emmc"; 101 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 102 }; 103 104 timer { 105 compatible = "arm,armv8-timer"; 106 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 110 }; 111 112 reserved-memory { 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 secure-memory@81000000 { 118 reg = <0x0 0x81000000 0x0 0x01000000>; 119 no-map; 120 }; 121 }; 122 123 soc@0 { 124 compatible = "simple-bus"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0 0 0 0xffffffff>; 128 129 spi0: spi@54006000 { 130 compatible = "socionext,uniphier-scssi"; 131 status = "disabled"; 132 reg = <0x54006000 0x100>; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_spi0>; 138 clocks = <&peri_clk 11>; 139 resets = <&peri_rst 11>; 140 }; 141 142 spi1: spi@54006100 { 143 compatible = "socionext,uniphier-scssi"; 144 status = "disabled"; 145 reg = <0x54006100 0x100>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_spi1>; 151 clocks = <&peri_clk 12>; 152 resets = <&peri_rst 12>; 153 }; 154 155 serial0: serial@54006800 { 156 compatible = "socionext,uniphier-uart"; 157 status = "disabled"; 158 reg = <0x54006800 0x40>; 159 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_uart0>; 162 clocks = <&peri_clk 0>; 163 resets = <&peri_rst 0>; 164 }; 165 166 serial1: serial@54006900 { 167 compatible = "socionext,uniphier-uart"; 168 status = "disabled"; 169 reg = <0x54006900 0x40>; 170 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pinctrl_uart1>; 173 clocks = <&peri_clk 1>; 174 resets = <&peri_rst 1>; 175 }; 176 177 serial2: serial@54006a00 { 178 compatible = "socionext,uniphier-uart"; 179 status = "disabled"; 180 reg = <0x54006a00 0x40>; 181 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_uart2>; 184 clocks = <&peri_clk 2>; 185 resets = <&peri_rst 2>; 186 }; 187 188 serial3: serial@54006b00 { 189 compatible = "socionext,uniphier-uart"; 190 status = "disabled"; 191 reg = <0x54006b00 0x40>; 192 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_uart3>; 195 clocks = <&peri_clk 3>; 196 resets = <&peri_rst 3>; 197 }; 198 199 gpio: gpio@55000000 { 200 compatible = "socionext,uniphier-gpio"; 201 reg = <0x55000000 0x200>; 202 interrupt-parent = <&aidet>; 203 interrupt-controller; 204 #interrupt-cells = <2>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 gpio-ranges = <&pinctrl 0 0 0>, 208 <&pinctrl 43 0 0>, 209 <&pinctrl 51 0 0>, 210 <&pinctrl 96 0 0>, 211 <&pinctrl 160 0 0>, 212 <&pinctrl 184 0 0>; 213 gpio-ranges-group-names = "gpio_range0", 214 "gpio_range1", 215 "gpio_range2", 216 "gpio_range3", 217 "gpio_range4", 218 "gpio_range5"; 219 ngpios = <200>; 220 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 221 <21 217 3>; 222 }; 223 224 audio@56000000 { 225 compatible = "socionext,uniphier-ld11-aio"; 226 reg = <0x56000000 0x80000>; 227 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_aout1>, 230 <&pinctrl_aoutiec1>; 231 clock-names = "aio"; 232 clocks = <&sys_clk 40>; 233 reset-names = "aio"; 234 resets = <&sys_rst 40>; 235 #sound-dai-cells = <1>; 236 socionext,syscon = <&soc_glue>; 237 238 i2s_port0: port@0 { 239 i2s_hdmi: endpoint { 240 }; 241 }; 242 243 i2s_port1: port@1 { 244 i2s_pcmin2: endpoint { 245 }; 246 }; 247 248 i2s_port2: port@2 { 249 i2s_line: endpoint { 250 dai-format = "i2s"; 251 remote-endpoint = <&evea_line>; 252 }; 253 }; 254 255 i2s_port3: port@3 { 256 i2s_hpcmout1: endpoint { 257 }; 258 }; 259 260 i2s_port4: port@4 { 261 i2s_hp: endpoint { 262 dai-format = "i2s"; 263 remote-endpoint = <&evea_hp>; 264 }; 265 }; 266 267 spdif_port0: port@5 { 268 spdif_hiecout1: endpoint { 269 }; 270 }; 271 272 src_port0: port@6 { 273 i2s_epcmout2: endpoint { 274 }; 275 }; 276 277 src_port1: port@7 { 278 i2s_epcmout3: endpoint { 279 }; 280 }; 281 282 comp_spdif_port0: port@8 { 283 comp_spdif_hiecout1: endpoint { 284 }; 285 }; 286 }; 287 288 codec@57900000 { 289 compatible = "socionext,uniphier-evea"; 290 reg = <0x57900000 0x1000>; 291 clock-names = "evea", "exiv"; 292 clocks = <&sys_clk 41>, <&sys_clk 42>; 293 reset-names = "evea", "exiv", "adamv"; 294 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 295 #sound-dai-cells = <1>; 296 297 port@0 { 298 evea_line: endpoint { 299 remote-endpoint = <&i2s_line>; 300 }; 301 }; 302 303 port@1 { 304 evea_hp: endpoint { 305 remote-endpoint = <&i2s_hp>; 306 }; 307 }; 308 }; 309 310 adamv@57920000 { 311 compatible = "socionext,uniphier-ld11-adamv", 312 "simple-mfd", "syscon"; 313 reg = <0x57920000 0x1000>; 314 315 adamv_rst: reset { 316 compatible = "socionext,uniphier-ld11-adamv-reset"; 317 #reset-cells = <1>; 318 }; 319 }; 320 321 i2c0: i2c@58780000 { 322 compatible = "socionext,uniphier-fi2c"; 323 status = "disabled"; 324 reg = <0x58780000 0x80>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_i2c0>; 330 clocks = <&peri_clk 4>; 331 resets = <&peri_rst 4>; 332 clock-frequency = <100000>; 333 }; 334 335 i2c1: i2c@58781000 { 336 compatible = "socionext,uniphier-fi2c"; 337 status = "disabled"; 338 reg = <0x58781000 0x80>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_i2c1>; 344 clocks = <&peri_clk 5>; 345 resets = <&peri_rst 5>; 346 clock-frequency = <100000>; 347 }; 348 349 i2c2: i2c@58782000 { 350 compatible = "socionext,uniphier-fi2c"; 351 reg = <0x58782000 0x80>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&peri_clk 6>; 356 resets = <&peri_rst 6>; 357 clock-frequency = <400000>; 358 }; 359 360 i2c3: i2c@58783000 { 361 compatible = "socionext,uniphier-fi2c"; 362 status = "disabled"; 363 reg = <0x58783000 0x80>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_i2c3>; 369 clocks = <&peri_clk 7>; 370 resets = <&peri_rst 7>; 371 clock-frequency = <100000>; 372 }; 373 374 i2c4: i2c@58784000 { 375 compatible = "socionext,uniphier-fi2c"; 376 status = "disabled"; 377 reg = <0x58784000 0x80>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_i2c4>; 383 clocks = <&peri_clk 8>; 384 resets = <&peri_rst 8>; 385 clock-frequency = <100000>; 386 }; 387 388 i2c5: i2c@58785000 { 389 compatible = "socionext,uniphier-fi2c"; 390 reg = <0x58785000 0x80>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&peri_clk 9>; 395 resets = <&peri_rst 9>; 396 clock-frequency = <400000>; 397 }; 398 399 system_bus: system-bus@58c00000 { 400 compatible = "socionext,uniphier-system-bus"; 401 status = "disabled"; 402 reg = <0x58c00000 0x400>; 403 #address-cells = <2>; 404 #size-cells = <1>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_system_bus>; 407 }; 408 409 smpctrl@59801000 { 410 compatible = "socionext,uniphier-smpctrl"; 411 reg = <0x59801000 0x400>; 412 }; 413 414 sdctrl@59810000 { 415 compatible = "socionext,uniphier-ld11-sdctrl", 416 "simple-mfd", "syscon"; 417 reg = <0x59810000 0x400>; 418 419 sd_rst: reset { 420 compatible = "socionext,uniphier-ld11-sd-reset"; 421 #reset-cells = <1>; 422 }; 423 }; 424 425 perictrl@59820000 { 426 compatible = "socionext,uniphier-ld11-perictrl", 427 "simple-mfd", "syscon"; 428 reg = <0x59820000 0x200>; 429 430 peri_clk: clock { 431 compatible = "socionext,uniphier-ld11-peri-clock"; 432 #clock-cells = <1>; 433 }; 434 435 peri_rst: reset { 436 compatible = "socionext,uniphier-ld11-peri-reset"; 437 #reset-cells = <1>; 438 }; 439 }; 440 441 emmc: mmc@5a000000 { 442 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 443 reg = <0x5a000000 0x400>; 444 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_emmc>; 447 clocks = <&sys_clk 4>; 448 resets = <&sys_rst 4>; 449 bus-width = <8>; 450 mmc-ddr-1_8v; 451 mmc-hs200-1_8v; 452 mmc-pwrseq = <&emmc_pwrseq>; 453 cdns,phy-input-delay-legacy = <9>; 454 cdns,phy-input-delay-mmc-highspeed = <2>; 455 cdns,phy-input-delay-mmc-ddr = <3>; 456 cdns,phy-dll-delay-sdclk = <21>; 457 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 458 }; 459 460 usb0: usb@5a800100 { 461 compatible = "socionext,uniphier-ehci", "generic-ehci"; 462 status = "disabled"; 463 reg = <0x5a800100 0x100>; 464 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&pinctrl_usb0>; 467 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 468 <&mio_clk 12>; 469 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 470 <&mio_rst 12>; 471 phy-names = "usb"; 472 phys = <&usb_phy0>; 473 has-transaction-translator; 474 }; 475 476 usb1: usb@5a810100 { 477 compatible = "socionext,uniphier-ehci", "generic-ehci"; 478 status = "disabled"; 479 reg = <0x5a810100 0x100>; 480 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_usb1>; 483 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 484 <&mio_clk 13>; 485 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 486 <&mio_rst 13>; 487 phy-names = "usb"; 488 phys = <&usb_phy1>; 489 has-transaction-translator; 490 }; 491 492 usb2: usb@5a820100 { 493 compatible = "socionext,uniphier-ehci", "generic-ehci"; 494 status = "disabled"; 495 reg = <0x5a820100 0x100>; 496 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&pinctrl_usb2>; 499 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 500 <&mio_clk 14>; 501 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 502 <&mio_rst 14>; 503 phy-names = "usb"; 504 phys = <&usb_phy2>; 505 has-transaction-translator; 506 }; 507 508 mioctrl@5b3e0000 { 509 compatible = "socionext,uniphier-ld11-mioctrl", 510 "simple-mfd", "syscon"; 511 reg = <0x5b3e0000 0x800>; 512 513 mio_clk: clock { 514 compatible = "socionext,uniphier-ld11-mio-clock"; 515 #clock-cells = <1>; 516 }; 517 518 mio_rst: reset { 519 compatible = "socionext,uniphier-ld11-mio-reset"; 520 #reset-cells = <1>; 521 resets = <&sys_rst 7>; 522 }; 523 }; 524 525 soc_glue: soc-glue@5f800000 { 526 compatible = "socionext,uniphier-ld11-soc-glue", 527 "simple-mfd", "syscon"; 528 reg = <0x5f800000 0x2000>; 529 530 pinctrl: pinctrl { 531 compatible = "socionext,uniphier-ld11-pinctrl"; 532 }; 533 534 usb-controller { 535 compatible = "socionext,uniphier-ld11-usb2-phy"; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 539 usb_phy0: phy@0 { 540 reg = <0>; 541 #phy-cells = <0>; 542 }; 543 544 usb_phy1: phy@1 { 545 reg = <1>; 546 #phy-cells = <0>; 547 }; 548 549 usb_phy2: phy@2 { 550 reg = <2>; 551 #phy-cells = <0>; 552 }; 553 }; 554 }; 555 556 soc-glue@5f900000 { 557 compatible = "socionext,uniphier-ld11-soc-glue-debug", 558 "simple-mfd"; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 ranges = <0 0x5f900000 0x2000>; 562 563 efuse@100 { 564 compatible = "socionext,uniphier-efuse"; 565 reg = <0x100 0x28>; 566 }; 567 568 efuse@200 { 569 compatible = "socionext,uniphier-efuse"; 570 reg = <0x200 0x68>; 571 }; 572 }; 573 574 xdmac: dma-controller@5fc10000 { 575 compatible = "socionext,uniphier-xdmac"; 576 reg = <0x5fc10000 0x5300>; 577 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 578 dma-channels = <16>; 579 #dma-cells = <2>; 580 }; 581 582 aidet: interrupt-controller@5fc20000 { 583 compatible = "socionext,uniphier-ld11-aidet"; 584 reg = <0x5fc20000 0x200>; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 589 gic: interrupt-controller@5fe00000 { 590 compatible = "arm,gic-v3"; 591 reg = <0x5fe00000 0x10000>, /* GICD */ 592 <0x5fe40000 0x80000>; /* GICR */ 593 interrupt-controller; 594 #interrupt-cells = <3>; 595 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 596 }; 597 598 sysctrl@61840000 { 599 compatible = "socionext,uniphier-ld11-sysctrl", 600 "simple-mfd", "syscon"; 601 reg = <0x61840000 0x10000>; 602 603 sys_clk: clock { 604 compatible = "socionext,uniphier-ld11-clock"; 605 #clock-cells = <1>; 606 }; 607 608 sys_rst: reset { 609 compatible = "socionext,uniphier-ld11-reset"; 610 #reset-cells = <1>; 611 }; 612 613 watchdog { 614 compatible = "socionext,uniphier-wdt"; 615 }; 616 }; 617 618 eth: ethernet@65000000 { 619 compatible = "socionext,uniphier-ld11-ave4"; 620 status = "disabled"; 621 reg = <0x65000000 0x8500>; 622 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 623 clock-names = "ether"; 624 clocks = <&sys_clk 6>; 625 reset-names = "ether"; 626 resets = <&sys_rst 6>; 627 phy-mode = "internal"; 628 local-mac-address = [00 00 00 00 00 00]; 629 socionext,syscon-phy-mode = <&soc_glue 0>; 630 631 mdio: mdio { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 }; 635 }; 636 637 nand: nand-controller@68000000 { 638 compatible = "socionext,uniphier-denali-nand-v5b"; 639 status = "disabled"; 640 reg-names = "nand_data", "denali_reg"; 641 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pinctrl_nand>; 647 clock-names = "nand", "nand_x", "ecc"; 648 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 649 reset-names = "nand", "reg"; 650 resets = <&sys_rst 2>, <&sys_rst 2>; 651 }; 652 }; 653}; 654 655#include "uniphier-pinctrl.dtsi" 656 657&pinctrl_aoutiec1 { 658 drive-strength = <4>; /* default: 4mA */ 659 660 ao1arc { 661 pins = "AO1ARC"; 662 drive-strength = <8>; /* 8mA */ 663 }; 664}; 665