1/*
2 * Device Tree Source for UniPhier LD11 SoC
3 *
4 * Copyright (C) 2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11
12/memreserve/ 0x80000000 0x02000000;
13
14/ {
15	compatible = "socionext,uniphier-ld11";
16	#address-cells = <2>;
17	#size-cells = <2>;
18	interrupt-parent = <&gic>;
19
20	cpus {
21		#address-cells = <2>;
22		#size-cells = <0>;
23
24		cpu-map {
25			cluster0 {
26				core0 {
27					cpu = <&cpu0>;
28				};
29				core1 {
30					cpu = <&cpu1>;
31				};
32			};
33		};
34
35		cpu0: cpu@0 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53", "arm,armv8";
38			reg = <0 0x000>;
39			clocks = <&sys_clk 33>;
40			enable-method = "psci";
41			operating-points-v2 = <&cluster0_opp>;
42		};
43
44		cpu1: cpu@1 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53", "arm,armv8";
47			reg = <0 0x001>;
48			clocks = <&sys_clk 33>;
49			enable-method = "psci";
50			operating-points-v2 = <&cluster0_opp>;
51		};
52	};
53
54	cluster0_opp: opp-table {
55		compatible = "operating-points-v2";
56		opp-shared;
57
58		opp-245000000 {
59			opp-hz = /bits/ 64 <245000000>;
60			clock-latency-ns = <300>;
61		};
62		opp-250000000 {
63			opp-hz = /bits/ 64 <250000000>;
64			clock-latency-ns = <300>;
65		};
66		opp-490000000 {
67			opp-hz = /bits/ 64 <490000000>;
68			clock-latency-ns = <300>;
69		};
70		opp-500000000 {
71			opp-hz = /bits/ 64 <500000000>;
72			clock-latency-ns = <300>;
73		};
74		opp-653334000 {
75			opp-hz = /bits/ 64 <653334000>;
76			clock-latency-ns = <300>;
77		};
78		opp-666667000 {
79			opp-hz = /bits/ 64 <666667000>;
80			clock-latency-ns = <300>;
81		};
82		opp-980000000 {
83			opp-hz = /bits/ 64 <980000000>;
84			clock-latency-ns = <300>;
85		};
86	};
87
88	psci {
89		compatible = "arm,psci-1.0";
90		method = "smc";
91	};
92
93	clocks {
94		refclk: ref {
95			compatible = "fixed-clock";
96			#clock-cells = <0>;
97			clock-frequency = <25000000>;
98		};
99	};
100
101	emmc_pwrseq: emmc-pwrseq {
102		compatible = "mmc-pwrseq-emmc";
103		reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
104	};
105
106	timer {
107		compatible = "arm,armv8-timer";
108		interrupts = <1 13 4>,
109			     <1 14 4>,
110			     <1 11 4>,
111			     <1 10 4>;
112	};
113
114	soc@0 {
115		compatible = "simple-bus";
116		#address-cells = <1>;
117		#size-cells = <1>;
118		ranges = <0 0 0 0xffffffff>;
119
120		serial0: serial@54006800 {
121			compatible = "socionext,uniphier-uart";
122			status = "disabled";
123			reg = <0x54006800 0x40>;
124			interrupts = <0 33 4>;
125			pinctrl-names = "default";
126			pinctrl-0 = <&pinctrl_uart0>;
127			clocks = <&peri_clk 0>;
128			resets = <&peri_rst 0>;
129		};
130
131		serial1: serial@54006900 {
132			compatible = "socionext,uniphier-uart";
133			status = "disabled";
134			reg = <0x54006900 0x40>;
135			interrupts = <0 35 4>;
136			pinctrl-names = "default";
137			pinctrl-0 = <&pinctrl_uart1>;
138			clocks = <&peri_clk 1>;
139			resets = <&peri_rst 1>;
140		};
141
142		serial2: serial@54006a00 {
143			compatible = "socionext,uniphier-uart";
144			status = "disabled";
145			reg = <0x54006a00 0x40>;
146			interrupts = <0 37 4>;
147			pinctrl-names = "default";
148			pinctrl-0 = <&pinctrl_uart2>;
149			clocks = <&peri_clk 2>;
150			resets = <&peri_rst 2>;
151		};
152
153		serial3: serial@54006b00 {
154			compatible = "socionext,uniphier-uart";
155			status = "disabled";
156			reg = <0x54006b00 0x40>;
157			interrupts = <0 177 4>;
158			pinctrl-names = "default";
159			pinctrl-0 = <&pinctrl_uart3>;
160			clocks = <&peri_clk 3>;
161			resets = <&peri_rst 3>;
162		};
163
164		gpio: gpio@55000000 {
165			compatible = "socionext,uniphier-gpio";
166			reg = <0x55000000 0x200>;
167			interrupt-parent = <&aidet>;
168			interrupt-controller;
169			#interrupt-cells = <2>;
170			gpio-controller;
171			#gpio-cells = <2>;
172			gpio-ranges = <&pinctrl 0 0 0>,
173				      <&pinctrl 43 0 0>,
174				      <&pinctrl 51 0 0>,
175				      <&pinctrl 96 0 0>,
176				      <&pinctrl 160 0 0>,
177				      <&pinctrl 184 0 0>;
178			gpio-ranges-group-names = "gpio_range0",
179						  "gpio_range1",
180						  "gpio_range2",
181						  "gpio_range3",
182						  "gpio_range4",
183						  "gpio_range5";
184			ngpios = <200>;
185			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
186						     <21 217 3>;
187		};
188
189		adamv@57920000 {
190			compatible = "socionext,uniphier-ld11-adamv",
191				     "simple-mfd", "syscon";
192			reg = <0x57920000 0x1000>;
193
194			adamv_rst: reset {
195				compatible = "socionext,uniphier-ld11-adamv-reset";
196				#reset-cells = <1>;
197			};
198		};
199
200		i2c0: i2c@58780000 {
201			compatible = "socionext,uniphier-fi2c";
202			status = "disabled";
203			reg = <0x58780000 0x80>;
204			#address-cells = <1>;
205			#size-cells = <0>;
206			interrupts = <0 41 4>;
207			pinctrl-names = "default";
208			pinctrl-0 = <&pinctrl_i2c0>;
209			clocks = <&peri_clk 4>;
210			resets = <&peri_rst 4>;
211			clock-frequency = <100000>;
212		};
213
214		i2c1: i2c@58781000 {
215			compatible = "socionext,uniphier-fi2c";
216			status = "disabled";
217			reg = <0x58781000 0x80>;
218			#address-cells = <1>;
219			#size-cells = <0>;
220			interrupts = <0 42 4>;
221			pinctrl-names = "default";
222			pinctrl-0 = <&pinctrl_i2c1>;
223			clocks = <&peri_clk 5>;
224			resets = <&peri_rst 5>;
225			clock-frequency = <100000>;
226		};
227
228		i2c2: i2c@58782000 {
229			compatible = "socionext,uniphier-fi2c";
230			reg = <0x58782000 0x80>;
231			#address-cells = <1>;
232			#size-cells = <0>;
233			interrupts = <0 43 4>;
234			clocks = <&peri_clk 6>;
235			resets = <&peri_rst 6>;
236			clock-frequency = <400000>;
237		};
238
239		i2c3: i2c@58783000 {
240			compatible = "socionext,uniphier-fi2c";
241			status = "disabled";
242			reg = <0x58783000 0x80>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			interrupts = <0 44 4>;
246			pinctrl-names = "default";
247			pinctrl-0 = <&pinctrl_i2c3>;
248			clocks = <&peri_clk 7>;
249			resets = <&peri_rst 7>;
250			clock-frequency = <100000>;
251		};
252
253		i2c4: i2c@58784000 {
254			compatible = "socionext,uniphier-fi2c";
255			status = "disabled";
256			reg = <0x58784000 0x80>;
257			#address-cells = <1>;
258			#size-cells = <0>;
259			interrupts = <0 45 4>;
260			pinctrl-names = "default";
261			pinctrl-0 = <&pinctrl_i2c4>;
262			clocks = <&peri_clk 8>;
263			resets = <&peri_rst 8>;
264			clock-frequency = <100000>;
265		};
266
267		i2c5: i2c@58785000 {
268			compatible = "socionext,uniphier-fi2c";
269			reg = <0x58785000 0x80>;
270			#address-cells = <1>;
271			#size-cells = <0>;
272			interrupts = <0 25 4>;
273			clocks = <&peri_clk 9>;
274			resets = <&peri_rst 9>;
275			clock-frequency = <400000>;
276		};
277
278		system_bus: system-bus@58c00000 {
279			compatible = "socionext,uniphier-system-bus";
280			status = "disabled";
281			reg = <0x58c00000 0x400>;
282			#address-cells = <2>;
283			#size-cells = <1>;
284			pinctrl-names = "default";
285			pinctrl-0 = <&pinctrl_system_bus>;
286		};
287
288		smpctrl@59801000 {
289			compatible = "socionext,uniphier-smpctrl";
290			reg = <0x59801000 0x400>;
291		};
292
293		sdctrl@59810000 {
294			compatible = "socionext,uniphier-ld11-sdctrl",
295				     "simple-mfd", "syscon";
296			reg = <0x59810000 0x400>;
297
298			sd_rst: reset {
299				compatible = "socionext,uniphier-ld11-sd-reset";
300				#reset-cells = <1>;
301			};
302		};
303
304		perictrl@59820000 {
305			compatible = "socionext,uniphier-ld11-perictrl",
306				     "simple-mfd", "syscon";
307			reg = <0x59820000 0x200>;
308
309			peri_clk: clock {
310				compatible = "socionext,uniphier-ld11-peri-clock";
311				#clock-cells = <1>;
312			};
313
314			peri_rst: reset {
315				compatible = "socionext,uniphier-ld11-peri-reset";
316				#reset-cells = <1>;
317			};
318		};
319
320		emmc: sdhc@5a000000 {
321			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
322			reg = <0x5a000000 0x400>;
323			interrupts = <0 78 4>;
324			pinctrl-names = "default";
325			pinctrl-0 = <&pinctrl_emmc>;
326			clocks = <&sys_clk 4>;
327			resets = <&sys_rst 4>;
328			bus-width = <8>;
329			mmc-ddr-1_8v;
330			mmc-hs200-1_8v;
331			mmc-pwrseq = <&emmc_pwrseq>;
332			cdns,phy-input-delay-legacy = <4>;
333			cdns,phy-input-delay-mmc-highspeed = <2>;
334			cdns,phy-input-delay-mmc-ddr = <3>;
335			cdns,phy-dll-delay-sdclk = <21>;
336			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
337		};
338
339		usb0: usb@5a800100 {
340			compatible = "socionext,uniphier-ehci", "generic-ehci";
341			status = "disabled";
342			reg = <0x5a800100 0x100>;
343			interrupts = <0 243 4>;
344			pinctrl-names = "default";
345			pinctrl-0 = <&pinctrl_usb0>;
346			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
347				 <&mio_clk 12>;
348			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
349				 <&mio_rst 12>;
350		};
351
352		usb1: usb@5a810100 {
353			compatible = "socionext,uniphier-ehci", "generic-ehci";
354			status = "disabled";
355			reg = <0x5a810100 0x100>;
356			interrupts = <0 244 4>;
357			pinctrl-names = "default";
358			pinctrl-0 = <&pinctrl_usb1>;
359			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
360				 <&mio_clk 13>;
361			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
362				 <&mio_rst 13>;
363		};
364
365		usb2: usb@5a820100 {
366			compatible = "socionext,uniphier-ehci", "generic-ehci";
367			status = "disabled";
368			reg = <0x5a820100 0x100>;
369			interrupts = <0 245 4>;
370			pinctrl-names = "default";
371			pinctrl-0 = <&pinctrl_usb2>;
372			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
373				 <&mio_clk 14>;
374			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
375				 <&mio_rst 14>;
376		};
377
378		mioctrl@5b3e0000 {
379			compatible = "socionext,uniphier-ld11-mioctrl",
380				     "simple-mfd", "syscon";
381			reg = <0x5b3e0000 0x800>;
382
383			mio_clk: clock {
384				compatible = "socionext,uniphier-ld11-mio-clock";
385				#clock-cells = <1>;
386			};
387
388			mio_rst: reset {
389				compatible = "socionext,uniphier-ld11-mio-reset";
390				#reset-cells = <1>;
391				resets = <&sys_rst 7>;
392			};
393		};
394
395		soc-glue@5f800000 {
396			compatible = "socionext,uniphier-ld11-soc-glue",
397				     "simple-mfd", "syscon";
398			reg = <0x5f800000 0x2000>;
399
400			pinctrl: pinctrl {
401				compatible = "socionext,uniphier-ld11-pinctrl";
402			};
403		};
404
405		soc-glue@5f900000 {
406			compatible = "socionext,uniphier-ld11-soc-glue-debug",
407				     "simple-mfd";
408			#address-cells = <1>;
409			#size-cells = <1>;
410			ranges = <0 0x5f900000 0x2000>;
411
412			efuse@100 {
413				compatible = "socionext,uniphier-efuse";
414				reg = <0x100 0x28>;
415			};
416
417			efuse@200 {
418				compatible = "socionext,uniphier-efuse";
419				reg = <0x200 0x68>;
420			};
421		};
422
423		aidet: aidet@5fc20000 {
424			compatible = "socionext,uniphier-ld11-aidet";
425			reg = <0x5fc20000 0x200>;
426			interrupt-controller;
427			#interrupt-cells = <2>;
428		};
429
430		gic: interrupt-controller@5fe00000 {
431			compatible = "arm,gic-v3";
432			reg = <0x5fe00000 0x10000>,	/* GICD */
433			      <0x5fe40000 0x80000>;	/* GICR */
434			interrupt-controller;
435			#interrupt-cells = <3>;
436			interrupts = <1 9 4>;
437		};
438
439		sysctrl@61840000 {
440			compatible = "socionext,uniphier-ld11-sysctrl",
441				     "simple-mfd", "syscon";
442			reg = <0x61840000 0x10000>;
443
444			sys_clk: clock {
445				compatible = "socionext,uniphier-ld11-clock";
446				#clock-cells = <1>;
447			};
448
449			sys_rst: reset {
450				compatible = "socionext,uniphier-ld11-reset";
451				#reset-cells = <1>;
452			};
453
454			watchdog {
455				compatible = "socionext,uniphier-wdt";
456			};
457		};
458
459		nand: nand@68000000 {
460			compatible = "socionext,uniphier-denali-nand-v5b";
461			status = "disabled";
462			reg-names = "nand_data", "denali_reg";
463			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
464			interrupts = <0 65 4>;
465			pinctrl-names = "default";
466			pinctrl-0 = <&pinctrl_nand>;
467			clocks = <&sys_clk 2>;
468			resets = <&sys_rst 2>;
469		};
470	};
471};
472
473#include "uniphier-pinctrl.dtsi"
474