1/*
2 * Device Tree Source for UniPhier LD11 SoC
3 *
4 * Copyright (C) 2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/gpio/uniphier-gpio.h>
12
13/memreserve/ 0x80000000 0x02000000;
14
15/ {
16	compatible = "socionext,uniphier-ld11";
17	#address-cells = <2>;
18	#size-cells = <2>;
19	interrupt-parent = <&gic>;
20
21	cpus {
22		#address-cells = <2>;
23		#size-cells = <0>;
24
25		cpu-map {
26			cluster0 {
27				core0 {
28					cpu = <&cpu0>;
29				};
30				core1 {
31					cpu = <&cpu1>;
32				};
33			};
34		};
35
36		cpu0: cpu@0 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a53", "arm,armv8";
39			reg = <0 0x000>;
40			clocks = <&sys_clk 33>;
41			enable-method = "psci";
42			operating-points-v2 = <&cluster0_opp>;
43		};
44
45		cpu1: cpu@1 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a53", "arm,armv8";
48			reg = <0 0x001>;
49			clocks = <&sys_clk 33>;
50			enable-method = "psci";
51			operating-points-v2 = <&cluster0_opp>;
52		};
53	};
54
55	cluster0_opp: opp-table {
56		compatible = "operating-points-v2";
57		opp-shared;
58
59		opp-245000000 {
60			opp-hz = /bits/ 64 <245000000>;
61			clock-latency-ns = <300>;
62		};
63		opp-250000000 {
64			opp-hz = /bits/ 64 <250000000>;
65			clock-latency-ns = <300>;
66		};
67		opp-490000000 {
68			opp-hz = /bits/ 64 <490000000>;
69			clock-latency-ns = <300>;
70		};
71		opp-500000000 {
72			opp-hz = /bits/ 64 <500000000>;
73			clock-latency-ns = <300>;
74		};
75		opp-653334000 {
76			opp-hz = /bits/ 64 <653334000>;
77			clock-latency-ns = <300>;
78		};
79		opp-666667000 {
80			opp-hz = /bits/ 64 <666667000>;
81			clock-latency-ns = <300>;
82		};
83		opp-980000000 {
84			opp-hz = /bits/ 64 <980000000>;
85			clock-latency-ns = <300>;
86		};
87	};
88
89	psci {
90		compatible = "arm,psci-1.0";
91		method = "smc";
92	};
93
94	clocks {
95		refclk: ref {
96			compatible = "fixed-clock";
97			#clock-cells = <0>;
98			clock-frequency = <25000000>;
99		};
100	};
101
102	emmc_pwrseq: emmc-pwrseq {
103		compatible = "mmc-pwrseq-emmc";
104		reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
105	};
106
107	timer {
108		compatible = "arm,armv8-timer";
109		interrupts = <1 13 4>,
110			     <1 14 4>,
111			     <1 11 4>,
112			     <1 10 4>;
113	};
114
115	soc@0 {
116		compatible = "simple-bus";
117		#address-cells = <1>;
118		#size-cells = <1>;
119		ranges = <0 0 0 0xffffffff>;
120
121		serial0: serial@54006800 {
122			compatible = "socionext,uniphier-uart";
123			status = "disabled";
124			reg = <0x54006800 0x40>;
125			interrupts = <0 33 4>;
126			pinctrl-names = "default";
127			pinctrl-0 = <&pinctrl_uart0>;
128			clocks = <&peri_clk 0>;
129			resets = <&peri_rst 0>;
130		};
131
132		serial1: serial@54006900 {
133			compatible = "socionext,uniphier-uart";
134			status = "disabled";
135			reg = <0x54006900 0x40>;
136			interrupts = <0 35 4>;
137			pinctrl-names = "default";
138			pinctrl-0 = <&pinctrl_uart1>;
139			clocks = <&peri_clk 1>;
140			resets = <&peri_rst 1>;
141		};
142
143		serial2: serial@54006a00 {
144			compatible = "socionext,uniphier-uart";
145			status = "disabled";
146			reg = <0x54006a00 0x40>;
147			interrupts = <0 37 4>;
148			pinctrl-names = "default";
149			pinctrl-0 = <&pinctrl_uart2>;
150			clocks = <&peri_clk 2>;
151			resets = <&peri_rst 2>;
152		};
153
154		serial3: serial@54006b00 {
155			compatible = "socionext,uniphier-uart";
156			status = "disabled";
157			reg = <0x54006b00 0x40>;
158			interrupts = <0 177 4>;
159			pinctrl-names = "default";
160			pinctrl-0 = <&pinctrl_uart3>;
161			clocks = <&peri_clk 3>;
162			resets = <&peri_rst 3>;
163		};
164
165		gpio: gpio@55000000 {
166			compatible = "socionext,uniphier-gpio";
167			reg = <0x55000000 0x200>;
168			interrupt-parent = <&aidet>;
169			interrupt-controller;
170			#interrupt-cells = <2>;
171			gpio-controller;
172			#gpio-cells = <2>;
173			gpio-ranges = <&pinctrl 0 0 0>,
174				      <&pinctrl 43 0 0>,
175				      <&pinctrl 51 0 0>,
176				      <&pinctrl 96 0 0>,
177				      <&pinctrl 160 0 0>,
178				      <&pinctrl 184 0 0>;
179			gpio-ranges-group-names = "gpio_range0",
180						  "gpio_range1",
181						  "gpio_range2",
182						  "gpio_range3",
183						  "gpio_range4",
184						  "gpio_range5";
185			ngpios = <200>;
186			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
187						     <21 217 3>;
188		};
189
190		adamv@57920000 {
191			compatible = "socionext,uniphier-ld11-adamv",
192				     "simple-mfd", "syscon";
193			reg = <0x57920000 0x1000>;
194
195			adamv_rst: reset {
196				compatible = "socionext,uniphier-ld11-adamv-reset";
197				#reset-cells = <1>;
198			};
199		};
200
201		i2c0: i2c@58780000 {
202			compatible = "socionext,uniphier-fi2c";
203			status = "disabled";
204			reg = <0x58780000 0x80>;
205			#address-cells = <1>;
206			#size-cells = <0>;
207			interrupts = <0 41 4>;
208			pinctrl-names = "default";
209			pinctrl-0 = <&pinctrl_i2c0>;
210			clocks = <&peri_clk 4>;
211			resets = <&peri_rst 4>;
212			clock-frequency = <100000>;
213		};
214
215		i2c1: i2c@58781000 {
216			compatible = "socionext,uniphier-fi2c";
217			status = "disabled";
218			reg = <0x58781000 0x80>;
219			#address-cells = <1>;
220			#size-cells = <0>;
221			interrupts = <0 42 4>;
222			pinctrl-names = "default";
223			pinctrl-0 = <&pinctrl_i2c1>;
224			clocks = <&peri_clk 5>;
225			resets = <&peri_rst 5>;
226			clock-frequency = <100000>;
227		};
228
229		i2c2: i2c@58782000 {
230			compatible = "socionext,uniphier-fi2c";
231			reg = <0x58782000 0x80>;
232			#address-cells = <1>;
233			#size-cells = <0>;
234			interrupts = <0 43 4>;
235			clocks = <&peri_clk 6>;
236			resets = <&peri_rst 6>;
237			clock-frequency = <400000>;
238		};
239
240		i2c3: i2c@58783000 {
241			compatible = "socionext,uniphier-fi2c";
242			status = "disabled";
243			reg = <0x58783000 0x80>;
244			#address-cells = <1>;
245			#size-cells = <0>;
246			interrupts = <0 44 4>;
247			pinctrl-names = "default";
248			pinctrl-0 = <&pinctrl_i2c3>;
249			clocks = <&peri_clk 7>;
250			resets = <&peri_rst 7>;
251			clock-frequency = <100000>;
252		};
253
254		i2c4: i2c@58784000 {
255			compatible = "socionext,uniphier-fi2c";
256			status = "disabled";
257			reg = <0x58784000 0x80>;
258			#address-cells = <1>;
259			#size-cells = <0>;
260			interrupts = <0 45 4>;
261			pinctrl-names = "default";
262			pinctrl-0 = <&pinctrl_i2c4>;
263			clocks = <&peri_clk 8>;
264			resets = <&peri_rst 8>;
265			clock-frequency = <100000>;
266		};
267
268		i2c5: i2c@58785000 {
269			compatible = "socionext,uniphier-fi2c";
270			reg = <0x58785000 0x80>;
271			#address-cells = <1>;
272			#size-cells = <0>;
273			interrupts = <0 25 4>;
274			clocks = <&peri_clk 9>;
275			resets = <&peri_rst 9>;
276			clock-frequency = <400000>;
277		};
278
279		system_bus: system-bus@58c00000 {
280			compatible = "socionext,uniphier-system-bus";
281			status = "disabled";
282			reg = <0x58c00000 0x400>;
283			#address-cells = <2>;
284			#size-cells = <1>;
285			pinctrl-names = "default";
286			pinctrl-0 = <&pinctrl_system_bus>;
287		};
288
289		smpctrl@59801000 {
290			compatible = "socionext,uniphier-smpctrl";
291			reg = <0x59801000 0x400>;
292		};
293
294		sdctrl@59810000 {
295			compatible = "socionext,uniphier-ld11-sdctrl",
296				     "simple-mfd", "syscon";
297			reg = <0x59810000 0x400>;
298
299			sd_rst: reset {
300				compatible = "socionext,uniphier-ld11-sd-reset";
301				#reset-cells = <1>;
302			};
303		};
304
305		perictrl@59820000 {
306			compatible = "socionext,uniphier-ld11-perictrl",
307				     "simple-mfd", "syscon";
308			reg = <0x59820000 0x200>;
309
310			peri_clk: clock {
311				compatible = "socionext,uniphier-ld11-peri-clock";
312				#clock-cells = <1>;
313			};
314
315			peri_rst: reset {
316				compatible = "socionext,uniphier-ld11-peri-reset";
317				#reset-cells = <1>;
318			};
319		};
320
321		emmc: sdhc@5a000000 {
322			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
323			reg = <0x5a000000 0x400>;
324			interrupts = <0 78 4>;
325			pinctrl-names = "default";
326			pinctrl-0 = <&pinctrl_emmc>;
327			clocks = <&sys_clk 4>;
328			resets = <&sys_rst 4>;
329			bus-width = <8>;
330			mmc-ddr-1_8v;
331			mmc-hs200-1_8v;
332			mmc-pwrseq = <&emmc_pwrseq>;
333			cdns,phy-input-delay-legacy = <4>;
334			cdns,phy-input-delay-mmc-highspeed = <2>;
335			cdns,phy-input-delay-mmc-ddr = <3>;
336			cdns,phy-dll-delay-sdclk = <21>;
337			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
338		};
339
340		usb0: usb@5a800100 {
341			compatible = "socionext,uniphier-ehci", "generic-ehci";
342			status = "disabled";
343			reg = <0x5a800100 0x100>;
344			interrupts = <0 243 4>;
345			pinctrl-names = "default";
346			pinctrl-0 = <&pinctrl_usb0>;
347			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
348				 <&mio_clk 12>;
349			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
350				 <&mio_rst 12>;
351			has-transaction-translator;
352		};
353
354		usb1: usb@5a810100 {
355			compatible = "socionext,uniphier-ehci", "generic-ehci";
356			status = "disabled";
357			reg = <0x5a810100 0x100>;
358			interrupts = <0 244 4>;
359			pinctrl-names = "default";
360			pinctrl-0 = <&pinctrl_usb1>;
361			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
362				 <&mio_clk 13>;
363			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
364				 <&mio_rst 13>;
365			has-transaction-translator;
366		};
367
368		usb2: usb@5a820100 {
369			compatible = "socionext,uniphier-ehci", "generic-ehci";
370			status = "disabled";
371			reg = <0x5a820100 0x100>;
372			interrupts = <0 245 4>;
373			pinctrl-names = "default";
374			pinctrl-0 = <&pinctrl_usb2>;
375			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
376				 <&mio_clk 14>;
377			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
378				 <&mio_rst 14>;
379			has-transaction-translator;
380		};
381
382		mioctrl@5b3e0000 {
383			compatible = "socionext,uniphier-ld11-mioctrl",
384				     "simple-mfd", "syscon";
385			reg = <0x5b3e0000 0x800>;
386
387			mio_clk: clock {
388				compatible = "socionext,uniphier-ld11-mio-clock";
389				#clock-cells = <1>;
390			};
391
392			mio_rst: reset {
393				compatible = "socionext,uniphier-ld11-mio-reset";
394				#reset-cells = <1>;
395				resets = <&sys_rst 7>;
396			};
397		};
398
399		soc-glue@5f800000 {
400			compatible = "socionext,uniphier-ld11-soc-glue",
401				     "simple-mfd", "syscon";
402			reg = <0x5f800000 0x2000>;
403
404			pinctrl: pinctrl {
405				compatible = "socionext,uniphier-ld11-pinctrl";
406			};
407		};
408
409		soc-glue@5f900000 {
410			compatible = "socionext,uniphier-ld11-soc-glue-debug",
411				     "simple-mfd";
412			#address-cells = <1>;
413			#size-cells = <1>;
414			ranges = <0 0x5f900000 0x2000>;
415
416			efuse@100 {
417				compatible = "socionext,uniphier-efuse";
418				reg = <0x100 0x28>;
419			};
420
421			efuse@200 {
422				compatible = "socionext,uniphier-efuse";
423				reg = <0x200 0x68>;
424			};
425		};
426
427		aidet: aidet@5fc20000 {
428			compatible = "socionext,uniphier-ld11-aidet";
429			reg = <0x5fc20000 0x200>;
430			interrupt-controller;
431			#interrupt-cells = <2>;
432		};
433
434		gic: interrupt-controller@5fe00000 {
435			compatible = "arm,gic-v3";
436			reg = <0x5fe00000 0x10000>,	/* GICD */
437			      <0x5fe40000 0x80000>;	/* GICR */
438			interrupt-controller;
439			#interrupt-cells = <3>;
440			interrupts = <1 9 4>;
441		};
442
443		sysctrl@61840000 {
444			compatible = "socionext,uniphier-ld11-sysctrl",
445				     "simple-mfd", "syscon";
446			reg = <0x61840000 0x10000>;
447
448			sys_clk: clock {
449				compatible = "socionext,uniphier-ld11-clock";
450				#clock-cells = <1>;
451			};
452
453			sys_rst: reset {
454				compatible = "socionext,uniphier-ld11-reset";
455				#reset-cells = <1>;
456			};
457
458			watchdog {
459				compatible = "socionext,uniphier-wdt";
460			};
461		};
462
463		nand: nand@68000000 {
464			compatible = "socionext,uniphier-denali-nand-v5b";
465			status = "disabled";
466			reg-names = "nand_data", "denali_reg";
467			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
468			interrupts = <0 65 4>;
469			pinctrl-names = "default";
470			pinctrl-0 = <&pinctrl_nand>;
471			clocks = <&sys_clk 2>;
472			resets = <&sys_rst 2>;
473		};
474	};
475};
476
477#include "uniphier-pinctrl.dtsi"
478