1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD11 SoC 4// 5// Copyright (C) 2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10 11/memreserve/ 0x80000000 0x02000000; 12 13/ { 14 compatible = "socionext,uniphier-ld11"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 }; 32 }; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53", "arm,armv8"; 37 reg = <0 0x000>; 38 clocks = <&sys_clk 33>; 39 enable-method = "psci"; 40 operating-points-v2 = <&cluster0_opp>; 41 }; 42 43 cpu1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53", "arm,armv8"; 46 reg = <0 0x001>; 47 clocks = <&sys_clk 33>; 48 enable-method = "psci"; 49 operating-points-v2 = <&cluster0_opp>; 50 }; 51 }; 52 53 cluster0_opp: opp-table { 54 compatible = "operating-points-v2"; 55 opp-shared; 56 57 opp-245000000 { 58 opp-hz = /bits/ 64 <245000000>; 59 clock-latency-ns = <300>; 60 }; 61 opp-250000000 { 62 opp-hz = /bits/ 64 <250000000>; 63 clock-latency-ns = <300>; 64 }; 65 opp-490000000 { 66 opp-hz = /bits/ 64 <490000000>; 67 clock-latency-ns = <300>; 68 }; 69 opp-500000000 { 70 opp-hz = /bits/ 64 <500000000>; 71 clock-latency-ns = <300>; 72 }; 73 opp-653334000 { 74 opp-hz = /bits/ 64 <653334000>; 75 clock-latency-ns = <300>; 76 }; 77 opp-666667000 { 78 opp-hz = /bits/ 64 <666667000>; 79 clock-latency-ns = <300>; 80 }; 81 opp-980000000 { 82 opp-hz = /bits/ 64 <980000000>; 83 clock-latency-ns = <300>; 84 }; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0"; 89 method = "smc"; 90 }; 91 92 clocks { 93 refclk: ref { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <25000000>; 97 }; 98 }; 99 100 emmc_pwrseq: emmc-pwrseq { 101 compatible = "mmc-pwrseq-emmc"; 102 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupts = <1 13 4>, 108 <1 14 4>, 109 <1 11 4>, 110 <1 10 4>; 111 }; 112 113 soc@0 { 114 compatible = "simple-bus"; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges = <0 0 0 0xffffffff>; 118 119 serial0: serial@54006800 { 120 compatible = "socionext,uniphier-uart"; 121 status = "disabled"; 122 reg = <0x54006800 0x40>; 123 interrupts = <0 33 4>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_uart0>; 126 clocks = <&peri_clk 0>; 127 resets = <&peri_rst 0>; 128 }; 129 130 serial1: serial@54006900 { 131 compatible = "socionext,uniphier-uart"; 132 status = "disabled"; 133 reg = <0x54006900 0x40>; 134 interrupts = <0 35 4>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_uart1>; 137 clocks = <&peri_clk 1>; 138 resets = <&peri_rst 1>; 139 }; 140 141 serial2: serial@54006a00 { 142 compatible = "socionext,uniphier-uart"; 143 status = "disabled"; 144 reg = <0x54006a00 0x40>; 145 interrupts = <0 37 4>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_uart2>; 148 clocks = <&peri_clk 2>; 149 resets = <&peri_rst 2>; 150 }; 151 152 serial3: serial@54006b00 { 153 compatible = "socionext,uniphier-uart"; 154 status = "disabled"; 155 reg = <0x54006b00 0x40>; 156 interrupts = <0 177 4>; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_uart3>; 159 clocks = <&peri_clk 3>; 160 resets = <&peri_rst 3>; 161 }; 162 163 gpio: gpio@55000000 { 164 compatible = "socionext,uniphier-gpio"; 165 reg = <0x55000000 0x200>; 166 interrupt-parent = <&aidet>; 167 interrupt-controller; 168 #interrupt-cells = <2>; 169 gpio-controller; 170 #gpio-cells = <2>; 171 gpio-ranges = <&pinctrl 0 0 0>, 172 <&pinctrl 43 0 0>, 173 <&pinctrl 51 0 0>, 174 <&pinctrl 96 0 0>, 175 <&pinctrl 160 0 0>, 176 <&pinctrl 184 0 0>; 177 gpio-ranges-group-names = "gpio_range0", 178 "gpio_range1", 179 "gpio_range2", 180 "gpio_range3", 181 "gpio_range4", 182 "gpio_range5"; 183 ngpios = <200>; 184 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 185 <21 217 3>; 186 }; 187 188 audio@56000000 { 189 compatible = "socionext,uniphier-ld11-aio"; 190 reg = <0x56000000 0x80000>; 191 interrupts = <0 144 4>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_aout1>, 194 <&pinctrl_aoutiec1>; 195 clock-names = "aio"; 196 clocks = <&sys_clk 40>; 197 reset-names = "aio"; 198 resets = <&sys_rst 40>; 199 #sound-dai-cells = <1>; 200 201 i2s_port0: port@0 { 202 i2s_hdmi: endpoint { 203 }; 204 }; 205 206 i2s_port1: port@1 { 207 i2s_pcmin2: endpoint { 208 }; 209 }; 210 211 i2s_port2: port@2 { 212 i2s_line: endpoint { 213 dai-format = "i2s"; 214 remote-endpoint = <&evea_line>; 215 }; 216 }; 217 218 i2s_port3: port@3 { 219 i2s_hpcmout1: endpoint { 220 }; 221 }; 222 223 i2s_port4: port@4 { 224 i2s_hp: endpoint { 225 dai-format = "i2s"; 226 remote-endpoint = <&evea_hp>; 227 }; 228 }; 229 230 spdif_port0: port@5 { 231 spdif_hiecout1: endpoint { 232 }; 233 }; 234 235 src_port0: port@6 { 236 i2s_epcmout2: endpoint { 237 }; 238 }; 239 240 src_port1: port@7 { 241 i2s_epcmout3: endpoint { 242 }; 243 }; 244 245 comp_spdif_port0: port@8 { 246 comp_spdif_hiecout1: endpoint { 247 }; 248 }; 249 }; 250 251 codec@57900000 { 252 compatible = "socionext,uniphier-evea"; 253 reg = <0x57900000 0x1000>; 254 clock-names = "evea", "exiv"; 255 clocks = <&sys_clk 41>, <&sys_clk 42>; 256 reset-names = "evea", "exiv", "adamv"; 257 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 258 #sound-dai-cells = <1>; 259 260 port@0 { 261 evea_line: endpoint { 262 remote-endpoint = <&i2s_line>; 263 }; 264 }; 265 266 port@1 { 267 evea_hp: endpoint { 268 remote-endpoint = <&i2s_hp>; 269 }; 270 }; 271 }; 272 273 adamv@57920000 { 274 compatible = "socionext,uniphier-ld11-adamv", 275 "simple-mfd", "syscon"; 276 reg = <0x57920000 0x1000>; 277 278 adamv_rst: reset { 279 compatible = "socionext,uniphier-ld11-adamv-reset"; 280 #reset-cells = <1>; 281 }; 282 }; 283 284 i2c0: i2c@58780000 { 285 compatible = "socionext,uniphier-fi2c"; 286 status = "disabled"; 287 reg = <0x58780000 0x80>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 interrupts = <0 41 4>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_i2c0>; 293 clocks = <&peri_clk 4>; 294 resets = <&peri_rst 4>; 295 clock-frequency = <100000>; 296 }; 297 298 i2c1: i2c@58781000 { 299 compatible = "socionext,uniphier-fi2c"; 300 status = "disabled"; 301 reg = <0x58781000 0x80>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 interrupts = <0 42 4>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_i2c1>; 307 clocks = <&peri_clk 5>; 308 resets = <&peri_rst 5>; 309 clock-frequency = <100000>; 310 }; 311 312 i2c2: i2c@58782000 { 313 compatible = "socionext,uniphier-fi2c"; 314 reg = <0x58782000 0x80>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 interrupts = <0 43 4>; 318 clocks = <&peri_clk 6>; 319 resets = <&peri_rst 6>; 320 clock-frequency = <400000>; 321 }; 322 323 i2c3: i2c@58783000 { 324 compatible = "socionext,uniphier-fi2c"; 325 status = "disabled"; 326 reg = <0x58783000 0x80>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 interrupts = <0 44 4>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_i2c3>; 332 clocks = <&peri_clk 7>; 333 resets = <&peri_rst 7>; 334 clock-frequency = <100000>; 335 }; 336 337 i2c4: i2c@58784000 { 338 compatible = "socionext,uniphier-fi2c"; 339 status = "disabled"; 340 reg = <0x58784000 0x80>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 interrupts = <0 45 4>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_i2c4>; 346 clocks = <&peri_clk 8>; 347 resets = <&peri_rst 8>; 348 clock-frequency = <100000>; 349 }; 350 351 i2c5: i2c@58785000 { 352 compatible = "socionext,uniphier-fi2c"; 353 reg = <0x58785000 0x80>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 interrupts = <0 25 4>; 357 clocks = <&peri_clk 9>; 358 resets = <&peri_rst 9>; 359 clock-frequency = <400000>; 360 }; 361 362 system_bus: system-bus@58c00000 { 363 compatible = "socionext,uniphier-system-bus"; 364 status = "disabled"; 365 reg = <0x58c00000 0x400>; 366 #address-cells = <2>; 367 #size-cells = <1>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_system_bus>; 370 }; 371 372 smpctrl@59801000 { 373 compatible = "socionext,uniphier-smpctrl"; 374 reg = <0x59801000 0x400>; 375 }; 376 377 sdctrl@59810000 { 378 compatible = "socionext,uniphier-ld11-sdctrl", 379 "simple-mfd", "syscon"; 380 reg = <0x59810000 0x400>; 381 382 sd_rst: reset { 383 compatible = "socionext,uniphier-ld11-sd-reset"; 384 #reset-cells = <1>; 385 }; 386 }; 387 388 perictrl@59820000 { 389 compatible = "socionext,uniphier-ld11-perictrl", 390 "simple-mfd", "syscon"; 391 reg = <0x59820000 0x200>; 392 393 peri_clk: clock { 394 compatible = "socionext,uniphier-ld11-peri-clock"; 395 #clock-cells = <1>; 396 }; 397 398 peri_rst: reset { 399 compatible = "socionext,uniphier-ld11-peri-reset"; 400 #reset-cells = <1>; 401 }; 402 }; 403 404 emmc: sdhc@5a000000 { 405 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 406 reg = <0x5a000000 0x400>; 407 interrupts = <0 78 4>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_emmc>; 410 clocks = <&sys_clk 4>; 411 resets = <&sys_rst 4>; 412 bus-width = <8>; 413 mmc-ddr-1_8v; 414 mmc-hs200-1_8v; 415 mmc-pwrseq = <&emmc_pwrseq>; 416 cdns,phy-input-delay-legacy = <4>; 417 cdns,phy-input-delay-mmc-highspeed = <2>; 418 cdns,phy-input-delay-mmc-ddr = <3>; 419 cdns,phy-dll-delay-sdclk = <21>; 420 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 421 }; 422 423 usb0: usb@5a800100 { 424 compatible = "socionext,uniphier-ehci", "generic-ehci"; 425 status = "disabled"; 426 reg = <0x5a800100 0x100>; 427 interrupts = <0 243 4>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&pinctrl_usb0>; 430 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 431 <&mio_clk 12>; 432 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 433 <&mio_rst 12>; 434 has-transaction-translator; 435 }; 436 437 usb1: usb@5a810100 { 438 compatible = "socionext,uniphier-ehci", "generic-ehci"; 439 status = "disabled"; 440 reg = <0x5a810100 0x100>; 441 interrupts = <0 244 4>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&pinctrl_usb1>; 444 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 445 <&mio_clk 13>; 446 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 447 <&mio_rst 13>; 448 has-transaction-translator; 449 }; 450 451 usb2: usb@5a820100 { 452 compatible = "socionext,uniphier-ehci", "generic-ehci"; 453 status = "disabled"; 454 reg = <0x5a820100 0x100>; 455 interrupts = <0 245 4>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_usb2>; 458 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 459 <&mio_clk 14>; 460 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 461 <&mio_rst 14>; 462 has-transaction-translator; 463 }; 464 465 mioctrl@5b3e0000 { 466 compatible = "socionext,uniphier-ld11-mioctrl", 467 "simple-mfd", "syscon"; 468 reg = <0x5b3e0000 0x800>; 469 470 mio_clk: clock { 471 compatible = "socionext,uniphier-ld11-mio-clock"; 472 #clock-cells = <1>; 473 }; 474 475 mio_rst: reset { 476 compatible = "socionext,uniphier-ld11-mio-reset"; 477 #reset-cells = <1>; 478 resets = <&sys_rst 7>; 479 }; 480 }; 481 482 soc-glue@5f800000 { 483 compatible = "socionext,uniphier-ld11-soc-glue", 484 "simple-mfd", "syscon"; 485 reg = <0x5f800000 0x2000>; 486 487 pinctrl: pinctrl { 488 compatible = "socionext,uniphier-ld11-pinctrl"; 489 }; 490 }; 491 492 soc-glue@5f900000 { 493 compatible = "socionext,uniphier-ld11-soc-glue-debug", 494 "simple-mfd"; 495 #address-cells = <1>; 496 #size-cells = <1>; 497 ranges = <0 0x5f900000 0x2000>; 498 499 efuse@100 { 500 compatible = "socionext,uniphier-efuse"; 501 reg = <0x100 0x28>; 502 }; 503 504 efuse@200 { 505 compatible = "socionext,uniphier-efuse"; 506 reg = <0x200 0x68>; 507 }; 508 }; 509 510 aidet: aidet@5fc20000 { 511 compatible = "socionext,uniphier-ld11-aidet"; 512 reg = <0x5fc20000 0x200>; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 }; 516 517 gic: interrupt-controller@5fe00000 { 518 compatible = "arm,gic-v3"; 519 reg = <0x5fe00000 0x10000>, /* GICD */ 520 <0x5fe40000 0x80000>; /* GICR */ 521 interrupt-controller; 522 #interrupt-cells = <3>; 523 interrupts = <1 9 4>; 524 }; 525 526 sysctrl@61840000 { 527 compatible = "socionext,uniphier-ld11-sysctrl", 528 "simple-mfd", "syscon"; 529 reg = <0x61840000 0x10000>; 530 531 sys_clk: clock { 532 compatible = "socionext,uniphier-ld11-clock"; 533 #clock-cells = <1>; 534 }; 535 536 sys_rst: reset { 537 compatible = "socionext,uniphier-ld11-reset"; 538 #reset-cells = <1>; 539 }; 540 541 watchdog { 542 compatible = "socionext,uniphier-wdt"; 543 }; 544 }; 545 546 eth: ethernet@65000000 { 547 compatible = "socionext,uniphier-ld11-ave4"; 548 status = "disabled"; 549 reg = <0x65000000 0x8500>; 550 interrupts = <0 66 4>; 551 clocks = <&sys_clk 6>; 552 resets = <&sys_rst 6>; 553 phy-mode = "rmii"; 554 local-mac-address = [00 00 00 00 00 00]; 555 556 mdio: mdio { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 }; 560 }; 561 562 nand: nand@68000000 { 563 compatible = "socionext,uniphier-denali-nand-v5b"; 564 status = "disabled"; 565 reg-names = "nand_data", "denali_reg"; 566 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 567 interrupts = <0 65 4>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pinctrl_nand>; 570 clocks = <&sys_clk 2>; 571 resets = <&sys_rst 2>; 572 }; 573 }; 574}; 575 576#include "uniphier-pinctrl.dtsi" 577 578&pinctrl_aoutiec1 { 579 drive-strength = <4>; /* default: 4mA */ 580 581 ao1arc { 582 pins = "AO1ARC"; 583 drive-strength = <8>; /* 8mA */ 584 }; 585}; 586