1270e0c3eSMasahiro Yamada/* 2270e0c3eSMasahiro Yamada * Device Tree Source for UniPhier LD11 SoC 3270e0c3eSMasahiro Yamada * 4270e0c3eSMasahiro Yamada * Copyright (C) 2016 Socionext Inc. 5270e0c3eSMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6270e0c3eSMasahiro Yamada * 712301cffSMasahiro Yamada * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8270e0c3eSMasahiro Yamada */ 9270e0c3eSMasahiro Yamada 10b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 118311ca57SMasahiro Yamada#include <dt-bindings/gpio/uniphier-gpio.h> 12b6e5ec20SMasahiro Yamada 1379d4be39SMasahiro Yamada/memreserve/ 0x80000000 0x02000000; 14270e0c3eSMasahiro Yamada 15270e0c3eSMasahiro Yamada/ { 16270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11"; 17270e0c3eSMasahiro Yamada #address-cells = <2>; 18270e0c3eSMasahiro Yamada #size-cells = <2>; 19270e0c3eSMasahiro Yamada interrupt-parent = <&gic>; 20270e0c3eSMasahiro Yamada 21270e0c3eSMasahiro Yamada cpus { 22270e0c3eSMasahiro Yamada #address-cells = <2>; 23270e0c3eSMasahiro Yamada #size-cells = <0>; 24270e0c3eSMasahiro Yamada 25270e0c3eSMasahiro Yamada cpu-map { 26270e0c3eSMasahiro Yamada cluster0 { 27270e0c3eSMasahiro Yamada core0 { 28270e0c3eSMasahiro Yamada cpu = <&cpu0>; 29270e0c3eSMasahiro Yamada }; 30270e0c3eSMasahiro Yamada core1 { 31270e0c3eSMasahiro Yamada cpu = <&cpu1>; 32270e0c3eSMasahiro Yamada }; 33270e0c3eSMasahiro Yamada }; 34270e0c3eSMasahiro Yamada }; 35270e0c3eSMasahiro Yamada 36270e0c3eSMasahiro Yamada cpu0: cpu@0 { 37270e0c3eSMasahiro Yamada device_type = "cpu"; 38270e0c3eSMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 39270e0c3eSMasahiro Yamada reg = <0 0x000>; 40bdb81836SMasahiro Yamada clocks = <&sys_clk 33>; 412f81137fSMasahiro Yamada enable-method = "psci"; 42bdb81836SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 43270e0c3eSMasahiro Yamada }; 44270e0c3eSMasahiro Yamada 45270e0c3eSMasahiro Yamada cpu1: cpu@1 { 46270e0c3eSMasahiro Yamada device_type = "cpu"; 47270e0c3eSMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 48270e0c3eSMasahiro Yamada reg = <0 0x001>; 49bdb81836SMasahiro Yamada clocks = <&sys_clk 33>; 502f81137fSMasahiro Yamada enable-method = "psci"; 51bdb81836SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 52bdb81836SMasahiro Yamada }; 53bdb81836SMasahiro Yamada }; 54bdb81836SMasahiro Yamada 559cd7d03fSMasahiro Yamada cluster0_opp: opp-table { 56bdb81836SMasahiro Yamada compatible = "operating-points-v2"; 57bdb81836SMasahiro Yamada opp-shared; 58bdb81836SMasahiro Yamada 593fc9a121SViresh Kumar opp-245000000 { 60bdb81836SMasahiro Yamada opp-hz = /bits/ 64 <245000000>; 61bdb81836SMasahiro Yamada clock-latency-ns = <300>; 62bdb81836SMasahiro Yamada }; 633fc9a121SViresh Kumar opp-250000000 { 64bdb81836SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 65bdb81836SMasahiro Yamada clock-latency-ns = <300>; 66bdb81836SMasahiro Yamada }; 673fc9a121SViresh Kumar opp-490000000 { 68bdb81836SMasahiro Yamada opp-hz = /bits/ 64 <490000000>; 69bdb81836SMasahiro Yamada clock-latency-ns = <300>; 70bdb81836SMasahiro Yamada }; 713fc9a121SViresh Kumar opp-500000000 { 72bdb81836SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 73bdb81836SMasahiro Yamada clock-latency-ns = <300>; 74bdb81836SMasahiro Yamada }; 753fc9a121SViresh Kumar opp-653334000 { 76bdb81836SMasahiro Yamada opp-hz = /bits/ 64 <653334000>; 77bdb81836SMasahiro Yamada clock-latency-ns = <300>; 78bdb81836SMasahiro Yamada }; 793fc9a121SViresh Kumar opp-666667000 { 80bdb81836SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 81bdb81836SMasahiro Yamada clock-latency-ns = <300>; 82bdb81836SMasahiro Yamada }; 833fc9a121SViresh Kumar opp-980000000 { 84bdb81836SMasahiro Yamada opp-hz = /bits/ 64 <980000000>; 85bdb81836SMasahiro Yamada clock-latency-ns = <300>; 86270e0c3eSMasahiro Yamada }; 87270e0c3eSMasahiro Yamada }; 88270e0c3eSMasahiro Yamada 892f81137fSMasahiro Yamada psci { 902f81137fSMasahiro Yamada compatible = "arm,psci-1.0"; 912f81137fSMasahiro Yamada method = "smc"; 922f81137fSMasahiro Yamada }; 932f81137fSMasahiro Yamada 94270e0c3eSMasahiro Yamada clocks { 95270e0c3eSMasahiro Yamada refclk: ref { 96270e0c3eSMasahiro Yamada compatible = "fixed-clock"; 97270e0c3eSMasahiro Yamada #clock-cells = <0>; 98270e0c3eSMasahiro Yamada clock-frequency = <25000000>; 99270e0c3eSMasahiro Yamada }; 100270e0c3eSMasahiro Yamada }; 101270e0c3eSMasahiro Yamada 102b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 103b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 1048311ca57SMasahiro Yamada reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 105b6e5ec20SMasahiro Yamada }; 106b6e5ec20SMasahiro Yamada 107270e0c3eSMasahiro Yamada timer { 108270e0c3eSMasahiro Yamada compatible = "arm,armv8-timer"; 109270e0c3eSMasahiro Yamada interrupts = <1 13 4>, 110270e0c3eSMasahiro Yamada <1 14 4>, 111270e0c3eSMasahiro Yamada <1 11 4>, 112270e0c3eSMasahiro Yamada <1 10 4>; 113270e0c3eSMasahiro Yamada }; 114270e0c3eSMasahiro Yamada 115b5027603SMasahiro Yamada soc@0 { 116270e0c3eSMasahiro Yamada compatible = "simple-bus"; 117270e0c3eSMasahiro Yamada #address-cells = <1>; 118270e0c3eSMasahiro Yamada #size-cells = <1>; 119270e0c3eSMasahiro Yamada ranges = <0 0 0 0xffffffff>; 120270e0c3eSMasahiro Yamada 121270e0c3eSMasahiro Yamada serial0: serial@54006800 { 122270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-uart"; 123270e0c3eSMasahiro Yamada status = "disabled"; 124270e0c3eSMasahiro Yamada reg = <0x54006800 0x40>; 125270e0c3eSMasahiro Yamada interrupts = <0 33 4>; 126270e0c3eSMasahiro Yamada pinctrl-names = "default"; 127270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 128270e0c3eSMasahiro Yamada clocks = <&peri_clk 0>; 12976c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 130270e0c3eSMasahiro Yamada }; 131270e0c3eSMasahiro Yamada 132270e0c3eSMasahiro Yamada serial1: serial@54006900 { 133270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-uart"; 134270e0c3eSMasahiro Yamada status = "disabled"; 135270e0c3eSMasahiro Yamada reg = <0x54006900 0x40>; 136270e0c3eSMasahiro Yamada interrupts = <0 35 4>; 137270e0c3eSMasahiro Yamada pinctrl-names = "default"; 138270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 139270e0c3eSMasahiro Yamada clocks = <&peri_clk 1>; 14076c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 141270e0c3eSMasahiro Yamada }; 142270e0c3eSMasahiro Yamada 143270e0c3eSMasahiro Yamada serial2: serial@54006a00 { 144270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-uart"; 145270e0c3eSMasahiro Yamada status = "disabled"; 146270e0c3eSMasahiro Yamada reg = <0x54006a00 0x40>; 147270e0c3eSMasahiro Yamada interrupts = <0 37 4>; 148270e0c3eSMasahiro Yamada pinctrl-names = "default"; 149270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 150270e0c3eSMasahiro Yamada clocks = <&peri_clk 2>; 15176c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 152270e0c3eSMasahiro Yamada }; 153270e0c3eSMasahiro Yamada 154270e0c3eSMasahiro Yamada serial3: serial@54006b00 { 155270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-uart"; 156270e0c3eSMasahiro Yamada status = "disabled"; 157270e0c3eSMasahiro Yamada reg = <0x54006b00 0x40>; 158270e0c3eSMasahiro Yamada interrupts = <0 177 4>; 159270e0c3eSMasahiro Yamada pinctrl-names = "default"; 160270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 161270e0c3eSMasahiro Yamada clocks = <&peri_clk 3>; 16276c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 163270e0c3eSMasahiro Yamada }; 164270e0c3eSMasahiro Yamada 165277b51e7SMasahiro Yamada gpio: gpio@55000000 { 166277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 167277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 168277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 169277b51e7SMasahiro Yamada interrupt-controller; 170277b51e7SMasahiro Yamada #interrupt-cells = <2>; 171277b51e7SMasahiro Yamada gpio-controller; 172277b51e7SMasahiro Yamada #gpio-cells = <2>; 173277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 174277b51e7SMasahiro Yamada <&pinctrl 43 0 0>, 175277b51e7SMasahiro Yamada <&pinctrl 51 0 0>, 176277b51e7SMasahiro Yamada <&pinctrl 96 0 0>, 177277b51e7SMasahiro Yamada <&pinctrl 160 0 0>, 178277b51e7SMasahiro Yamada <&pinctrl 184 0 0>; 179277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 180277b51e7SMasahiro Yamada "gpio_range1", 181277b51e7SMasahiro Yamada "gpio_range2", 182277b51e7SMasahiro Yamada "gpio_range3", 183277b51e7SMasahiro Yamada "gpio_range4", 184277b51e7SMasahiro Yamada "gpio_range5"; 185277b51e7SMasahiro Yamada ngpios = <200>; 186277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 187277b51e7SMasahiro Yamada <21 217 3>; 188270e0c3eSMasahiro Yamada }; 189270e0c3eSMasahiro Yamada 190178b3568SKatsuhiro Suzuki adamv@57920000 { 191178b3568SKatsuhiro Suzuki compatible = "socionext,uniphier-ld11-adamv", 192178b3568SKatsuhiro Suzuki "simple-mfd", "syscon"; 193178b3568SKatsuhiro Suzuki reg = <0x57920000 0x1000>; 194178b3568SKatsuhiro Suzuki 195178b3568SKatsuhiro Suzuki adamv_rst: reset { 196178b3568SKatsuhiro Suzuki compatible = "socionext,uniphier-ld11-adamv-reset"; 197178b3568SKatsuhiro Suzuki #reset-cells = <1>; 198178b3568SKatsuhiro Suzuki }; 199178b3568SKatsuhiro Suzuki }; 200178b3568SKatsuhiro Suzuki 201270e0c3eSMasahiro Yamada i2c0: i2c@58780000 { 202270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 203270e0c3eSMasahiro Yamada status = "disabled"; 204270e0c3eSMasahiro Yamada reg = <0x58780000 0x80>; 205270e0c3eSMasahiro Yamada #address-cells = <1>; 206270e0c3eSMasahiro Yamada #size-cells = <0>; 207270e0c3eSMasahiro Yamada interrupts = <0 41 4>; 208270e0c3eSMasahiro Yamada pinctrl-names = "default"; 209270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 210270e0c3eSMasahiro Yamada clocks = <&peri_clk 4>; 21176c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 212270e0c3eSMasahiro Yamada clock-frequency = <100000>; 213270e0c3eSMasahiro Yamada }; 214270e0c3eSMasahiro Yamada 215270e0c3eSMasahiro Yamada i2c1: i2c@58781000 { 216270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 217270e0c3eSMasahiro Yamada status = "disabled"; 218270e0c3eSMasahiro Yamada reg = <0x58781000 0x80>; 219270e0c3eSMasahiro Yamada #address-cells = <1>; 220270e0c3eSMasahiro Yamada #size-cells = <0>; 221270e0c3eSMasahiro Yamada interrupts = <0 42 4>; 222270e0c3eSMasahiro Yamada pinctrl-names = "default"; 223270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 224270e0c3eSMasahiro Yamada clocks = <&peri_clk 5>; 22576c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 226270e0c3eSMasahiro Yamada clock-frequency = <100000>; 227270e0c3eSMasahiro Yamada }; 228270e0c3eSMasahiro Yamada 229270e0c3eSMasahiro Yamada i2c2: i2c@58782000 { 230270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 231270e0c3eSMasahiro Yamada reg = <0x58782000 0x80>; 232270e0c3eSMasahiro Yamada #address-cells = <1>; 233270e0c3eSMasahiro Yamada #size-cells = <0>; 234270e0c3eSMasahiro Yamada interrupts = <0 43 4>; 235270e0c3eSMasahiro Yamada clocks = <&peri_clk 6>; 23676c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 237270e0c3eSMasahiro Yamada clock-frequency = <400000>; 238270e0c3eSMasahiro Yamada }; 239270e0c3eSMasahiro Yamada 240270e0c3eSMasahiro Yamada i2c3: i2c@58783000 { 241270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 242270e0c3eSMasahiro Yamada status = "disabled"; 243270e0c3eSMasahiro Yamada reg = <0x58783000 0x80>; 244270e0c3eSMasahiro Yamada #address-cells = <1>; 245270e0c3eSMasahiro Yamada #size-cells = <0>; 246270e0c3eSMasahiro Yamada interrupts = <0 44 4>; 247270e0c3eSMasahiro Yamada pinctrl-names = "default"; 248270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 249270e0c3eSMasahiro Yamada clocks = <&peri_clk 7>; 25076c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 251270e0c3eSMasahiro Yamada clock-frequency = <100000>; 252270e0c3eSMasahiro Yamada }; 253270e0c3eSMasahiro Yamada 254270e0c3eSMasahiro Yamada i2c4: i2c@58784000 { 255270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 256270e0c3eSMasahiro Yamada status = "disabled"; 257270e0c3eSMasahiro Yamada reg = <0x58784000 0x80>; 258270e0c3eSMasahiro Yamada #address-cells = <1>; 259270e0c3eSMasahiro Yamada #size-cells = <0>; 260270e0c3eSMasahiro Yamada interrupts = <0 45 4>; 261270e0c3eSMasahiro Yamada pinctrl-names = "default"; 262270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_i2c4>; 263270e0c3eSMasahiro Yamada clocks = <&peri_clk 8>; 26476c48e1eSMasahiro Yamada resets = <&peri_rst 8>; 265270e0c3eSMasahiro Yamada clock-frequency = <100000>; 266270e0c3eSMasahiro Yamada }; 267270e0c3eSMasahiro Yamada 268270e0c3eSMasahiro Yamada i2c5: i2c@58785000 { 269270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 270270e0c3eSMasahiro Yamada reg = <0x58785000 0x80>; 271270e0c3eSMasahiro Yamada #address-cells = <1>; 272270e0c3eSMasahiro Yamada #size-cells = <0>; 273270e0c3eSMasahiro Yamada interrupts = <0 25 4>; 274270e0c3eSMasahiro Yamada clocks = <&peri_clk 9>; 27576c48e1eSMasahiro Yamada resets = <&peri_rst 9>; 276270e0c3eSMasahiro Yamada clock-frequency = <400000>; 277270e0c3eSMasahiro Yamada }; 278270e0c3eSMasahiro Yamada 279270e0c3eSMasahiro Yamada system_bus: system-bus@58c00000 { 280270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 281270e0c3eSMasahiro Yamada status = "disabled"; 282270e0c3eSMasahiro Yamada reg = <0x58c00000 0x400>; 283270e0c3eSMasahiro Yamada #address-cells = <2>; 284270e0c3eSMasahiro Yamada #size-cells = <1>; 285270e0c3eSMasahiro Yamada pinctrl-names = "default"; 286270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 287270e0c3eSMasahiro Yamada }; 288270e0c3eSMasahiro Yamada 289b10ee7e3SMasahiro Yamada smpctrl@59801000 { 290270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 291270e0c3eSMasahiro Yamada reg = <0x59801000 0x400>; 292270e0c3eSMasahiro Yamada }; 293270e0c3eSMasahiro Yamada 2948f32b812SMasahiro Yamada sdctrl@59810000 { 2958f32b812SMasahiro Yamada compatible = "socionext,uniphier-ld11-sdctrl", 2968f32b812SMasahiro Yamada "simple-mfd", "syscon"; 2978f32b812SMasahiro Yamada reg = <0x59810000 0x400>; 2988f32b812SMasahiro Yamada 2998f32b812SMasahiro Yamada sd_rst: reset { 3008f32b812SMasahiro Yamada compatible = "socionext,uniphier-ld11-sd-reset"; 3018f32b812SMasahiro Yamada #reset-cells = <1>; 3028f32b812SMasahiro Yamada }; 3038f32b812SMasahiro Yamada }; 3048f32b812SMasahiro Yamada 305270e0c3eSMasahiro Yamada perictrl@59820000 { 306fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld11-perictrl", 307270e0c3eSMasahiro Yamada "simple-mfd", "syscon"; 308270e0c3eSMasahiro Yamada reg = <0x59820000 0x200>; 309270e0c3eSMasahiro Yamada 310270e0c3eSMasahiro Yamada peri_clk: clock { 311270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-peri-clock"; 312270e0c3eSMasahiro Yamada #clock-cells = <1>; 313270e0c3eSMasahiro Yamada }; 314270e0c3eSMasahiro Yamada 315270e0c3eSMasahiro Yamada peri_rst: reset { 316270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-peri-reset"; 317270e0c3eSMasahiro Yamada #reset-cells = <1>; 318270e0c3eSMasahiro Yamada }; 319270e0c3eSMasahiro Yamada }; 320270e0c3eSMasahiro Yamada 3213a93cc26SMasahiro Yamada emmc: sdhc@5a000000 { 3223a93cc26SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 3233a93cc26SMasahiro Yamada reg = <0x5a000000 0x400>; 3243a93cc26SMasahiro Yamada interrupts = <0 78 4>; 3259c0a9700SMasahiro Yamada pinctrl-names = "default"; 3269c0a9700SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 3273a93cc26SMasahiro Yamada clocks = <&sys_clk 4>; 32876c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 3293a93cc26SMasahiro Yamada bus-width = <8>; 3303a93cc26SMasahiro Yamada mmc-ddr-1_8v; 3313a93cc26SMasahiro Yamada mmc-hs200-1_8v; 332b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 333ba6f7011SMasahiro Yamada cdns,phy-input-delay-legacy = <4>; 334ba6f7011SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 335ba6f7011SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 336e345ededSMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 337e345ededSMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 3383a93cc26SMasahiro Yamada }; 3393a93cc26SMasahiro Yamada 340270e0c3eSMasahiro Yamada usb0: usb@5a800100 { 341270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ehci", "generic-ehci"; 342270e0c3eSMasahiro Yamada status = "disabled"; 343270e0c3eSMasahiro Yamada reg = <0x5a800100 0x100>; 344270e0c3eSMasahiro Yamada interrupts = <0 243 4>; 345270e0c3eSMasahiro Yamada pinctrl-names = "default"; 346270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_usb0>; 347deaa5519SMasahiro Yamada clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 348deaa5519SMasahiro Yamada <&mio_clk 12>; 3497a201e31SMasahiro Yamada resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 3507a201e31SMasahiro Yamada <&mio_rst 12>; 351270e0c3eSMasahiro Yamada }; 352270e0c3eSMasahiro Yamada 353270e0c3eSMasahiro Yamada usb1: usb@5a810100 { 354270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ehci", "generic-ehci"; 355270e0c3eSMasahiro Yamada status = "disabled"; 356270e0c3eSMasahiro Yamada reg = <0x5a810100 0x100>; 357270e0c3eSMasahiro Yamada interrupts = <0 244 4>; 358270e0c3eSMasahiro Yamada pinctrl-names = "default"; 359270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_usb1>; 360deaa5519SMasahiro Yamada clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 361deaa5519SMasahiro Yamada <&mio_clk 13>; 3627a201e31SMasahiro Yamada resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 3637a201e31SMasahiro Yamada <&mio_rst 13>; 364270e0c3eSMasahiro Yamada }; 365270e0c3eSMasahiro Yamada 366270e0c3eSMasahiro Yamada usb2: usb@5a820100 { 367270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ehci", "generic-ehci"; 368270e0c3eSMasahiro Yamada status = "disabled"; 369270e0c3eSMasahiro Yamada reg = <0x5a820100 0x100>; 370270e0c3eSMasahiro Yamada interrupts = <0 245 4>; 371270e0c3eSMasahiro Yamada pinctrl-names = "default"; 372270e0c3eSMasahiro Yamada pinctrl-0 = <&pinctrl_usb2>; 373deaa5519SMasahiro Yamada clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 374deaa5519SMasahiro Yamada <&mio_clk 14>; 3757a201e31SMasahiro Yamada resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 3767a201e31SMasahiro Yamada <&mio_rst 14>; 377270e0c3eSMasahiro Yamada }; 378270e0c3eSMasahiro Yamada 379270e0c3eSMasahiro Yamada mioctrl@5b3e0000 { 380fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld11-mioctrl", 381270e0c3eSMasahiro Yamada "simple-mfd", "syscon"; 382270e0c3eSMasahiro Yamada reg = <0x5b3e0000 0x800>; 383270e0c3eSMasahiro Yamada 384270e0c3eSMasahiro Yamada mio_clk: clock { 385270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-mio-clock"; 386270e0c3eSMasahiro Yamada #clock-cells = <1>; 387270e0c3eSMasahiro Yamada }; 388270e0c3eSMasahiro Yamada 389270e0c3eSMasahiro Yamada mio_rst: reset { 390270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-mio-reset"; 391270e0c3eSMasahiro Yamada #reset-cells = <1>; 392270e0c3eSMasahiro Yamada resets = <&sys_rst 7>; 393270e0c3eSMasahiro Yamada }; 394270e0c3eSMasahiro Yamada }; 395270e0c3eSMasahiro Yamada 396270e0c3eSMasahiro Yamada soc-glue@5f800000 { 397fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld11-soc-glue", 398270e0c3eSMasahiro Yamada "simple-mfd", "syscon"; 399270e0c3eSMasahiro Yamada reg = <0x5f800000 0x2000>; 400270e0c3eSMasahiro Yamada 401270e0c3eSMasahiro Yamada pinctrl: pinctrl { 402270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-pinctrl"; 403270e0c3eSMasahiro Yamada }; 404270e0c3eSMasahiro Yamada }; 405270e0c3eSMasahiro Yamada 406f05851e1SKeiji Hayashibara soc-glue@5f900000 { 407f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-ld11-soc-glue-debug", 408f05851e1SKeiji Hayashibara "simple-mfd"; 409f05851e1SKeiji Hayashibara #address-cells = <1>; 410f05851e1SKeiji Hayashibara #size-cells = <1>; 411f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 412f05851e1SKeiji Hayashibara 413f05851e1SKeiji Hayashibara efuse@100 { 414f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 415f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 416f05851e1SKeiji Hayashibara }; 417f05851e1SKeiji Hayashibara 418f05851e1SKeiji Hayashibara efuse@200 { 419f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 420f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 421f05851e1SKeiji Hayashibara }; 422f05851e1SKeiji Hayashibara }; 423f05851e1SKeiji Hayashibara 4243dfc6e98SMasahiro Yamada aidet: aidet@5fc20000 { 4253dfc6e98SMasahiro Yamada compatible = "socionext,uniphier-ld11-aidet"; 4263dfc6e98SMasahiro Yamada reg = <0x5fc20000 0x200>; 4273dfc6e98SMasahiro Yamada interrupt-controller; 4283dfc6e98SMasahiro Yamada #interrupt-cells = <2>; 4293dfc6e98SMasahiro Yamada }; 4303dfc6e98SMasahiro Yamada 431270e0c3eSMasahiro Yamada gic: interrupt-controller@5fe00000 { 432270e0c3eSMasahiro Yamada compatible = "arm,gic-v3"; 433270e0c3eSMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 434270e0c3eSMasahiro Yamada <0x5fe40000 0x80000>; /* GICR */ 435270e0c3eSMasahiro Yamada interrupt-controller; 436270e0c3eSMasahiro Yamada #interrupt-cells = <3>; 437270e0c3eSMasahiro Yamada interrupts = <1 9 4>; 438270e0c3eSMasahiro Yamada }; 439270e0c3eSMasahiro Yamada 440270e0c3eSMasahiro Yamada sysctrl@61840000 { 441270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-sysctrl", 442270e0c3eSMasahiro Yamada "simple-mfd", "syscon"; 4431ef64af8SMasahiro Yamada reg = <0x61840000 0x10000>; 444270e0c3eSMasahiro Yamada 445270e0c3eSMasahiro Yamada sys_clk: clock { 446270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-clock"; 447270e0c3eSMasahiro Yamada #clock-cells = <1>; 448270e0c3eSMasahiro Yamada }; 449270e0c3eSMasahiro Yamada 450270e0c3eSMasahiro Yamada sys_rst: reset { 451270e0c3eSMasahiro Yamada compatible = "socionext,uniphier-ld11-reset"; 452270e0c3eSMasahiro Yamada #reset-cells = <1>; 453270e0c3eSMasahiro Yamada }; 4544c4c960aSKeiji Hayashibara 4554c4c960aSKeiji Hayashibara watchdog { 4564c4c960aSKeiji Hayashibara compatible = "socionext,uniphier-wdt"; 4574c4c960aSKeiji Hayashibara }; 458270e0c3eSMasahiro Yamada }; 459e5aefb38SMasahiro Yamada 460e5aefb38SMasahiro Yamada nand: nand@68000000 { 461e5aefb38SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 462e5aefb38SMasahiro Yamada status = "disabled"; 463e5aefb38SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 464e5aefb38SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 465e5aefb38SMasahiro Yamada interrupts = <0 65 4>; 466e5aefb38SMasahiro Yamada pinctrl-names = "default"; 467e5aefb38SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 468e5aefb38SMasahiro Yamada clocks = <&sys_clk 2>; 46976c48e1eSMasahiro Yamada resets = <&sys_rst 2>; 470e5aefb38SMasahiro Yamada }; 471270e0c3eSMasahiro Yamada }; 472270e0c3eSMasahiro Yamada}; 473270e0c3eSMasahiro Yamada 4745740ea4eSMasahiro Yamada#include "uniphier-pinctrl.dtsi" 475