1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2LC SMARC pincontrol parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11&pinctrl {
12	pinctrl-0 = <&sound_clk_pins>;
13	pinctrl-names = "default";
14
15#if SW_SCIF_CAN
16	/* SW8 should be at position 2->1 */
17	can1_pins: can1 {
18		pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */
19			 <RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */
20	};
21#endif
22
23#if SW_RSPI_CAN
24	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
25	can1-stb-hog {
26		gpio-hog;
27		gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
28		output-low;
29		line-name = "can1_stb";
30	};
31
32	can1_pins: can1 {
33		pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */
34			 <RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */
35	};
36#endif
37
38	scif0_pins: scif0 {
39		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
40			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
41	};
42
43	scif1_pins: scif1 {
44		pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
45			 <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
46			 <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
47			 <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
48	};
49
50	sd1-pwr-en-hog {
51		gpio-hog;
52		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
53		output-high;
54		line-name = "sd1_pwr_en";
55	};
56
57	sdhi1_pins: sd1 {
58		sd1_data {
59			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
60			power-source = <3300>;
61		};
62
63		sd1_ctrl {
64			pins = "SD1_CLK", "SD1_CMD";
65			power-source = <3300>;
66		};
67
68		sd1_mux {
69			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
70		};
71	};
72
73	sdhi1_pins_uhs: sd1_uhs {
74		sd1_data_uhs {
75			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
76			power-source = <1800>;
77		};
78
79		sd1_ctrl_uhs {
80			pins = "SD1_CLK", "SD1_CMD";
81			power-source = <1800>;
82		};
83
84		sd1_mux_uhs {
85			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
86		};
87	};
88
89	sound_clk_pins: sound_clk {
90		pins = "AUDIO_CLK1", "AUDIO_CLK2";
91		input-enable;
92	};
93
94	usb0_pins: usb0 {
95		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
96			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
97			 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
98	};
99
100	usb1_pins: usb1 {
101		pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
102			 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
103	};
104};
105
106