1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g043-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g043"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio2-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-125000000 { 50 opp-hz = /bits/ 64 <125000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-250000000 { 55 opp-hz = /bits/ 64 <250000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-500000000 { 60 opp-hz = /bits/ 64 <500000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1000000000 { 65 opp-hz = /bits/ 64 <1000000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu0: cpu@0 { 77 compatible = "arm,cortex-a55"; 78 reg = <0>; 79 device_type = "cpu"; 80 #cooling-cells = <2>; 81 next-level-cache = <&L3_CA55>; 82 enable-method = "psci"; 83 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 87 L3_CA55: cache-controller-0 { 88 compatible = "cache"; 89 cache-unified; 90 cache-size = <0x40000>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0", "arm,psci-0.2"; 96 method = "smc"; 97 }; 98 99 soc: soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&gic>; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 106 ssi0: ssi@10049c00 { 107 compatible = "renesas,r9a07g043-ssi", 108 "renesas,rz-ssi"; 109 reg = <0 0x10049c00 0 0x400>; 110 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 112 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 113 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 114 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 115 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 116 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 117 <&audio_clk1>, <&audio_clk2>; 118 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 119 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 120 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 121 dma-names = "tx", "rx"; 122 power-domains = <&cpg>; 123 #sound-dai-cells = <0>; 124 status = "disabled"; 125 }; 126 127 ssi1: ssi@1004a000 { 128 compatible = "renesas,r9a07g043-ssi", 129 "renesas,rz-ssi"; 130 reg = <0 0x1004a000 0 0x400>; 131 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 133 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 134 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 135 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 136 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 137 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 138 <&audio_clk1>, <&audio_clk2>; 139 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 140 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 141 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 142 dma-names = "tx", "rx"; 143 power-domains = <&cpg>; 144 #sound-dai-cells = <0>; 145 status = "disabled"; 146 }; 147 148 ssi2: ssi@1004a400 { 149 compatible = "renesas,r9a07g043-ssi", 150 "renesas,rz-ssi"; 151 reg = <0 0x1004a400 0 0x400>; 152 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 154 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 155 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 156 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 157 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 158 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 159 <&audio_clk1>, <&audio_clk2>; 160 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 161 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 162 dmas = <&dmac 0x265f>; 163 dma-names = "rt"; 164 power-domains = <&cpg>; 165 #sound-dai-cells = <0>; 166 status = "disabled"; 167 }; 168 169 ssi3: ssi@1004a800 { 170 compatible = "renesas,r9a07g043-ssi", 171 "renesas,rz-ssi"; 172 reg = <0 0x1004a800 0 0x400>; 173 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 175 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 176 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 177 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 178 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 179 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 180 <&audio_clk1>, <&audio_clk2>; 181 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 182 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 183 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 184 dma-names = "tx", "rx"; 185 power-domains = <&cpg>; 186 #sound-dai-cells = <0>; 187 status = "disabled"; 188 }; 189 190 spi0: spi@1004ac00 { 191 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 192 reg = <0 0x1004ac00 0 0x400>; 193 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-names = "error", "rx", "tx"; 197 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; 198 resets = <&cpg R9A07G043_RSPI0_RST>; 199 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 200 dma-names = "tx", "rx"; 201 power-domains = <&cpg>; 202 num-cs = <1>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 status = "disabled"; 206 }; 207 208 spi1: spi@1004b000 { 209 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 210 reg = <0 0x1004b000 0 0x400>; 211 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "error", "rx", "tx"; 215 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; 216 resets = <&cpg R9A07G043_RSPI1_RST>; 217 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 218 dma-names = "tx", "rx"; 219 power-domains = <&cpg>; 220 num-cs = <1>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 status = "disabled"; 224 }; 225 226 spi2: spi@1004b400 { 227 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 228 reg = <0 0x1004b400 0 0x400>; 229 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 232 interrupt-names = "error", "rx", "tx"; 233 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; 234 resets = <&cpg R9A07G043_RSPI2_RST>; 235 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 236 dma-names = "tx", "rx"; 237 power-domains = <&cpg>; 238 num-cs = <1>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 status = "disabled"; 242 }; 243 244 scif0: serial@1004b800 { 245 compatible = "renesas,scif-r9a07g043", 246 "renesas,scif-r9a07g044"; 247 reg = <0 0x1004b800 0 0x400>; 248 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 254 interrupt-names = "eri", "rxi", "txi", 255 "bri", "dri", "tei"; 256 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 257 clock-names = "fck"; 258 power-domains = <&cpg>; 259 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 260 status = "disabled"; 261 }; 262 263 scif1: serial@1004bc00 { 264 compatible = "renesas,scif-r9a07g043", 265 "renesas,scif-r9a07g044"; 266 reg = <0 0x1004bc00 0 0x400>; 267 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "eri", "rxi", "txi", 274 "bri", "dri", "tei"; 275 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 276 clock-names = "fck"; 277 power-domains = <&cpg>; 278 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 279 status = "disabled"; 280 }; 281 282 scif2: serial@1004c000 { 283 compatible = "renesas,scif-r9a07g043", 284 "renesas,scif-r9a07g044"; 285 reg = <0 0x1004c000 0 0x400>; 286 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-names = "eri", "rxi", "txi", 293 "bri", "dri", "tei"; 294 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 295 clock-names = "fck"; 296 power-domains = <&cpg>; 297 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 298 status = "disabled"; 299 }; 300 301 scif3: serial@1004c400 { 302 compatible = "renesas,scif-r9a07g043", 303 "renesas,scif-r9a07g044"; 304 reg = <0 0x1004c400 0 0x400>; 305 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 311 interrupt-names = "eri", "rxi", "txi", 312 "bri", "dri", "tei"; 313 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 314 clock-names = "fck"; 315 power-domains = <&cpg>; 316 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 317 status = "disabled"; 318 }; 319 320 scif4: serial@1004c800 { 321 compatible = "renesas,scif-r9a07g043", 322 "renesas,scif-r9a07g044"; 323 reg = <0 0x1004c800 0 0x400>; 324 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 330 interrupt-names = "eri", "rxi", "txi", 331 "bri", "dri", "tei"; 332 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 333 clock-names = "fck"; 334 power-domains = <&cpg>; 335 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 336 status = "disabled"; 337 }; 338 339 sci0: serial@1004d000 { 340 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 341 reg = <0 0x1004d000 0 0x400>; 342 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-names = "eri", "rxi", "txi", "tei"; 347 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 348 clock-names = "fck"; 349 power-domains = <&cpg>; 350 resets = <&cpg R9A07G043_SCI0_RST>; 351 status = "disabled"; 352 }; 353 354 sci1: serial@1004d400 { 355 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 356 reg = <0 0x1004d400 0 0x400>; 357 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 359 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 360 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 361 interrupt-names = "eri", "rxi", "txi", "tei"; 362 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 363 clock-names = "fck"; 364 power-domains = <&cpg>; 365 resets = <&cpg R9A07G043_SCI1_RST>; 366 status = "disabled"; 367 }; 368 369 canfd: can@10050000 { 370 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; 371 reg = <0 0x10050000 0 0x8000>; 372 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 380 interrupt-names = "g_err", "g_recc", 381 "ch0_err", "ch0_rec", "ch0_trx", 382 "ch1_err", "ch1_rec", "ch1_trx"; 383 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, 384 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, 385 <&can_clk>; 386 clock-names = "fck", "canfd", "can_clk"; 387 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; 388 assigned-clock-rates = <50000000>; 389 resets = <&cpg R9A07G043_CANFD_RSTP_N>, 390 <&cpg R9A07G043_CANFD_RSTC_N>; 391 reset-names = "rstp_n", "rstc_n"; 392 power-domains = <&cpg>; 393 status = "disabled"; 394 395 channel0 { 396 status = "disabled"; 397 }; 398 channel1 { 399 status = "disabled"; 400 }; 401 }; 402 403 i2c0: i2c@10058000 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 407 reg = <0 0x10058000 0 0x400>; 408 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "tei", "ri", "ti", "spi", "sti", 417 "naki", "ali", "tmoi"; 418 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 419 clock-frequency = <100000>; 420 resets = <&cpg R9A07G043_I2C0_MRST>; 421 power-domains = <&cpg>; 422 status = "disabled"; 423 }; 424 425 i2c1: i2c@10058400 { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 429 reg = <0 0x10058400 0 0x400>; 430 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 432 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 433 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 438 interrupt-names = "tei", "ri", "ti", "spi", "sti", 439 "naki", "ali", "tmoi"; 440 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 441 clock-frequency = <100000>; 442 resets = <&cpg R9A07G043_I2C1_MRST>; 443 power-domains = <&cpg>; 444 status = "disabled"; 445 }; 446 447 i2c2: i2c@10058800 { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 451 reg = <0 0x10058800 0 0x400>; 452 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-names = "tei", "ri", "ti", "spi", "sti", 461 "naki", "ali", "tmoi"; 462 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 463 clock-frequency = <100000>; 464 resets = <&cpg R9A07G043_I2C2_MRST>; 465 power-domains = <&cpg>; 466 status = "disabled"; 467 }; 468 469 i2c3: i2c@10058c00 { 470 #address-cells = <1>; 471 #size-cells = <0>; 472 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 473 reg = <0 0x10058c00 0 0x400>; 474 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "tei", "ri", "ti", "spi", "sti", 483 "naki", "ali", "tmoi"; 484 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 485 clock-frequency = <100000>; 486 resets = <&cpg R9A07G043_I2C3_MRST>; 487 power-domains = <&cpg>; 488 status = "disabled"; 489 }; 490 491 adc: adc@10059000 { 492 compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; 493 reg = <0 0x10059000 0 0x400>; 494 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 495 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, 496 <&cpg CPG_MOD R9A07G043_ADC_PCLK>; 497 clock-names = "adclk", "pclk"; 498 resets = <&cpg R9A07G043_ADC_PRESETN>, 499 <&cpg R9A07G043_ADC_ADRST_N>; 500 reset-names = "presetn", "adrst-n"; 501 power-domains = <&cpg>; 502 status = "disabled"; 503 504 #address-cells = <1>; 505 #size-cells = <0>; 506 507 channel@0 { 508 reg = <0>; 509 }; 510 channel@1 { 511 reg = <1>; 512 }; 513 }; 514 515 tsu: thermal@10059400 { 516 compatible = "renesas,r9a07g043-tsu", 517 "renesas,rzg2l-tsu"; 518 reg = <0 0x10059400 0 0x400>; 519 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; 520 resets = <&cpg R9A07G043_TSU_PRESETN>; 521 power-domains = <&cpg>; 522 #thermal-sensor-cells = <1>; 523 }; 524 525 sbc: spi@10060000 { 526 compatible = "renesas,r9a07g043-rpc-if", 527 "renesas,rzg2l-rpc-if"; 528 reg = <0 0x10060000 0 0x10000>, 529 <0 0x20000000 0 0x10000000>, 530 <0 0x10070000 0 0x10000>; 531 reg-names = "regs", "dirmap", "wbuf"; 532 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, 533 <&cpg CPG_MOD R9A07G043_SPI_CLK>; 534 resets = <&cpg R9A07G043_SPI_RST>; 535 power-domains = <&cpg>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 cpg: clock-controller@11010000 { 542 compatible = "renesas,r9a07g043-cpg"; 543 reg = <0 0x11010000 0 0x10000>; 544 clocks = <&extal_clk>; 545 clock-names = "extal"; 546 #clock-cells = <2>; 547 #reset-cells = <1>; 548 #power-domain-cells = <0>; 549 }; 550 551 sysc: system-controller@11020000 { 552 compatible = "renesas,r9a07g043-sysc"; 553 reg = <0 0x11020000 0 0x10000>; 554 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 558 interrupt-names = "lpm_int", "ca55stbydone_int", 559 "cm33stbyr_int", "ca55_deny"; 560 status = "disabled"; 561 }; 562 563 pinctrl: pinctrl@11030000 { 564 compatible = "renesas,r9a07g043-pinctrl"; 565 reg = <0 0x11030000 0 0x10000>; 566 gpio-controller; 567 #gpio-cells = <2>; 568 gpio-ranges = <&pinctrl 0 0 152>; 569 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 570 power-domains = <&cpg>; 571 resets = <&cpg R9A07G043_GPIO_RSTN>, 572 <&cpg R9A07G043_GPIO_PORT_RESETN>, 573 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 574 }; 575 576 dmac: dma-controller@11820000 { 577 compatible = "renesas,r9a07g043-dmac", 578 "renesas,rz-dmac"; 579 reg = <0 0x11820000 0 0x10000>, 580 <0 0x11830000 0 0x10000>; 581 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 587 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 588 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 589 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 590 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 591 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 592 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 593 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 594 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 595 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 596 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 597 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 598 interrupt-names = "error", 599 "ch0", "ch1", "ch2", "ch3", 600 "ch4", "ch5", "ch6", "ch7", 601 "ch8", "ch9", "ch10", "ch11", 602 "ch12", "ch13", "ch14", "ch15"; 603 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 604 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 605 power-domains = <&cpg>; 606 resets = <&cpg R9A07G043_DMAC_ARESETN>, 607 <&cpg R9A07G043_DMAC_RST_ASYNC>; 608 #dma-cells = <1>; 609 dma-channels = <16>; 610 }; 611 612 gic: interrupt-controller@11900000 { 613 compatible = "arm,gic-v3"; 614 #interrupt-cells = <3>; 615 #address-cells = <0>; 616 interrupt-controller; 617 reg = <0x0 0x11900000 0 0x40000>, 618 <0x0 0x11940000 0 0x60000>; 619 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 620 }; 621 622 sdhi0: mmc@11c00000 { 623 compatible = "renesas,sdhi-r9a07g043", 624 "renesas,rcar-gen3-sdhi"; 625 reg = <0x0 0x11c00000 0 0x10000>; 626 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 629 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 630 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 631 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 632 clock-names = "core", "clkh", "cd", "aclk"; 633 resets = <&cpg R9A07G043_SDHI0_IXRST>; 634 power-domains = <&cpg>; 635 status = "disabled"; 636 }; 637 638 sdhi1: mmc@11c10000 { 639 compatible = "renesas,sdhi-r9a07g043", 640 "renesas,rcar-gen3-sdhi"; 641 reg = <0x0 0x11c10000 0 0x10000>; 642 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 645 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 646 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 647 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 648 clock-names = "core", "clkh", "cd", "aclk"; 649 resets = <&cpg R9A07G043_SDHI1_IXRST>; 650 power-domains = <&cpg>; 651 status = "disabled"; 652 }; 653 654 eth0: ethernet@11c20000 { 655 compatible = "renesas,r9a07g043-gbeth", 656 "renesas,rzg2l-gbeth"; 657 reg = <0 0x11c20000 0 0x10000>; 658 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 661 interrupt-names = "mux", "fil", "arp_ns"; 662 phy-mode = "rgmii"; 663 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 664 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 665 <&cpg CPG_CORE R9A07G043_CLK_HP>; 666 clock-names = "axi", "chi", "refclk"; 667 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 668 power-domains = <&cpg>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 status = "disabled"; 672 }; 673 674 eth1: ethernet@11c30000 { 675 compatible = "renesas,r9a07g043-gbeth", 676 "renesas,rzg2l-gbeth"; 677 reg = <0 0x11c30000 0 0x10000>; 678 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 681 interrupt-names = "mux", "fil", "arp_ns"; 682 phy-mode = "rgmii"; 683 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 684 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 685 <&cpg CPG_CORE R9A07G043_CLK_HP>; 686 clock-names = "axi", "chi", "refclk"; 687 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 688 power-domains = <&cpg>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 phyrst: usbphy-ctrl@11c40000 { 695 compatible = "renesas,r9a07g043-usbphy-ctrl", 696 "renesas,rzg2l-usbphy-ctrl"; 697 reg = <0 0x11c40000 0 0x10000>; 698 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; 699 resets = <&cpg R9A07G043_USB_PRESETN>; 700 power-domains = <&cpg>; 701 #reset-cells = <1>; 702 status = "disabled"; 703 }; 704 705 ohci0: usb@11c50000 { 706 compatible = "generic-ohci"; 707 reg = <0 0x11c50000 0 0x100>; 708 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 710 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 711 resets = <&phyrst 0>, 712 <&cpg R9A07G043_USB_U2H0_HRESETN>; 713 phys = <&usb2_phy0 1>; 714 phy-names = "usb"; 715 power-domains = <&cpg>; 716 status = "disabled"; 717 }; 718 719 ohci1: usb@11c70000 { 720 compatible = "generic-ohci"; 721 reg = <0 0x11c70000 0 0x100>; 722 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 724 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 725 resets = <&phyrst 1>, 726 <&cpg R9A07G043_USB_U2H1_HRESETN>; 727 phys = <&usb2_phy1 1>; 728 phy-names = "usb"; 729 power-domains = <&cpg>; 730 status = "disabled"; 731 }; 732 733 ehci0: usb@11c50100 { 734 compatible = "generic-ehci"; 735 reg = <0 0x11c50100 0 0x100>; 736 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 738 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 739 resets = <&phyrst 0>, 740 <&cpg R9A07G043_USB_U2H0_HRESETN>; 741 phys = <&usb2_phy0 2>; 742 phy-names = "usb"; 743 companion = <&ohci0>; 744 power-domains = <&cpg>; 745 status = "disabled"; 746 }; 747 748 ehci1: usb@11c70100 { 749 compatible = "generic-ehci"; 750 reg = <0 0x11c70100 0 0x100>; 751 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 753 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 754 resets = <&phyrst 1>, 755 <&cpg R9A07G043_USB_U2H1_HRESETN>; 756 phys = <&usb2_phy1 2>; 757 phy-names = "usb"; 758 companion = <&ohci1>; 759 power-domains = <&cpg>; 760 status = "disabled"; 761 }; 762 763 usb2_phy0: usb-phy@11c50200 { 764 compatible = "renesas,usb2-phy-r9a07g043", 765 "renesas,rzg2l-usb2-phy"; 766 reg = <0 0x11c50200 0 0x700>; 767 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 769 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 770 resets = <&phyrst 0>; 771 #phy-cells = <1>; 772 power-domains = <&cpg>; 773 status = "disabled"; 774 }; 775 776 usb2_phy1: usb-phy@11c70200 { 777 compatible = "renesas,usb2-phy-r9a07g043", 778 "renesas,rzg2l-usb2-phy"; 779 reg = <0 0x11c70200 0 0x700>; 780 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 782 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 783 resets = <&phyrst 1>; 784 #phy-cells = <1>; 785 power-domains = <&cpg>; 786 status = "disabled"; 787 }; 788 789 hsusb: usb@11c60000 { 790 compatible = "renesas,usbhs-r9a07g043", 791 "renesas,rza2-usbhs"; 792 reg = <0 0x11c60000 0 0x10000>; 793 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 794 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 798 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; 799 resets = <&phyrst 0>, 800 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; 801 renesas,buswait = <7>; 802 phys = <&usb2_phy0 3>; 803 phy-names = "usb"; 804 power-domains = <&cpg>; 805 status = "disabled"; 806 }; 807 808 wdt0: watchdog@12800800 { 809 compatible = "renesas,r9a07g043-wdt", 810 "renesas,rzg2l-wdt"; 811 reg = <0 0x12800800 0 0x400>; 812 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, 813 <&cpg CPG_MOD R9A07G043_WDT0_CLK>; 814 clock-names = "pclk", "oscclk"; 815 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "wdt", "perrout"; 818 resets = <&cpg R9A07G043_WDT0_PRESETN>; 819 power-domains = <&cpg>; 820 status = "disabled"; 821 }; 822 823 wdt2: watchdog@12800400 { 824 compatible = "renesas,r9a07g043-wdt", 825 "renesas,rzg2l-wdt"; 826 reg = <0 0x12800400 0 0x400>; 827 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>, 828 <&cpg CPG_MOD R9A07G043_WDT2_CLK>; 829 clock-names = "pclk", "oscclk"; 830 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "wdt", "perrout"; 833 resets = <&cpg R9A07G043_WDT2_PRESETN>; 834 power-domains = <&cpg>; 835 status = "disabled"; 836 }; 837 838 ostm0: timer@12801000 { 839 compatible = "renesas,r9a07g043-ostm", 840 "renesas,ostm"; 841 reg = <0x0 0x12801000 0x0 0x400>; 842 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 843 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; 844 resets = <&cpg R9A07G043_OSTM0_PRESETZ>; 845 power-domains = <&cpg>; 846 status = "disabled"; 847 }; 848 849 ostm1: timer@12801400 { 850 compatible = "renesas,r9a07g043-ostm", 851 "renesas,ostm"; 852 reg = <0x0 0x12801400 0x0 0x400>; 853 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 854 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; 855 resets = <&cpg R9A07G043_OSTM1_PRESETZ>; 856 power-domains = <&cpg>; 857 status = "disabled"; 858 }; 859 860 ostm2: timer@12801800 { 861 compatible = "renesas,r9a07g043-ostm", 862 "renesas,ostm"; 863 reg = <0x0 0x12801800 0x0 0x400>; 864 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 865 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; 866 resets = <&cpg R9A07G043_OSTM2_PRESETZ>; 867 power-domains = <&cpg>; 868 status = "disabled"; 869 }; 870 }; 871 872 thermal-zones { 873 cpu-thermal { 874 polling-delay-passive = <250>; 875 polling-delay = <1000>; 876 thermal-sensors = <&tsu 0>; 877 sustainable-power = <717>; 878 879 cooling-maps { 880 map0 { 881 trip = <&target>; 882 cooling-device = <&cpu0 0 2>; 883 contribution = <1024>; 884 }; 885 }; 886 887 trips { 888 sensor_crit: sensor-crit { 889 temperature = <125000>; 890 hysteresis = <1000>; 891 type = "critical"; 892 }; 893 894 target: trip-point { 895 temperature = <100000>; 896 hysteresis = <1000>; 897 type = "passive"; 898 }; 899 }; 900 }; 901 }; 902 903 timer { 904 compatible = "arm,armv8-timer"; 905 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 906 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 907 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 908 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 909 }; 910}; 911