1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 a55_0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 26 }; 27 }; 28 29 extal_clk: extal { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 /* This value must be overridden by the board */ 33 clock-frequency = <0>; 34 }; 35 36 extalr_clk: extalr { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 /* This value must be overridden by the board */ 40 clock-frequency = <0>; 41 }; 42 43 pmu_a55 { 44 compatible = "arm,cortex-a55-pmu"; 45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46 }; 47 48 /* External SCIF clock - to be overridden by boards that provide it */ 49 scif_clk: scif { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 53 }; 54 55 soc: soc { 56 compatible = "simple-bus"; 57 interrupt-parent = <&gic>; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 62 rwdt: watchdog@e6020000 { 63 compatible = "renesas,r8a779f0-wdt", 64 "renesas,rcar-gen4-wdt"; 65 reg = <0 0xe6020000 0 0x0c>; 66 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&cpg CPG_MOD 907>; 68 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 69 resets = <&cpg 907>; 70 status = "disabled"; 71 }; 72 73 pfc: pinctrl@e6050000 { 74 compatible = "renesas,pfc-r8a779f0"; 75 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 76 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 77 }; 78 79 cpg: clock-controller@e6150000 { 80 compatible = "renesas,r8a779f0-cpg-mssr"; 81 reg = <0 0xe6150000 0 0x4000>; 82 clocks = <&extal_clk>, <&extalr_clk>; 83 clock-names = "extal", "extalr"; 84 #clock-cells = <2>; 85 #power-domain-cells = <0>; 86 #reset-cells = <1>; 87 }; 88 89 rst: reset-controller@e6160000 { 90 compatible = "renesas,r8a779f0-rst"; 91 reg = <0 0xe6160000 0 0x4000>; 92 }; 93 94 sysc: system-controller@e6180000 { 95 compatible = "renesas,r8a779f0-sysc"; 96 reg = <0 0xe6180000 0 0x4000>; 97 #power-domain-cells = <1>; 98 }; 99 100 i2c0: i2c@e6500000 { 101 compatible = "renesas,i2c-r8a779f0", 102 "renesas,rcar-gen4-i2c"; 103 reg = <0 0xe6500000 0 0x40>; 104 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&cpg CPG_MOD 518>; 106 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 107 resets = <&cpg 518>; 108 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 109 <&dmac1 0x91>, <&dmac1 0x90>; 110 dma-names = "tx", "rx", "tx", "rx"; 111 i2c-scl-internal-delay-ns = <110>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 status = "disabled"; 115 }; 116 117 i2c1: i2c@e6508000 { 118 compatible = "renesas,i2c-r8a779f0", 119 "renesas,rcar-gen4-i2c"; 120 reg = <0 0xe6508000 0 0x40>; 121 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&cpg CPG_MOD 519>; 123 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 124 resets = <&cpg 519>; 125 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 126 <&dmac1 0x93>, <&dmac1 0x92>; 127 dma-names = "tx", "rx", "tx", "rx"; 128 i2c-scl-internal-delay-ns = <110>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 status = "disabled"; 132 }; 133 134 i2c2: i2c@e6510000 { 135 compatible = "renesas,i2c-r8a779f0", 136 "renesas,rcar-gen4-i2c"; 137 reg = <0 0xe6510000 0 0x40>; 138 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&cpg CPG_MOD 520>; 140 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 141 resets = <&cpg 520>; 142 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 143 <&dmac1 0x95>, <&dmac1 0x94>; 144 dma-names = "tx", "rx", "tx", "rx"; 145 i2c-scl-internal-delay-ns = <110>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 status = "disabled"; 149 }; 150 151 i2c3: i2c@e66d0000 { 152 compatible = "renesas,i2c-r8a779f0", 153 "renesas,rcar-gen4-i2c"; 154 reg = <0 0xe66d0000 0 0x40>; 155 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&cpg CPG_MOD 521>; 157 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 158 resets = <&cpg 521>; 159 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 160 <&dmac1 0x97>, <&dmac1 0x96>; 161 dma-names = "tx", "rx", "tx", "rx"; 162 i2c-scl-internal-delay-ns = <110>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 status = "disabled"; 166 }; 167 168 i2c4: i2c@e66d8000 { 169 compatible = "renesas,i2c-r8a779f0", 170 "renesas,rcar-gen4-i2c"; 171 reg = <0 0xe66d8000 0 0x40>; 172 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&cpg CPG_MOD 522>; 174 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 175 resets = <&cpg 522>; 176 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 177 <&dmac1 0x99>, <&dmac1 0x98>; 178 dma-names = "tx", "rx", "tx", "rx"; 179 i2c-scl-internal-delay-ns = <110>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 status = "disabled"; 183 }; 184 185 i2c5: i2c@e66e0000 { 186 compatible = "renesas,i2c-r8a779f0", 187 "renesas,rcar-gen4-i2c"; 188 reg = <0 0xe66e0000 0 0x40>; 189 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&cpg CPG_MOD 523>; 191 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 192 resets = <&cpg 523>; 193 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 194 <&dmac1 0x9b>, <&dmac1 0x9a>; 195 dma-names = "tx", "rx", "tx", "rx"; 196 i2c-scl-internal-delay-ns = <110>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 status = "disabled"; 200 }; 201 202 scif3: serial@e6c50000 { 203 compatible = "renesas,scif-r8a779f0", 204 "renesas,rcar-gen4-scif", "renesas,scif"; 205 reg = <0 0xe6c50000 0 64>; 206 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cpg CPG_MOD 704>, 208 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 209 <&scif_clk>; 210 clock-names = "fck", "brg_int", "scif_clk"; 211 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 212 resets = <&cpg 704>; 213 status = "disabled"; 214 }; 215 216 dmac0: dma-controller@e7350000 { 217 compatible = "renesas,dmac-r8a779f0", 218 "renesas,rcar-gen4-dmac"; 219 reg = <0 0xe7350000 0 0x1000>, 220 <0 0xe7300000 0 0x10000>; 221 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-names = "error", 239 "ch0", "ch1", "ch2", "ch3", "ch4", 240 "ch5", "ch6", "ch7", "ch8", "ch9", 241 "ch10", "ch11", "ch12", "ch13", 242 "ch14", "ch15"; 243 clocks = <&cpg CPG_MOD 709>; 244 clock-names = "fck"; 245 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 246 resets = <&cpg 709>; 247 #dma-cells = <1>; 248 dma-channels = <16>; 249 }; 250 251 dmac1: dma-controller@e7351000 { 252 compatible = "renesas,dmac-r8a779f0", 253 "renesas,rcar-gen4-dmac"; 254 reg = <0 0xe7351000 0 0x1000>, 255 <0 0xe7310000 0 0x10000>; 256 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "error", 274 "ch0", "ch1", "ch2", "ch3", "ch4", 275 "ch5", "ch6", "ch7", "ch8", "ch9", 276 "ch10", "ch11", "ch12", "ch13", 277 "ch14", "ch15"; 278 clocks = <&cpg CPG_MOD 710>; 279 clock-names = "fck"; 280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 281 resets = <&cpg 710>; 282 #dma-cells = <1>; 283 dma-channels = <16>; 284 }; 285 286 gic: interrupt-controller@f1000000 { 287 compatible = "arm,gic-v3"; 288 #interrupt-cells = <3>; 289 #address-cells = <0>; 290 interrupt-controller; 291 reg = <0x0 0xf1000000 0 0x20000>, 292 <0x0 0xf1060000 0 0x110000>; 293 interrupts = <GIC_PPI 9 294 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 295 }; 296 297 prr: chipid@fff00044 { 298 compatible = "renesas,prr"; 299 reg = <0 0xfff00044 0 4>; 300 }; 301 }; 302 303 timer { 304 compatible = "arm,armv8-timer"; 305 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 306 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 307 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 308 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 309 }; 310}; 311