1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 a55_0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 26 }; 27 }; 28 29 extal_clk: extal { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 /* This value must be overridden by the board */ 33 clock-frequency = <0>; 34 }; 35 36 extalr_clk: extalr { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 /* This value must be overridden by the board */ 40 clock-frequency = <0>; 41 }; 42 43 pmu_a55 { 44 compatible = "arm,cortex-a55-pmu"; 45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46 }; 47 48 /* External SCIF clock - to be overridden by boards that provide it */ 49 scif_clk: scif { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 53 }; 54 55 soc: soc { 56 compatible = "simple-bus"; 57 interrupt-parent = <&gic>; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 62 rwdt: watchdog@e6020000 { 63 compatible = "renesas,r8a779f0-wdt", 64 "renesas,rcar-gen4-wdt"; 65 reg = <0 0xe6020000 0 0x0c>; 66 clocks = <&cpg CPG_MOD 907>; 67 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 68 resets = <&cpg 907>; 69 status = "disabled"; 70 }; 71 72 pfc: pinctrl@e6050000 { 73 compatible = "renesas,pfc-r8a779f0"; 74 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 75 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 76 }; 77 78 cpg: clock-controller@e6150000 { 79 compatible = "renesas,r8a779f0-cpg-mssr"; 80 reg = <0 0xe6150000 0 0x4000>; 81 clocks = <&extal_clk>, <&extalr_clk>; 82 clock-names = "extal", "extalr"; 83 #clock-cells = <2>; 84 #power-domain-cells = <0>; 85 #reset-cells = <1>; 86 }; 87 88 rst: reset-controller@e6160000 { 89 compatible = "renesas,r8a779f0-rst"; 90 reg = <0 0xe6160000 0 0x4000>; 91 }; 92 93 sysc: system-controller@e6180000 { 94 compatible = "renesas,r8a779f0-sysc"; 95 reg = <0 0xe6180000 0 0x4000>; 96 #power-domain-cells = <1>; 97 }; 98 99 i2c0: i2c@e6500000 { 100 compatible = "renesas,i2c-r8a779f0", 101 "renesas,rcar-gen4-i2c"; 102 reg = <0 0xe6500000 0 0x40>; 103 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&cpg CPG_MOD 518>; 105 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 106 resets = <&cpg 518>; 107 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 108 <&dmac1 0x91>, <&dmac1 0x90>; 109 dma-names = "tx", "rx", "tx", "rx"; 110 i2c-scl-internal-delay-ns = <110>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 status = "disabled"; 114 }; 115 116 i2c1: i2c@e6508000 { 117 compatible = "renesas,i2c-r8a779f0", 118 "renesas,rcar-gen4-i2c"; 119 reg = <0 0xe6508000 0 0x40>; 120 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&cpg CPG_MOD 519>; 122 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 123 resets = <&cpg 519>; 124 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 125 <&dmac1 0x93>, <&dmac1 0x92>; 126 dma-names = "tx", "rx", "tx", "rx"; 127 i2c-scl-internal-delay-ns = <110>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 status = "disabled"; 131 }; 132 133 i2c2: i2c@e6510000 { 134 compatible = "renesas,i2c-r8a779f0", 135 "renesas,rcar-gen4-i2c"; 136 reg = <0 0xe6510000 0 0x40>; 137 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&cpg CPG_MOD 520>; 139 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 140 resets = <&cpg 520>; 141 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 142 <&dmac1 0x95>, <&dmac1 0x94>; 143 dma-names = "tx", "rx", "tx", "rx"; 144 i2c-scl-internal-delay-ns = <110>; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 status = "disabled"; 148 }; 149 150 i2c3: i2c@e66d0000 { 151 compatible = "renesas,i2c-r8a779f0", 152 "renesas,rcar-gen4-i2c"; 153 reg = <0 0xe66d0000 0 0x40>; 154 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&cpg CPG_MOD 521>; 156 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 157 resets = <&cpg 521>; 158 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 159 <&dmac1 0x97>, <&dmac1 0x96>; 160 dma-names = "tx", "rx", "tx", "rx"; 161 i2c-scl-internal-delay-ns = <110>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 status = "disabled"; 165 }; 166 167 i2c4: i2c@e66d8000 { 168 compatible = "renesas,i2c-r8a779f0", 169 "renesas,rcar-gen4-i2c"; 170 reg = <0 0xe66d8000 0 0x40>; 171 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&cpg CPG_MOD 522>; 173 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 174 resets = <&cpg 522>; 175 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 176 <&dmac1 0x99>, <&dmac1 0x98>; 177 dma-names = "tx", "rx", "tx", "rx"; 178 i2c-scl-internal-delay-ns = <110>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 status = "disabled"; 182 }; 183 184 i2c5: i2c@e66e0000 { 185 compatible = "renesas,i2c-r8a779f0", 186 "renesas,rcar-gen4-i2c"; 187 reg = <0 0xe66e0000 0 0x40>; 188 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cpg CPG_MOD 523>; 190 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 191 resets = <&cpg 523>; 192 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 193 <&dmac1 0x9b>, <&dmac1 0x9a>; 194 dma-names = "tx", "rx", "tx", "rx"; 195 i2c-scl-internal-delay-ns = <110>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 status = "disabled"; 199 }; 200 201 scif3: serial@e6c50000 { 202 compatible = "renesas,scif-r8a779f0", 203 "renesas,rcar-gen4-scif", "renesas,scif"; 204 reg = <0 0xe6c50000 0 64>; 205 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cpg CPG_MOD 704>, 207 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 208 <&scif_clk>; 209 clock-names = "fck", "brg_int", "scif_clk"; 210 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 211 resets = <&cpg 704>; 212 status = "disabled"; 213 }; 214 215 dmac0: dma-controller@e7350000 { 216 compatible = "renesas,dmac-r8a779f0", 217 "renesas,rcar-gen4-dmac"; 218 reg = <0 0xe7350000 0 0x1000>, 219 <0 0xe7300000 0 0x10000>; 220 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "error", 238 "ch0", "ch1", "ch2", "ch3", "ch4", 239 "ch5", "ch6", "ch7", "ch8", "ch9", 240 "ch10", "ch11", "ch12", "ch13", 241 "ch14", "ch15"; 242 clocks = <&cpg CPG_MOD 709>; 243 clock-names = "fck"; 244 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 245 resets = <&cpg 709>; 246 #dma-cells = <1>; 247 dma-channels = <16>; 248 }; 249 250 dmac1: dma-controller@e7351000 { 251 compatible = "renesas,dmac-r8a779f0", 252 "renesas,rcar-gen4-dmac"; 253 reg = <0 0xe7351000 0 0x1000>, 254 <0 0xe7310000 0 0x10000>; 255 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "error", 273 "ch0", "ch1", "ch2", "ch3", "ch4", 274 "ch5", "ch6", "ch7", "ch8", "ch9", 275 "ch10", "ch11", "ch12", "ch13", 276 "ch14", "ch15"; 277 clocks = <&cpg CPG_MOD 710>; 278 clock-names = "fck"; 279 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 280 resets = <&cpg 710>; 281 #dma-cells = <1>; 282 dma-channels = <16>; 283 }; 284 285 gic: interrupt-controller@f1000000 { 286 compatible = "arm,gic-v3"; 287 #interrupt-cells = <3>; 288 #address-cells = <0>; 289 interrupt-controller; 290 reg = <0x0 0xf1000000 0 0x20000>, 291 <0x0 0xf1060000 0 0x110000>; 292 interrupts = <GIC_PPI 9 293 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 294 }; 295 296 prr: chipid@fff00044 { 297 compatible = "renesas,prr"; 298 reg = <0 0xfff00044 0 4>; 299 }; 300 }; 301 302 timer { 303 compatible = "arm,armv8-timer"; 304 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 305 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 306 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 307 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 308 }; 309}; 310