1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu-map { 22 cluster0 { 23 core0 { 24 cpu = <&a55_0>; 25 }; 26 core1 { 27 cpu = <&a55_1>; 28 }; 29 }; 30 31 cluster1 { 32 core0 { 33 cpu = <&a55_2>; 34 }; 35 core1 { 36 cpu = <&a55_3>; 37 }; 38 }; 39 40 cluster2 { 41 core0 { 42 cpu = <&a55_4>; 43 }; 44 core1 { 45 cpu = <&a55_5>; 46 }; 47 }; 48 49 cluster3 { 50 core0 { 51 cpu = <&a55_6>; 52 }; 53 core1 { 54 cpu = <&a55_7>; 55 }; 56 }; 57 }; 58 59 a55_0: cpu@0 { 60 compatible = "arm,cortex-a55"; 61 reg = <0>; 62 device_type = "cpu"; 63 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 64 next-level-cache = <&L3_CA55_0>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 68 }; 69 70 a55_1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; 75 next-level-cache = <&L3_CA55_0>; 76 enable-method = "psci"; 77 cpu-idle-states = <&CPU_SLEEP_0>; 78 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 79 }; 80 81 a55_2: cpu@10000 { 82 compatible = "arm,cortex-a55"; 83 reg = <0x10000>; 84 device_type = "cpu"; 85 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; 86 next-level-cache = <&L3_CA55_1>; 87 enable-method = "psci"; 88 cpu-idle-states = <&CPU_SLEEP_0>; 89 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 90 }; 91 92 a55_3: cpu@10100 { 93 compatible = "arm,cortex-a55"; 94 reg = <0x10100>; 95 device_type = "cpu"; 96 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; 97 next-level-cache = <&L3_CA55_1>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 101 }; 102 103 a55_4: cpu@20000 { 104 compatible = "arm,cortex-a55"; 105 reg = <0x20000>; 106 device_type = "cpu"; 107 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; 108 next-level-cache = <&L3_CA55_2>; 109 enable-method = "psci"; 110 cpu-idle-states = <&CPU_SLEEP_0>; 111 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 112 }; 113 114 a55_5: cpu@20100 { 115 compatible = "arm,cortex-a55"; 116 reg = <0x20100>; 117 device_type = "cpu"; 118 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; 119 next-level-cache = <&L3_CA55_2>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP_0>; 122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 123 }; 124 125 a55_6: cpu@30000 { 126 compatible = "arm,cortex-a55"; 127 reg = <0x30000>; 128 device_type = "cpu"; 129 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; 130 next-level-cache = <&L3_CA55_3>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0>; 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 134 }; 135 136 a55_7: cpu@30100 { 137 compatible = "arm,cortex-a55"; 138 reg = <0x30100>; 139 device_type = "cpu"; 140 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; 141 next-level-cache = <&L3_CA55_3>; 142 enable-method = "psci"; 143 cpu-idle-states = <&CPU_SLEEP_0>; 144 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 145 }; 146 147 L3_CA55_0: cache-controller-0 { 148 compatible = "cache"; 149 power-domains = <&sysc R8A779F0_PD_A2E0D0>; 150 cache-unified; 151 cache-level = <3>; 152 }; 153 154 L3_CA55_1: cache-controller-1 { 155 compatible = "cache"; 156 power-domains = <&sysc R8A779F0_PD_A2E0D1>; 157 cache-unified; 158 cache-level = <3>; 159 }; 160 161 L3_CA55_2: cache-controller-2 { 162 compatible = "cache"; 163 power-domains = <&sysc R8A779F0_PD_A2E1D0>; 164 cache-unified; 165 cache-level = <3>; 166 }; 167 168 L3_CA55_3: cache-controller-3 { 169 compatible = "cache"; 170 power-domains = <&sysc R8A779F0_PD_A2E1D1>; 171 cache-unified; 172 cache-level = <3>; 173 }; 174 175 idle-states { 176 entry-method = "psci"; 177 178 CPU_SLEEP_0: cpu-sleep-0 { 179 compatible = "arm,idle-state"; 180 arm,psci-suspend-param = <0x0010000>; 181 local-timer-stop; 182 entry-latency-us = <400>; 183 exit-latency-us = <500>; 184 min-residency-us = <4000>; 185 }; 186 }; 187 }; 188 189 extal_clk: extal { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 /* This value must be overridden by the board */ 193 clock-frequency = <0>; 194 }; 195 196 extalr_clk: extalr { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 /* This value must be overridden by the board */ 200 clock-frequency = <0>; 201 }; 202 203 pmu_a55 { 204 compatible = "arm,cortex-a55-pmu"; 205 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 206 }; 207 208 psci { 209 compatible = "arm,psci-1.0", "arm,psci-0.2"; 210 method = "smc"; 211 }; 212 213 /* External SCIF clock - to be overridden by boards that provide it */ 214 scif_clk: scif { 215 compatible = "fixed-clock"; 216 #clock-cells = <0>; 217 clock-frequency = <0>; 218 }; 219 220 soc: soc { 221 compatible = "simple-bus"; 222 interrupt-parent = <&gic>; 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges; 226 227 rwdt: watchdog@e6020000 { 228 compatible = "renesas,r8a779f0-wdt", 229 "renesas,rcar-gen4-wdt"; 230 reg = <0 0xe6020000 0 0x0c>; 231 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 status = "disabled"; 236 }; 237 238 pfc: pinctrl@e6050000 { 239 compatible = "renesas,pfc-r8a779f0"; 240 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 241 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 242 }; 243 244 gpio0: gpio@e6050180 { 245 compatible = "renesas,gpio-r8a779f0", 246 "renesas,rcar-gen4-gpio"; 247 reg = <0 0xe6050180 0 0x54>; 248 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cpg CPG_MOD 915>; 250 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 251 resets = <&cpg 915>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 gpio-ranges = <&pfc 0 0 21>; 255 interrupt-controller; 256 #interrupt-cells = <2>; 257 }; 258 259 gpio1: gpio@e6050980 { 260 compatible = "renesas,gpio-r8a779f0", 261 "renesas,rcar-gen4-gpio"; 262 reg = <0 0xe6050980 0 0x54>; 263 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&cpg CPG_MOD 915>; 265 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 266 resets = <&cpg 915>; 267 gpio-controller; 268 #gpio-cells = <2>; 269 gpio-ranges = <&pfc 0 32 25>; 270 interrupt-controller; 271 #interrupt-cells = <2>; 272 }; 273 274 gpio2: gpio@e6051180 { 275 compatible = "renesas,gpio-r8a779f0", 276 "renesas,rcar-gen4-gpio"; 277 reg = <0 0xe6051180 0 0x54>; 278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cpg CPG_MOD 915>; 280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 281 resets = <&cpg 915>; 282 gpio-controller; 283 #gpio-cells = <2>; 284 gpio-ranges = <&pfc 0 64 17>; 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 }; 288 289 gpio3: gpio@e6051980 { 290 compatible = "renesas,gpio-r8a779f0", 291 "renesas,rcar-gen4-gpio"; 292 reg = <0 0xe6051980 0 0x54>; 293 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cpg CPG_MOD 915>; 295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 296 resets = <&cpg 915>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 gpio-ranges = <&pfc 0 96 19>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 }; 303 304 cmt0: timer@e60f0000 { 305 compatible = "renesas,r8a779f0-cmt0", 306 "renesas,rcar-gen4-cmt0"; 307 reg = <0 0xe60f0000 0 0x1004>; 308 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 910>; 311 clock-names = "fck"; 312 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 313 resets = <&cpg 910>; 314 status = "disabled"; 315 }; 316 317 cmt1: timer@e6130000 { 318 compatible = "renesas,r8a779f0-cmt1", 319 "renesas,rcar-gen4-cmt1"; 320 reg = <0 0xe6130000 0 0x1004>; 321 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cpg CPG_MOD 911>; 330 clock-names = "fck"; 331 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 332 resets = <&cpg 911>; 333 status = "disabled"; 334 }; 335 336 cmt2: timer@e6140000 { 337 compatible = "renesas,r8a779f0-cmt1", 338 "renesas,rcar-gen4-cmt1"; 339 reg = <0 0xe6140000 0 0x1004>; 340 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cpg CPG_MOD 912>; 349 clock-names = "fck"; 350 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 351 resets = <&cpg 912>; 352 status = "disabled"; 353 }; 354 355 cmt3: timer@e6148000 { 356 compatible = "renesas,r8a779f0-cmt1", 357 "renesas,rcar-gen4-cmt1"; 358 reg = <0 0xe6148000 0 0x1004>; 359 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cpg CPG_MOD 913>; 368 clock-names = "fck"; 369 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 370 resets = <&cpg 913>; 371 status = "disabled"; 372 }; 373 374 cpg: clock-controller@e6150000 { 375 compatible = "renesas,r8a779f0-cpg-mssr"; 376 reg = <0 0xe6150000 0 0x4000>; 377 clocks = <&extal_clk>, <&extalr_clk>; 378 clock-names = "extal", "extalr"; 379 #clock-cells = <2>; 380 #power-domain-cells = <0>; 381 #reset-cells = <1>; 382 }; 383 384 rst: reset-controller@e6160000 { 385 compatible = "renesas,r8a779f0-rst"; 386 reg = <0 0xe6160000 0 0x4000>; 387 }; 388 389 sysc: system-controller@e6180000 { 390 compatible = "renesas,r8a779f0-sysc"; 391 reg = <0 0xe6180000 0 0x4000>; 392 #power-domain-cells = <1>; 393 }; 394 395 tsc: thermal@e6198000 { 396 compatible = "renesas,r8a779f0-thermal"; 397 /* The 4th sensor is in control domain and not for Linux */ 398 reg = <0 0xe6198000 0 0x200>, 399 <0 0xe61a0000 0 0x200>, 400 <0 0xe61a8000 0 0x200>; 401 clocks = <&cpg CPG_MOD 919>; 402 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 403 resets = <&cpg 919>; 404 #thermal-sensor-cells = <1>; 405 }; 406 407 tmu0: timer@e61e0000 { 408 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 409 reg = <0 0xe61e0000 0 0x30>; 410 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&cpg CPG_MOD 713>; 414 clock-names = "fck"; 415 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 416 resets = <&cpg 713>; 417 status = "disabled"; 418 }; 419 420 tmu1: timer@e6fc0000 { 421 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 422 reg = <0 0xe6fc0000 0 0x30>; 423 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&cpg CPG_MOD 714>; 427 clock-names = "fck"; 428 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 429 resets = <&cpg 714>; 430 status = "disabled"; 431 }; 432 433 tmu2: timer@e6fd0000 { 434 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 435 reg = <0 0xe6fd0000 0 0x30>; 436 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cpg CPG_MOD 715>; 440 clock-names = "fck"; 441 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 442 resets = <&cpg 715>; 443 status = "disabled"; 444 }; 445 446 tmu3: timer@e6fe0000 { 447 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 448 reg = <0 0xe6fe0000 0 0x30>; 449 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cpg CPG_MOD 716>; 453 clock-names = "fck"; 454 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 455 resets = <&cpg 716>; 456 status = "disabled"; 457 }; 458 459 tmu4: timer@ffc00000 { 460 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 461 reg = <0 0xffc00000 0 0x30>; 462 interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cpg CPG_MOD 717>; 466 clock-names = "fck"; 467 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 468 resets = <&cpg 717>; 469 status = "disabled"; 470 }; 471 472 eth_serdes: phy@e6444000 { 473 compatible = "renesas,r8a779f0-ether-serdes"; 474 reg = <0 0xe6444000 0 0x2800>; 475 clocks = <&cpg CPG_MOD 1506>; 476 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 477 resets = <&cpg 1506>; 478 #phy-cells = <1>; 479 status = "disabled"; 480 }; 481 482 i2c0: i2c@e6500000 { 483 compatible = "renesas,i2c-r8a779f0", 484 "renesas,rcar-gen4-i2c"; 485 reg = <0 0xe6500000 0 0x40>; 486 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 518>; 488 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 489 resets = <&cpg 518>; 490 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 491 <&dmac1 0x91>, <&dmac1 0x90>; 492 dma-names = "tx", "rx", "tx", "rx"; 493 i2c-scl-internal-delay-ns = <110>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 status = "disabled"; 497 }; 498 499 i2c1: i2c@e6508000 { 500 compatible = "renesas,i2c-r8a779f0", 501 "renesas,rcar-gen4-i2c"; 502 reg = <0 0xe6508000 0 0x40>; 503 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cpg CPG_MOD 519>; 505 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 506 resets = <&cpg 519>; 507 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 508 <&dmac1 0x93>, <&dmac1 0x92>; 509 dma-names = "tx", "rx", "tx", "rx"; 510 i2c-scl-internal-delay-ns = <110>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 status = "disabled"; 514 }; 515 516 i2c2: i2c@e6510000 { 517 compatible = "renesas,i2c-r8a779f0", 518 "renesas,rcar-gen4-i2c"; 519 reg = <0 0xe6510000 0 0x40>; 520 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cpg CPG_MOD 520>; 522 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 523 resets = <&cpg 520>; 524 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 525 <&dmac1 0x95>, <&dmac1 0x94>; 526 dma-names = "tx", "rx", "tx", "rx"; 527 i2c-scl-internal-delay-ns = <110>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 i2c3: i2c@e66d0000 { 534 compatible = "renesas,i2c-r8a779f0", 535 "renesas,rcar-gen4-i2c"; 536 reg = <0 0xe66d0000 0 0x40>; 537 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&cpg CPG_MOD 521>; 539 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 540 resets = <&cpg 521>; 541 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 542 <&dmac1 0x97>, <&dmac1 0x96>; 543 dma-names = "tx", "rx", "tx", "rx"; 544 i2c-scl-internal-delay-ns = <110>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 status = "disabled"; 548 }; 549 550 i2c4: i2c@e66d8000 { 551 compatible = "renesas,i2c-r8a779f0", 552 "renesas,rcar-gen4-i2c"; 553 reg = <0 0xe66d8000 0 0x40>; 554 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 522>; 556 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 557 resets = <&cpg 522>; 558 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 559 <&dmac1 0x99>, <&dmac1 0x98>; 560 dma-names = "tx", "rx", "tx", "rx"; 561 i2c-scl-internal-delay-ns = <110>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 i2c5: i2c@e66e0000 { 568 compatible = "renesas,i2c-r8a779f0", 569 "renesas,rcar-gen4-i2c"; 570 reg = <0 0xe66e0000 0 0x40>; 571 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 523>; 573 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 574 resets = <&cpg 523>; 575 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 576 <&dmac1 0x9b>, <&dmac1 0x9a>; 577 dma-names = "tx", "rx", "tx", "rx"; 578 i2c-scl-internal-delay-ns = <110>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 hscif0: serial@e6540000 { 585 compatible = "renesas,hscif-r8a779f0", 586 "renesas,rcar-gen4-hscif", "renesas,hscif"; 587 reg = <0 0xe6540000 0 0x60>; 588 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&cpg CPG_MOD 514>, 590 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 591 <&scif_clk>; 592 clock-names = "fck", "brg_int", "scif_clk"; 593 dmas = <&dmac0 0x31>, <&dmac0 0x30>, 594 <&dmac1 0x31>, <&dmac1 0x30>; 595 dma-names = "tx", "rx", "tx", "rx"; 596 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 597 resets = <&cpg 514>; 598 status = "disabled"; 599 }; 600 601 hscif1: serial@e6550000 { 602 compatible = "renesas,hscif-r8a779f0", 603 "renesas,rcar-gen4-hscif", "renesas,hscif"; 604 reg = <0 0xe6550000 0 0x60>; 605 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&cpg CPG_MOD 515>, 607 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 608 <&scif_clk>; 609 clock-names = "fck", "brg_int", "scif_clk"; 610 dmas = <&dmac0 0x33>, <&dmac0 0x32>, 611 <&dmac1 0x33>, <&dmac1 0x32>; 612 dma-names = "tx", "rx", "tx", "rx"; 613 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 614 resets = <&cpg 515>; 615 status = "disabled"; 616 }; 617 618 hscif2: serial@e6560000 { 619 compatible = "renesas,hscif-r8a779f0", 620 "renesas,rcar-gen4-hscif", "renesas,hscif"; 621 reg = <0 0xe6560000 0 0x60>; 622 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&cpg CPG_MOD 516>, 624 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 625 <&scif_clk>; 626 clock-names = "fck", "brg_int", "scif_clk"; 627 dmas = <&dmac0 0x35>, <&dmac0 0x34>, 628 <&dmac1 0x35>, <&dmac1 0x34>; 629 dma-names = "tx", "rx", "tx", "rx"; 630 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 631 resets = <&cpg 516>; 632 status = "disabled"; 633 }; 634 635 hscif3: serial@e66a0000 { 636 compatible = "renesas,hscif-r8a779f0", 637 "renesas,rcar-gen4-hscif", "renesas,hscif"; 638 reg = <0 0xe66a0000 0 0x60>; 639 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cpg CPG_MOD 517>, 641 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 642 <&scif_clk>; 643 clock-names = "fck", "brg_int", "scif_clk"; 644 dmas = <&dmac0 0x37>, <&dmac0 0x36>, 645 <&dmac1 0x37>, <&dmac1 0x36>; 646 dma-names = "tx", "rx", "tx", "rx"; 647 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 648 resets = <&cpg 517>; 649 status = "disabled"; 650 }; 651 652 ufs: ufs@e6860000 { 653 compatible = "renesas,r8a779f0-ufs"; 654 reg = <0 0xe6860000 0 0x100>; 655 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; 657 clock-names = "fck", "ref_clk"; 658 freq-table-hz = <200000000 200000000>, <38400000 38400000>; 659 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 660 resets = <&cpg 1514>; 661 status = "disabled"; 662 }; 663 664 rswitch: ethernet@e6880000 { 665 compatible = "renesas,r8a779f0-ether-switch"; 666 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; 667 reg-names = "base", "secure_base"; 668 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "mfwd_error", "race_error", 716 "coma_error", "gwca0_error", 717 "gwca1_error", "etha0_error", 718 "etha1_error", "etha2_error", 719 "gptp0_status", "gptp1_status", 720 "mfwd_status", "race_status", 721 "coma_status", "gwca0_status", 722 "gwca1_status", "etha0_status", 723 "etha1_status", "etha2_status", 724 "rmac0_status", "rmac1_status", 725 "rmac2_status", 726 "gwca0_rxtx0", "gwca0_rxtx1", 727 "gwca0_rxtx2", "gwca0_rxtx3", 728 "gwca0_rxtx4", "gwca0_rxtx5", 729 "gwca0_rxtx6", "gwca0_rxtx7", 730 "gwca1_rxtx0", "gwca1_rxtx1", 731 "gwca1_rxtx2", "gwca1_rxtx3", 732 "gwca1_rxtx4", "gwca1_rxtx5", 733 "gwca1_rxtx6", "gwca1_rxtx7", 734 "gwca0_rxts0", "gwca0_rxts1", 735 "gwca1_rxts0", "gwca1_rxts1", 736 "rmac0_mdio", "rmac1_mdio", 737 "rmac2_mdio", 738 "rmac0_phy", "rmac1_phy", 739 "rmac2_phy"; 740 clocks = <&cpg CPG_MOD 1505>; 741 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 742 resets = <&cpg 1505>; 743 status = "disabled"; 744 745 ethernet-ports { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 749 port@0 { 750 reg = <0>; 751 phys = <ð_serdes 0>; 752 }; 753 port@1 { 754 reg = <1>; 755 phys = <ð_serdes 1>; 756 }; 757 port@2 { 758 reg = <2>; 759 phys = <ð_serdes 2>; 760 }; 761 }; 762 }; 763 764 scif0: serial@e6e60000 { 765 compatible = "renesas,scif-r8a779f0", 766 "renesas,rcar-gen4-scif", "renesas,scif"; 767 reg = <0 0xe6e60000 0 64>; 768 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&cpg CPG_MOD 702>, 770 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 771 <&scif_clk>; 772 clock-names = "fck", "brg_int", "scif_clk"; 773 dmas = <&dmac0 0x51>, <&dmac0 0x50>, 774 <&dmac1 0x51>, <&dmac1 0x50>; 775 dma-names = "tx", "rx", "tx", "rx"; 776 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 777 resets = <&cpg 702>; 778 status = "disabled"; 779 }; 780 781 scif1: serial@e6e68000 { 782 compatible = "renesas,scif-r8a779f0", 783 "renesas,rcar-gen4-scif", "renesas,scif"; 784 reg = <0 0xe6e68000 0 64>; 785 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&cpg CPG_MOD 703>, 787 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 788 <&scif_clk>; 789 clock-names = "fck", "brg_int", "scif_clk"; 790 dmas = <&dmac0 0x53>, <&dmac0 0x52>, 791 <&dmac1 0x53>, <&dmac1 0x52>; 792 dma-names = "tx", "rx", "tx", "rx"; 793 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 794 resets = <&cpg 703>; 795 status = "disabled"; 796 }; 797 798 scif3: serial@e6c50000 { 799 compatible = "renesas,scif-r8a779f0", 800 "renesas,rcar-gen4-scif", "renesas,scif"; 801 reg = <0 0xe6c50000 0 64>; 802 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&cpg CPG_MOD 704>, 804 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 805 <&scif_clk>; 806 clock-names = "fck", "brg_int", "scif_clk"; 807 dmas = <&dmac0 0x57>, <&dmac0 0x56>, 808 <&dmac1 0x57>, <&dmac1 0x56>; 809 dma-names = "tx", "rx", "tx", "rx"; 810 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 811 resets = <&cpg 704>; 812 status = "disabled"; 813 }; 814 815 scif4: serial@e6c40000 { 816 compatible = "renesas,scif-r8a779f0", 817 "renesas,rcar-gen4-scif", "renesas,scif"; 818 reg = <0 0xe6c40000 0 64>; 819 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&cpg CPG_MOD 705>, 821 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 822 <&scif_clk>; 823 clock-names = "fck", "brg_int", "scif_clk"; 824 dmas = <&dmac0 0x59>, <&dmac0 0x58>, 825 <&dmac1 0x59>, <&dmac1 0x58>; 826 dma-names = "tx", "rx", "tx", "rx"; 827 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 828 resets = <&cpg 705>; 829 status = "disabled"; 830 }; 831 832 msiof0: spi@e6e90000 { 833 compatible = "renesas,msiof-r8a779f0", 834 "renesas,rcar-gen4-msiof"; 835 reg = <0 0xe6e90000 0 0x0064>; 836 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&cpg CPG_MOD 618>; 838 dmas = <&dmac0 0x41>, <&dmac0 0x40>, 839 <&dmac1 0x41>, <&dmac1 0x40>; 840 dma-names = "tx", "rx", "tx", "rx"; 841 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 842 resets = <&cpg 618>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 status = "disabled"; 846 }; 847 848 msiof1: spi@e6ea0000 { 849 compatible = "renesas,msiof-r8a779f0", 850 "renesas,rcar-gen4-msiof"; 851 reg = <0 0xe6ea0000 0 0x0064>; 852 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&cpg CPG_MOD 619>; 854 dmas = <&dmac0 0x43>, <&dmac0 0x42>, 855 <&dmac1 0x43>, <&dmac1 0x42>; 856 dma-names = "tx", "rx", "tx", "rx"; 857 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 858 resets = <&cpg 619>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 }; 863 864 msiof2: spi@e6c00000 { 865 compatible = "renesas,msiof-r8a779f0", 866 "renesas,rcar-gen4-msiof"; 867 reg = <0 0xe6c00000 0 0x0064>; 868 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cpg CPG_MOD 620>; 870 dmas = <&dmac0 0x45>, <&dmac0 0x44>, 871 <&dmac1 0x45>, <&dmac1 0x44>; 872 dma-names = "tx", "rx", "tx", "rx"; 873 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 874 resets = <&cpg 620>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 status = "disabled"; 878 }; 879 880 msiof3: spi@e6c10000 { 881 compatible = "renesas,msiof-r8a779f0", 882 "renesas,rcar-gen4-msiof"; 883 reg = <0 0xe6c10000 0 0x0064>; 884 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cpg CPG_MOD 621>; 886 dmas = <&dmac0 0x47>, <&dmac0 0x46>, 887 <&dmac1 0x47>, <&dmac1 0x46>; 888 dma-names = "tx", "rx", "tx", "rx"; 889 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 890 resets = <&cpg 621>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 status = "disabled"; 894 }; 895 896 dmac0: dma-controller@e7350000 { 897 compatible = "renesas,dmac-r8a779f0", 898 "renesas,rcar-gen4-dmac"; 899 reg = <0 0xe7350000 0 0x1000>, 900 <0 0xe7300000 0 0x10000>; 901 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 918 interrupt-names = "error", 919 "ch0", "ch1", "ch2", "ch3", "ch4", 920 "ch5", "ch6", "ch7", "ch8", "ch9", 921 "ch10", "ch11", "ch12", "ch13", 922 "ch14", "ch15"; 923 clocks = <&cpg CPG_MOD 709>; 924 clock-names = "fck"; 925 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 926 resets = <&cpg 709>; 927 #dma-cells = <1>; 928 dma-channels = <16>; 929 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 930 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 931 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 932 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 933 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 934 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 935 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 936 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 937 }; 938 939 dmac1: dma-controller@e7351000 { 940 compatible = "renesas,dmac-r8a779f0", 941 "renesas,rcar-gen4-dmac"; 942 reg = <0 0xe7351000 0 0x1000>, 943 <0 0xe7310000 0 0x10000>; 944 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 961 interrupt-names = "error", 962 "ch0", "ch1", "ch2", "ch3", "ch4", 963 "ch5", "ch6", "ch7", "ch8", "ch9", 964 "ch10", "ch11", "ch12", "ch13", 965 "ch14", "ch15"; 966 clocks = <&cpg CPG_MOD 710>; 967 clock-names = "fck"; 968 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 969 resets = <&cpg 710>; 970 #dma-cells = <1>; 971 dma-channels = <16>; 972 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 973 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 974 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 975 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 976 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 977 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 978 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 979 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 980 }; 981 982 mmc0: mmc@ee140000 { 983 compatible = "renesas,sdhi-r8a779f0", 984 "renesas,rcar-gen4-sdhi"; 985 reg = <0 0xee140000 0 0x2000>; 986 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; 988 clock-names = "core", "clkh"; 989 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 990 resets = <&cpg 706>; 991 max-frequency = <200000000>; 992 status = "disabled"; 993 }; 994 995 ipmmu_rt0: iommu@ee480000 { 996 compatible = "renesas,ipmmu-r8a779f0", 997 "renesas,rcar-gen4-ipmmu-vmsa"; 998 reg = <0 0xee480000 0 0x20000>; 999 renesas,ipmmu-main = <&ipmmu_mm 10>; 1000 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1001 #iommu-cells = <1>; 1002 }; 1003 1004 ipmmu_rt1: iommu@ee4c0000 { 1005 compatible = "renesas,ipmmu-r8a779f0", 1006 "renesas,rcar-gen4-ipmmu-vmsa"; 1007 reg = <0 0xee4c0000 0 0x20000>; 1008 renesas,ipmmu-main = <&ipmmu_mm 19>; 1009 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1010 #iommu-cells = <1>; 1011 }; 1012 1013 ipmmu_ds0: iommu@eed00000 { 1014 compatible = "renesas,ipmmu-r8a779f0", 1015 "renesas,rcar-gen4-ipmmu-vmsa"; 1016 reg = <0 0xeed00000 0 0x20000>; 1017 renesas,ipmmu-main = <&ipmmu_mm 0>; 1018 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1019 #iommu-cells = <1>; 1020 }; 1021 1022 ipmmu_hc: iommu@eed40000 { 1023 compatible = "renesas,ipmmu-r8a779f0", 1024 "renesas,rcar-gen4-ipmmu-vmsa"; 1025 reg = <0 0xeed40000 0 0x20000>; 1026 renesas,ipmmu-main = <&ipmmu_mm 2>; 1027 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1028 #iommu-cells = <1>; 1029 }; 1030 1031 ipmmu_mm: iommu@eefc0000 { 1032 compatible = "renesas,ipmmu-r8a779f0", 1033 "renesas,rcar-gen4-ipmmu-vmsa"; 1034 reg = <0 0xeefc0000 0 0x20000>; 1035 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1037 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1038 #iommu-cells = <1>; 1039 }; 1040 1041 gic: interrupt-controller@f1000000 { 1042 compatible = "arm,gic-v3"; 1043 #interrupt-cells = <3>; 1044 #address-cells = <0>; 1045 interrupt-controller; 1046 reg = <0x0 0xf1000000 0 0x20000>, 1047 <0x0 0xf1060000 0 0x110000>; 1048 interrupts = <GIC_PPI 9 1049 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1050 }; 1051 1052 prr: chipid@fff00044 { 1053 compatible = "renesas,prr"; 1054 reg = <0 0xfff00044 0 4>; 1055 }; 1056 }; 1057 1058 thermal-zones { 1059 sensor_thermal1: sensor1-thermal { 1060 polling-delay-passive = <250>; 1061 polling-delay = <1000>; 1062 thermal-sensors = <&tsc 0>; 1063 1064 trips { 1065 sensor1_crit: sensor1-crit { 1066 temperature = <120000>; 1067 hysteresis = <1000>; 1068 type = "critical"; 1069 }; 1070 }; 1071 }; 1072 1073 sensor_thermal2: sensor2-thermal { 1074 polling-delay-passive = <250>; 1075 polling-delay = <1000>; 1076 thermal-sensors = <&tsc 1>; 1077 1078 trips { 1079 sensor2_crit: sensor2-crit { 1080 temperature = <120000>; 1081 hysteresis = <1000>; 1082 type = "critical"; 1083 }; 1084 }; 1085 }; 1086 1087 sensor_thermal3: sensor3-thermal { 1088 polling-delay-passive = <250>; 1089 polling-delay = <1000>; 1090 thermal-sensors = <&tsc 2>; 1091 1092 trips { 1093 sensor3_crit: sensor3-crit { 1094 temperature = <120000>; 1095 hysteresis = <1000>; 1096 type = "critical"; 1097 }; 1098 }; 1099 }; 1100 }; 1101 1102 timer { 1103 compatible = "arm,armv8-timer"; 1104 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1105 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1106 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1107 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1108 }; 1109 1110 ufs30_clk: ufs30-clk { 1111 compatible = "fixed-clock"; 1112 #clock-cells = <0>; 1113 /* This value must be overridden by the board */ 1114 clock-frequency = <0>; 1115 }; 1116}; 1117