1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 a55_0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 26 }; 27 }; 28 29 extal_clk: extal { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 /* This value must be overridden by the board */ 33 clock-frequency = <0>; 34 }; 35 36 extalr_clk: extalr { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 /* This value must be overridden by the board */ 40 clock-frequency = <0>; 41 }; 42 43 pmu_a55 { 44 compatible = "arm,cortex-a55-pmu"; 45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46 }; 47 48 /* External SCIF clock - to be overridden by boards that provide it */ 49 scif_clk: scif { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 53 }; 54 55 soc: soc { 56 compatible = "simple-bus"; 57 interrupt-parent = <&gic>; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 62 cpg: clock-controller@e6150000 { 63 compatible = "renesas,r8a779f0-cpg-mssr"; 64 reg = <0 0xe6150000 0 0x4000>; 65 clocks = <&extal_clk>, <&extalr_clk>; 66 clock-names = "extal", "extalr"; 67 #clock-cells = <2>; 68 #power-domain-cells = <0>; 69 #reset-cells = <1>; 70 }; 71 72 rst: reset-controller@e6160000 { 73 compatible = "renesas,r8a779f0-rst"; 74 reg = <0 0xe6160000 0 0x4000>; 75 }; 76 77 sysc: system-controller@e6180000 { 78 compatible = "renesas,r8a779f0-sysc"; 79 reg = <0 0xe6180000 0 0x4000>; 80 #power-domain-cells = <1>; 81 }; 82 83 scif3: serial@e6c50000 { 84 compatible = "renesas,scif-r8a779f0", 85 "renesas,rcar-gen4-scif", "renesas,scif"; 86 reg = <0 0xe6c50000 0 64>; 87 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 88 clocks = <&cpg CPG_MOD 704>, 89 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 90 <&scif_clk>; 91 clock-names = "fck", "brg_int", "scif_clk"; 92 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 93 resets = <&cpg 704>; 94 status = "disabled"; 95 }; 96 97 dmac0: dma-controller@e7350000 { 98 compatible = "renesas,dmac-r8a779f0", 99 "renesas,rcar-gen4-dmac"; 100 reg = <0 0xe7350000 0 0x1000>, 101 <0 0xe7300000 0 0x10000>; 102 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-names = "error", 120 "ch0", "ch1", "ch2", "ch3", "ch4", 121 "ch5", "ch6", "ch7", "ch8", "ch9", 122 "ch10", "ch11", "ch12", "ch13", 123 "ch14", "ch15"; 124 clocks = <&cpg CPG_MOD 709>; 125 clock-names = "fck"; 126 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 127 resets = <&cpg 709>; 128 #dma-cells = <1>; 129 dma-channels = <16>; 130 }; 131 132 dmac1: dma-controller@e7351000 { 133 compatible = "renesas,dmac-r8a779f0", 134 "renesas,rcar-gen4-dmac"; 135 reg = <0 0xe7351000 0 0x1000>, 136 <0 0xe7310000 0 0x10000>; 137 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 154 interrupt-names = "error", 155 "ch0", "ch1", "ch2", "ch3", "ch4", 156 "ch5", "ch6", "ch7", "ch8", "ch9", 157 "ch10", "ch11", "ch12", "ch13", 158 "ch14", "ch15"; 159 clocks = <&cpg CPG_MOD 710>; 160 clock-names = "fck"; 161 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 162 resets = <&cpg 710>; 163 #dma-cells = <1>; 164 dma-channels = <16>; 165 }; 166 167 gic: interrupt-controller@f1000000 { 168 compatible = "arm,gic-v3"; 169 #interrupt-cells = <3>; 170 #address-cells = <0>; 171 interrupt-controller; 172 reg = <0x0 0xf1000000 0 0x20000>, 173 <0x0 0xf1060000 0 0x110000>; 174 interrupts = <GIC_PPI 9 175 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 176 }; 177 178 prr: chipid@fff00044 { 179 compatible = "renesas,prr"; 180 reg = <0 0xfff00044 0 4>; 181 }; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 187 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 188 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 189 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 190 }; 191}; 192