1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Richard Acayan. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/phy/phy-qcom-qusb2.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { }; 26 27 chosen { }; 28 29 cpus { 30 #address-cells = <2>; 31 #size-cells = <0>; 32 33 CPU0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "qcom,kryo360"; 36 reg = <0x0 0x0>; 37 enable-method = "psci"; 38 power-domains = <&CPU_PD0>; 39 power-domain-names = "psci"; 40 next-level-cache = <&L2_0>; 41 L2_0: l2-cache { 42 compatible = "cache"; 43 next-level-cache = <&L3_0>; 44 L3_0: l3-cache { 45 compatible = "cache"; 46 }; 47 }; 48 }; 49 50 CPU1: cpu@100 { 51 device_type = "cpu"; 52 compatible = "qcom,kryo360"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 power-domains = <&CPU_PD1>; 56 power-domain-names = "psci"; 57 next-level-cache = <&L2_100>; 58 L2_100: l2-cache { 59 compatible = "cache"; 60 next-level-cache = <&L3_0>; 61 }; 62 }; 63 64 CPU2: cpu@200 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo360"; 67 reg = <0x0 0x200>; 68 enable-method = "psci"; 69 power-domains = <&CPU_PD2>; 70 power-domain-names = "psci"; 71 next-level-cache = <&L2_200>; 72 L2_200: l2-cache { 73 compatible = "cache"; 74 next-level-cache = <&L3_0>; 75 }; 76 }; 77 78 CPU3: cpu@300 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo360"; 81 reg = <0x0 0x300>; 82 enable-method = "psci"; 83 power-domains = <&CPU_PD3>; 84 power-domain-names = "psci"; 85 next-level-cache = <&L2_300>; 86 L2_300: l2-cache { 87 compatible = "cache"; 88 next-level-cache = <&L3_0>; 89 }; 90 }; 91 92 CPU4: cpu@400 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo360"; 95 reg = <0x0 0x400>; 96 enable-method = "psci"; 97 power-domains = <&CPU_PD4>; 98 power-domain-names = "psci"; 99 next-level-cache = <&L2_400>; 100 L2_400: l2-cache { 101 compatible = "cache"; 102 next-level-cache = <&L3_0>; 103 }; 104 }; 105 106 CPU5: cpu@500 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo360"; 109 reg = <0x0 0x500>; 110 enable-method = "psci"; 111 power-domains = <&CPU_PD5>; 112 power-domain-names = "psci"; 113 next-level-cache = <&L2_500>; 114 L2_500: l2-cache { 115 compatible = "cache"; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU6: cpu@600 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo360"; 123 reg = <0x0 0x600>; 124 enable-method = "psci"; 125 power-domains = <&CPU_PD6>; 126 power-domain-names = "psci"; 127 next-level-cache = <&L2_600>; 128 L2_600: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU7: cpu@700 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo360"; 137 reg = <0x0 0x700>; 138 enable-method = "psci"; 139 power-domains = <&CPU_PD7>; 140 power-domain-names = "psci"; 141 next-level-cache = <&L2_700>; 142 L2_700: l2-cache { 143 compatible = "cache"; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 cpu-map { 149 cluster0 { 150 core0 { 151 cpu = <&CPU0>; 152 }; 153 154 core1 { 155 cpu = <&CPU1>; 156 }; 157 158 core2 { 159 cpu = <&CPU2>; 160 }; 161 162 core3 { 163 cpu = <&CPU3>; 164 }; 165 166 core4 { 167 cpu = <&CPU4>; 168 }; 169 170 core5 { 171 cpu = <&CPU5>; 172 }; 173 174 core6 { 175 cpu = <&CPU6>; 176 }; 177 178 core7 { 179 cpu = <&CPU7>; 180 }; 181 }; 182 }; 183 184 idle-states { 185 entry-method = "psci"; 186 187 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 188 compatible = "arm,idle-state"; 189 idle-state-name = "little-rail-power-collapse"; 190 arm,psci-suspend-param = <0x40000004>; 191 entry-latency-us = <702>; 192 exit-latency-us = <915>; 193 min-residency-us = <1617>; 194 local-timer-stop; 195 }; 196 197 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 198 compatible = "arm,idle-state"; 199 idle-state-name = "big-rail-power-collapse"; 200 arm,psci-suspend-param = <0x40000004>; 201 entry-latency-us = <526>; 202 exit-latency-us = <1854>; 203 min-residency-us = <2380>; 204 local-timer-stop; 205 }; 206 }; 207 208 domain-idle-states { 209 CLUSTER_SLEEP_0: cluster-sleep-0 { 210 compatible = "domain-idle-state"; 211 arm,psci-suspend-param = <0x4100c244>; 212 entry-latency-us = <3263>; 213 exit-latency-us = <6562>; 214 min-residency-us = <9825>; 215 }; 216 }; 217 }; 218 219 firmware { 220 scm { 221 compatible = "qcom,scm-sdm670", "qcom,scm"; 222 }; 223 }; 224 225 memory@80000000 { 226 device_type = "memory"; 227 /* We expect the bootloader to fill in the size */ 228 reg = <0x0 0x80000000 0x0 0x0>; 229 }; 230 231 psci { 232 compatible = "arm,psci-1.0"; 233 method = "smc"; 234 235 CPU_PD0: power-domain-cpu0 { 236 #power-domain-cells = <0>; 237 power-domains = <&CLUSTER_PD>; 238 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 239 }; 240 241 CPU_PD1: power-domain-cpu1 { 242 #power-domain-cells = <0>; 243 power-domains = <&CLUSTER_PD>; 244 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 245 }; 246 247 CPU_PD2: power-domain-cpu2 { 248 #power-domain-cells = <0>; 249 power-domains = <&CLUSTER_PD>; 250 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 251 }; 252 253 CPU_PD3: power-domain-cpu3 { 254 #power-domain-cells = <0>; 255 power-domains = <&CLUSTER_PD>; 256 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 257 }; 258 259 CPU_PD4: power-domain-cpu4 { 260 #power-domain-cells = <0>; 261 power-domains = <&CLUSTER_PD>; 262 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 263 }; 264 265 CPU_PD5: power-domain-cpu5 { 266 #power-domain-cells = <0>; 267 power-domains = <&CLUSTER_PD>; 268 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 269 }; 270 271 CPU_PD6: power-domain-cpu6 { 272 #power-domain-cells = <0>; 273 power-domains = <&CLUSTER_PD>; 274 domain-idle-states = <&BIG_CPU_SLEEP_0>; 275 }; 276 277 CPU_PD7: power-domain-cpu7 { 278 #power-domain-cells = <0>; 279 power-domains = <&CLUSTER_PD>; 280 domain-idle-states = <&BIG_CPU_SLEEP_0>; 281 }; 282 283 CLUSTER_PD: power-domain-cluster { 284 #power-domain-cells = <0>; 285 domain-idle-states = <&CLUSTER_SLEEP_0>; 286 }; 287 }; 288 289 reserved-memory { 290 #address-cells = <2>; 291 #size-cells = <2>; 292 ranges; 293 294 hyp_mem: hyp-mem@85700000 { 295 reg = <0 0x85700000 0 0x600000>; 296 no-map; 297 }; 298 299 xbl_mem: xbl-mem@85e00000 { 300 reg = <0 0x85e00000 0 0x100000>; 301 no-map; 302 }; 303 304 aop_mem: aop-mem@85fc0000 { 305 reg = <0 0x85fc0000 0 0x20000>; 306 no-map; 307 }; 308 309 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 310 compatible = "qcom,cmd-db"; 311 reg = <0 0x85fe0000 0 0x20000>; 312 no-map; 313 }; 314 315 camera_mem: camera-mem@8ab00000 { 316 reg = <0 0x8ab00000 0 0x500000>; 317 no-map; 318 }; 319 320 mpss_region: mpss@8b000000 { 321 reg = <0 0x8b000000 0 0x7e00000>; 322 no-map; 323 }; 324 325 venus_mem: venus@92e00000 { 326 reg = <0 0x92e00000 0 0x500000>; 327 no-map; 328 }; 329 330 wlan_msa_mem: wlan-msa@93300000 { 331 reg = <0 0x93300000 0 0x100000>; 332 no-map; 333 }; 334 335 cdsp_mem: cdsp@93400000 { 336 reg = <0 0x93400000 0 0x800000>; 337 no-map; 338 }; 339 340 mba_region: mba@93c00000 { 341 reg = <0 0x93c00000 0 0x200000>; 342 no-map; 343 }; 344 345 adsp_mem: adsp@93e00000 { 346 reg = <0 0x93e00000 0 0x1e00000>; 347 no-map; 348 }; 349 350 ipa_fw_mem: ipa-fw@95c00000 { 351 reg = <0 0x95c00000 0 0x10000>; 352 no-map; 353 }; 354 355 ipa_gsi_mem: ipa-gsi@95c10000 { 356 reg = <0 0x95c10000 0 0x5000>; 357 no-map; 358 }; 359 360 gpu_mem: gpu@95c15000 { 361 reg = <0 0x95c15000 0 0x2000>; 362 no-map; 363 }; 364 365 spss_mem: spss@97b00000 { 366 reg = <0 0x97b00000 0 0x100000>; 367 no-map; 368 }; 369 370 qseecom_mem: qseecom@9e400000 { 371 reg = <0 0x9e400000 0 0x1400000>; 372 no-map; 373 }; 374 }; 375 376 timer { 377 compatible = "arm,armv8-timer"; 378 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 379 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 380 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 381 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 382 }; 383 384 soc: soc@0 { 385 #address-cells = <2>; 386 #size-cells = <2>; 387 ranges = <0 0 0 0 0x10 0>; 388 dma-ranges = <0 0 0 0 0x10 0>; 389 compatible = "simple-bus"; 390 391 gcc: clock-controller@100000 { 392 compatible = "qcom,gcc-sdm670"; 393 reg = <0 0x00100000 0 0x1f0000>; 394 clocks = <&rpmhcc RPMH_CXO_CLK>, 395 <&rpmhcc RPMH_CXO_CLK_A>, 396 <&sleep_clk>; 397 clock-names = "bi_tcxo", 398 "bi_tcxo_ao", 399 "sleep_clk"; 400 #clock-cells = <1>; 401 #reset-cells = <1>; 402 #power-domain-cells = <1>; 403 }; 404 405 qfprom: qfprom@784000 { 406 compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; 407 reg = <0 0x00784000 0 0x1000>; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 411 qusb2_hstx_trim: hstx-trim@1eb { 412 reg = <0x1eb 0x1>; 413 bits = <1 4>; 414 }; 415 }; 416 417 sdhc_1: mmc@7c4000 { 418 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; 419 reg = <0 0x007c4000 0 0x1000>, 420 <0 0x007c5000 0 0x1000>, 421 <0 0x007c8000 0 0x8000>; 422 reg-names = "hc", "cqhci", "ice"; 423 424 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "hc_irq", "pwr_irq"; 427 428 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 429 <&gcc GCC_SDCC1_APPS_CLK>, 430 <&rpmhcc RPMH_CXO_CLK>, 431 <&gcc GCC_SDCC1_ICE_CORE_CLK>, 432 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 433 clock-names = "iface", "core", "xo", "ice", "bus"; 434 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, 435 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; 436 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 437 operating-points-v2 = <&sdhc1_opp_table>; 438 439 iommus = <&apps_smmu 0x140 0xf>; 440 441 pinctrl-names = "default", "sleep"; 442 pinctrl-0 = <&sdc1_state_on>; 443 pinctrl-1 = <&sdc1_state_off>; 444 power-domains = <&rpmhpd SDM670_CX>; 445 446 bus-width = <8>; 447 non-removable; 448 449 status = "disabled"; 450 451 sdhc1_opp_table: opp-table { 452 compatible = "operating-points-v2"; 453 454 opp-20000000 { 455 opp-hz = /bits/ 64 <20000000>; 456 required-opps = <&rpmhpd_opp_min_svs>; 457 opp-peak-kBps = <80000 80000>; 458 opp-avg-kBps = <52286 80000>; 459 }; 460 461 opp-50000000 { 462 opp-hz = /bits/ 64 <50000000>; 463 required-opps = <&rpmhpd_opp_low_svs>; 464 opp-peak-kBps = <200000 100000>; 465 opp-avg-kBps = <130718 100000>; 466 }; 467 468 opp-100000000 { 469 opp-hz = /bits/ 64 <100000000>; 470 required-opps = <&rpmhpd_opp_svs>; 471 opp-peak-kBps = <200000 130000>; 472 opp-avg-kBps = <130718 130000>; 473 }; 474 475 opp-384000000 { 476 opp-hz = /bits/ 64 <384000000>; 477 required-opps = <&rpmhpd_opp_nom>; 478 opp-peak-kBps = <4096000 4096000>; 479 opp-avg-kBps = <1338562 1338562>; 480 }; 481 }; 482 }; 483 484 gpi_dma0: dma-controller@800000 { 485 #dma-cells = <3>; 486 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 487 reg = <0 0x00800000 0 0x60000>; 488 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 501 dma-channels = <13>; 502 dma-channel-mask = <0xfa>; 503 iommus = <&apps_smmu 0x16 0x0>; 504 status = "disabled"; 505 }; 506 507 qupv3_id_0: geniqup@8c0000 { 508 compatible = "qcom,geni-se-qup"; 509 reg = <0 0x008c0000 0 0x6000>; 510 clock-names = "m-ahb", "s-ahb"; 511 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 512 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 513 iommus = <&apps_smmu 0x3 0x0>; 514 #address-cells = <2>; 515 #size-cells = <2>; 516 ranges; 517 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; 518 interconnect-names = "qup-core"; 519 status = "disabled"; 520 521 i2c0: i2c@880000 { 522 compatible = "qcom,geni-i2c"; 523 reg = <0 0x00880000 0 0x4000>; 524 clock-names = "se"; 525 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&qup_i2c0_default>; 528 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 power-domains = <&rpmhpd SDM670_CX>; 532 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 533 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 534 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 535 interconnect-names = "qup-core", "qup-config", "qup-memory"; 536 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 537 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 538 dma-names = "tx", "rx"; 539 status = "disabled"; 540 }; 541 542 i2c1: i2c@884000 { 543 compatible = "qcom,geni-i2c"; 544 reg = <0 0x00884000 0 0x4000>; 545 clock-names = "se"; 546 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&qup_i2c1_default>; 549 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 power-domains = <&rpmhpd SDM670_CX>; 553 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 554 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 555 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 556 interconnect-names = "qup-core", "qup-config", "qup-memory"; 557 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 558 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 559 dma-names = "tx", "rx"; 560 status = "disabled"; 561 }; 562 563 i2c2: i2c@888000 { 564 compatible = "qcom,geni-i2c"; 565 reg = <0 0x00888000 0 0x4000>; 566 clock-names = "se"; 567 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&qup_i2c2_default>; 570 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 power-domains = <&rpmhpd SDM670_CX>; 574 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 575 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 576 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 578 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 579 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 580 dma-names = "tx", "rx"; 581 status = "disabled"; 582 }; 583 584 i2c3: i2c@88c000 { 585 compatible = "qcom,geni-i2c"; 586 reg = <0 0x0088c000 0 0x4000>; 587 clock-names = "se"; 588 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&qup_i2c3_default>; 591 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 power-domains = <&rpmhpd SDM670_CX>; 595 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 596 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 597 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 598 interconnect-names = "qup-core", "qup-config", "qup-memory"; 599 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 600 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 601 dma-names = "tx", "rx"; 602 status = "disabled"; 603 }; 604 605 i2c4: i2c@890000 { 606 compatible = "qcom,geni-i2c"; 607 reg = <0 0x00890000 0 0x4000>; 608 clock-names = "se"; 609 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&qup_i2c4_default>; 612 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 power-domains = <&rpmhpd SDM670_CX>; 616 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 617 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 618 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 619 interconnect-names = "qup-core", "qup-config", "qup-memory"; 620 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 621 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 622 dma-names = "tx", "rx"; 623 status = "disabled"; 624 }; 625 626 i2c5: i2c@894000 { 627 compatible = "qcom,geni-i2c"; 628 reg = <0 0x00894000 0 0x4000>; 629 clock-names = "se"; 630 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&qup_i2c5_default>; 633 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 power-domains = <&rpmhpd SDM670_CX>; 637 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 638 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 639 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 640 interconnect-names = "qup-core", "qup-config", "qup-memory"; 641 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 642 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 643 dma-names = "tx", "rx"; 644 status = "disabled"; 645 }; 646 647 i2c6: i2c@898000 { 648 compatible = "qcom,geni-i2c"; 649 reg = <0 0x00898000 0 0x4000>; 650 clock-names = "se"; 651 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&qup_i2c6_default>; 654 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 power-domains = <&rpmhpd SDM670_CX>; 658 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 659 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 660 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 661 interconnect-names = "qup-core", "qup-config", "qup-memory"; 662 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 663 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 664 dma-names = "tx", "rx"; 665 status = "disabled"; 666 }; 667 668 i2c7: i2c@89c000 { 669 compatible = "qcom,geni-i2c"; 670 reg = <0 0x0089c000 0 0x4000>; 671 clock-names = "se"; 672 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&qup_i2c7_default>; 675 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 power-domains = <&rpmhpd SDM670_CX>; 679 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 680 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 681 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 682 interconnect-names = "qup-core", "qup-config", "qup-memory"; 683 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 684 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 685 dma-names = "tx", "rx"; 686 status = "disabled"; 687 }; 688 }; 689 690 gpi_dma1: dma-controller@a00000 { 691 #dma-cells = <3>; 692 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 693 reg = <0 0x00a00000 0 0x60000>; 694 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 707 dma-channels = <13>; 708 dma-channel-mask = <0xfa>; 709 iommus = <&apps_smmu 0x6d6 0x0>; 710 status = "disabled"; 711 }; 712 713 qupv3_id_1: geniqup@ac0000 { 714 compatible = "qcom,geni-se-qup"; 715 reg = <0 0x00ac0000 0 0x6000>; 716 clock-names = "m-ahb", "s-ahb"; 717 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 718 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 719 iommus = <&apps_smmu 0x6c3 0x0>; 720 #address-cells = <2>; 721 #size-cells = <2>; 722 ranges; 723 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; 724 interconnect-names = "qup-core"; 725 status = "disabled"; 726 727 i2c8: i2c@a80000 { 728 compatible = "qcom,geni-i2c"; 729 reg = <0 0x00a80000 0 0x4000>; 730 clock-names = "se"; 731 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&qup_i2c8_default>; 734 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 power-domains = <&rpmhpd SDM670_CX>; 738 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 739 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 740 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 741 interconnect-names = "qup-core", "qup-config", "qup-memory"; 742 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 743 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 744 dma-names = "tx", "rx"; 745 status = "disabled"; 746 }; 747 748 i2c9: i2c@a84000 { 749 compatible = "qcom,geni-i2c"; 750 reg = <0 0x00a84000 0 0x4000>; 751 clock-names = "se"; 752 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 753 pinctrl-names = "default"; 754 pinctrl-0 = <&qup_i2c9_default>; 755 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 power-domains = <&rpmhpd SDM670_CX>; 759 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 760 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 761 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 762 interconnect-names = "qup-core", "qup-config", "qup-memory"; 763 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 764 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 765 dma-names = "tx", "rx"; 766 status = "disabled"; 767 }; 768 769 i2c10: i2c@a88000 { 770 compatible = "qcom,geni-i2c"; 771 reg = <0 0x00a88000 0 0x4000>; 772 clock-names = "se"; 773 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 774 pinctrl-names = "default"; 775 pinctrl-0 = <&qup_i2c10_default>; 776 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 power-domains = <&rpmhpd SDM670_CX>; 780 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 781 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 782 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 783 interconnect-names = "qup-core", "qup-config", "qup-memory"; 784 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 785 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 786 dma-names = "tx", "rx"; 787 status = "disabled"; 788 }; 789 790 i2c11: i2c@a8c000 { 791 compatible = "qcom,geni-i2c"; 792 reg = <0 0x00a8c000 0 0x4000>; 793 clock-names = "se"; 794 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&qup_i2c11_default>; 797 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 power-domains = <&rpmhpd SDM670_CX>; 801 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 802 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 803 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 804 interconnect-names = "qup-core", "qup-config", "qup-memory"; 805 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 806 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 807 dma-names = "tx", "rx"; 808 status = "disabled"; 809 }; 810 811 i2c12: i2c@a90000 { 812 compatible = "qcom,geni-i2c"; 813 reg = <0 0x00a90000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_i2c12_default>; 818 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 power-domains = <&rpmhpd SDM670_CX>; 822 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 823 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 824 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 825 interconnect-names = "qup-core", "qup-config", "qup-memory"; 826 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 827 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 828 dma-names = "tx", "rx"; 829 status = "disabled"; 830 }; 831 832 i2c13: i2c@a94000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x00a94000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c13_default>; 839 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 power-domains = <&rpmhpd SDM670_CX>; 843 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 844 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 845 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 846 interconnect-names = "qup-core", "qup-config", "qup-memory"; 847 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 848 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 849 dma-names = "tx", "rx"; 850 status = "disabled"; 851 }; 852 853 i2c14: i2c@a98000 { 854 compatible = "qcom,geni-i2c"; 855 reg = <0 0x00a98000 0 0x4000>; 856 clock-names = "se"; 857 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&qup_i2c14_default>; 860 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 power-domains = <&rpmhpd SDM670_CX>; 864 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 865 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 866 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 867 interconnect-names = "qup-core", "qup-config", "qup-memory"; 868 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 869 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 870 dma-names = "tx", "rx"; 871 status = "disabled"; 872 }; 873 874 i2c15: i2c@a9c000 { 875 compatible = "qcom,geni-i2c"; 876 reg = <0 0x00a9c000 0 0x4000>; 877 clock-names = "se"; 878 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&qup_i2c15_default>; 881 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 power-domains = <&rpmhpd SDM670_CX>; 885 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 886 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 887 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 888 interconnect-names = "qup-core", "qup-config", "qup-memory"; 889 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 890 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 891 dma-names = "tx", "rx"; 892 status = "disabled"; 893 }; 894 }; 895 896 mem_noc: interconnect@1380000 { 897 compatible = "qcom,sdm670-mem-noc"; 898 reg = <0 0x01380000 0 0x27200>; 899 #interconnect-cells = <2>; 900 qcom,bcm-voters = <&apps_bcm_voter>; 901 }; 902 903 dc_noc: interconnect@14e0000 { 904 compatible = "qcom,sdm670-dc-noc"; 905 reg = <0 0x014e0000 0 0x400>; 906 #interconnect-cells = <2>; 907 qcom,bcm-voters = <&apps_bcm_voter>; 908 }; 909 910 config_noc: interconnect@1500000 { 911 compatible = "qcom,sdm670-config-noc"; 912 reg = <0 0x01500000 0 0x5080>; 913 #interconnect-cells = <2>; 914 qcom,bcm-voters = <&apps_bcm_voter>; 915 }; 916 917 system_noc: interconnect@1620000 { 918 compatible = "qcom,sdm670-system-noc"; 919 reg = <0 0x01620000 0 0x18080>; 920 #interconnect-cells = <2>; 921 qcom,bcm-voters = <&apps_bcm_voter>; 922 }; 923 924 aggre1_noc: interconnect@16e0000 { 925 compatible = "qcom,sdm670-aggre1-noc"; 926 reg = <0 0x016e0000 0 0x15080>; 927 #interconnect-cells = <2>; 928 qcom,bcm-voters = <&apps_bcm_voter>; 929 }; 930 931 aggre2_noc: interconnect@1700000 { 932 compatible = "qcom,sdm670-aggre2-noc"; 933 reg = <0 0x01700000 0 0x1f300>; 934 #interconnect-cells = <2>; 935 qcom,bcm-voters = <&apps_bcm_voter>; 936 }; 937 938 mmss_noc: interconnect@1740000 { 939 compatible = "qcom,sdm670-mmss-noc"; 940 reg = <0 0x01740000 0 0x1c100>; 941 #interconnect-cells = <2>; 942 qcom,bcm-voters = <&apps_bcm_voter>; 943 }; 944 945 tlmm: pinctrl@3400000 { 946 compatible = "qcom,sdm670-tlmm"; 947 reg = <0 0x03400000 0 0xc00000>; 948 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 949 gpio-controller; 950 #gpio-cells = <2>; 951 interrupt-controller; 952 #interrupt-cells = <2>; 953 gpio-ranges = <&tlmm 0 0 151>; 954 955 qup_i2c0_default: qup-i2c0-default-state { 956 pins = "gpio0", "gpio1"; 957 function = "qup0"; 958 }; 959 960 qup_i2c1_default: qup-i2c1-default-state { 961 pins = "gpio17", "gpio18"; 962 function = "qup1"; 963 }; 964 965 qup_i2c2_default: qup-i2c2-default-state { 966 pins = "gpio27", "gpio28"; 967 function = "qup2"; 968 }; 969 970 qup_i2c3_default: qup-i2c3-default-state { 971 pins = "gpio41", "gpio42"; 972 function = "qup3"; 973 }; 974 975 qup_i2c4_default: qup-i2c4-default-state { 976 pins = "gpio89", "gpio90"; 977 function = "qup4"; 978 }; 979 980 qup_i2c5_default: qup-i2c5-default-state { 981 pins = "gpio85", "gpio86"; 982 function = "qup5"; 983 }; 984 985 qup_i2c6_default: qup-i2c6-default-state { 986 pins = "gpio45", "gpio46"; 987 function = "qup6"; 988 }; 989 990 qup_i2c7_default: qup-i2c7-default-state { 991 pins = "gpio93", "gpio94"; 992 function = "qup7"; 993 }; 994 995 qup_i2c8_default: qup-i2c8-default-state { 996 pins = "gpio65", "gpio66"; 997 function = "qup8"; 998 }; 999 1000 qup_i2c9_default: qup-i2c9-default-state { 1001 pins = "gpio6", "gpio7"; 1002 function = "qup9"; 1003 }; 1004 1005 qup_i2c10_default: qup-i2c10-default-state { 1006 pins = "gpio55", "gpio56"; 1007 function = "qup10"; 1008 }; 1009 1010 qup_i2c11_default: qup-i2c11-default-state { 1011 pins = "gpio31", "gpio32"; 1012 function = "qup11"; 1013 }; 1014 1015 qup_i2c12_default: qup-i2c12-default-state { 1016 pins = "gpio49", "gpio50"; 1017 function = "qup12"; 1018 }; 1019 1020 qup_i2c13_default: qup-i2c13-default-state { 1021 pins = "gpio105", "gpio106"; 1022 function = "qup13"; 1023 }; 1024 1025 qup_i2c14_default: qup-i2c14-default-state { 1026 pins = "gpio33", "gpio34"; 1027 function = "qup14"; 1028 }; 1029 1030 qup_i2c15_default: qup-i2c15-default-state { 1031 pins = "gpio81", "gpio82"; 1032 function = "qup15"; 1033 }; 1034 1035 sdc1_state_on: sdc1-on-state { 1036 clk-pins { 1037 pins = "sdc1_clk"; 1038 bias-disable; 1039 drive-strength = <16>; 1040 }; 1041 1042 cmd-pins { 1043 pins = "sdc1_cmd"; 1044 bias-pull-up; 1045 drive-strength = <10>; 1046 }; 1047 1048 data-pins { 1049 pins = "sdc1_data"; 1050 bias-pull-up; 1051 drive-strength = <10>; 1052 }; 1053 1054 rclk-pins { 1055 pins = "sdc1_rclk"; 1056 bias-pull-down; 1057 }; 1058 }; 1059 1060 sdc1_state_off: sdc1-off-state { 1061 clk-pins { 1062 pins = "sdc1_clk"; 1063 bias-disable; 1064 drive-strength = <2>; 1065 }; 1066 1067 cmd-pins { 1068 pins = "sdc1_cmd"; 1069 bias-pull-up; 1070 drive-strength = <2>; 1071 }; 1072 1073 data-pins { 1074 pins = "sdc1_data"; 1075 bias-pull-up; 1076 drive-strength = <2>; 1077 }; 1078 1079 rclk-pins { 1080 pins = "sdc1_rclk"; 1081 bias-pull-down; 1082 }; 1083 }; 1084 }; 1085 1086 usb_1_hsphy: phy@88e2000 { 1087 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; 1088 reg = <0 0x088e2000 0 0x400>; 1089 #phy-cells = <0>; 1090 1091 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1092 <&rpmhcc RPMH_CXO_CLK>; 1093 clock-names = "cfg_ahb", "ref"; 1094 1095 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1096 1097 nvmem-cells = <&qusb2_hstx_trim>; 1098 1099 status = "disabled"; 1100 }; 1101 1102 usb_1: usb@a6f8800 { 1103 compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; 1104 reg = <0 0x0a6f8800 0 0x400>; 1105 #address-cells = <2>; 1106 #size-cells = <2>; 1107 ranges; 1108 dma-ranges; 1109 1110 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1111 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1112 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1113 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1114 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1115 clock-names = "cfg_noc", 1116 "core", 1117 "iface", 1118 "sleep", 1119 "mock_utmi"; 1120 1121 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1122 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1123 assigned-clock-rates = <19200000>, <150000000>; 1124 1125 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1129 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1130 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1131 1132 power-domains = <&gcc USB30_PRIM_GDSC>; 1133 1134 resets = <&gcc GCC_USB30_PRIM_BCR>; 1135 1136 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, 1137 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1138 interconnect-names = "usb-ddr", "apps-usb"; 1139 1140 status = "disabled"; 1141 1142 usb_1_dwc3: usb@a600000 { 1143 compatible = "snps,dwc3"; 1144 reg = <0 0x0a600000 0 0xcd00>; 1145 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1146 iommus = <&apps_smmu 0x740 0>; 1147 snps,dis_u2_susphy_quirk; 1148 snps,dis_enblslpm_quirk; 1149 phys = <&usb_1_hsphy>; 1150 phy-names = "usb2-phy"; 1151 }; 1152 }; 1153 1154 spmi_bus: spmi@c440000 { 1155 compatible = "qcom,spmi-pmic-arb"; 1156 reg = <0 0x0c440000 0 0x1100>, 1157 <0 0x0c600000 0 0x2000000>, 1158 <0 0x0e600000 0 0x100000>, 1159 <0 0x0e700000 0 0xa0000>, 1160 <0 0x0c40a000 0 0x26000>; 1161 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1162 interrupt-names = "periph_irq"; 1163 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1164 qcom,ee = <0>; 1165 qcom,channel = <0>; 1166 #address-cells = <2>; 1167 #size-cells = <0>; 1168 interrupt-controller; 1169 #interrupt-cells = <4>; 1170 }; 1171 1172 apps_smmu: iommu@15000000 { 1173 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1174 reg = <0 0x15000000 0 0x80000>; 1175 #iommu-cells = <2>; 1176 #global-interrupts = <1>; 1177 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1242 }; 1243 1244 gladiator_noc: interconnect@17900000 { 1245 compatible = "qcom,sdm670-gladiator-noc"; 1246 reg = <0 0x17900000 0 0xd080>; 1247 #interconnect-cells = <2>; 1248 qcom,bcm-voters = <&apps_bcm_voter>; 1249 }; 1250 1251 apps_rsc: rsc@179c0000 { 1252 compatible = "qcom,rpmh-rsc"; 1253 reg = <0 0x179c0000 0 0x10000>, 1254 <0 0x179d0000 0 0x10000>, 1255 <0 0x179e0000 0 0x10000>; 1256 reg-names = "drv-0", "drv-1", "drv-2"; 1257 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1260 label = "apps_rsc"; 1261 qcom,tcs-offset = <0xd00>; 1262 qcom,drv-id = <2>; 1263 qcom,tcs-config = <ACTIVE_TCS 2>, 1264 <SLEEP_TCS 3>, 1265 <WAKE_TCS 3>, 1266 <CONTROL_TCS 1>; 1267 1268 apps_bcm_voter: bcm-voter { 1269 compatible = "qcom,bcm-voter"; 1270 }; 1271 1272 rpmhcc: clock-controller { 1273 compatible = "qcom,sdm670-rpmh-clk"; 1274 #clock-cells = <1>; 1275 clock-names = "xo"; 1276 clocks = <&xo_board>; 1277 }; 1278 1279 rpmhpd: power-controller { 1280 compatible = "qcom,sdm670-rpmhpd"; 1281 #power-domain-cells = <1>; 1282 operating-points-v2 = <&rpmhpd_opp_table>; 1283 1284 rpmhpd_opp_table: opp-table { 1285 compatible = "operating-points-v2"; 1286 1287 rpmhpd_opp_ret: opp1 { 1288 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1289 }; 1290 1291 rpmhpd_opp_min_svs: opp2 { 1292 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1293 }; 1294 1295 rpmhpd_opp_low_svs: opp3 { 1296 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1297 }; 1298 1299 rpmhpd_opp_svs: opp4 { 1300 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1301 }; 1302 1303 rpmhpd_opp_svs_l1: opp5 { 1304 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1305 }; 1306 1307 rpmhpd_opp_nom: opp6 { 1308 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1309 }; 1310 1311 rpmhpd_opp_nom_l1: opp7 { 1312 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1313 }; 1314 1315 rpmhpd_opp_nom_l2: opp8 { 1316 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1317 }; 1318 1319 rpmhpd_opp_turbo: opp9 { 1320 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1321 }; 1322 1323 rpmhpd_opp_turbo_l1: opp10 { 1324 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1325 }; 1326 }; 1327 }; 1328 }; 1329 1330 intc: interrupt-controller@17a00000 { 1331 compatible = "arm,gic-v3"; 1332 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1333 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1334 interrupt-controller; 1335 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1336 #interrupt-cells = <3>; 1337 }; 1338 }; 1339}; 1340