1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Richard Acayan. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/phy/phy-qcom-qusb2.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { }; 25 26 chosen { }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 CPU0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "qcom,kryo360"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 power-domains = <&CPU_PD0>; 38 power-domain-names = "psci"; 39 next-level-cache = <&L2_0>; 40 L2_0: l2-cache { 41 compatible = "cache"; 42 next-level-cache = <&L3_0>; 43 L3_0: l3-cache { 44 compatible = "cache"; 45 }; 46 }; 47 }; 48 49 CPU1: cpu@100 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo360"; 52 reg = <0x0 0x100>; 53 enable-method = "psci"; 54 power-domains = <&CPU_PD1>; 55 power-domain-names = "psci"; 56 next-level-cache = <&L2_100>; 57 L2_100: l2-cache { 58 compatible = "cache"; 59 next-level-cache = <&L3_0>; 60 }; 61 }; 62 63 CPU2: cpu@200 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo360"; 66 reg = <0x0 0x200>; 67 enable-method = "psci"; 68 power-domains = <&CPU_PD2>; 69 power-domain-names = "psci"; 70 next-level-cache = <&L2_200>; 71 L2_200: l2-cache { 72 compatible = "cache"; 73 next-level-cache = <&L3_0>; 74 }; 75 }; 76 77 CPU3: cpu@300 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo360"; 80 reg = <0x0 0x300>; 81 enable-method = "psci"; 82 power-domains = <&CPU_PD3>; 83 power-domain-names = "psci"; 84 next-level-cache = <&L2_300>; 85 L2_300: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 }; 90 91 CPU4: cpu@400 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo360"; 94 reg = <0x0 0x400>; 95 enable-method = "psci"; 96 power-domains = <&CPU_PD4>; 97 power-domain-names = "psci"; 98 next-level-cache = <&L2_400>; 99 L2_400: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU5: cpu@500 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo360"; 108 reg = <0x0 0x500>; 109 enable-method = "psci"; 110 power-domains = <&CPU_PD5>; 111 power-domain-names = "psci"; 112 next-level-cache = <&L2_500>; 113 L2_500: l2-cache { 114 compatible = "cache"; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU6: cpu@600 { 120 device_type = "cpu"; 121 compatible = "qcom,kryo360"; 122 reg = <0x0 0x600>; 123 enable-method = "psci"; 124 power-domains = <&CPU_PD6>; 125 power-domain-names = "psci"; 126 next-level-cache = <&L2_600>; 127 L2_600: l2-cache { 128 compatible = "cache"; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU7: cpu@700 { 134 device_type = "cpu"; 135 compatible = "qcom,kryo360"; 136 reg = <0x0 0x700>; 137 enable-method = "psci"; 138 power-domains = <&CPU_PD7>; 139 power-domain-names = "psci"; 140 next-level-cache = <&L2_700>; 141 L2_700: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 cpu-map { 148 cluster0 { 149 core0 { 150 cpu = <&CPU0>; 151 }; 152 153 core1 { 154 cpu = <&CPU1>; 155 }; 156 157 core2 { 158 cpu = <&CPU2>; 159 }; 160 161 core3 { 162 cpu = <&CPU3>; 163 }; 164 165 core4 { 166 cpu = <&CPU4>; 167 }; 168 169 core5 { 170 cpu = <&CPU5>; 171 }; 172 173 core6 { 174 cpu = <&CPU6>; 175 }; 176 177 core7 { 178 cpu = <&CPU7>; 179 }; 180 }; 181 }; 182 183 idle-states { 184 entry-method = "psci"; 185 186 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 187 compatible = "arm,idle-state"; 188 idle-state-name = "little-rail-power-collapse"; 189 arm,psci-suspend-param = <0x40000004>; 190 entry-latency-us = <702>; 191 exit-latency-us = <915>; 192 min-residency-us = <1617>; 193 local-timer-stop; 194 }; 195 196 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 197 compatible = "arm,idle-state"; 198 idle-state-name = "big-rail-power-collapse"; 199 arm,psci-suspend-param = <0x40000004>; 200 entry-latency-us = <526>; 201 exit-latency-us = <1854>; 202 min-residency-us = <2380>; 203 local-timer-stop; 204 }; 205 }; 206 207 domain-idle-states { 208 CLUSTER_SLEEP_0: cluster-sleep-0 { 209 compatible = "domain-idle-state"; 210 arm,psci-suspend-param = <0x4100c244>; 211 entry-latency-us = <3263>; 212 exit-latency-us = <6562>; 213 min-residency-us = <9825>; 214 }; 215 }; 216 }; 217 218 firmware { 219 scm { 220 compatible = "qcom,scm-sdm670", "qcom,scm"; 221 }; 222 }; 223 224 memory@80000000 { 225 device_type = "memory"; 226 /* We expect the bootloader to fill in the size */ 227 reg = <0x0 0x80000000 0x0 0x0>; 228 }; 229 230 psci { 231 compatible = "arm,psci-1.0"; 232 method = "smc"; 233 234 CPU_PD0: power-domain-cpu0 { 235 #power-domain-cells = <0>; 236 power-domains = <&CLUSTER_PD>; 237 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 238 }; 239 240 CPU_PD1: power-domain-cpu1 { 241 #power-domain-cells = <0>; 242 power-domains = <&CLUSTER_PD>; 243 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 244 }; 245 246 CPU_PD2: power-domain-cpu2 { 247 #power-domain-cells = <0>; 248 power-domains = <&CLUSTER_PD>; 249 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 250 }; 251 252 CPU_PD3: power-domain-cpu3 { 253 #power-domain-cells = <0>; 254 power-domains = <&CLUSTER_PD>; 255 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 256 }; 257 258 CPU_PD4: power-domain-cpu4 { 259 #power-domain-cells = <0>; 260 power-domains = <&CLUSTER_PD>; 261 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 262 }; 263 264 CPU_PD5: power-domain-cpu5 { 265 #power-domain-cells = <0>; 266 power-domains = <&CLUSTER_PD>; 267 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 268 }; 269 270 CPU_PD6: power-domain-cpu6 { 271 #power-domain-cells = <0>; 272 power-domains = <&CLUSTER_PD>; 273 domain-idle-states = <&BIG_CPU_SLEEP_0>; 274 }; 275 276 CPU_PD7: power-domain-cpu7 { 277 #power-domain-cells = <0>; 278 power-domains = <&CLUSTER_PD>; 279 domain-idle-states = <&BIG_CPU_SLEEP_0>; 280 }; 281 282 CLUSTER_PD: power-domain-cluster { 283 #power-domain-cells = <0>; 284 domain-idle-states = <&CLUSTER_SLEEP_0>; 285 }; 286 }; 287 288 reserved-memory { 289 #address-cells = <2>; 290 #size-cells = <2>; 291 ranges; 292 293 hyp_mem: hyp-mem@85700000 { 294 reg = <0 0x85700000 0 0x600000>; 295 no-map; 296 }; 297 298 xbl_mem: xbl-mem@85e00000 { 299 reg = <0 0x85e00000 0 0x100000>; 300 no-map; 301 }; 302 303 aop_mem: aop-mem@85fc0000 { 304 reg = <0 0x85fc0000 0 0x20000>; 305 no-map; 306 }; 307 308 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 309 compatible = "qcom,cmd-db"; 310 reg = <0 0x85fe0000 0 0x20000>; 311 no-map; 312 }; 313 314 camera_mem: camera-mem@8ab00000 { 315 reg = <0 0x8ab00000 0 0x500000>; 316 no-map; 317 }; 318 319 mpss_region: mpss@8b000000 { 320 reg = <0 0x8b000000 0 0x7e00000>; 321 no-map; 322 }; 323 324 venus_mem: venus@92e00000 { 325 reg = <0 0x92e00000 0 0x500000>; 326 no-map; 327 }; 328 329 wlan_msa_mem: wlan-msa@93300000 { 330 reg = <0 0x93300000 0 0x100000>; 331 no-map; 332 }; 333 334 cdsp_mem: cdsp@93400000 { 335 reg = <0 0x93400000 0 0x800000>; 336 no-map; 337 }; 338 339 mba_region: mba@93c00000 { 340 reg = <0 0x93c00000 0 0x200000>; 341 no-map; 342 }; 343 344 adsp_mem: adsp@93e00000 { 345 reg = <0 0x93e00000 0 0x1e00000>; 346 no-map; 347 }; 348 349 ipa_fw_mem: ipa-fw@95c00000 { 350 reg = <0 0x95c00000 0 0x10000>; 351 no-map; 352 }; 353 354 ipa_gsi_mem: ipa-gsi@95c10000 { 355 reg = <0 0x95c10000 0 0x5000>; 356 no-map; 357 }; 358 359 gpu_mem: gpu@95c15000 { 360 reg = <0 0x95c15000 0 0x2000>; 361 no-map; 362 }; 363 364 spss_mem: spss@97b00000 { 365 reg = <0 0x97b00000 0 0x100000>; 366 no-map; 367 }; 368 369 qseecom_mem: qseecom@9e400000 { 370 reg = <0 0x9e400000 0 0x1400000>; 371 no-map; 372 }; 373 }; 374 375 timer { 376 compatible = "arm,armv8-timer"; 377 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 378 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 379 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 380 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 381 }; 382 383 soc: soc@0 { 384 #address-cells = <2>; 385 #size-cells = <2>; 386 ranges = <0 0 0 0 0x10 0>; 387 dma-ranges = <0 0 0 0 0x10 0>; 388 compatible = "simple-bus"; 389 390 gcc: clock-controller@100000 { 391 compatible = "qcom,gcc-sdm670"; 392 reg = <0 0x00100000 0 0x1f0000>; 393 clocks = <&rpmhcc RPMH_CXO_CLK>, 394 <&rpmhcc RPMH_CXO_CLK_A>, 395 <&sleep_clk>; 396 clock-names = "bi_tcxo", 397 "bi_tcxo_ao", 398 "sleep_clk"; 399 #clock-cells = <1>; 400 #reset-cells = <1>; 401 #power-domain-cells = <1>; 402 }; 403 404 sdhc_1: mmc@7c4000 { 405 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; 406 reg = <0 0x007c4000 0 0x1000>, 407 <0 0x007c5000 0 0x1000>, 408 <0 0x007c8000 0 0x8000>; 409 reg-names = "hc", "cqhci", "ice"; 410 411 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "hc_irq", "pwr_irq"; 414 415 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 416 <&gcc GCC_SDCC1_APPS_CLK>, 417 <&rpmhcc RPMH_CXO_CLK>, 418 <&gcc GCC_SDCC1_ICE_CORE_CLK>, 419 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 420 clock-names = "iface", "core", "xo", "ice", "bus"; 421 422 iommus = <&apps_smmu 0x140 0xf>; 423 424 pinctrl-names = "default", "sleep"; 425 pinctrl-0 = <&sdc1_state_on>; 426 pinctrl-1 = <&sdc1_state_off>; 427 power-domains = <&rpmhpd SDM670_CX>; 428 429 bus-width = <8>; 430 non-removable; 431 432 status = "disabled"; 433 }; 434 435 gpi_dma0: dma-controller@800000 { 436 #dma-cells = <3>; 437 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 438 reg = <0 0x00800000 0 0x60000>; 439 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 452 dma-channels = <13>; 453 dma-channel-mask = <0xfa>; 454 iommus = <&apps_smmu 0x16 0x0>; 455 status = "disabled"; 456 }; 457 458 qupv3_id_0: geniqup@8c0000 { 459 compatible = "qcom,geni-se-qup"; 460 reg = <0 0x008c0000 0 0x6000>; 461 clock-names = "m-ahb", "s-ahb"; 462 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 463 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 464 iommus = <&apps_smmu 0x3 0x0>; 465 #address-cells = <2>; 466 #size-cells = <2>; 467 ranges; 468 status = "disabled"; 469 470 i2c0: i2c@880000 { 471 compatible = "qcom,geni-i2c"; 472 reg = <0 0x00880000 0 0x4000>; 473 clock-names = "se"; 474 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&qup_i2c0_default>; 477 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 power-domains = <&rpmhpd SDM670_CX>; 481 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 482 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 483 dma-names = "tx", "rx"; 484 status = "disabled"; 485 }; 486 487 i2c1: i2c@884000 { 488 compatible = "qcom,geni-i2c"; 489 reg = <0 0x00884000 0 0x4000>; 490 clock-names = "se"; 491 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&qup_i2c1_default>; 494 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 power-domains = <&rpmhpd SDM670_CX>; 498 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 499 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 500 dma-names = "tx", "rx"; 501 status = "disabled"; 502 }; 503 504 i2c2: i2c@888000 { 505 compatible = "qcom,geni-i2c"; 506 reg = <0 0x00888000 0 0x4000>; 507 clock-names = "se"; 508 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&qup_i2c2_default>; 511 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 power-domains = <&rpmhpd SDM670_CX>; 515 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 516 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 517 dma-names = "tx", "rx"; 518 status = "disabled"; 519 }; 520 521 i2c3: i2c@88c000 { 522 compatible = "qcom,geni-i2c"; 523 reg = <0 0x0088c000 0 0x4000>; 524 clock-names = "se"; 525 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&qup_i2c3_default>; 528 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 power-domains = <&rpmhpd SDM670_CX>; 532 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 533 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 534 dma-names = "tx", "rx"; 535 status = "disabled"; 536 }; 537 538 i2c4: i2c@890000 { 539 compatible = "qcom,geni-i2c"; 540 reg = <0 0x00890000 0 0x4000>; 541 clock-names = "se"; 542 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&qup_i2c4_default>; 545 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 power-domains = <&rpmhpd SDM670_CX>; 549 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 550 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 551 dma-names = "tx", "rx"; 552 status = "disabled"; 553 }; 554 555 i2c5: i2c@894000 { 556 compatible = "qcom,geni-i2c"; 557 reg = <0 0x00894000 0 0x4000>; 558 clock-names = "se"; 559 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&qup_i2c5_default>; 562 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 power-domains = <&rpmhpd SDM670_CX>; 566 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 567 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 568 dma-names = "tx", "rx"; 569 status = "disabled"; 570 }; 571 572 i2c6: i2c@898000 { 573 compatible = "qcom,geni-i2c"; 574 reg = <0 0x00898000 0 0x4000>; 575 clock-names = "se"; 576 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&qup_i2c6_default>; 579 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 power-domains = <&rpmhpd SDM670_CX>; 583 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 584 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 585 dma-names = "tx", "rx"; 586 status = "disabled"; 587 }; 588 589 i2c7: i2c@89c000 { 590 compatible = "qcom,geni-i2c"; 591 reg = <0 0x0089c000 0 0x4000>; 592 clock-names = "se"; 593 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&qup_i2c7_default>; 596 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 power-domains = <&rpmhpd SDM670_CX>; 600 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 601 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 602 dma-names = "tx", "rx"; 603 status = "disabled"; 604 }; 605 }; 606 607 gpi_dma1: dma-controller@a00000 { 608 #dma-cells = <3>; 609 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 610 reg = <0 0x00a00000 0 0x60000>; 611 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 624 dma-channels = <13>; 625 dma-channel-mask = <0xfa>; 626 iommus = <&apps_smmu 0x6d6 0x0>; 627 status = "disabled"; 628 }; 629 630 qupv3_id_1: geniqup@ac0000 { 631 compatible = "qcom,geni-se-qup"; 632 reg = <0 0x00ac0000 0 0x6000>; 633 clock-names = "m-ahb", "s-ahb"; 634 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 635 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 636 iommus = <&apps_smmu 0x6c3 0x0>; 637 #address-cells = <2>; 638 #size-cells = <2>; 639 ranges; 640 status = "disabled"; 641 642 i2c8: i2c@a80000 { 643 compatible = "qcom,geni-i2c"; 644 reg = <0 0x00a80000 0 0x4000>; 645 clock-names = "se"; 646 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&qup_i2c8_default>; 649 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 power-domains = <&rpmhpd SDM670_CX>; 653 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 654 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 655 dma-names = "tx", "rx"; 656 status = "disabled"; 657 }; 658 659 i2c9: i2c@a84000 { 660 compatible = "qcom,geni-i2c"; 661 reg = <0 0x00a84000 0 0x4000>; 662 clock-names = "se"; 663 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&qup_i2c9_default>; 666 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 power-domains = <&rpmhpd SDM670_CX>; 670 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 671 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 672 dma-names = "tx", "rx"; 673 status = "disabled"; 674 }; 675 676 i2c10: i2c@a88000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0 0x00a88000 0 0x4000>; 679 clock-names = "se"; 680 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_i2c10_default>; 683 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 power-domains = <&rpmhpd SDM670_CX>; 687 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 688 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 689 dma-names = "tx", "rx"; 690 status = "disabled"; 691 }; 692 693 i2c11: i2c@a8c000 { 694 compatible = "qcom,geni-i2c"; 695 reg = <0 0x00a8c000 0 0x4000>; 696 clock-names = "se"; 697 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&qup_i2c11_default>; 700 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 power-domains = <&rpmhpd SDM670_CX>; 704 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 705 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 706 dma-names = "tx", "rx"; 707 status = "disabled"; 708 }; 709 710 i2c12: i2c@a90000 { 711 compatible = "qcom,geni-i2c"; 712 reg = <0 0x00a90000 0 0x4000>; 713 clock-names = "se"; 714 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&qup_i2c12_default>; 717 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 power-domains = <&rpmhpd SDM670_CX>; 721 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 722 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 723 dma-names = "tx", "rx"; 724 status = "disabled"; 725 }; 726 727 i2c13: i2c@a94000 { 728 compatible = "qcom,geni-i2c"; 729 reg = <0 0x00a94000 0 0x4000>; 730 clock-names = "se"; 731 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&qup_i2c13_default>; 734 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 power-domains = <&rpmhpd SDM670_CX>; 738 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 739 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 740 dma-names = "tx", "rx"; 741 status = "disabled"; 742 }; 743 744 i2c14: i2c@a98000 { 745 compatible = "qcom,geni-i2c"; 746 reg = <0 0x00a98000 0 0x4000>; 747 clock-names = "se"; 748 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&qup_i2c14_default>; 751 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 power-domains = <&rpmhpd SDM670_CX>; 755 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 756 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 757 dma-names = "tx", "rx"; 758 status = "disabled"; 759 }; 760 761 i2c15: i2c@a9c000 { 762 compatible = "qcom,geni-i2c"; 763 reg = <0 0x00a9c000 0 0x4000>; 764 clock-names = "se"; 765 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&qup_i2c15_default>; 768 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 power-domains = <&rpmhpd SDM670_CX>; 772 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 773 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 774 dma-names = "tx", "rx"; 775 status = "disabled"; 776 }; 777 }; 778 779 tlmm: pinctrl@3400000 { 780 compatible = "qcom,sdm670-tlmm"; 781 reg = <0 0x03400000 0 0xc00000>; 782 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 783 gpio-controller; 784 #gpio-cells = <2>; 785 interrupt-controller; 786 #interrupt-cells = <2>; 787 gpio-ranges = <&tlmm 0 0 151>; 788 789 qup_i2c0_default: qup-i2c0-default-state { 790 pins = "gpio0", "gpio1"; 791 function = "qup0"; 792 }; 793 794 qup_i2c1_default: qup-i2c1-default-state { 795 pins = "gpio17", "gpio18"; 796 function = "qup1"; 797 }; 798 799 qup_i2c2_default: qup-i2c2-default-state { 800 pins = "gpio27", "gpio28"; 801 function = "qup2"; 802 }; 803 804 qup_i2c3_default: qup-i2c3-default-state { 805 pins = "gpio41", "gpio42"; 806 function = "qup3"; 807 }; 808 809 qup_i2c4_default: qup-i2c4-default-state { 810 pins = "gpio89", "gpio90"; 811 function = "qup4"; 812 }; 813 814 qup_i2c5_default: qup-i2c5-default-state { 815 pins = "gpio85", "gpio86"; 816 function = "qup5"; 817 }; 818 819 qup_i2c6_default: qup-i2c6-default-state { 820 pins = "gpio45", "gpio46"; 821 function = "qup6"; 822 }; 823 824 qup_i2c7_default: qup-i2c7-default-state { 825 pins = "gpio93", "gpio94"; 826 function = "qup7"; 827 }; 828 829 qup_i2c8_default: qup-i2c8-default-state { 830 pins = "gpio65", "gpio66"; 831 function = "qup8"; 832 }; 833 834 qup_i2c9_default: qup-i2c9-default-state { 835 pins = "gpio6", "gpio7"; 836 function = "qup9"; 837 }; 838 839 qup_i2c10_default: qup-i2c10-default-state { 840 pins = "gpio55", "gpio56"; 841 function = "qup10"; 842 }; 843 844 qup_i2c11_default: qup-i2c11-default-state { 845 pins = "gpio31", "gpio32"; 846 function = "qup11"; 847 }; 848 849 qup_i2c12_default: qup-i2c12-default-state { 850 pins = "gpio49", "gpio50"; 851 function = "qup12"; 852 }; 853 854 qup_i2c13_default: qup-i2c13-default-state { 855 pins = "gpio105", "gpio106"; 856 function = "qup13"; 857 }; 858 859 qup_i2c14_default: qup-i2c14-default-state { 860 pins = "gpio33", "gpio34"; 861 function = "qup14"; 862 }; 863 864 qup_i2c15_default: qup-i2c15-default-state { 865 pins = "gpio81", "gpio82"; 866 function = "qup15"; 867 }; 868 869 sdc1_state_on: sdc1-on-state { 870 clk-pins { 871 pins = "sdc1_clk"; 872 bias-disable; 873 drive-strength = <16>; 874 }; 875 876 cmd-pins { 877 pins = "sdc1_cmd"; 878 bias-pull-up; 879 drive-strength = <10>; 880 }; 881 882 data-pins { 883 pins = "sdc1_data"; 884 bias-pull-up; 885 drive-strength = <10>; 886 }; 887 888 rclk-pins { 889 pins = "sdc1_rclk"; 890 bias-pull-down; 891 }; 892 }; 893 894 sdc1_state_off: sdc1-off-state { 895 clk-pins { 896 pins = "sdc1_clk"; 897 bias-disable; 898 drive-strength = <2>; 899 }; 900 901 cmd-pins { 902 pins = "sdc1_cmd"; 903 bias-pull-up; 904 drive-strength = <2>; 905 }; 906 907 data-pins { 908 pins = "sdc1_data"; 909 bias-pull-up; 910 drive-strength = <2>; 911 }; 912 913 rclk-pins { 914 pins = "sdc1_rclk"; 915 bias-pull-down; 916 }; 917 }; 918 }; 919 920 usb_1_hsphy: phy@88e2000 { 921 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; 922 reg = <0 0x088e2000 0 0x400>; 923 #phy-cells = <0>; 924 925 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 926 <&rpmhcc RPMH_CXO_CLK>; 927 clock-names = "cfg_ahb", "ref"; 928 929 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 930 931 status = "disabled"; 932 }; 933 934 usb_1: usb@a6f8800 { 935 compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; 936 reg = <0 0x0a6f8800 0 0x400>; 937 #address-cells = <2>; 938 #size-cells = <2>; 939 ranges; 940 dma-ranges; 941 942 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 943 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 944 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 945 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 946 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 947 clock-names = "cfg_noc", 948 "core", 949 "iface", 950 "sleep", 951 "mock_utmi"; 952 953 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 954 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 955 assigned-clock-rates = <19200000>, <150000000>; 956 957 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 961 interrupt-names = "hs_phy_irq", "ss_phy_irq", 962 "dm_hs_phy_irq", "dp_hs_phy_irq"; 963 964 power-domains = <&gcc USB30_PRIM_GDSC>; 965 966 resets = <&gcc GCC_USB30_PRIM_BCR>; 967 968 status = "disabled"; 969 970 usb_1_dwc3: usb@a600000 { 971 compatible = "snps,dwc3"; 972 reg = <0 0x0a600000 0 0xcd00>; 973 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 974 iommus = <&apps_smmu 0x740 0>; 975 snps,dis_u2_susphy_quirk; 976 snps,dis_enblslpm_quirk; 977 phys = <&usb_1_hsphy>; 978 phy-names = "usb2-phy"; 979 }; 980 }; 981 982 spmi_bus: spmi@c440000 { 983 compatible = "qcom,spmi-pmic-arb"; 984 reg = <0 0x0c440000 0 0x1100>, 985 <0 0x0c600000 0 0x2000000>, 986 <0 0x0e600000 0 0x100000>, 987 <0 0x0e700000 0 0xa0000>, 988 <0 0x0c40a000 0 0x26000>; 989 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 990 interrupt-names = "periph_irq"; 991 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 992 qcom,ee = <0>; 993 qcom,channel = <0>; 994 #address-cells = <2>; 995 #size-cells = <0>; 996 interrupt-controller; 997 #interrupt-cells = <4>; 998 }; 999 1000 apps_smmu: iommu@15000000 { 1001 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1002 reg = <0 0x15000000 0 0x80000>; 1003 #iommu-cells = <2>; 1004 #global-interrupts = <1>; 1005 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1070 }; 1071 1072 apps_rsc: rsc@179c0000 { 1073 compatible = "qcom,rpmh-rsc"; 1074 reg = <0 0x179c0000 0 0x10000>, 1075 <0 0x179d0000 0 0x10000>, 1076 <0 0x179e0000 0 0x10000>; 1077 reg-names = "drv-0", "drv-1", "drv-2"; 1078 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1081 label = "apps_rsc"; 1082 qcom,tcs-offset = <0xd00>; 1083 qcom,drv-id = <2>; 1084 qcom,tcs-config = <ACTIVE_TCS 2>, 1085 <SLEEP_TCS 3>, 1086 <WAKE_TCS 3>, 1087 <CONTROL_TCS 1>; 1088 1089 apps_bcm_voter: bcm-voter { 1090 compatible = "qcom,bcm-voter"; 1091 }; 1092 1093 rpmhcc: clock-controller { 1094 compatible = "qcom,sdm670-rpmh-clk"; 1095 #clock-cells = <1>; 1096 clock-names = "xo"; 1097 clocks = <&xo_board>; 1098 }; 1099 1100 rpmhpd: power-controller { 1101 compatible = "qcom,sdm670-rpmhpd"; 1102 #power-domain-cells = <1>; 1103 operating-points-v2 = <&rpmhpd_opp_table>; 1104 1105 rpmhpd_opp_table: opp-table { 1106 compatible = "operating-points-v2"; 1107 1108 rpmhpd_opp_ret: opp1 { 1109 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1110 }; 1111 1112 rpmhpd_opp_min_svs: opp2 { 1113 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1114 }; 1115 1116 rpmhpd_opp_low_svs: opp3 { 1117 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1118 }; 1119 1120 rpmhpd_opp_svs: opp4 { 1121 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1122 }; 1123 1124 rpmhpd_opp_svs_l1: opp5 { 1125 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1126 }; 1127 1128 rpmhpd_opp_nom: opp6 { 1129 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1130 }; 1131 1132 rpmhpd_opp_nom_l1: opp7 { 1133 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1134 }; 1135 1136 rpmhpd_opp_nom_l2: opp8 { 1137 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1138 }; 1139 1140 rpmhpd_opp_turbo: opp9 { 1141 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1142 }; 1143 1144 rpmhpd_opp_turbo_l1: opp10 { 1145 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1146 }; 1147 }; 1148 }; 1149 }; 1150 1151 intc: interrupt-controller@17a00000 { 1152 compatible = "arm,gic-v3"; 1153 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1154 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1155 interrupt-controller; 1156 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1157 #interrupt-cells = <3>; 1158 }; 1159 }; 1160}; 1161