1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 L3_0: l3-cache { 187 compatible = "cache"; 188 cache-level = <3>; 189 }; 190 }; 191 }; 192 193 CPU1: cpu@100 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo"; 196 reg = <0x0 0x100>; 197 clocks = <&cpufreq_hw 0>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_100>; 203 operating-points-v2 = <&cpu0_opp_table>; 204 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 205 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 206 qcom,freq-domain = <&cpufreq_hw 0>; 207 #cooling-cells = <2>; 208 L2_100: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 next-level-cache = <&L3_0>; 212 }; 213 }; 214 215 CPU2: cpu@200 { 216 device_type = "cpu"; 217 compatible = "qcom,kryo"; 218 reg = <0x0 0x200>; 219 clocks = <&cpufreq_hw 0>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 next-level-cache = <&L2_200>; 225 operating-points-v2 = <&cpu0_opp_table>; 226 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 227 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 228 qcom,freq-domain = <&cpufreq_hw 0>; 229 #cooling-cells = <2>; 230 L2_200: l2-cache { 231 compatible = "cache"; 232 cache-level = <2>; 233 next-level-cache = <&L3_0>; 234 }; 235 }; 236 237 CPU3: cpu@300 { 238 device_type = "cpu"; 239 compatible = "qcom,kryo"; 240 reg = <0x0 0x300>; 241 clocks = <&cpufreq_hw 0>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 next-level-cache = <&L2_300>; 247 operating-points-v2 = <&cpu0_opp_table>; 248 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 249 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 250 qcom,freq-domain = <&cpufreq_hw 0>; 251 #cooling-cells = <2>; 252 L2_300: l2-cache { 253 compatible = "cache"; 254 cache-level = <2>; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU4: cpu@400 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo"; 262 reg = <0x0 0x400>; 263 clocks = <&cpufreq_hw 1>; 264 enable-method = "psci"; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 next-level-cache = <&L2_400>; 269 operating-points-v2 = <&cpu4_opp_table>; 270 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 271 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 272 qcom,freq-domain = <&cpufreq_hw 1>; 273 #cooling-cells = <2>; 274 L2_400: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU5: cpu@500 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo"; 284 reg = <0x0 0x500>; 285 clocks = <&cpufreq_hw 1>; 286 enable-method = "psci"; 287 cpu-idle-states = <&BIG_CPU_SLEEP_0 288 &BIG_CPU_SLEEP_1 289 &CLUSTER_SLEEP_0>; 290 next-level-cache = <&L2_500>; 291 operating-points-v2 = <&cpu4_opp_table>; 292 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 293 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 294 qcom,freq-domain = <&cpufreq_hw 1>; 295 #cooling-cells = <2>; 296 L2_500: l2-cache { 297 compatible = "cache"; 298 cache-level = <2>; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 CPU6: cpu@600 { 304 device_type = "cpu"; 305 compatible = "qcom,kryo"; 306 reg = <0x0 0x600>; 307 clocks = <&cpufreq_hw 1>; 308 enable-method = "psci"; 309 cpu-idle-states = <&BIG_CPU_SLEEP_0 310 &BIG_CPU_SLEEP_1 311 &CLUSTER_SLEEP_0>; 312 next-level-cache = <&L2_600>; 313 operating-points-v2 = <&cpu4_opp_table>; 314 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 315 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 316 qcom,freq-domain = <&cpufreq_hw 1>; 317 #cooling-cells = <2>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 cache-level = <2>; 321 next-level-cache = <&L3_0>; 322 }; 323 }; 324 325 CPU7: cpu@700 { 326 device_type = "cpu"; 327 compatible = "qcom,kryo"; 328 reg = <0x0 0x700>; 329 clocks = <&cpufreq_hw 2>; 330 enable-method = "psci"; 331 cpu-idle-states = <&BIG_CPU_SLEEP_0 332 &BIG_CPU_SLEEP_1 333 &CLUSTER_SLEEP_0>; 334 next-level-cache = <&L2_700>; 335 operating-points-v2 = <&cpu7_opp_table>; 336 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 337 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 338 qcom,freq-domain = <&cpufreq_hw 2>; 339 #cooling-cells = <2>; 340 L2_700: l2-cache { 341 compatible = "cache"; 342 cache-level = <2>; 343 next-level-cache = <&L3_0>; 344 }; 345 }; 346 347 cpu-map { 348 cluster0 { 349 core0 { 350 cpu = <&CPU0>; 351 }; 352 353 core1 { 354 cpu = <&CPU1>; 355 }; 356 357 core2 { 358 cpu = <&CPU2>; 359 }; 360 361 core3 { 362 cpu = <&CPU3>; 363 }; 364 365 core4 { 366 cpu = <&CPU4>; 367 }; 368 369 core5 { 370 cpu = <&CPU5>; 371 }; 372 373 core6 { 374 cpu = <&CPU6>; 375 }; 376 377 core7 { 378 cpu = <&CPU7>; 379 }; 380 }; 381 }; 382 383 idle-states { 384 entry-method = "psci"; 385 386 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 387 compatible = "arm,idle-state"; 388 idle-state-name = "little-power-down"; 389 arm,psci-suspend-param = <0x40000003>; 390 entry-latency-us = <549>; 391 exit-latency-us = <901>; 392 min-residency-us = <1774>; 393 local-timer-stop; 394 }; 395 396 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "little-rail-power-down"; 399 arm,psci-suspend-param = <0x40000004>; 400 entry-latency-us = <702>; 401 exit-latency-us = <915>; 402 min-residency-us = <4001>; 403 local-timer-stop; 404 }; 405 406 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "big-power-down"; 409 arm,psci-suspend-param = <0x40000003>; 410 entry-latency-us = <523>; 411 exit-latency-us = <1244>; 412 min-residency-us = <2207>; 413 local-timer-stop; 414 }; 415 416 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "big-rail-power-down"; 419 arm,psci-suspend-param = <0x40000004>; 420 entry-latency-us = <526>; 421 exit-latency-us = <1854>; 422 min-residency-us = <5555>; 423 local-timer-stop; 424 }; 425 426 CLUSTER_SLEEP_0: cluster-sleep-0 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "cluster-power-down"; 429 arm,psci-suspend-param = <0x40003444>; 430 entry-latency-us = <3263>; 431 exit-latency-us = <6562>; 432 min-residency-us = <9926>; 433 local-timer-stop; 434 }; 435 }; 436 }; 437 438 cpu0_opp_table: opp-table-cpu0 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 cpu0_opp_300mhz: opp-300000000 { 443 opp-hz = /bits/ 64 <300000000>; 444 opp-peak-kBps = <800000 9600000>; 445 }; 446 447 cpu0_opp_691mhz: opp-691200000 { 448 opp-hz = /bits/ 64 <691200000>; 449 opp-peak-kBps = <800000 17817600>; 450 }; 451 452 cpu0_opp_806mhz: opp-806400000 { 453 opp-hz = /bits/ 64 <806400000>; 454 opp-peak-kBps = <800000 20889600>; 455 }; 456 457 cpu0_opp_941mhz: opp-940800000 { 458 opp-hz = /bits/ 64 <940800000>; 459 opp-peak-kBps = <1804000 24576000>; 460 }; 461 462 cpu0_opp_1152mhz: opp-1152000000 { 463 opp-hz = /bits/ 64 <1152000000>; 464 opp-peak-kBps = <2188000 27033600>; 465 }; 466 467 cpu0_opp_1325mhz: opp-1324800000 { 468 opp-hz = /bits/ 64 <1324800000>; 469 opp-peak-kBps = <2188000 33792000>; 470 }; 471 472 cpu0_opp_1517mhz: opp-1516800000 { 473 opp-hz = /bits/ 64 <1516800000>; 474 opp-peak-kBps = <3072000 38092800>; 475 }; 476 477 cpu0_opp_1651mhz: opp-1651200000 { 478 opp-hz = /bits/ 64 <1651200000>; 479 opp-peak-kBps = <3072000 41779200>; 480 }; 481 482 cpu0_opp_1805mhz: opp-1804800000 { 483 opp-hz = /bits/ 64 <1804800000>; 484 opp-peak-kBps = <4068000 48537600>; 485 }; 486 487 cpu0_opp_1958mhz: opp-1958400000 { 488 opp-hz = /bits/ 64 <1958400000>; 489 opp-peak-kBps = <4068000 48537600>; 490 }; 491 492 cpu0_opp_2016mhz: opp-2016000000 { 493 opp-hz = /bits/ 64 <2016000000>; 494 opp-peak-kBps = <6220000 48537600>; 495 }; 496 }; 497 498 cpu4_opp_table: opp-table-cpu4 { 499 compatible = "operating-points-v2"; 500 opp-shared; 501 502 cpu4_opp_691mhz: opp-691200000 { 503 opp-hz = /bits/ 64 <691200000>; 504 opp-peak-kBps = <1804000 9600000>; 505 }; 506 507 cpu4_opp_941mhz: opp-940800000 { 508 opp-hz = /bits/ 64 <940800000>; 509 opp-peak-kBps = <2188000 17817600>; 510 }; 511 512 cpu4_opp_1229mhz: opp-1228800000 { 513 opp-hz = /bits/ 64 <1228800000>; 514 opp-peak-kBps = <4068000 24576000>; 515 }; 516 517 cpu4_opp_1344mhz: opp-1344000000 { 518 opp-hz = /bits/ 64 <1344000000>; 519 opp-peak-kBps = <4068000 24576000>; 520 }; 521 522 cpu4_opp_1517mhz: opp-1516800000 { 523 opp-hz = /bits/ 64 <1516800000>; 524 opp-peak-kBps = <4068000 24576000>; 525 }; 526 527 cpu4_opp_1651mhz: opp-1651200000 { 528 opp-hz = /bits/ 64 <1651200000>; 529 opp-peak-kBps = <6220000 38092800>; 530 }; 531 532 cpu4_opp_1901mhz: opp-1900800000 { 533 opp-hz = /bits/ 64 <1900800000>; 534 opp-peak-kBps = <6220000 44851200>; 535 }; 536 537 cpu4_opp_2054mhz: opp-2054400000 { 538 opp-hz = /bits/ 64 <2054400000>; 539 opp-peak-kBps = <6220000 44851200>; 540 }; 541 542 cpu4_opp_2112mhz: opp-2112000000 { 543 opp-hz = /bits/ 64 <2112000000>; 544 opp-peak-kBps = <6220000 44851200>; 545 }; 546 547 cpu4_opp_2131mhz: opp-2131200000 { 548 opp-hz = /bits/ 64 <2131200000>; 549 opp-peak-kBps = <6220000 44851200>; 550 }; 551 552 cpu4_opp_2208mhz: opp-2208000000 { 553 opp-hz = /bits/ 64 <2208000000>; 554 opp-peak-kBps = <6220000 44851200>; 555 }; 556 557 cpu4_opp_2400mhz: opp-2400000000 { 558 opp-hz = /bits/ 64 <2400000000>; 559 opp-peak-kBps = <8532000 48537600>; 560 }; 561 562 cpu4_opp_2611mhz: opp-2611200000 { 563 opp-hz = /bits/ 64 <2611200000>; 564 opp-peak-kBps = <8532000 48537600>; 565 }; 566 }; 567 568 cpu7_opp_table: opp-table-cpu7 { 569 compatible = "operating-points-v2"; 570 opp-shared; 571 572 cpu7_opp_806mhz: opp-806400000 { 573 opp-hz = /bits/ 64 <806400000>; 574 opp-peak-kBps = <1804000 9600000>; 575 }; 576 577 cpu7_opp_1056mhz: opp-1056000000 { 578 opp-hz = /bits/ 64 <1056000000>; 579 opp-peak-kBps = <2188000 17817600>; 580 }; 581 582 cpu7_opp_1325mhz: opp-1324800000 { 583 opp-hz = /bits/ 64 <1324800000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu7_opp_1517mhz: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu7_opp_1766mhz: opp-1766400000 { 593 opp-hz = /bits/ 64 <1766400000>; 594 opp-peak-kBps = <6220000 38092800>; 595 }; 596 597 cpu7_opp_1862mhz: opp-1862400000 { 598 opp-hz = /bits/ 64 <1862400000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu7_opp_2035mhz: opp-2035200000 { 603 opp-hz = /bits/ 64 <2035200000>; 604 opp-peak-kBps = <6220000 38092800>; 605 }; 606 607 cpu7_opp_2112mhz: opp-2112000000 { 608 opp-hz = /bits/ 64 <2112000000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu7_opp_2208mhz: opp-2208000000 { 613 opp-hz = /bits/ 64 <2208000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu7_opp_2381mhz: opp-2380800000 { 618 opp-hz = /bits/ 64 <2380800000>; 619 opp-peak-kBps = <6832000 44851200>; 620 }; 621 622 cpu7_opp_2400mhz: opp-2400000000 { 623 opp-hz = /bits/ 64 <2400000000>; 624 opp-peak-kBps = <8532000 48537600>; 625 }; 626 627 cpu7_opp_2515mhz: opp-2515200000 { 628 opp-hz = /bits/ 64 <2515200000>; 629 opp-peak-kBps = <8532000 48537600>; 630 }; 631 632 cpu7_opp_2707mhz: opp-2707200000 { 633 opp-hz = /bits/ 64 <2707200000>; 634 opp-peak-kBps = <8532000 48537600>; 635 }; 636 637 cpu7_opp_3014mhz: opp-3014400000 { 638 opp-hz = /bits/ 64 <3014400000>; 639 opp-peak-kBps = <8532000 48537600>; 640 }; 641 }; 642 643 memory@80000000 { 644 device_type = "memory"; 645 /* We expect the bootloader to fill in the size */ 646 reg = <0 0x80000000 0 0>; 647 }; 648 649 firmware { 650 scm { 651 compatible = "qcom,scm-sc7280", "qcom,scm"; 652 }; 653 }; 654 655 clk_virt: interconnect { 656 compatible = "qcom,sc7280-clk-virt"; 657 #interconnect-cells = <2>; 658 qcom,bcm-voters = <&apps_bcm_voter>; 659 }; 660 661 smem { 662 compatible = "qcom,smem"; 663 memory-region = <&smem_mem>; 664 hwlocks = <&tcsr_mutex 3>; 665 }; 666 667 smp2p-adsp { 668 compatible = "qcom,smp2p"; 669 qcom,smem = <443>, <429>; 670 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 671 IPCC_MPROC_SIGNAL_SMP2P 672 IRQ_TYPE_EDGE_RISING>; 673 mboxes = <&ipcc IPCC_CLIENT_LPASS 674 IPCC_MPROC_SIGNAL_SMP2P>; 675 676 qcom,local-pid = <0>; 677 qcom,remote-pid = <2>; 678 679 adsp_smp2p_out: master-kernel { 680 qcom,entry-name = "master-kernel"; 681 #qcom,smem-state-cells = <1>; 682 }; 683 684 adsp_smp2p_in: slave-kernel { 685 qcom,entry-name = "slave-kernel"; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 }; 689 }; 690 691 smp2p-cdsp { 692 compatible = "qcom,smp2p"; 693 qcom,smem = <94>, <432>; 694 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 695 IPCC_MPROC_SIGNAL_SMP2P 696 IRQ_TYPE_EDGE_RISING>; 697 mboxes = <&ipcc IPCC_CLIENT_CDSP 698 IPCC_MPROC_SIGNAL_SMP2P>; 699 700 qcom,local-pid = <0>; 701 qcom,remote-pid = <5>; 702 703 cdsp_smp2p_out: master-kernel { 704 qcom,entry-name = "master-kernel"; 705 #qcom,smem-state-cells = <1>; 706 }; 707 708 cdsp_smp2p_in: slave-kernel { 709 qcom,entry-name = "slave-kernel"; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 }; 713 }; 714 715 smp2p-mpss { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <435>, <428>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_MPSS 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <1>; 726 727 modem_smp2p_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 modem_smp2p_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 738 ipa_smp2p_out: ipa-ap-to-modem { 739 qcom,entry-name = "ipa"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 ipa_smp2p_in: ipa-modem-to-ap { 744 qcom,entry-name = "ipa"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-wpss { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <617>, <616>; 753 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 mboxes = <&ipcc IPCC_CLIENT_WPSS 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,local-pid = <0>; 760 qcom,remote-pid = <13>; 761 762 wpss_smp2p_out: master-kernel { 763 qcom,entry-name = "master-kernel"; 764 #qcom,smem-state-cells = <1>; 765 }; 766 767 wpss_smp2p_in: slave-kernel { 768 qcom,entry-name = "slave-kernel"; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 773 wlan_smp2p_out: wlan-ap-to-wpss { 774 qcom,entry-name = "wlan"; 775 #qcom,smem-state-cells = <1>; 776 }; 777 778 wlan_smp2p_in: wlan-wpss-to-ap { 779 qcom,entry-name = "wlan"; 780 interrupt-controller; 781 #interrupt-cells = <2>; 782 }; 783 }; 784 785 pmu { 786 compatible = "arm,armv8-pmuv3"; 787 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 788 }; 789 790 psci { 791 compatible = "arm,psci-1.0"; 792 method = "smc"; 793 }; 794 795 qspi_opp_table: opp-table-qspi { 796 compatible = "operating-points-v2"; 797 798 opp-75000000 { 799 opp-hz = /bits/ 64 <75000000>; 800 required-opps = <&rpmhpd_opp_low_svs>; 801 }; 802 803 opp-150000000 { 804 opp-hz = /bits/ 64 <150000000>; 805 required-opps = <&rpmhpd_opp_svs>; 806 }; 807 808 opp-200000000 { 809 opp-hz = /bits/ 64 <200000000>; 810 required-opps = <&rpmhpd_opp_svs_l1>; 811 }; 812 813 opp-300000000 { 814 opp-hz = /bits/ 64 <300000000>; 815 required-opps = <&rpmhpd_opp_nom>; 816 }; 817 }; 818 819 qup_opp_table: opp-table-qup { 820 compatible = "operating-points-v2"; 821 822 opp-75000000 { 823 opp-hz = /bits/ 64 <75000000>; 824 required-opps = <&rpmhpd_opp_low_svs>; 825 }; 826 827 opp-100000000 { 828 opp-hz = /bits/ 64 <100000000>; 829 required-opps = <&rpmhpd_opp_svs>; 830 }; 831 832 opp-128000000 { 833 opp-hz = /bits/ 64 <128000000>; 834 required-opps = <&rpmhpd_opp_nom>; 835 }; 836 }; 837 838 soc: soc@0 { 839 #address-cells = <2>; 840 #size-cells = <2>; 841 ranges = <0 0 0 0 0x10 0>; 842 dma-ranges = <0 0 0 0 0x10 0>; 843 compatible = "simple-bus"; 844 845 gcc: clock-controller@100000 { 846 compatible = "qcom,gcc-sc7280"; 847 reg = <0 0x00100000 0 0x1f0000>; 848 clocks = <&rpmhcc RPMH_CXO_CLK>, 849 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 850 <0>, <&pcie1_lane>, 851 <0>, <0>, <0>, <0>; 852 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 853 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 854 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 855 "ufs_phy_tx_symbol_0_clk", 856 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 857 #clock-cells = <1>; 858 #reset-cells = <1>; 859 #power-domain-cells = <1>; 860 power-domains = <&rpmhpd SC7280_CX>; 861 }; 862 863 ipcc: mailbox@408000 { 864 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 865 reg = <0 0x00408000 0 0x1000>; 866 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-controller; 868 #interrupt-cells = <3>; 869 #mbox-cells = <2>; 870 }; 871 872 qfprom: efuse@784000 { 873 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 874 reg = <0 0x00784000 0 0xa20>, 875 <0 0x00780000 0 0xa20>, 876 <0 0x00782000 0 0x120>, 877 <0 0x00786000 0 0x1fff>; 878 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 879 clock-names = "core"; 880 power-domains = <&rpmhpd SC7280_MX>; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 884 gpu_speed_bin: gpu_speed_bin@1e9 { 885 reg = <0x1e9 0x2>; 886 bits = <5 8>; 887 }; 888 }; 889 890 sdhc_1: mmc@7c4000 { 891 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 892 pinctrl-names = "default", "sleep"; 893 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 894 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 895 status = "disabled"; 896 897 reg = <0 0x007c4000 0 0x1000>, 898 <0 0x007c5000 0 0x1000>; 899 reg-names = "hc", "cqhci"; 900 901 iommus = <&apps_smmu 0xc0 0x0>; 902 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "hc_irq", "pwr_irq"; 905 906 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 907 <&gcc GCC_SDCC1_APPS_CLK>, 908 <&rpmhcc RPMH_CXO_CLK>; 909 clock-names = "iface", "core", "xo"; 910 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 912 interconnect-names = "sdhc-ddr","cpu-sdhc"; 913 power-domains = <&rpmhpd SC7280_CX>; 914 operating-points-v2 = <&sdhc1_opp_table>; 915 916 bus-width = <8>; 917 supports-cqe; 918 919 qcom,dll-config = <0x0007642c>; 920 qcom,ddr-config = <0x80040868>; 921 922 mmc-ddr-1_8v; 923 mmc-hs200-1_8v; 924 mmc-hs400-1_8v; 925 mmc-hs400-enhanced-strobe; 926 927 resets = <&gcc GCC_SDCC1_BCR>; 928 929 sdhc1_opp_table: opp-table { 930 compatible = "operating-points-v2"; 931 932 opp-100000000 { 933 opp-hz = /bits/ 64 <100000000>; 934 required-opps = <&rpmhpd_opp_low_svs>; 935 opp-peak-kBps = <1800000 400000>; 936 opp-avg-kBps = <100000 0>; 937 }; 938 939 opp-384000000 { 940 opp-hz = /bits/ 64 <384000000>; 941 required-opps = <&rpmhpd_opp_nom>; 942 opp-peak-kBps = <5400000 1600000>; 943 opp-avg-kBps = <390000 0>; 944 }; 945 }; 946 }; 947 948 gpi_dma0: dma-controller@900000 { 949 #dma-cells = <3>; 950 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 951 reg = <0 0x00900000 0 0x60000>; 952 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 964 dma-channels = <12>; 965 dma-channel-mask = <0x7f>; 966 iommus = <&apps_smmu 0x0136 0x0>; 967 status = "disabled"; 968 }; 969 970 qupv3_id_0: geniqup@9c0000 { 971 compatible = "qcom,geni-se-qup"; 972 reg = <0 0x009c0000 0 0x2000>; 973 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 974 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 975 clock-names = "m-ahb", "s-ahb"; 976 #address-cells = <2>; 977 #size-cells = <2>; 978 ranges; 979 iommus = <&apps_smmu 0x123 0x0>; 980 status = "disabled"; 981 982 i2c0: i2c@980000 { 983 compatible = "qcom,geni-i2c"; 984 reg = <0 0x00980000 0 0x4000>; 985 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 986 clock-names = "se"; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_i2c0_data_clk>; 989 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 994 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 995 interconnect-names = "qup-core", "qup-config", 996 "qup-memory"; 997 power-domains = <&rpmhpd SC7280_CX>; 998 required-opps = <&rpmhpd_opp_low_svs>; 999 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1000 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1001 dma-names = "tx", "rx"; 1002 status = "disabled"; 1003 }; 1004 1005 spi0: spi@980000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00980000 0 0x4000>; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1009 clock-names = "se"; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1012 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 power-domains = <&rpmhpd SC7280_CX>; 1016 operating-points-v2 = <&qup_opp_table>; 1017 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1019 interconnect-names = "qup-core", "qup-config"; 1020 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1021 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1022 dma-names = "tx", "rx"; 1023 status = "disabled"; 1024 }; 1025 1026 uart0: serial@980000 { 1027 compatible = "qcom,geni-uart"; 1028 reg = <0 0x00980000 0 0x4000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1030 clock-names = "se"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1033 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1034 power-domains = <&rpmhpd SC7280_CX>; 1035 operating-points-v2 = <&qup_opp_table>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1038 interconnect-names = "qup-core", "qup-config"; 1039 status = "disabled"; 1040 }; 1041 1042 i2c1: i2c@984000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00984000 0 0x4000>; 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1046 clock-names = "se"; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c1_data_clk>; 1049 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1053 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1054 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1055 interconnect-names = "qup-core", "qup-config", 1056 "qup-memory"; 1057 power-domains = <&rpmhpd SC7280_CX>; 1058 required-opps = <&rpmhpd_opp_low_svs>; 1059 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1060 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1061 dma-names = "tx", "rx"; 1062 status = "disabled"; 1063 }; 1064 1065 spi1: spi@984000 { 1066 compatible = "qcom,geni-spi"; 1067 reg = <0 0x00984000 0 0x4000>; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1069 clock-names = "se"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1072 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 power-domains = <&rpmhpd SC7280_CX>; 1076 operating-points-v2 = <&qup_opp_table>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1079 interconnect-names = "qup-core", "qup-config"; 1080 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1081 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1082 dma-names = "tx", "rx"; 1083 status = "disabled"; 1084 }; 1085 1086 uart1: serial@984000 { 1087 compatible = "qcom,geni-uart"; 1088 reg = <0 0x00984000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1093 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1094 power-domains = <&rpmhpd SC7280_CX>; 1095 operating-points-v2 = <&qup_opp_table>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1098 interconnect-names = "qup-core", "qup-config"; 1099 status = "disabled"; 1100 }; 1101 1102 i2c2: i2c@988000 { 1103 compatible = "qcom,geni-i2c"; 1104 reg = <0 0x00988000 0 0x4000>; 1105 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1106 clock-names = "se"; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&qup_i2c2_data_clk>; 1109 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1113 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1114 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1115 interconnect-names = "qup-core", "qup-config", 1116 "qup-memory"; 1117 power-domains = <&rpmhpd SC7280_CX>; 1118 required-opps = <&rpmhpd_opp_low_svs>; 1119 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1120 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1121 dma-names = "tx", "rx"; 1122 status = "disabled"; 1123 }; 1124 1125 spi2: spi@988000 { 1126 compatible = "qcom,geni-spi"; 1127 reg = <0 0x00988000 0 0x4000>; 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1129 clock-names = "se"; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1132 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 power-domains = <&rpmhpd SC7280_CX>; 1136 operating-points-v2 = <&qup_opp_table>; 1137 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1138 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1139 interconnect-names = "qup-core", "qup-config"; 1140 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1141 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1142 dma-names = "tx", "rx"; 1143 status = "disabled"; 1144 }; 1145 1146 uart2: serial@988000 { 1147 compatible = "qcom,geni-uart"; 1148 reg = <0 0x00988000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1153 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1154 power-domains = <&rpmhpd SC7280_CX>; 1155 operating-points-v2 = <&qup_opp_table>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1158 interconnect-names = "qup-core", "qup-config"; 1159 status = "disabled"; 1160 }; 1161 1162 i2c3: i2c@98c000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0 0x0098c000 0 0x4000>; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1166 clock-names = "se"; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&qup_i2c3_data_clk>; 1169 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1173 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1175 interconnect-names = "qup-core", "qup-config", 1176 "qup-memory"; 1177 power-domains = <&rpmhpd SC7280_CX>; 1178 required-opps = <&rpmhpd_opp_low_svs>; 1179 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1180 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1181 dma-names = "tx", "rx"; 1182 status = "disabled"; 1183 }; 1184 1185 spi3: spi@98c000 { 1186 compatible = "qcom,geni-spi"; 1187 reg = <0 0x0098c000 0 0x4000>; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1189 clock-names = "se"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1192 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 power-domains = <&rpmhpd SC7280_CX>; 1196 operating-points-v2 = <&qup_opp_table>; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1201 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1202 dma-names = "tx", "rx"; 1203 status = "disabled"; 1204 }; 1205 1206 uart3: serial@98c000 { 1207 compatible = "qcom,geni-uart"; 1208 reg = <0 0x0098c000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1213 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1214 power-domains = <&rpmhpd SC7280_CX>; 1215 operating-points-v2 = <&qup_opp_table>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1218 interconnect-names = "qup-core", "qup-config"; 1219 status = "disabled"; 1220 }; 1221 1222 i2c4: i2c@990000 { 1223 compatible = "qcom,geni-i2c"; 1224 reg = <0 0x00990000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1226 clock-names = "se"; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_i2c4_data_clk>; 1229 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1233 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1234 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1235 interconnect-names = "qup-core", "qup-config", 1236 "qup-memory"; 1237 power-domains = <&rpmhpd SC7280_CX>; 1238 required-opps = <&rpmhpd_opp_low_svs>; 1239 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1240 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1241 dma-names = "tx", "rx"; 1242 status = "disabled"; 1243 }; 1244 1245 spi4: spi@990000 { 1246 compatible = "qcom,geni-spi"; 1247 reg = <0 0x00990000 0 0x4000>; 1248 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1249 clock-names = "se"; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1252 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 power-domains = <&rpmhpd SC7280_CX>; 1256 operating-points-v2 = <&qup_opp_table>; 1257 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1258 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1259 interconnect-names = "qup-core", "qup-config"; 1260 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1261 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 uart4: serial@990000 { 1267 compatible = "qcom,geni-uart"; 1268 reg = <0 0x00990000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1273 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1274 power-domains = <&rpmhpd SC7280_CX>; 1275 operating-points-v2 = <&qup_opp_table>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1278 interconnect-names = "qup-core", "qup-config"; 1279 status = "disabled"; 1280 }; 1281 1282 i2c5: i2c@994000 { 1283 compatible = "qcom,geni-i2c"; 1284 reg = <0 0x00994000 0 0x4000>; 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1286 clock-names = "se"; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&qup_i2c5_data_clk>; 1289 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1293 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1294 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1295 interconnect-names = "qup-core", "qup-config", 1296 "qup-memory"; 1297 power-domains = <&rpmhpd SC7280_CX>; 1298 required-opps = <&rpmhpd_opp_low_svs>; 1299 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1300 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1301 dma-names = "tx", "rx"; 1302 status = "disabled"; 1303 }; 1304 1305 spi5: spi@994000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0 0x00994000 0 0x4000>; 1308 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1309 clock-names = "se"; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1312 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 power-domains = <&rpmhpd SC7280_CX>; 1316 operating-points-v2 = <&qup_opp_table>; 1317 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1318 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1319 interconnect-names = "qup-core", "qup-config"; 1320 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1321 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1322 dma-names = "tx", "rx"; 1323 status = "disabled"; 1324 }; 1325 1326 uart5: serial@994000 { 1327 compatible = "qcom,geni-uart"; 1328 reg = <0 0x00994000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1333 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1334 power-domains = <&rpmhpd SC7280_CX>; 1335 operating-points-v2 = <&qup_opp_table>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1338 interconnect-names = "qup-core", "qup-config"; 1339 status = "disabled"; 1340 }; 1341 1342 i2c6: i2c@998000 { 1343 compatible = "qcom,geni-i2c"; 1344 reg = <0 0x00998000 0 0x4000>; 1345 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1346 clock-names = "se"; 1347 pinctrl-names = "default"; 1348 pinctrl-0 = <&qup_i2c6_data_clk>; 1349 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1354 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", 1356 "qup-memory"; 1357 power-domains = <&rpmhpd SC7280_CX>; 1358 required-opps = <&rpmhpd_opp_low_svs>; 1359 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1360 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1361 dma-names = "tx", "rx"; 1362 status = "disabled"; 1363 }; 1364 1365 spi6: spi@998000 { 1366 compatible = "qcom,geni-spi"; 1367 reg = <0 0x00998000 0 0x4000>; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1369 clock-names = "se"; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1372 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 power-domains = <&rpmhpd SC7280_CX>; 1376 operating-points-v2 = <&qup_opp_table>; 1377 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1379 interconnect-names = "qup-core", "qup-config"; 1380 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1381 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1382 dma-names = "tx", "rx"; 1383 status = "disabled"; 1384 }; 1385 1386 uart6: serial@998000 { 1387 compatible = "qcom,geni-uart"; 1388 reg = <0 0x00998000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1393 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1394 power-domains = <&rpmhpd SC7280_CX>; 1395 operating-points-v2 = <&qup_opp_table>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1398 interconnect-names = "qup-core", "qup-config"; 1399 status = "disabled"; 1400 }; 1401 1402 i2c7: i2c@99c000 { 1403 compatible = "qcom,geni-i2c"; 1404 reg = <0 0x0099c000 0 0x4000>; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1406 clock-names = "se"; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_i2c7_data_clk>; 1409 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1413 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1414 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1415 interconnect-names = "qup-core", "qup-config", 1416 "qup-memory"; 1417 power-domains = <&rpmhpd SC7280_CX>; 1418 required-opps = <&rpmhpd_opp_low_svs>; 1419 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1420 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1421 dma-names = "tx", "rx"; 1422 status = "disabled"; 1423 }; 1424 1425 spi7: spi@99c000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x0099c000 0 0x4000>; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1429 clock-names = "se"; 1430 pinctrl-names = "default"; 1431 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1432 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 power-domains = <&rpmhpd SC7280_CX>; 1436 operating-points-v2 = <&qup_opp_table>; 1437 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1438 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1439 interconnect-names = "qup-core", "qup-config"; 1440 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1441 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1442 dma-names = "tx", "rx"; 1443 status = "disabled"; 1444 }; 1445 1446 uart7: serial@99c000 { 1447 compatible = "qcom,geni-uart"; 1448 reg = <0 0x0099c000 0 0x4000>; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1450 clock-names = "se"; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1453 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1454 power-domains = <&rpmhpd SC7280_CX>; 1455 operating-points-v2 = <&qup_opp_table>; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1457 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1458 interconnect-names = "qup-core", "qup-config"; 1459 status = "disabled"; 1460 }; 1461 }; 1462 1463 gpi_dma1: dma-controller@a00000 { 1464 #dma-cells = <3>; 1465 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1466 reg = <0 0x00a00000 0 0x60000>; 1467 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1479 dma-channels = <12>; 1480 dma-channel-mask = <0x1e>; 1481 iommus = <&apps_smmu 0x56 0x0>; 1482 status = "disabled"; 1483 }; 1484 1485 qupv3_id_1: geniqup@ac0000 { 1486 compatible = "qcom,geni-se-qup"; 1487 reg = <0 0x00ac0000 0 0x2000>; 1488 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1489 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1490 clock-names = "m-ahb", "s-ahb"; 1491 #address-cells = <2>; 1492 #size-cells = <2>; 1493 ranges; 1494 iommus = <&apps_smmu 0x43 0x0>; 1495 status = "disabled"; 1496 1497 i2c8: i2c@a80000 { 1498 compatible = "qcom,geni-i2c"; 1499 reg = <0 0x00a80000 0 0x4000>; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1501 clock-names = "se"; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_i2c8_data_clk>; 1504 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1508 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1509 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1510 interconnect-names = "qup-core", "qup-config", 1511 "qup-memory"; 1512 power-domains = <&rpmhpd SC7280_CX>; 1513 required-opps = <&rpmhpd_opp_low_svs>; 1514 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1515 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1516 dma-names = "tx", "rx"; 1517 status = "disabled"; 1518 }; 1519 1520 spi8: spi@a80000 { 1521 compatible = "qcom,geni-spi"; 1522 reg = <0 0x00a80000 0 0x4000>; 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1524 clock-names = "se"; 1525 pinctrl-names = "default"; 1526 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1527 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 power-domains = <&rpmhpd SC7280_CX>; 1531 operating-points-v2 = <&qup_opp_table>; 1532 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1533 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1534 interconnect-names = "qup-core", "qup-config"; 1535 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1536 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1537 dma-names = "tx", "rx"; 1538 status = "disabled"; 1539 }; 1540 1541 uart8: serial@a80000 { 1542 compatible = "qcom,geni-uart"; 1543 reg = <0 0x00a80000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1548 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1549 power-domains = <&rpmhpd SC7280_CX>; 1550 operating-points-v2 = <&qup_opp_table>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1552 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1553 interconnect-names = "qup-core", "qup-config"; 1554 status = "disabled"; 1555 }; 1556 1557 i2c9: i2c@a84000 { 1558 compatible = "qcom,geni-i2c"; 1559 reg = <0 0x00a84000 0 0x4000>; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1561 clock-names = "se"; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&qup_i2c9_data_clk>; 1564 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1568 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1569 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1570 interconnect-names = "qup-core", "qup-config", 1571 "qup-memory"; 1572 power-domains = <&rpmhpd SC7280_CX>; 1573 required-opps = <&rpmhpd_opp_low_svs>; 1574 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1575 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1576 dma-names = "tx", "rx"; 1577 status = "disabled"; 1578 }; 1579 1580 spi9: spi@a84000 { 1581 compatible = "qcom,geni-spi"; 1582 reg = <0 0x00a84000 0 0x4000>; 1583 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1584 clock-names = "se"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1587 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 power-domains = <&rpmhpd SC7280_CX>; 1591 operating-points-v2 = <&qup_opp_table>; 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1593 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1594 interconnect-names = "qup-core", "qup-config"; 1595 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1596 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1597 dma-names = "tx", "rx"; 1598 status = "disabled"; 1599 }; 1600 1601 uart9: serial@a84000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0 0x00a84000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1605 clock-names = "se"; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1608 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1609 power-domains = <&rpmhpd SC7280_CX>; 1610 operating-points-v2 = <&qup_opp_table>; 1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1612 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1613 interconnect-names = "qup-core", "qup-config"; 1614 status = "disabled"; 1615 }; 1616 1617 i2c10: i2c@a88000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0 0x00a88000 0 0x4000>; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 clock-names = "se"; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_i2c10_data_clk>; 1624 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1628 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1629 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1630 interconnect-names = "qup-core", "qup-config", 1631 "qup-memory"; 1632 power-domains = <&rpmhpd SC7280_CX>; 1633 required-opps = <&rpmhpd_opp_low_svs>; 1634 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1635 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1636 dma-names = "tx", "rx"; 1637 status = "disabled"; 1638 }; 1639 1640 spi10: spi@a88000 { 1641 compatible = "qcom,geni-spi"; 1642 reg = <0 0x00a88000 0 0x4000>; 1643 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1644 clock-names = "se"; 1645 pinctrl-names = "default"; 1646 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1647 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1648 #address-cells = <1>; 1649 #size-cells = <0>; 1650 power-domains = <&rpmhpd SC7280_CX>; 1651 operating-points-v2 = <&qup_opp_table>; 1652 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1654 interconnect-names = "qup-core", "qup-config"; 1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1656 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1657 dma-names = "tx", "rx"; 1658 status = "disabled"; 1659 }; 1660 1661 uart10: serial@a88000 { 1662 compatible = "qcom,geni-uart"; 1663 reg = <0 0x00a88000 0 0x4000>; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1665 clock-names = "se"; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1669 power-domains = <&rpmhpd SC7280_CX>; 1670 operating-points-v2 = <&qup_opp_table>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1673 interconnect-names = "qup-core", "qup-config"; 1674 status = "disabled"; 1675 }; 1676 1677 i2c11: i2c@a8c000 { 1678 compatible = "qcom,geni-i2c"; 1679 reg = <0 0x00a8c000 0 0x4000>; 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1681 clock-names = "se"; 1682 pinctrl-names = "default"; 1683 pinctrl-0 = <&qup_i2c11_data_clk>; 1684 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1688 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1689 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1690 interconnect-names = "qup-core", "qup-config", 1691 "qup-memory"; 1692 power-domains = <&rpmhpd SC7280_CX>; 1693 required-opps = <&rpmhpd_opp_low_svs>; 1694 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1695 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1696 dma-names = "tx", "rx"; 1697 status = "disabled"; 1698 }; 1699 1700 spi11: spi@a8c000 { 1701 compatible = "qcom,geni-spi"; 1702 reg = <0 0x00a8c000 0 0x4000>; 1703 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1704 clock-names = "se"; 1705 pinctrl-names = "default"; 1706 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1707 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 power-domains = <&rpmhpd SC7280_CX>; 1711 operating-points-v2 = <&qup_opp_table>; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1714 interconnect-names = "qup-core", "qup-config"; 1715 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1716 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1717 dma-names = "tx", "rx"; 1718 status = "disabled"; 1719 }; 1720 1721 uart11: serial@a8c000 { 1722 compatible = "qcom,geni-uart"; 1723 reg = <0 0x00a8c000 0 0x4000>; 1724 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1725 clock-names = "se"; 1726 pinctrl-names = "default"; 1727 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1728 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1729 power-domains = <&rpmhpd SC7280_CX>; 1730 operating-points-v2 = <&qup_opp_table>; 1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1732 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1733 interconnect-names = "qup-core", "qup-config"; 1734 status = "disabled"; 1735 }; 1736 1737 i2c12: i2c@a90000 { 1738 compatible = "qcom,geni-i2c"; 1739 reg = <0 0x00a90000 0 0x4000>; 1740 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1741 clock-names = "se"; 1742 pinctrl-names = "default"; 1743 pinctrl-0 = <&qup_i2c12_data_clk>; 1744 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1748 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1749 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1750 interconnect-names = "qup-core", "qup-config", 1751 "qup-memory"; 1752 power-domains = <&rpmhpd SC7280_CX>; 1753 required-opps = <&rpmhpd_opp_low_svs>; 1754 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1755 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1756 dma-names = "tx", "rx"; 1757 status = "disabled"; 1758 }; 1759 1760 spi12: spi@a90000 { 1761 compatible = "qcom,geni-spi"; 1762 reg = <0 0x00a90000 0 0x4000>; 1763 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1764 clock-names = "se"; 1765 pinctrl-names = "default"; 1766 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1767 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 power-domains = <&rpmhpd SC7280_CX>; 1771 operating-points-v2 = <&qup_opp_table>; 1772 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1773 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1774 interconnect-names = "qup-core", "qup-config"; 1775 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1776 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1777 dma-names = "tx", "rx"; 1778 status = "disabled"; 1779 }; 1780 1781 uart12: serial@a90000 { 1782 compatible = "qcom,geni-uart"; 1783 reg = <0 0x00a90000 0 0x4000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1785 clock-names = "se"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1788 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1789 power-domains = <&rpmhpd SC7280_CX>; 1790 operating-points-v2 = <&qup_opp_table>; 1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1792 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1793 interconnect-names = "qup-core", "qup-config"; 1794 status = "disabled"; 1795 }; 1796 1797 i2c13: i2c@a94000 { 1798 compatible = "qcom,geni-i2c"; 1799 reg = <0 0x00a94000 0 0x4000>; 1800 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1801 clock-names = "se"; 1802 pinctrl-names = "default"; 1803 pinctrl-0 = <&qup_i2c13_data_clk>; 1804 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1808 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1809 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1810 interconnect-names = "qup-core", "qup-config", 1811 "qup-memory"; 1812 power-domains = <&rpmhpd SC7280_CX>; 1813 required-opps = <&rpmhpd_opp_low_svs>; 1814 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1815 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1816 dma-names = "tx", "rx"; 1817 status = "disabled"; 1818 }; 1819 1820 spi13: spi@a94000 { 1821 compatible = "qcom,geni-spi"; 1822 reg = <0 0x00a94000 0 0x4000>; 1823 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1824 clock-names = "se"; 1825 pinctrl-names = "default"; 1826 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1827 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 power-domains = <&rpmhpd SC7280_CX>; 1831 operating-points-v2 = <&qup_opp_table>; 1832 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1833 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1834 interconnect-names = "qup-core", "qup-config"; 1835 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1836 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1837 dma-names = "tx", "rx"; 1838 status = "disabled"; 1839 }; 1840 1841 uart13: serial@a94000 { 1842 compatible = "qcom,geni-uart"; 1843 reg = <0 0x00a94000 0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1845 clock-names = "se"; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1848 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1849 power-domains = <&rpmhpd SC7280_CX>; 1850 operating-points-v2 = <&qup_opp_table>; 1851 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1852 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1853 interconnect-names = "qup-core", "qup-config"; 1854 status = "disabled"; 1855 }; 1856 1857 i2c14: i2c@a98000 { 1858 compatible = "qcom,geni-i2c"; 1859 reg = <0 0x00a98000 0 0x4000>; 1860 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1861 clock-names = "se"; 1862 pinctrl-names = "default"; 1863 pinctrl-0 = <&qup_i2c14_data_clk>; 1864 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1868 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1869 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1870 interconnect-names = "qup-core", "qup-config", 1871 "qup-memory"; 1872 power-domains = <&rpmhpd SC7280_CX>; 1873 required-opps = <&rpmhpd_opp_low_svs>; 1874 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1875 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1876 dma-names = "tx", "rx"; 1877 status = "disabled"; 1878 }; 1879 1880 spi14: spi@a98000 { 1881 compatible = "qcom,geni-spi"; 1882 reg = <0 0x00a98000 0 0x4000>; 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1884 clock-names = "se"; 1885 pinctrl-names = "default"; 1886 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1887 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 power-domains = <&rpmhpd SC7280_CX>; 1891 operating-points-v2 = <&qup_opp_table>; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1893 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1894 interconnect-names = "qup-core", "qup-config"; 1895 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1896 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1897 dma-names = "tx", "rx"; 1898 status = "disabled"; 1899 }; 1900 1901 uart14: serial@a98000 { 1902 compatible = "qcom,geni-uart"; 1903 reg = <0 0x00a98000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1908 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1909 power-domains = <&rpmhpd SC7280_CX>; 1910 operating-points-v2 = <&qup_opp_table>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1913 interconnect-names = "qup-core", "qup-config"; 1914 status = "disabled"; 1915 }; 1916 1917 i2c15: i2c@a9c000 { 1918 compatible = "qcom,geni-i2c"; 1919 reg = <0 0x00a9c000 0 0x4000>; 1920 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1921 clock-names = "se"; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&qup_i2c15_data_clk>; 1924 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1928 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1929 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1930 interconnect-names = "qup-core", "qup-config", 1931 "qup-memory"; 1932 power-domains = <&rpmhpd SC7280_CX>; 1933 required-opps = <&rpmhpd_opp_low_svs>; 1934 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1935 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1936 dma-names = "tx", "rx"; 1937 status = "disabled"; 1938 }; 1939 1940 spi15: spi@a9c000 { 1941 compatible = "qcom,geni-spi"; 1942 reg = <0 0x00a9c000 0 0x4000>; 1943 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1944 clock-names = "se"; 1945 pinctrl-names = "default"; 1946 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1947 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1948 #address-cells = <1>; 1949 #size-cells = <0>; 1950 power-domains = <&rpmhpd SC7280_CX>; 1951 operating-points-v2 = <&qup_opp_table>; 1952 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1953 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1954 interconnect-names = "qup-core", "qup-config"; 1955 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1956 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1957 dma-names = "tx", "rx"; 1958 status = "disabled"; 1959 }; 1960 1961 uart15: serial@a9c000 { 1962 compatible = "qcom,geni-uart"; 1963 reg = <0 0x00a9c000 0 0x4000>; 1964 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1965 clock-names = "se"; 1966 pinctrl-names = "default"; 1967 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1968 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1969 power-domains = <&rpmhpd SC7280_CX>; 1970 operating-points-v2 = <&qup_opp_table>; 1971 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1972 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1973 interconnect-names = "qup-core", "qup-config"; 1974 status = "disabled"; 1975 }; 1976 }; 1977 1978 cnoc2: interconnect@1500000 { 1979 reg = <0 0x01500000 0 0x1000>; 1980 compatible = "qcom,sc7280-cnoc2"; 1981 #interconnect-cells = <2>; 1982 qcom,bcm-voters = <&apps_bcm_voter>; 1983 }; 1984 1985 cnoc3: interconnect@1502000 { 1986 reg = <0 0x01502000 0 0x1000>; 1987 compatible = "qcom,sc7280-cnoc3"; 1988 #interconnect-cells = <2>; 1989 qcom,bcm-voters = <&apps_bcm_voter>; 1990 }; 1991 1992 mc_virt: interconnect@1580000 { 1993 reg = <0 0x01580000 0 0x4>; 1994 compatible = "qcom,sc7280-mc-virt"; 1995 #interconnect-cells = <2>; 1996 qcom,bcm-voters = <&apps_bcm_voter>; 1997 }; 1998 1999 system_noc: interconnect@1680000 { 2000 reg = <0 0x01680000 0 0x15480>; 2001 compatible = "qcom,sc7280-system-noc"; 2002 #interconnect-cells = <2>; 2003 qcom,bcm-voters = <&apps_bcm_voter>; 2004 }; 2005 2006 aggre1_noc: interconnect@16e0000 { 2007 compatible = "qcom,sc7280-aggre1-noc"; 2008 reg = <0 0x016e0000 0 0x1c080>; 2009 #interconnect-cells = <2>; 2010 qcom,bcm-voters = <&apps_bcm_voter>; 2011 }; 2012 2013 aggre2_noc: interconnect@1700000 { 2014 reg = <0 0x01700000 0 0x2b080>; 2015 compatible = "qcom,sc7280-aggre2-noc"; 2016 #interconnect-cells = <2>; 2017 qcom,bcm-voters = <&apps_bcm_voter>; 2018 }; 2019 2020 mmss_noc: interconnect@1740000 { 2021 reg = <0 0x01740000 0 0x1e080>; 2022 compatible = "qcom,sc7280-mmss-noc"; 2023 #interconnect-cells = <2>; 2024 qcom,bcm-voters = <&apps_bcm_voter>; 2025 }; 2026 2027 wifi: wifi@17a10040 { 2028 compatible = "qcom,wcn6750-wifi"; 2029 reg = <0 0x17a10040 0 0x0>; 2030 iommus = <&apps_smmu 0x1c00 0x1>; 2031 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2063 qcom,rproc = <&remoteproc_wpss>; 2064 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2065 status = "disabled"; 2066 qcom,smem-states = <&wlan_smp2p_out 0>; 2067 qcom,smem-state-names = "wlan-smp2p-out"; 2068 }; 2069 2070 pcie1: pci@1c08000 { 2071 compatible = "qcom,pcie-sc7280"; 2072 reg = <0 0x01c08000 0 0x3000>, 2073 <0 0x40000000 0 0xf1d>, 2074 <0 0x40000f20 0 0xa8>, 2075 <0 0x40001000 0 0x1000>, 2076 <0 0x40100000 0 0x100000>; 2077 2078 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2079 device_type = "pci"; 2080 linux,pci-domain = <1>; 2081 bus-range = <0x00 0xff>; 2082 num-lanes = <2>; 2083 2084 #address-cells = <3>; 2085 #size-cells = <2>; 2086 2087 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2088 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2089 2090 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2091 interrupt-names = "msi"; 2092 #interrupt-cells = <1>; 2093 interrupt-map-mask = <0 0 0 0x7>; 2094 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2095 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2096 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2097 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2098 2099 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2100 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2101 <&pcie1_lane>, 2102 <&rpmhcc RPMH_CXO_CLK>, 2103 <&gcc GCC_PCIE_1_AUX_CLK>, 2104 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2105 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2106 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2107 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2108 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2109 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2110 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2111 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2112 2113 clock-names = "pipe", 2114 "pipe_mux", 2115 "phy_pipe", 2116 "ref", 2117 "aux", 2118 "cfg", 2119 "bus_master", 2120 "bus_slave", 2121 "slave_q2a", 2122 "tbu", 2123 "ddrss_sf_tbu", 2124 "aggre0", 2125 "aggre1"; 2126 2127 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2128 assigned-clock-rates = <19200000>; 2129 2130 resets = <&gcc GCC_PCIE_1_BCR>; 2131 reset-names = "pci"; 2132 2133 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2134 2135 phys = <&pcie1_lane>; 2136 phy-names = "pciephy"; 2137 2138 pinctrl-names = "default"; 2139 pinctrl-0 = <&pcie1_clkreq_n>; 2140 2141 dma-coherent; 2142 2143 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2144 <0x100 &apps_smmu 0x1c81 0x1>; 2145 2146 status = "disabled"; 2147 }; 2148 2149 pcie1_phy: phy@1c0e000 { 2150 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2151 reg = <0 0x01c0e000 0 0x1c0>; 2152 #address-cells = <2>; 2153 #size-cells = <2>; 2154 ranges; 2155 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2156 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2157 <&gcc GCC_PCIE_CLKREF_EN>, 2158 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2159 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2160 2161 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2162 reset-names = "phy"; 2163 2164 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2165 assigned-clock-rates = <100000000>; 2166 2167 status = "disabled"; 2168 2169 pcie1_lane: phy@1c0e200 { 2170 reg = <0 0x01c0e200 0 0x170>, 2171 <0 0x01c0e400 0 0x200>, 2172 <0 0x01c0ea00 0 0x1f0>, 2173 <0 0x01c0e600 0 0x170>, 2174 <0 0x01c0e800 0 0x200>, 2175 <0 0x01c0ee00 0 0xf4>; 2176 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2177 clock-names = "pipe0"; 2178 2179 #phy-cells = <0>; 2180 #clock-cells = <0>; 2181 clock-output-names = "pcie_1_pipe_clk"; 2182 }; 2183 }; 2184 2185 ipa: ipa@1e40000 { 2186 compatible = "qcom,sc7280-ipa"; 2187 2188 iommus = <&apps_smmu 0x480 0x0>, 2189 <&apps_smmu 0x482 0x0>; 2190 reg = <0 0x01e40000 0 0x8000>, 2191 <0 0x01e50000 0 0x4ad0>, 2192 <0 0x01e04000 0 0x23000>; 2193 reg-names = "ipa-reg", 2194 "ipa-shared", 2195 "gsi"; 2196 2197 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2198 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2199 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2200 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2201 interrupt-names = "ipa", 2202 "gsi", 2203 "ipa-clock-query", 2204 "ipa-setup-ready"; 2205 2206 clocks = <&rpmhcc RPMH_IPA_CLK>; 2207 clock-names = "core"; 2208 2209 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2211 interconnect-names = "memory", 2212 "config"; 2213 2214 qcom,qmp = <&aoss_qmp>; 2215 2216 qcom,smem-states = <&ipa_smp2p_out 0>, 2217 <&ipa_smp2p_out 1>; 2218 qcom,smem-state-names = "ipa-clock-enabled-valid", 2219 "ipa-clock-enabled"; 2220 2221 status = "disabled"; 2222 }; 2223 2224 tcsr_mutex: hwlock@1f40000 { 2225 compatible = "qcom,tcsr-mutex"; 2226 reg = <0 0x01f40000 0 0x20000>; 2227 #hwlock-cells = <1>; 2228 }; 2229 2230 tcsr_1: syscon@1f60000 { 2231 compatible = "qcom,sc7280-tcsr", "syscon"; 2232 reg = <0 0x01f60000 0 0x20000>; 2233 }; 2234 2235 tcsr_2: syscon@1fc0000 { 2236 compatible = "qcom,sc7280-tcsr", "syscon"; 2237 reg = <0 0x01fc0000 0 0x30000>; 2238 }; 2239 2240 lpasscc: lpasscc@3000000 { 2241 compatible = "qcom,sc7280-lpasscc"; 2242 reg = <0 0x03000000 0 0x40>, 2243 <0 0x03c04000 0 0x4>; 2244 reg-names = "qdsp6ss", "top_cc"; 2245 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2246 clock-names = "iface"; 2247 #clock-cells = <1>; 2248 }; 2249 2250 lpass_rx_macro: codec@3200000 { 2251 compatible = "qcom,sc7280-lpass-rx-macro"; 2252 reg = <0 0x03200000 0 0x1000>; 2253 2254 pinctrl-names = "default"; 2255 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2256 2257 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2258 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2259 <&lpass_va_macro>; 2260 clock-names = "mclk", "npl", "fsgen"; 2261 2262 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2263 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2264 power-domain-names = "macro", "dcodec"; 2265 2266 #clock-cells = <0>; 2267 #sound-dai-cells = <1>; 2268 2269 status = "disabled"; 2270 }; 2271 2272 swr0: soundwire@3210000 { 2273 compatible = "qcom,soundwire-v1.6.0"; 2274 reg = <0 0x03210000 0 0x2000>; 2275 2276 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2277 clocks = <&lpass_rx_macro>; 2278 clock-names = "iface"; 2279 2280 qcom,din-ports = <0>; 2281 qcom,dout-ports = <5>; 2282 2283 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2284 reset-names = "swr_audio_cgcr"; 2285 2286 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2287 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2288 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2289 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2290 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2291 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2292 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2293 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2294 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2295 2296 #sound-dai-cells = <1>; 2297 #address-cells = <2>; 2298 #size-cells = <0>; 2299 2300 status = "disabled"; 2301 }; 2302 2303 lpass_tx_macro: codec@3220000 { 2304 compatible = "qcom,sc7280-lpass-tx-macro"; 2305 reg = <0 0x03220000 0 0x1000>; 2306 2307 pinctrl-names = "default"; 2308 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2309 2310 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2311 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2312 <&lpass_va_macro>; 2313 clock-names = "mclk", "npl", "fsgen"; 2314 2315 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2316 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2317 power-domain-names = "macro", "dcodec"; 2318 2319 #clock-cells = <0>; 2320 #sound-dai-cells = <1>; 2321 2322 status = "disabled"; 2323 }; 2324 2325 swr1: soundwire@3230000 { 2326 compatible = "qcom,soundwire-v1.6.0"; 2327 reg = <0 0x03230000 0 0x2000>; 2328 2329 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2330 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2331 clocks = <&lpass_tx_macro>; 2332 clock-names = "iface"; 2333 2334 qcom,din-ports = <3>; 2335 qcom,dout-ports = <0>; 2336 2337 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2338 reset-names = "swr_audio_cgcr"; 2339 2340 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2341 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2342 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2343 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2344 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2345 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2346 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2347 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2348 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2349 2350 #sound-dai-cells = <1>; 2351 #address-cells = <2>; 2352 #size-cells = <0>; 2353 2354 status = "disabled"; 2355 }; 2356 2357 lpass_audiocc: clock-controller@3300000 { 2358 compatible = "qcom,sc7280-lpassaudiocc"; 2359 reg = <0 0x03300000 0 0x30000>, 2360 <0 0x032a9000 0 0x1000>; 2361 clocks = <&rpmhcc RPMH_CXO_CLK>, 2362 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2363 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2364 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2365 #clock-cells = <1>; 2366 #power-domain-cells = <1>; 2367 #reset-cells = <1>; 2368 }; 2369 2370 lpass_va_macro: codec@3370000 { 2371 compatible = "qcom,sc7280-lpass-va-macro"; 2372 reg = <0 0x03370000 0 0x1000>; 2373 2374 pinctrl-names = "default"; 2375 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2376 2377 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2378 clock-names = "mclk"; 2379 2380 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2381 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2382 power-domain-names = "macro", "dcodec"; 2383 2384 #clock-cells = <0>; 2385 #sound-dai-cells = <1>; 2386 2387 status = "disabled"; 2388 }; 2389 2390 lpass_aon: clock-controller@3380000 { 2391 compatible = "qcom,sc7280-lpassaoncc"; 2392 reg = <0 0x03380000 0 0x30000>; 2393 clocks = <&rpmhcc RPMH_CXO_CLK>, 2394 <&rpmhcc RPMH_CXO_CLK_A>, 2395 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2396 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2397 #clock-cells = <1>; 2398 #power-domain-cells = <1>; 2399 }; 2400 2401 lpass_core: clock-controller@3900000 { 2402 compatible = "qcom,sc7280-lpasscorecc"; 2403 reg = <0 0x03900000 0 0x50000>; 2404 clocks = <&rpmhcc RPMH_CXO_CLK>; 2405 clock-names = "bi_tcxo"; 2406 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2407 #clock-cells = <1>; 2408 #power-domain-cells = <1>; 2409 }; 2410 2411 lpass_cpu: audio@3987000 { 2412 compatible = "qcom,sc7280-lpass-cpu"; 2413 2414 reg = <0 0x03987000 0 0x68000>, 2415 <0 0x03b00000 0 0x29000>, 2416 <0 0x03260000 0 0xc000>, 2417 <0 0x03280000 0 0x29000>, 2418 <0 0x03340000 0 0x29000>, 2419 <0 0x0336c000 0 0x3000>; 2420 reg-names = "lpass-hdmiif", 2421 "lpass-lpaif", 2422 "lpass-rxtx-cdc-dma-lpm", 2423 "lpass-rxtx-lpaif", 2424 "lpass-va-lpaif", 2425 "lpass-va-cdc-dma-lpm"; 2426 2427 iommus = <&apps_smmu 0x1820 0>, 2428 <&apps_smmu 0x1821 0>, 2429 <&apps_smmu 0x1832 0>; 2430 2431 power-domains = <&rpmhpd SC7280_LCX>; 2432 power-domain-names = "lcx"; 2433 required-opps = <&rpmhpd_opp_nom>; 2434 2435 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2436 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2437 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2438 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2439 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2440 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2441 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2442 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2443 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2444 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2445 clock-names = "aon_cc_audio_hm_h", 2446 "audio_cc_ext_mclk0", 2447 "core_cc_sysnoc_mport_core", 2448 "core_cc_ext_if0_ibit", 2449 "core_cc_ext_if1_ibit", 2450 "audio_cc_codec_mem", 2451 "audio_cc_codec_mem0", 2452 "audio_cc_codec_mem1", 2453 "audio_cc_codec_mem2", 2454 "aon_cc_va_mem0"; 2455 2456 #sound-dai-cells = <1>; 2457 #address-cells = <1>; 2458 #size-cells = <0>; 2459 2460 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2464 interrupt-names = "lpass-irq-lpaif", 2465 "lpass-irq-hdmi", 2466 "lpass-irq-vaif", 2467 "lpass-irq-rxtxif"; 2468 2469 status = "disabled"; 2470 }; 2471 2472 lpass_hm: clock-controller@3c00000 { 2473 compatible = "qcom,sc7280-lpasshm"; 2474 reg = <0 0x03c00000 0 0x28>; 2475 clocks = <&rpmhcc RPMH_CXO_CLK>; 2476 clock-names = "bi_tcxo"; 2477 #clock-cells = <1>; 2478 #power-domain-cells = <1>; 2479 }; 2480 2481 lpass_ag_noc: interconnect@3c40000 { 2482 reg = <0 0x03c40000 0 0xf080>; 2483 compatible = "qcom,sc7280-lpass-ag-noc"; 2484 #interconnect-cells = <2>; 2485 qcom,bcm-voters = <&apps_bcm_voter>; 2486 }; 2487 2488 lpass_tlmm: pinctrl@33c0000 { 2489 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2490 reg = <0 0x033c0000 0x0 0x20000>, 2491 <0 0x03550000 0x0 0x10000>; 2492 qcom,adsp-bypass-mode; 2493 gpio-controller; 2494 #gpio-cells = <2>; 2495 gpio-ranges = <&lpass_tlmm 0 0 15>; 2496 2497 lpass_dmic01_clk: dmic01-clk-state { 2498 pins = "gpio6"; 2499 function = "dmic1_clk"; 2500 }; 2501 2502 lpass_dmic01_data: dmic01-data-state { 2503 pins = "gpio7"; 2504 function = "dmic1_data"; 2505 }; 2506 2507 lpass_dmic23_clk: dmic23-clk-state { 2508 pins = "gpio8"; 2509 function = "dmic2_clk"; 2510 }; 2511 2512 lpass_dmic23_data: dmic23-data-state { 2513 pins = "gpio9"; 2514 function = "dmic2_data"; 2515 }; 2516 2517 lpass_rx_swr_clk: rx-swr-clk-state { 2518 pins = "gpio3"; 2519 function = "swr_rx_clk"; 2520 }; 2521 2522 lpass_rx_swr_data: rx-swr-data-state { 2523 pins = "gpio4", "gpio5"; 2524 function = "swr_rx_data"; 2525 }; 2526 2527 lpass_tx_swr_clk: tx-swr-clk-state { 2528 pins = "gpio0"; 2529 function = "swr_tx_clk"; 2530 }; 2531 2532 lpass_tx_swr_data: tx-swr-data-state { 2533 pins = "gpio1", "gpio2", "gpio14"; 2534 function = "swr_tx_data"; 2535 }; 2536 }; 2537 2538 gpu: gpu@3d00000 { 2539 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2540 reg = <0 0x03d00000 0 0x40000>, 2541 <0 0x03d9e000 0 0x1000>, 2542 <0 0x03d61000 0 0x800>; 2543 reg-names = "kgsl_3d0_reg_memory", 2544 "cx_mem", 2545 "cx_dbgc"; 2546 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2547 iommus = <&adreno_smmu 0 0x401>; 2548 operating-points-v2 = <&gpu_opp_table>; 2549 qcom,gmu = <&gmu>; 2550 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2551 interconnect-names = "gfx-mem"; 2552 #cooling-cells = <2>; 2553 2554 nvmem-cells = <&gpu_speed_bin>; 2555 nvmem-cell-names = "speed_bin"; 2556 2557 gpu_opp_table: opp-table { 2558 compatible = "operating-points-v2"; 2559 2560 opp-315000000 { 2561 opp-hz = /bits/ 64 <315000000>; 2562 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2563 opp-peak-kBps = <1804000>; 2564 opp-supported-hw = <0x03>; 2565 }; 2566 2567 opp-450000000 { 2568 opp-hz = /bits/ 64 <450000000>; 2569 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2570 opp-peak-kBps = <4068000>; 2571 opp-supported-hw = <0x03>; 2572 }; 2573 2574 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2575 opp-550000000-0 { 2576 opp-hz = /bits/ 64 <550000000>; 2577 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2578 opp-peak-kBps = <8368000>; 2579 opp-supported-hw = <0x01>; 2580 }; 2581 2582 opp-550000000-1 { 2583 opp-hz = /bits/ 64 <550000000>; 2584 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2585 opp-peak-kBps = <6832000>; 2586 opp-supported-hw = <0x02>; 2587 }; 2588 2589 opp-608000000 { 2590 opp-hz = /bits/ 64 <608000000>; 2591 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2592 opp-peak-kBps = <8368000>; 2593 opp-supported-hw = <0x02>; 2594 }; 2595 2596 opp-700000000 { 2597 opp-hz = /bits/ 64 <700000000>; 2598 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2599 opp-peak-kBps = <8532000>; 2600 opp-supported-hw = <0x02>; 2601 }; 2602 2603 opp-812000000 { 2604 opp-hz = /bits/ 64 <812000000>; 2605 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2606 opp-peak-kBps = <8532000>; 2607 opp-supported-hw = <0x02>; 2608 }; 2609 2610 opp-840000000 { 2611 opp-hz = /bits/ 64 <840000000>; 2612 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2613 opp-peak-kBps = <8532000>; 2614 opp-supported-hw = <0x02>; 2615 }; 2616 2617 opp-900000000 { 2618 opp-hz = /bits/ 64 <900000000>; 2619 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2620 opp-peak-kBps = <8532000>; 2621 opp-supported-hw = <0x02>; 2622 }; 2623 }; 2624 }; 2625 2626 gmu: gmu@3d6a000 { 2627 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2628 reg = <0 0x03d6a000 0 0x34000>, 2629 <0 0x3de0000 0 0x10000>, 2630 <0 0x0b290000 0 0x10000>; 2631 reg-names = "gmu", "rscc", "gmu_pdc"; 2632 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2634 interrupt-names = "hfi", "gmu"; 2635 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2636 <&gpucc GPU_CC_CXO_CLK>, 2637 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2638 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2639 <&gpucc GPU_CC_AHB_CLK>, 2640 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2641 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2642 clock-names = "gmu", 2643 "cxo", 2644 "axi", 2645 "memnoc", 2646 "ahb", 2647 "hub", 2648 "smmu_vote"; 2649 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2650 <&gpucc GPU_CC_GX_GDSC>; 2651 power-domain-names = "cx", 2652 "gx"; 2653 iommus = <&adreno_smmu 5 0x400>; 2654 operating-points-v2 = <&gmu_opp_table>; 2655 2656 gmu_opp_table: opp-table { 2657 compatible = "operating-points-v2"; 2658 2659 opp-200000000 { 2660 opp-hz = /bits/ 64 <200000000>; 2661 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2662 }; 2663 }; 2664 }; 2665 2666 gpucc: clock-controller@3d90000 { 2667 compatible = "qcom,sc7280-gpucc"; 2668 reg = <0 0x03d90000 0 0x9000>; 2669 clocks = <&rpmhcc RPMH_CXO_CLK>, 2670 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2671 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2672 clock-names = "bi_tcxo", 2673 "gcc_gpu_gpll0_clk_src", 2674 "gcc_gpu_gpll0_div_clk_src"; 2675 #clock-cells = <1>; 2676 #reset-cells = <1>; 2677 #power-domain-cells = <1>; 2678 }; 2679 2680 dma@117f000 { 2681 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2682 reg = <0x0 0x0117f000 0x0 0x1000>, 2683 <0x0 0x01112000 0x0 0x6000>; 2684 }; 2685 2686 adreno_smmu: iommu@3da0000 { 2687 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2688 "qcom,smmu-500", "arm,mmu-500"; 2689 reg = <0 0x03da0000 0 0x20000>; 2690 #iommu-cells = <2>; 2691 #global-interrupts = <2>; 2692 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2704 2705 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2706 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2707 <&gpucc GPU_CC_AHB_CLK>, 2708 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2709 <&gpucc GPU_CC_CX_GMU_CLK>, 2710 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2711 <&gpucc GPU_CC_HUB_AON_CLK>; 2712 clock-names = "gcc_gpu_memnoc_gfx_clk", 2713 "gcc_gpu_snoc_dvm_gfx_clk", 2714 "gpu_cc_ahb_clk", 2715 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2716 "gpu_cc_cx_gmu_clk", 2717 "gpu_cc_hub_cx_int_clk", 2718 "gpu_cc_hub_aon_clk"; 2719 2720 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2721 }; 2722 2723 remoteproc_mpss: remoteproc@4080000 { 2724 compatible = "qcom,sc7280-mpss-pas"; 2725 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2726 reg-names = "qdsp6", "rmb"; 2727 2728 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2729 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2730 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2731 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2732 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2733 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2734 interrupt-names = "wdog", "fatal", "ready", "handover", 2735 "stop-ack", "shutdown-ack"; 2736 2737 clocks = <&rpmhcc RPMH_CXO_CLK>; 2738 clock-names = "xo"; 2739 2740 power-domains = <&rpmhpd SC7280_CX>, 2741 <&rpmhpd SC7280_MSS>; 2742 power-domain-names = "cx", "mss"; 2743 2744 memory-region = <&mpss_mem>; 2745 2746 qcom,qmp = <&aoss_qmp>; 2747 2748 qcom,smem-states = <&modem_smp2p_out 0>; 2749 qcom,smem-state-names = "stop"; 2750 2751 status = "disabled"; 2752 2753 glink-edge { 2754 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2755 IPCC_MPROC_SIGNAL_GLINK_QMP 2756 IRQ_TYPE_EDGE_RISING>; 2757 mboxes = <&ipcc IPCC_CLIENT_MPSS 2758 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2759 label = "modem"; 2760 qcom,remote-pid = <1>; 2761 }; 2762 }; 2763 2764 stm@6002000 { 2765 compatible = "arm,coresight-stm", "arm,primecell"; 2766 reg = <0 0x06002000 0 0x1000>, 2767 <0 0x16280000 0 0x180000>; 2768 reg-names = "stm-base", "stm-stimulus-base"; 2769 2770 clocks = <&aoss_qmp>; 2771 clock-names = "apb_pclk"; 2772 2773 out-ports { 2774 port { 2775 stm_out: endpoint { 2776 remote-endpoint = <&funnel0_in7>; 2777 }; 2778 }; 2779 }; 2780 }; 2781 2782 funnel@6041000 { 2783 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2784 reg = <0 0x06041000 0 0x1000>; 2785 2786 clocks = <&aoss_qmp>; 2787 clock-names = "apb_pclk"; 2788 2789 out-ports { 2790 port { 2791 funnel0_out: endpoint { 2792 remote-endpoint = <&merge_funnel_in0>; 2793 }; 2794 }; 2795 }; 2796 2797 in-ports { 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 port@7 { 2802 reg = <7>; 2803 funnel0_in7: endpoint { 2804 remote-endpoint = <&stm_out>; 2805 }; 2806 }; 2807 }; 2808 }; 2809 2810 funnel@6042000 { 2811 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2812 reg = <0 0x06042000 0 0x1000>; 2813 2814 clocks = <&aoss_qmp>; 2815 clock-names = "apb_pclk"; 2816 2817 out-ports { 2818 port { 2819 funnel1_out: endpoint { 2820 remote-endpoint = <&merge_funnel_in1>; 2821 }; 2822 }; 2823 }; 2824 2825 in-ports { 2826 #address-cells = <1>; 2827 #size-cells = <0>; 2828 2829 port@4 { 2830 reg = <4>; 2831 funnel1_in4: endpoint { 2832 remote-endpoint = <&apss_merge_funnel_out>; 2833 }; 2834 }; 2835 }; 2836 }; 2837 2838 funnel@6045000 { 2839 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2840 reg = <0 0x06045000 0 0x1000>; 2841 2842 clocks = <&aoss_qmp>; 2843 clock-names = "apb_pclk"; 2844 2845 out-ports { 2846 port { 2847 merge_funnel_out: endpoint { 2848 remote-endpoint = <&swao_funnel_in>; 2849 }; 2850 }; 2851 }; 2852 2853 in-ports { 2854 #address-cells = <1>; 2855 #size-cells = <0>; 2856 2857 port@0 { 2858 reg = <0>; 2859 merge_funnel_in0: endpoint { 2860 remote-endpoint = <&funnel0_out>; 2861 }; 2862 }; 2863 2864 port@1 { 2865 reg = <1>; 2866 merge_funnel_in1: endpoint { 2867 remote-endpoint = <&funnel1_out>; 2868 }; 2869 }; 2870 }; 2871 }; 2872 2873 replicator@6046000 { 2874 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2875 reg = <0 0x06046000 0 0x1000>; 2876 2877 clocks = <&aoss_qmp>; 2878 clock-names = "apb_pclk"; 2879 2880 out-ports { 2881 port { 2882 replicator_out: endpoint { 2883 remote-endpoint = <&etr_in>; 2884 }; 2885 }; 2886 }; 2887 2888 in-ports { 2889 port { 2890 replicator_in: endpoint { 2891 remote-endpoint = <&swao_replicator_out>; 2892 }; 2893 }; 2894 }; 2895 }; 2896 2897 etr@6048000 { 2898 compatible = "arm,coresight-tmc", "arm,primecell"; 2899 reg = <0 0x06048000 0 0x1000>; 2900 iommus = <&apps_smmu 0x04c0 0>; 2901 2902 clocks = <&aoss_qmp>; 2903 clock-names = "apb_pclk"; 2904 arm,scatter-gather; 2905 2906 in-ports { 2907 port { 2908 etr_in: endpoint { 2909 remote-endpoint = <&replicator_out>; 2910 }; 2911 }; 2912 }; 2913 }; 2914 2915 funnel@6b04000 { 2916 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2917 reg = <0 0x06b04000 0 0x1000>; 2918 2919 clocks = <&aoss_qmp>; 2920 clock-names = "apb_pclk"; 2921 2922 out-ports { 2923 port { 2924 swao_funnel_out: endpoint { 2925 remote-endpoint = <&etf_in>; 2926 }; 2927 }; 2928 }; 2929 2930 in-ports { 2931 #address-cells = <1>; 2932 #size-cells = <0>; 2933 2934 port@7 { 2935 reg = <7>; 2936 swao_funnel_in: endpoint { 2937 remote-endpoint = <&merge_funnel_out>; 2938 }; 2939 }; 2940 }; 2941 }; 2942 2943 etf@6b05000 { 2944 compatible = "arm,coresight-tmc", "arm,primecell"; 2945 reg = <0 0x06b05000 0 0x1000>; 2946 2947 clocks = <&aoss_qmp>; 2948 clock-names = "apb_pclk"; 2949 2950 out-ports { 2951 port { 2952 etf_out: endpoint { 2953 remote-endpoint = <&swao_replicator_in>; 2954 }; 2955 }; 2956 }; 2957 2958 in-ports { 2959 port { 2960 etf_in: endpoint { 2961 remote-endpoint = <&swao_funnel_out>; 2962 }; 2963 }; 2964 }; 2965 }; 2966 2967 replicator@6b06000 { 2968 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2969 reg = <0 0x06b06000 0 0x1000>; 2970 2971 clocks = <&aoss_qmp>; 2972 clock-names = "apb_pclk"; 2973 qcom,replicator-loses-context; 2974 2975 out-ports { 2976 port { 2977 swao_replicator_out: endpoint { 2978 remote-endpoint = <&replicator_in>; 2979 }; 2980 }; 2981 }; 2982 2983 in-ports { 2984 port { 2985 swao_replicator_in: endpoint { 2986 remote-endpoint = <&etf_out>; 2987 }; 2988 }; 2989 }; 2990 }; 2991 2992 etm@7040000 { 2993 compatible = "arm,coresight-etm4x", "arm,primecell"; 2994 reg = <0 0x07040000 0 0x1000>; 2995 2996 cpu = <&CPU0>; 2997 2998 clocks = <&aoss_qmp>; 2999 clock-names = "apb_pclk"; 3000 arm,coresight-loses-context-with-cpu; 3001 qcom,skip-power-up; 3002 3003 out-ports { 3004 port { 3005 etm0_out: endpoint { 3006 remote-endpoint = <&apss_funnel_in0>; 3007 }; 3008 }; 3009 }; 3010 }; 3011 3012 etm@7140000 { 3013 compatible = "arm,coresight-etm4x", "arm,primecell"; 3014 reg = <0 0x07140000 0 0x1000>; 3015 3016 cpu = <&CPU1>; 3017 3018 clocks = <&aoss_qmp>; 3019 clock-names = "apb_pclk"; 3020 arm,coresight-loses-context-with-cpu; 3021 qcom,skip-power-up; 3022 3023 out-ports { 3024 port { 3025 etm1_out: endpoint { 3026 remote-endpoint = <&apss_funnel_in1>; 3027 }; 3028 }; 3029 }; 3030 }; 3031 3032 etm@7240000 { 3033 compatible = "arm,coresight-etm4x", "arm,primecell"; 3034 reg = <0 0x07240000 0 0x1000>; 3035 3036 cpu = <&CPU2>; 3037 3038 clocks = <&aoss_qmp>; 3039 clock-names = "apb_pclk"; 3040 arm,coresight-loses-context-with-cpu; 3041 qcom,skip-power-up; 3042 3043 out-ports { 3044 port { 3045 etm2_out: endpoint { 3046 remote-endpoint = <&apss_funnel_in2>; 3047 }; 3048 }; 3049 }; 3050 }; 3051 3052 etm@7340000 { 3053 compatible = "arm,coresight-etm4x", "arm,primecell"; 3054 reg = <0 0x07340000 0 0x1000>; 3055 3056 cpu = <&CPU3>; 3057 3058 clocks = <&aoss_qmp>; 3059 clock-names = "apb_pclk"; 3060 arm,coresight-loses-context-with-cpu; 3061 qcom,skip-power-up; 3062 3063 out-ports { 3064 port { 3065 etm3_out: endpoint { 3066 remote-endpoint = <&apss_funnel_in3>; 3067 }; 3068 }; 3069 }; 3070 }; 3071 3072 etm@7440000 { 3073 compatible = "arm,coresight-etm4x", "arm,primecell"; 3074 reg = <0 0x07440000 0 0x1000>; 3075 3076 cpu = <&CPU4>; 3077 3078 clocks = <&aoss_qmp>; 3079 clock-names = "apb_pclk"; 3080 arm,coresight-loses-context-with-cpu; 3081 qcom,skip-power-up; 3082 3083 out-ports { 3084 port { 3085 etm4_out: endpoint { 3086 remote-endpoint = <&apss_funnel_in4>; 3087 }; 3088 }; 3089 }; 3090 }; 3091 3092 etm@7540000 { 3093 compatible = "arm,coresight-etm4x", "arm,primecell"; 3094 reg = <0 0x07540000 0 0x1000>; 3095 3096 cpu = <&CPU5>; 3097 3098 clocks = <&aoss_qmp>; 3099 clock-names = "apb_pclk"; 3100 arm,coresight-loses-context-with-cpu; 3101 qcom,skip-power-up; 3102 3103 out-ports { 3104 port { 3105 etm5_out: endpoint { 3106 remote-endpoint = <&apss_funnel_in5>; 3107 }; 3108 }; 3109 }; 3110 }; 3111 3112 etm@7640000 { 3113 compatible = "arm,coresight-etm4x", "arm,primecell"; 3114 reg = <0 0x07640000 0 0x1000>; 3115 3116 cpu = <&CPU6>; 3117 3118 clocks = <&aoss_qmp>; 3119 clock-names = "apb_pclk"; 3120 arm,coresight-loses-context-with-cpu; 3121 qcom,skip-power-up; 3122 3123 out-ports { 3124 port { 3125 etm6_out: endpoint { 3126 remote-endpoint = <&apss_funnel_in6>; 3127 }; 3128 }; 3129 }; 3130 }; 3131 3132 etm@7740000 { 3133 compatible = "arm,coresight-etm4x", "arm,primecell"; 3134 reg = <0 0x07740000 0 0x1000>; 3135 3136 cpu = <&CPU7>; 3137 3138 clocks = <&aoss_qmp>; 3139 clock-names = "apb_pclk"; 3140 arm,coresight-loses-context-with-cpu; 3141 qcom,skip-power-up; 3142 3143 out-ports { 3144 port { 3145 etm7_out: endpoint { 3146 remote-endpoint = <&apss_funnel_in7>; 3147 }; 3148 }; 3149 }; 3150 }; 3151 3152 funnel@7800000 { /* APSS Funnel */ 3153 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3154 reg = <0 0x07800000 0 0x1000>; 3155 3156 clocks = <&aoss_qmp>; 3157 clock-names = "apb_pclk"; 3158 3159 out-ports { 3160 port { 3161 apss_funnel_out: endpoint { 3162 remote-endpoint = <&apss_merge_funnel_in>; 3163 }; 3164 }; 3165 }; 3166 3167 in-ports { 3168 #address-cells = <1>; 3169 #size-cells = <0>; 3170 3171 port@0 { 3172 reg = <0>; 3173 apss_funnel_in0: endpoint { 3174 remote-endpoint = <&etm0_out>; 3175 }; 3176 }; 3177 3178 port@1 { 3179 reg = <1>; 3180 apss_funnel_in1: endpoint { 3181 remote-endpoint = <&etm1_out>; 3182 }; 3183 }; 3184 3185 port@2 { 3186 reg = <2>; 3187 apss_funnel_in2: endpoint { 3188 remote-endpoint = <&etm2_out>; 3189 }; 3190 }; 3191 3192 port@3 { 3193 reg = <3>; 3194 apss_funnel_in3: endpoint { 3195 remote-endpoint = <&etm3_out>; 3196 }; 3197 }; 3198 3199 port@4 { 3200 reg = <4>; 3201 apss_funnel_in4: endpoint { 3202 remote-endpoint = <&etm4_out>; 3203 }; 3204 }; 3205 3206 port@5 { 3207 reg = <5>; 3208 apss_funnel_in5: endpoint { 3209 remote-endpoint = <&etm5_out>; 3210 }; 3211 }; 3212 3213 port@6 { 3214 reg = <6>; 3215 apss_funnel_in6: endpoint { 3216 remote-endpoint = <&etm6_out>; 3217 }; 3218 }; 3219 3220 port@7 { 3221 reg = <7>; 3222 apss_funnel_in7: endpoint { 3223 remote-endpoint = <&etm7_out>; 3224 }; 3225 }; 3226 }; 3227 }; 3228 3229 funnel@7810000 { 3230 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3231 reg = <0 0x07810000 0 0x1000>; 3232 3233 clocks = <&aoss_qmp>; 3234 clock-names = "apb_pclk"; 3235 3236 out-ports { 3237 port { 3238 apss_merge_funnel_out: endpoint { 3239 remote-endpoint = <&funnel1_in4>; 3240 }; 3241 }; 3242 }; 3243 3244 in-ports { 3245 port { 3246 apss_merge_funnel_in: endpoint { 3247 remote-endpoint = <&apss_funnel_out>; 3248 }; 3249 }; 3250 }; 3251 }; 3252 3253 sdhc_2: mmc@8804000 { 3254 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3255 pinctrl-names = "default", "sleep"; 3256 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3257 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3258 status = "disabled"; 3259 3260 reg = <0 0x08804000 0 0x1000>; 3261 3262 iommus = <&apps_smmu 0x100 0x0>; 3263 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3265 interrupt-names = "hc_irq", "pwr_irq"; 3266 3267 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3268 <&gcc GCC_SDCC2_APPS_CLK>, 3269 <&rpmhcc RPMH_CXO_CLK>; 3270 clock-names = "iface", "core", "xo"; 3271 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3272 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3273 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3274 power-domains = <&rpmhpd SC7280_CX>; 3275 operating-points-v2 = <&sdhc2_opp_table>; 3276 3277 bus-width = <4>; 3278 3279 qcom,dll-config = <0x0007642c>; 3280 3281 resets = <&gcc GCC_SDCC2_BCR>; 3282 3283 sdhc2_opp_table: opp-table { 3284 compatible = "operating-points-v2"; 3285 3286 opp-100000000 { 3287 opp-hz = /bits/ 64 <100000000>; 3288 required-opps = <&rpmhpd_opp_low_svs>; 3289 opp-peak-kBps = <1800000 400000>; 3290 opp-avg-kBps = <100000 0>; 3291 }; 3292 3293 opp-202000000 { 3294 opp-hz = /bits/ 64 <202000000>; 3295 required-opps = <&rpmhpd_opp_nom>; 3296 opp-peak-kBps = <5400000 1600000>; 3297 opp-avg-kBps = <200000 0>; 3298 }; 3299 }; 3300 }; 3301 3302 usb_1_hsphy: phy@88e3000 { 3303 compatible = "qcom,sc7280-usb-hs-phy", 3304 "qcom,usb-snps-hs-7nm-phy"; 3305 reg = <0 0x088e3000 0 0x400>; 3306 status = "disabled"; 3307 #phy-cells = <0>; 3308 3309 clocks = <&rpmhcc RPMH_CXO_CLK>; 3310 clock-names = "ref"; 3311 3312 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3313 }; 3314 3315 usb_2_hsphy: phy@88e4000 { 3316 compatible = "qcom,sc7280-usb-hs-phy", 3317 "qcom,usb-snps-hs-7nm-phy"; 3318 reg = <0 0x088e4000 0 0x400>; 3319 status = "disabled"; 3320 #phy-cells = <0>; 3321 3322 clocks = <&rpmhcc RPMH_CXO_CLK>; 3323 clock-names = "ref"; 3324 3325 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3326 }; 3327 3328 usb_1_qmpphy: phy-wrapper@88e9000 { 3329 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3330 "qcom,sm8250-qmp-usb3-dp-phy"; 3331 reg = <0 0x088e9000 0 0x200>, 3332 <0 0x088e8000 0 0x40>, 3333 <0 0x088ea000 0 0x200>; 3334 status = "disabled"; 3335 #address-cells = <2>; 3336 #size-cells = <2>; 3337 ranges; 3338 3339 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3340 <&rpmhcc RPMH_CXO_CLK>, 3341 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3342 clock-names = "aux", "ref_clk_src", "com_aux"; 3343 3344 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3345 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3346 reset-names = "phy", "common"; 3347 3348 usb_1_ssphy: usb3-phy@88e9200 { 3349 reg = <0 0x088e9200 0 0x200>, 3350 <0 0x088e9400 0 0x200>, 3351 <0 0x088e9c00 0 0x400>, 3352 <0 0x088e9600 0 0x200>, 3353 <0 0x088e9800 0 0x200>, 3354 <0 0x088e9a00 0 0x100>; 3355 #clock-cells = <0>; 3356 #phy-cells = <0>; 3357 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3358 clock-names = "pipe0"; 3359 clock-output-names = "usb3_phy_pipe_clk_src"; 3360 }; 3361 3362 dp_phy: dp-phy@88ea200 { 3363 reg = <0 0x088ea200 0 0x200>, 3364 <0 0x088ea400 0 0x200>, 3365 <0 0x088eaa00 0 0x200>, 3366 <0 0x088ea600 0 0x200>, 3367 <0 0x088ea800 0 0x200>; 3368 #phy-cells = <0>; 3369 #clock-cells = <1>; 3370 }; 3371 }; 3372 3373 usb_2: usb@8cf8800 { 3374 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3375 reg = <0 0x08cf8800 0 0x400>; 3376 status = "disabled"; 3377 #address-cells = <2>; 3378 #size-cells = <2>; 3379 ranges; 3380 dma-ranges; 3381 3382 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3383 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3384 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3385 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3386 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3387 clock-names = "cfg_noc", 3388 "core", 3389 "iface", 3390 "sleep", 3391 "mock_utmi"; 3392 3393 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3394 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3395 assigned-clock-rates = <19200000>, <200000000>; 3396 3397 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3398 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3399 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3400 interrupt-names = "hs_phy_irq", 3401 "dp_hs_phy_irq", 3402 "dm_hs_phy_irq"; 3403 3404 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3405 required-opps = <&rpmhpd_opp_nom>; 3406 3407 resets = <&gcc GCC_USB30_SEC_BCR>; 3408 3409 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3410 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3411 interconnect-names = "usb-ddr", "apps-usb"; 3412 3413 usb_2_dwc3: usb@8c00000 { 3414 compatible = "snps,dwc3"; 3415 reg = <0 0x08c00000 0 0xe000>; 3416 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3417 iommus = <&apps_smmu 0xa0 0x0>; 3418 snps,dis_u2_susphy_quirk; 3419 snps,dis_enblslpm_quirk; 3420 phys = <&usb_2_hsphy>; 3421 phy-names = "usb2-phy"; 3422 maximum-speed = "high-speed"; 3423 usb-role-switch; 3424 port { 3425 usb2_role_switch: endpoint { 3426 remote-endpoint = <&eud_ep>; 3427 }; 3428 }; 3429 }; 3430 }; 3431 3432 qspi: spi@88dc000 { 3433 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3434 reg = <0 0x088dc000 0 0x1000>; 3435 #address-cells = <1>; 3436 #size-cells = <0>; 3437 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3438 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3439 <&gcc GCC_QSPI_CORE_CLK>; 3440 clock-names = "iface", "core"; 3441 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3442 &cnoc2 SLAVE_QSPI_0 0>; 3443 interconnect-names = "qspi-config"; 3444 power-domains = <&rpmhpd SC7280_CX>; 3445 operating-points-v2 = <&qspi_opp_table>; 3446 status = "disabled"; 3447 }; 3448 3449 remoteproc_wpss: remoteproc@8a00000 { 3450 compatible = "qcom,sc7280-wpss-pil"; 3451 reg = <0 0x08a00000 0 0x10000>; 3452 3453 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3454 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3455 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3456 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3457 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3458 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3459 interrupt-names = "wdog", "fatal", "ready", "handover", 3460 "stop-ack", "shutdown-ack"; 3461 3462 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3463 <&gcc GCC_WPSS_AHB_CLK>, 3464 <&gcc GCC_WPSS_RSCP_CLK>, 3465 <&rpmhcc RPMH_CXO_CLK>; 3466 clock-names = "ahb_bdg", "ahb", 3467 "rscp", "xo"; 3468 3469 power-domains = <&rpmhpd SC7280_CX>, 3470 <&rpmhpd SC7280_MX>; 3471 power-domain-names = "cx", "mx"; 3472 3473 memory-region = <&wpss_mem>; 3474 3475 qcom,qmp = <&aoss_qmp>; 3476 3477 qcom,smem-states = <&wpss_smp2p_out 0>; 3478 qcom,smem-state-names = "stop"; 3479 3480 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3481 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3482 reset-names = "restart", "pdc_sync"; 3483 3484 qcom,halt-regs = <&tcsr_1 0x17000>; 3485 3486 status = "disabled"; 3487 3488 glink-edge { 3489 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3490 IPCC_MPROC_SIGNAL_GLINK_QMP 3491 IRQ_TYPE_EDGE_RISING>; 3492 mboxes = <&ipcc IPCC_CLIENT_WPSS 3493 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3494 3495 label = "wpss"; 3496 qcom,remote-pid = <13>; 3497 }; 3498 }; 3499 3500 pmu@9091000 { 3501 compatible = "qcom,sc7280-llcc-bwmon"; 3502 reg = <0 0x09091000 0 0x1000>; 3503 3504 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3505 3506 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3507 3508 operating-points-v2 = <&llcc_bwmon_opp_table>; 3509 3510 llcc_bwmon_opp_table: opp-table { 3511 compatible = "operating-points-v2"; 3512 3513 opp-0 { 3514 opp-peak-kBps = <800000>; 3515 }; 3516 opp-1 { 3517 opp-peak-kBps = <1804000>; 3518 }; 3519 opp-2 { 3520 opp-peak-kBps = <2188000>; 3521 }; 3522 opp-3 { 3523 opp-peak-kBps = <3072000>; 3524 }; 3525 opp-4 { 3526 opp-peak-kBps = <4068000>; 3527 }; 3528 opp-5 { 3529 opp-peak-kBps = <6220000>; 3530 }; 3531 opp-6 { 3532 opp-peak-kBps = <6832000>; 3533 }; 3534 opp-7 { 3535 opp-peak-kBps = <8532000>; 3536 }; 3537 }; 3538 }; 3539 3540 pmu@90b6400 { 3541 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3542 reg = <0 0x090b6400 0 0x600>; 3543 3544 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3545 3546 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3547 operating-points-v2 = <&cpu_bwmon_opp_table>; 3548 3549 cpu_bwmon_opp_table: opp-table { 3550 compatible = "operating-points-v2"; 3551 3552 opp-0 { 3553 opp-peak-kBps = <2400000>; 3554 }; 3555 opp-1 { 3556 opp-peak-kBps = <4800000>; 3557 }; 3558 opp-2 { 3559 opp-peak-kBps = <7456000>; 3560 }; 3561 opp-3 { 3562 opp-peak-kBps = <9600000>; 3563 }; 3564 opp-4 { 3565 opp-peak-kBps = <12896000>; 3566 }; 3567 opp-5 { 3568 opp-peak-kBps = <14928000>; 3569 }; 3570 opp-6 { 3571 opp-peak-kBps = <17056000>; 3572 }; 3573 }; 3574 }; 3575 3576 dc_noc: interconnect@90e0000 { 3577 reg = <0 0x090e0000 0 0x5080>; 3578 compatible = "qcom,sc7280-dc-noc"; 3579 #interconnect-cells = <2>; 3580 qcom,bcm-voters = <&apps_bcm_voter>; 3581 }; 3582 3583 gem_noc: interconnect@9100000 { 3584 reg = <0 0x09100000 0 0xe2200>; 3585 compatible = "qcom,sc7280-gem-noc"; 3586 #interconnect-cells = <2>; 3587 qcom,bcm-voters = <&apps_bcm_voter>; 3588 }; 3589 3590 system-cache-controller@9200000 { 3591 compatible = "qcom,sc7280-llcc"; 3592 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3593 <0 0x09600000 0 0x58000>; 3594 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3595 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3596 }; 3597 3598 eud: eud@88e0000 { 3599 compatible = "qcom,sc7280-eud","qcom,eud"; 3600 reg = <0 0x088e0000 0 0x2000>, 3601 <0 0x088e2000 0 0x1000>; 3602 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3603 ports { 3604 #address-cells = <1>; 3605 #size-cells = <0>; 3606 3607 port@0 { 3608 reg = <0>; 3609 eud_ep: endpoint { 3610 remote-endpoint = <&usb2_role_switch>; 3611 }; 3612 }; 3613 port@1 { 3614 reg = <1>; 3615 eud_con: endpoint { 3616 remote-endpoint = <&con_eud>; 3617 }; 3618 }; 3619 }; 3620 }; 3621 3622 eud_typec: connector { 3623 compatible = "usb-c-connector"; 3624 ports { 3625 #address-cells = <1>; 3626 #size-cells = <0>; 3627 3628 port@0 { 3629 reg = <0>; 3630 con_eud: endpoint { 3631 remote-endpoint = <&eud_con>; 3632 }; 3633 }; 3634 }; 3635 }; 3636 3637 nsp_noc: interconnect@a0c0000 { 3638 reg = <0 0x0a0c0000 0 0x10000>; 3639 compatible = "qcom,sc7280-nsp-noc"; 3640 #interconnect-cells = <2>; 3641 qcom,bcm-voters = <&apps_bcm_voter>; 3642 }; 3643 3644 usb_1: usb@a6f8800 { 3645 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3646 reg = <0 0x0a6f8800 0 0x400>; 3647 status = "disabled"; 3648 #address-cells = <2>; 3649 #size-cells = <2>; 3650 ranges; 3651 dma-ranges; 3652 3653 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3654 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3655 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3656 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3657 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3658 clock-names = "cfg_noc", 3659 "core", 3660 "iface", 3661 "sleep", 3662 "mock_utmi"; 3663 3664 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3665 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3666 assigned-clock-rates = <19200000>, <200000000>; 3667 3668 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3669 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3670 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3671 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3672 interrupt-names = "hs_phy_irq", 3673 "dp_hs_phy_irq", 3674 "dm_hs_phy_irq", 3675 "ss_phy_irq"; 3676 3677 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3678 required-opps = <&rpmhpd_opp_nom>; 3679 3680 resets = <&gcc GCC_USB30_PRIM_BCR>; 3681 3682 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3683 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3684 interconnect-names = "usb-ddr", "apps-usb"; 3685 3686 wakeup-source; 3687 3688 usb_1_dwc3: usb@a600000 { 3689 compatible = "snps,dwc3"; 3690 reg = <0 0x0a600000 0 0xe000>; 3691 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3692 iommus = <&apps_smmu 0xe0 0x0>; 3693 snps,dis_u2_susphy_quirk; 3694 snps,dis_enblslpm_quirk; 3695 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3696 phy-names = "usb2-phy", "usb3-phy"; 3697 maximum-speed = "super-speed"; 3698 }; 3699 }; 3700 3701 venus: video-codec@aa00000 { 3702 compatible = "qcom,sc7280-venus"; 3703 reg = <0 0x0aa00000 0 0xd0600>; 3704 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3705 3706 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3707 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3708 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3709 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3710 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3711 clock-names = "core", "bus", "iface", 3712 "vcodec_core", "vcodec_bus"; 3713 3714 power-domains = <&videocc MVSC_GDSC>, 3715 <&videocc MVS0_GDSC>, 3716 <&rpmhpd SC7280_CX>; 3717 power-domain-names = "venus", "vcodec0", "cx"; 3718 operating-points-v2 = <&venus_opp_table>; 3719 3720 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3721 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3722 interconnect-names = "cpu-cfg", "video-mem"; 3723 3724 iommus = <&apps_smmu 0x2180 0x20>, 3725 <&apps_smmu 0x2184 0x20>; 3726 memory-region = <&video_mem>; 3727 3728 video-decoder { 3729 compatible = "venus-decoder"; 3730 }; 3731 3732 video-encoder { 3733 compatible = "venus-encoder"; 3734 }; 3735 3736 video-firmware { 3737 iommus = <&apps_smmu 0x21a2 0x0>; 3738 }; 3739 3740 venus_opp_table: opp-table { 3741 compatible = "operating-points-v2"; 3742 3743 opp-133330000 { 3744 opp-hz = /bits/ 64 <133330000>; 3745 required-opps = <&rpmhpd_opp_low_svs>; 3746 }; 3747 3748 opp-240000000 { 3749 opp-hz = /bits/ 64 <240000000>; 3750 required-opps = <&rpmhpd_opp_svs>; 3751 }; 3752 3753 opp-335000000 { 3754 opp-hz = /bits/ 64 <335000000>; 3755 required-opps = <&rpmhpd_opp_svs_l1>; 3756 }; 3757 3758 opp-424000000 { 3759 opp-hz = /bits/ 64 <424000000>; 3760 required-opps = <&rpmhpd_opp_nom>; 3761 }; 3762 3763 opp-460000048 { 3764 opp-hz = /bits/ 64 <460000048>; 3765 required-opps = <&rpmhpd_opp_turbo>; 3766 }; 3767 }; 3768 }; 3769 3770 videocc: clock-controller@aaf0000 { 3771 compatible = "qcom,sc7280-videocc"; 3772 reg = <0 0x0aaf0000 0 0x10000>; 3773 clocks = <&rpmhcc RPMH_CXO_CLK>, 3774 <&rpmhcc RPMH_CXO_CLK_A>; 3775 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3776 #clock-cells = <1>; 3777 #reset-cells = <1>; 3778 #power-domain-cells = <1>; 3779 }; 3780 3781 camcc: clock-controller@ad00000 { 3782 compatible = "qcom,sc7280-camcc"; 3783 reg = <0 0x0ad00000 0 0x10000>; 3784 clocks = <&rpmhcc RPMH_CXO_CLK>, 3785 <&rpmhcc RPMH_CXO_CLK_A>, 3786 <&sleep_clk>; 3787 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3788 #clock-cells = <1>; 3789 #reset-cells = <1>; 3790 #power-domain-cells = <1>; 3791 }; 3792 3793 dispcc: clock-controller@af00000 { 3794 compatible = "qcom,sc7280-dispcc"; 3795 reg = <0 0x0af00000 0 0x20000>; 3796 clocks = <&rpmhcc RPMH_CXO_CLK>, 3797 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3798 <&mdss_dsi_phy 0>, 3799 <&mdss_dsi_phy 1>, 3800 <&dp_phy 0>, 3801 <&dp_phy 1>, 3802 <&mdss_edp_phy 0>, 3803 <&mdss_edp_phy 1>; 3804 clock-names = "bi_tcxo", 3805 "gcc_disp_gpll0_clk", 3806 "dsi0_phy_pll_out_byteclk", 3807 "dsi0_phy_pll_out_dsiclk", 3808 "dp_phy_pll_link_clk", 3809 "dp_phy_pll_vco_div_clk", 3810 "edp_phy_pll_link_clk", 3811 "edp_phy_pll_vco_div_clk"; 3812 #clock-cells = <1>; 3813 #reset-cells = <1>; 3814 #power-domain-cells = <1>; 3815 }; 3816 3817 mdss: display-subsystem@ae00000 { 3818 compatible = "qcom,sc7280-mdss"; 3819 reg = <0 0x0ae00000 0 0x1000>; 3820 reg-names = "mdss"; 3821 3822 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3823 3824 clocks = <&gcc GCC_DISP_AHB_CLK>, 3825 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3826 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3827 clock-names = "iface", 3828 "ahb", 3829 "core"; 3830 3831 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3832 interrupt-controller; 3833 #interrupt-cells = <1>; 3834 3835 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3836 interconnect-names = "mdp0-mem"; 3837 3838 iommus = <&apps_smmu 0x900 0x402>; 3839 3840 #address-cells = <2>; 3841 #size-cells = <2>; 3842 ranges; 3843 3844 status = "disabled"; 3845 3846 mdss_mdp: display-controller@ae01000 { 3847 compatible = "qcom,sc7280-dpu"; 3848 reg = <0 0x0ae01000 0 0x8f030>, 3849 <0 0x0aeb0000 0 0x2008>; 3850 reg-names = "mdp", "vbif"; 3851 3852 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3853 <&gcc GCC_DISP_SF_AXI_CLK>, 3854 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3855 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3856 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3857 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3858 clock-names = "bus", 3859 "nrt_bus", 3860 "iface", 3861 "lut", 3862 "core", 3863 "vsync"; 3864 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3865 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3866 assigned-clock-rates = <19200000>, 3867 <19200000>; 3868 operating-points-v2 = <&mdp_opp_table>; 3869 power-domains = <&rpmhpd SC7280_CX>; 3870 3871 interrupt-parent = <&mdss>; 3872 interrupts = <0>; 3873 3874 status = "disabled"; 3875 3876 ports { 3877 #address-cells = <1>; 3878 #size-cells = <0>; 3879 3880 port@0 { 3881 reg = <0>; 3882 dpu_intf1_out: endpoint { 3883 remote-endpoint = <&dsi0_in>; 3884 }; 3885 }; 3886 3887 port@1 { 3888 reg = <1>; 3889 dpu_intf5_out: endpoint { 3890 remote-endpoint = <&edp_in>; 3891 }; 3892 }; 3893 3894 port@2 { 3895 reg = <2>; 3896 dpu_intf0_out: endpoint { 3897 remote-endpoint = <&dp_in>; 3898 }; 3899 }; 3900 }; 3901 3902 mdp_opp_table: opp-table { 3903 compatible = "operating-points-v2"; 3904 3905 opp-200000000 { 3906 opp-hz = /bits/ 64 <200000000>; 3907 required-opps = <&rpmhpd_opp_low_svs>; 3908 }; 3909 3910 opp-300000000 { 3911 opp-hz = /bits/ 64 <300000000>; 3912 required-opps = <&rpmhpd_opp_svs>; 3913 }; 3914 3915 opp-380000000 { 3916 opp-hz = /bits/ 64 <380000000>; 3917 required-opps = <&rpmhpd_opp_svs_l1>; 3918 }; 3919 3920 opp-506666667 { 3921 opp-hz = /bits/ 64 <506666667>; 3922 required-opps = <&rpmhpd_opp_nom>; 3923 }; 3924 }; 3925 }; 3926 3927 mdss_dsi: dsi@ae94000 { 3928 compatible = "qcom,sc7280-dsi-ctrl", 3929 "qcom,mdss-dsi-ctrl"; 3930 reg = <0 0x0ae94000 0 0x400>; 3931 reg-names = "dsi_ctrl"; 3932 3933 interrupt-parent = <&mdss>; 3934 interrupts = <4>; 3935 3936 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3937 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3938 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3939 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3940 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3941 <&gcc GCC_DISP_HF_AXI_CLK>; 3942 clock-names = "byte", 3943 "byte_intf", 3944 "pixel", 3945 "core", 3946 "iface", 3947 "bus"; 3948 3949 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3950 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3951 3952 operating-points-v2 = <&dsi_opp_table>; 3953 power-domains = <&rpmhpd SC7280_CX>; 3954 3955 phys = <&mdss_dsi_phy>; 3956 3957 #address-cells = <1>; 3958 #size-cells = <0>; 3959 3960 status = "disabled"; 3961 3962 ports { 3963 #address-cells = <1>; 3964 #size-cells = <0>; 3965 3966 port@0 { 3967 reg = <0>; 3968 dsi0_in: endpoint { 3969 remote-endpoint = <&dpu_intf1_out>; 3970 }; 3971 }; 3972 3973 port@1 { 3974 reg = <1>; 3975 dsi0_out: endpoint { 3976 }; 3977 }; 3978 }; 3979 3980 dsi_opp_table: opp-table { 3981 compatible = "operating-points-v2"; 3982 3983 opp-187500000 { 3984 opp-hz = /bits/ 64 <187500000>; 3985 required-opps = <&rpmhpd_opp_low_svs>; 3986 }; 3987 3988 opp-300000000 { 3989 opp-hz = /bits/ 64 <300000000>; 3990 required-opps = <&rpmhpd_opp_svs>; 3991 }; 3992 3993 opp-358000000 { 3994 opp-hz = /bits/ 64 <358000000>; 3995 required-opps = <&rpmhpd_opp_svs_l1>; 3996 }; 3997 }; 3998 }; 3999 4000 mdss_dsi_phy: phy@ae94400 { 4001 compatible = "qcom,sc7280-dsi-phy-7nm"; 4002 reg = <0 0x0ae94400 0 0x200>, 4003 <0 0x0ae94600 0 0x280>, 4004 <0 0x0ae94900 0 0x280>; 4005 reg-names = "dsi_phy", 4006 "dsi_phy_lane", 4007 "dsi_pll"; 4008 4009 #clock-cells = <1>; 4010 #phy-cells = <0>; 4011 4012 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4013 <&rpmhcc RPMH_CXO_CLK>; 4014 clock-names = "iface", "ref"; 4015 4016 status = "disabled"; 4017 }; 4018 4019 mdss_edp: edp@aea0000 { 4020 compatible = "qcom,sc7280-edp"; 4021 pinctrl-names = "default"; 4022 pinctrl-0 = <&edp_hot_plug_det>; 4023 4024 reg = <0 0x0aea0000 0 0x200>, 4025 <0 0x0aea0200 0 0x200>, 4026 <0 0x0aea0400 0 0xc00>, 4027 <0 0x0aea1000 0 0x400>; 4028 4029 interrupt-parent = <&mdss>; 4030 interrupts = <14>; 4031 4032 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4033 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4034 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4035 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4036 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4037 clock-names = "core_iface", 4038 "core_aux", 4039 "ctrl_link", 4040 "ctrl_link_iface", 4041 "stream_pixel"; 4042 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4043 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4044 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4045 4046 phys = <&mdss_edp_phy>; 4047 phy-names = "dp"; 4048 4049 operating-points-v2 = <&edp_opp_table>; 4050 power-domains = <&rpmhpd SC7280_CX>; 4051 4052 status = "disabled"; 4053 4054 ports { 4055 #address-cells = <1>; 4056 #size-cells = <0>; 4057 4058 port@0 { 4059 reg = <0>; 4060 edp_in: endpoint { 4061 remote-endpoint = <&dpu_intf5_out>; 4062 }; 4063 }; 4064 4065 port@1 { 4066 reg = <1>; 4067 mdss_edp_out: endpoint { }; 4068 }; 4069 }; 4070 4071 edp_opp_table: opp-table { 4072 compatible = "operating-points-v2"; 4073 4074 opp-160000000 { 4075 opp-hz = /bits/ 64 <160000000>; 4076 required-opps = <&rpmhpd_opp_low_svs>; 4077 }; 4078 4079 opp-270000000 { 4080 opp-hz = /bits/ 64 <270000000>; 4081 required-opps = <&rpmhpd_opp_svs>; 4082 }; 4083 4084 opp-540000000 { 4085 opp-hz = /bits/ 64 <540000000>; 4086 required-opps = <&rpmhpd_opp_nom>; 4087 }; 4088 4089 opp-810000000 { 4090 opp-hz = /bits/ 64 <810000000>; 4091 required-opps = <&rpmhpd_opp_nom>; 4092 }; 4093 }; 4094 }; 4095 4096 mdss_edp_phy: phy@aec2a00 { 4097 compatible = "qcom,sc7280-edp-phy"; 4098 4099 reg = <0 0x0aec2a00 0 0x19c>, 4100 <0 0x0aec2200 0 0xa0>, 4101 <0 0x0aec2600 0 0xa0>, 4102 <0 0x0aec2000 0 0x1c0>; 4103 4104 clocks = <&rpmhcc RPMH_CXO_CLK>, 4105 <&gcc GCC_EDP_CLKREF_EN>; 4106 clock-names = "aux", 4107 "cfg_ahb"; 4108 4109 #clock-cells = <1>; 4110 #phy-cells = <0>; 4111 4112 status = "disabled"; 4113 }; 4114 4115 mdss_dp: displayport-controller@ae90000 { 4116 compatible = "qcom,sc7280-dp"; 4117 4118 reg = <0 0x0ae90000 0 0x200>, 4119 <0 0x0ae90200 0 0x200>, 4120 <0 0x0ae90400 0 0xc00>, 4121 <0 0x0ae91000 0 0x400>, 4122 <0 0x0ae91400 0 0x400>; 4123 4124 interrupt-parent = <&mdss>; 4125 interrupts = <12>; 4126 4127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4128 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4129 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4130 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4131 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4132 clock-names = "core_iface", 4133 "core_aux", 4134 "ctrl_link", 4135 "ctrl_link_iface", 4136 "stream_pixel"; 4137 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4138 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4139 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4140 phys = <&dp_phy>; 4141 phy-names = "dp"; 4142 4143 operating-points-v2 = <&dp_opp_table>; 4144 power-domains = <&rpmhpd SC7280_CX>; 4145 4146 #sound-dai-cells = <0>; 4147 4148 status = "disabled"; 4149 4150 ports { 4151 #address-cells = <1>; 4152 #size-cells = <0>; 4153 4154 port@0 { 4155 reg = <0>; 4156 dp_in: endpoint { 4157 remote-endpoint = <&dpu_intf0_out>; 4158 }; 4159 }; 4160 4161 port@1 { 4162 reg = <1>; 4163 mdss_dp_out: endpoint { }; 4164 }; 4165 }; 4166 4167 dp_opp_table: opp-table { 4168 compatible = "operating-points-v2"; 4169 4170 opp-160000000 { 4171 opp-hz = /bits/ 64 <160000000>; 4172 required-opps = <&rpmhpd_opp_low_svs>; 4173 }; 4174 4175 opp-270000000 { 4176 opp-hz = /bits/ 64 <270000000>; 4177 required-opps = <&rpmhpd_opp_svs>; 4178 }; 4179 4180 opp-540000000 { 4181 opp-hz = /bits/ 64 <540000000>; 4182 required-opps = <&rpmhpd_opp_svs_l1>; 4183 }; 4184 4185 opp-810000000 { 4186 opp-hz = /bits/ 64 <810000000>; 4187 required-opps = <&rpmhpd_opp_nom>; 4188 }; 4189 }; 4190 }; 4191 }; 4192 4193 pdc: interrupt-controller@b220000 { 4194 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4195 reg = <0 0x0b220000 0 0x30000>; 4196 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4197 <55 306 4>, <59 312 3>, <62 374 2>, 4198 <64 434 2>, <66 438 3>, <69 86 1>, 4199 <70 520 54>, <124 609 31>, <155 63 1>, 4200 <156 716 12>; 4201 #interrupt-cells = <2>; 4202 interrupt-parent = <&intc>; 4203 interrupt-controller; 4204 }; 4205 4206 pdc_reset: reset-controller@b5e0000 { 4207 compatible = "qcom,sc7280-pdc-global"; 4208 reg = <0 0x0b5e0000 0 0x20000>; 4209 #reset-cells = <1>; 4210 }; 4211 4212 tsens0: thermal-sensor@c263000 { 4213 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4214 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4215 <0 0x0c222000 0 0x1ff>; /* SROT */ 4216 #qcom,sensors = <15>; 4217 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4219 interrupt-names = "uplow","critical"; 4220 #thermal-sensor-cells = <1>; 4221 }; 4222 4223 tsens1: thermal-sensor@c265000 { 4224 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4225 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4226 <0 0x0c223000 0 0x1ff>; /* SROT */ 4227 #qcom,sensors = <12>; 4228 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4230 interrupt-names = "uplow","critical"; 4231 #thermal-sensor-cells = <1>; 4232 }; 4233 4234 aoss_reset: reset-controller@c2a0000 { 4235 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4236 reg = <0 0x0c2a0000 0 0x31000>; 4237 #reset-cells = <1>; 4238 }; 4239 4240 aoss_qmp: power-management@c300000 { 4241 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4242 reg = <0 0x0c300000 0 0x400>; 4243 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4244 IPCC_MPROC_SIGNAL_GLINK_QMP 4245 IRQ_TYPE_EDGE_RISING>; 4246 mboxes = <&ipcc IPCC_CLIENT_AOP 4247 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4248 4249 #clock-cells = <0>; 4250 }; 4251 4252 sram@c3f0000 { 4253 compatible = "qcom,rpmh-stats"; 4254 reg = <0 0x0c3f0000 0 0x400>; 4255 }; 4256 4257 spmi_bus: spmi@c440000 { 4258 compatible = "qcom,spmi-pmic-arb"; 4259 reg = <0 0x0c440000 0 0x1100>, 4260 <0 0x0c600000 0 0x2000000>, 4261 <0 0x0e600000 0 0x100000>, 4262 <0 0x0e700000 0 0xa0000>, 4263 <0 0x0c40a000 0 0x26000>; 4264 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4265 interrupt-names = "periph_irq"; 4266 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4267 qcom,ee = <0>; 4268 qcom,channel = <0>; 4269 #address-cells = <2>; 4270 #size-cells = <0>; 4271 interrupt-controller; 4272 #interrupt-cells = <4>; 4273 }; 4274 4275 tlmm: pinctrl@f100000 { 4276 compatible = "qcom,sc7280-pinctrl"; 4277 reg = <0 0x0f100000 0 0x300000>; 4278 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4279 gpio-controller; 4280 #gpio-cells = <2>; 4281 interrupt-controller; 4282 #interrupt-cells = <2>; 4283 gpio-ranges = <&tlmm 0 0 175>; 4284 wakeup-parent = <&pdc>; 4285 4286 dp_hot_plug_det: dp-hot-plug-det-state { 4287 pins = "gpio47"; 4288 function = "dp_hot"; 4289 }; 4290 4291 edp_hot_plug_det: edp-hot-plug-det-state { 4292 pins = "gpio60"; 4293 function = "edp_hot"; 4294 }; 4295 4296 mi2s0_data0: mi2s0-data0-state { 4297 pins = "gpio98"; 4298 function = "mi2s0_data0"; 4299 }; 4300 4301 mi2s0_data1: mi2s0-data1-state { 4302 pins = "gpio99"; 4303 function = "mi2s0_data1"; 4304 }; 4305 4306 mi2s0_mclk: mi2s0-mclk-state { 4307 pins = "gpio96"; 4308 function = "pri_mi2s"; 4309 }; 4310 4311 mi2s0_sclk: mi2s0-sclk-state { 4312 pins = "gpio97"; 4313 function = "mi2s0_sck"; 4314 }; 4315 4316 mi2s0_ws: mi2s0-ws-state { 4317 pins = "gpio100"; 4318 function = "mi2s0_ws"; 4319 }; 4320 4321 mi2s1_data0: mi2s1-data0-state { 4322 pins = "gpio107"; 4323 function = "mi2s1_data0"; 4324 }; 4325 4326 mi2s1_sclk: mi2s1-sclk-state { 4327 pins = "gpio106"; 4328 function = "mi2s1_sck"; 4329 }; 4330 4331 mi2s1_ws: mi2s1-ws-state { 4332 pins = "gpio108"; 4333 function = "mi2s1_ws"; 4334 }; 4335 4336 pcie1_clkreq_n: pcie1-clkreq-n-state { 4337 pins = "gpio79"; 4338 function = "pcie1_clkreqn"; 4339 }; 4340 4341 qspi_clk: qspi-clk-state { 4342 pins = "gpio14"; 4343 function = "qspi_clk"; 4344 }; 4345 4346 qspi_cs0: qspi-cs0-state { 4347 pins = "gpio15"; 4348 function = "qspi_cs"; 4349 }; 4350 4351 qspi_cs1: qspi-cs1-state { 4352 pins = "gpio19"; 4353 function = "qspi_cs"; 4354 }; 4355 4356 qspi_data0: qspi-data0-state { 4357 pins = "gpio12"; 4358 function = "qspi_data"; 4359 }; 4360 4361 qspi_data1: qspi-data1-state { 4362 pins = "gpio13"; 4363 function = "qspi_data"; 4364 }; 4365 4366 qspi_data23: qspi-data23-state { 4367 pins = "gpio16", "gpio17"; 4368 function = "qspi_data"; 4369 }; 4370 4371 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4372 pins = "gpio0", "gpio1"; 4373 function = "qup00"; 4374 }; 4375 4376 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4377 pins = "gpio4", "gpio5"; 4378 function = "qup01"; 4379 }; 4380 4381 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4382 pins = "gpio8", "gpio9"; 4383 function = "qup02"; 4384 }; 4385 4386 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4387 pins = "gpio12", "gpio13"; 4388 function = "qup03"; 4389 }; 4390 4391 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4392 pins = "gpio16", "gpio17"; 4393 function = "qup04"; 4394 }; 4395 4396 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4397 pins = "gpio20", "gpio21"; 4398 function = "qup05"; 4399 }; 4400 4401 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4402 pins = "gpio24", "gpio25"; 4403 function = "qup06"; 4404 }; 4405 4406 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4407 pins = "gpio28", "gpio29"; 4408 function = "qup07"; 4409 }; 4410 4411 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4412 pins = "gpio32", "gpio33"; 4413 function = "qup10"; 4414 }; 4415 4416 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4417 pins = "gpio36", "gpio37"; 4418 function = "qup11"; 4419 }; 4420 4421 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4422 pins = "gpio40", "gpio41"; 4423 function = "qup12"; 4424 }; 4425 4426 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4427 pins = "gpio44", "gpio45"; 4428 function = "qup13"; 4429 }; 4430 4431 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4432 pins = "gpio48", "gpio49"; 4433 function = "qup14"; 4434 }; 4435 4436 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4437 pins = "gpio52", "gpio53"; 4438 function = "qup15"; 4439 }; 4440 4441 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4442 pins = "gpio56", "gpio57"; 4443 function = "qup16"; 4444 }; 4445 4446 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4447 pins = "gpio60", "gpio61"; 4448 function = "qup17"; 4449 }; 4450 4451 qup_spi0_data_clk: qup-spi0-data-clk-state { 4452 pins = "gpio0", "gpio1", "gpio2"; 4453 function = "qup00"; 4454 }; 4455 4456 qup_spi0_cs: qup-spi0-cs-state { 4457 pins = "gpio3"; 4458 function = "qup00"; 4459 }; 4460 4461 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4462 pins = "gpio3"; 4463 function = "gpio"; 4464 }; 4465 4466 qup_spi1_data_clk: qup-spi1-data-clk-state { 4467 pins = "gpio4", "gpio5", "gpio6"; 4468 function = "qup01"; 4469 }; 4470 4471 qup_spi1_cs: qup-spi1-cs-state { 4472 pins = "gpio7"; 4473 function = "qup01"; 4474 }; 4475 4476 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4477 pins = "gpio7"; 4478 function = "gpio"; 4479 }; 4480 4481 qup_spi2_data_clk: qup-spi2-data-clk-state { 4482 pins = "gpio8", "gpio9", "gpio10"; 4483 function = "qup02"; 4484 }; 4485 4486 qup_spi2_cs: qup-spi2-cs-state { 4487 pins = "gpio11"; 4488 function = "qup02"; 4489 }; 4490 4491 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4492 pins = "gpio11"; 4493 function = "gpio"; 4494 }; 4495 4496 qup_spi3_data_clk: qup-spi3-data-clk-state { 4497 pins = "gpio12", "gpio13", "gpio14"; 4498 function = "qup03"; 4499 }; 4500 4501 qup_spi3_cs: qup-spi3-cs-state { 4502 pins = "gpio15"; 4503 function = "qup03"; 4504 }; 4505 4506 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4507 pins = "gpio15"; 4508 function = "gpio"; 4509 }; 4510 4511 qup_spi4_data_clk: qup-spi4-data-clk-state { 4512 pins = "gpio16", "gpio17", "gpio18"; 4513 function = "qup04"; 4514 }; 4515 4516 qup_spi4_cs: qup-spi4-cs-state { 4517 pins = "gpio19"; 4518 function = "qup04"; 4519 }; 4520 4521 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4522 pins = "gpio19"; 4523 function = "gpio"; 4524 }; 4525 4526 qup_spi5_data_clk: qup-spi5-data-clk-state { 4527 pins = "gpio20", "gpio21", "gpio22"; 4528 function = "qup05"; 4529 }; 4530 4531 qup_spi5_cs: qup-spi5-cs-state { 4532 pins = "gpio23"; 4533 function = "qup05"; 4534 }; 4535 4536 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4537 pins = "gpio23"; 4538 function = "gpio"; 4539 }; 4540 4541 qup_spi6_data_clk: qup-spi6-data-clk-state { 4542 pins = "gpio24", "gpio25", "gpio26"; 4543 function = "qup06"; 4544 }; 4545 4546 qup_spi6_cs: qup-spi6-cs-state { 4547 pins = "gpio27"; 4548 function = "qup06"; 4549 }; 4550 4551 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4552 pins = "gpio27"; 4553 function = "gpio"; 4554 }; 4555 4556 qup_spi7_data_clk: qup-spi7-data-clk-state { 4557 pins = "gpio28", "gpio29", "gpio30"; 4558 function = "qup07"; 4559 }; 4560 4561 qup_spi7_cs: qup-spi7-cs-state { 4562 pins = "gpio31"; 4563 function = "qup07"; 4564 }; 4565 4566 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4567 pins = "gpio31"; 4568 function = "gpio"; 4569 }; 4570 4571 qup_spi8_data_clk: qup-spi8-data-clk-state { 4572 pins = "gpio32", "gpio33", "gpio34"; 4573 function = "qup10"; 4574 }; 4575 4576 qup_spi8_cs: qup-spi8-cs-state { 4577 pins = "gpio35"; 4578 function = "qup10"; 4579 }; 4580 4581 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4582 pins = "gpio35"; 4583 function = "gpio"; 4584 }; 4585 4586 qup_spi9_data_clk: qup-spi9-data-clk-state { 4587 pins = "gpio36", "gpio37", "gpio38"; 4588 function = "qup11"; 4589 }; 4590 4591 qup_spi9_cs: qup-spi9-cs-state { 4592 pins = "gpio39"; 4593 function = "qup11"; 4594 }; 4595 4596 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4597 pins = "gpio39"; 4598 function = "gpio"; 4599 }; 4600 4601 qup_spi10_data_clk: qup-spi10-data-clk-state { 4602 pins = "gpio40", "gpio41", "gpio42"; 4603 function = "qup12"; 4604 }; 4605 4606 qup_spi10_cs: qup-spi10-cs-state { 4607 pins = "gpio43"; 4608 function = "qup12"; 4609 }; 4610 4611 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4612 pins = "gpio43"; 4613 function = "gpio"; 4614 }; 4615 4616 qup_spi11_data_clk: qup-spi11-data-clk-state { 4617 pins = "gpio44", "gpio45", "gpio46"; 4618 function = "qup13"; 4619 }; 4620 4621 qup_spi11_cs: qup-spi11-cs-state { 4622 pins = "gpio47"; 4623 function = "qup13"; 4624 }; 4625 4626 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4627 pins = "gpio47"; 4628 function = "gpio"; 4629 }; 4630 4631 qup_spi12_data_clk: qup-spi12-data-clk-state { 4632 pins = "gpio48", "gpio49", "gpio50"; 4633 function = "qup14"; 4634 }; 4635 4636 qup_spi12_cs: qup-spi12-cs-state { 4637 pins = "gpio51"; 4638 function = "qup14"; 4639 }; 4640 4641 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4642 pins = "gpio51"; 4643 function = "gpio"; 4644 }; 4645 4646 qup_spi13_data_clk: qup-spi13-data-clk-state { 4647 pins = "gpio52", "gpio53", "gpio54"; 4648 function = "qup15"; 4649 }; 4650 4651 qup_spi13_cs: qup-spi13-cs-state { 4652 pins = "gpio55"; 4653 function = "qup15"; 4654 }; 4655 4656 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4657 pins = "gpio55"; 4658 function = "gpio"; 4659 }; 4660 4661 qup_spi14_data_clk: qup-spi14-data-clk-state { 4662 pins = "gpio56", "gpio57", "gpio58"; 4663 function = "qup16"; 4664 }; 4665 4666 qup_spi14_cs: qup-spi14-cs-state { 4667 pins = "gpio59"; 4668 function = "qup16"; 4669 }; 4670 4671 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4672 pins = "gpio59"; 4673 function = "gpio"; 4674 }; 4675 4676 qup_spi15_data_clk: qup-spi15-data-clk-state { 4677 pins = "gpio60", "gpio61", "gpio62"; 4678 function = "qup17"; 4679 }; 4680 4681 qup_spi15_cs: qup-spi15-cs-state { 4682 pins = "gpio63"; 4683 function = "qup17"; 4684 }; 4685 4686 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4687 pins = "gpio63"; 4688 function = "gpio"; 4689 }; 4690 4691 qup_uart0_cts: qup-uart0-cts-state { 4692 pins = "gpio0"; 4693 function = "qup00"; 4694 }; 4695 4696 qup_uart0_rts: qup-uart0-rts-state { 4697 pins = "gpio1"; 4698 function = "qup00"; 4699 }; 4700 4701 qup_uart0_tx: qup-uart0-tx-state { 4702 pins = "gpio2"; 4703 function = "qup00"; 4704 }; 4705 4706 qup_uart0_rx: qup-uart0-rx-state { 4707 pins = "gpio3"; 4708 function = "qup00"; 4709 }; 4710 4711 qup_uart1_cts: qup-uart1-cts-state { 4712 pins = "gpio4"; 4713 function = "qup01"; 4714 }; 4715 4716 qup_uart1_rts: qup-uart1-rts-state { 4717 pins = "gpio5"; 4718 function = "qup01"; 4719 }; 4720 4721 qup_uart1_tx: qup-uart1-tx-state { 4722 pins = "gpio6"; 4723 function = "qup01"; 4724 }; 4725 4726 qup_uart1_rx: qup-uart1-rx-state { 4727 pins = "gpio7"; 4728 function = "qup01"; 4729 }; 4730 4731 qup_uart2_cts: qup-uart2-cts-state { 4732 pins = "gpio8"; 4733 function = "qup02"; 4734 }; 4735 4736 qup_uart2_rts: qup-uart2-rts-state { 4737 pins = "gpio9"; 4738 function = "qup02"; 4739 }; 4740 4741 qup_uart2_tx: qup-uart2-tx-state { 4742 pins = "gpio10"; 4743 function = "qup02"; 4744 }; 4745 4746 qup_uart2_rx: qup-uart2-rx-state { 4747 pins = "gpio11"; 4748 function = "qup02"; 4749 }; 4750 4751 qup_uart3_cts: qup-uart3-cts-state { 4752 pins = "gpio12"; 4753 function = "qup03"; 4754 }; 4755 4756 qup_uart3_rts: qup-uart3-rts-state { 4757 pins = "gpio13"; 4758 function = "qup03"; 4759 }; 4760 4761 qup_uart3_tx: qup-uart3-tx-state { 4762 pins = "gpio14"; 4763 function = "qup03"; 4764 }; 4765 4766 qup_uart3_rx: qup-uart3-rx-state { 4767 pins = "gpio15"; 4768 function = "qup03"; 4769 }; 4770 4771 qup_uart4_cts: qup-uart4-cts-state { 4772 pins = "gpio16"; 4773 function = "qup04"; 4774 }; 4775 4776 qup_uart4_rts: qup-uart4-rts-state { 4777 pins = "gpio17"; 4778 function = "qup04"; 4779 }; 4780 4781 qup_uart4_tx: qup-uart4-tx-state { 4782 pins = "gpio18"; 4783 function = "qup04"; 4784 }; 4785 4786 qup_uart4_rx: qup-uart4-rx-state { 4787 pins = "gpio19"; 4788 function = "qup04"; 4789 }; 4790 4791 qup_uart5_cts: qup-uart5-cts-state { 4792 pins = "gpio20"; 4793 function = "qup05"; 4794 }; 4795 4796 qup_uart5_rts: qup-uart5-rts-state { 4797 pins = "gpio21"; 4798 function = "qup05"; 4799 }; 4800 4801 qup_uart5_tx: qup-uart5-tx-state { 4802 pins = "gpio22"; 4803 function = "qup05"; 4804 }; 4805 4806 qup_uart5_rx: qup-uart5-rx-state { 4807 pins = "gpio23"; 4808 function = "qup05"; 4809 }; 4810 4811 qup_uart6_cts: qup-uart6-cts-state { 4812 pins = "gpio24"; 4813 function = "qup06"; 4814 }; 4815 4816 qup_uart6_rts: qup-uart6-rts-state { 4817 pins = "gpio25"; 4818 function = "qup06"; 4819 }; 4820 4821 qup_uart6_tx: qup-uart6-tx-state { 4822 pins = "gpio26"; 4823 function = "qup06"; 4824 }; 4825 4826 qup_uart6_rx: qup-uart6-rx-state { 4827 pins = "gpio27"; 4828 function = "qup06"; 4829 }; 4830 4831 qup_uart7_cts: qup-uart7-cts-state { 4832 pins = "gpio28"; 4833 function = "qup07"; 4834 }; 4835 4836 qup_uart7_rts: qup-uart7-rts-state { 4837 pins = "gpio29"; 4838 function = "qup07"; 4839 }; 4840 4841 qup_uart7_tx: qup-uart7-tx-state { 4842 pins = "gpio30"; 4843 function = "qup07"; 4844 }; 4845 4846 qup_uart7_rx: qup-uart7-rx-state { 4847 pins = "gpio31"; 4848 function = "qup07"; 4849 }; 4850 4851 qup_uart8_cts: qup-uart8-cts-state { 4852 pins = "gpio32"; 4853 function = "qup10"; 4854 }; 4855 4856 qup_uart8_rts: qup-uart8-rts-state { 4857 pins = "gpio33"; 4858 function = "qup10"; 4859 }; 4860 4861 qup_uart8_tx: qup-uart8-tx-state { 4862 pins = "gpio34"; 4863 function = "qup10"; 4864 }; 4865 4866 qup_uart8_rx: qup-uart8-rx-state { 4867 pins = "gpio35"; 4868 function = "qup10"; 4869 }; 4870 4871 qup_uart9_cts: qup-uart9-cts-state { 4872 pins = "gpio36"; 4873 function = "qup11"; 4874 }; 4875 4876 qup_uart9_rts: qup-uart9-rts-state { 4877 pins = "gpio37"; 4878 function = "qup11"; 4879 }; 4880 4881 qup_uart9_tx: qup-uart9-tx-state { 4882 pins = "gpio38"; 4883 function = "qup11"; 4884 }; 4885 4886 qup_uart9_rx: qup-uart9-rx-state { 4887 pins = "gpio39"; 4888 function = "qup11"; 4889 }; 4890 4891 qup_uart10_cts: qup-uart10-cts-state { 4892 pins = "gpio40"; 4893 function = "qup12"; 4894 }; 4895 4896 qup_uart10_rts: qup-uart10-rts-state { 4897 pins = "gpio41"; 4898 function = "qup12"; 4899 }; 4900 4901 qup_uart10_tx: qup-uart10-tx-state { 4902 pins = "gpio42"; 4903 function = "qup12"; 4904 }; 4905 4906 qup_uart10_rx: qup-uart10-rx-state { 4907 pins = "gpio43"; 4908 function = "qup12"; 4909 }; 4910 4911 qup_uart11_cts: qup-uart11-cts-state { 4912 pins = "gpio44"; 4913 function = "qup13"; 4914 }; 4915 4916 qup_uart11_rts: qup-uart11-rts-state { 4917 pins = "gpio45"; 4918 function = "qup13"; 4919 }; 4920 4921 qup_uart11_tx: qup-uart11-tx-state { 4922 pins = "gpio46"; 4923 function = "qup13"; 4924 }; 4925 4926 qup_uart11_rx: qup-uart11-rx-state { 4927 pins = "gpio47"; 4928 function = "qup13"; 4929 }; 4930 4931 qup_uart12_cts: qup-uart12-cts-state { 4932 pins = "gpio48"; 4933 function = "qup14"; 4934 }; 4935 4936 qup_uart12_rts: qup-uart12-rts-state { 4937 pins = "gpio49"; 4938 function = "qup14"; 4939 }; 4940 4941 qup_uart12_tx: qup-uart12-tx-state { 4942 pins = "gpio50"; 4943 function = "qup14"; 4944 }; 4945 4946 qup_uart12_rx: qup-uart12-rx-state { 4947 pins = "gpio51"; 4948 function = "qup14"; 4949 }; 4950 4951 qup_uart13_cts: qup-uart13-cts-state { 4952 pins = "gpio52"; 4953 function = "qup15"; 4954 }; 4955 4956 qup_uart13_rts: qup-uart13-rts-state { 4957 pins = "gpio53"; 4958 function = "qup15"; 4959 }; 4960 4961 qup_uart13_tx: qup-uart13-tx-state { 4962 pins = "gpio54"; 4963 function = "qup15"; 4964 }; 4965 4966 qup_uart13_rx: qup-uart13-rx-state { 4967 pins = "gpio55"; 4968 function = "qup15"; 4969 }; 4970 4971 qup_uart14_cts: qup-uart14-cts-state { 4972 pins = "gpio56"; 4973 function = "qup16"; 4974 }; 4975 4976 qup_uart14_rts: qup-uart14-rts-state { 4977 pins = "gpio57"; 4978 function = "qup16"; 4979 }; 4980 4981 qup_uart14_tx: qup-uart14-tx-state { 4982 pins = "gpio58"; 4983 function = "qup16"; 4984 }; 4985 4986 qup_uart14_rx: qup-uart14-rx-state { 4987 pins = "gpio59"; 4988 function = "qup16"; 4989 }; 4990 4991 qup_uart15_cts: qup-uart15-cts-state { 4992 pins = "gpio60"; 4993 function = "qup17"; 4994 }; 4995 4996 qup_uart15_rts: qup-uart15-rts-state { 4997 pins = "gpio61"; 4998 function = "qup17"; 4999 }; 5000 5001 qup_uart15_tx: qup-uart15-tx-state { 5002 pins = "gpio62"; 5003 function = "qup17"; 5004 }; 5005 5006 qup_uart15_rx: qup-uart15-rx-state { 5007 pins = "gpio63"; 5008 function = "qup17"; 5009 }; 5010 5011 sdc1_clk: sdc1-clk-state { 5012 pins = "sdc1_clk"; 5013 }; 5014 5015 sdc1_cmd: sdc1-cmd-state { 5016 pins = "sdc1_cmd"; 5017 }; 5018 5019 sdc1_data: sdc1-data-state { 5020 pins = "sdc1_data"; 5021 }; 5022 5023 sdc1_rclk: sdc1-rclk-state { 5024 pins = "sdc1_rclk"; 5025 }; 5026 5027 sdc1_clk_sleep: sdc1-clk-sleep-state { 5028 pins = "sdc1_clk"; 5029 drive-strength = <2>; 5030 bias-bus-hold; 5031 }; 5032 5033 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5034 pins = "sdc1_cmd"; 5035 drive-strength = <2>; 5036 bias-bus-hold; 5037 }; 5038 5039 sdc1_data_sleep: sdc1-data-sleep-state { 5040 pins = "sdc1_data"; 5041 drive-strength = <2>; 5042 bias-bus-hold; 5043 }; 5044 5045 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5046 pins = "sdc1_rclk"; 5047 drive-strength = <2>; 5048 bias-bus-hold; 5049 }; 5050 5051 sdc2_clk: sdc2-clk-state { 5052 pins = "sdc2_clk"; 5053 }; 5054 5055 sdc2_cmd: sdc2-cmd-state { 5056 pins = "sdc2_cmd"; 5057 }; 5058 5059 sdc2_data: sdc2-data-state { 5060 pins = "sdc2_data"; 5061 }; 5062 5063 sdc2_clk_sleep: sdc2-clk-sleep-state { 5064 pins = "sdc2_clk"; 5065 drive-strength = <2>; 5066 bias-bus-hold; 5067 }; 5068 5069 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5070 pins = "sdc2_cmd"; 5071 drive-strength = <2>; 5072 bias-bus-hold; 5073 }; 5074 5075 sdc2_data_sleep: sdc2-data-sleep-state { 5076 pins = "sdc2_data"; 5077 drive-strength = <2>; 5078 bias-bus-hold; 5079 }; 5080 }; 5081 5082 sram@146a5000 { 5083 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5084 reg = <0 0x146a5000 0 0x6000>; 5085 5086 #address-cells = <1>; 5087 #size-cells = <1>; 5088 5089 ranges = <0 0 0x146a5000 0x6000>; 5090 5091 pil-reloc@594c { 5092 compatible = "qcom,pil-reloc-info"; 5093 reg = <0x594c 0xc8>; 5094 }; 5095 }; 5096 5097 apps_smmu: iommu@15000000 { 5098 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5099 reg = <0 0x15000000 0 0x100000>; 5100 #iommu-cells = <2>; 5101 #global-interrupts = <1>; 5102 dma-coherent; 5103 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5184 }; 5185 5186 intc: interrupt-controller@17a00000 { 5187 compatible = "arm,gic-v3"; 5188 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5189 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5190 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5191 #interrupt-cells = <3>; 5192 interrupt-controller; 5193 #address-cells = <2>; 5194 #size-cells = <2>; 5195 ranges; 5196 5197 msi-controller@17a40000 { 5198 compatible = "arm,gic-v3-its"; 5199 reg = <0 0x17a40000 0 0x20000>; 5200 msi-controller; 5201 #msi-cells = <1>; 5202 status = "disabled"; 5203 }; 5204 }; 5205 5206 watchdog@17c10000 { 5207 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5208 reg = <0 0x17c10000 0 0x1000>; 5209 clocks = <&sleep_clk>; 5210 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5211 }; 5212 5213 timer@17c20000 { 5214 #address-cells = <1>; 5215 #size-cells = <1>; 5216 ranges = <0 0 0 0x20000000>; 5217 compatible = "arm,armv7-timer-mem"; 5218 reg = <0 0x17c20000 0 0x1000>; 5219 5220 frame@17c21000 { 5221 frame-number = <0>; 5222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5223 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5224 reg = <0x17c21000 0x1000>, 5225 <0x17c22000 0x1000>; 5226 }; 5227 5228 frame@17c23000 { 5229 frame-number = <1>; 5230 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5231 reg = <0x17c23000 0x1000>; 5232 status = "disabled"; 5233 }; 5234 5235 frame@17c25000 { 5236 frame-number = <2>; 5237 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5238 reg = <0x17c25000 0x1000>; 5239 status = "disabled"; 5240 }; 5241 5242 frame@17c27000 { 5243 frame-number = <3>; 5244 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5245 reg = <0x17c27000 0x1000>; 5246 status = "disabled"; 5247 }; 5248 5249 frame@17c29000 { 5250 frame-number = <4>; 5251 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5252 reg = <0x17c29000 0x1000>; 5253 status = "disabled"; 5254 }; 5255 5256 frame@17c2b000 { 5257 frame-number = <5>; 5258 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5259 reg = <0x17c2b000 0x1000>; 5260 status = "disabled"; 5261 }; 5262 5263 frame@17c2d000 { 5264 frame-number = <6>; 5265 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5266 reg = <0x17c2d000 0x1000>; 5267 status = "disabled"; 5268 }; 5269 }; 5270 5271 apps_rsc: rsc@18200000 { 5272 compatible = "qcom,rpmh-rsc"; 5273 reg = <0 0x18200000 0 0x10000>, 5274 <0 0x18210000 0 0x10000>, 5275 <0 0x18220000 0 0x10000>; 5276 reg-names = "drv-0", "drv-1", "drv-2"; 5277 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5278 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5279 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5280 qcom,tcs-offset = <0xd00>; 5281 qcom,drv-id = <2>; 5282 qcom,tcs-config = <ACTIVE_TCS 2>, 5283 <SLEEP_TCS 3>, 5284 <WAKE_TCS 3>, 5285 <CONTROL_TCS 1>; 5286 5287 apps_bcm_voter: bcm-voter { 5288 compatible = "qcom,bcm-voter"; 5289 }; 5290 5291 rpmhpd: power-controller { 5292 compatible = "qcom,sc7280-rpmhpd"; 5293 #power-domain-cells = <1>; 5294 operating-points-v2 = <&rpmhpd_opp_table>; 5295 5296 rpmhpd_opp_table: opp-table { 5297 compatible = "operating-points-v2"; 5298 5299 rpmhpd_opp_ret: opp1 { 5300 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5301 }; 5302 5303 rpmhpd_opp_low_svs: opp2 { 5304 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5305 }; 5306 5307 rpmhpd_opp_svs: opp3 { 5308 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5309 }; 5310 5311 rpmhpd_opp_svs_l1: opp4 { 5312 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5313 }; 5314 5315 rpmhpd_opp_svs_l2: opp5 { 5316 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5317 }; 5318 5319 rpmhpd_opp_nom: opp6 { 5320 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5321 }; 5322 5323 rpmhpd_opp_nom_l1: opp7 { 5324 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5325 }; 5326 5327 rpmhpd_opp_turbo: opp8 { 5328 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5329 }; 5330 5331 rpmhpd_opp_turbo_l1: opp9 { 5332 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5333 }; 5334 }; 5335 }; 5336 5337 rpmhcc: clock-controller { 5338 compatible = "qcom,sc7280-rpmh-clk"; 5339 clocks = <&xo_board>; 5340 clock-names = "xo"; 5341 #clock-cells = <1>; 5342 }; 5343 }; 5344 5345 epss_l3: interconnect@18590000 { 5346 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5347 reg = <0 0x18590000 0 0x1000>; 5348 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5349 clock-names = "xo", "alternate"; 5350 #interconnect-cells = <1>; 5351 }; 5352 5353 cpufreq_hw: cpufreq@18591000 { 5354 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5355 reg = <0 0x18591000 0 0x1000>, 5356 <0 0x18592000 0 0x1000>, 5357 <0 0x18593000 0 0x1000>; 5358 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5359 clock-names = "xo", "alternate"; 5360 #freq-domain-cells = <1>; 5361 #clock-cells = <1>; 5362 }; 5363 }; 5364 5365 thermal_zones: thermal-zones { 5366 cpu0-thermal { 5367 polling-delay-passive = <250>; 5368 polling-delay = <0>; 5369 5370 thermal-sensors = <&tsens0 1>; 5371 5372 trips { 5373 cpu0_alert0: trip-point0 { 5374 temperature = <90000>; 5375 hysteresis = <2000>; 5376 type = "passive"; 5377 }; 5378 5379 cpu0_alert1: trip-point1 { 5380 temperature = <95000>; 5381 hysteresis = <2000>; 5382 type = "passive"; 5383 }; 5384 5385 cpu0_crit: cpu-crit { 5386 temperature = <110000>; 5387 hysteresis = <0>; 5388 type = "critical"; 5389 }; 5390 }; 5391 5392 cooling-maps { 5393 map0 { 5394 trip = <&cpu0_alert0>; 5395 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5396 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5397 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5398 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5399 }; 5400 map1 { 5401 trip = <&cpu0_alert1>; 5402 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5403 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5406 }; 5407 }; 5408 }; 5409 5410 cpu1-thermal { 5411 polling-delay-passive = <250>; 5412 polling-delay = <0>; 5413 5414 thermal-sensors = <&tsens0 2>; 5415 5416 trips { 5417 cpu1_alert0: trip-point0 { 5418 temperature = <90000>; 5419 hysteresis = <2000>; 5420 type = "passive"; 5421 }; 5422 5423 cpu1_alert1: trip-point1 { 5424 temperature = <95000>; 5425 hysteresis = <2000>; 5426 type = "passive"; 5427 }; 5428 5429 cpu1_crit: cpu-crit { 5430 temperature = <110000>; 5431 hysteresis = <0>; 5432 type = "critical"; 5433 }; 5434 }; 5435 5436 cooling-maps { 5437 map0 { 5438 trip = <&cpu1_alert0>; 5439 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5440 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5441 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5442 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5443 }; 5444 map1 { 5445 trip = <&cpu1_alert1>; 5446 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5447 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5450 }; 5451 }; 5452 }; 5453 5454 cpu2-thermal { 5455 polling-delay-passive = <250>; 5456 polling-delay = <0>; 5457 5458 thermal-sensors = <&tsens0 3>; 5459 5460 trips { 5461 cpu2_alert0: trip-point0 { 5462 temperature = <90000>; 5463 hysteresis = <2000>; 5464 type = "passive"; 5465 }; 5466 5467 cpu2_alert1: trip-point1 { 5468 temperature = <95000>; 5469 hysteresis = <2000>; 5470 type = "passive"; 5471 }; 5472 5473 cpu2_crit: cpu-crit { 5474 temperature = <110000>; 5475 hysteresis = <0>; 5476 type = "critical"; 5477 }; 5478 }; 5479 5480 cooling-maps { 5481 map0 { 5482 trip = <&cpu2_alert0>; 5483 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5484 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5485 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5486 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5487 }; 5488 map1 { 5489 trip = <&cpu2_alert1>; 5490 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5491 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5494 }; 5495 }; 5496 }; 5497 5498 cpu3-thermal { 5499 polling-delay-passive = <250>; 5500 polling-delay = <0>; 5501 5502 thermal-sensors = <&tsens0 4>; 5503 5504 trips { 5505 cpu3_alert0: trip-point0 { 5506 temperature = <90000>; 5507 hysteresis = <2000>; 5508 type = "passive"; 5509 }; 5510 5511 cpu3_alert1: trip-point1 { 5512 temperature = <95000>; 5513 hysteresis = <2000>; 5514 type = "passive"; 5515 }; 5516 5517 cpu3_crit: cpu-crit { 5518 temperature = <110000>; 5519 hysteresis = <0>; 5520 type = "critical"; 5521 }; 5522 }; 5523 5524 cooling-maps { 5525 map0 { 5526 trip = <&cpu3_alert0>; 5527 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5528 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5529 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5530 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5531 }; 5532 map1 { 5533 trip = <&cpu3_alert1>; 5534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5538 }; 5539 }; 5540 }; 5541 5542 cpu4-thermal { 5543 polling-delay-passive = <250>; 5544 polling-delay = <0>; 5545 5546 thermal-sensors = <&tsens0 7>; 5547 5548 trips { 5549 cpu4_alert0: trip-point0 { 5550 temperature = <90000>; 5551 hysteresis = <2000>; 5552 type = "passive"; 5553 }; 5554 5555 cpu4_alert1: trip-point1 { 5556 temperature = <95000>; 5557 hysteresis = <2000>; 5558 type = "passive"; 5559 }; 5560 5561 cpu4_crit: cpu-crit { 5562 temperature = <110000>; 5563 hysteresis = <0>; 5564 type = "critical"; 5565 }; 5566 }; 5567 5568 cooling-maps { 5569 map0 { 5570 trip = <&cpu4_alert0>; 5571 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5572 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5573 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5574 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5575 }; 5576 map1 { 5577 trip = <&cpu4_alert1>; 5578 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5582 }; 5583 }; 5584 }; 5585 5586 cpu5-thermal { 5587 polling-delay-passive = <250>; 5588 polling-delay = <0>; 5589 5590 thermal-sensors = <&tsens0 8>; 5591 5592 trips { 5593 cpu5_alert0: trip-point0 { 5594 temperature = <90000>; 5595 hysteresis = <2000>; 5596 type = "passive"; 5597 }; 5598 5599 cpu5_alert1: trip-point1 { 5600 temperature = <95000>; 5601 hysteresis = <2000>; 5602 type = "passive"; 5603 }; 5604 5605 cpu5_crit: cpu-crit { 5606 temperature = <110000>; 5607 hysteresis = <0>; 5608 type = "critical"; 5609 }; 5610 }; 5611 5612 cooling-maps { 5613 map0 { 5614 trip = <&cpu5_alert0>; 5615 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5616 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5617 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5618 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5619 }; 5620 map1 { 5621 trip = <&cpu5_alert1>; 5622 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5623 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5626 }; 5627 }; 5628 }; 5629 5630 cpu6-thermal { 5631 polling-delay-passive = <250>; 5632 polling-delay = <0>; 5633 5634 thermal-sensors = <&tsens0 9>; 5635 5636 trips { 5637 cpu6_alert0: trip-point0 { 5638 temperature = <90000>; 5639 hysteresis = <2000>; 5640 type = "passive"; 5641 }; 5642 5643 cpu6_alert1: trip-point1 { 5644 temperature = <95000>; 5645 hysteresis = <2000>; 5646 type = "passive"; 5647 }; 5648 5649 cpu6_crit: cpu-crit { 5650 temperature = <110000>; 5651 hysteresis = <0>; 5652 type = "critical"; 5653 }; 5654 }; 5655 5656 cooling-maps { 5657 map0 { 5658 trip = <&cpu6_alert0>; 5659 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5660 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5661 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5662 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5663 }; 5664 map1 { 5665 trip = <&cpu6_alert1>; 5666 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5667 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5670 }; 5671 }; 5672 }; 5673 5674 cpu7-thermal { 5675 polling-delay-passive = <250>; 5676 polling-delay = <0>; 5677 5678 thermal-sensors = <&tsens0 10>; 5679 5680 trips { 5681 cpu7_alert0: trip-point0 { 5682 temperature = <90000>; 5683 hysteresis = <2000>; 5684 type = "passive"; 5685 }; 5686 5687 cpu7_alert1: trip-point1 { 5688 temperature = <95000>; 5689 hysteresis = <2000>; 5690 type = "passive"; 5691 }; 5692 5693 cpu7_crit: cpu-crit { 5694 temperature = <110000>; 5695 hysteresis = <0>; 5696 type = "critical"; 5697 }; 5698 }; 5699 5700 cooling-maps { 5701 map0 { 5702 trip = <&cpu7_alert0>; 5703 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5704 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5705 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5706 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5707 }; 5708 map1 { 5709 trip = <&cpu7_alert1>; 5710 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5714 }; 5715 }; 5716 }; 5717 5718 cpu8-thermal { 5719 polling-delay-passive = <250>; 5720 polling-delay = <0>; 5721 5722 thermal-sensors = <&tsens0 11>; 5723 5724 trips { 5725 cpu8_alert0: trip-point0 { 5726 temperature = <90000>; 5727 hysteresis = <2000>; 5728 type = "passive"; 5729 }; 5730 5731 cpu8_alert1: trip-point1 { 5732 temperature = <95000>; 5733 hysteresis = <2000>; 5734 type = "passive"; 5735 }; 5736 5737 cpu8_crit: cpu-crit { 5738 temperature = <110000>; 5739 hysteresis = <0>; 5740 type = "critical"; 5741 }; 5742 }; 5743 5744 cooling-maps { 5745 map0 { 5746 trip = <&cpu8_alert0>; 5747 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5748 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5749 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5750 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5751 }; 5752 map1 { 5753 trip = <&cpu8_alert1>; 5754 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5758 }; 5759 }; 5760 }; 5761 5762 cpu9-thermal { 5763 polling-delay-passive = <250>; 5764 polling-delay = <0>; 5765 5766 thermal-sensors = <&tsens0 12>; 5767 5768 trips { 5769 cpu9_alert0: trip-point0 { 5770 temperature = <90000>; 5771 hysteresis = <2000>; 5772 type = "passive"; 5773 }; 5774 5775 cpu9_alert1: trip-point1 { 5776 temperature = <95000>; 5777 hysteresis = <2000>; 5778 type = "passive"; 5779 }; 5780 5781 cpu9_crit: cpu-crit { 5782 temperature = <110000>; 5783 hysteresis = <0>; 5784 type = "critical"; 5785 }; 5786 }; 5787 5788 cooling-maps { 5789 map0 { 5790 trip = <&cpu9_alert0>; 5791 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5792 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5793 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5794 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5795 }; 5796 map1 { 5797 trip = <&cpu9_alert1>; 5798 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5802 }; 5803 }; 5804 }; 5805 5806 cpu10-thermal { 5807 polling-delay-passive = <250>; 5808 polling-delay = <0>; 5809 5810 thermal-sensors = <&tsens0 13>; 5811 5812 trips { 5813 cpu10_alert0: trip-point0 { 5814 temperature = <90000>; 5815 hysteresis = <2000>; 5816 type = "passive"; 5817 }; 5818 5819 cpu10_alert1: trip-point1 { 5820 temperature = <95000>; 5821 hysteresis = <2000>; 5822 type = "passive"; 5823 }; 5824 5825 cpu10_crit: cpu-crit { 5826 temperature = <110000>; 5827 hysteresis = <0>; 5828 type = "critical"; 5829 }; 5830 }; 5831 5832 cooling-maps { 5833 map0 { 5834 trip = <&cpu10_alert0>; 5835 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5836 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5837 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5838 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5839 }; 5840 map1 { 5841 trip = <&cpu10_alert1>; 5842 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5846 }; 5847 }; 5848 }; 5849 5850 cpu11-thermal { 5851 polling-delay-passive = <250>; 5852 polling-delay = <0>; 5853 5854 thermal-sensors = <&tsens0 14>; 5855 5856 trips { 5857 cpu11_alert0: trip-point0 { 5858 temperature = <90000>; 5859 hysteresis = <2000>; 5860 type = "passive"; 5861 }; 5862 5863 cpu11_alert1: trip-point1 { 5864 temperature = <95000>; 5865 hysteresis = <2000>; 5866 type = "passive"; 5867 }; 5868 5869 cpu11_crit: cpu-crit { 5870 temperature = <110000>; 5871 hysteresis = <0>; 5872 type = "critical"; 5873 }; 5874 }; 5875 5876 cooling-maps { 5877 map0 { 5878 trip = <&cpu11_alert0>; 5879 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5880 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5881 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5882 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5883 }; 5884 map1 { 5885 trip = <&cpu11_alert1>; 5886 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5887 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5890 }; 5891 }; 5892 }; 5893 5894 aoss0-thermal { 5895 polling-delay-passive = <0>; 5896 polling-delay = <0>; 5897 5898 thermal-sensors = <&tsens0 0>; 5899 5900 trips { 5901 aoss0_alert0: trip-point0 { 5902 temperature = <90000>; 5903 hysteresis = <2000>; 5904 type = "hot"; 5905 }; 5906 5907 aoss0_crit: aoss0-crit { 5908 temperature = <110000>; 5909 hysteresis = <0>; 5910 type = "critical"; 5911 }; 5912 }; 5913 }; 5914 5915 aoss1-thermal { 5916 polling-delay-passive = <0>; 5917 polling-delay = <0>; 5918 5919 thermal-sensors = <&tsens1 0>; 5920 5921 trips { 5922 aoss1_alert0: trip-point0 { 5923 temperature = <90000>; 5924 hysteresis = <2000>; 5925 type = "hot"; 5926 }; 5927 5928 aoss1_crit: aoss1-crit { 5929 temperature = <110000>; 5930 hysteresis = <0>; 5931 type = "critical"; 5932 }; 5933 }; 5934 }; 5935 5936 cpuss0-thermal { 5937 polling-delay-passive = <0>; 5938 polling-delay = <0>; 5939 5940 thermal-sensors = <&tsens0 5>; 5941 5942 trips { 5943 cpuss0_alert0: trip-point0 { 5944 temperature = <90000>; 5945 hysteresis = <2000>; 5946 type = "hot"; 5947 }; 5948 cpuss0_crit: cluster0-crit { 5949 temperature = <110000>; 5950 hysteresis = <0>; 5951 type = "critical"; 5952 }; 5953 }; 5954 }; 5955 5956 cpuss1-thermal { 5957 polling-delay-passive = <0>; 5958 polling-delay = <0>; 5959 5960 thermal-sensors = <&tsens0 6>; 5961 5962 trips { 5963 cpuss1_alert0: trip-point0 { 5964 temperature = <90000>; 5965 hysteresis = <2000>; 5966 type = "hot"; 5967 }; 5968 cpuss1_crit: cluster0-crit { 5969 temperature = <110000>; 5970 hysteresis = <0>; 5971 type = "critical"; 5972 }; 5973 }; 5974 }; 5975 5976 gpuss0-thermal { 5977 polling-delay-passive = <100>; 5978 polling-delay = <0>; 5979 5980 thermal-sensors = <&tsens1 1>; 5981 5982 trips { 5983 gpuss0_alert0: trip-point0 { 5984 temperature = <95000>; 5985 hysteresis = <2000>; 5986 type = "passive"; 5987 }; 5988 5989 gpuss0_crit: gpuss0-crit { 5990 temperature = <110000>; 5991 hysteresis = <0>; 5992 type = "critical"; 5993 }; 5994 }; 5995 5996 cooling-maps { 5997 map0 { 5998 trip = <&gpuss0_alert0>; 5999 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6000 }; 6001 }; 6002 }; 6003 6004 gpuss1-thermal { 6005 polling-delay-passive = <100>; 6006 polling-delay = <0>; 6007 6008 thermal-sensors = <&tsens1 2>; 6009 6010 trips { 6011 gpuss1_alert0: trip-point0 { 6012 temperature = <95000>; 6013 hysteresis = <2000>; 6014 type = "passive"; 6015 }; 6016 6017 gpuss1_crit: gpuss1-crit { 6018 temperature = <110000>; 6019 hysteresis = <0>; 6020 type = "critical"; 6021 }; 6022 }; 6023 6024 cooling-maps { 6025 map0 { 6026 trip = <&gpuss1_alert0>; 6027 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6028 }; 6029 }; 6030 }; 6031 6032 nspss0-thermal { 6033 polling-delay-passive = <0>; 6034 polling-delay = <0>; 6035 6036 thermal-sensors = <&tsens1 3>; 6037 6038 trips { 6039 nspss0_alert0: trip-point0 { 6040 temperature = <90000>; 6041 hysteresis = <2000>; 6042 type = "hot"; 6043 }; 6044 6045 nspss0_crit: nspss0-crit { 6046 temperature = <110000>; 6047 hysteresis = <0>; 6048 type = "critical"; 6049 }; 6050 }; 6051 }; 6052 6053 nspss1-thermal { 6054 polling-delay-passive = <0>; 6055 polling-delay = <0>; 6056 6057 thermal-sensors = <&tsens1 4>; 6058 6059 trips { 6060 nspss1_alert0: trip-point0 { 6061 temperature = <90000>; 6062 hysteresis = <2000>; 6063 type = "hot"; 6064 }; 6065 6066 nspss1_crit: nspss1-crit { 6067 temperature = <110000>; 6068 hysteresis = <0>; 6069 type = "critical"; 6070 }; 6071 }; 6072 }; 6073 6074 video-thermal { 6075 polling-delay-passive = <0>; 6076 polling-delay = <0>; 6077 6078 thermal-sensors = <&tsens1 5>; 6079 6080 trips { 6081 video_alert0: trip-point0 { 6082 temperature = <90000>; 6083 hysteresis = <2000>; 6084 type = "hot"; 6085 }; 6086 6087 video_crit: video-crit { 6088 temperature = <110000>; 6089 hysteresis = <0>; 6090 type = "critical"; 6091 }; 6092 }; 6093 }; 6094 6095 ddr-thermal { 6096 polling-delay-passive = <0>; 6097 polling-delay = <0>; 6098 6099 thermal-sensors = <&tsens1 6>; 6100 6101 trips { 6102 ddr_alert0: trip-point0 { 6103 temperature = <90000>; 6104 hysteresis = <2000>; 6105 type = "hot"; 6106 }; 6107 6108 ddr_crit: ddr-crit { 6109 temperature = <110000>; 6110 hysteresis = <0>; 6111 type = "critical"; 6112 }; 6113 }; 6114 }; 6115 6116 mdmss0-thermal { 6117 polling-delay-passive = <0>; 6118 polling-delay = <0>; 6119 6120 thermal-sensors = <&tsens1 7>; 6121 6122 trips { 6123 mdmss0_alert0: trip-point0 { 6124 temperature = <90000>; 6125 hysteresis = <2000>; 6126 type = "hot"; 6127 }; 6128 6129 mdmss0_crit: mdmss0-crit { 6130 temperature = <110000>; 6131 hysteresis = <0>; 6132 type = "critical"; 6133 }; 6134 }; 6135 }; 6136 6137 mdmss1-thermal { 6138 polling-delay-passive = <0>; 6139 polling-delay = <0>; 6140 6141 thermal-sensors = <&tsens1 8>; 6142 6143 trips { 6144 mdmss1_alert0: trip-point0 { 6145 temperature = <90000>; 6146 hysteresis = <2000>; 6147 type = "hot"; 6148 }; 6149 6150 mdmss1_crit: mdmss1-crit { 6151 temperature = <110000>; 6152 hysteresis = <0>; 6153 type = "critical"; 6154 }; 6155 }; 6156 }; 6157 6158 mdmss2-thermal { 6159 polling-delay-passive = <0>; 6160 polling-delay = <0>; 6161 6162 thermal-sensors = <&tsens1 9>; 6163 6164 trips { 6165 mdmss2_alert0: trip-point0 { 6166 temperature = <90000>; 6167 hysteresis = <2000>; 6168 type = "hot"; 6169 }; 6170 6171 mdmss2_crit: mdmss2-crit { 6172 temperature = <110000>; 6173 hysteresis = <0>; 6174 type = "critical"; 6175 }; 6176 }; 6177 }; 6178 6179 mdmss3-thermal { 6180 polling-delay-passive = <0>; 6181 polling-delay = <0>; 6182 6183 thermal-sensors = <&tsens1 10>; 6184 6185 trips { 6186 mdmss3_alert0: trip-point0 { 6187 temperature = <90000>; 6188 hysteresis = <2000>; 6189 type = "hot"; 6190 }; 6191 6192 mdmss3_crit: mdmss3-crit { 6193 temperature = <110000>; 6194 hysteresis = <0>; 6195 type = "critical"; 6196 }; 6197 }; 6198 }; 6199 6200 camera0-thermal { 6201 polling-delay-passive = <0>; 6202 polling-delay = <0>; 6203 6204 thermal-sensors = <&tsens1 11>; 6205 6206 trips { 6207 camera0_alert0: trip-point0 { 6208 temperature = <90000>; 6209 hysteresis = <2000>; 6210 type = "hot"; 6211 }; 6212 6213 camera0_crit: camera0-crit { 6214 temperature = <110000>; 6215 hysteresis = <0>; 6216 type = "critical"; 6217 }; 6218 }; 6219 }; 6220 }; 6221 6222 timer { 6223 compatible = "arm,armv8-timer"; 6224 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6225 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6226 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6227 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6228 }; 6229}; 6230