1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 L3_0: l3-cache { 188 compatible = "cache"; 189 cache-level = <3>; 190 cache-unified; 191 }; 192 }; 193 }; 194 195 CPU1: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x100>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 &LITTLE_CPU_SLEEP_1 226 &CLUSTER_SLEEP_0>; 227 next-level-cache = <&L2_200>; 228 operating-points-v2 = <&cpu0_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 #cooling-cells = <2>; 233 L2_200: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU3: cpu@300 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo"; 244 reg = <0x0 0x300>; 245 clocks = <&cpufreq_hw 0>; 246 enable-method = "psci"; 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 248 &LITTLE_CPU_SLEEP_1 249 &CLUSTER_SLEEP_0>; 250 next-level-cache = <&L2_300>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 254 qcom,freq-domain = <&cpufreq_hw 0>; 255 #cooling-cells = <2>; 256 L2_300: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-unified; 260 next-level-cache = <&L3_0>; 261 }; 262 }; 263 264 CPU4: cpu@400 { 265 device_type = "cpu"; 266 compatible = "qcom,kryo"; 267 reg = <0x0 0x400>; 268 clocks = <&cpufreq_hw 1>; 269 enable-method = "psci"; 270 cpu-idle-states = <&BIG_CPU_SLEEP_0 271 &BIG_CPU_SLEEP_1 272 &CLUSTER_SLEEP_0>; 273 next-level-cache = <&L2_400>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 276 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 L2_400: l2-cache { 280 compatible = "cache"; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo"; 290 reg = <0x0 0x500>; 291 clocks = <&cpufreq_hw 1>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_500>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_500: l2-cache { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-unified; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU6: cpu@600 { 311 device_type = "cpu"; 312 compatible = "qcom,kryo"; 313 reg = <0x0 0x600>; 314 clocks = <&cpufreq_hw 1>; 315 enable-method = "psci"; 316 cpu-idle-states = <&BIG_CPU_SLEEP_0 317 &BIG_CPU_SLEEP_1 318 &CLUSTER_SLEEP_0>; 319 next-level-cache = <&L2_600>; 320 operating-points-v2 = <&cpu4_opp_table>; 321 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 322 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 323 qcom,freq-domain = <&cpufreq_hw 1>; 324 #cooling-cells = <2>; 325 L2_600: l2-cache { 326 compatible = "cache"; 327 cache-level = <2>; 328 cache-unified; 329 next-level-cache = <&L3_0>; 330 }; 331 }; 332 333 CPU7: cpu@700 { 334 device_type = "cpu"; 335 compatible = "qcom,kryo"; 336 reg = <0x0 0x700>; 337 clocks = <&cpufreq_hw 2>; 338 enable-method = "psci"; 339 cpu-idle-states = <&BIG_CPU_SLEEP_0 340 &BIG_CPU_SLEEP_1 341 &CLUSTER_SLEEP_0>; 342 next-level-cache = <&L2_700>; 343 operating-points-v2 = <&cpu7_opp_table>; 344 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 345 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 346 qcom,freq-domain = <&cpufreq_hw 2>; 347 #cooling-cells = <2>; 348 L2_700: l2-cache { 349 compatible = "cache"; 350 cache-level = <2>; 351 cache-unified; 352 next-level-cache = <&L3_0>; 353 }; 354 }; 355 356 cpu-map { 357 cluster0 { 358 core0 { 359 cpu = <&CPU0>; 360 }; 361 362 core1 { 363 cpu = <&CPU1>; 364 }; 365 366 core2 { 367 cpu = <&CPU2>; 368 }; 369 370 core3 { 371 cpu = <&CPU3>; 372 }; 373 374 core4 { 375 cpu = <&CPU4>; 376 }; 377 378 core5 { 379 cpu = <&CPU5>; 380 }; 381 382 core6 { 383 cpu = <&CPU6>; 384 }; 385 386 core7 { 387 cpu = <&CPU7>; 388 }; 389 }; 390 }; 391 392 idle-states { 393 entry-method = "psci"; 394 395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "little-power-down"; 398 arm,psci-suspend-param = <0x40000003>; 399 entry-latency-us = <549>; 400 exit-latency-us = <901>; 401 min-residency-us = <1774>; 402 local-timer-stop; 403 }; 404 405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-down"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <702>; 410 exit-latency-us = <915>; 411 min-residency-us = <4001>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-power-down"; 418 arm,psci-suspend-param = <0x40000003>; 419 entry-latency-us = <523>; 420 exit-latency-us = <1244>; 421 min-residency-us = <2207>; 422 local-timer-stop; 423 }; 424 425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 426 compatible = "arm,idle-state"; 427 idle-state-name = "big-rail-power-down"; 428 arm,psci-suspend-param = <0x40000004>; 429 entry-latency-us = <526>; 430 exit-latency-us = <1854>; 431 min-residency-us = <5555>; 432 local-timer-stop; 433 }; 434 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "cluster-power-down"; 438 arm,psci-suspend-param = <0x40003444>; 439 entry-latency-us = <3263>; 440 exit-latency-us = <6562>; 441 min-residency-us = <9926>; 442 local-timer-stop; 443 }; 444 }; 445 }; 446 447 cpu0_opp_table: opp-table-cpu0 { 448 compatible = "operating-points-v2"; 449 opp-shared; 450 451 cpu0_opp_300mhz: opp-300000000 { 452 opp-hz = /bits/ 64 <300000000>; 453 opp-peak-kBps = <800000 9600000>; 454 }; 455 456 cpu0_opp_691mhz: opp-691200000 { 457 opp-hz = /bits/ 64 <691200000>; 458 opp-peak-kBps = <800000 17817600>; 459 }; 460 461 cpu0_opp_806mhz: opp-806400000 { 462 opp-hz = /bits/ 64 <806400000>; 463 opp-peak-kBps = <800000 20889600>; 464 }; 465 466 cpu0_opp_941mhz: opp-940800000 { 467 opp-hz = /bits/ 64 <940800000>; 468 opp-peak-kBps = <1804000 24576000>; 469 }; 470 471 cpu0_opp_1152mhz: opp-1152000000 { 472 opp-hz = /bits/ 64 <1152000000>; 473 opp-peak-kBps = <2188000 27033600>; 474 }; 475 476 cpu0_opp_1325mhz: opp-1324800000 { 477 opp-hz = /bits/ 64 <1324800000>; 478 opp-peak-kBps = <2188000 33792000>; 479 }; 480 481 cpu0_opp_1517mhz: opp-1516800000 { 482 opp-hz = /bits/ 64 <1516800000>; 483 opp-peak-kBps = <3072000 38092800>; 484 }; 485 486 cpu0_opp_1651mhz: opp-1651200000 { 487 opp-hz = /bits/ 64 <1651200000>; 488 opp-peak-kBps = <3072000 41779200>; 489 }; 490 491 cpu0_opp_1805mhz: opp-1804800000 { 492 opp-hz = /bits/ 64 <1804800000>; 493 opp-peak-kBps = <4068000 48537600>; 494 }; 495 496 cpu0_opp_1958mhz: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <4068000 48537600>; 499 }; 500 501 cpu0_opp_2016mhz: opp-2016000000 { 502 opp-hz = /bits/ 64 <2016000000>; 503 opp-peak-kBps = <6220000 48537600>; 504 }; 505 }; 506 507 cpu4_opp_table: opp-table-cpu4 { 508 compatible = "operating-points-v2"; 509 opp-shared; 510 511 cpu4_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <1804000 9600000>; 514 }; 515 516 cpu4_opp_941mhz: opp-940800000 { 517 opp-hz = /bits/ 64 <940800000>; 518 opp-peak-kBps = <2188000 17817600>; 519 }; 520 521 cpu4_opp_1229mhz: opp-1228800000 { 522 opp-hz = /bits/ 64 <1228800000>; 523 opp-peak-kBps = <4068000 24576000>; 524 }; 525 526 cpu4_opp_1344mhz: opp-1344000000 { 527 opp-hz = /bits/ 64 <1344000000>; 528 opp-peak-kBps = <4068000 24576000>; 529 }; 530 531 cpu4_opp_1517mhz: opp-1516800000 { 532 opp-hz = /bits/ 64 <1516800000>; 533 opp-peak-kBps = <4068000 24576000>; 534 }; 535 536 cpu4_opp_1651mhz: opp-1651200000 { 537 opp-hz = /bits/ 64 <1651200000>; 538 opp-peak-kBps = <6220000 38092800>; 539 }; 540 541 cpu4_opp_1901mhz: opp-1900800000 { 542 opp-hz = /bits/ 64 <1900800000>; 543 opp-peak-kBps = <6220000 44851200>; 544 }; 545 546 cpu4_opp_2054mhz: opp-2054400000 { 547 opp-hz = /bits/ 64 <2054400000>; 548 opp-peak-kBps = <6220000 44851200>; 549 }; 550 551 cpu4_opp_2112mhz: opp-2112000000 { 552 opp-hz = /bits/ 64 <2112000000>; 553 opp-peak-kBps = <6220000 44851200>; 554 }; 555 556 cpu4_opp_2131mhz: opp-2131200000 { 557 opp-hz = /bits/ 64 <2131200000>; 558 opp-peak-kBps = <6220000 44851200>; 559 }; 560 561 cpu4_opp_2208mhz: opp-2208000000 { 562 opp-hz = /bits/ 64 <2208000000>; 563 opp-peak-kBps = <6220000 44851200>; 564 }; 565 566 cpu4_opp_2400mhz: opp-2400000000 { 567 opp-hz = /bits/ 64 <2400000000>; 568 opp-peak-kBps = <8532000 48537600>; 569 }; 570 571 cpu4_opp_2611mhz: opp-2611200000 { 572 opp-hz = /bits/ 64 <2611200000>; 573 opp-peak-kBps = <8532000 48537600>; 574 }; 575 }; 576 577 cpu7_opp_table: opp-table-cpu7 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 cpu7_opp_806mhz: opp-806400000 { 582 opp-hz = /bits/ 64 <806400000>; 583 opp-peak-kBps = <1804000 9600000>; 584 }; 585 586 cpu7_opp_1056mhz: opp-1056000000 { 587 opp-hz = /bits/ 64 <1056000000>; 588 opp-peak-kBps = <2188000 17817600>; 589 }; 590 591 cpu7_opp_1325mhz: opp-1324800000 { 592 opp-hz = /bits/ 64 <1324800000>; 593 opp-peak-kBps = <4068000 24576000>; 594 }; 595 596 cpu7_opp_1517mhz: opp-1516800000 { 597 opp-hz = /bits/ 64 <1516800000>; 598 opp-peak-kBps = <4068000 24576000>; 599 }; 600 601 cpu7_opp_1766mhz: opp-1766400000 { 602 opp-hz = /bits/ 64 <1766400000>; 603 opp-peak-kBps = <6220000 38092800>; 604 }; 605 606 cpu7_opp_1862mhz: opp-1862400000 { 607 opp-hz = /bits/ 64 <1862400000>; 608 opp-peak-kBps = <6220000 38092800>; 609 }; 610 611 cpu7_opp_2035mhz: opp-2035200000 { 612 opp-hz = /bits/ 64 <2035200000>; 613 opp-peak-kBps = <6220000 38092800>; 614 }; 615 616 cpu7_opp_2112mhz: opp-2112000000 { 617 opp-hz = /bits/ 64 <2112000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu7_opp_2208mhz: opp-2208000000 { 622 opp-hz = /bits/ 64 <2208000000>; 623 opp-peak-kBps = <6220000 44851200>; 624 }; 625 626 cpu7_opp_2381mhz: opp-2380800000 { 627 opp-hz = /bits/ 64 <2380800000>; 628 opp-peak-kBps = <6832000 44851200>; 629 }; 630 631 cpu7_opp_2400mhz: opp-2400000000 { 632 opp-hz = /bits/ 64 <2400000000>; 633 opp-peak-kBps = <8532000 48537600>; 634 }; 635 636 cpu7_opp_2515mhz: opp-2515200000 { 637 opp-hz = /bits/ 64 <2515200000>; 638 opp-peak-kBps = <8532000 48537600>; 639 }; 640 641 cpu7_opp_2707mhz: opp-2707200000 { 642 opp-hz = /bits/ 64 <2707200000>; 643 opp-peak-kBps = <8532000 48537600>; 644 }; 645 646 cpu7_opp_3014mhz: opp-3014400000 { 647 opp-hz = /bits/ 64 <3014400000>; 648 opp-peak-kBps = <8532000 48537600>; 649 }; 650 }; 651 652 memory@80000000 { 653 device_type = "memory"; 654 /* We expect the bootloader to fill in the size */ 655 reg = <0 0x80000000 0 0>; 656 }; 657 658 firmware { 659 scm: scm { 660 compatible = "qcom,scm-sc7280", "qcom,scm"; 661 }; 662 }; 663 664 clk_virt: interconnect { 665 compatible = "qcom,sc7280-clk-virt"; 666 #interconnect-cells = <2>; 667 qcom,bcm-voters = <&apps_bcm_voter>; 668 }; 669 670 smem { 671 compatible = "qcom,smem"; 672 memory-region = <&smem_mem>; 673 hwlocks = <&tcsr_mutex 3>; 674 }; 675 676 smp2p-adsp { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 680 IPCC_MPROC_SIGNAL_SMP2P 681 IRQ_TYPE_EDGE_RISING>; 682 mboxes = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <2>; 687 688 adsp_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 adsp_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-cdsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <94>, <432>; 703 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 mboxes = <&ipcc IPCC_CLIENT_CDSP 707 IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-mpss { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <435>, <428>; 727 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 mboxes = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <1>; 735 736 modem_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 modem_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 ipa_smp2p_out: ipa-ap-to-modem { 748 qcom,entry-name = "ipa"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 ipa_smp2p_in: ipa-modem-to-ap { 753 qcom,entry-name = "ipa"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-wpss { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <617>, <616>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_WPSS 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <13>; 770 771 wpss_smp2p_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 wpss_smp2p_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 782 wlan_smp2p_out: wlan-ap-to-wpss { 783 qcom,entry-name = "wlan"; 784 #qcom,smem-state-cells = <1>; 785 }; 786 787 wlan_smp2p_in: wlan-wpss-to-ap { 788 qcom,entry-name = "wlan"; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 }; 792 }; 793 794 pmu { 795 compatible = "arm,armv8-pmuv3"; 796 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 797 }; 798 799 psci { 800 compatible = "arm,psci-1.0"; 801 method = "smc"; 802 }; 803 804 qspi_opp_table: opp-table-qspi { 805 compatible = "operating-points-v2"; 806 807 opp-75000000 { 808 opp-hz = /bits/ 64 <75000000>; 809 required-opps = <&rpmhpd_opp_low_svs>; 810 }; 811 812 opp-150000000 { 813 opp-hz = /bits/ 64 <150000000>; 814 required-opps = <&rpmhpd_opp_svs>; 815 }; 816 817 opp-200000000 { 818 opp-hz = /bits/ 64 <200000000>; 819 required-opps = <&rpmhpd_opp_svs_l1>; 820 }; 821 822 opp-300000000 { 823 opp-hz = /bits/ 64 <300000000>; 824 required-opps = <&rpmhpd_opp_nom>; 825 }; 826 }; 827 828 qup_opp_table: opp-table-qup { 829 compatible = "operating-points-v2"; 830 831 opp-75000000 { 832 opp-hz = /bits/ 64 <75000000>; 833 required-opps = <&rpmhpd_opp_low_svs>; 834 }; 835 836 opp-100000000 { 837 opp-hz = /bits/ 64 <100000000>; 838 required-opps = <&rpmhpd_opp_svs>; 839 }; 840 841 opp-128000000 { 842 opp-hz = /bits/ 64 <128000000>; 843 required-opps = <&rpmhpd_opp_nom>; 844 }; 845 }; 846 847 soc: soc@0 { 848 #address-cells = <2>; 849 #size-cells = <2>; 850 ranges = <0 0 0 0 0x10 0>; 851 dma-ranges = <0 0 0 0 0x10 0>; 852 compatible = "simple-bus"; 853 854 gcc: clock-controller@100000 { 855 compatible = "qcom,gcc-sc7280"; 856 reg = <0 0x00100000 0 0x1f0000>; 857 clocks = <&rpmhcc RPMH_CXO_CLK>, 858 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 859 <0>, <&pcie1_lane>, 860 <0>, <0>, <0>, 861 <&usb_1_ssphy>; 862 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 863 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 864 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 865 "ufs_phy_tx_symbol_0_clk", 866 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 #power-domain-cells = <1>; 870 power-domains = <&rpmhpd SC7280_CX>; 871 }; 872 873 ipcc: mailbox@408000 { 874 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 875 reg = <0 0x00408000 0 0x1000>; 876 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-controller; 878 #interrupt-cells = <3>; 879 #mbox-cells = <2>; 880 }; 881 882 qfprom: efuse@784000 { 883 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 884 reg = <0 0x00784000 0 0xa20>, 885 <0 0x00780000 0 0xa20>, 886 <0 0x00782000 0 0x120>, 887 <0 0x00786000 0 0x1fff>; 888 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 889 clock-names = "core"; 890 power-domains = <&rpmhpd SC7280_MX>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 894 gpu_speed_bin: gpu_speed_bin@1e9 { 895 reg = <0x1e9 0x2>; 896 bits = <5 8>; 897 }; 898 }; 899 900 sdhc_1: mmc@7c4000 { 901 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 902 pinctrl-names = "default", "sleep"; 903 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 904 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 905 status = "disabled"; 906 907 reg = <0 0x007c4000 0 0x1000>, 908 <0 0x007c5000 0 0x1000>; 909 reg-names = "hc", "cqhci"; 910 911 iommus = <&apps_smmu 0xc0 0x0>; 912 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "hc_irq", "pwr_irq"; 915 916 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 917 <&gcc GCC_SDCC1_APPS_CLK>, 918 <&rpmhcc RPMH_CXO_CLK>; 919 clock-names = "iface", "core", "xo"; 920 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 922 interconnect-names = "sdhc-ddr","cpu-sdhc"; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&sdhc1_opp_table>; 925 926 bus-width = <8>; 927 supports-cqe; 928 dma-coherent; 929 930 qcom,dll-config = <0x0007642c>; 931 qcom,ddr-config = <0x80040868>; 932 933 mmc-ddr-1_8v; 934 mmc-hs200-1_8v; 935 mmc-hs400-1_8v; 936 mmc-hs400-enhanced-strobe; 937 938 resets = <&gcc GCC_SDCC1_BCR>; 939 940 sdhc1_opp_table: opp-table { 941 compatible = "operating-points-v2"; 942 943 opp-100000000 { 944 opp-hz = /bits/ 64 <100000000>; 945 required-opps = <&rpmhpd_opp_low_svs>; 946 opp-peak-kBps = <1800000 400000>; 947 opp-avg-kBps = <100000 0>; 948 }; 949 950 opp-384000000 { 951 opp-hz = /bits/ 64 <384000000>; 952 required-opps = <&rpmhpd_opp_nom>; 953 opp-peak-kBps = <5400000 1600000>; 954 opp-avg-kBps = <390000 0>; 955 }; 956 }; 957 }; 958 959 gpi_dma0: dma-controller@900000 { 960 #dma-cells = <3>; 961 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 962 reg = <0 0x00900000 0 0x60000>; 963 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 975 dma-channels = <12>; 976 dma-channel-mask = <0x7f>; 977 iommus = <&apps_smmu 0x0136 0x0>; 978 status = "disabled"; 979 }; 980 981 qupv3_id_0: geniqup@9c0000 { 982 compatible = "qcom,geni-se-qup"; 983 reg = <0 0x009c0000 0 0x2000>; 984 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 985 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 986 clock-names = "m-ahb", "s-ahb"; 987 #address-cells = <2>; 988 #size-cells = <2>; 989 ranges; 990 iommus = <&apps_smmu 0x123 0x0>; 991 status = "disabled"; 992 993 i2c0: i2c@980000 { 994 compatible = "qcom,geni-i2c"; 995 reg = <0 0x00980000 0 0x4000>; 996 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 997 clock-names = "se"; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_i2c0_data_clk>; 1000 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1005 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", 1007 "qup-memory"; 1008 power-domains = <&rpmhpd SC7280_CX>; 1009 required-opps = <&rpmhpd_opp_low_svs>; 1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1011 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1012 dma-names = "tx", "rx"; 1013 status = "disabled"; 1014 }; 1015 1016 spi0: spi@980000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00980000 0 0x4000>; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1020 clock-names = "se"; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1023 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 power-domains = <&rpmhpd SC7280_CX>; 1027 operating-points-v2 = <&qup_opp_table>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1029 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1030 interconnect-names = "qup-core", "qup-config"; 1031 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1032 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1033 dma-names = "tx", "rx"; 1034 status = "disabled"; 1035 }; 1036 1037 uart0: serial@980000 { 1038 compatible = "qcom,geni-uart"; 1039 reg = <0 0x00980000 0 0x4000>; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1041 clock-names = "se"; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1044 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1045 power-domains = <&rpmhpd SC7280_CX>; 1046 operating-points-v2 = <&qup_opp_table>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1048 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1049 interconnect-names = "qup-core", "qup-config"; 1050 status = "disabled"; 1051 }; 1052 1053 i2c1: i2c@984000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0 0x00984000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_i2c1_data_clk>; 1060 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1065 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1066 interconnect-names = "qup-core", "qup-config", 1067 "qup-memory"; 1068 power-domains = <&rpmhpd SC7280_CX>; 1069 required-opps = <&rpmhpd_opp_low_svs>; 1070 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1071 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 status = "disabled"; 1074 }; 1075 1076 spi1: spi@984000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00984000 0 0x4000>; 1079 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1080 clock-names = "se"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1083 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 power-domains = <&rpmhpd SC7280_CX>; 1087 operating-points-v2 = <&qup_opp_table>; 1088 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1089 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1090 interconnect-names = "qup-core", "qup-config"; 1091 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1092 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1093 dma-names = "tx", "rx"; 1094 status = "disabled"; 1095 }; 1096 1097 uart1: serial@984000 { 1098 compatible = "qcom,geni-uart"; 1099 reg = <0 0x00984000 0 0x4000>; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1101 clock-names = "se"; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1104 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1105 power-domains = <&rpmhpd SC7280_CX>; 1106 operating-points-v2 = <&qup_opp_table>; 1107 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1108 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1109 interconnect-names = "qup-core", "qup-config"; 1110 status = "disabled"; 1111 }; 1112 1113 i2c2: i2c@988000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00988000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1117 clock-names = "se"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_i2c2_data_clk>; 1120 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1125 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1126 interconnect-names = "qup-core", "qup-config", 1127 "qup-memory"; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 required-opps = <&rpmhpd_opp_low_svs>; 1130 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1131 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1132 dma-names = "tx", "rx"; 1133 status = "disabled"; 1134 }; 1135 1136 spi2: spi@988000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00988000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1143 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 power-domains = <&rpmhpd SC7280_CX>; 1147 operating-points-v2 = <&qup_opp_table>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1152 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 status = "disabled"; 1155 }; 1156 1157 uart2: serial@988000 { 1158 compatible = "qcom,geni-uart"; 1159 reg = <0 0x00988000 0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1161 clock-names = "se"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1164 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1165 power-domains = <&rpmhpd SC7280_CX>; 1166 operating-points-v2 = <&qup_opp_table>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1169 interconnect-names = "qup-core", "qup-config"; 1170 status = "disabled"; 1171 }; 1172 1173 i2c3: i2c@98c000 { 1174 compatible = "qcom,geni-i2c"; 1175 reg = <0 0x0098c000 0 0x4000>; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1177 clock-names = "se"; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&qup_i2c3_data_clk>; 1180 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1184 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1185 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1186 interconnect-names = "qup-core", "qup-config", 1187 "qup-memory"; 1188 power-domains = <&rpmhpd SC7280_CX>; 1189 required-opps = <&rpmhpd_opp_low_svs>; 1190 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1191 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1192 dma-names = "tx", "rx"; 1193 status = "disabled"; 1194 }; 1195 1196 spi3: spi@98c000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x0098c000 0 0x4000>; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1200 clock-names = "se"; 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1203 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 power-domains = <&rpmhpd SC7280_CX>; 1207 operating-points-v2 = <&qup_opp_table>; 1208 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1209 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1210 interconnect-names = "qup-core", "qup-config"; 1211 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1212 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 status = "disabled"; 1215 }; 1216 1217 uart3: serial@98c000 { 1218 compatible = "qcom,geni-uart"; 1219 reg = <0 0x0098c000 0 0x4000>; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1221 clock-names = "se"; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1224 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC7280_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c4: i2c@990000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00990000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_i2c4_data_clk>; 1240 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1245 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1246 interconnect-names = "qup-core", "qup-config", 1247 "qup-memory"; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 required-opps = <&rpmhpd_opp_low_svs>; 1250 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1251 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1252 dma-names = "tx", "rx"; 1253 status = "disabled"; 1254 }; 1255 1256 spi4: spi@990000 { 1257 compatible = "qcom,geni-spi"; 1258 reg = <0 0x00990000 0 0x4000>; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1260 clock-names = "se"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1263 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 power-domains = <&rpmhpd SC7280_CX>; 1267 operating-points-v2 = <&qup_opp_table>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1272 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1273 dma-names = "tx", "rx"; 1274 status = "disabled"; 1275 }; 1276 1277 uart4: serial@990000 { 1278 compatible = "qcom,geni-uart"; 1279 reg = <0 0x00990000 0 0x4000>; 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1281 clock-names = "se"; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1284 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1285 power-domains = <&rpmhpd SC7280_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1288 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1289 interconnect-names = "qup-core", "qup-config"; 1290 status = "disabled"; 1291 }; 1292 1293 i2c5: i2c@994000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x00994000 0 0x4000>; 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1297 clock-names = "se"; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&qup_i2c5_data_clk>; 1300 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1304 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1305 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1306 interconnect-names = "qup-core", "qup-config", 1307 "qup-memory"; 1308 power-domains = <&rpmhpd SC7280_CX>; 1309 required-opps = <&rpmhpd_opp_low_svs>; 1310 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1311 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 spi5: spi@994000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x00994000 0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1320 clock-names = "se"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1323 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 power-domains = <&rpmhpd SC7280_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1329 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1332 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1333 dma-names = "tx", "rx"; 1334 status = "disabled"; 1335 }; 1336 1337 uart5: serial@994000 { 1338 compatible = "qcom,geni-uart"; 1339 reg = <0 0x00994000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1341 clock-names = "se"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC7280_CX>; 1346 operating-points-v2 = <&qup_opp_table>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1349 interconnect-names = "qup-core", "qup-config"; 1350 status = "disabled"; 1351 }; 1352 1353 i2c6: i2c@998000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0 0x00998000 0 0x4000>; 1356 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1357 clock-names = "se"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_i2c6_data_clk>; 1360 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1364 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1366 interconnect-names = "qup-core", "qup-config", 1367 "qup-memory"; 1368 power-domains = <&rpmhpd SC7280_CX>; 1369 required-opps = <&rpmhpd_opp_low_svs>; 1370 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 status = "disabled"; 1374 }; 1375 1376 spi6: spi@998000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x00998000 0 0x4000>; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1380 clock-names = "se"; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1383 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 power-domains = <&rpmhpd SC7280_CX>; 1387 operating-points-v2 = <&qup_opp_table>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1390 interconnect-names = "qup-core", "qup-config"; 1391 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1392 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 status = "disabled"; 1395 }; 1396 1397 uart6: serial@998000 { 1398 compatible = "qcom,geni-uart"; 1399 reg = <0 0x00998000 0 0x4000>; 1400 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1401 clock-names = "se"; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1404 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1405 power-domains = <&rpmhpd SC7280_CX>; 1406 operating-points-v2 = <&qup_opp_table>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1408 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1409 interconnect-names = "qup-core", "qup-config"; 1410 status = "disabled"; 1411 }; 1412 1413 i2c7: i2c@99c000 { 1414 compatible = "qcom,geni-i2c"; 1415 reg = <0 0x0099c000 0 0x4000>; 1416 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1417 clock-names = "se"; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_i2c7_data_clk>; 1420 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1424 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1425 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1426 interconnect-names = "qup-core", "qup-config", 1427 "qup-memory"; 1428 power-domains = <&rpmhpd SC7280_CX>; 1429 required-opps = <&rpmhpd_opp_low_svs>; 1430 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1431 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1432 dma-names = "tx", "rx"; 1433 status = "disabled"; 1434 }; 1435 1436 spi7: spi@99c000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x0099c000 0 0x4000>; 1439 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1440 clock-names = "se"; 1441 pinctrl-names = "default"; 1442 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1443 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 power-domains = <&rpmhpd SC7280_CX>; 1447 operating-points-v2 = <&qup_opp_table>; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1449 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1450 interconnect-names = "qup-core", "qup-config"; 1451 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1452 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1453 dma-names = "tx", "rx"; 1454 status = "disabled"; 1455 }; 1456 1457 uart7: serial@99c000 { 1458 compatible = "qcom,geni-uart"; 1459 reg = <0 0x0099c000 0 0x4000>; 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1461 clock-names = "se"; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1464 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1465 power-domains = <&rpmhpd SC7280_CX>; 1466 operating-points-v2 = <&qup_opp_table>; 1467 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1468 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1469 interconnect-names = "qup-core", "qup-config"; 1470 status = "disabled"; 1471 }; 1472 }; 1473 1474 gpi_dma1: dma-controller@a00000 { 1475 #dma-cells = <3>; 1476 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1477 reg = <0 0x00a00000 0 0x60000>; 1478 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1490 dma-channels = <12>; 1491 dma-channel-mask = <0x1e>; 1492 iommus = <&apps_smmu 0x56 0x0>; 1493 status = "disabled"; 1494 }; 1495 1496 qupv3_id_1: geniqup@ac0000 { 1497 compatible = "qcom,geni-se-qup"; 1498 reg = <0 0x00ac0000 0 0x2000>; 1499 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1500 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1501 clock-names = "m-ahb", "s-ahb"; 1502 #address-cells = <2>; 1503 #size-cells = <2>; 1504 ranges; 1505 iommus = <&apps_smmu 0x43 0x0>; 1506 status = "disabled"; 1507 1508 i2c8: i2c@a80000 { 1509 compatible = "qcom,geni-i2c"; 1510 reg = <0 0x00a80000 0 0x4000>; 1511 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1512 clock-names = "se"; 1513 pinctrl-names = "default"; 1514 pinctrl-0 = <&qup_i2c8_data_clk>; 1515 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1519 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1520 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1521 interconnect-names = "qup-core", "qup-config", 1522 "qup-memory"; 1523 power-domains = <&rpmhpd SC7280_CX>; 1524 required-opps = <&rpmhpd_opp_low_svs>; 1525 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1526 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1527 dma-names = "tx", "rx"; 1528 status = "disabled"; 1529 }; 1530 1531 spi8: spi@a80000 { 1532 compatible = "qcom,geni-spi"; 1533 reg = <0 0x00a80000 0 0x4000>; 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1535 clock-names = "se"; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1538 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 power-domains = <&rpmhpd SC7280_CX>; 1542 operating-points-v2 = <&qup_opp_table>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1545 interconnect-names = "qup-core", "qup-config"; 1546 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1547 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1548 dma-names = "tx", "rx"; 1549 status = "disabled"; 1550 }; 1551 1552 uart8: serial@a80000 { 1553 compatible = "qcom,geni-uart"; 1554 reg = <0 0x00a80000 0 0x4000>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1556 clock-names = "se"; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1559 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1560 power-domains = <&rpmhpd SC7280_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1564 interconnect-names = "qup-core", "qup-config"; 1565 status = "disabled"; 1566 }; 1567 1568 i2c9: i2c@a84000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00a84000 0 0x4000>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1572 clock-names = "se"; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c9_data_clk>; 1575 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1579 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1580 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", 1582 "qup-memory"; 1583 power-domains = <&rpmhpd SC7280_CX>; 1584 required-opps = <&rpmhpd_opp_low_svs>; 1585 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1586 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1587 dma-names = "tx", "rx"; 1588 status = "disabled"; 1589 }; 1590 1591 spi9: spi@a84000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a84000 0 0x4000>; 1594 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1595 clock-names = "se"; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1598 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 power-domains = <&rpmhpd SC7280_CX>; 1602 operating-points-v2 = <&qup_opp_table>; 1603 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1604 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1605 interconnect-names = "qup-core", "qup-config"; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 uart9: serial@a84000 { 1613 compatible = "qcom,geni-uart"; 1614 reg = <0 0x00a84000 0 0x4000>; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1616 clock-names = "se"; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1620 power-domains = <&rpmhpd SC7280_CX>; 1621 operating-points-v2 = <&qup_opp_table>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1624 interconnect-names = "qup-core", "qup-config"; 1625 status = "disabled"; 1626 }; 1627 1628 i2c10: i2c@a88000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00a88000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1632 clock-names = "se"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c10_data_clk>; 1635 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1639 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1640 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "qup-core", "qup-config", 1642 "qup-memory"; 1643 power-domains = <&rpmhpd SC7280_CX>; 1644 required-opps = <&rpmhpd_opp_low_svs>; 1645 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1646 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1647 dma-names = "tx", "rx"; 1648 status = "disabled"; 1649 }; 1650 1651 spi10: spi@a88000 { 1652 compatible = "qcom,geni-spi"; 1653 reg = <0 0x00a88000 0 0x4000>; 1654 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1655 clock-names = "se"; 1656 pinctrl-names = "default"; 1657 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1658 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 power-domains = <&rpmhpd SC7280_CX>; 1662 operating-points-v2 = <&qup_opp_table>; 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1664 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1665 interconnect-names = "qup-core", "qup-config"; 1666 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1667 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1668 dma-names = "tx", "rx"; 1669 status = "disabled"; 1670 }; 1671 1672 uart10: serial@a88000 { 1673 compatible = "qcom,geni-uart"; 1674 reg = <0 0x00a88000 0 0x4000>; 1675 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1676 clock-names = "se"; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1679 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1680 power-domains = <&rpmhpd SC7280_CX>; 1681 operating-points-v2 = <&qup_opp_table>; 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1683 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1684 interconnect-names = "qup-core", "qup-config"; 1685 status = "disabled"; 1686 }; 1687 1688 i2c11: i2c@a8c000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0 0x00a8c000 0 0x4000>; 1691 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1692 clock-names = "se"; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_i2c11_data_clk>; 1695 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1699 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1700 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1701 interconnect-names = "qup-core", "qup-config", 1702 "qup-memory"; 1703 power-domains = <&rpmhpd SC7280_CX>; 1704 required-opps = <&rpmhpd_opp_low_svs>; 1705 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1706 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1707 dma-names = "tx", "rx"; 1708 status = "disabled"; 1709 }; 1710 1711 spi11: spi@a8c000 { 1712 compatible = "qcom,geni-spi"; 1713 reg = <0 0x00a8c000 0 0x4000>; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1715 clock-names = "se"; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1718 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 power-domains = <&rpmhpd SC7280_CX>; 1722 operating-points-v2 = <&qup_opp_table>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1724 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1725 interconnect-names = "qup-core", "qup-config"; 1726 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1727 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1728 dma-names = "tx", "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 uart11: serial@a8c000 { 1733 compatible = "qcom,geni-uart"; 1734 reg = <0 0x00a8c000 0 0x4000>; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1736 clock-names = "se"; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1739 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1740 power-domains = <&rpmhpd SC7280_CX>; 1741 operating-points-v2 = <&qup_opp_table>; 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1743 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1744 interconnect-names = "qup-core", "qup-config"; 1745 status = "disabled"; 1746 }; 1747 1748 i2c12: i2c@a90000 { 1749 compatible = "qcom,geni-i2c"; 1750 reg = <0 0x00a90000 0 0x4000>; 1751 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1752 clock-names = "se"; 1753 pinctrl-names = "default"; 1754 pinctrl-0 = <&qup_i2c12_data_clk>; 1755 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1760 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1761 interconnect-names = "qup-core", "qup-config", 1762 "qup-memory"; 1763 power-domains = <&rpmhpd SC7280_CX>; 1764 required-opps = <&rpmhpd_opp_low_svs>; 1765 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1766 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1767 dma-names = "tx", "rx"; 1768 status = "disabled"; 1769 }; 1770 1771 spi12: spi@a90000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0 0x00a90000 0 0x4000>; 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1775 clock-names = "se"; 1776 pinctrl-names = "default"; 1777 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1778 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 power-domains = <&rpmhpd SC7280_CX>; 1782 operating-points-v2 = <&qup_opp_table>; 1783 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1784 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1785 interconnect-names = "qup-core", "qup-config"; 1786 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1787 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1788 dma-names = "tx", "rx"; 1789 status = "disabled"; 1790 }; 1791 1792 uart12: serial@a90000 { 1793 compatible = "qcom,geni-uart"; 1794 reg = <0 0x00a90000 0 0x4000>; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1796 clock-names = "se"; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1799 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1800 power-domains = <&rpmhpd SC7280_CX>; 1801 operating-points-v2 = <&qup_opp_table>; 1802 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1803 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1804 interconnect-names = "qup-core", "qup-config"; 1805 status = "disabled"; 1806 }; 1807 1808 i2c13: i2c@a94000 { 1809 compatible = "qcom,geni-i2c"; 1810 reg = <0 0x00a94000 0 0x4000>; 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1812 clock-names = "se"; 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&qup_i2c13_data_clk>; 1815 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1819 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1820 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1821 interconnect-names = "qup-core", "qup-config", 1822 "qup-memory"; 1823 power-domains = <&rpmhpd SC7280_CX>; 1824 required-opps = <&rpmhpd_opp_low_svs>; 1825 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1827 dma-names = "tx", "rx"; 1828 status = "disabled"; 1829 }; 1830 1831 spi13: spi@a94000 { 1832 compatible = "qcom,geni-spi"; 1833 reg = <0 0x00a94000 0 0x4000>; 1834 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1835 clock-names = "se"; 1836 pinctrl-names = "default"; 1837 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1838 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 power-domains = <&rpmhpd SC7280_CX>; 1842 operating-points-v2 = <&qup_opp_table>; 1843 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1844 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1845 interconnect-names = "qup-core", "qup-config"; 1846 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1847 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1848 dma-names = "tx", "rx"; 1849 status = "disabled"; 1850 }; 1851 1852 uart13: serial@a94000 { 1853 compatible = "qcom,geni-uart"; 1854 reg = <0 0x00a94000 0 0x4000>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1856 clock-names = "se"; 1857 pinctrl-names = "default"; 1858 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1859 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1860 power-domains = <&rpmhpd SC7280_CX>; 1861 operating-points-v2 = <&qup_opp_table>; 1862 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1863 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1864 interconnect-names = "qup-core", "qup-config"; 1865 status = "disabled"; 1866 }; 1867 1868 i2c14: i2c@a98000 { 1869 compatible = "qcom,geni-i2c"; 1870 reg = <0 0x00a98000 0 0x4000>; 1871 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1872 clock-names = "se"; 1873 pinctrl-names = "default"; 1874 pinctrl-0 = <&qup_i2c14_data_clk>; 1875 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1879 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1880 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1881 interconnect-names = "qup-core", "qup-config", 1882 "qup-memory"; 1883 power-domains = <&rpmhpd SC7280_CX>; 1884 required-opps = <&rpmhpd_opp_low_svs>; 1885 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1886 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1887 dma-names = "tx", "rx"; 1888 status = "disabled"; 1889 }; 1890 1891 spi14: spi@a98000 { 1892 compatible = "qcom,geni-spi"; 1893 reg = <0 0x00a98000 0 0x4000>; 1894 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1895 clock-names = "se"; 1896 pinctrl-names = "default"; 1897 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1898 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 power-domains = <&rpmhpd SC7280_CX>; 1902 operating-points-v2 = <&qup_opp_table>; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1904 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1905 interconnect-names = "qup-core", "qup-config"; 1906 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1907 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1908 dma-names = "tx", "rx"; 1909 status = "disabled"; 1910 }; 1911 1912 uart14: serial@a98000 { 1913 compatible = "qcom,geni-uart"; 1914 reg = <0 0x00a98000 0 0x4000>; 1915 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1916 clock-names = "se"; 1917 pinctrl-names = "default"; 1918 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1919 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1920 power-domains = <&rpmhpd SC7280_CX>; 1921 operating-points-v2 = <&qup_opp_table>; 1922 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1923 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1924 interconnect-names = "qup-core", "qup-config"; 1925 status = "disabled"; 1926 }; 1927 1928 i2c15: i2c@a9c000 { 1929 compatible = "qcom,geni-i2c"; 1930 reg = <0 0x00a9c000 0 0x4000>; 1931 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1932 clock-names = "se"; 1933 pinctrl-names = "default"; 1934 pinctrl-0 = <&qup_i2c15_data_clk>; 1935 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1936 #address-cells = <1>; 1937 #size-cells = <0>; 1938 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1939 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1940 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1941 interconnect-names = "qup-core", "qup-config", 1942 "qup-memory"; 1943 power-domains = <&rpmhpd SC7280_CX>; 1944 required-opps = <&rpmhpd_opp_low_svs>; 1945 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1946 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1947 dma-names = "tx", "rx"; 1948 status = "disabled"; 1949 }; 1950 1951 spi15: spi@a9c000 { 1952 compatible = "qcom,geni-spi"; 1953 reg = <0 0x00a9c000 0 0x4000>; 1954 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1955 clock-names = "se"; 1956 pinctrl-names = "default"; 1957 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1958 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 power-domains = <&rpmhpd SC7280_CX>; 1962 operating-points-v2 = <&qup_opp_table>; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1964 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1965 interconnect-names = "qup-core", "qup-config"; 1966 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1967 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1968 dma-names = "tx", "rx"; 1969 status = "disabled"; 1970 }; 1971 1972 uart15: serial@a9c000 { 1973 compatible = "qcom,geni-uart"; 1974 reg = <0 0x00a9c000 0 0x4000>; 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1976 clock-names = "se"; 1977 pinctrl-names = "default"; 1978 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1979 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1980 power-domains = <&rpmhpd SC7280_CX>; 1981 operating-points-v2 = <&qup_opp_table>; 1982 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1983 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1984 interconnect-names = "qup-core", "qup-config"; 1985 status = "disabled"; 1986 }; 1987 }; 1988 1989 cnoc2: interconnect@1500000 { 1990 reg = <0 0x01500000 0 0x1000>; 1991 compatible = "qcom,sc7280-cnoc2"; 1992 #interconnect-cells = <2>; 1993 qcom,bcm-voters = <&apps_bcm_voter>; 1994 }; 1995 1996 cnoc3: interconnect@1502000 { 1997 reg = <0 0x01502000 0 0x1000>; 1998 compatible = "qcom,sc7280-cnoc3"; 1999 #interconnect-cells = <2>; 2000 qcom,bcm-voters = <&apps_bcm_voter>; 2001 }; 2002 2003 mc_virt: interconnect@1580000 { 2004 reg = <0 0x01580000 0 0x4>; 2005 compatible = "qcom,sc7280-mc-virt"; 2006 #interconnect-cells = <2>; 2007 qcom,bcm-voters = <&apps_bcm_voter>; 2008 }; 2009 2010 system_noc: interconnect@1680000 { 2011 reg = <0 0x01680000 0 0x15480>; 2012 compatible = "qcom,sc7280-system-noc"; 2013 #interconnect-cells = <2>; 2014 qcom,bcm-voters = <&apps_bcm_voter>; 2015 }; 2016 2017 aggre1_noc: interconnect@16e0000 { 2018 compatible = "qcom,sc7280-aggre1-noc"; 2019 reg = <0 0x016e0000 0 0x1c080>; 2020 #interconnect-cells = <2>; 2021 qcom,bcm-voters = <&apps_bcm_voter>; 2022 }; 2023 2024 aggre2_noc: interconnect@1700000 { 2025 reg = <0 0x01700000 0 0x2b080>; 2026 compatible = "qcom,sc7280-aggre2-noc"; 2027 #interconnect-cells = <2>; 2028 qcom,bcm-voters = <&apps_bcm_voter>; 2029 }; 2030 2031 mmss_noc: interconnect@1740000 { 2032 reg = <0 0x01740000 0 0x1e080>; 2033 compatible = "qcom,sc7280-mmss-noc"; 2034 #interconnect-cells = <2>; 2035 qcom,bcm-voters = <&apps_bcm_voter>; 2036 }; 2037 2038 wifi: wifi@17a10040 { 2039 compatible = "qcom,wcn6750-wifi"; 2040 reg = <0 0x17a10040 0 0x0>; 2041 iommus = <&apps_smmu 0x1c00 0x1>; 2042 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2073 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2074 qcom,rproc = <&remoteproc_wpss>; 2075 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2076 status = "disabled"; 2077 qcom,smem-states = <&wlan_smp2p_out 0>; 2078 qcom,smem-state-names = "wlan-smp2p-out"; 2079 }; 2080 2081 pcie1: pci@1c08000 { 2082 compatible = "qcom,pcie-sc7280"; 2083 reg = <0 0x01c08000 0 0x3000>, 2084 <0 0x40000000 0 0xf1d>, 2085 <0 0x40000f20 0 0xa8>, 2086 <0 0x40001000 0 0x1000>, 2087 <0 0x40100000 0 0x100000>; 2088 2089 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2090 device_type = "pci"; 2091 linux,pci-domain = <1>; 2092 bus-range = <0x00 0xff>; 2093 num-lanes = <2>; 2094 2095 #address-cells = <3>; 2096 #size-cells = <2>; 2097 2098 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2099 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2100 2101 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2102 interrupt-names = "msi"; 2103 #interrupt-cells = <1>; 2104 interrupt-map-mask = <0 0 0 0x7>; 2105 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2106 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2107 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2108 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2109 2110 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2111 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2112 <&pcie1_lane>, 2113 <&rpmhcc RPMH_CXO_CLK>, 2114 <&gcc GCC_PCIE_1_AUX_CLK>, 2115 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2116 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2117 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2118 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2119 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2120 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2121 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2122 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2123 2124 clock-names = "pipe", 2125 "pipe_mux", 2126 "phy_pipe", 2127 "ref", 2128 "aux", 2129 "cfg", 2130 "bus_master", 2131 "bus_slave", 2132 "slave_q2a", 2133 "tbu", 2134 "ddrss_sf_tbu", 2135 "aggre0", 2136 "aggre1"; 2137 2138 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2139 assigned-clock-rates = <19200000>; 2140 2141 resets = <&gcc GCC_PCIE_1_BCR>; 2142 reset-names = "pci"; 2143 2144 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2145 2146 phys = <&pcie1_lane>; 2147 phy-names = "pciephy"; 2148 2149 pinctrl-names = "default"; 2150 pinctrl-0 = <&pcie1_clkreq_n>; 2151 2152 dma-coherent; 2153 2154 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2155 <0x100 &apps_smmu 0x1c81 0x1>; 2156 2157 status = "disabled"; 2158 }; 2159 2160 pcie1_phy: phy@1c0e000 { 2161 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2162 reg = <0 0x01c0e000 0 0x1c0>; 2163 #address-cells = <2>; 2164 #size-cells = <2>; 2165 ranges; 2166 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2167 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2168 <&gcc GCC_PCIE_CLKREF_EN>, 2169 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2170 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2171 2172 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2173 reset-names = "phy"; 2174 2175 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2176 assigned-clock-rates = <100000000>; 2177 2178 status = "disabled"; 2179 2180 pcie1_lane: phy@1c0e200 { 2181 reg = <0 0x01c0e200 0 0x170>, 2182 <0 0x01c0e400 0 0x200>, 2183 <0 0x01c0ea00 0 0x1f0>, 2184 <0 0x01c0e600 0 0x170>, 2185 <0 0x01c0e800 0 0x200>, 2186 <0 0x01c0ee00 0 0xf4>; 2187 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2188 clock-names = "pipe0"; 2189 2190 #phy-cells = <0>; 2191 #clock-cells = <0>; 2192 clock-output-names = "pcie_1_pipe_clk"; 2193 }; 2194 }; 2195 2196 ipa: ipa@1e40000 { 2197 compatible = "qcom,sc7280-ipa"; 2198 2199 iommus = <&apps_smmu 0x480 0x0>, 2200 <&apps_smmu 0x482 0x0>; 2201 reg = <0 0x01e40000 0 0x8000>, 2202 <0 0x01e50000 0 0x4ad0>, 2203 <0 0x01e04000 0 0x23000>; 2204 reg-names = "ipa-reg", 2205 "ipa-shared", 2206 "gsi"; 2207 2208 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2209 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2210 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2211 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2212 interrupt-names = "ipa", 2213 "gsi", 2214 "ipa-clock-query", 2215 "ipa-setup-ready"; 2216 2217 clocks = <&rpmhcc RPMH_IPA_CLK>; 2218 clock-names = "core"; 2219 2220 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2221 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2222 interconnect-names = "memory", 2223 "config"; 2224 2225 qcom,qmp = <&aoss_qmp>; 2226 2227 qcom,smem-states = <&ipa_smp2p_out 0>, 2228 <&ipa_smp2p_out 1>; 2229 qcom,smem-state-names = "ipa-clock-enabled-valid", 2230 "ipa-clock-enabled"; 2231 2232 status = "disabled"; 2233 }; 2234 2235 tcsr_mutex: hwlock@1f40000 { 2236 compatible = "qcom,tcsr-mutex"; 2237 reg = <0 0x01f40000 0 0x20000>; 2238 #hwlock-cells = <1>; 2239 }; 2240 2241 tcsr_1: syscon@1f60000 { 2242 compatible = "qcom,sc7280-tcsr", "syscon"; 2243 reg = <0 0x01f60000 0 0x20000>; 2244 }; 2245 2246 tcsr_2: syscon@1fc0000 { 2247 compatible = "qcom,sc7280-tcsr", "syscon"; 2248 reg = <0 0x01fc0000 0 0x30000>; 2249 }; 2250 2251 lpasscc: lpasscc@3000000 { 2252 compatible = "qcom,sc7280-lpasscc"; 2253 reg = <0 0x03000000 0 0x40>, 2254 <0 0x03c04000 0 0x4>; 2255 reg-names = "qdsp6ss", "top_cc"; 2256 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2257 clock-names = "iface"; 2258 #clock-cells = <1>; 2259 status = "reserved"; /* Owned by ADSP firmware */ 2260 }; 2261 2262 lpass_rx_macro: codec@3200000 { 2263 compatible = "qcom,sc7280-lpass-rx-macro"; 2264 reg = <0 0x03200000 0 0x1000>; 2265 2266 pinctrl-names = "default"; 2267 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2268 2269 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2270 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2271 <&lpass_va_macro>; 2272 clock-names = "mclk", "npl", "fsgen"; 2273 2274 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2275 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2276 power-domain-names = "macro", "dcodec"; 2277 2278 #clock-cells = <0>; 2279 #sound-dai-cells = <1>; 2280 2281 status = "disabled"; 2282 }; 2283 2284 swr0: soundwire@3210000 { 2285 compatible = "qcom,soundwire-v1.6.0"; 2286 reg = <0 0x03210000 0 0x2000>; 2287 2288 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2289 clocks = <&lpass_rx_macro>; 2290 clock-names = "iface"; 2291 2292 qcom,din-ports = <0>; 2293 qcom,dout-ports = <5>; 2294 2295 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2296 reset-names = "swr_audio_cgcr"; 2297 2298 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2299 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2300 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2301 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2302 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2303 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2304 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2305 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2306 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2307 2308 #sound-dai-cells = <1>; 2309 #address-cells = <2>; 2310 #size-cells = <0>; 2311 2312 status = "disabled"; 2313 }; 2314 2315 lpass_tx_macro: codec@3220000 { 2316 compatible = "qcom,sc7280-lpass-tx-macro"; 2317 reg = <0 0x03220000 0 0x1000>; 2318 2319 pinctrl-names = "default"; 2320 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2321 2322 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2323 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2324 <&lpass_va_macro>; 2325 clock-names = "mclk", "npl", "fsgen"; 2326 2327 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2328 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2329 power-domain-names = "macro", "dcodec"; 2330 2331 #clock-cells = <0>; 2332 #sound-dai-cells = <1>; 2333 2334 status = "disabled"; 2335 }; 2336 2337 swr1: soundwire@3230000 { 2338 compatible = "qcom,soundwire-v1.6.0"; 2339 reg = <0 0x03230000 0 0x2000>; 2340 2341 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2342 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2343 clocks = <&lpass_tx_macro>; 2344 clock-names = "iface"; 2345 2346 qcom,din-ports = <3>; 2347 qcom,dout-ports = <0>; 2348 2349 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2350 reset-names = "swr_audio_cgcr"; 2351 2352 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2353 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2354 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2355 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2356 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2357 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2358 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2359 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2360 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2361 2362 #sound-dai-cells = <1>; 2363 #address-cells = <2>; 2364 #size-cells = <0>; 2365 2366 status = "disabled"; 2367 }; 2368 2369 lpass_audiocc: clock-controller@3300000 { 2370 compatible = "qcom,sc7280-lpassaudiocc"; 2371 reg = <0 0x03300000 0 0x30000>, 2372 <0 0x032a9000 0 0x1000>; 2373 clocks = <&rpmhcc RPMH_CXO_CLK>, 2374 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2375 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2376 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2377 #clock-cells = <1>; 2378 #power-domain-cells = <1>; 2379 #reset-cells = <1>; 2380 }; 2381 2382 lpass_va_macro: codec@3370000 { 2383 compatible = "qcom,sc7280-lpass-va-macro"; 2384 reg = <0 0x03370000 0 0x1000>; 2385 2386 pinctrl-names = "default"; 2387 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2388 2389 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2390 clock-names = "mclk"; 2391 2392 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2393 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2394 power-domain-names = "macro", "dcodec"; 2395 2396 #clock-cells = <0>; 2397 #sound-dai-cells = <1>; 2398 2399 status = "disabled"; 2400 }; 2401 2402 lpass_aon: clock-controller@3380000 { 2403 compatible = "qcom,sc7280-lpassaoncc"; 2404 reg = <0 0x03380000 0 0x30000>; 2405 clocks = <&rpmhcc RPMH_CXO_CLK>, 2406 <&rpmhcc RPMH_CXO_CLK_A>, 2407 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2408 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2409 #clock-cells = <1>; 2410 #power-domain-cells = <1>; 2411 status = "reserved"; /* Owned by ADSP firmware */ 2412 }; 2413 2414 lpass_core: clock-controller@3900000 { 2415 compatible = "qcom,sc7280-lpasscorecc"; 2416 reg = <0 0x03900000 0 0x50000>; 2417 clocks = <&rpmhcc RPMH_CXO_CLK>; 2418 clock-names = "bi_tcxo"; 2419 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2420 #clock-cells = <1>; 2421 #power-domain-cells = <1>; 2422 status = "reserved"; /* Owned by ADSP firmware */ 2423 }; 2424 2425 lpass_cpu: audio@3987000 { 2426 compatible = "qcom,sc7280-lpass-cpu"; 2427 2428 reg = <0 0x03987000 0 0x68000>, 2429 <0 0x03b00000 0 0x29000>, 2430 <0 0x03260000 0 0xc000>, 2431 <0 0x03280000 0 0x29000>, 2432 <0 0x03340000 0 0x29000>, 2433 <0 0x0336c000 0 0x3000>; 2434 reg-names = "lpass-hdmiif", 2435 "lpass-lpaif", 2436 "lpass-rxtx-cdc-dma-lpm", 2437 "lpass-rxtx-lpaif", 2438 "lpass-va-lpaif", 2439 "lpass-va-cdc-dma-lpm"; 2440 2441 iommus = <&apps_smmu 0x1820 0>, 2442 <&apps_smmu 0x1821 0>, 2443 <&apps_smmu 0x1832 0>; 2444 2445 power-domains = <&rpmhpd SC7280_LCX>; 2446 power-domain-names = "lcx"; 2447 required-opps = <&rpmhpd_opp_nom>; 2448 2449 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2450 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2451 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2452 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2453 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2454 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2455 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2456 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2457 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2458 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2459 clock-names = "aon_cc_audio_hm_h", 2460 "audio_cc_ext_mclk0", 2461 "core_cc_sysnoc_mport_core", 2462 "core_cc_ext_if0_ibit", 2463 "core_cc_ext_if1_ibit", 2464 "audio_cc_codec_mem", 2465 "audio_cc_codec_mem0", 2466 "audio_cc_codec_mem1", 2467 "audio_cc_codec_mem2", 2468 "aon_cc_va_mem0"; 2469 2470 #sound-dai-cells = <1>; 2471 #address-cells = <1>; 2472 #size-cells = <0>; 2473 2474 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2478 interrupt-names = "lpass-irq-lpaif", 2479 "lpass-irq-hdmi", 2480 "lpass-irq-vaif", 2481 "lpass-irq-rxtxif"; 2482 2483 status = "disabled"; 2484 }; 2485 2486 lpass_hm: clock-controller@3c00000 { 2487 compatible = "qcom,sc7280-lpasshm"; 2488 reg = <0 0x03c00000 0 0x28>; 2489 clocks = <&rpmhcc RPMH_CXO_CLK>; 2490 clock-names = "bi_tcxo"; 2491 #clock-cells = <1>; 2492 #power-domain-cells = <1>; 2493 status = "reserved"; /* Owned by ADSP firmware */ 2494 }; 2495 2496 lpass_ag_noc: interconnect@3c40000 { 2497 reg = <0 0x03c40000 0 0xf080>; 2498 compatible = "qcom,sc7280-lpass-ag-noc"; 2499 #interconnect-cells = <2>; 2500 qcom,bcm-voters = <&apps_bcm_voter>; 2501 }; 2502 2503 lpass_tlmm: pinctrl@33c0000 { 2504 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2505 reg = <0 0x033c0000 0x0 0x20000>, 2506 <0 0x03550000 0x0 0x10000>; 2507 qcom,adsp-bypass-mode; 2508 gpio-controller; 2509 #gpio-cells = <2>; 2510 gpio-ranges = <&lpass_tlmm 0 0 15>; 2511 2512 lpass_dmic01_clk: dmic01-clk-state { 2513 pins = "gpio6"; 2514 function = "dmic1_clk"; 2515 }; 2516 2517 lpass_dmic01_data: dmic01-data-state { 2518 pins = "gpio7"; 2519 function = "dmic1_data"; 2520 }; 2521 2522 lpass_dmic23_clk: dmic23-clk-state { 2523 pins = "gpio8"; 2524 function = "dmic2_clk"; 2525 }; 2526 2527 lpass_dmic23_data: dmic23-data-state { 2528 pins = "gpio9"; 2529 function = "dmic2_data"; 2530 }; 2531 2532 lpass_rx_swr_clk: rx-swr-clk-state { 2533 pins = "gpio3"; 2534 function = "swr_rx_clk"; 2535 }; 2536 2537 lpass_rx_swr_data: rx-swr-data-state { 2538 pins = "gpio4", "gpio5"; 2539 function = "swr_rx_data"; 2540 }; 2541 2542 lpass_tx_swr_clk: tx-swr-clk-state { 2543 pins = "gpio0"; 2544 function = "swr_tx_clk"; 2545 }; 2546 2547 lpass_tx_swr_data: tx-swr-data-state { 2548 pins = "gpio1", "gpio2", "gpio14"; 2549 function = "swr_tx_data"; 2550 }; 2551 }; 2552 2553 gpu: gpu@3d00000 { 2554 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2555 reg = <0 0x03d00000 0 0x40000>, 2556 <0 0x03d9e000 0 0x1000>, 2557 <0 0x03d61000 0 0x800>; 2558 reg-names = "kgsl_3d0_reg_memory", 2559 "cx_mem", 2560 "cx_dbgc"; 2561 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2562 iommus = <&adreno_smmu 0 0x400>, 2563 <&adreno_smmu 1 0x400>; 2564 operating-points-v2 = <&gpu_opp_table>; 2565 qcom,gmu = <&gmu>; 2566 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2567 interconnect-names = "gfx-mem"; 2568 #cooling-cells = <2>; 2569 2570 nvmem-cells = <&gpu_speed_bin>; 2571 nvmem-cell-names = "speed_bin"; 2572 2573 gpu_opp_table: opp-table { 2574 compatible = "operating-points-v2"; 2575 2576 opp-315000000 { 2577 opp-hz = /bits/ 64 <315000000>; 2578 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2579 opp-peak-kBps = <1804000>; 2580 opp-supported-hw = <0x03>; 2581 }; 2582 2583 opp-450000000 { 2584 opp-hz = /bits/ 64 <450000000>; 2585 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2586 opp-peak-kBps = <4068000>; 2587 opp-supported-hw = <0x03>; 2588 }; 2589 2590 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2591 opp-550000000-0 { 2592 opp-hz = /bits/ 64 <550000000>; 2593 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2594 opp-peak-kBps = <8368000>; 2595 opp-supported-hw = <0x01>; 2596 }; 2597 2598 opp-550000000-1 { 2599 opp-hz = /bits/ 64 <550000000>; 2600 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2601 opp-peak-kBps = <6832000>; 2602 opp-supported-hw = <0x02>; 2603 }; 2604 2605 opp-608000000 { 2606 opp-hz = /bits/ 64 <608000000>; 2607 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2608 opp-peak-kBps = <8368000>; 2609 opp-supported-hw = <0x02>; 2610 }; 2611 2612 opp-700000000 { 2613 opp-hz = /bits/ 64 <700000000>; 2614 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2615 opp-peak-kBps = <8532000>; 2616 opp-supported-hw = <0x02>; 2617 }; 2618 2619 opp-812000000 { 2620 opp-hz = /bits/ 64 <812000000>; 2621 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2622 opp-peak-kBps = <8532000>; 2623 opp-supported-hw = <0x02>; 2624 }; 2625 2626 opp-840000000 { 2627 opp-hz = /bits/ 64 <840000000>; 2628 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2629 opp-peak-kBps = <8532000>; 2630 opp-supported-hw = <0x02>; 2631 }; 2632 2633 opp-900000000 { 2634 opp-hz = /bits/ 64 <900000000>; 2635 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2636 opp-peak-kBps = <8532000>; 2637 opp-supported-hw = <0x02>; 2638 }; 2639 }; 2640 }; 2641 2642 gmu: gmu@3d6a000 { 2643 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2644 reg = <0 0x03d6a000 0 0x34000>, 2645 <0 0x3de0000 0 0x10000>, 2646 <0 0x0b290000 0 0x10000>; 2647 reg-names = "gmu", "rscc", "gmu_pdc"; 2648 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2649 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2650 interrupt-names = "hfi", "gmu"; 2651 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2652 <&gpucc GPU_CC_CXO_CLK>, 2653 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2654 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2655 <&gpucc GPU_CC_AHB_CLK>, 2656 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2657 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2658 clock-names = "gmu", 2659 "cxo", 2660 "axi", 2661 "memnoc", 2662 "ahb", 2663 "hub", 2664 "smmu_vote"; 2665 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2666 <&gpucc GPU_CC_GX_GDSC>; 2667 power-domain-names = "cx", 2668 "gx"; 2669 iommus = <&adreno_smmu 5 0x400>; 2670 operating-points-v2 = <&gmu_opp_table>; 2671 2672 gmu_opp_table: opp-table { 2673 compatible = "operating-points-v2"; 2674 2675 opp-200000000 { 2676 opp-hz = /bits/ 64 <200000000>; 2677 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2678 }; 2679 }; 2680 }; 2681 2682 gpucc: clock-controller@3d90000 { 2683 compatible = "qcom,sc7280-gpucc"; 2684 reg = <0 0x03d90000 0 0x9000>; 2685 clocks = <&rpmhcc RPMH_CXO_CLK>, 2686 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2687 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2688 clock-names = "bi_tcxo", 2689 "gcc_gpu_gpll0_clk_src", 2690 "gcc_gpu_gpll0_div_clk_src"; 2691 #clock-cells = <1>; 2692 #reset-cells = <1>; 2693 #power-domain-cells = <1>; 2694 }; 2695 2696 dma@117f000 { 2697 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2698 reg = <0x0 0x0117f000 0x0 0x1000>, 2699 <0x0 0x01112000 0x0 0x6000>; 2700 }; 2701 2702 adreno_smmu: iommu@3da0000 { 2703 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2704 "qcom,smmu-500", "arm,mmu-500"; 2705 reg = <0 0x03da0000 0 0x20000>; 2706 #iommu-cells = <2>; 2707 #global-interrupts = <2>; 2708 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2720 2721 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2722 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2723 <&gpucc GPU_CC_AHB_CLK>, 2724 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2725 <&gpucc GPU_CC_CX_GMU_CLK>, 2726 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2727 <&gpucc GPU_CC_HUB_AON_CLK>; 2728 clock-names = "gcc_gpu_memnoc_gfx_clk", 2729 "gcc_gpu_snoc_dvm_gfx_clk", 2730 "gpu_cc_ahb_clk", 2731 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2732 "gpu_cc_cx_gmu_clk", 2733 "gpu_cc_hub_cx_int_clk", 2734 "gpu_cc_hub_aon_clk"; 2735 2736 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2737 dma-coherent; 2738 }; 2739 2740 remoteproc_mpss: remoteproc@4080000 { 2741 compatible = "qcom,sc7280-mpss-pas"; 2742 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2743 reg-names = "qdsp6", "rmb"; 2744 2745 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2746 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2747 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2748 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2749 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2750 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2751 interrupt-names = "wdog", "fatal", "ready", "handover", 2752 "stop-ack", "shutdown-ack"; 2753 2754 clocks = <&rpmhcc RPMH_CXO_CLK>; 2755 clock-names = "xo"; 2756 2757 power-domains = <&rpmhpd SC7280_CX>, 2758 <&rpmhpd SC7280_MSS>; 2759 power-domain-names = "cx", "mss"; 2760 2761 memory-region = <&mpss_mem>; 2762 2763 qcom,qmp = <&aoss_qmp>; 2764 2765 qcom,smem-states = <&modem_smp2p_out 0>; 2766 qcom,smem-state-names = "stop"; 2767 2768 status = "disabled"; 2769 2770 glink-edge { 2771 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2772 IPCC_MPROC_SIGNAL_GLINK_QMP 2773 IRQ_TYPE_EDGE_RISING>; 2774 mboxes = <&ipcc IPCC_CLIENT_MPSS 2775 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2776 label = "modem"; 2777 qcom,remote-pid = <1>; 2778 }; 2779 }; 2780 2781 stm@6002000 { 2782 compatible = "arm,coresight-stm", "arm,primecell"; 2783 reg = <0 0x06002000 0 0x1000>, 2784 <0 0x16280000 0 0x180000>; 2785 reg-names = "stm-base", "stm-stimulus-base"; 2786 2787 clocks = <&aoss_qmp>; 2788 clock-names = "apb_pclk"; 2789 2790 out-ports { 2791 port { 2792 stm_out: endpoint { 2793 remote-endpoint = <&funnel0_in7>; 2794 }; 2795 }; 2796 }; 2797 }; 2798 2799 funnel@6041000 { 2800 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2801 reg = <0 0x06041000 0 0x1000>; 2802 2803 clocks = <&aoss_qmp>; 2804 clock-names = "apb_pclk"; 2805 2806 out-ports { 2807 port { 2808 funnel0_out: endpoint { 2809 remote-endpoint = <&merge_funnel_in0>; 2810 }; 2811 }; 2812 }; 2813 2814 in-ports { 2815 #address-cells = <1>; 2816 #size-cells = <0>; 2817 2818 port@7 { 2819 reg = <7>; 2820 funnel0_in7: endpoint { 2821 remote-endpoint = <&stm_out>; 2822 }; 2823 }; 2824 }; 2825 }; 2826 2827 funnel@6042000 { 2828 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2829 reg = <0 0x06042000 0 0x1000>; 2830 2831 clocks = <&aoss_qmp>; 2832 clock-names = "apb_pclk"; 2833 2834 out-ports { 2835 port { 2836 funnel1_out: endpoint { 2837 remote-endpoint = <&merge_funnel_in1>; 2838 }; 2839 }; 2840 }; 2841 2842 in-ports { 2843 #address-cells = <1>; 2844 #size-cells = <0>; 2845 2846 port@4 { 2847 reg = <4>; 2848 funnel1_in4: endpoint { 2849 remote-endpoint = <&apss_merge_funnel_out>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 funnel@6045000 { 2856 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2857 reg = <0 0x06045000 0 0x1000>; 2858 2859 clocks = <&aoss_qmp>; 2860 clock-names = "apb_pclk"; 2861 2862 out-ports { 2863 port { 2864 merge_funnel_out: endpoint { 2865 remote-endpoint = <&swao_funnel_in>; 2866 }; 2867 }; 2868 }; 2869 2870 in-ports { 2871 #address-cells = <1>; 2872 #size-cells = <0>; 2873 2874 port@0 { 2875 reg = <0>; 2876 merge_funnel_in0: endpoint { 2877 remote-endpoint = <&funnel0_out>; 2878 }; 2879 }; 2880 2881 port@1 { 2882 reg = <1>; 2883 merge_funnel_in1: endpoint { 2884 remote-endpoint = <&funnel1_out>; 2885 }; 2886 }; 2887 }; 2888 }; 2889 2890 replicator@6046000 { 2891 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2892 reg = <0 0x06046000 0 0x1000>; 2893 2894 clocks = <&aoss_qmp>; 2895 clock-names = "apb_pclk"; 2896 2897 out-ports { 2898 port { 2899 replicator_out: endpoint { 2900 remote-endpoint = <&etr_in>; 2901 }; 2902 }; 2903 }; 2904 2905 in-ports { 2906 port { 2907 replicator_in: endpoint { 2908 remote-endpoint = <&swao_replicator_out>; 2909 }; 2910 }; 2911 }; 2912 }; 2913 2914 etr@6048000 { 2915 compatible = "arm,coresight-tmc", "arm,primecell"; 2916 reg = <0 0x06048000 0 0x1000>; 2917 iommus = <&apps_smmu 0x04c0 0>; 2918 2919 clocks = <&aoss_qmp>; 2920 clock-names = "apb_pclk"; 2921 arm,scatter-gather; 2922 2923 in-ports { 2924 port { 2925 etr_in: endpoint { 2926 remote-endpoint = <&replicator_out>; 2927 }; 2928 }; 2929 }; 2930 }; 2931 2932 funnel@6b04000 { 2933 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2934 reg = <0 0x06b04000 0 0x1000>; 2935 2936 clocks = <&aoss_qmp>; 2937 clock-names = "apb_pclk"; 2938 2939 out-ports { 2940 port { 2941 swao_funnel_out: endpoint { 2942 remote-endpoint = <&etf_in>; 2943 }; 2944 }; 2945 }; 2946 2947 in-ports { 2948 #address-cells = <1>; 2949 #size-cells = <0>; 2950 2951 port@7 { 2952 reg = <7>; 2953 swao_funnel_in: endpoint { 2954 remote-endpoint = <&merge_funnel_out>; 2955 }; 2956 }; 2957 }; 2958 }; 2959 2960 etf@6b05000 { 2961 compatible = "arm,coresight-tmc", "arm,primecell"; 2962 reg = <0 0x06b05000 0 0x1000>; 2963 2964 clocks = <&aoss_qmp>; 2965 clock-names = "apb_pclk"; 2966 2967 out-ports { 2968 port { 2969 etf_out: endpoint { 2970 remote-endpoint = <&swao_replicator_in>; 2971 }; 2972 }; 2973 }; 2974 2975 in-ports { 2976 port { 2977 etf_in: endpoint { 2978 remote-endpoint = <&swao_funnel_out>; 2979 }; 2980 }; 2981 }; 2982 }; 2983 2984 replicator@6b06000 { 2985 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2986 reg = <0 0x06b06000 0 0x1000>; 2987 2988 clocks = <&aoss_qmp>; 2989 clock-names = "apb_pclk"; 2990 qcom,replicator-loses-context; 2991 2992 out-ports { 2993 port { 2994 swao_replicator_out: endpoint { 2995 remote-endpoint = <&replicator_in>; 2996 }; 2997 }; 2998 }; 2999 3000 in-ports { 3001 port { 3002 swao_replicator_in: endpoint { 3003 remote-endpoint = <&etf_out>; 3004 }; 3005 }; 3006 }; 3007 }; 3008 3009 etm@7040000 { 3010 compatible = "arm,coresight-etm4x", "arm,primecell"; 3011 reg = <0 0x07040000 0 0x1000>; 3012 3013 cpu = <&CPU0>; 3014 3015 clocks = <&aoss_qmp>; 3016 clock-names = "apb_pclk"; 3017 arm,coresight-loses-context-with-cpu; 3018 qcom,skip-power-up; 3019 3020 out-ports { 3021 port { 3022 etm0_out: endpoint { 3023 remote-endpoint = <&apss_funnel_in0>; 3024 }; 3025 }; 3026 }; 3027 }; 3028 3029 etm@7140000 { 3030 compatible = "arm,coresight-etm4x", "arm,primecell"; 3031 reg = <0 0x07140000 0 0x1000>; 3032 3033 cpu = <&CPU1>; 3034 3035 clocks = <&aoss_qmp>; 3036 clock-names = "apb_pclk"; 3037 arm,coresight-loses-context-with-cpu; 3038 qcom,skip-power-up; 3039 3040 out-ports { 3041 port { 3042 etm1_out: endpoint { 3043 remote-endpoint = <&apss_funnel_in1>; 3044 }; 3045 }; 3046 }; 3047 }; 3048 3049 etm@7240000 { 3050 compatible = "arm,coresight-etm4x", "arm,primecell"; 3051 reg = <0 0x07240000 0 0x1000>; 3052 3053 cpu = <&CPU2>; 3054 3055 clocks = <&aoss_qmp>; 3056 clock-names = "apb_pclk"; 3057 arm,coresight-loses-context-with-cpu; 3058 qcom,skip-power-up; 3059 3060 out-ports { 3061 port { 3062 etm2_out: endpoint { 3063 remote-endpoint = <&apss_funnel_in2>; 3064 }; 3065 }; 3066 }; 3067 }; 3068 3069 etm@7340000 { 3070 compatible = "arm,coresight-etm4x", "arm,primecell"; 3071 reg = <0 0x07340000 0 0x1000>; 3072 3073 cpu = <&CPU3>; 3074 3075 clocks = <&aoss_qmp>; 3076 clock-names = "apb_pclk"; 3077 arm,coresight-loses-context-with-cpu; 3078 qcom,skip-power-up; 3079 3080 out-ports { 3081 port { 3082 etm3_out: endpoint { 3083 remote-endpoint = <&apss_funnel_in3>; 3084 }; 3085 }; 3086 }; 3087 }; 3088 3089 etm@7440000 { 3090 compatible = "arm,coresight-etm4x", "arm,primecell"; 3091 reg = <0 0x07440000 0 0x1000>; 3092 3093 cpu = <&CPU4>; 3094 3095 clocks = <&aoss_qmp>; 3096 clock-names = "apb_pclk"; 3097 arm,coresight-loses-context-with-cpu; 3098 qcom,skip-power-up; 3099 3100 out-ports { 3101 port { 3102 etm4_out: endpoint { 3103 remote-endpoint = <&apss_funnel_in4>; 3104 }; 3105 }; 3106 }; 3107 }; 3108 3109 etm@7540000 { 3110 compatible = "arm,coresight-etm4x", "arm,primecell"; 3111 reg = <0 0x07540000 0 0x1000>; 3112 3113 cpu = <&CPU5>; 3114 3115 clocks = <&aoss_qmp>; 3116 clock-names = "apb_pclk"; 3117 arm,coresight-loses-context-with-cpu; 3118 qcom,skip-power-up; 3119 3120 out-ports { 3121 port { 3122 etm5_out: endpoint { 3123 remote-endpoint = <&apss_funnel_in5>; 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 etm@7640000 { 3130 compatible = "arm,coresight-etm4x", "arm,primecell"; 3131 reg = <0 0x07640000 0 0x1000>; 3132 3133 cpu = <&CPU6>; 3134 3135 clocks = <&aoss_qmp>; 3136 clock-names = "apb_pclk"; 3137 arm,coresight-loses-context-with-cpu; 3138 qcom,skip-power-up; 3139 3140 out-ports { 3141 port { 3142 etm6_out: endpoint { 3143 remote-endpoint = <&apss_funnel_in6>; 3144 }; 3145 }; 3146 }; 3147 }; 3148 3149 etm@7740000 { 3150 compatible = "arm,coresight-etm4x", "arm,primecell"; 3151 reg = <0 0x07740000 0 0x1000>; 3152 3153 cpu = <&CPU7>; 3154 3155 clocks = <&aoss_qmp>; 3156 clock-names = "apb_pclk"; 3157 arm,coresight-loses-context-with-cpu; 3158 qcom,skip-power-up; 3159 3160 out-ports { 3161 port { 3162 etm7_out: endpoint { 3163 remote-endpoint = <&apss_funnel_in7>; 3164 }; 3165 }; 3166 }; 3167 }; 3168 3169 funnel@7800000 { /* APSS Funnel */ 3170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3171 reg = <0 0x07800000 0 0x1000>; 3172 3173 clocks = <&aoss_qmp>; 3174 clock-names = "apb_pclk"; 3175 3176 out-ports { 3177 port { 3178 apss_funnel_out: endpoint { 3179 remote-endpoint = <&apss_merge_funnel_in>; 3180 }; 3181 }; 3182 }; 3183 3184 in-ports { 3185 #address-cells = <1>; 3186 #size-cells = <0>; 3187 3188 port@0 { 3189 reg = <0>; 3190 apss_funnel_in0: endpoint { 3191 remote-endpoint = <&etm0_out>; 3192 }; 3193 }; 3194 3195 port@1 { 3196 reg = <1>; 3197 apss_funnel_in1: endpoint { 3198 remote-endpoint = <&etm1_out>; 3199 }; 3200 }; 3201 3202 port@2 { 3203 reg = <2>; 3204 apss_funnel_in2: endpoint { 3205 remote-endpoint = <&etm2_out>; 3206 }; 3207 }; 3208 3209 port@3 { 3210 reg = <3>; 3211 apss_funnel_in3: endpoint { 3212 remote-endpoint = <&etm3_out>; 3213 }; 3214 }; 3215 3216 port@4 { 3217 reg = <4>; 3218 apss_funnel_in4: endpoint { 3219 remote-endpoint = <&etm4_out>; 3220 }; 3221 }; 3222 3223 port@5 { 3224 reg = <5>; 3225 apss_funnel_in5: endpoint { 3226 remote-endpoint = <&etm5_out>; 3227 }; 3228 }; 3229 3230 port@6 { 3231 reg = <6>; 3232 apss_funnel_in6: endpoint { 3233 remote-endpoint = <&etm6_out>; 3234 }; 3235 }; 3236 3237 port@7 { 3238 reg = <7>; 3239 apss_funnel_in7: endpoint { 3240 remote-endpoint = <&etm7_out>; 3241 }; 3242 }; 3243 }; 3244 }; 3245 3246 funnel@7810000 { 3247 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3248 reg = <0 0x07810000 0 0x1000>; 3249 3250 clocks = <&aoss_qmp>; 3251 clock-names = "apb_pclk"; 3252 3253 out-ports { 3254 port { 3255 apss_merge_funnel_out: endpoint { 3256 remote-endpoint = <&funnel1_in4>; 3257 }; 3258 }; 3259 }; 3260 3261 in-ports { 3262 port { 3263 apss_merge_funnel_in: endpoint { 3264 remote-endpoint = <&apss_funnel_out>; 3265 }; 3266 }; 3267 }; 3268 }; 3269 3270 sdhc_2: mmc@8804000 { 3271 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3272 pinctrl-names = "default", "sleep"; 3273 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3274 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3275 status = "disabled"; 3276 3277 reg = <0 0x08804000 0 0x1000>; 3278 3279 iommus = <&apps_smmu 0x100 0x0>; 3280 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3282 interrupt-names = "hc_irq", "pwr_irq"; 3283 3284 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3285 <&gcc GCC_SDCC2_APPS_CLK>, 3286 <&rpmhcc RPMH_CXO_CLK>; 3287 clock-names = "iface", "core", "xo"; 3288 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3289 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3290 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3291 power-domains = <&rpmhpd SC7280_CX>; 3292 operating-points-v2 = <&sdhc2_opp_table>; 3293 3294 bus-width = <4>; 3295 dma-coherent; 3296 3297 qcom,dll-config = <0x0007642c>; 3298 3299 resets = <&gcc GCC_SDCC2_BCR>; 3300 3301 sdhc2_opp_table: opp-table { 3302 compatible = "operating-points-v2"; 3303 3304 opp-100000000 { 3305 opp-hz = /bits/ 64 <100000000>; 3306 required-opps = <&rpmhpd_opp_low_svs>; 3307 opp-peak-kBps = <1800000 400000>; 3308 opp-avg-kBps = <100000 0>; 3309 }; 3310 3311 opp-202000000 { 3312 opp-hz = /bits/ 64 <202000000>; 3313 required-opps = <&rpmhpd_opp_nom>; 3314 opp-peak-kBps = <5400000 1600000>; 3315 opp-avg-kBps = <200000 0>; 3316 }; 3317 }; 3318 }; 3319 3320 usb_1_hsphy: phy@88e3000 { 3321 compatible = "qcom,sc7280-usb-hs-phy", 3322 "qcom,usb-snps-hs-7nm-phy"; 3323 reg = <0 0x088e3000 0 0x400>; 3324 status = "disabled"; 3325 #phy-cells = <0>; 3326 3327 clocks = <&rpmhcc RPMH_CXO_CLK>; 3328 clock-names = "ref"; 3329 3330 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3331 }; 3332 3333 usb_2_hsphy: phy@88e4000 { 3334 compatible = "qcom,sc7280-usb-hs-phy", 3335 "qcom,usb-snps-hs-7nm-phy"; 3336 reg = <0 0x088e4000 0 0x400>; 3337 status = "disabled"; 3338 #phy-cells = <0>; 3339 3340 clocks = <&rpmhcc RPMH_CXO_CLK>; 3341 clock-names = "ref"; 3342 3343 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3344 }; 3345 3346 usb_1_qmpphy: phy-wrapper@88e9000 { 3347 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3348 "qcom,sm8250-qmp-usb3-dp-phy"; 3349 reg = <0 0x088e9000 0 0x200>, 3350 <0 0x088e8000 0 0x40>, 3351 <0 0x088ea000 0 0x200>; 3352 status = "disabled"; 3353 #address-cells = <2>; 3354 #size-cells = <2>; 3355 ranges; 3356 3357 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3358 <&rpmhcc RPMH_CXO_CLK>, 3359 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3360 clock-names = "aux", "ref_clk_src", "com_aux"; 3361 3362 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3363 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3364 reset-names = "phy", "common"; 3365 3366 usb_1_ssphy: usb3-phy@88e9200 { 3367 reg = <0 0x088e9200 0 0x200>, 3368 <0 0x088e9400 0 0x200>, 3369 <0 0x088e9c00 0 0x400>, 3370 <0 0x088e9600 0 0x200>, 3371 <0 0x088e9800 0 0x200>, 3372 <0 0x088e9a00 0 0x100>; 3373 #clock-cells = <0>; 3374 #phy-cells = <0>; 3375 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3376 clock-names = "pipe0"; 3377 clock-output-names = "usb3_phy_pipe_clk_src"; 3378 }; 3379 3380 dp_phy: dp-phy@88ea200 { 3381 reg = <0 0x088ea200 0 0x200>, 3382 <0 0x088ea400 0 0x200>, 3383 <0 0x088eaa00 0 0x200>, 3384 <0 0x088ea600 0 0x200>, 3385 <0 0x088ea800 0 0x200>; 3386 #phy-cells = <0>; 3387 #clock-cells = <1>; 3388 }; 3389 }; 3390 3391 usb_2: usb@8cf8800 { 3392 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3393 reg = <0 0x08cf8800 0 0x400>; 3394 status = "disabled"; 3395 #address-cells = <2>; 3396 #size-cells = <2>; 3397 ranges; 3398 dma-ranges; 3399 3400 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3401 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3402 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3403 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3404 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3405 clock-names = "cfg_noc", 3406 "core", 3407 "iface", 3408 "sleep", 3409 "mock_utmi"; 3410 3411 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3412 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3413 assigned-clock-rates = <19200000>, <200000000>; 3414 3415 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3416 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3417 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3418 interrupt-names = "hs_phy_irq", 3419 "dp_hs_phy_irq", 3420 "dm_hs_phy_irq"; 3421 3422 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3423 required-opps = <&rpmhpd_opp_nom>; 3424 3425 resets = <&gcc GCC_USB30_SEC_BCR>; 3426 3427 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3428 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3429 interconnect-names = "usb-ddr", "apps-usb"; 3430 3431 usb_2_dwc3: usb@8c00000 { 3432 compatible = "snps,dwc3"; 3433 reg = <0 0x08c00000 0 0xe000>; 3434 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3435 iommus = <&apps_smmu 0xa0 0x0>; 3436 snps,dis_u2_susphy_quirk; 3437 snps,dis_enblslpm_quirk; 3438 phys = <&usb_2_hsphy>; 3439 phy-names = "usb2-phy"; 3440 maximum-speed = "high-speed"; 3441 usb-role-switch; 3442 3443 port { 3444 usb2_role_switch: endpoint { 3445 remote-endpoint = <&eud_ep>; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 qspi: spi@88dc000 { 3452 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3453 reg = <0 0x088dc000 0 0x1000>; 3454 iommus = <&apps_smmu 0x20 0x0>; 3455 #address-cells = <1>; 3456 #size-cells = <0>; 3457 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3458 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3459 <&gcc GCC_QSPI_CORE_CLK>; 3460 clock-names = "iface", "core"; 3461 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3462 &cnoc2 SLAVE_QSPI_0 0>; 3463 interconnect-names = "qspi-config"; 3464 power-domains = <&rpmhpd SC7280_CX>; 3465 operating-points-v2 = <&qspi_opp_table>; 3466 status = "disabled"; 3467 }; 3468 3469 remoteproc_wpss: remoteproc@8a00000 { 3470 compatible = "qcom,sc7280-wpss-pil"; 3471 reg = <0 0x08a00000 0 0x10000>; 3472 3473 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3474 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3475 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3476 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3477 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3478 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3479 interrupt-names = "wdog", "fatal", "ready", "handover", 3480 "stop-ack", "shutdown-ack"; 3481 3482 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3483 <&gcc GCC_WPSS_AHB_CLK>, 3484 <&gcc GCC_WPSS_RSCP_CLK>, 3485 <&rpmhcc RPMH_CXO_CLK>; 3486 clock-names = "ahb_bdg", "ahb", 3487 "rscp", "xo"; 3488 3489 power-domains = <&rpmhpd SC7280_CX>, 3490 <&rpmhpd SC7280_MX>; 3491 power-domain-names = "cx", "mx"; 3492 3493 memory-region = <&wpss_mem>; 3494 3495 qcom,qmp = <&aoss_qmp>; 3496 3497 qcom,smem-states = <&wpss_smp2p_out 0>; 3498 qcom,smem-state-names = "stop"; 3499 3500 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3501 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3502 reset-names = "restart", "pdc_sync"; 3503 3504 qcom,halt-regs = <&tcsr_1 0x17000>; 3505 3506 status = "disabled"; 3507 3508 glink-edge { 3509 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3510 IPCC_MPROC_SIGNAL_GLINK_QMP 3511 IRQ_TYPE_EDGE_RISING>; 3512 mboxes = <&ipcc IPCC_CLIENT_WPSS 3513 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3514 3515 label = "wpss"; 3516 qcom,remote-pid = <13>; 3517 }; 3518 }; 3519 3520 pmu@9091000 { 3521 compatible = "qcom,sc7280-llcc-bwmon"; 3522 reg = <0 0x09091000 0 0x1000>; 3523 3524 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3525 3526 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3527 3528 operating-points-v2 = <&llcc_bwmon_opp_table>; 3529 3530 llcc_bwmon_opp_table: opp-table { 3531 compatible = "operating-points-v2"; 3532 3533 opp-0 { 3534 opp-peak-kBps = <800000>; 3535 }; 3536 opp-1 { 3537 opp-peak-kBps = <1804000>; 3538 }; 3539 opp-2 { 3540 opp-peak-kBps = <2188000>; 3541 }; 3542 opp-3 { 3543 opp-peak-kBps = <3072000>; 3544 }; 3545 opp-4 { 3546 opp-peak-kBps = <4068000>; 3547 }; 3548 opp-5 { 3549 opp-peak-kBps = <6220000>; 3550 }; 3551 opp-6 { 3552 opp-peak-kBps = <6832000>; 3553 }; 3554 opp-7 { 3555 opp-peak-kBps = <8532000>; 3556 }; 3557 }; 3558 }; 3559 3560 pmu@90b6400 { 3561 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3562 reg = <0 0x090b6400 0 0x600>; 3563 3564 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3565 3566 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3567 operating-points-v2 = <&cpu_bwmon_opp_table>; 3568 3569 cpu_bwmon_opp_table: opp-table { 3570 compatible = "operating-points-v2"; 3571 3572 opp-0 { 3573 opp-peak-kBps = <2400000>; 3574 }; 3575 opp-1 { 3576 opp-peak-kBps = <4800000>; 3577 }; 3578 opp-2 { 3579 opp-peak-kBps = <7456000>; 3580 }; 3581 opp-3 { 3582 opp-peak-kBps = <9600000>; 3583 }; 3584 opp-4 { 3585 opp-peak-kBps = <12896000>; 3586 }; 3587 opp-5 { 3588 opp-peak-kBps = <14928000>; 3589 }; 3590 opp-6 { 3591 opp-peak-kBps = <17056000>; 3592 }; 3593 }; 3594 }; 3595 3596 dc_noc: interconnect@90e0000 { 3597 reg = <0 0x090e0000 0 0x5080>; 3598 compatible = "qcom,sc7280-dc-noc"; 3599 #interconnect-cells = <2>; 3600 qcom,bcm-voters = <&apps_bcm_voter>; 3601 }; 3602 3603 gem_noc: interconnect@9100000 { 3604 reg = <0 0x09100000 0 0xe2200>; 3605 compatible = "qcom,sc7280-gem-noc"; 3606 #interconnect-cells = <2>; 3607 qcom,bcm-voters = <&apps_bcm_voter>; 3608 }; 3609 3610 system-cache-controller@9200000 { 3611 compatible = "qcom,sc7280-llcc"; 3612 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3613 <0 0x09600000 0 0x58000>; 3614 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3615 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3616 }; 3617 3618 eud: eud@88e0000 { 3619 compatible = "qcom,sc7280-eud", "qcom,eud"; 3620 reg = <0 0x88e0000 0 0x2000>, 3621 <0 0x88e2000 0 0x1000>; 3622 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3623 3624 status = "disabled"; 3625 3626 ports { 3627 #address-cells = <1>; 3628 #size-cells = <0>; 3629 3630 port@0 { 3631 reg = <0>; 3632 eud_ep: endpoint { 3633 remote-endpoint = <&usb2_role_switch>; 3634 }; 3635 }; 3636 }; 3637 }; 3638 3639 nsp_noc: interconnect@a0c0000 { 3640 reg = <0 0x0a0c0000 0 0x10000>; 3641 compatible = "qcom,sc7280-nsp-noc"; 3642 #interconnect-cells = <2>; 3643 qcom,bcm-voters = <&apps_bcm_voter>; 3644 }; 3645 3646 usb_1: usb@a6f8800 { 3647 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3648 reg = <0 0x0a6f8800 0 0x400>; 3649 status = "disabled"; 3650 #address-cells = <2>; 3651 #size-cells = <2>; 3652 ranges; 3653 dma-ranges; 3654 3655 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3656 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3657 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3658 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3659 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3660 clock-names = "cfg_noc", 3661 "core", 3662 "iface", 3663 "sleep", 3664 "mock_utmi"; 3665 3666 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3667 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3668 assigned-clock-rates = <19200000>, <200000000>; 3669 3670 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3671 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3672 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3673 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3674 interrupt-names = "hs_phy_irq", 3675 "dp_hs_phy_irq", 3676 "dm_hs_phy_irq", 3677 "ss_phy_irq"; 3678 3679 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3680 required-opps = <&rpmhpd_opp_nom>; 3681 3682 resets = <&gcc GCC_USB30_PRIM_BCR>; 3683 3684 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3685 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3686 interconnect-names = "usb-ddr", "apps-usb"; 3687 3688 wakeup-source; 3689 3690 usb_1_dwc3: usb@a600000 { 3691 compatible = "snps,dwc3"; 3692 reg = <0 0x0a600000 0 0xe000>; 3693 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3694 iommus = <&apps_smmu 0xe0 0x0>; 3695 snps,dis_u2_susphy_quirk; 3696 snps,dis_enblslpm_quirk; 3697 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3698 phy-names = "usb2-phy", "usb3-phy"; 3699 maximum-speed = "super-speed"; 3700 }; 3701 }; 3702 3703 venus: video-codec@aa00000 { 3704 compatible = "qcom,sc7280-venus"; 3705 reg = <0 0x0aa00000 0 0xd0600>; 3706 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3707 3708 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3709 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3710 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3711 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3712 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3713 clock-names = "core", "bus", "iface", 3714 "vcodec_core", "vcodec_bus"; 3715 3716 power-domains = <&videocc MVSC_GDSC>, 3717 <&videocc MVS0_GDSC>, 3718 <&rpmhpd SC7280_CX>; 3719 power-domain-names = "venus", "vcodec0", "cx"; 3720 operating-points-v2 = <&venus_opp_table>; 3721 3722 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3723 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3724 interconnect-names = "cpu-cfg", "video-mem"; 3725 3726 iommus = <&apps_smmu 0x2180 0x20>, 3727 <&apps_smmu 0x2184 0x20>; 3728 memory-region = <&video_mem>; 3729 3730 video-decoder { 3731 compatible = "venus-decoder"; 3732 }; 3733 3734 video-encoder { 3735 compatible = "venus-encoder"; 3736 }; 3737 3738 video-firmware { 3739 iommus = <&apps_smmu 0x21a2 0x0>; 3740 }; 3741 3742 venus_opp_table: opp-table { 3743 compatible = "operating-points-v2"; 3744 3745 opp-133330000 { 3746 opp-hz = /bits/ 64 <133330000>; 3747 required-opps = <&rpmhpd_opp_low_svs>; 3748 }; 3749 3750 opp-240000000 { 3751 opp-hz = /bits/ 64 <240000000>; 3752 required-opps = <&rpmhpd_opp_svs>; 3753 }; 3754 3755 opp-335000000 { 3756 opp-hz = /bits/ 64 <335000000>; 3757 required-opps = <&rpmhpd_opp_svs_l1>; 3758 }; 3759 3760 opp-424000000 { 3761 opp-hz = /bits/ 64 <424000000>; 3762 required-opps = <&rpmhpd_opp_nom>; 3763 }; 3764 3765 opp-460000048 { 3766 opp-hz = /bits/ 64 <460000048>; 3767 required-opps = <&rpmhpd_opp_turbo>; 3768 }; 3769 }; 3770 }; 3771 3772 videocc: clock-controller@aaf0000 { 3773 compatible = "qcom,sc7280-videocc"; 3774 reg = <0 0x0aaf0000 0 0x10000>; 3775 clocks = <&rpmhcc RPMH_CXO_CLK>, 3776 <&rpmhcc RPMH_CXO_CLK_A>; 3777 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3778 #clock-cells = <1>; 3779 #reset-cells = <1>; 3780 #power-domain-cells = <1>; 3781 }; 3782 3783 camcc: clock-controller@ad00000 { 3784 compatible = "qcom,sc7280-camcc"; 3785 reg = <0 0x0ad00000 0 0x10000>; 3786 clocks = <&rpmhcc RPMH_CXO_CLK>, 3787 <&rpmhcc RPMH_CXO_CLK_A>, 3788 <&sleep_clk>; 3789 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3790 #clock-cells = <1>; 3791 #reset-cells = <1>; 3792 #power-domain-cells = <1>; 3793 }; 3794 3795 dispcc: clock-controller@af00000 { 3796 compatible = "qcom,sc7280-dispcc"; 3797 reg = <0 0x0af00000 0 0x20000>; 3798 clocks = <&rpmhcc RPMH_CXO_CLK>, 3799 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3800 <&mdss_dsi_phy 0>, 3801 <&mdss_dsi_phy 1>, 3802 <&dp_phy 0>, 3803 <&dp_phy 1>, 3804 <&mdss_edp_phy 0>, 3805 <&mdss_edp_phy 1>; 3806 clock-names = "bi_tcxo", 3807 "gcc_disp_gpll0_clk", 3808 "dsi0_phy_pll_out_byteclk", 3809 "dsi0_phy_pll_out_dsiclk", 3810 "dp_phy_pll_link_clk", 3811 "dp_phy_pll_vco_div_clk", 3812 "edp_phy_pll_link_clk", 3813 "edp_phy_pll_vco_div_clk"; 3814 #clock-cells = <1>; 3815 #reset-cells = <1>; 3816 #power-domain-cells = <1>; 3817 }; 3818 3819 mdss: display-subsystem@ae00000 { 3820 compatible = "qcom,sc7280-mdss"; 3821 reg = <0 0x0ae00000 0 0x1000>; 3822 reg-names = "mdss"; 3823 3824 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3825 3826 clocks = <&gcc GCC_DISP_AHB_CLK>, 3827 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3828 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3829 clock-names = "iface", 3830 "ahb", 3831 "core"; 3832 3833 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3834 interrupt-controller; 3835 #interrupt-cells = <1>; 3836 3837 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3838 interconnect-names = "mdp0-mem"; 3839 3840 iommus = <&apps_smmu 0x900 0x402>; 3841 3842 #address-cells = <2>; 3843 #size-cells = <2>; 3844 ranges; 3845 3846 status = "disabled"; 3847 3848 mdss_mdp: display-controller@ae01000 { 3849 compatible = "qcom,sc7280-dpu"; 3850 reg = <0 0x0ae01000 0 0x8f030>, 3851 <0 0x0aeb0000 0 0x2008>; 3852 reg-names = "mdp", "vbif"; 3853 3854 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3855 <&gcc GCC_DISP_SF_AXI_CLK>, 3856 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3857 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3858 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3859 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3860 clock-names = "bus", 3861 "nrt_bus", 3862 "iface", 3863 "lut", 3864 "core", 3865 "vsync"; 3866 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3867 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3868 assigned-clock-rates = <19200000>, 3869 <19200000>; 3870 operating-points-v2 = <&mdp_opp_table>; 3871 power-domains = <&rpmhpd SC7280_CX>; 3872 3873 interrupt-parent = <&mdss>; 3874 interrupts = <0>; 3875 3876 ports { 3877 #address-cells = <1>; 3878 #size-cells = <0>; 3879 3880 port@0 { 3881 reg = <0>; 3882 dpu_intf1_out: endpoint { 3883 remote-endpoint = <&mdss_dsi0_in>; 3884 }; 3885 }; 3886 3887 port@1 { 3888 reg = <1>; 3889 dpu_intf5_out: endpoint { 3890 remote-endpoint = <&edp_in>; 3891 }; 3892 }; 3893 3894 port@2 { 3895 reg = <2>; 3896 dpu_intf0_out: endpoint { 3897 remote-endpoint = <&dp_in>; 3898 }; 3899 }; 3900 }; 3901 3902 mdp_opp_table: opp-table { 3903 compatible = "operating-points-v2"; 3904 3905 opp-200000000 { 3906 opp-hz = /bits/ 64 <200000000>; 3907 required-opps = <&rpmhpd_opp_low_svs>; 3908 }; 3909 3910 opp-300000000 { 3911 opp-hz = /bits/ 64 <300000000>; 3912 required-opps = <&rpmhpd_opp_svs>; 3913 }; 3914 3915 opp-380000000 { 3916 opp-hz = /bits/ 64 <380000000>; 3917 required-opps = <&rpmhpd_opp_svs_l1>; 3918 }; 3919 3920 opp-506666667 { 3921 opp-hz = /bits/ 64 <506666667>; 3922 required-opps = <&rpmhpd_opp_nom>; 3923 }; 3924 }; 3925 }; 3926 3927 mdss_dsi: dsi@ae94000 { 3928 compatible = "qcom,sc7280-dsi-ctrl", 3929 "qcom,mdss-dsi-ctrl"; 3930 reg = <0 0x0ae94000 0 0x400>; 3931 reg-names = "dsi_ctrl"; 3932 3933 interrupt-parent = <&mdss>; 3934 interrupts = <4>; 3935 3936 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3937 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3938 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3939 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3940 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3941 <&gcc GCC_DISP_HF_AXI_CLK>; 3942 clock-names = "byte", 3943 "byte_intf", 3944 "pixel", 3945 "core", 3946 "iface", 3947 "bus"; 3948 3949 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3950 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3951 3952 operating-points-v2 = <&dsi_opp_table>; 3953 power-domains = <&rpmhpd SC7280_CX>; 3954 3955 phys = <&mdss_dsi_phy>; 3956 3957 #address-cells = <1>; 3958 #size-cells = <0>; 3959 3960 status = "disabled"; 3961 3962 ports { 3963 #address-cells = <1>; 3964 #size-cells = <0>; 3965 3966 port@0 { 3967 reg = <0>; 3968 mdss_dsi0_in: endpoint { 3969 remote-endpoint = <&dpu_intf1_out>; 3970 }; 3971 }; 3972 3973 port@1 { 3974 reg = <1>; 3975 mdss_dsi0_out: endpoint { 3976 }; 3977 }; 3978 }; 3979 3980 dsi_opp_table: opp-table { 3981 compatible = "operating-points-v2"; 3982 3983 opp-187500000 { 3984 opp-hz = /bits/ 64 <187500000>; 3985 required-opps = <&rpmhpd_opp_low_svs>; 3986 }; 3987 3988 opp-300000000 { 3989 opp-hz = /bits/ 64 <300000000>; 3990 required-opps = <&rpmhpd_opp_svs>; 3991 }; 3992 3993 opp-358000000 { 3994 opp-hz = /bits/ 64 <358000000>; 3995 required-opps = <&rpmhpd_opp_svs_l1>; 3996 }; 3997 }; 3998 }; 3999 4000 mdss_dsi_phy: phy@ae94400 { 4001 compatible = "qcom,sc7280-dsi-phy-7nm"; 4002 reg = <0 0x0ae94400 0 0x200>, 4003 <0 0x0ae94600 0 0x280>, 4004 <0 0x0ae94900 0 0x280>; 4005 reg-names = "dsi_phy", 4006 "dsi_phy_lane", 4007 "dsi_pll"; 4008 4009 #clock-cells = <1>; 4010 #phy-cells = <0>; 4011 4012 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4013 <&rpmhcc RPMH_CXO_CLK>; 4014 clock-names = "iface", "ref"; 4015 4016 status = "disabled"; 4017 }; 4018 4019 mdss_edp: edp@aea0000 { 4020 compatible = "qcom,sc7280-edp"; 4021 pinctrl-names = "default"; 4022 pinctrl-0 = <&edp_hot_plug_det>; 4023 4024 reg = <0 0x0aea0000 0 0x200>, 4025 <0 0x0aea0200 0 0x200>, 4026 <0 0x0aea0400 0 0xc00>, 4027 <0 0x0aea1000 0 0x400>; 4028 4029 interrupt-parent = <&mdss>; 4030 interrupts = <14>; 4031 4032 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4033 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4034 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4035 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4036 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4037 clock-names = "core_iface", 4038 "core_aux", 4039 "ctrl_link", 4040 "ctrl_link_iface", 4041 "stream_pixel"; 4042 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4043 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4044 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4045 4046 phys = <&mdss_edp_phy>; 4047 phy-names = "dp"; 4048 4049 operating-points-v2 = <&edp_opp_table>; 4050 power-domains = <&rpmhpd SC7280_CX>; 4051 4052 status = "disabled"; 4053 4054 ports { 4055 #address-cells = <1>; 4056 #size-cells = <0>; 4057 4058 port@0 { 4059 reg = <0>; 4060 edp_in: endpoint { 4061 remote-endpoint = <&dpu_intf5_out>; 4062 }; 4063 }; 4064 4065 port@1 { 4066 reg = <1>; 4067 mdss_edp_out: endpoint { }; 4068 }; 4069 }; 4070 4071 edp_opp_table: opp-table { 4072 compatible = "operating-points-v2"; 4073 4074 opp-160000000 { 4075 opp-hz = /bits/ 64 <160000000>; 4076 required-opps = <&rpmhpd_opp_low_svs>; 4077 }; 4078 4079 opp-270000000 { 4080 opp-hz = /bits/ 64 <270000000>; 4081 required-opps = <&rpmhpd_opp_svs>; 4082 }; 4083 4084 opp-540000000 { 4085 opp-hz = /bits/ 64 <540000000>; 4086 required-opps = <&rpmhpd_opp_nom>; 4087 }; 4088 4089 opp-810000000 { 4090 opp-hz = /bits/ 64 <810000000>; 4091 required-opps = <&rpmhpd_opp_nom>; 4092 }; 4093 }; 4094 }; 4095 4096 mdss_edp_phy: phy@aec2a00 { 4097 compatible = "qcom,sc7280-edp-phy"; 4098 4099 reg = <0 0x0aec2a00 0 0x19c>, 4100 <0 0x0aec2200 0 0xa0>, 4101 <0 0x0aec2600 0 0xa0>, 4102 <0 0x0aec2000 0 0x1c0>; 4103 4104 clocks = <&rpmhcc RPMH_CXO_CLK>, 4105 <&gcc GCC_EDP_CLKREF_EN>; 4106 clock-names = "aux", 4107 "cfg_ahb"; 4108 4109 #clock-cells = <1>; 4110 #phy-cells = <0>; 4111 4112 status = "disabled"; 4113 }; 4114 4115 mdss_dp: displayport-controller@ae90000 { 4116 compatible = "qcom,sc7280-dp"; 4117 4118 reg = <0 0x0ae90000 0 0x200>, 4119 <0 0x0ae90200 0 0x200>, 4120 <0 0x0ae90400 0 0xc00>, 4121 <0 0x0ae91000 0 0x400>, 4122 <0 0x0ae91400 0 0x400>; 4123 4124 interrupt-parent = <&mdss>; 4125 interrupts = <12>; 4126 4127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4128 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4129 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4130 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4131 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4132 clock-names = "core_iface", 4133 "core_aux", 4134 "ctrl_link", 4135 "ctrl_link_iface", 4136 "stream_pixel"; 4137 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4138 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4139 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4140 phys = <&dp_phy>; 4141 phy-names = "dp"; 4142 4143 operating-points-v2 = <&dp_opp_table>; 4144 power-domains = <&rpmhpd SC7280_CX>; 4145 4146 #sound-dai-cells = <0>; 4147 4148 status = "disabled"; 4149 4150 ports { 4151 #address-cells = <1>; 4152 #size-cells = <0>; 4153 4154 port@0 { 4155 reg = <0>; 4156 dp_in: endpoint { 4157 remote-endpoint = <&dpu_intf0_out>; 4158 }; 4159 }; 4160 4161 port@1 { 4162 reg = <1>; 4163 mdss_dp_out: endpoint { }; 4164 }; 4165 }; 4166 4167 dp_opp_table: opp-table { 4168 compatible = "operating-points-v2"; 4169 4170 opp-160000000 { 4171 opp-hz = /bits/ 64 <160000000>; 4172 required-opps = <&rpmhpd_opp_low_svs>; 4173 }; 4174 4175 opp-270000000 { 4176 opp-hz = /bits/ 64 <270000000>; 4177 required-opps = <&rpmhpd_opp_svs>; 4178 }; 4179 4180 opp-540000000 { 4181 opp-hz = /bits/ 64 <540000000>; 4182 required-opps = <&rpmhpd_opp_svs_l1>; 4183 }; 4184 4185 opp-810000000 { 4186 opp-hz = /bits/ 64 <810000000>; 4187 required-opps = <&rpmhpd_opp_nom>; 4188 }; 4189 }; 4190 }; 4191 }; 4192 4193 pdc: interrupt-controller@b220000 { 4194 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4195 reg = <0 0x0b220000 0 0x30000>; 4196 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4197 <55 306 4>, <59 312 3>, <62 374 2>, 4198 <64 434 2>, <66 438 3>, <69 86 1>, 4199 <70 520 54>, <124 609 31>, <155 63 1>, 4200 <156 716 12>; 4201 #interrupt-cells = <2>; 4202 interrupt-parent = <&intc>; 4203 interrupt-controller; 4204 }; 4205 4206 pdc_reset: reset-controller@b5e0000 { 4207 compatible = "qcom,sc7280-pdc-global"; 4208 reg = <0 0x0b5e0000 0 0x20000>; 4209 #reset-cells = <1>; 4210 status = "reserved"; /* Owned by firmware */ 4211 }; 4212 4213 tsens0: thermal-sensor@c263000 { 4214 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4215 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4216 <0 0x0c222000 0 0x1ff>; /* SROT */ 4217 #qcom,sensors = <15>; 4218 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4220 interrupt-names = "uplow","critical"; 4221 #thermal-sensor-cells = <1>; 4222 }; 4223 4224 tsens1: thermal-sensor@c265000 { 4225 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4226 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4227 <0 0x0c223000 0 0x1ff>; /* SROT */ 4228 #qcom,sensors = <12>; 4229 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4231 interrupt-names = "uplow","critical"; 4232 #thermal-sensor-cells = <1>; 4233 }; 4234 4235 aoss_reset: reset-controller@c2a0000 { 4236 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4237 reg = <0 0x0c2a0000 0 0x31000>; 4238 #reset-cells = <1>; 4239 }; 4240 4241 aoss_qmp: power-management@c300000 { 4242 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4243 reg = <0 0x0c300000 0 0x400>; 4244 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4245 IPCC_MPROC_SIGNAL_GLINK_QMP 4246 IRQ_TYPE_EDGE_RISING>; 4247 mboxes = <&ipcc IPCC_CLIENT_AOP 4248 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4249 4250 #clock-cells = <0>; 4251 }; 4252 4253 sram@c3f0000 { 4254 compatible = "qcom,rpmh-stats"; 4255 reg = <0 0x0c3f0000 0 0x400>; 4256 }; 4257 4258 spmi_bus: spmi@c440000 { 4259 compatible = "qcom,spmi-pmic-arb"; 4260 reg = <0 0x0c440000 0 0x1100>, 4261 <0 0x0c600000 0 0x2000000>, 4262 <0 0x0e600000 0 0x100000>, 4263 <0 0x0e700000 0 0xa0000>, 4264 <0 0x0c40a000 0 0x26000>; 4265 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4266 interrupt-names = "periph_irq"; 4267 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4268 qcom,ee = <0>; 4269 qcom,channel = <0>; 4270 #address-cells = <2>; 4271 #size-cells = <0>; 4272 interrupt-controller; 4273 #interrupt-cells = <4>; 4274 }; 4275 4276 tlmm: pinctrl@f100000 { 4277 compatible = "qcom,sc7280-pinctrl"; 4278 reg = <0 0x0f100000 0 0x300000>; 4279 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4280 gpio-controller; 4281 #gpio-cells = <2>; 4282 interrupt-controller; 4283 #interrupt-cells = <2>; 4284 gpio-ranges = <&tlmm 0 0 175>; 4285 wakeup-parent = <&pdc>; 4286 4287 dp_hot_plug_det: dp-hot-plug-det-state { 4288 pins = "gpio47"; 4289 function = "dp_hot"; 4290 }; 4291 4292 edp_hot_plug_det: edp-hot-plug-det-state { 4293 pins = "gpio60"; 4294 function = "edp_hot"; 4295 }; 4296 4297 mi2s0_data0: mi2s0-data0-state { 4298 pins = "gpio98"; 4299 function = "mi2s0_data0"; 4300 }; 4301 4302 mi2s0_data1: mi2s0-data1-state { 4303 pins = "gpio99"; 4304 function = "mi2s0_data1"; 4305 }; 4306 4307 mi2s0_mclk: mi2s0-mclk-state { 4308 pins = "gpio96"; 4309 function = "pri_mi2s"; 4310 }; 4311 4312 mi2s0_sclk: mi2s0-sclk-state { 4313 pins = "gpio97"; 4314 function = "mi2s0_sck"; 4315 }; 4316 4317 mi2s0_ws: mi2s0-ws-state { 4318 pins = "gpio100"; 4319 function = "mi2s0_ws"; 4320 }; 4321 4322 mi2s1_data0: mi2s1-data0-state { 4323 pins = "gpio107"; 4324 function = "mi2s1_data0"; 4325 }; 4326 4327 mi2s1_sclk: mi2s1-sclk-state { 4328 pins = "gpio106"; 4329 function = "mi2s1_sck"; 4330 }; 4331 4332 mi2s1_ws: mi2s1-ws-state { 4333 pins = "gpio108"; 4334 function = "mi2s1_ws"; 4335 }; 4336 4337 pcie1_clkreq_n: pcie1-clkreq-n-state { 4338 pins = "gpio79"; 4339 function = "pcie1_clkreqn"; 4340 }; 4341 4342 qspi_clk: qspi-clk-state { 4343 pins = "gpio14"; 4344 function = "qspi_clk"; 4345 }; 4346 4347 qspi_cs0: qspi-cs0-state { 4348 pins = "gpio15"; 4349 function = "qspi_cs"; 4350 }; 4351 4352 qspi_cs1: qspi-cs1-state { 4353 pins = "gpio19"; 4354 function = "qspi_cs"; 4355 }; 4356 4357 qspi_data0: qspi-data0-state { 4358 pins = "gpio12"; 4359 function = "qspi_data"; 4360 }; 4361 4362 qspi_data1: qspi-data1-state { 4363 pins = "gpio13"; 4364 function = "qspi_data"; 4365 }; 4366 4367 qspi_data23: qspi-data23-state { 4368 pins = "gpio16", "gpio17"; 4369 function = "qspi_data"; 4370 }; 4371 4372 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4373 pins = "gpio0", "gpio1"; 4374 function = "qup00"; 4375 }; 4376 4377 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4378 pins = "gpio4", "gpio5"; 4379 function = "qup01"; 4380 }; 4381 4382 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4383 pins = "gpio8", "gpio9"; 4384 function = "qup02"; 4385 }; 4386 4387 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4388 pins = "gpio12", "gpio13"; 4389 function = "qup03"; 4390 }; 4391 4392 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4393 pins = "gpio16", "gpio17"; 4394 function = "qup04"; 4395 }; 4396 4397 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4398 pins = "gpio20", "gpio21"; 4399 function = "qup05"; 4400 }; 4401 4402 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4403 pins = "gpio24", "gpio25"; 4404 function = "qup06"; 4405 }; 4406 4407 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4408 pins = "gpio28", "gpio29"; 4409 function = "qup07"; 4410 }; 4411 4412 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4413 pins = "gpio32", "gpio33"; 4414 function = "qup10"; 4415 }; 4416 4417 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4418 pins = "gpio36", "gpio37"; 4419 function = "qup11"; 4420 }; 4421 4422 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4423 pins = "gpio40", "gpio41"; 4424 function = "qup12"; 4425 }; 4426 4427 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4428 pins = "gpio44", "gpio45"; 4429 function = "qup13"; 4430 }; 4431 4432 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4433 pins = "gpio48", "gpio49"; 4434 function = "qup14"; 4435 }; 4436 4437 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4438 pins = "gpio52", "gpio53"; 4439 function = "qup15"; 4440 }; 4441 4442 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4443 pins = "gpio56", "gpio57"; 4444 function = "qup16"; 4445 }; 4446 4447 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4448 pins = "gpio60", "gpio61"; 4449 function = "qup17"; 4450 }; 4451 4452 qup_spi0_data_clk: qup-spi0-data-clk-state { 4453 pins = "gpio0", "gpio1", "gpio2"; 4454 function = "qup00"; 4455 }; 4456 4457 qup_spi0_cs: qup-spi0-cs-state { 4458 pins = "gpio3"; 4459 function = "qup00"; 4460 }; 4461 4462 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4463 pins = "gpio3"; 4464 function = "gpio"; 4465 }; 4466 4467 qup_spi1_data_clk: qup-spi1-data-clk-state { 4468 pins = "gpio4", "gpio5", "gpio6"; 4469 function = "qup01"; 4470 }; 4471 4472 qup_spi1_cs: qup-spi1-cs-state { 4473 pins = "gpio7"; 4474 function = "qup01"; 4475 }; 4476 4477 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4478 pins = "gpio7"; 4479 function = "gpio"; 4480 }; 4481 4482 qup_spi2_data_clk: qup-spi2-data-clk-state { 4483 pins = "gpio8", "gpio9", "gpio10"; 4484 function = "qup02"; 4485 }; 4486 4487 qup_spi2_cs: qup-spi2-cs-state { 4488 pins = "gpio11"; 4489 function = "qup02"; 4490 }; 4491 4492 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4493 pins = "gpio11"; 4494 function = "gpio"; 4495 }; 4496 4497 qup_spi3_data_clk: qup-spi3-data-clk-state { 4498 pins = "gpio12", "gpio13", "gpio14"; 4499 function = "qup03"; 4500 }; 4501 4502 qup_spi3_cs: qup-spi3-cs-state { 4503 pins = "gpio15"; 4504 function = "qup03"; 4505 }; 4506 4507 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4508 pins = "gpio15"; 4509 function = "gpio"; 4510 }; 4511 4512 qup_spi4_data_clk: qup-spi4-data-clk-state { 4513 pins = "gpio16", "gpio17", "gpio18"; 4514 function = "qup04"; 4515 }; 4516 4517 qup_spi4_cs: qup-spi4-cs-state { 4518 pins = "gpio19"; 4519 function = "qup04"; 4520 }; 4521 4522 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4523 pins = "gpio19"; 4524 function = "gpio"; 4525 }; 4526 4527 qup_spi5_data_clk: qup-spi5-data-clk-state { 4528 pins = "gpio20", "gpio21", "gpio22"; 4529 function = "qup05"; 4530 }; 4531 4532 qup_spi5_cs: qup-spi5-cs-state { 4533 pins = "gpio23"; 4534 function = "qup05"; 4535 }; 4536 4537 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4538 pins = "gpio23"; 4539 function = "gpio"; 4540 }; 4541 4542 qup_spi6_data_clk: qup-spi6-data-clk-state { 4543 pins = "gpio24", "gpio25", "gpio26"; 4544 function = "qup06"; 4545 }; 4546 4547 qup_spi6_cs: qup-spi6-cs-state { 4548 pins = "gpio27"; 4549 function = "qup06"; 4550 }; 4551 4552 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4553 pins = "gpio27"; 4554 function = "gpio"; 4555 }; 4556 4557 qup_spi7_data_clk: qup-spi7-data-clk-state { 4558 pins = "gpio28", "gpio29", "gpio30"; 4559 function = "qup07"; 4560 }; 4561 4562 qup_spi7_cs: qup-spi7-cs-state { 4563 pins = "gpio31"; 4564 function = "qup07"; 4565 }; 4566 4567 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4568 pins = "gpio31"; 4569 function = "gpio"; 4570 }; 4571 4572 qup_spi8_data_clk: qup-spi8-data-clk-state { 4573 pins = "gpio32", "gpio33", "gpio34"; 4574 function = "qup10"; 4575 }; 4576 4577 qup_spi8_cs: qup-spi8-cs-state { 4578 pins = "gpio35"; 4579 function = "qup10"; 4580 }; 4581 4582 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4583 pins = "gpio35"; 4584 function = "gpio"; 4585 }; 4586 4587 qup_spi9_data_clk: qup-spi9-data-clk-state { 4588 pins = "gpio36", "gpio37", "gpio38"; 4589 function = "qup11"; 4590 }; 4591 4592 qup_spi9_cs: qup-spi9-cs-state { 4593 pins = "gpio39"; 4594 function = "qup11"; 4595 }; 4596 4597 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4598 pins = "gpio39"; 4599 function = "gpio"; 4600 }; 4601 4602 qup_spi10_data_clk: qup-spi10-data-clk-state { 4603 pins = "gpio40", "gpio41", "gpio42"; 4604 function = "qup12"; 4605 }; 4606 4607 qup_spi10_cs: qup-spi10-cs-state { 4608 pins = "gpio43"; 4609 function = "qup12"; 4610 }; 4611 4612 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4613 pins = "gpio43"; 4614 function = "gpio"; 4615 }; 4616 4617 qup_spi11_data_clk: qup-spi11-data-clk-state { 4618 pins = "gpio44", "gpio45", "gpio46"; 4619 function = "qup13"; 4620 }; 4621 4622 qup_spi11_cs: qup-spi11-cs-state { 4623 pins = "gpio47"; 4624 function = "qup13"; 4625 }; 4626 4627 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4628 pins = "gpio47"; 4629 function = "gpio"; 4630 }; 4631 4632 qup_spi12_data_clk: qup-spi12-data-clk-state { 4633 pins = "gpio48", "gpio49", "gpio50"; 4634 function = "qup14"; 4635 }; 4636 4637 qup_spi12_cs: qup-spi12-cs-state { 4638 pins = "gpio51"; 4639 function = "qup14"; 4640 }; 4641 4642 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4643 pins = "gpio51"; 4644 function = "gpio"; 4645 }; 4646 4647 qup_spi13_data_clk: qup-spi13-data-clk-state { 4648 pins = "gpio52", "gpio53", "gpio54"; 4649 function = "qup15"; 4650 }; 4651 4652 qup_spi13_cs: qup-spi13-cs-state { 4653 pins = "gpio55"; 4654 function = "qup15"; 4655 }; 4656 4657 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4658 pins = "gpio55"; 4659 function = "gpio"; 4660 }; 4661 4662 qup_spi14_data_clk: qup-spi14-data-clk-state { 4663 pins = "gpio56", "gpio57", "gpio58"; 4664 function = "qup16"; 4665 }; 4666 4667 qup_spi14_cs: qup-spi14-cs-state { 4668 pins = "gpio59"; 4669 function = "qup16"; 4670 }; 4671 4672 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4673 pins = "gpio59"; 4674 function = "gpio"; 4675 }; 4676 4677 qup_spi15_data_clk: qup-spi15-data-clk-state { 4678 pins = "gpio60", "gpio61", "gpio62"; 4679 function = "qup17"; 4680 }; 4681 4682 qup_spi15_cs: qup-spi15-cs-state { 4683 pins = "gpio63"; 4684 function = "qup17"; 4685 }; 4686 4687 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4688 pins = "gpio63"; 4689 function = "gpio"; 4690 }; 4691 4692 qup_uart0_cts: qup-uart0-cts-state { 4693 pins = "gpio0"; 4694 function = "qup00"; 4695 }; 4696 4697 qup_uart0_rts: qup-uart0-rts-state { 4698 pins = "gpio1"; 4699 function = "qup00"; 4700 }; 4701 4702 qup_uart0_tx: qup-uart0-tx-state { 4703 pins = "gpio2"; 4704 function = "qup00"; 4705 }; 4706 4707 qup_uart0_rx: qup-uart0-rx-state { 4708 pins = "gpio3"; 4709 function = "qup00"; 4710 }; 4711 4712 qup_uart1_cts: qup-uart1-cts-state { 4713 pins = "gpio4"; 4714 function = "qup01"; 4715 }; 4716 4717 qup_uart1_rts: qup-uart1-rts-state { 4718 pins = "gpio5"; 4719 function = "qup01"; 4720 }; 4721 4722 qup_uart1_tx: qup-uart1-tx-state { 4723 pins = "gpio6"; 4724 function = "qup01"; 4725 }; 4726 4727 qup_uart1_rx: qup-uart1-rx-state { 4728 pins = "gpio7"; 4729 function = "qup01"; 4730 }; 4731 4732 qup_uart2_cts: qup-uart2-cts-state { 4733 pins = "gpio8"; 4734 function = "qup02"; 4735 }; 4736 4737 qup_uart2_rts: qup-uart2-rts-state { 4738 pins = "gpio9"; 4739 function = "qup02"; 4740 }; 4741 4742 qup_uart2_tx: qup-uart2-tx-state { 4743 pins = "gpio10"; 4744 function = "qup02"; 4745 }; 4746 4747 qup_uart2_rx: qup-uart2-rx-state { 4748 pins = "gpio11"; 4749 function = "qup02"; 4750 }; 4751 4752 qup_uart3_cts: qup-uart3-cts-state { 4753 pins = "gpio12"; 4754 function = "qup03"; 4755 }; 4756 4757 qup_uart3_rts: qup-uart3-rts-state { 4758 pins = "gpio13"; 4759 function = "qup03"; 4760 }; 4761 4762 qup_uart3_tx: qup-uart3-tx-state { 4763 pins = "gpio14"; 4764 function = "qup03"; 4765 }; 4766 4767 qup_uart3_rx: qup-uart3-rx-state { 4768 pins = "gpio15"; 4769 function = "qup03"; 4770 }; 4771 4772 qup_uart4_cts: qup-uart4-cts-state { 4773 pins = "gpio16"; 4774 function = "qup04"; 4775 }; 4776 4777 qup_uart4_rts: qup-uart4-rts-state { 4778 pins = "gpio17"; 4779 function = "qup04"; 4780 }; 4781 4782 qup_uart4_tx: qup-uart4-tx-state { 4783 pins = "gpio18"; 4784 function = "qup04"; 4785 }; 4786 4787 qup_uart4_rx: qup-uart4-rx-state { 4788 pins = "gpio19"; 4789 function = "qup04"; 4790 }; 4791 4792 qup_uart5_cts: qup-uart5-cts-state { 4793 pins = "gpio20"; 4794 function = "qup05"; 4795 }; 4796 4797 qup_uart5_rts: qup-uart5-rts-state { 4798 pins = "gpio21"; 4799 function = "qup05"; 4800 }; 4801 4802 qup_uart5_tx: qup-uart5-tx-state { 4803 pins = "gpio22"; 4804 function = "qup05"; 4805 }; 4806 4807 qup_uart5_rx: qup-uart5-rx-state { 4808 pins = "gpio23"; 4809 function = "qup05"; 4810 }; 4811 4812 qup_uart6_cts: qup-uart6-cts-state { 4813 pins = "gpio24"; 4814 function = "qup06"; 4815 }; 4816 4817 qup_uart6_rts: qup-uart6-rts-state { 4818 pins = "gpio25"; 4819 function = "qup06"; 4820 }; 4821 4822 qup_uart6_tx: qup-uart6-tx-state { 4823 pins = "gpio26"; 4824 function = "qup06"; 4825 }; 4826 4827 qup_uart6_rx: qup-uart6-rx-state { 4828 pins = "gpio27"; 4829 function = "qup06"; 4830 }; 4831 4832 qup_uart7_cts: qup-uart7-cts-state { 4833 pins = "gpio28"; 4834 function = "qup07"; 4835 }; 4836 4837 qup_uart7_rts: qup-uart7-rts-state { 4838 pins = "gpio29"; 4839 function = "qup07"; 4840 }; 4841 4842 qup_uart7_tx: qup-uart7-tx-state { 4843 pins = "gpio30"; 4844 function = "qup07"; 4845 }; 4846 4847 qup_uart7_rx: qup-uart7-rx-state { 4848 pins = "gpio31"; 4849 function = "qup07"; 4850 }; 4851 4852 qup_uart8_cts: qup-uart8-cts-state { 4853 pins = "gpio32"; 4854 function = "qup10"; 4855 }; 4856 4857 qup_uart8_rts: qup-uart8-rts-state { 4858 pins = "gpio33"; 4859 function = "qup10"; 4860 }; 4861 4862 qup_uart8_tx: qup-uart8-tx-state { 4863 pins = "gpio34"; 4864 function = "qup10"; 4865 }; 4866 4867 qup_uart8_rx: qup-uart8-rx-state { 4868 pins = "gpio35"; 4869 function = "qup10"; 4870 }; 4871 4872 qup_uart9_cts: qup-uart9-cts-state { 4873 pins = "gpio36"; 4874 function = "qup11"; 4875 }; 4876 4877 qup_uart9_rts: qup-uart9-rts-state { 4878 pins = "gpio37"; 4879 function = "qup11"; 4880 }; 4881 4882 qup_uart9_tx: qup-uart9-tx-state { 4883 pins = "gpio38"; 4884 function = "qup11"; 4885 }; 4886 4887 qup_uart9_rx: qup-uart9-rx-state { 4888 pins = "gpio39"; 4889 function = "qup11"; 4890 }; 4891 4892 qup_uart10_cts: qup-uart10-cts-state { 4893 pins = "gpio40"; 4894 function = "qup12"; 4895 }; 4896 4897 qup_uart10_rts: qup-uart10-rts-state { 4898 pins = "gpio41"; 4899 function = "qup12"; 4900 }; 4901 4902 qup_uart10_tx: qup-uart10-tx-state { 4903 pins = "gpio42"; 4904 function = "qup12"; 4905 }; 4906 4907 qup_uart10_rx: qup-uart10-rx-state { 4908 pins = "gpio43"; 4909 function = "qup12"; 4910 }; 4911 4912 qup_uart11_cts: qup-uart11-cts-state { 4913 pins = "gpio44"; 4914 function = "qup13"; 4915 }; 4916 4917 qup_uart11_rts: qup-uart11-rts-state { 4918 pins = "gpio45"; 4919 function = "qup13"; 4920 }; 4921 4922 qup_uart11_tx: qup-uart11-tx-state { 4923 pins = "gpio46"; 4924 function = "qup13"; 4925 }; 4926 4927 qup_uart11_rx: qup-uart11-rx-state { 4928 pins = "gpio47"; 4929 function = "qup13"; 4930 }; 4931 4932 qup_uart12_cts: qup-uart12-cts-state { 4933 pins = "gpio48"; 4934 function = "qup14"; 4935 }; 4936 4937 qup_uart12_rts: qup-uart12-rts-state { 4938 pins = "gpio49"; 4939 function = "qup14"; 4940 }; 4941 4942 qup_uart12_tx: qup-uart12-tx-state { 4943 pins = "gpio50"; 4944 function = "qup14"; 4945 }; 4946 4947 qup_uart12_rx: qup-uart12-rx-state { 4948 pins = "gpio51"; 4949 function = "qup14"; 4950 }; 4951 4952 qup_uart13_cts: qup-uart13-cts-state { 4953 pins = "gpio52"; 4954 function = "qup15"; 4955 }; 4956 4957 qup_uart13_rts: qup-uart13-rts-state { 4958 pins = "gpio53"; 4959 function = "qup15"; 4960 }; 4961 4962 qup_uart13_tx: qup-uart13-tx-state { 4963 pins = "gpio54"; 4964 function = "qup15"; 4965 }; 4966 4967 qup_uart13_rx: qup-uart13-rx-state { 4968 pins = "gpio55"; 4969 function = "qup15"; 4970 }; 4971 4972 qup_uart14_cts: qup-uart14-cts-state { 4973 pins = "gpio56"; 4974 function = "qup16"; 4975 }; 4976 4977 qup_uart14_rts: qup-uart14-rts-state { 4978 pins = "gpio57"; 4979 function = "qup16"; 4980 }; 4981 4982 qup_uart14_tx: qup-uart14-tx-state { 4983 pins = "gpio58"; 4984 function = "qup16"; 4985 }; 4986 4987 qup_uart14_rx: qup-uart14-rx-state { 4988 pins = "gpio59"; 4989 function = "qup16"; 4990 }; 4991 4992 qup_uart15_cts: qup-uart15-cts-state { 4993 pins = "gpio60"; 4994 function = "qup17"; 4995 }; 4996 4997 qup_uart15_rts: qup-uart15-rts-state { 4998 pins = "gpio61"; 4999 function = "qup17"; 5000 }; 5001 5002 qup_uart15_tx: qup-uart15-tx-state { 5003 pins = "gpio62"; 5004 function = "qup17"; 5005 }; 5006 5007 qup_uart15_rx: qup-uart15-rx-state { 5008 pins = "gpio63"; 5009 function = "qup17"; 5010 }; 5011 5012 sdc1_clk: sdc1-clk-state { 5013 pins = "sdc1_clk"; 5014 }; 5015 5016 sdc1_cmd: sdc1-cmd-state { 5017 pins = "sdc1_cmd"; 5018 }; 5019 5020 sdc1_data: sdc1-data-state { 5021 pins = "sdc1_data"; 5022 }; 5023 5024 sdc1_rclk: sdc1-rclk-state { 5025 pins = "sdc1_rclk"; 5026 }; 5027 5028 sdc1_clk_sleep: sdc1-clk-sleep-state { 5029 pins = "sdc1_clk"; 5030 drive-strength = <2>; 5031 bias-bus-hold; 5032 }; 5033 5034 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5035 pins = "sdc1_cmd"; 5036 drive-strength = <2>; 5037 bias-bus-hold; 5038 }; 5039 5040 sdc1_data_sleep: sdc1-data-sleep-state { 5041 pins = "sdc1_data"; 5042 drive-strength = <2>; 5043 bias-bus-hold; 5044 }; 5045 5046 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5047 pins = "sdc1_rclk"; 5048 drive-strength = <2>; 5049 bias-bus-hold; 5050 }; 5051 5052 sdc2_clk: sdc2-clk-state { 5053 pins = "sdc2_clk"; 5054 }; 5055 5056 sdc2_cmd: sdc2-cmd-state { 5057 pins = "sdc2_cmd"; 5058 }; 5059 5060 sdc2_data: sdc2-data-state { 5061 pins = "sdc2_data"; 5062 }; 5063 5064 sdc2_clk_sleep: sdc2-clk-sleep-state { 5065 pins = "sdc2_clk"; 5066 drive-strength = <2>; 5067 bias-bus-hold; 5068 }; 5069 5070 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5071 pins = "sdc2_cmd"; 5072 drive-strength = <2>; 5073 bias-bus-hold; 5074 }; 5075 5076 sdc2_data_sleep: sdc2-data-sleep-state { 5077 pins = "sdc2_data"; 5078 drive-strength = <2>; 5079 bias-bus-hold; 5080 }; 5081 }; 5082 5083 sram@146a5000 { 5084 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5085 reg = <0 0x146a5000 0 0x6000>; 5086 5087 #address-cells = <1>; 5088 #size-cells = <1>; 5089 5090 ranges = <0 0 0x146a5000 0x6000>; 5091 5092 pil-reloc@594c { 5093 compatible = "qcom,pil-reloc-info"; 5094 reg = <0x594c 0xc8>; 5095 }; 5096 }; 5097 5098 apps_smmu: iommu@15000000 { 5099 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5100 reg = <0 0x15000000 0 0x100000>; 5101 #iommu-cells = <2>; 5102 #global-interrupts = <1>; 5103 dma-coherent; 5104 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5185 }; 5186 5187 intc: interrupt-controller@17a00000 { 5188 compatible = "arm,gic-v3"; 5189 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5190 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5191 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5192 #interrupt-cells = <3>; 5193 interrupt-controller; 5194 #address-cells = <2>; 5195 #size-cells = <2>; 5196 ranges; 5197 5198 msi-controller@17a40000 { 5199 compatible = "arm,gic-v3-its"; 5200 reg = <0 0x17a40000 0 0x20000>; 5201 msi-controller; 5202 #msi-cells = <1>; 5203 status = "disabled"; 5204 }; 5205 }; 5206 5207 watchdog: watchdog@17c10000 { 5208 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5209 reg = <0 0x17c10000 0 0x1000>; 5210 clocks = <&sleep_clk>; 5211 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5212 status = "reserved"; /* Owned by Gunyah hyp */ 5213 }; 5214 5215 timer@17c20000 { 5216 #address-cells = <1>; 5217 #size-cells = <1>; 5218 ranges = <0 0 0 0x20000000>; 5219 compatible = "arm,armv7-timer-mem"; 5220 reg = <0 0x17c20000 0 0x1000>; 5221 5222 frame@17c21000 { 5223 frame-number = <0>; 5224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5225 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5226 reg = <0x17c21000 0x1000>, 5227 <0x17c22000 0x1000>; 5228 }; 5229 5230 frame@17c23000 { 5231 frame-number = <1>; 5232 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5233 reg = <0x17c23000 0x1000>; 5234 status = "disabled"; 5235 }; 5236 5237 frame@17c25000 { 5238 frame-number = <2>; 5239 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5240 reg = <0x17c25000 0x1000>; 5241 status = "disabled"; 5242 }; 5243 5244 frame@17c27000 { 5245 frame-number = <3>; 5246 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5247 reg = <0x17c27000 0x1000>; 5248 status = "disabled"; 5249 }; 5250 5251 frame@17c29000 { 5252 frame-number = <4>; 5253 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5254 reg = <0x17c29000 0x1000>; 5255 status = "disabled"; 5256 }; 5257 5258 frame@17c2b000 { 5259 frame-number = <5>; 5260 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5261 reg = <0x17c2b000 0x1000>; 5262 status = "disabled"; 5263 }; 5264 5265 frame@17c2d000 { 5266 frame-number = <6>; 5267 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5268 reg = <0x17c2d000 0x1000>; 5269 status = "disabled"; 5270 }; 5271 }; 5272 5273 apps_rsc: rsc@18200000 { 5274 compatible = "qcom,rpmh-rsc"; 5275 reg = <0 0x18200000 0 0x10000>, 5276 <0 0x18210000 0 0x10000>, 5277 <0 0x18220000 0 0x10000>; 5278 reg-names = "drv-0", "drv-1", "drv-2"; 5279 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5280 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5281 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5282 qcom,tcs-offset = <0xd00>; 5283 qcom,drv-id = <2>; 5284 qcom,tcs-config = <ACTIVE_TCS 2>, 5285 <SLEEP_TCS 3>, 5286 <WAKE_TCS 3>, 5287 <CONTROL_TCS 1>; 5288 5289 apps_bcm_voter: bcm-voter { 5290 compatible = "qcom,bcm-voter"; 5291 }; 5292 5293 rpmhpd: power-controller { 5294 compatible = "qcom,sc7280-rpmhpd"; 5295 #power-domain-cells = <1>; 5296 operating-points-v2 = <&rpmhpd_opp_table>; 5297 5298 rpmhpd_opp_table: opp-table { 5299 compatible = "operating-points-v2"; 5300 5301 rpmhpd_opp_ret: opp1 { 5302 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5303 }; 5304 5305 rpmhpd_opp_low_svs: opp2 { 5306 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5307 }; 5308 5309 rpmhpd_opp_svs: opp3 { 5310 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5311 }; 5312 5313 rpmhpd_opp_svs_l1: opp4 { 5314 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5315 }; 5316 5317 rpmhpd_opp_svs_l2: opp5 { 5318 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5319 }; 5320 5321 rpmhpd_opp_nom: opp6 { 5322 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5323 }; 5324 5325 rpmhpd_opp_nom_l1: opp7 { 5326 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5327 }; 5328 5329 rpmhpd_opp_turbo: opp8 { 5330 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5331 }; 5332 5333 rpmhpd_opp_turbo_l1: opp9 { 5334 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5335 }; 5336 }; 5337 }; 5338 5339 rpmhcc: clock-controller { 5340 compatible = "qcom,sc7280-rpmh-clk"; 5341 clocks = <&xo_board>; 5342 clock-names = "xo"; 5343 #clock-cells = <1>; 5344 }; 5345 }; 5346 5347 epss_l3: interconnect@18590000 { 5348 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5349 reg = <0 0x18590000 0 0x1000>; 5350 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5351 clock-names = "xo", "alternate"; 5352 #interconnect-cells = <1>; 5353 }; 5354 5355 cpufreq_hw: cpufreq@18591000 { 5356 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5357 reg = <0 0x18591000 0 0x1000>, 5358 <0 0x18592000 0 0x1000>, 5359 <0 0x18593000 0 0x1000>; 5360 5361 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5362 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5363 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5364 interrupt-names = "dcvsh-irq-0", 5365 "dcvsh-irq-1", 5366 "dcvsh-irq-2"; 5367 5368 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5369 clock-names = "xo", "alternate"; 5370 #freq-domain-cells = <1>; 5371 #clock-cells = <1>; 5372 }; 5373 }; 5374 5375 thermal_zones: thermal-zones { 5376 cpu0-thermal { 5377 polling-delay-passive = <250>; 5378 polling-delay = <0>; 5379 5380 thermal-sensors = <&tsens0 1>; 5381 5382 trips { 5383 cpu0_alert0: trip-point0 { 5384 temperature = <90000>; 5385 hysteresis = <2000>; 5386 type = "passive"; 5387 }; 5388 5389 cpu0_alert1: trip-point1 { 5390 temperature = <95000>; 5391 hysteresis = <2000>; 5392 type = "passive"; 5393 }; 5394 5395 cpu0_crit: cpu-crit { 5396 temperature = <110000>; 5397 hysteresis = <0>; 5398 type = "critical"; 5399 }; 5400 }; 5401 5402 cooling-maps { 5403 map0 { 5404 trip = <&cpu0_alert0>; 5405 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5407 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5408 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5409 }; 5410 map1 { 5411 trip = <&cpu0_alert1>; 5412 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5413 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5414 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5415 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5416 }; 5417 }; 5418 }; 5419 5420 cpu1-thermal { 5421 polling-delay-passive = <250>; 5422 polling-delay = <0>; 5423 5424 thermal-sensors = <&tsens0 2>; 5425 5426 trips { 5427 cpu1_alert0: trip-point0 { 5428 temperature = <90000>; 5429 hysteresis = <2000>; 5430 type = "passive"; 5431 }; 5432 5433 cpu1_alert1: trip-point1 { 5434 temperature = <95000>; 5435 hysteresis = <2000>; 5436 type = "passive"; 5437 }; 5438 5439 cpu1_crit: cpu-crit { 5440 temperature = <110000>; 5441 hysteresis = <0>; 5442 type = "critical"; 5443 }; 5444 }; 5445 5446 cooling-maps { 5447 map0 { 5448 trip = <&cpu1_alert0>; 5449 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5451 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5452 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5453 }; 5454 map1 { 5455 trip = <&cpu1_alert1>; 5456 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5457 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5458 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5459 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5460 }; 5461 }; 5462 }; 5463 5464 cpu2-thermal { 5465 polling-delay-passive = <250>; 5466 polling-delay = <0>; 5467 5468 thermal-sensors = <&tsens0 3>; 5469 5470 trips { 5471 cpu2_alert0: trip-point0 { 5472 temperature = <90000>; 5473 hysteresis = <2000>; 5474 type = "passive"; 5475 }; 5476 5477 cpu2_alert1: trip-point1 { 5478 temperature = <95000>; 5479 hysteresis = <2000>; 5480 type = "passive"; 5481 }; 5482 5483 cpu2_crit: cpu-crit { 5484 temperature = <110000>; 5485 hysteresis = <0>; 5486 type = "critical"; 5487 }; 5488 }; 5489 5490 cooling-maps { 5491 map0 { 5492 trip = <&cpu2_alert0>; 5493 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5495 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5496 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5497 }; 5498 map1 { 5499 trip = <&cpu2_alert1>; 5500 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5501 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5502 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5503 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5504 }; 5505 }; 5506 }; 5507 5508 cpu3-thermal { 5509 polling-delay-passive = <250>; 5510 polling-delay = <0>; 5511 5512 thermal-sensors = <&tsens0 4>; 5513 5514 trips { 5515 cpu3_alert0: trip-point0 { 5516 temperature = <90000>; 5517 hysteresis = <2000>; 5518 type = "passive"; 5519 }; 5520 5521 cpu3_alert1: trip-point1 { 5522 temperature = <95000>; 5523 hysteresis = <2000>; 5524 type = "passive"; 5525 }; 5526 5527 cpu3_crit: cpu-crit { 5528 temperature = <110000>; 5529 hysteresis = <0>; 5530 type = "critical"; 5531 }; 5532 }; 5533 5534 cooling-maps { 5535 map0 { 5536 trip = <&cpu3_alert0>; 5537 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5539 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5540 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5541 }; 5542 map1 { 5543 trip = <&cpu3_alert1>; 5544 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5545 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5546 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5547 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5548 }; 5549 }; 5550 }; 5551 5552 cpu4-thermal { 5553 polling-delay-passive = <250>; 5554 polling-delay = <0>; 5555 5556 thermal-sensors = <&tsens0 7>; 5557 5558 trips { 5559 cpu4_alert0: trip-point0 { 5560 temperature = <90000>; 5561 hysteresis = <2000>; 5562 type = "passive"; 5563 }; 5564 5565 cpu4_alert1: trip-point1 { 5566 temperature = <95000>; 5567 hysteresis = <2000>; 5568 type = "passive"; 5569 }; 5570 5571 cpu4_crit: cpu-crit { 5572 temperature = <110000>; 5573 hysteresis = <0>; 5574 type = "critical"; 5575 }; 5576 }; 5577 5578 cooling-maps { 5579 map0 { 5580 trip = <&cpu4_alert0>; 5581 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5583 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5584 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5585 }; 5586 map1 { 5587 trip = <&cpu4_alert1>; 5588 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5589 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5590 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5591 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5592 }; 5593 }; 5594 }; 5595 5596 cpu5-thermal { 5597 polling-delay-passive = <250>; 5598 polling-delay = <0>; 5599 5600 thermal-sensors = <&tsens0 8>; 5601 5602 trips { 5603 cpu5_alert0: trip-point0 { 5604 temperature = <90000>; 5605 hysteresis = <2000>; 5606 type = "passive"; 5607 }; 5608 5609 cpu5_alert1: trip-point1 { 5610 temperature = <95000>; 5611 hysteresis = <2000>; 5612 type = "passive"; 5613 }; 5614 5615 cpu5_crit: cpu-crit { 5616 temperature = <110000>; 5617 hysteresis = <0>; 5618 type = "critical"; 5619 }; 5620 }; 5621 5622 cooling-maps { 5623 map0 { 5624 trip = <&cpu5_alert0>; 5625 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5627 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5628 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5629 }; 5630 map1 { 5631 trip = <&cpu5_alert1>; 5632 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5633 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5634 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5635 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5636 }; 5637 }; 5638 }; 5639 5640 cpu6-thermal { 5641 polling-delay-passive = <250>; 5642 polling-delay = <0>; 5643 5644 thermal-sensors = <&tsens0 9>; 5645 5646 trips { 5647 cpu6_alert0: trip-point0 { 5648 temperature = <90000>; 5649 hysteresis = <2000>; 5650 type = "passive"; 5651 }; 5652 5653 cpu6_alert1: trip-point1 { 5654 temperature = <95000>; 5655 hysteresis = <2000>; 5656 type = "passive"; 5657 }; 5658 5659 cpu6_crit: cpu-crit { 5660 temperature = <110000>; 5661 hysteresis = <0>; 5662 type = "critical"; 5663 }; 5664 }; 5665 5666 cooling-maps { 5667 map0 { 5668 trip = <&cpu6_alert0>; 5669 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5671 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5672 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5673 }; 5674 map1 { 5675 trip = <&cpu6_alert1>; 5676 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5677 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5678 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5679 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5680 }; 5681 }; 5682 }; 5683 5684 cpu7-thermal { 5685 polling-delay-passive = <250>; 5686 polling-delay = <0>; 5687 5688 thermal-sensors = <&tsens0 10>; 5689 5690 trips { 5691 cpu7_alert0: trip-point0 { 5692 temperature = <90000>; 5693 hysteresis = <2000>; 5694 type = "passive"; 5695 }; 5696 5697 cpu7_alert1: trip-point1 { 5698 temperature = <95000>; 5699 hysteresis = <2000>; 5700 type = "passive"; 5701 }; 5702 5703 cpu7_crit: cpu-crit { 5704 temperature = <110000>; 5705 hysteresis = <0>; 5706 type = "critical"; 5707 }; 5708 }; 5709 5710 cooling-maps { 5711 map0 { 5712 trip = <&cpu7_alert0>; 5713 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5715 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5716 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5717 }; 5718 map1 { 5719 trip = <&cpu7_alert1>; 5720 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5721 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5722 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5723 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5724 }; 5725 }; 5726 }; 5727 5728 cpu8-thermal { 5729 polling-delay-passive = <250>; 5730 polling-delay = <0>; 5731 5732 thermal-sensors = <&tsens0 11>; 5733 5734 trips { 5735 cpu8_alert0: trip-point0 { 5736 temperature = <90000>; 5737 hysteresis = <2000>; 5738 type = "passive"; 5739 }; 5740 5741 cpu8_alert1: trip-point1 { 5742 temperature = <95000>; 5743 hysteresis = <2000>; 5744 type = "passive"; 5745 }; 5746 5747 cpu8_crit: cpu-crit { 5748 temperature = <110000>; 5749 hysteresis = <0>; 5750 type = "critical"; 5751 }; 5752 }; 5753 5754 cooling-maps { 5755 map0 { 5756 trip = <&cpu8_alert0>; 5757 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5759 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5760 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5761 }; 5762 map1 { 5763 trip = <&cpu8_alert1>; 5764 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5765 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5766 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5767 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5768 }; 5769 }; 5770 }; 5771 5772 cpu9-thermal { 5773 polling-delay-passive = <250>; 5774 polling-delay = <0>; 5775 5776 thermal-sensors = <&tsens0 12>; 5777 5778 trips { 5779 cpu9_alert0: trip-point0 { 5780 temperature = <90000>; 5781 hysteresis = <2000>; 5782 type = "passive"; 5783 }; 5784 5785 cpu9_alert1: trip-point1 { 5786 temperature = <95000>; 5787 hysteresis = <2000>; 5788 type = "passive"; 5789 }; 5790 5791 cpu9_crit: cpu-crit { 5792 temperature = <110000>; 5793 hysteresis = <0>; 5794 type = "critical"; 5795 }; 5796 }; 5797 5798 cooling-maps { 5799 map0 { 5800 trip = <&cpu9_alert0>; 5801 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5803 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5804 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5805 }; 5806 map1 { 5807 trip = <&cpu9_alert1>; 5808 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5809 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5810 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5811 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5812 }; 5813 }; 5814 }; 5815 5816 cpu10-thermal { 5817 polling-delay-passive = <250>; 5818 polling-delay = <0>; 5819 5820 thermal-sensors = <&tsens0 13>; 5821 5822 trips { 5823 cpu10_alert0: trip-point0 { 5824 temperature = <90000>; 5825 hysteresis = <2000>; 5826 type = "passive"; 5827 }; 5828 5829 cpu10_alert1: trip-point1 { 5830 temperature = <95000>; 5831 hysteresis = <2000>; 5832 type = "passive"; 5833 }; 5834 5835 cpu10_crit: cpu-crit { 5836 temperature = <110000>; 5837 hysteresis = <0>; 5838 type = "critical"; 5839 }; 5840 }; 5841 5842 cooling-maps { 5843 map0 { 5844 trip = <&cpu10_alert0>; 5845 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5847 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5848 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5849 }; 5850 map1 { 5851 trip = <&cpu10_alert1>; 5852 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5853 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5854 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5855 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5856 }; 5857 }; 5858 }; 5859 5860 cpu11-thermal { 5861 polling-delay-passive = <250>; 5862 polling-delay = <0>; 5863 5864 thermal-sensors = <&tsens0 14>; 5865 5866 trips { 5867 cpu11_alert0: trip-point0 { 5868 temperature = <90000>; 5869 hysteresis = <2000>; 5870 type = "passive"; 5871 }; 5872 5873 cpu11_alert1: trip-point1 { 5874 temperature = <95000>; 5875 hysteresis = <2000>; 5876 type = "passive"; 5877 }; 5878 5879 cpu11_crit: cpu-crit { 5880 temperature = <110000>; 5881 hysteresis = <0>; 5882 type = "critical"; 5883 }; 5884 }; 5885 5886 cooling-maps { 5887 map0 { 5888 trip = <&cpu11_alert0>; 5889 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5891 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5892 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5893 }; 5894 map1 { 5895 trip = <&cpu11_alert1>; 5896 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5897 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5898 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5899 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5900 }; 5901 }; 5902 }; 5903 5904 aoss0-thermal { 5905 polling-delay-passive = <0>; 5906 polling-delay = <0>; 5907 5908 thermal-sensors = <&tsens0 0>; 5909 5910 trips { 5911 aoss0_alert0: trip-point0 { 5912 temperature = <90000>; 5913 hysteresis = <2000>; 5914 type = "hot"; 5915 }; 5916 5917 aoss0_crit: aoss0-crit { 5918 temperature = <110000>; 5919 hysteresis = <0>; 5920 type = "critical"; 5921 }; 5922 }; 5923 }; 5924 5925 aoss1-thermal { 5926 polling-delay-passive = <0>; 5927 polling-delay = <0>; 5928 5929 thermal-sensors = <&tsens1 0>; 5930 5931 trips { 5932 aoss1_alert0: trip-point0 { 5933 temperature = <90000>; 5934 hysteresis = <2000>; 5935 type = "hot"; 5936 }; 5937 5938 aoss1_crit: aoss1-crit { 5939 temperature = <110000>; 5940 hysteresis = <0>; 5941 type = "critical"; 5942 }; 5943 }; 5944 }; 5945 5946 cpuss0-thermal { 5947 polling-delay-passive = <0>; 5948 polling-delay = <0>; 5949 5950 thermal-sensors = <&tsens0 5>; 5951 5952 trips { 5953 cpuss0_alert0: trip-point0 { 5954 temperature = <90000>; 5955 hysteresis = <2000>; 5956 type = "hot"; 5957 }; 5958 cpuss0_crit: cluster0-crit { 5959 temperature = <110000>; 5960 hysteresis = <0>; 5961 type = "critical"; 5962 }; 5963 }; 5964 }; 5965 5966 cpuss1-thermal { 5967 polling-delay-passive = <0>; 5968 polling-delay = <0>; 5969 5970 thermal-sensors = <&tsens0 6>; 5971 5972 trips { 5973 cpuss1_alert0: trip-point0 { 5974 temperature = <90000>; 5975 hysteresis = <2000>; 5976 type = "hot"; 5977 }; 5978 cpuss1_crit: cluster0-crit { 5979 temperature = <110000>; 5980 hysteresis = <0>; 5981 type = "critical"; 5982 }; 5983 }; 5984 }; 5985 5986 gpuss0-thermal { 5987 polling-delay-passive = <100>; 5988 polling-delay = <0>; 5989 5990 thermal-sensors = <&tsens1 1>; 5991 5992 trips { 5993 gpuss0_alert0: trip-point0 { 5994 temperature = <95000>; 5995 hysteresis = <2000>; 5996 type = "passive"; 5997 }; 5998 5999 gpuss0_crit: gpuss0-crit { 6000 temperature = <110000>; 6001 hysteresis = <0>; 6002 type = "critical"; 6003 }; 6004 }; 6005 6006 cooling-maps { 6007 map0 { 6008 trip = <&gpuss0_alert0>; 6009 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6010 }; 6011 }; 6012 }; 6013 6014 gpuss1-thermal { 6015 polling-delay-passive = <100>; 6016 polling-delay = <0>; 6017 6018 thermal-sensors = <&tsens1 2>; 6019 6020 trips { 6021 gpuss1_alert0: trip-point0 { 6022 temperature = <95000>; 6023 hysteresis = <2000>; 6024 type = "passive"; 6025 }; 6026 6027 gpuss1_crit: gpuss1-crit { 6028 temperature = <110000>; 6029 hysteresis = <0>; 6030 type = "critical"; 6031 }; 6032 }; 6033 6034 cooling-maps { 6035 map0 { 6036 trip = <&gpuss1_alert0>; 6037 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6038 }; 6039 }; 6040 }; 6041 6042 nspss0-thermal { 6043 polling-delay-passive = <0>; 6044 polling-delay = <0>; 6045 6046 thermal-sensors = <&tsens1 3>; 6047 6048 trips { 6049 nspss0_alert0: trip-point0 { 6050 temperature = <90000>; 6051 hysteresis = <2000>; 6052 type = "hot"; 6053 }; 6054 6055 nspss0_crit: nspss0-crit { 6056 temperature = <110000>; 6057 hysteresis = <0>; 6058 type = "critical"; 6059 }; 6060 }; 6061 }; 6062 6063 nspss1-thermal { 6064 polling-delay-passive = <0>; 6065 polling-delay = <0>; 6066 6067 thermal-sensors = <&tsens1 4>; 6068 6069 trips { 6070 nspss1_alert0: trip-point0 { 6071 temperature = <90000>; 6072 hysteresis = <2000>; 6073 type = "hot"; 6074 }; 6075 6076 nspss1_crit: nspss1-crit { 6077 temperature = <110000>; 6078 hysteresis = <0>; 6079 type = "critical"; 6080 }; 6081 }; 6082 }; 6083 6084 video-thermal { 6085 polling-delay-passive = <0>; 6086 polling-delay = <0>; 6087 6088 thermal-sensors = <&tsens1 5>; 6089 6090 trips { 6091 video_alert0: trip-point0 { 6092 temperature = <90000>; 6093 hysteresis = <2000>; 6094 type = "hot"; 6095 }; 6096 6097 video_crit: video-crit { 6098 temperature = <110000>; 6099 hysteresis = <0>; 6100 type = "critical"; 6101 }; 6102 }; 6103 }; 6104 6105 ddr-thermal { 6106 polling-delay-passive = <0>; 6107 polling-delay = <0>; 6108 6109 thermal-sensors = <&tsens1 6>; 6110 6111 trips { 6112 ddr_alert0: trip-point0 { 6113 temperature = <90000>; 6114 hysteresis = <2000>; 6115 type = "hot"; 6116 }; 6117 6118 ddr_crit: ddr-crit { 6119 temperature = <110000>; 6120 hysteresis = <0>; 6121 type = "critical"; 6122 }; 6123 }; 6124 }; 6125 6126 mdmss0-thermal { 6127 polling-delay-passive = <0>; 6128 polling-delay = <0>; 6129 6130 thermal-sensors = <&tsens1 7>; 6131 6132 trips { 6133 mdmss0_alert0: trip-point0 { 6134 temperature = <90000>; 6135 hysteresis = <2000>; 6136 type = "hot"; 6137 }; 6138 6139 mdmss0_crit: mdmss0-crit { 6140 temperature = <110000>; 6141 hysteresis = <0>; 6142 type = "critical"; 6143 }; 6144 }; 6145 }; 6146 6147 mdmss1-thermal { 6148 polling-delay-passive = <0>; 6149 polling-delay = <0>; 6150 6151 thermal-sensors = <&tsens1 8>; 6152 6153 trips { 6154 mdmss1_alert0: trip-point0 { 6155 temperature = <90000>; 6156 hysteresis = <2000>; 6157 type = "hot"; 6158 }; 6159 6160 mdmss1_crit: mdmss1-crit { 6161 temperature = <110000>; 6162 hysteresis = <0>; 6163 type = "critical"; 6164 }; 6165 }; 6166 }; 6167 6168 mdmss2-thermal { 6169 polling-delay-passive = <0>; 6170 polling-delay = <0>; 6171 6172 thermal-sensors = <&tsens1 9>; 6173 6174 trips { 6175 mdmss2_alert0: trip-point0 { 6176 temperature = <90000>; 6177 hysteresis = <2000>; 6178 type = "hot"; 6179 }; 6180 6181 mdmss2_crit: mdmss2-crit { 6182 temperature = <110000>; 6183 hysteresis = <0>; 6184 type = "critical"; 6185 }; 6186 }; 6187 }; 6188 6189 mdmss3-thermal { 6190 polling-delay-passive = <0>; 6191 polling-delay = <0>; 6192 6193 thermal-sensors = <&tsens1 10>; 6194 6195 trips { 6196 mdmss3_alert0: trip-point0 { 6197 temperature = <90000>; 6198 hysteresis = <2000>; 6199 type = "hot"; 6200 }; 6201 6202 mdmss3_crit: mdmss3-crit { 6203 temperature = <110000>; 6204 hysteresis = <0>; 6205 type = "critical"; 6206 }; 6207 }; 6208 }; 6209 6210 camera0-thermal { 6211 polling-delay-passive = <0>; 6212 polling-delay = <0>; 6213 6214 thermal-sensors = <&tsens1 11>; 6215 6216 trips { 6217 camera0_alert0: trip-point0 { 6218 temperature = <90000>; 6219 hysteresis = <2000>; 6220 type = "hot"; 6221 }; 6222 6223 camera0_crit: camera0-crit { 6224 temperature = <110000>; 6225 hysteresis = <0>; 6226 type = "critical"; 6227 }; 6228 }; 6229 }; 6230 }; 6231 6232 timer { 6233 compatible = "arm,armv8-timer"; 6234 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6235 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6236 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6237 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6238 }; 6239}; 6240