1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 ipa_fw_mem: memory@8b700000 { 133 reg = <0 0x8b700000 0 0x10000>; 134 no-map; 135 }; 136 137 rmtfs_mem: memory@9c900000 { 138 compatible = "qcom,rmtfs-mem"; 139 reg = <0x0 0x9c900000 0x0 0x280000>; 140 no-map; 141 142 qcom,client-id = <1>; 143 qcom,vmid = <15>; 144 }; 145 }; 146 147 cpus { 148 #address-cells = <2>; 149 #size-cells = <0>; 150 151 CPU0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,kryo"; 154 reg = <0x0 0x0>; 155 enable-method = "psci"; 156 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 157 &LITTLE_CPU_SLEEP_1 158 &CLUSTER_SLEEP_0>; 159 next-level-cache = <&L2_0>; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 #cooling-cells = <2>; 162 L2_0: l2-cache { 163 compatible = "cache"; 164 next-level-cache = <&L3_0>; 165 L3_0: l3-cache { 166 compatible = "cache"; 167 }; 168 }; 169 }; 170 171 CPU1: cpu@100 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x100>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_100>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_100: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU2: cpu@200 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x200>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_200>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 #cooling-cells = <2>; 199 L2_200: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU3: cpu@300 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x300>; 209 enable-method = "psci"; 210 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 211 &LITTLE_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_300>; 214 qcom,freq-domain = <&cpufreq_hw 0>; 215 #cooling-cells = <2>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "arm,kryo"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&BIG_CPU_SLEEP_0 228 &BIG_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 next-level-cache = <&L2_400>; 231 qcom,freq-domain = <&cpufreq_hw 1>; 232 #cooling-cells = <2>; 233 L2_400: l2-cache { 234 compatible = "cache"; 235 next-level-cache = <&L3_0>; 236 }; 237 }; 238 239 CPU5: cpu@500 { 240 device_type = "cpu"; 241 compatible = "arm,kryo"; 242 reg = <0x0 0x500>; 243 enable-method = "psci"; 244 cpu-idle-states = <&BIG_CPU_SLEEP_0 245 &BIG_CPU_SLEEP_1 246 &CLUSTER_SLEEP_0>; 247 next-level-cache = <&L2_500>; 248 qcom,freq-domain = <&cpufreq_hw 1>; 249 #cooling-cells = <2>; 250 L2_500: l2-cache { 251 compatible = "cache"; 252 next-level-cache = <&L3_0>; 253 }; 254 }; 255 256 CPU6: cpu@600 { 257 device_type = "cpu"; 258 compatible = "arm,kryo"; 259 reg = <0x0 0x600>; 260 enable-method = "psci"; 261 cpu-idle-states = <&BIG_CPU_SLEEP_0 262 &BIG_CPU_SLEEP_1 263 &CLUSTER_SLEEP_0>; 264 next-level-cache = <&L2_600>; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 #cooling-cells = <2>; 267 L2_600: l2-cache { 268 compatible = "cache"; 269 next-level-cache = <&L3_0>; 270 }; 271 }; 272 273 CPU7: cpu@700 { 274 device_type = "cpu"; 275 compatible = "arm,kryo"; 276 reg = <0x0 0x700>; 277 enable-method = "psci"; 278 cpu-idle-states = <&BIG_CPU_SLEEP_0 279 &BIG_CPU_SLEEP_1 280 &CLUSTER_SLEEP_0>; 281 next-level-cache = <&L2_700>; 282 qcom,freq-domain = <&cpufreq_hw 2>; 283 #cooling-cells = <2>; 284 L2_700: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 cpu-map { 291 cluster0 { 292 core0 { 293 cpu = <&CPU0>; 294 }; 295 296 core1 { 297 cpu = <&CPU1>; 298 }; 299 300 core2 { 301 cpu = <&CPU2>; 302 }; 303 304 core3 { 305 cpu = <&CPU3>; 306 }; 307 308 core4 { 309 cpu = <&CPU4>; 310 }; 311 312 core5 { 313 cpu = <&CPU5>; 314 }; 315 316 core6 { 317 cpu = <&CPU6>; 318 }; 319 320 core7 { 321 cpu = <&CPU7>; 322 }; 323 }; 324 }; 325 326 idle-states { 327 entry-method = "psci"; 328 329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-power-down"; 332 arm,psci-suspend-param = <0x40000003>; 333 entry-latency-us = <549>; 334 exit-latency-us = <901>; 335 min-residency-us = <1774>; 336 local-timer-stop; 337 }; 338 339 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "little-rail-power-down"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <702>; 344 exit-latency-us = <915>; 345 min-residency-us = <4001>; 346 local-timer-stop; 347 }; 348 349 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "big-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <523>; 354 exit-latency-us = <1244>; 355 min-residency-us = <2207>; 356 local-timer-stop; 357 }; 358 359 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "big-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <526>; 364 exit-latency-us = <1854>; 365 min-residency-us = <5555>; 366 local-timer-stop; 367 }; 368 369 CLUSTER_SLEEP_0: cluster-sleep-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "cluster-power-down"; 372 arm,psci-suspend-param = <0x40003444>; 373 entry-latency-us = <3263>; 374 exit-latency-us = <6562>; 375 min-residency-us = <9926>; 376 local-timer-stop; 377 }; 378 }; 379 }; 380 381 memory@80000000 { 382 device_type = "memory"; 383 /* We expect the bootloader to fill in the size */ 384 reg = <0 0x80000000 0 0>; 385 }; 386 387 firmware { 388 scm { 389 compatible = "qcom,scm-sc7280", "qcom,scm"; 390 }; 391 }; 392 393 clk_virt: interconnect { 394 compatible = "qcom,sc7280-clk-virt"; 395 #interconnect-cells = <2>; 396 qcom,bcm-voters = <&apps_bcm_voter>; 397 }; 398 399 smem { 400 compatible = "qcom,smem"; 401 memory-region = <&smem_mem>; 402 hwlocks = <&tcsr_mutex 3>; 403 }; 404 405 smp2p-adsp { 406 compatible = "qcom,smp2p"; 407 qcom,smem = <443>, <429>; 408 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 409 IPCC_MPROC_SIGNAL_SMP2P 410 IRQ_TYPE_EDGE_RISING>; 411 mboxes = <&ipcc IPCC_CLIENT_LPASS 412 IPCC_MPROC_SIGNAL_SMP2P>; 413 414 qcom,local-pid = <0>; 415 qcom,remote-pid = <2>; 416 417 adsp_smp2p_out: master-kernel { 418 qcom,entry-name = "master-kernel"; 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 adsp_smp2p_in: slave-kernel { 423 qcom,entry-name = "slave-kernel"; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 }; 428 429 smp2p-cdsp { 430 compatible = "qcom,smp2p"; 431 qcom,smem = <94>, <432>; 432 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 433 IPCC_MPROC_SIGNAL_SMP2P 434 IRQ_TYPE_EDGE_RISING>; 435 mboxes = <&ipcc IPCC_CLIENT_CDSP 436 IPCC_MPROC_SIGNAL_SMP2P>; 437 438 qcom,local-pid = <0>; 439 qcom,remote-pid = <5>; 440 441 cdsp_smp2p_out: master-kernel { 442 qcom,entry-name = "master-kernel"; 443 #qcom,smem-state-cells = <1>; 444 }; 445 446 cdsp_smp2p_in: slave-kernel { 447 qcom,entry-name = "slave-kernel"; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 }; 451 }; 452 453 smp2p-mpss { 454 compatible = "qcom,smp2p"; 455 qcom,smem = <435>, <428>; 456 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 457 IPCC_MPROC_SIGNAL_SMP2P 458 IRQ_TYPE_EDGE_RISING>; 459 mboxes = <&ipcc IPCC_CLIENT_MPSS 460 IPCC_MPROC_SIGNAL_SMP2P>; 461 462 qcom,local-pid = <0>; 463 qcom,remote-pid = <1>; 464 465 modem_smp2p_out: master-kernel { 466 qcom,entry-name = "master-kernel"; 467 #qcom,smem-state-cells = <1>; 468 }; 469 470 modem_smp2p_in: slave-kernel { 471 qcom,entry-name = "slave-kernel"; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 }; 475 476 ipa_smp2p_out: ipa-ap-to-modem { 477 qcom,entry-name = "ipa"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 ipa_smp2p_in: ipa-modem-to-ap { 482 qcom,entry-name = "ipa"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 smp2p-wpss { 489 compatible = "qcom,smp2p"; 490 qcom,smem = <617>, <616>; 491 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 492 IPCC_MPROC_SIGNAL_SMP2P 493 IRQ_TYPE_EDGE_RISING>; 494 mboxes = <&ipcc IPCC_CLIENT_WPSS 495 IPCC_MPROC_SIGNAL_SMP2P>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <13>; 499 500 wpss_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 wpss_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 pmu { 513 compatible = "arm,armv8-pmuv3"; 514 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 515 }; 516 517 psci { 518 compatible = "arm,psci-1.0"; 519 method = "smc"; 520 }; 521 522 qspi_opp_table: qspi-opp-table { 523 compatible = "operating-points-v2"; 524 525 opp-75000000 { 526 opp-hz = /bits/ 64 <75000000>; 527 required-opps = <&rpmhpd_opp_low_svs>; 528 }; 529 530 opp-150000000 { 531 opp-hz = /bits/ 64 <150000000>; 532 required-opps = <&rpmhpd_opp_svs>; 533 }; 534 535 opp-300000000 { 536 opp-hz = /bits/ 64 <300000000>; 537 required-opps = <&rpmhpd_opp_nom>; 538 }; 539 }; 540 541 qup_opp_table: qup-opp-table { 542 compatible = "operating-points-v2"; 543 544 opp-75000000 { 545 opp-hz = /bits/ 64 <75000000>; 546 required-opps = <&rpmhpd_opp_low_svs>; 547 }; 548 549 opp-100000000 { 550 opp-hz = /bits/ 64 <100000000>; 551 required-opps = <&rpmhpd_opp_svs>; 552 }; 553 554 opp-128000000 { 555 opp-hz = /bits/ 64 <128000000>; 556 required-opps = <&rpmhpd_opp_nom>; 557 }; 558 }; 559 560 soc: soc@0 { 561 #address-cells = <2>; 562 #size-cells = <2>; 563 ranges = <0 0 0 0 0x10 0>; 564 dma-ranges = <0 0 0 0 0x10 0>; 565 compatible = "simple-bus"; 566 567 gcc: clock-controller@100000 { 568 compatible = "qcom,gcc-sc7280"; 569 reg = <0 0x00100000 0 0x1f0000>; 570 clocks = <&rpmhcc RPMH_CXO_CLK>, 571 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 572 <0>, <0>, <0>, <0>, <0>, <0>; 573 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 574 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 575 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 576 "ufs_phy_tx_symbol_0_clk", 577 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 578 #clock-cells = <1>; 579 #reset-cells = <1>; 580 #power-domain-cells = <1>; 581 }; 582 583 ipcc: mailbox@408000 { 584 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 585 reg = <0 0x00408000 0 0x1000>; 586 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-controller; 588 #interrupt-cells = <3>; 589 #mbox-cells = <2>; 590 }; 591 592 qfprom: efuse@784000 { 593 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 594 reg = <0 0x00784000 0 0xa20>, 595 <0 0x00780000 0 0xa20>, 596 <0 0x00782000 0 0x120>, 597 <0 0x00786000 0 0x1fff>; 598 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 599 clock-names = "core"; 600 power-domains = <&rpmhpd SC7280_MX>; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 }; 604 605 sdhc_1: sdhci@7c4000 { 606 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 607 status = "disabled"; 608 609 reg = <0 0x007c4000 0 0x1000>, 610 <0 0x007c5000 0 0x1000>; 611 reg-names = "hc", "cqhci"; 612 613 iommus = <&apps_smmu 0xc0 0x0>; 614 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 616 interrupt-names = "hc_irq", "pwr_irq"; 617 618 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 619 <&gcc GCC_SDCC1_AHB_CLK>, 620 <&rpmhcc RPMH_CXO_CLK>; 621 clock-names = "core", "iface", "xo"; 622 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 624 interconnect-names = "sdhc-ddr","cpu-sdhc"; 625 power-domains = <&rpmhpd SC7280_CX>; 626 operating-points-v2 = <&sdhc1_opp_table>; 627 628 bus-width = <8>; 629 supports-cqe; 630 631 qcom,dll-config = <0x0007642c>; 632 qcom,ddr-config = <0x80040868>; 633 634 mmc-ddr-1_8v; 635 mmc-hs200-1_8v; 636 mmc-hs400-1_8v; 637 mmc-hs400-enhanced-strobe; 638 639 sdhc1_opp_table: opp-table { 640 compatible = "operating-points-v2"; 641 642 opp-100000000 { 643 opp-hz = /bits/ 64 <100000000>; 644 required-opps = <&rpmhpd_opp_low_svs>; 645 opp-peak-kBps = <1800000 400000>; 646 opp-avg-kBps = <100000 0>; 647 }; 648 649 opp-384000000 { 650 opp-hz = /bits/ 64 <384000000>; 651 required-opps = <&rpmhpd_opp_nom>; 652 opp-peak-kBps = <5400000 1600000>; 653 opp-avg-kBps = <390000 0>; 654 }; 655 }; 656 657 }; 658 659 qupv3_id_0: geniqup@9c0000 { 660 compatible = "qcom,geni-se-qup"; 661 reg = <0 0x009c0000 0 0x2000>; 662 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 663 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 664 clock-names = "m-ahb", "s-ahb"; 665 #address-cells = <2>; 666 #size-cells = <2>; 667 ranges; 668 iommus = <&apps_smmu 0x123 0x0>; 669 status = "disabled"; 670 671 i2c0: i2c@980000 { 672 compatible = "qcom,geni-i2c"; 673 reg = <0 0x00980000 0 0x4000>; 674 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 675 clock-names = "se"; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&qup_i2c0_data_clk>; 678 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 683 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 684 interconnect-names = "qup-core", "qup-config", 685 "qup-memory"; 686 status = "disabled"; 687 }; 688 689 spi0: spi@980000 { 690 compatible = "qcom,geni-spi"; 691 reg = <0 0x00980000 0 0x4000>; 692 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 693 clock-names = "se"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 696 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 power-domains = <&rpmhpd SC7280_CX>; 700 operating-points-v2 = <&qup_opp_table>; 701 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 702 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 703 interconnect-names = "qup-core", "qup-config"; 704 status = "disabled"; 705 }; 706 707 uart0: serial@980000 { 708 compatible = "qcom,geni-uart"; 709 reg = <0 0x00980000 0 0x4000>; 710 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 711 clock-names = "se"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 714 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 715 power-domains = <&rpmhpd SC7280_CX>; 716 operating-points-v2 = <&qup_opp_table>; 717 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 719 interconnect-names = "qup-core", "qup-config"; 720 status = "disabled"; 721 }; 722 723 i2c1: i2c@984000 { 724 compatible = "qcom,geni-i2c"; 725 reg = <0 0x00984000 0 0x4000>; 726 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 727 clock-names = "se"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&qup_i2c1_data_clk>; 730 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 735 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 736 interconnect-names = "qup-core", "qup-config", 737 "qup-memory"; 738 status = "disabled"; 739 }; 740 741 spi1: spi@984000 { 742 compatible = "qcom,geni-spi"; 743 reg = <0 0x00984000 0 0x4000>; 744 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 745 clock-names = "se"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 748 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 power-domains = <&rpmhpd SC7280_CX>; 752 operating-points-v2 = <&qup_opp_table>; 753 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 755 interconnect-names = "qup-core", "qup-config"; 756 status = "disabled"; 757 }; 758 759 uart1: serial@984000 { 760 compatible = "qcom,geni-uart"; 761 reg = <0 0x00984000 0 0x4000>; 762 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 763 clock-names = "se"; 764 pinctrl-names = "default"; 765 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 766 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 767 power-domains = <&rpmhpd SC7280_CX>; 768 operating-points-v2 = <&qup_opp_table>; 769 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 770 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 771 interconnect-names = "qup-core", "qup-config"; 772 status = "disabled"; 773 }; 774 775 i2c2: i2c@988000 { 776 compatible = "qcom,geni-i2c"; 777 reg = <0 0x00988000 0 0x4000>; 778 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 779 clock-names = "se"; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&qup_i2c2_data_clk>; 782 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 786 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 787 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 788 interconnect-names = "qup-core", "qup-config", 789 "qup-memory"; 790 status = "disabled"; 791 }; 792 793 spi2: spi@988000 { 794 compatible = "qcom,geni-spi"; 795 reg = <0 0x00988000 0 0x4000>; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 797 clock-names = "se"; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 800 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 power-domains = <&rpmhpd SC7280_CX>; 804 operating-points-v2 = <&qup_opp_table>; 805 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 807 interconnect-names = "qup-core", "qup-config"; 808 status = "disabled"; 809 }; 810 811 uart2: serial@988000 { 812 compatible = "qcom,geni-uart"; 813 reg = <0 0x00988000 0 0x4000>; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 815 clock-names = "se"; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 818 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 819 power-domains = <&rpmhpd SC7280_CX>; 820 operating-points-v2 = <&qup_opp_table>; 821 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 822 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 823 interconnect-names = "qup-core", "qup-config"; 824 status = "disabled"; 825 }; 826 827 i2c3: i2c@98c000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x0098c000 0 0x4000>; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 831 clock-names = "se"; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c3_data_clk>; 834 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 839 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 840 interconnect-names = "qup-core", "qup-config", 841 "qup-memory"; 842 status = "disabled"; 843 }; 844 845 spi3: spi@98c000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0 0x0098c000 0 0x4000>; 848 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 849 clock-names = "se"; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 852 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 power-domains = <&rpmhpd SC7280_CX>; 856 operating-points-v2 = <&qup_opp_table>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 858 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 859 interconnect-names = "qup-core", "qup-config"; 860 status = "disabled"; 861 }; 862 863 uart3: serial@98c000 { 864 compatible = "qcom,geni-uart"; 865 reg = <0 0x0098c000 0 0x4000>; 866 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 867 clock-names = "se"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 870 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 871 power-domains = <&rpmhpd SC7280_CX>; 872 operating-points-v2 = <&qup_opp_table>; 873 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 874 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 875 interconnect-names = "qup-core", "qup-config"; 876 status = "disabled"; 877 }; 878 879 i2c4: i2c@990000 { 880 compatible = "qcom,geni-i2c"; 881 reg = <0 0x00990000 0 0x4000>; 882 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 883 clock-names = "se"; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&qup_i2c4_data_clk>; 886 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 890 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 891 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 892 interconnect-names = "qup-core", "qup-config", 893 "qup-memory"; 894 status = "disabled"; 895 }; 896 897 spi4: spi@990000 { 898 compatible = "qcom,geni-spi"; 899 reg = <0 0x00990000 0 0x4000>; 900 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 901 clock-names = "se"; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 904 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 power-domains = <&rpmhpd SC7280_CX>; 908 operating-points-v2 = <&qup_opp_table>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 910 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 911 interconnect-names = "qup-core", "qup-config"; 912 status = "disabled"; 913 }; 914 915 uart4: serial@990000 { 916 compatible = "qcom,geni-uart"; 917 reg = <0 0x00990000 0 0x4000>; 918 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 919 clock-names = "se"; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 922 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&qup_opp_table>; 925 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 926 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 927 interconnect-names = "qup-core", "qup-config"; 928 status = "disabled"; 929 }; 930 931 i2c5: i2c@994000 { 932 compatible = "qcom,geni-i2c"; 933 reg = <0 0x00994000 0 0x4000>; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 935 clock-names = "se"; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_i2c5_data_clk>; 938 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 943 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 944 interconnect-names = "qup-core", "qup-config", 945 "qup-memory"; 946 status = "disabled"; 947 }; 948 949 spi5: spi@994000 { 950 compatible = "qcom,geni-spi"; 951 reg = <0 0x00994000 0 0x4000>; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 953 clock-names = "se"; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 956 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 power-domains = <&rpmhpd SC7280_CX>; 960 operating-points-v2 = <&qup_opp_table>; 961 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 962 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 963 interconnect-names = "qup-core", "qup-config"; 964 status = "disabled"; 965 }; 966 967 uart5: serial@994000 { 968 compatible = "qcom,geni-uart"; 969 reg = <0 0x00994000 0 0x4000>; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 971 clock-names = "se"; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 974 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 975 power-domains = <&rpmhpd SC7280_CX>; 976 operating-points-v2 = <&qup_opp_table>; 977 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 978 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 979 interconnect-names = "qup-core", "qup-config"; 980 status = "disabled"; 981 }; 982 983 i2c6: i2c@998000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0 0x00998000 0 0x4000>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 987 clock-names = "se"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c6_data_clk>; 990 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 995 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 996 interconnect-names = "qup-core", "qup-config", 997 "qup-memory"; 998 status = "disabled"; 999 }; 1000 1001 spi6: spi@998000 { 1002 compatible = "qcom,geni-spi"; 1003 reg = <0 0x00998000 0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1005 clock-names = "se"; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1008 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 power-domains = <&rpmhpd SC7280_CX>; 1012 operating-points-v2 = <&qup_opp_table>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1015 interconnect-names = "qup-core", "qup-config"; 1016 status = "disabled"; 1017 }; 1018 1019 uart6: serial@998000 { 1020 compatible = "qcom,geni-uart"; 1021 reg = <0 0x00998000 0 0x4000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1023 clock-names = "se"; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1026 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&rpmhpd SC7280_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 status = "disabled"; 1033 }; 1034 1035 i2c7: i2c@99c000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x0099c000 0 0x4000>; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1039 clock-names = "se"; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c7_data_clk>; 1042 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1047 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", 1049 "qup-memory"; 1050 status = "disabled"; 1051 }; 1052 1053 spi7: spi@99c000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0 0x0099c000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1060 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 power-domains = <&rpmhpd SC7280_CX>; 1064 operating-points-v2 = <&qup_opp_table>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1066 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 status = "disabled"; 1069 }; 1070 1071 uart7: serial@99c000 { 1072 compatible = "qcom,geni-uart"; 1073 reg = <0 0x0099c000 0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1075 clock-names = "se"; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1078 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1079 power-domains = <&rpmhpd SC7280_CX>; 1080 operating-points-v2 = <&qup_opp_table>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1082 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1083 interconnect-names = "qup-core", "qup-config"; 1084 status = "disabled"; 1085 }; 1086 }; 1087 1088 qupv3_id_1: geniqup@ac0000 { 1089 compatible = "qcom,geni-se-qup"; 1090 reg = <0 0x00ac0000 0 0x2000>; 1091 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1092 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1093 clock-names = "m-ahb", "s-ahb"; 1094 #address-cells = <2>; 1095 #size-cells = <2>; 1096 ranges; 1097 iommus = <&apps_smmu 0x43 0x0>; 1098 status = "disabled"; 1099 1100 i2c8: i2c@a80000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0 0x00a80000 0 0x4000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1104 clock-names = "se"; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c8_data_clk>; 1107 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1111 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1112 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1113 interconnect-names = "qup-core", "qup-config", 1114 "qup-memory"; 1115 status = "disabled"; 1116 }; 1117 1118 spi8: spi@a80000 { 1119 compatible = "qcom,geni-spi"; 1120 reg = <0 0x00a80000 0 0x4000>; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 clock-names = "se"; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1125 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 operating-points-v2 = <&qup_opp_table>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1132 interconnect-names = "qup-core", "qup-config"; 1133 status = "disabled"; 1134 }; 1135 1136 uart8: serial@a80000 { 1137 compatible = "qcom,geni-uart"; 1138 reg = <0 0x00a80000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1143 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1144 power-domains = <&rpmhpd SC7280_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1148 interconnect-names = "qup-core", "qup-config"; 1149 status = "disabled"; 1150 }; 1151 1152 i2c9: i2c@a84000 { 1153 compatible = "qcom,geni-i2c"; 1154 reg = <0 0x00a84000 0 0x4000>; 1155 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1156 clock-names = "se"; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_i2c9_data_clk>; 1159 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1164 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", 1166 "qup-memory"; 1167 status = "disabled"; 1168 }; 1169 1170 spi9: spi@a84000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0 0x00a84000 0 0x4000>; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1174 clock-names = "se"; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1177 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 power-domains = <&rpmhpd SC7280_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1184 interconnect-names = "qup-core", "qup-config"; 1185 status = "disabled"; 1186 }; 1187 1188 uart9: serial@a84000 { 1189 compatible = "qcom,geni-uart"; 1190 reg = <0 0x00a84000 0 0x4000>; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1192 clock-names = "se"; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1195 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1196 power-domains = <&rpmhpd SC7280_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1200 interconnect-names = "qup-core", "qup-config"; 1201 status = "disabled"; 1202 }; 1203 1204 i2c10: i2c@a88000 { 1205 compatible = "qcom,geni-i2c"; 1206 reg = <0 0x00a88000 0 0x4000>; 1207 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1208 clock-names = "se"; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_i2c10_data_clk>; 1211 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1216 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1217 interconnect-names = "qup-core", "qup-config", 1218 "qup-memory"; 1219 status = "disabled"; 1220 }; 1221 1222 spi10: spi@a88000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0 0x00a88000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1226 clock-names = "se"; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1229 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 power-domains = <&rpmhpd SC7280_CX>; 1233 operating-points-v2 = <&qup_opp_table>; 1234 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1235 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 status = "disabled"; 1238 }; 1239 1240 uart10: serial@a88000 { 1241 compatible = "qcom,geni-uart"; 1242 reg = <0 0x00a88000 0 0x4000>; 1243 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1244 clock-names = "se"; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1247 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 operating-points-v2 = <&qup_opp_table>; 1250 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1251 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1252 interconnect-names = "qup-core", "qup-config"; 1253 status = "disabled"; 1254 }; 1255 1256 i2c11: i2c@a8c000 { 1257 compatible = "qcom,geni-i2c"; 1258 reg = <0 0x00a8c000 0 0x4000>; 1259 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1260 clock-names = "se"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_i2c11_data_clk>; 1263 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1267 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1268 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1269 interconnect-names = "qup-core", "qup-config", 1270 "qup-memory"; 1271 status = "disabled"; 1272 }; 1273 1274 spi11: spi@a8c000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1278 clock-names = "se"; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 power-domains = <&rpmhpd SC7280_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1288 interconnect-names = "qup-core", "qup-config"; 1289 status = "disabled"; 1290 }; 1291 1292 uart11: serial@a8c000 { 1293 compatible = "qcom,geni-uart"; 1294 reg = <0 0x00a8c000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1296 clock-names = "se"; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1299 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1300 power-domains = <&rpmhpd SC7280_CX>; 1301 operating-points-v2 = <&qup_opp_table>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1304 interconnect-names = "qup-core", "qup-config"; 1305 status = "disabled"; 1306 }; 1307 1308 i2c12: i2c@a90000 { 1309 compatible = "qcom,geni-i2c"; 1310 reg = <0 0x00a90000 0 0x4000>; 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1312 clock-names = "se"; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&qup_i2c12_data_clk>; 1315 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1319 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1320 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1321 interconnect-names = "qup-core", "qup-config", 1322 "qup-memory"; 1323 status = "disabled"; 1324 }; 1325 1326 spi12: spi@a90000 { 1327 compatible = "qcom,geni-spi"; 1328 reg = <0 0x00a90000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 power-domains = <&rpmhpd SC7280_CX>; 1337 operating-points-v2 = <&qup_opp_table>; 1338 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1339 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 status = "disabled"; 1342 }; 1343 1344 uart12: serial@a90000 { 1345 compatible = "qcom,geni-uart"; 1346 reg = <0 0x00a90000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1348 clock-names = "se"; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1351 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1352 power-domains = <&rpmhpd SC7280_CX>; 1353 operating-points-v2 = <&qup_opp_table>; 1354 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1355 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1356 interconnect-names = "qup-core", "qup-config"; 1357 status = "disabled"; 1358 }; 1359 1360 i2c13: i2c@a94000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x00a94000 0 0x4000>; 1363 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1364 clock-names = "se"; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c13_data_clk>; 1367 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1372 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", 1374 "qup-memory"; 1375 status = "disabled"; 1376 }; 1377 1378 spi13: spi@a94000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0 0x00a94000 0 0x4000>; 1381 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1382 clock-names = "se"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1385 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 power-domains = <&rpmhpd SC7280_CX>; 1389 operating-points-v2 = <&qup_opp_table>; 1390 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1391 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1392 interconnect-names = "qup-core", "qup-config"; 1393 status = "disabled"; 1394 }; 1395 1396 uart13: serial@a94000 { 1397 compatible = "qcom,geni-uart"; 1398 reg = <0 0x00a94000 0 0x4000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1400 clock-names = "se"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1403 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1404 power-domains = <&rpmhpd SC7280_CX>; 1405 operating-points-v2 = <&qup_opp_table>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1407 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1408 interconnect-names = "qup-core", "qup-config"; 1409 status = "disabled"; 1410 }; 1411 1412 i2c14: i2c@a98000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00a98000 0 0x4000>; 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1416 clock-names = "se"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c14_data_clk>; 1419 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1424 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1425 interconnect-names = "qup-core", "qup-config", 1426 "qup-memory"; 1427 status = "disabled"; 1428 }; 1429 1430 spi14: spi@a98000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00a98000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1437 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 power-domains = <&rpmhpd SC7280_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1443 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 uart14: serial@a98000 { 1449 compatible = "qcom,geni-uart"; 1450 reg = <0 0x00a98000 0 0x4000>; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1452 clock-names = "se"; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1455 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1456 power-domains = <&rpmhpd SC7280_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1459 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1460 interconnect-names = "qup-core", "qup-config"; 1461 status = "disabled"; 1462 }; 1463 1464 i2c15: i2c@a9c000 { 1465 compatible = "qcom,geni-i2c"; 1466 reg = <0 0x00a9c000 0 0x4000>; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1468 clock-names = "se"; 1469 pinctrl-names = "default"; 1470 pinctrl-0 = <&qup_i2c15_data_clk>; 1471 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1475 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1476 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1477 interconnect-names = "qup-core", "qup-config", 1478 "qup-memory"; 1479 status = "disabled"; 1480 }; 1481 1482 spi15: spi@a9c000 { 1483 compatible = "qcom,geni-spi"; 1484 reg = <0 0x00a9c000 0 0x4000>; 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1486 clock-names = "se"; 1487 pinctrl-names = "default"; 1488 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1489 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 power-domains = <&rpmhpd SC7280_CX>; 1493 operating-points-v2 = <&qup_opp_table>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1495 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1496 interconnect-names = "qup-core", "qup-config"; 1497 status = "disabled"; 1498 }; 1499 1500 uart15: serial@a9c000 { 1501 compatible = "qcom,geni-uart"; 1502 reg = <0 0x00a9c000 0 0x4000>; 1503 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1504 clock-names = "se"; 1505 pinctrl-names = "default"; 1506 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1507 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1508 power-domains = <&rpmhpd SC7280_CX>; 1509 operating-points-v2 = <&qup_opp_table>; 1510 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1511 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1512 interconnect-names = "qup-core", "qup-config"; 1513 status = "disabled"; 1514 }; 1515 }; 1516 1517 cnoc2: interconnect@1500000 { 1518 reg = <0 0x01500000 0 0x1000>; 1519 compatible = "qcom,sc7280-cnoc2"; 1520 #interconnect-cells = <2>; 1521 qcom,bcm-voters = <&apps_bcm_voter>; 1522 }; 1523 1524 cnoc3: interconnect@1502000 { 1525 reg = <0 0x01502000 0 0x1000>; 1526 compatible = "qcom,sc7280-cnoc3"; 1527 #interconnect-cells = <2>; 1528 qcom,bcm-voters = <&apps_bcm_voter>; 1529 }; 1530 1531 mc_virt: interconnect@1580000 { 1532 reg = <0 0x01580000 0 0x4>; 1533 compatible = "qcom,sc7280-mc-virt"; 1534 #interconnect-cells = <2>; 1535 qcom,bcm-voters = <&apps_bcm_voter>; 1536 }; 1537 1538 system_noc: interconnect@1680000 { 1539 reg = <0 0x01680000 0 0x15480>; 1540 compatible = "qcom,sc7280-system-noc"; 1541 #interconnect-cells = <2>; 1542 qcom,bcm-voters = <&apps_bcm_voter>; 1543 }; 1544 1545 aggre1_noc: interconnect@16e0000 { 1546 compatible = "qcom,sc7280-aggre1-noc"; 1547 reg = <0 0x016e0000 0 0x1c080>; 1548 #interconnect-cells = <2>; 1549 qcom,bcm-voters = <&apps_bcm_voter>; 1550 }; 1551 1552 aggre2_noc: interconnect@1700000 { 1553 reg = <0 0x01700000 0 0x2b080>; 1554 compatible = "qcom,sc7280-aggre2-noc"; 1555 #interconnect-cells = <2>; 1556 qcom,bcm-voters = <&apps_bcm_voter>; 1557 }; 1558 1559 mmss_noc: interconnect@1740000 { 1560 reg = <0 0x01740000 0 0x1e080>; 1561 compatible = "qcom,sc7280-mmss-noc"; 1562 #interconnect-cells = <2>; 1563 qcom,bcm-voters = <&apps_bcm_voter>; 1564 }; 1565 1566 ipa: ipa@1e40000 { 1567 compatible = "qcom,sc7280-ipa"; 1568 1569 iommus = <&apps_smmu 0x480 0x0>, 1570 <&apps_smmu 0x482 0x0>; 1571 reg = <0 0x1e40000 0 0x8000>, 1572 <0 0x1e50000 0 0x4ad0>, 1573 <0 0x1e04000 0 0x23000>; 1574 reg-names = "ipa-reg", 1575 "ipa-shared", 1576 "gsi"; 1577 1578 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1579 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1580 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1581 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1582 interrupt-names = "ipa", 1583 "gsi", 1584 "ipa-clock-query", 1585 "ipa-setup-ready"; 1586 1587 clocks = <&rpmhcc RPMH_IPA_CLK>; 1588 clock-names = "core"; 1589 1590 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1591 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1592 interconnect-names = "memory", 1593 "config"; 1594 1595 qcom,smem-states = <&ipa_smp2p_out 0>, 1596 <&ipa_smp2p_out 1>; 1597 qcom,smem-state-names = "ipa-clock-enabled-valid", 1598 "ipa-clock-enabled"; 1599 1600 status = "disabled"; 1601 }; 1602 1603 tcsr_mutex: hwlock@1f40000 { 1604 compatible = "qcom,tcsr-mutex", "syscon"; 1605 reg = <0 0x01f40000 0 0x40000>; 1606 #hwlock-cells = <1>; 1607 }; 1608 1609 lpasscc: lpasscc@3000000 { 1610 compatible = "qcom,sc7280-lpasscc"; 1611 reg = <0 0x03000000 0 0x40>, 1612 <0 0x03c04000 0 0x4>, 1613 <0 0x03389000 0 0x24>; 1614 reg-names = "qdsp6ss", "top_cc", "cc"; 1615 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1616 clock-names = "iface"; 1617 #clock-cells = <1>; 1618 }; 1619 1620 lpass_ag_noc: interconnect@3c40000 { 1621 reg = <0 0x03c40000 0 0xf080>; 1622 compatible = "qcom,sc7280-lpass-ag-noc"; 1623 #interconnect-cells = <2>; 1624 qcom,bcm-voters = <&apps_bcm_voter>; 1625 }; 1626 1627 gpu: gpu@3d00000 { 1628 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1629 #stream-id-cells = <16>; 1630 reg = <0 0x03d00000 0 0x40000>, 1631 <0 0x03d9e000 0 0x1000>, 1632 <0 0x03d61000 0 0x800>; 1633 reg-names = "kgsl_3d0_reg_memory", 1634 "cx_mem", 1635 "cx_dbgc"; 1636 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1637 iommus = <&adreno_smmu 0 0x401>; 1638 operating-points-v2 = <&gpu_opp_table>; 1639 qcom,gmu = <&gmu>; 1640 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "gfx-mem"; 1642 #cooling-cells = <2>; 1643 1644 gpu_opp_table: opp-table { 1645 compatible = "operating-points-v2"; 1646 1647 opp-315000000 { 1648 opp-hz = /bits/ 64 <315000000>; 1649 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1650 opp-peak-kBps = <1804000>; 1651 }; 1652 1653 opp-450000000 { 1654 opp-hz = /bits/ 64 <450000000>; 1655 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1656 opp-peak-kBps = <4068000>; 1657 }; 1658 1659 opp-550000000 { 1660 opp-hz = /bits/ 64 <550000000>; 1661 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1662 opp-peak-kBps = <6832000>; 1663 }; 1664 }; 1665 }; 1666 1667 gmu: gmu@3d69000 { 1668 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1669 reg = <0 0x03d6a000 0 0x34000>, 1670 <0 0x3de0000 0 0x10000>, 1671 <0 0x0b290000 0 0x10000>; 1672 reg-names = "gmu", "rscc", "gmu_pdc"; 1673 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1675 interrupt-names = "hfi", "gmu"; 1676 clocks = <&gpucc 5>, 1677 <&gpucc 8>, 1678 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1679 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1680 <&gpucc 2>, 1681 <&gpucc 15>, 1682 <&gpucc 11>; 1683 clock-names = "gmu", 1684 "cxo", 1685 "axi", 1686 "memnoc", 1687 "ahb", 1688 "hub", 1689 "smmu_vote"; 1690 power-domains = <&gpucc 0>, 1691 <&gpucc 1>; 1692 power-domain-names = "cx", 1693 "gx"; 1694 iommus = <&adreno_smmu 5 0x400>; 1695 operating-points-v2 = <&gmu_opp_table>; 1696 1697 gmu_opp_table: opp-table { 1698 compatible = "operating-points-v2"; 1699 1700 opp-200000000 { 1701 opp-hz = /bits/ 64 <200000000>; 1702 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1703 }; 1704 }; 1705 }; 1706 1707 gpucc: clock-controller@3d90000 { 1708 compatible = "qcom,sc7280-gpucc"; 1709 reg = <0 0x03d90000 0 0x9000>; 1710 clocks = <&rpmhcc RPMH_CXO_CLK>, 1711 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1712 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1713 clock-names = "bi_tcxo", 1714 "gcc_gpu_gpll0_clk_src", 1715 "gcc_gpu_gpll0_div_clk_src"; 1716 #clock-cells = <1>; 1717 #reset-cells = <1>; 1718 #power-domain-cells = <1>; 1719 }; 1720 1721 adreno_smmu: iommu@3da0000 { 1722 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1723 reg = <0 0x03da0000 0 0x20000>; 1724 #iommu-cells = <2>; 1725 #global-interrupts = <2>; 1726 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1738 1739 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1740 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1741 <&gpucc 2>, 1742 <&gpucc 11>, 1743 <&gpucc 5>, 1744 <&gpucc 15>, 1745 <&gpucc 13>; 1746 clock-names = "gcc_gpu_memnoc_gfx_clk", 1747 "gcc_gpu_snoc_dvm_gfx_clk", 1748 "gpu_cc_ahb_clk", 1749 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1750 "gpu_cc_cx_gmu_clk", 1751 "gpu_cc_hub_cx_int_clk", 1752 "gpu_cc_hub_aon_clk"; 1753 1754 power-domains = <&gpucc 0>; 1755 }; 1756 1757 stm@6002000 { 1758 compatible = "arm,coresight-stm", "arm,primecell"; 1759 reg = <0 0x06002000 0 0x1000>, 1760 <0 0x16280000 0 0x180000>; 1761 reg-names = "stm-base", "stm-stimulus-base"; 1762 1763 clocks = <&aoss_qmp>; 1764 clock-names = "apb_pclk"; 1765 1766 out-ports { 1767 port { 1768 stm_out: endpoint { 1769 remote-endpoint = <&funnel0_in7>; 1770 }; 1771 }; 1772 }; 1773 }; 1774 1775 funnel@6041000 { 1776 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1777 reg = <0 0x06041000 0 0x1000>; 1778 1779 clocks = <&aoss_qmp>; 1780 clock-names = "apb_pclk"; 1781 1782 out-ports { 1783 port { 1784 funnel0_out: endpoint { 1785 remote-endpoint = <&merge_funnel_in0>; 1786 }; 1787 }; 1788 }; 1789 1790 in-ports { 1791 #address-cells = <1>; 1792 #size-cells = <0>; 1793 1794 port@7 { 1795 reg = <7>; 1796 funnel0_in7: endpoint { 1797 remote-endpoint = <&stm_out>; 1798 }; 1799 }; 1800 }; 1801 }; 1802 1803 funnel@6042000 { 1804 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1805 reg = <0 0x06042000 0 0x1000>; 1806 1807 clocks = <&aoss_qmp>; 1808 clock-names = "apb_pclk"; 1809 1810 out-ports { 1811 port { 1812 funnel1_out: endpoint { 1813 remote-endpoint = <&merge_funnel_in1>; 1814 }; 1815 }; 1816 }; 1817 1818 in-ports { 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 1822 port@4 { 1823 reg = <4>; 1824 funnel1_in4: endpoint { 1825 remote-endpoint = <&apss_merge_funnel_out>; 1826 }; 1827 }; 1828 }; 1829 }; 1830 1831 funnel@6045000 { 1832 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1833 reg = <0 0x06045000 0 0x1000>; 1834 1835 clocks = <&aoss_qmp>; 1836 clock-names = "apb_pclk"; 1837 1838 out-ports { 1839 port { 1840 merge_funnel_out: endpoint { 1841 remote-endpoint = <&swao_funnel_in>; 1842 }; 1843 }; 1844 }; 1845 1846 in-ports { 1847 #address-cells = <1>; 1848 #size-cells = <0>; 1849 1850 port@0 { 1851 reg = <0>; 1852 merge_funnel_in0: endpoint { 1853 remote-endpoint = <&funnel0_out>; 1854 }; 1855 }; 1856 1857 port@1 { 1858 reg = <1>; 1859 merge_funnel_in1: endpoint { 1860 remote-endpoint = <&funnel1_out>; 1861 }; 1862 }; 1863 }; 1864 }; 1865 1866 replicator@6046000 { 1867 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1868 reg = <0 0x06046000 0 0x1000>; 1869 1870 clocks = <&aoss_qmp>; 1871 clock-names = "apb_pclk"; 1872 1873 out-ports { 1874 port { 1875 replicator_out: endpoint { 1876 remote-endpoint = <&etr_in>; 1877 }; 1878 }; 1879 }; 1880 1881 in-ports { 1882 port { 1883 replicator_in: endpoint { 1884 remote-endpoint = <&swao_replicator_out>; 1885 }; 1886 }; 1887 }; 1888 }; 1889 1890 etr@6048000 { 1891 compatible = "arm,coresight-tmc", "arm,primecell"; 1892 reg = <0 0x06048000 0 0x1000>; 1893 iommus = <&apps_smmu 0x04c0 0>; 1894 1895 clocks = <&aoss_qmp>; 1896 clock-names = "apb_pclk"; 1897 arm,scatter-gather; 1898 1899 in-ports { 1900 port { 1901 etr_in: endpoint { 1902 remote-endpoint = <&replicator_out>; 1903 }; 1904 }; 1905 }; 1906 }; 1907 1908 funnel@6b04000 { 1909 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1910 reg = <0 0x06b04000 0 0x1000>; 1911 1912 clocks = <&aoss_qmp>; 1913 clock-names = "apb_pclk"; 1914 1915 out-ports { 1916 port { 1917 swao_funnel_out: endpoint { 1918 remote-endpoint = <&etf_in>; 1919 }; 1920 }; 1921 }; 1922 1923 in-ports { 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 1927 port@7 { 1928 reg = <7>; 1929 swao_funnel_in: endpoint { 1930 remote-endpoint = <&merge_funnel_out>; 1931 }; 1932 }; 1933 }; 1934 }; 1935 1936 etf@6b05000 { 1937 compatible = "arm,coresight-tmc", "arm,primecell"; 1938 reg = <0 0x06b05000 0 0x1000>; 1939 1940 clocks = <&aoss_qmp>; 1941 clock-names = "apb_pclk"; 1942 1943 out-ports { 1944 port { 1945 etf_out: endpoint { 1946 remote-endpoint = <&swao_replicator_in>; 1947 }; 1948 }; 1949 }; 1950 1951 in-ports { 1952 port { 1953 etf_in: endpoint { 1954 remote-endpoint = <&swao_funnel_out>; 1955 }; 1956 }; 1957 }; 1958 }; 1959 1960 replicator@6b06000 { 1961 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1962 reg = <0 0x06b06000 0 0x1000>; 1963 1964 clocks = <&aoss_qmp>; 1965 clock-names = "apb_pclk"; 1966 qcom,replicator-loses-context; 1967 1968 out-ports { 1969 port { 1970 swao_replicator_out: endpoint { 1971 remote-endpoint = <&replicator_in>; 1972 }; 1973 }; 1974 }; 1975 1976 in-ports { 1977 port { 1978 swao_replicator_in: endpoint { 1979 remote-endpoint = <&etf_out>; 1980 }; 1981 }; 1982 }; 1983 }; 1984 1985 etm@7040000 { 1986 compatible = "arm,coresight-etm4x", "arm,primecell"; 1987 reg = <0 0x07040000 0 0x1000>; 1988 1989 cpu = <&CPU0>; 1990 1991 clocks = <&aoss_qmp>; 1992 clock-names = "apb_pclk"; 1993 arm,coresight-loses-context-with-cpu; 1994 qcom,skip-power-up; 1995 1996 out-ports { 1997 port { 1998 etm0_out: endpoint { 1999 remote-endpoint = <&apss_funnel_in0>; 2000 }; 2001 }; 2002 }; 2003 }; 2004 2005 etm@7140000 { 2006 compatible = "arm,coresight-etm4x", "arm,primecell"; 2007 reg = <0 0x07140000 0 0x1000>; 2008 2009 cpu = <&CPU1>; 2010 2011 clocks = <&aoss_qmp>; 2012 clock-names = "apb_pclk"; 2013 arm,coresight-loses-context-with-cpu; 2014 qcom,skip-power-up; 2015 2016 out-ports { 2017 port { 2018 etm1_out: endpoint { 2019 remote-endpoint = <&apss_funnel_in1>; 2020 }; 2021 }; 2022 }; 2023 }; 2024 2025 etm@7240000 { 2026 compatible = "arm,coresight-etm4x", "arm,primecell"; 2027 reg = <0 0x07240000 0 0x1000>; 2028 2029 cpu = <&CPU2>; 2030 2031 clocks = <&aoss_qmp>; 2032 clock-names = "apb_pclk"; 2033 arm,coresight-loses-context-with-cpu; 2034 qcom,skip-power-up; 2035 2036 out-ports { 2037 port { 2038 etm2_out: endpoint { 2039 remote-endpoint = <&apss_funnel_in2>; 2040 }; 2041 }; 2042 }; 2043 }; 2044 2045 etm@7340000 { 2046 compatible = "arm,coresight-etm4x", "arm,primecell"; 2047 reg = <0 0x07340000 0 0x1000>; 2048 2049 cpu = <&CPU3>; 2050 2051 clocks = <&aoss_qmp>; 2052 clock-names = "apb_pclk"; 2053 arm,coresight-loses-context-with-cpu; 2054 qcom,skip-power-up; 2055 2056 out-ports { 2057 port { 2058 etm3_out: endpoint { 2059 remote-endpoint = <&apss_funnel_in3>; 2060 }; 2061 }; 2062 }; 2063 }; 2064 2065 etm@7440000 { 2066 compatible = "arm,coresight-etm4x", "arm,primecell"; 2067 reg = <0 0x07440000 0 0x1000>; 2068 2069 cpu = <&CPU4>; 2070 2071 clocks = <&aoss_qmp>; 2072 clock-names = "apb_pclk"; 2073 arm,coresight-loses-context-with-cpu; 2074 qcom,skip-power-up; 2075 2076 out-ports { 2077 port { 2078 etm4_out: endpoint { 2079 remote-endpoint = <&apss_funnel_in4>; 2080 }; 2081 }; 2082 }; 2083 }; 2084 2085 etm@7540000 { 2086 compatible = "arm,coresight-etm4x", "arm,primecell"; 2087 reg = <0 0x07540000 0 0x1000>; 2088 2089 cpu = <&CPU5>; 2090 2091 clocks = <&aoss_qmp>; 2092 clock-names = "apb_pclk"; 2093 arm,coresight-loses-context-with-cpu; 2094 qcom,skip-power-up; 2095 2096 out-ports { 2097 port { 2098 etm5_out: endpoint { 2099 remote-endpoint = <&apss_funnel_in5>; 2100 }; 2101 }; 2102 }; 2103 }; 2104 2105 etm@7640000 { 2106 compatible = "arm,coresight-etm4x", "arm,primecell"; 2107 reg = <0 0x07640000 0 0x1000>; 2108 2109 cpu = <&CPU6>; 2110 2111 clocks = <&aoss_qmp>; 2112 clock-names = "apb_pclk"; 2113 arm,coresight-loses-context-with-cpu; 2114 qcom,skip-power-up; 2115 2116 out-ports { 2117 port { 2118 etm6_out: endpoint { 2119 remote-endpoint = <&apss_funnel_in6>; 2120 }; 2121 }; 2122 }; 2123 }; 2124 2125 etm@7740000 { 2126 compatible = "arm,coresight-etm4x", "arm,primecell"; 2127 reg = <0 0x07740000 0 0x1000>; 2128 2129 cpu = <&CPU7>; 2130 2131 clocks = <&aoss_qmp>; 2132 clock-names = "apb_pclk"; 2133 arm,coresight-loses-context-with-cpu; 2134 qcom,skip-power-up; 2135 2136 out-ports { 2137 port { 2138 etm7_out: endpoint { 2139 remote-endpoint = <&apss_funnel_in7>; 2140 }; 2141 }; 2142 }; 2143 }; 2144 2145 funnel@7800000 { /* APSS Funnel */ 2146 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2147 reg = <0 0x07800000 0 0x1000>; 2148 2149 clocks = <&aoss_qmp>; 2150 clock-names = "apb_pclk"; 2151 2152 out-ports { 2153 port { 2154 apss_funnel_out: endpoint { 2155 remote-endpoint = <&apss_merge_funnel_in>; 2156 }; 2157 }; 2158 }; 2159 2160 in-ports { 2161 #address-cells = <1>; 2162 #size-cells = <0>; 2163 2164 port@0 { 2165 reg = <0>; 2166 apss_funnel_in0: endpoint { 2167 remote-endpoint = <&etm0_out>; 2168 }; 2169 }; 2170 2171 port@1 { 2172 reg = <1>; 2173 apss_funnel_in1: endpoint { 2174 remote-endpoint = <&etm1_out>; 2175 }; 2176 }; 2177 2178 port@2 { 2179 reg = <2>; 2180 apss_funnel_in2: endpoint { 2181 remote-endpoint = <&etm2_out>; 2182 }; 2183 }; 2184 2185 port@3 { 2186 reg = <3>; 2187 apss_funnel_in3: endpoint { 2188 remote-endpoint = <&etm3_out>; 2189 }; 2190 }; 2191 2192 port@4 { 2193 reg = <4>; 2194 apss_funnel_in4: endpoint { 2195 remote-endpoint = <&etm4_out>; 2196 }; 2197 }; 2198 2199 port@5 { 2200 reg = <5>; 2201 apss_funnel_in5: endpoint { 2202 remote-endpoint = <&etm5_out>; 2203 }; 2204 }; 2205 2206 port@6 { 2207 reg = <6>; 2208 apss_funnel_in6: endpoint { 2209 remote-endpoint = <&etm6_out>; 2210 }; 2211 }; 2212 2213 port@7 { 2214 reg = <7>; 2215 apss_funnel_in7: endpoint { 2216 remote-endpoint = <&etm7_out>; 2217 }; 2218 }; 2219 }; 2220 }; 2221 2222 funnel@7810000 { 2223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2224 reg = <0 0x07810000 0 0x1000>; 2225 2226 clocks = <&aoss_qmp>; 2227 clock-names = "apb_pclk"; 2228 2229 out-ports { 2230 port { 2231 apss_merge_funnel_out: endpoint { 2232 remote-endpoint = <&funnel1_in4>; 2233 }; 2234 }; 2235 }; 2236 2237 in-ports { 2238 port { 2239 apss_merge_funnel_in: endpoint { 2240 remote-endpoint = <&apss_funnel_out>; 2241 }; 2242 }; 2243 }; 2244 }; 2245 2246 sdhc_2: sdhci@8804000 { 2247 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2248 status = "disabled"; 2249 2250 reg = <0 0x08804000 0 0x1000>; 2251 2252 iommus = <&apps_smmu 0x100 0x0>; 2253 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2255 interrupt-names = "hc_irq", "pwr_irq"; 2256 2257 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2258 <&gcc GCC_SDCC2_AHB_CLK>, 2259 <&rpmhcc RPMH_CXO_CLK>; 2260 clock-names = "core", "iface", "xo"; 2261 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2262 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2263 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2264 power-domains = <&rpmhpd SC7280_CX>; 2265 operating-points-v2 = <&sdhc2_opp_table>; 2266 2267 bus-width = <4>; 2268 2269 qcom,dll-config = <0x0007642c>; 2270 2271 sdhc2_opp_table: opp-table { 2272 compatible = "operating-points-v2"; 2273 2274 opp-100000000 { 2275 opp-hz = /bits/ 64 <100000000>; 2276 required-opps = <&rpmhpd_opp_low_svs>; 2277 opp-peak-kBps = <1800000 400000>; 2278 opp-avg-kBps = <100000 0>; 2279 }; 2280 2281 opp-202000000 { 2282 opp-hz = /bits/ 64 <202000000>; 2283 required-opps = <&rpmhpd_opp_nom>; 2284 opp-peak-kBps = <5400000 1600000>; 2285 opp-avg-kBps = <200000 0>; 2286 }; 2287 }; 2288 2289 }; 2290 2291 usb_1_hsphy: phy@88e3000 { 2292 compatible = "qcom,sc7280-usb-hs-phy", 2293 "qcom,usb-snps-hs-7nm-phy"; 2294 reg = <0 0x088e3000 0 0x400>; 2295 status = "disabled"; 2296 #phy-cells = <0>; 2297 2298 clocks = <&rpmhcc RPMH_CXO_CLK>; 2299 clock-names = "ref"; 2300 2301 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2302 }; 2303 2304 usb_2_hsphy: phy@88e4000 { 2305 compatible = "qcom,sc7280-usb-hs-phy", 2306 "qcom,usb-snps-hs-7nm-phy"; 2307 reg = <0 0x088e4000 0 0x400>; 2308 status = "disabled"; 2309 #phy-cells = <0>; 2310 2311 clocks = <&rpmhcc RPMH_CXO_CLK>; 2312 clock-names = "ref"; 2313 2314 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2315 }; 2316 2317 usb_1_qmpphy: phy-wrapper@88e9000 { 2318 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2319 "qcom,sm8250-qmp-usb3-dp-phy"; 2320 reg = <0 0x088e9000 0 0x200>, 2321 <0 0x088e8000 0 0x40>, 2322 <0 0x088ea000 0 0x200>; 2323 status = "disabled"; 2324 #address-cells = <2>; 2325 #size-cells = <2>; 2326 ranges; 2327 2328 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2329 <&rpmhcc RPMH_CXO_CLK>, 2330 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2331 clock-names = "aux", "ref_clk_src", "com_aux"; 2332 2333 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2334 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2335 reset-names = "phy", "common"; 2336 2337 usb_1_ssphy: usb3-phy@88e9200 { 2338 reg = <0 0x088e9200 0 0x200>, 2339 <0 0x088e9400 0 0x200>, 2340 <0 0x088e9c00 0 0x400>, 2341 <0 0x088e9600 0 0x200>, 2342 <0 0x088e9800 0 0x200>, 2343 <0 0x088e9a00 0 0x100>; 2344 #clock-cells = <0>; 2345 #phy-cells = <0>; 2346 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2347 clock-names = "pipe0"; 2348 clock-output-names = "usb3_phy_pipe_clk_src"; 2349 }; 2350 2351 dp_phy: dp-phy@88ea200 { 2352 reg = <0 0x088ea200 0 0x200>, 2353 <0 0x088ea400 0 0x200>, 2354 <0 0x088eaa00 0 0x200>, 2355 <0 0x088ea600 0 0x200>, 2356 <0 0x088ea800 0 0x200>; 2357 #phy-cells = <0>; 2358 #clock-cells = <1>; 2359 }; 2360 }; 2361 2362 usb_2: usb@8cf8800 { 2363 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2364 reg = <0 0x08cf8800 0 0x400>; 2365 status = "disabled"; 2366 #address-cells = <2>; 2367 #size-cells = <2>; 2368 ranges; 2369 dma-ranges; 2370 2371 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2372 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2373 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2374 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2375 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2376 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2377 "sleep"; 2378 2379 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2380 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2381 assigned-clock-rates = <19200000>, <200000000>; 2382 2383 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2384 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2385 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2386 interrupt-names = "hs_phy_irq", 2387 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2388 2389 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2390 2391 resets = <&gcc GCC_USB30_SEC_BCR>; 2392 2393 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2394 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2395 interconnect-names = "usb-ddr", "apps-usb"; 2396 2397 usb_2_dwc3: usb@8c00000 { 2398 compatible = "snps,dwc3"; 2399 reg = <0 0x08c00000 0 0xe000>; 2400 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2401 iommus = <&apps_smmu 0xa0 0x0>; 2402 snps,dis_u2_susphy_quirk; 2403 snps,dis_enblslpm_quirk; 2404 phys = <&usb_2_hsphy>; 2405 phy-names = "usb2-phy"; 2406 maximum-speed = "high-speed"; 2407 }; 2408 }; 2409 2410 qspi: spi@88dc000 { 2411 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2412 reg = <0 0x088dc000 0 0x1000>; 2413 #address-cells = <1>; 2414 #size-cells = <0>; 2415 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2416 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2417 <&gcc GCC_QSPI_CORE_CLK>; 2418 clock-names = "iface", "core"; 2419 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2420 &cnoc2 SLAVE_QSPI_0 0>; 2421 interconnect-names = "qspi-config"; 2422 power-domains = <&rpmhpd SC7280_CX>; 2423 operating-points-v2 = <&qspi_opp_table>; 2424 status = "disabled"; 2425 }; 2426 2427 dc_noc: interconnect@90e0000 { 2428 reg = <0 0x090e0000 0 0x5080>; 2429 compatible = "qcom,sc7280-dc-noc"; 2430 #interconnect-cells = <2>; 2431 qcom,bcm-voters = <&apps_bcm_voter>; 2432 }; 2433 2434 gem_noc: interconnect@9100000 { 2435 reg = <0 0x9100000 0 0xe2200>; 2436 compatible = "qcom,sc7280-gem-noc"; 2437 #interconnect-cells = <2>; 2438 qcom,bcm-voters = <&apps_bcm_voter>; 2439 }; 2440 2441 system-cache-controller@9200000 { 2442 compatible = "qcom,sc7280-llcc"; 2443 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2444 reg-names = "llcc_base", "llcc_broadcast_base"; 2445 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2446 }; 2447 2448 nsp_noc: interconnect@a0c0000 { 2449 reg = <0 0x0a0c0000 0 0x10000>; 2450 compatible = "qcom,sc7280-nsp-noc"; 2451 #interconnect-cells = <2>; 2452 qcom,bcm-voters = <&apps_bcm_voter>; 2453 }; 2454 2455 usb_1: usb@a6f8800 { 2456 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2457 reg = <0 0x0a6f8800 0 0x400>; 2458 status = "disabled"; 2459 #address-cells = <2>; 2460 #size-cells = <2>; 2461 ranges; 2462 dma-ranges; 2463 2464 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2465 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2466 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2467 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2468 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2469 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2470 "sleep"; 2471 2472 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2473 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2474 assigned-clock-rates = <19200000>, <200000000>; 2475 2476 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2477 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2478 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2479 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2480 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2481 "dm_hs_phy_irq", "ss_phy_irq"; 2482 2483 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2484 2485 resets = <&gcc GCC_USB30_PRIM_BCR>; 2486 2487 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2488 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2489 interconnect-names = "usb-ddr", "apps-usb"; 2490 2491 usb_1_dwc3: usb@a600000 { 2492 compatible = "snps,dwc3"; 2493 reg = <0 0x0a600000 0 0xe000>; 2494 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2495 iommus = <&apps_smmu 0xe0 0x0>; 2496 snps,dis_u2_susphy_quirk; 2497 snps,dis_enblslpm_quirk; 2498 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2499 phy-names = "usb2-phy", "usb3-phy"; 2500 maximum-speed = "super-speed"; 2501 }; 2502 }; 2503 2504 videocc: clock-controller@aaf0000 { 2505 compatible = "qcom,sc7280-videocc"; 2506 reg = <0 0xaaf0000 0 0x10000>; 2507 clocks = <&rpmhcc RPMH_CXO_CLK>, 2508 <&rpmhcc RPMH_CXO_CLK_A>; 2509 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2510 #clock-cells = <1>; 2511 #reset-cells = <1>; 2512 #power-domain-cells = <1>; 2513 }; 2514 2515 dispcc: clock-controller@af00000 { 2516 compatible = "qcom,sc7280-dispcc"; 2517 reg = <0 0xaf00000 0 0x20000>; 2518 clocks = <&rpmhcc RPMH_CXO_CLK>, 2519 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2520 <0>, <0>, <0>, <0>, <0>, <0>; 2521 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2522 "dsi0_phy_pll_out_byteclk", 2523 "dsi0_phy_pll_out_dsiclk", 2524 "dp_phy_pll_link_clk", 2525 "dp_phy_pll_vco_div_clk", 2526 "edp_phy_pll_link_clk", 2527 "edp_phy_pll_vco_div_clk"; 2528 #clock-cells = <1>; 2529 #reset-cells = <1>; 2530 #power-domain-cells = <1>; 2531 }; 2532 2533 pdc: interrupt-controller@b220000 { 2534 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2535 reg = <0 0x0b220000 0 0x30000>; 2536 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2537 <55 306 4>, <59 312 3>, <62 374 2>, 2538 <64 434 2>, <66 438 3>, <69 86 1>, 2539 <70 520 54>, <124 609 31>, <155 63 1>, 2540 <156 716 12>; 2541 #interrupt-cells = <2>; 2542 interrupt-parent = <&intc>; 2543 interrupt-controller; 2544 }; 2545 2546 pdc_reset: reset-controller@b5e0000 { 2547 compatible = "qcom,sc7280-pdc-global"; 2548 reg = <0 0x0b5e0000 0 0x20000>; 2549 #reset-cells = <1>; 2550 }; 2551 2552 tsens0: thermal-sensor@c263000 { 2553 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2554 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2555 <0 0x0c222000 0 0x1ff>; /* SROT */ 2556 #qcom,sensors = <15>; 2557 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2558 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2559 interrupt-names = "uplow","critical"; 2560 #thermal-sensor-cells = <1>; 2561 }; 2562 2563 tsens1: thermal-sensor@c265000 { 2564 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2565 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2566 <0 0x0c223000 0 0x1ff>; /* SROT */ 2567 #qcom,sensors = <12>; 2568 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2569 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2570 interrupt-names = "uplow","critical"; 2571 #thermal-sensor-cells = <1>; 2572 }; 2573 2574 aoss_reset: reset-controller@c2a0000 { 2575 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2576 reg = <0 0x0c2a0000 0 0x31000>; 2577 #reset-cells = <1>; 2578 }; 2579 2580 aoss_qmp: power-controller@c300000 { 2581 compatible = "qcom,sc7280-aoss-qmp"; 2582 reg = <0 0x0c300000 0 0x100000>; 2583 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2584 IPCC_MPROC_SIGNAL_GLINK_QMP 2585 IRQ_TYPE_EDGE_RISING>; 2586 mboxes = <&ipcc IPCC_CLIENT_AOP 2587 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2588 2589 #clock-cells = <0>; 2590 }; 2591 2592 spmi_bus: spmi@c440000 { 2593 compatible = "qcom,spmi-pmic-arb"; 2594 reg = <0 0x0c440000 0 0x1100>, 2595 <0 0x0c600000 0 0x2000000>, 2596 <0 0x0e600000 0 0x100000>, 2597 <0 0x0e700000 0 0xa0000>, 2598 <0 0x0c40a000 0 0x26000>; 2599 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2600 interrupt-names = "periph_irq"; 2601 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2602 qcom,ee = <0>; 2603 qcom,channel = <0>; 2604 #address-cells = <1>; 2605 #size-cells = <1>; 2606 interrupt-controller; 2607 #interrupt-cells = <4>; 2608 }; 2609 2610 tlmm: pinctrl@f100000 { 2611 compatible = "qcom,sc7280-pinctrl"; 2612 reg = <0 0x0f100000 0 0x300000>; 2613 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2614 gpio-controller; 2615 #gpio-cells = <2>; 2616 interrupt-controller; 2617 #interrupt-cells = <2>; 2618 gpio-ranges = <&tlmm 0 0 175>; 2619 wakeup-parent = <&pdc>; 2620 2621 qspi_clk: qspi-clk { 2622 pins = "gpio14"; 2623 function = "qspi_clk"; 2624 }; 2625 2626 qspi_cs0: qspi-cs0 { 2627 pins = "gpio15"; 2628 function = "qspi_cs"; 2629 }; 2630 2631 qspi_cs1: qspi-cs1 { 2632 pins = "gpio19"; 2633 function = "qspi_cs"; 2634 }; 2635 2636 qspi_data01: qspi-data01 { 2637 pins = "gpio12", "gpio13"; 2638 function = "qspi_data"; 2639 }; 2640 2641 qspi_data12: qspi-data12 { 2642 pins = "gpio16", "gpio17"; 2643 function = "qspi_data"; 2644 }; 2645 2646 qup_i2c0_data_clk: qup-i2c0-data-clk { 2647 pins = "gpio0", "gpio1"; 2648 function = "qup00"; 2649 }; 2650 2651 qup_i2c1_data_clk: qup-i2c1-data-clk { 2652 pins = "gpio4", "gpio5"; 2653 function = "qup01"; 2654 }; 2655 2656 qup_i2c2_data_clk: qup-i2c2-data-clk { 2657 pins = "gpio8", "gpio9"; 2658 function = "qup02"; 2659 }; 2660 2661 qup_i2c3_data_clk: qup-i2c3-data-clk { 2662 pins = "gpio12", "gpio13"; 2663 function = "qup03"; 2664 }; 2665 2666 qup_i2c4_data_clk: qup-i2c4-data-clk { 2667 pins = "gpio16", "gpio17"; 2668 function = "qup04"; 2669 }; 2670 2671 qup_i2c5_data_clk: qup-i2c5-data-clk { 2672 pins = "gpio20", "gpio21"; 2673 function = "qup05"; 2674 }; 2675 2676 qup_i2c6_data_clk: qup-i2c6-data-clk { 2677 pins = "gpio24", "gpio25"; 2678 function = "qup06"; 2679 }; 2680 2681 qup_i2c7_data_clk: qup-i2c7-data-clk { 2682 pins = "gpio28", "gpio29"; 2683 function = "qup07"; 2684 }; 2685 2686 qup_i2c8_data_clk: qup-i2c8-data-clk { 2687 pins = "gpio32", "gpio33"; 2688 function = "qup10"; 2689 }; 2690 2691 qup_i2c9_data_clk: qup-i2c9-data-clk { 2692 pins = "gpio36", "gpio37"; 2693 function = "qup11"; 2694 }; 2695 2696 qup_i2c10_data_clk: qup-i2c10-data-clk { 2697 pins = "gpio40", "gpio41"; 2698 function = "qup12"; 2699 }; 2700 2701 qup_i2c11_data_clk: qup-i2c11-data-clk { 2702 pins = "gpio44", "gpio45"; 2703 function = "qup13"; 2704 }; 2705 2706 qup_i2c12_data_clk: qup-i2c12-data-clk { 2707 pins = "gpio48", "gpio49"; 2708 function = "qup14"; 2709 }; 2710 2711 qup_i2c13_data_clk: qup-i2c13-data-clk { 2712 pins = "gpio52", "gpio53"; 2713 function = "qup15"; 2714 }; 2715 2716 qup_i2c14_data_clk: qup-i2c14-data-clk { 2717 pins = "gpio56", "gpio57"; 2718 function = "qup16"; 2719 }; 2720 2721 qup_i2c15_data_clk: qup-i2c15-data-clk { 2722 pins = "gpio60", "gpio61"; 2723 function = "qup17"; 2724 }; 2725 2726 qup_spi0_data_clk: qup-spi0-data-clk { 2727 pins = "gpio0", "gpio1", "gpio2"; 2728 function = "qup00"; 2729 }; 2730 2731 qup_spi0_cs: qup-spi0-cs { 2732 pins = "gpio3"; 2733 function = "qup00"; 2734 }; 2735 2736 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2737 pins = "gpio3"; 2738 function = "gpio"; 2739 }; 2740 2741 qup_spi1_data_clk: qup-spi1-data-clk { 2742 pins = "gpio4", "gpio5", "gpio6"; 2743 function = "qup01"; 2744 }; 2745 2746 qup_spi1_cs: qup-spi1-cs { 2747 pins = "gpio7"; 2748 function = "qup01"; 2749 }; 2750 2751 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2752 pins = "gpio7"; 2753 function = "gpio"; 2754 }; 2755 2756 qup_spi2_data_clk: qup-spi2-data-clk { 2757 pins = "gpio8", "gpio9", "gpio10"; 2758 function = "qup02"; 2759 }; 2760 2761 qup_spi2_cs: qup-spi2-cs { 2762 pins = "gpio11"; 2763 function = "qup02"; 2764 }; 2765 2766 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2767 pins = "gpio11"; 2768 function = "gpio"; 2769 }; 2770 2771 qup_spi3_data_clk: qup-spi3-data-clk { 2772 pins = "gpio12", "gpio13", "gpio14"; 2773 function = "qup03"; 2774 }; 2775 2776 qup_spi3_cs: qup-spi3-cs { 2777 pins = "gpio15"; 2778 function = "qup03"; 2779 }; 2780 2781 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2782 pins = "gpio15"; 2783 function = "gpio"; 2784 }; 2785 2786 qup_spi4_data_clk: qup-spi4-data-clk { 2787 pins = "gpio16", "gpio17", "gpio18"; 2788 function = "qup04"; 2789 }; 2790 2791 qup_spi4_cs: qup-spi4-cs { 2792 pins = "gpio19"; 2793 function = "qup04"; 2794 }; 2795 2796 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2797 pins = "gpio19"; 2798 function = "gpio"; 2799 }; 2800 2801 qup_spi5_data_clk: qup-spi5-data-clk { 2802 pins = "gpio20", "gpio21", "gpio22"; 2803 function = "qup05"; 2804 }; 2805 2806 qup_spi5_cs: qup-spi5-cs { 2807 pins = "gpio23"; 2808 function = "qup05"; 2809 }; 2810 2811 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2812 pins = "gpio23"; 2813 function = "gpio"; 2814 }; 2815 2816 qup_spi6_data_clk: qup-spi6-data-clk { 2817 pins = "gpio24", "gpio25", "gpio26"; 2818 function = "qup06"; 2819 }; 2820 2821 qup_spi6_cs: qup-spi6-cs { 2822 pins = "gpio27"; 2823 function = "qup06"; 2824 }; 2825 2826 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2827 pins = "gpio27"; 2828 function = "gpio"; 2829 }; 2830 2831 qup_spi7_data_clk: qup-spi7-data-clk { 2832 pins = "gpio28", "gpio29", "gpio30"; 2833 function = "qup07"; 2834 }; 2835 2836 qup_spi7_cs: qup-spi7-cs { 2837 pins = "gpio31"; 2838 function = "qup07"; 2839 }; 2840 2841 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2842 pins = "gpio31"; 2843 function = "gpio"; 2844 }; 2845 2846 qup_spi8_data_clk: qup-spi8-data-clk { 2847 pins = "gpio32", "gpio33", "gpio34"; 2848 function = "qup10"; 2849 }; 2850 2851 qup_spi8_cs: qup-spi8-cs { 2852 pins = "gpio35"; 2853 function = "qup10"; 2854 }; 2855 2856 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 2857 pins = "gpio35"; 2858 function = "gpio"; 2859 }; 2860 2861 qup_spi9_data_clk: qup-spi9-data-clk { 2862 pins = "gpio36", "gpio37", "gpio38"; 2863 function = "qup11"; 2864 }; 2865 2866 qup_spi9_cs: qup-spi9-cs { 2867 pins = "gpio39"; 2868 function = "qup11"; 2869 }; 2870 2871 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 2872 pins = "gpio39"; 2873 function = "gpio"; 2874 }; 2875 2876 qup_spi10_data_clk: qup-spi10-data-clk { 2877 pins = "gpio40", "gpio41", "gpio42"; 2878 function = "qup12"; 2879 }; 2880 2881 qup_spi10_cs: qup-spi10-cs { 2882 pins = "gpio43"; 2883 function = "qup12"; 2884 }; 2885 2886 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 2887 pins = "gpio43"; 2888 function = "gpio"; 2889 }; 2890 2891 qup_spi11_data_clk: qup-spi11-data-clk { 2892 pins = "gpio44", "gpio45", "gpio46"; 2893 function = "qup13"; 2894 }; 2895 2896 qup_spi11_cs: qup-spi11-cs { 2897 pins = "gpio47"; 2898 function = "qup13"; 2899 }; 2900 2901 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 2902 pins = "gpio47"; 2903 function = "gpio"; 2904 }; 2905 2906 qup_spi12_data_clk: qup-spi12-data-clk { 2907 pins = "gpio48", "gpio49", "gpio50"; 2908 function = "qup14"; 2909 }; 2910 2911 qup_spi12_cs: qup-spi12-cs { 2912 pins = "gpio51"; 2913 function = "qup14"; 2914 }; 2915 2916 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 2917 pins = "gpio51"; 2918 function = "gpio"; 2919 }; 2920 2921 qup_spi13_data_clk: qup-spi13-data-clk { 2922 pins = "gpio52", "gpio53", "gpio54"; 2923 function = "qup15"; 2924 }; 2925 2926 qup_spi13_cs: qup-spi13-cs { 2927 pins = "gpio55"; 2928 function = "qup15"; 2929 }; 2930 2931 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 2932 pins = "gpio55"; 2933 function = "gpio"; 2934 }; 2935 2936 qup_spi14_data_clk: qup-spi14-data-clk { 2937 pins = "gpio56", "gpio57", "gpio58"; 2938 function = "qup16"; 2939 }; 2940 2941 qup_spi14_cs: qup-spi14-cs { 2942 pins = "gpio59"; 2943 function = "qup16"; 2944 }; 2945 2946 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 2947 pins = "gpio59"; 2948 function = "gpio"; 2949 }; 2950 2951 qup_spi15_data_clk: qup-spi15-data-clk { 2952 pins = "gpio60", "gpio61", "gpio62"; 2953 function = "qup17"; 2954 }; 2955 2956 qup_spi15_cs: qup-spi15-cs { 2957 pins = "gpio63"; 2958 function = "qup17"; 2959 }; 2960 2961 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 2962 pins = "gpio63"; 2963 function = "gpio"; 2964 }; 2965 2966 qup_uart0_cts: qup-uart0-cts { 2967 pins = "gpio0"; 2968 function = "qup00"; 2969 }; 2970 2971 qup_uart0_rts: qup-uart0-rts { 2972 pins = "gpio1"; 2973 function = "qup00"; 2974 }; 2975 2976 qup_uart0_tx: qup-uart0-tx { 2977 pins = "gpio2"; 2978 function = "qup00"; 2979 }; 2980 2981 qup_uart0_rx: qup-uart0-rx { 2982 pins = "gpio3"; 2983 function = "qup00"; 2984 }; 2985 2986 qup_uart1_cts: qup-uart1-cts { 2987 pins = "gpio4"; 2988 function = "qup01"; 2989 }; 2990 2991 qup_uart1_rts: qup-uart1-rts { 2992 pins = "gpio5"; 2993 function = "qup01"; 2994 }; 2995 2996 qup_uart1_tx: qup-uart1-tx { 2997 pins = "gpio6"; 2998 function = "qup01"; 2999 }; 3000 3001 qup_uart1_rx: qup-uart1-rx { 3002 pins = "gpio7"; 3003 function = "qup01"; 3004 }; 3005 3006 qup_uart2_cts: qup-uart2-cts { 3007 pins = "gpio8"; 3008 function = "qup02"; 3009 }; 3010 3011 qup_uart2_rts: qup-uart2-rts { 3012 pins = "gpio9"; 3013 function = "qup02"; 3014 }; 3015 3016 qup_uart2_tx: qup-uart2-tx { 3017 pins = "gpio10"; 3018 function = "qup02"; 3019 }; 3020 3021 qup_uart2_rx: qup-uart2-rx { 3022 pins = "gpio11"; 3023 function = "qup02"; 3024 }; 3025 3026 qup_uart3_cts: qup-uart3-cts { 3027 pins = "gpio12"; 3028 function = "qup03"; 3029 }; 3030 3031 qup_uart3_rts: qup-uart3-rts { 3032 pins = "gpio13"; 3033 function = "qup03"; 3034 }; 3035 3036 qup_uart3_tx: qup-uart3-tx { 3037 pins = "gpio14"; 3038 function = "qup03"; 3039 }; 3040 3041 qup_uart3_rx: qup-uart3-rx { 3042 pins = "gpio15"; 3043 function = "qup03"; 3044 }; 3045 3046 qup_uart4_cts: qup-uart4-cts { 3047 pins = "gpio16"; 3048 function = "qup04"; 3049 }; 3050 3051 qup_uart4_rts: qup-uart4-rts { 3052 pins = "gpio17"; 3053 function = "qup04"; 3054 }; 3055 3056 qup_uart4_tx: qup-uart4-tx { 3057 pins = "gpio18"; 3058 function = "qup04"; 3059 }; 3060 3061 qup_uart4_rx: qup-uart4-rx { 3062 pins = "gpio19"; 3063 function = "qup04"; 3064 }; 3065 3066 qup_uart5_cts: qup-uart5-cts { 3067 pins = "gpio20"; 3068 function = "qup05"; 3069 }; 3070 3071 qup_uart5_rts: qup-uart5-rts { 3072 pins = "gpio21"; 3073 function = "qup05"; 3074 }; 3075 3076 qup_uart5_tx: qup-uart5-tx { 3077 pins = "gpio22"; 3078 function = "qup05"; 3079 }; 3080 3081 qup_uart5_rx: qup-uart5-rx { 3082 pins = "gpio23"; 3083 function = "qup05"; 3084 }; 3085 3086 qup_uart6_cts: qup-uart6-cts { 3087 pins = "gpio24"; 3088 function = "qup06"; 3089 }; 3090 3091 qup_uart6_rts: qup-uart6-rts { 3092 pins = "gpio25"; 3093 function = "qup06"; 3094 }; 3095 3096 qup_uart6_tx: qup-uart6-tx { 3097 pins = "gpio26"; 3098 function = "qup06"; 3099 }; 3100 3101 qup_uart6_rx: qup-uart6-rx { 3102 pins = "gpio27"; 3103 function = "qup06"; 3104 }; 3105 3106 qup_uart7_cts: qup-uart7-cts { 3107 pins = "gpio28"; 3108 function = "qup07"; 3109 }; 3110 3111 qup_uart7_rts: qup-uart7-rts { 3112 pins = "gpio29"; 3113 function = "qup07"; 3114 }; 3115 3116 qup_uart7_tx: qup-uart7-tx { 3117 pins = "gpio30"; 3118 function = "qup07"; 3119 }; 3120 3121 qup_uart7_rx: qup-uart7-rx { 3122 pins = "gpio31"; 3123 function = "qup07"; 3124 }; 3125 3126 sdc1_on: sdc1-on { 3127 clk { 3128 pins = "sdc1_clk"; 3129 }; 3130 3131 cmd { 3132 pins = "sdc1_cmd"; 3133 }; 3134 3135 data { 3136 pins = "sdc1_data"; 3137 }; 3138 3139 rclk { 3140 pins = "sdc1_rclk"; 3141 }; 3142 }; 3143 3144 sdc1_off: sdc1-off { 3145 clk { 3146 pins = "sdc1_clk"; 3147 drive-strength = <2>; 3148 bias-bus-hold; 3149 }; 3150 3151 cmd { 3152 pins = "sdc1_cmd"; 3153 drive-strength = <2>; 3154 bias-bus-hold; 3155 }; 3156 3157 data { 3158 pins = "sdc1_data"; 3159 drive-strength = <2>; 3160 bias-bus-hold; 3161 }; 3162 3163 rclk { 3164 pins = "sdc1_rclk"; 3165 bias-bus-hold; 3166 }; 3167 }; 3168 3169 sdc2_on: sdc2-on { 3170 clk { 3171 pins = "sdc2_clk"; 3172 }; 3173 3174 cmd { 3175 pins = "sdc2_cmd"; 3176 }; 3177 3178 data { 3179 pins = "sdc2_data"; 3180 }; 3181 }; 3182 3183 sdc2_off: sdc2-off { 3184 clk { 3185 pins = "sdc2_clk"; 3186 drive-strength = <2>; 3187 bias-bus-hold; 3188 }; 3189 3190 cmd { 3191 pins ="sdc2_cmd"; 3192 drive-strength = <2>; 3193 bias-bus-hold; 3194 }; 3195 3196 data { 3197 pins ="sdc2_data"; 3198 drive-strength = <2>; 3199 bias-bus-hold; 3200 }; 3201 }; 3202 3203 qup_uart8_cts: qup-uart8-cts { 3204 pins = "gpio32"; 3205 function = "qup10"; 3206 }; 3207 3208 qup_uart8_rts: qup-uart8-rts { 3209 pins = "gpio33"; 3210 function = "qup10"; 3211 }; 3212 3213 qup_uart8_tx: qup-uart8-tx { 3214 pins = "gpio34"; 3215 function = "qup10"; 3216 }; 3217 3218 qup_uart8_rx: qup-uart8-rx { 3219 pins = "gpio35"; 3220 function = "qup10"; 3221 }; 3222 3223 qup_uart9_cts: qup-uart9-cts { 3224 pins = "gpio36"; 3225 function = "qup11"; 3226 }; 3227 3228 qup_uart9_rts: qup-uart9-rts { 3229 pins = "gpio37"; 3230 function = "qup11"; 3231 }; 3232 3233 qup_uart9_tx: qup-uart9-tx { 3234 pins = "gpio38"; 3235 function = "qup11"; 3236 }; 3237 3238 qup_uart9_rx: qup-uart9-rx { 3239 pins = "gpio39"; 3240 function = "qup11"; 3241 }; 3242 3243 qup_uart10_cts: qup-uart10-cts { 3244 pins = "gpio40"; 3245 function = "qup12"; 3246 }; 3247 3248 qup_uart10_rts: qup-uart10-rts { 3249 pins = "gpio41"; 3250 function = "qup12"; 3251 }; 3252 3253 qup_uart10_tx: qup-uart10-tx { 3254 pins = "gpio42"; 3255 function = "qup12"; 3256 }; 3257 3258 qup_uart10_rx: qup-uart10-rx { 3259 pins = "gpio43"; 3260 function = "qup12"; 3261 }; 3262 3263 qup_uart11_cts: qup-uart11-cts { 3264 pins = "gpio44"; 3265 function = "qup13"; 3266 }; 3267 3268 qup_uart11_rts: qup-uart11-rts { 3269 pins = "gpio45"; 3270 function = "qup13"; 3271 }; 3272 3273 qup_uart11_tx: qup-uart11-tx { 3274 pins = "gpio46"; 3275 function = "qup13"; 3276 }; 3277 3278 qup_uart11_rx: qup-uart11-rx { 3279 pins = "gpio47"; 3280 function = "qup13"; 3281 }; 3282 3283 qup_uart12_cts: qup-uart12-cts { 3284 pins = "gpio48"; 3285 function = "qup14"; 3286 }; 3287 3288 qup_uart12_rts: qup-uart12-rts { 3289 pins = "gpio49"; 3290 function = "qup14"; 3291 }; 3292 3293 qup_uart12_tx: qup-uart12-tx { 3294 pins = "gpio50"; 3295 function = "qup14"; 3296 }; 3297 3298 qup_uart12_rx: qup-uart12-rx { 3299 pins = "gpio51"; 3300 function = "qup14"; 3301 }; 3302 3303 qup_uart13_cts: qup-uart13-cts { 3304 pins = "gpio52"; 3305 function = "qup15"; 3306 }; 3307 3308 qup_uart13_rts: qup-uart13-rts { 3309 pins = "gpio53"; 3310 function = "qup15"; 3311 }; 3312 3313 qup_uart13_tx: qup-uart13-tx { 3314 pins = "gpio54"; 3315 function = "qup15"; 3316 }; 3317 3318 qup_uart13_rx: qup-uart13-rx { 3319 pins = "gpio55"; 3320 function = "qup15"; 3321 }; 3322 3323 qup_uart14_cts: qup-uart14-cts { 3324 pins = "gpio56"; 3325 function = "qup16"; 3326 }; 3327 3328 qup_uart14_rts: qup-uart14-rts { 3329 pins = "gpio57"; 3330 function = "qup16"; 3331 }; 3332 3333 qup_uart14_tx: qup-uart14-tx { 3334 pins = "gpio58"; 3335 function = "qup16"; 3336 }; 3337 3338 qup_uart14_rx: qup-uart14-rx { 3339 pins = "gpio59"; 3340 function = "qup16"; 3341 }; 3342 3343 qup_uart15_cts: qup-uart15-cts { 3344 pins = "gpio60"; 3345 function = "qup17"; 3346 }; 3347 3348 qup_uart15_rts: qup-uart15-rts { 3349 pins = "gpio61"; 3350 function = "qup17"; 3351 }; 3352 3353 qup_uart15_tx: qup-uart15-tx { 3354 pins = "gpio62"; 3355 function = "qup17"; 3356 }; 3357 3358 qup_uart15_rx: qup-uart15-rx { 3359 pins = "gpio63"; 3360 function = "qup17"; 3361 }; 3362 }; 3363 3364 apps_smmu: iommu@15000000 { 3365 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3366 reg = <0 0x15000000 0 0x100000>; 3367 #iommu-cells = <2>; 3368 #global-interrupts = <1>; 3369 dma-coherent; 3370 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3451 }; 3452 3453 intc: interrupt-controller@17a00000 { 3454 compatible = "arm,gic-v3"; 3455 #address-cells = <2>; 3456 #size-cells = <2>; 3457 ranges; 3458 #interrupt-cells = <3>; 3459 interrupt-controller; 3460 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3461 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3462 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3463 3464 gic-its@17a40000 { 3465 compatible = "arm,gic-v3-its"; 3466 msi-controller; 3467 #msi-cells = <1>; 3468 reg = <0 0x17a40000 0 0x20000>; 3469 status = "disabled"; 3470 }; 3471 }; 3472 3473 watchdog@17c10000 { 3474 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3475 reg = <0 0x17c10000 0 0x1000>; 3476 clocks = <&sleep_clk>; 3477 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3478 }; 3479 3480 timer@17c20000 { 3481 #address-cells = <2>; 3482 #size-cells = <2>; 3483 ranges; 3484 compatible = "arm,armv7-timer-mem"; 3485 reg = <0 0x17c20000 0 0x1000>; 3486 3487 frame@17c21000 { 3488 frame-number = <0>; 3489 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3491 reg = <0 0x17c21000 0 0x1000>, 3492 <0 0x17c22000 0 0x1000>; 3493 }; 3494 3495 frame@17c23000 { 3496 frame-number = <1>; 3497 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3498 reg = <0 0x17c23000 0 0x1000>; 3499 status = "disabled"; 3500 }; 3501 3502 frame@17c25000 { 3503 frame-number = <2>; 3504 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3505 reg = <0 0x17c25000 0 0x1000>; 3506 status = "disabled"; 3507 }; 3508 3509 frame@17c27000 { 3510 frame-number = <3>; 3511 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3512 reg = <0 0x17c27000 0 0x1000>; 3513 status = "disabled"; 3514 }; 3515 3516 frame@17c29000 { 3517 frame-number = <4>; 3518 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3519 reg = <0 0x17c29000 0 0x1000>; 3520 status = "disabled"; 3521 }; 3522 3523 frame@17c2b000 { 3524 frame-number = <5>; 3525 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3526 reg = <0 0x17c2b000 0 0x1000>; 3527 status = "disabled"; 3528 }; 3529 3530 frame@17c2d000 { 3531 frame-number = <6>; 3532 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3533 reg = <0 0x17c2d000 0 0x1000>; 3534 status = "disabled"; 3535 }; 3536 }; 3537 3538 apps_rsc: rsc@18200000 { 3539 compatible = "qcom,rpmh-rsc"; 3540 reg = <0 0x18200000 0 0x10000>, 3541 <0 0x18210000 0 0x10000>, 3542 <0 0x18220000 0 0x10000>; 3543 reg-names = "drv-0", "drv-1", "drv-2"; 3544 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3547 qcom,tcs-offset = <0xd00>; 3548 qcom,drv-id = <2>; 3549 qcom,tcs-config = <ACTIVE_TCS 2>, 3550 <SLEEP_TCS 3>, 3551 <WAKE_TCS 3>, 3552 <CONTROL_TCS 1>; 3553 3554 apps_bcm_voter: bcm-voter { 3555 compatible = "qcom,bcm-voter"; 3556 }; 3557 3558 rpmhpd: power-controller { 3559 compatible = "qcom,sc7280-rpmhpd"; 3560 #power-domain-cells = <1>; 3561 operating-points-v2 = <&rpmhpd_opp_table>; 3562 3563 rpmhpd_opp_table: opp-table { 3564 compatible = "operating-points-v2"; 3565 3566 rpmhpd_opp_ret: opp1 { 3567 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3568 }; 3569 3570 rpmhpd_opp_low_svs: opp2 { 3571 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3572 }; 3573 3574 rpmhpd_opp_svs: opp3 { 3575 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3576 }; 3577 3578 rpmhpd_opp_svs_l1: opp4 { 3579 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3580 }; 3581 3582 rpmhpd_opp_svs_l2: opp5 { 3583 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3584 }; 3585 3586 rpmhpd_opp_nom: opp6 { 3587 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3588 }; 3589 3590 rpmhpd_opp_nom_l1: opp7 { 3591 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3592 }; 3593 3594 rpmhpd_opp_turbo: opp8 { 3595 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3596 }; 3597 3598 rpmhpd_opp_turbo_l1: opp9 { 3599 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3600 }; 3601 }; 3602 }; 3603 3604 rpmhcc: clock-controller { 3605 compatible = "qcom,sc7280-rpmh-clk"; 3606 clocks = <&xo_board>; 3607 clock-names = "xo"; 3608 #clock-cells = <1>; 3609 }; 3610 }; 3611 3612 cpufreq_hw: cpufreq@18591000 { 3613 compatible = "qcom,cpufreq-epss"; 3614 reg = <0 0x18591100 0 0x900>, 3615 <0 0x18592100 0 0x900>, 3616 <0 0x18593100 0 0x900>; 3617 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3618 clock-names = "xo", "alternate"; 3619 #freq-domain-cells = <1>; 3620 }; 3621 }; 3622 3623 thermal_zones: thermal-zones { 3624 cpu0-thermal { 3625 polling-delay-passive = <250>; 3626 polling-delay = <0>; 3627 3628 thermal-sensors = <&tsens0 1>; 3629 3630 trips { 3631 cpu0_alert0: trip-point0 { 3632 temperature = <90000>; 3633 hysteresis = <2000>; 3634 type = "passive"; 3635 }; 3636 3637 cpu0_alert1: trip-point1 { 3638 temperature = <95000>; 3639 hysteresis = <2000>; 3640 type = "passive"; 3641 }; 3642 3643 cpu0_crit: cpu-crit { 3644 temperature = <110000>; 3645 hysteresis = <0>; 3646 type = "critical"; 3647 }; 3648 }; 3649 3650 cooling-maps { 3651 map0 { 3652 trip = <&cpu0_alert0>; 3653 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3654 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3655 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3656 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3657 }; 3658 map1 { 3659 trip = <&cpu0_alert1>; 3660 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3661 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3662 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3663 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3664 }; 3665 }; 3666 }; 3667 3668 cpu1-thermal { 3669 polling-delay-passive = <250>; 3670 polling-delay = <0>; 3671 3672 thermal-sensors = <&tsens0 2>; 3673 3674 trips { 3675 cpu1_alert0: trip-point0 { 3676 temperature = <90000>; 3677 hysteresis = <2000>; 3678 type = "passive"; 3679 }; 3680 3681 cpu1_alert1: trip-point1 { 3682 temperature = <95000>; 3683 hysteresis = <2000>; 3684 type = "passive"; 3685 }; 3686 3687 cpu1_crit: cpu-crit { 3688 temperature = <110000>; 3689 hysteresis = <0>; 3690 type = "critical"; 3691 }; 3692 }; 3693 3694 cooling-maps { 3695 map0 { 3696 trip = <&cpu1_alert0>; 3697 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3699 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3700 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3701 }; 3702 map1 { 3703 trip = <&cpu1_alert1>; 3704 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3705 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3706 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3707 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3708 }; 3709 }; 3710 }; 3711 3712 cpu2-thermal { 3713 polling-delay-passive = <250>; 3714 polling-delay = <0>; 3715 3716 thermal-sensors = <&tsens0 3>; 3717 3718 trips { 3719 cpu2_alert0: trip-point0 { 3720 temperature = <90000>; 3721 hysteresis = <2000>; 3722 type = "passive"; 3723 }; 3724 3725 cpu2_alert1: trip-point1 { 3726 temperature = <95000>; 3727 hysteresis = <2000>; 3728 type = "passive"; 3729 }; 3730 3731 cpu2_crit: cpu-crit { 3732 temperature = <110000>; 3733 hysteresis = <0>; 3734 type = "critical"; 3735 }; 3736 }; 3737 3738 cooling-maps { 3739 map0 { 3740 trip = <&cpu2_alert0>; 3741 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3743 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3745 }; 3746 map1 { 3747 trip = <&cpu2_alert1>; 3748 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3749 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3750 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3751 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3752 }; 3753 }; 3754 }; 3755 3756 cpu3-thermal { 3757 polling-delay-passive = <250>; 3758 polling-delay = <0>; 3759 3760 thermal-sensors = <&tsens0 4>; 3761 3762 trips { 3763 cpu3_alert0: trip-point0 { 3764 temperature = <90000>; 3765 hysteresis = <2000>; 3766 type = "passive"; 3767 }; 3768 3769 cpu3_alert1: trip-point1 { 3770 temperature = <95000>; 3771 hysteresis = <2000>; 3772 type = "passive"; 3773 }; 3774 3775 cpu3_crit: cpu-crit { 3776 temperature = <110000>; 3777 hysteresis = <0>; 3778 type = "critical"; 3779 }; 3780 }; 3781 3782 cooling-maps { 3783 map0 { 3784 trip = <&cpu3_alert0>; 3785 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3788 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3789 }; 3790 map1 { 3791 trip = <&cpu3_alert1>; 3792 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3795 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3796 }; 3797 }; 3798 }; 3799 3800 cpu4-thermal { 3801 polling-delay-passive = <250>; 3802 polling-delay = <0>; 3803 3804 thermal-sensors = <&tsens0 7>; 3805 3806 trips { 3807 cpu4_alert0: trip-point0 { 3808 temperature = <90000>; 3809 hysteresis = <2000>; 3810 type = "passive"; 3811 }; 3812 3813 cpu4_alert1: trip-point1 { 3814 temperature = <95000>; 3815 hysteresis = <2000>; 3816 type = "passive"; 3817 }; 3818 3819 cpu4_crit: cpu-crit { 3820 temperature = <110000>; 3821 hysteresis = <0>; 3822 type = "critical"; 3823 }; 3824 }; 3825 3826 cooling-maps { 3827 map0 { 3828 trip = <&cpu4_alert0>; 3829 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3831 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3832 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3833 }; 3834 map1 { 3835 trip = <&cpu4_alert1>; 3836 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3839 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3840 }; 3841 }; 3842 }; 3843 3844 cpu5-thermal { 3845 polling-delay-passive = <250>; 3846 polling-delay = <0>; 3847 3848 thermal-sensors = <&tsens0 8>; 3849 3850 trips { 3851 cpu5_alert0: trip-point0 { 3852 temperature = <90000>; 3853 hysteresis = <2000>; 3854 type = "passive"; 3855 }; 3856 3857 cpu5_alert1: trip-point1 { 3858 temperature = <95000>; 3859 hysteresis = <2000>; 3860 type = "passive"; 3861 }; 3862 3863 cpu5_crit: cpu-crit { 3864 temperature = <110000>; 3865 hysteresis = <0>; 3866 type = "critical"; 3867 }; 3868 }; 3869 3870 cooling-maps { 3871 map0 { 3872 trip = <&cpu5_alert0>; 3873 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3876 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3877 }; 3878 map1 { 3879 trip = <&cpu5_alert1>; 3880 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3882 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3883 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3884 }; 3885 }; 3886 }; 3887 3888 cpu6-thermal { 3889 polling-delay-passive = <250>; 3890 polling-delay = <0>; 3891 3892 thermal-sensors = <&tsens0 9>; 3893 3894 trips { 3895 cpu6_alert0: trip-point0 { 3896 temperature = <90000>; 3897 hysteresis = <2000>; 3898 type = "passive"; 3899 }; 3900 3901 cpu6_alert1: trip-point1 { 3902 temperature = <95000>; 3903 hysteresis = <2000>; 3904 type = "passive"; 3905 }; 3906 3907 cpu6_crit: cpu-crit { 3908 temperature = <110000>; 3909 hysteresis = <0>; 3910 type = "critical"; 3911 }; 3912 }; 3913 3914 cooling-maps { 3915 map0 { 3916 trip = <&cpu6_alert0>; 3917 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3921 }; 3922 map1 { 3923 trip = <&cpu6_alert1>; 3924 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3926 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3927 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3928 }; 3929 }; 3930 }; 3931 3932 cpu7-thermal { 3933 polling-delay-passive = <250>; 3934 polling-delay = <0>; 3935 3936 thermal-sensors = <&tsens0 10>; 3937 3938 trips { 3939 cpu7_alert0: trip-point0 { 3940 temperature = <90000>; 3941 hysteresis = <2000>; 3942 type = "passive"; 3943 }; 3944 3945 cpu7_alert1: trip-point1 { 3946 temperature = <95000>; 3947 hysteresis = <2000>; 3948 type = "passive"; 3949 }; 3950 3951 cpu7_crit: cpu-crit { 3952 temperature = <110000>; 3953 hysteresis = <0>; 3954 type = "critical"; 3955 }; 3956 }; 3957 3958 cooling-maps { 3959 map0 { 3960 trip = <&cpu7_alert0>; 3961 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3965 }; 3966 map1 { 3967 trip = <&cpu7_alert1>; 3968 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3969 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3971 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3972 }; 3973 }; 3974 }; 3975 3976 cpu8-thermal { 3977 polling-delay-passive = <250>; 3978 polling-delay = <0>; 3979 3980 thermal-sensors = <&tsens0 11>; 3981 3982 trips { 3983 cpu8_alert0: trip-point0 { 3984 temperature = <90000>; 3985 hysteresis = <2000>; 3986 type = "passive"; 3987 }; 3988 3989 cpu8_alert1: trip-point1 { 3990 temperature = <95000>; 3991 hysteresis = <2000>; 3992 type = "passive"; 3993 }; 3994 3995 cpu8_crit: cpu-crit { 3996 temperature = <110000>; 3997 hysteresis = <0>; 3998 type = "critical"; 3999 }; 4000 }; 4001 4002 cooling-maps { 4003 map0 { 4004 trip = <&cpu8_alert0>; 4005 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4007 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4009 }; 4010 map1 { 4011 trip = <&cpu8_alert1>; 4012 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4013 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4014 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4015 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4016 }; 4017 }; 4018 }; 4019 4020 cpu9-thermal { 4021 polling-delay-passive = <250>; 4022 polling-delay = <0>; 4023 4024 thermal-sensors = <&tsens0 12>; 4025 4026 trips { 4027 cpu9_alert0: trip-point0 { 4028 temperature = <90000>; 4029 hysteresis = <2000>; 4030 type = "passive"; 4031 }; 4032 4033 cpu9_alert1: trip-point1 { 4034 temperature = <95000>; 4035 hysteresis = <2000>; 4036 type = "passive"; 4037 }; 4038 4039 cpu9_crit: cpu-crit { 4040 temperature = <110000>; 4041 hysteresis = <0>; 4042 type = "critical"; 4043 }; 4044 }; 4045 4046 cooling-maps { 4047 map0 { 4048 trip = <&cpu9_alert0>; 4049 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4052 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4053 }; 4054 map1 { 4055 trip = <&cpu9_alert1>; 4056 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4057 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4058 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4059 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4060 }; 4061 }; 4062 }; 4063 4064 cpu10-thermal { 4065 polling-delay-passive = <250>; 4066 polling-delay = <0>; 4067 4068 thermal-sensors = <&tsens0 13>; 4069 4070 trips { 4071 cpu10_alert0: trip-point0 { 4072 temperature = <90000>; 4073 hysteresis = <2000>; 4074 type = "passive"; 4075 }; 4076 4077 cpu10_alert1: trip-point1 { 4078 temperature = <95000>; 4079 hysteresis = <2000>; 4080 type = "passive"; 4081 }; 4082 4083 cpu10_crit: cpu-crit { 4084 temperature = <110000>; 4085 hysteresis = <0>; 4086 type = "critical"; 4087 }; 4088 }; 4089 4090 cooling-maps { 4091 map0 { 4092 trip = <&cpu10_alert0>; 4093 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4095 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4096 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4097 }; 4098 map1 { 4099 trip = <&cpu10_alert1>; 4100 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4102 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4103 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4104 }; 4105 }; 4106 }; 4107 4108 cpu11-thermal { 4109 polling-delay-passive = <250>; 4110 polling-delay = <0>; 4111 4112 thermal-sensors = <&tsens0 14>; 4113 4114 trips { 4115 cpu11_alert0: trip-point0 { 4116 temperature = <90000>; 4117 hysteresis = <2000>; 4118 type = "passive"; 4119 }; 4120 4121 cpu11_alert1: trip-point1 { 4122 temperature = <95000>; 4123 hysteresis = <2000>; 4124 type = "passive"; 4125 }; 4126 4127 cpu11_crit: cpu-crit { 4128 temperature = <110000>; 4129 hysteresis = <0>; 4130 type = "critical"; 4131 }; 4132 }; 4133 4134 cooling-maps { 4135 map0 { 4136 trip = <&cpu11_alert0>; 4137 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4140 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4141 }; 4142 map1 { 4143 trip = <&cpu11_alert1>; 4144 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4145 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4146 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4147 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4148 }; 4149 }; 4150 }; 4151 4152 aoss0-thermal { 4153 polling-delay-passive = <0>; 4154 polling-delay = <0>; 4155 4156 thermal-sensors = <&tsens0 0>; 4157 4158 trips { 4159 aoss0_alert0: trip-point0 { 4160 temperature = <90000>; 4161 hysteresis = <2000>; 4162 type = "hot"; 4163 }; 4164 4165 aoss0_crit: aoss0-crit { 4166 temperature = <110000>; 4167 hysteresis = <0>; 4168 type = "critical"; 4169 }; 4170 }; 4171 }; 4172 4173 aoss1-thermal { 4174 polling-delay-passive = <0>; 4175 polling-delay = <0>; 4176 4177 thermal-sensors = <&tsens1 0>; 4178 4179 trips { 4180 aoss1_alert0: trip-point0 { 4181 temperature = <90000>; 4182 hysteresis = <2000>; 4183 type = "hot"; 4184 }; 4185 4186 aoss1_crit: aoss1-crit { 4187 temperature = <110000>; 4188 hysteresis = <0>; 4189 type = "critical"; 4190 }; 4191 }; 4192 }; 4193 4194 cpuss0-thermal { 4195 polling-delay-passive = <0>; 4196 polling-delay = <0>; 4197 4198 thermal-sensors = <&tsens0 5>; 4199 4200 trips { 4201 cpuss0_alert0: trip-point0 { 4202 temperature = <90000>; 4203 hysteresis = <2000>; 4204 type = "hot"; 4205 }; 4206 cpuss0_crit: cluster0-crit { 4207 temperature = <110000>; 4208 hysteresis = <0>; 4209 type = "critical"; 4210 }; 4211 }; 4212 }; 4213 4214 cpuss1-thermal { 4215 polling-delay-passive = <0>; 4216 polling-delay = <0>; 4217 4218 thermal-sensors = <&tsens0 6>; 4219 4220 trips { 4221 cpuss1_alert0: trip-point0 { 4222 temperature = <90000>; 4223 hysteresis = <2000>; 4224 type = "hot"; 4225 }; 4226 cpuss1_crit: cluster0-crit { 4227 temperature = <110000>; 4228 hysteresis = <0>; 4229 type = "critical"; 4230 }; 4231 }; 4232 }; 4233 4234 gpuss0-thermal { 4235 polling-delay-passive = <100>; 4236 polling-delay = <0>; 4237 4238 thermal-sensors = <&tsens1 1>; 4239 4240 trips { 4241 gpuss0_alert0: trip-point0 { 4242 temperature = <95000>; 4243 hysteresis = <2000>; 4244 type = "passive"; 4245 }; 4246 4247 gpuss0_crit: gpuss0-crit { 4248 temperature = <110000>; 4249 hysteresis = <0>; 4250 type = "critical"; 4251 }; 4252 }; 4253 4254 cooling-maps { 4255 map0 { 4256 trip = <&gpuss0_alert0>; 4257 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4258 }; 4259 }; 4260 }; 4261 4262 gpuss1-thermal { 4263 polling-delay-passive = <100>; 4264 polling-delay = <0>; 4265 4266 thermal-sensors = <&tsens1 2>; 4267 4268 trips { 4269 gpuss1_alert0: trip-point0 { 4270 temperature = <95000>; 4271 hysteresis = <2000>; 4272 type = "passive"; 4273 }; 4274 4275 gpuss1_crit: gpuss1-crit { 4276 temperature = <110000>; 4277 hysteresis = <0>; 4278 type = "critical"; 4279 }; 4280 }; 4281 4282 cooling-maps { 4283 map0 { 4284 trip = <&gpuss1_alert0>; 4285 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4286 }; 4287 }; 4288 }; 4289 4290 nspss0-thermal { 4291 polling-delay-passive = <0>; 4292 polling-delay = <0>; 4293 4294 thermal-sensors = <&tsens1 3>; 4295 4296 trips { 4297 nspss0_alert0: trip-point0 { 4298 temperature = <90000>; 4299 hysteresis = <2000>; 4300 type = "hot"; 4301 }; 4302 4303 nspss0_crit: nspss0-crit { 4304 temperature = <110000>; 4305 hysteresis = <0>; 4306 type = "critical"; 4307 }; 4308 }; 4309 }; 4310 4311 nspss1-thermal { 4312 polling-delay-passive = <0>; 4313 polling-delay = <0>; 4314 4315 thermal-sensors = <&tsens1 4>; 4316 4317 trips { 4318 nspss1_alert0: trip-point0 { 4319 temperature = <90000>; 4320 hysteresis = <2000>; 4321 type = "hot"; 4322 }; 4323 4324 nspss1_crit: nspss1-crit { 4325 temperature = <110000>; 4326 hysteresis = <0>; 4327 type = "critical"; 4328 }; 4329 }; 4330 }; 4331 4332 video-thermal { 4333 polling-delay-passive = <0>; 4334 polling-delay = <0>; 4335 4336 thermal-sensors = <&tsens1 5>; 4337 4338 trips { 4339 video_alert0: trip-point0 { 4340 temperature = <90000>; 4341 hysteresis = <2000>; 4342 type = "hot"; 4343 }; 4344 4345 video_crit: video-crit { 4346 temperature = <110000>; 4347 hysteresis = <0>; 4348 type = "critical"; 4349 }; 4350 }; 4351 }; 4352 4353 ddr-thermal { 4354 polling-delay-passive = <0>; 4355 polling-delay = <0>; 4356 4357 thermal-sensors = <&tsens1 6>; 4358 4359 trips { 4360 ddr_alert0: trip-point0 { 4361 temperature = <90000>; 4362 hysteresis = <2000>; 4363 type = "hot"; 4364 }; 4365 4366 ddr_crit: ddr-crit { 4367 temperature = <110000>; 4368 hysteresis = <0>; 4369 type = "critical"; 4370 }; 4371 }; 4372 }; 4373 4374 mdmss0-thermal { 4375 polling-delay-passive = <0>; 4376 polling-delay = <0>; 4377 4378 thermal-sensors = <&tsens1 7>; 4379 4380 trips { 4381 mdmss0_alert0: trip-point0 { 4382 temperature = <90000>; 4383 hysteresis = <2000>; 4384 type = "hot"; 4385 }; 4386 4387 mdmss0_crit: mdmss0-crit { 4388 temperature = <110000>; 4389 hysteresis = <0>; 4390 type = "critical"; 4391 }; 4392 }; 4393 }; 4394 4395 mdmss1-thermal { 4396 polling-delay-passive = <0>; 4397 polling-delay = <0>; 4398 4399 thermal-sensors = <&tsens1 8>; 4400 4401 trips { 4402 mdmss1_alert0: trip-point0 { 4403 temperature = <90000>; 4404 hysteresis = <2000>; 4405 type = "hot"; 4406 }; 4407 4408 mdmss1_crit: mdmss1-crit { 4409 temperature = <110000>; 4410 hysteresis = <0>; 4411 type = "critical"; 4412 }; 4413 }; 4414 }; 4415 4416 mdmss2-thermal { 4417 polling-delay-passive = <0>; 4418 polling-delay = <0>; 4419 4420 thermal-sensors = <&tsens1 9>; 4421 4422 trips { 4423 mdmss2_alert0: trip-point0 { 4424 temperature = <90000>; 4425 hysteresis = <2000>; 4426 type = "hot"; 4427 }; 4428 4429 mdmss2_crit: mdmss2-crit { 4430 temperature = <110000>; 4431 hysteresis = <0>; 4432 type = "critical"; 4433 }; 4434 }; 4435 }; 4436 4437 mdmss3-thermal { 4438 polling-delay-passive = <0>; 4439 polling-delay = <0>; 4440 4441 thermal-sensors = <&tsens1 10>; 4442 4443 trips { 4444 mdmss3_alert0: trip-point0 { 4445 temperature = <90000>; 4446 hysteresis = <2000>; 4447 type = "hot"; 4448 }; 4449 4450 mdmss3_crit: mdmss3-crit { 4451 temperature = <110000>; 4452 hysteresis = <0>; 4453 type = "critical"; 4454 }; 4455 }; 4456 }; 4457 4458 camera0-thermal { 4459 polling-delay-passive = <0>; 4460 polling-delay = <0>; 4461 4462 thermal-sensors = <&tsens1 11>; 4463 4464 trips { 4465 camera0_alert0: trip-point0 { 4466 temperature = <90000>; 4467 hysteresis = <2000>; 4468 type = "hot"; 4469 }; 4470 4471 camera0_crit: camera0-crit { 4472 temperature = <110000>; 4473 hysteresis = <0>; 4474 type = "critical"; 4475 }; 4476 }; 4477 }; 4478 }; 4479 4480 timer { 4481 compatible = "arm,armv8-timer"; 4482 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4483 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4484 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4485 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4486 }; 4487}; 4488