1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 pmu { 758 compatible = "arm,armv8-pmuv3"; 759 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 760 }; 761 762 psci { 763 compatible = "arm,psci-1.0"; 764 method = "smc"; 765 }; 766 767 qspi_opp_table: opp-table-qspi { 768 compatible = "operating-points-v2"; 769 770 opp-75000000 { 771 opp-hz = /bits/ 64 <75000000>; 772 required-opps = <&rpmhpd_opp_low_svs>; 773 }; 774 775 opp-150000000 { 776 opp-hz = /bits/ 64 <150000000>; 777 required-opps = <&rpmhpd_opp_svs>; 778 }; 779 780 opp-200000000 { 781 opp-hz = /bits/ 64 <200000000>; 782 required-opps = <&rpmhpd_opp_svs_l1>; 783 }; 784 785 opp-300000000 { 786 opp-hz = /bits/ 64 <300000000>; 787 required-opps = <&rpmhpd_opp_nom>; 788 }; 789 }; 790 791 qup_opp_table: opp-table-qup { 792 compatible = "operating-points-v2"; 793 794 opp-75000000 { 795 opp-hz = /bits/ 64 <75000000>; 796 required-opps = <&rpmhpd_opp_low_svs>; 797 }; 798 799 opp-100000000 { 800 opp-hz = /bits/ 64 <100000000>; 801 required-opps = <&rpmhpd_opp_svs>; 802 }; 803 804 opp-128000000 { 805 opp-hz = /bits/ 64 <128000000>; 806 required-opps = <&rpmhpd_opp_nom>; 807 }; 808 }; 809 810 soc: soc@0 { 811 #address-cells = <2>; 812 #size-cells = <2>; 813 ranges = <0 0 0 0 0x10 0>; 814 dma-ranges = <0 0 0 0 0x10 0>; 815 compatible = "simple-bus"; 816 817 gcc: clock-controller@100000 { 818 compatible = "qcom,gcc-sc7280"; 819 reg = <0 0x00100000 0 0x1f0000>; 820 clocks = <&rpmhcc RPMH_CXO_CLK>, 821 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 822 <0>, <&pcie1_lane>, 823 <0>, <0>, <0>, <0>; 824 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 825 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 826 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 827 "ufs_phy_tx_symbol_0_clk", 828 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 power-domains = <&rpmhpd SC7280_CX>; 833 }; 834 835 ipcc: mailbox@408000 { 836 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 837 reg = <0 0x00408000 0 0x1000>; 838 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-controller; 840 #interrupt-cells = <3>; 841 #mbox-cells = <2>; 842 }; 843 844 qfprom: efuse@784000 { 845 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 846 reg = <0 0x00784000 0 0xa20>, 847 <0 0x00780000 0 0xa20>, 848 <0 0x00782000 0 0x120>, 849 <0 0x00786000 0 0x1fff>; 850 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 851 clock-names = "core"; 852 power-domains = <&rpmhpd SC7280_MX>; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 856 gpu_speed_bin: gpu_speed_bin@1e9 { 857 reg = <0x1e9 0x2>; 858 bits = <5 8>; 859 }; 860 }; 861 862 sdhc_1: mmc@7c4000 { 863 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 864 pinctrl-names = "default", "sleep"; 865 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 866 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 867 status = "disabled"; 868 869 reg = <0 0x007c4000 0 0x1000>, 870 <0 0x007c5000 0 0x1000>; 871 reg-names = "hc", "cqhci"; 872 873 iommus = <&apps_smmu 0xc0 0x0>; 874 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "hc_irq", "pwr_irq"; 877 878 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 879 <&gcc GCC_SDCC1_APPS_CLK>, 880 <&rpmhcc RPMH_CXO_CLK>; 881 clock-names = "iface", "core", "xo"; 882 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 883 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 884 interconnect-names = "sdhc-ddr","cpu-sdhc"; 885 power-domains = <&rpmhpd SC7280_CX>; 886 operating-points-v2 = <&sdhc1_opp_table>; 887 888 bus-width = <8>; 889 supports-cqe; 890 891 qcom,dll-config = <0x0007642c>; 892 qcom,ddr-config = <0x80040868>; 893 894 mmc-ddr-1_8v; 895 mmc-hs200-1_8v; 896 mmc-hs400-1_8v; 897 mmc-hs400-enhanced-strobe; 898 899 resets = <&gcc GCC_SDCC1_BCR>; 900 901 sdhc1_opp_table: opp-table { 902 compatible = "operating-points-v2"; 903 904 opp-100000000 { 905 opp-hz = /bits/ 64 <100000000>; 906 required-opps = <&rpmhpd_opp_low_svs>; 907 opp-peak-kBps = <1800000 400000>; 908 opp-avg-kBps = <100000 0>; 909 }; 910 911 opp-384000000 { 912 opp-hz = /bits/ 64 <384000000>; 913 required-opps = <&rpmhpd_opp_nom>; 914 opp-peak-kBps = <5400000 1600000>; 915 opp-avg-kBps = <390000 0>; 916 }; 917 }; 918 919 }; 920 921 gpi_dma0: dma-controller@900000 { 922 #dma-cells = <3>; 923 compatible = "qcom,sc7280-gpi-dma"; 924 reg = <0 0x00900000 0 0x60000>; 925 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 937 dma-channels = <12>; 938 dma-channel-mask = <0x7f>; 939 iommus = <&apps_smmu 0x0136 0x0>; 940 status = "disabled"; 941 }; 942 943 qupv3_id_0: geniqup@9c0000 { 944 compatible = "qcom,geni-se-qup"; 945 reg = <0 0x009c0000 0 0x2000>; 946 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 947 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 948 clock-names = "m-ahb", "s-ahb"; 949 #address-cells = <2>; 950 #size-cells = <2>; 951 ranges; 952 iommus = <&apps_smmu 0x123 0x0>; 953 status = "disabled"; 954 955 i2c0: i2c@980000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x00980000 0 0x4000>; 958 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 959 clock-names = "se"; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_i2c0_data_clk>; 962 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 967 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", 969 "qup-memory"; 970 power-domains = <&rpmhpd SC7280_CX>; 971 required-opps = <&rpmhpd_opp_low_svs>; 972 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 973 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 974 dma-names = "tx", "rx"; 975 status = "disabled"; 976 }; 977 978 spi0: spi@980000 { 979 compatible = "qcom,geni-spi"; 980 reg = <0 0x00980000 0 0x4000>; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 982 clock-names = "se"; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 985 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 power-domains = <&rpmhpd SC7280_CX>; 989 operating-points-v2 = <&qup_opp_table>; 990 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 991 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 992 interconnect-names = "qup-core", "qup-config"; 993 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 994 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 995 dma-names = "tx", "rx"; 996 status = "disabled"; 997 }; 998 999 uart0: serial@980000 { 1000 compatible = "qcom,geni-uart"; 1001 reg = <0 0x00980000 0 0x4000>; 1002 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1003 clock-names = "se"; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1006 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1007 power-domains = <&rpmhpd SC7280_CX>; 1008 operating-points-v2 = <&qup_opp_table>; 1009 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1010 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1011 interconnect-names = "qup-core", "qup-config"; 1012 status = "disabled"; 1013 }; 1014 1015 i2c1: i2c@984000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00984000 0 0x4000>; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1019 clock-names = "se"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c1_data_clk>; 1022 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1027 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1028 interconnect-names = "qup-core", "qup-config", 1029 "qup-memory"; 1030 power-domains = <&rpmhpd SC7280_CX>; 1031 required-opps = <&rpmhpd_opp_low_svs>; 1032 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1033 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1034 dma-names = "tx", "rx"; 1035 status = "disabled"; 1036 }; 1037 1038 spi1: spi@984000 { 1039 compatible = "qcom,geni-spi"; 1040 reg = <0 0x00984000 0 0x4000>; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1042 clock-names = "se"; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1045 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 power-domains = <&rpmhpd SC7280_CX>; 1049 operating-points-v2 = <&qup_opp_table>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1052 interconnect-names = "qup-core", "qup-config"; 1053 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1054 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1055 dma-names = "tx", "rx"; 1056 status = "disabled"; 1057 }; 1058 1059 uart1: serial@984000 { 1060 compatible = "qcom,geni-uart"; 1061 reg = <0 0x00984000 0 0x4000>; 1062 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1063 clock-names = "se"; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1066 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1067 power-domains = <&rpmhpd SC7280_CX>; 1068 operating-points-v2 = <&qup_opp_table>; 1069 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1070 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1071 interconnect-names = "qup-core", "qup-config"; 1072 status = "disabled"; 1073 }; 1074 1075 i2c2: i2c@988000 { 1076 compatible = "qcom,geni-i2c"; 1077 reg = <0 0x00988000 0 0x4000>; 1078 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1079 clock-names = "se"; 1080 pinctrl-names = "default"; 1081 pinctrl-0 = <&qup_i2c2_data_clk>; 1082 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1086 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1087 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1088 interconnect-names = "qup-core", "qup-config", 1089 "qup-memory"; 1090 power-domains = <&rpmhpd SC7280_CX>; 1091 required-opps = <&rpmhpd_opp_low_svs>; 1092 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1093 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1094 dma-names = "tx", "rx"; 1095 status = "disabled"; 1096 }; 1097 1098 spi2: spi@988000 { 1099 compatible = "qcom,geni-spi"; 1100 reg = <0 0x00988000 0 0x4000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1102 clock-names = "se"; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1105 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 power-domains = <&rpmhpd SC7280_CX>; 1109 operating-points-v2 = <&qup_opp_table>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1111 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1112 interconnect-names = "qup-core", "qup-config"; 1113 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1114 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1115 dma-names = "tx", "rx"; 1116 status = "disabled"; 1117 }; 1118 1119 uart2: serial@988000 { 1120 compatible = "qcom,geni-uart"; 1121 reg = <0 0x00988000 0 0x4000>; 1122 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1123 clock-names = "se"; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1126 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1127 power-domains = <&rpmhpd SC7280_CX>; 1128 operating-points-v2 = <&qup_opp_table>; 1129 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1130 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1131 interconnect-names = "qup-core", "qup-config"; 1132 status = "disabled"; 1133 }; 1134 1135 i2c3: i2c@98c000 { 1136 compatible = "qcom,geni-i2c"; 1137 reg = <0 0x0098c000 0 0x4000>; 1138 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1139 clock-names = "se"; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_i2c3_data_clk>; 1142 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1146 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1147 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1148 interconnect-names = "qup-core", "qup-config", 1149 "qup-memory"; 1150 power-domains = <&rpmhpd SC7280_CX>; 1151 required-opps = <&rpmhpd_opp_low_svs>; 1152 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1153 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1154 dma-names = "tx", "rx"; 1155 status = "disabled"; 1156 }; 1157 1158 spi3: spi@98c000 { 1159 compatible = "qcom,geni-spi"; 1160 reg = <0 0x0098c000 0 0x4000>; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1162 clock-names = "se"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1165 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 power-domains = <&rpmhpd SC7280_CX>; 1169 operating-points-v2 = <&qup_opp_table>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1174 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1175 dma-names = "tx", "rx"; 1176 status = "disabled"; 1177 }; 1178 1179 uart3: serial@98c000 { 1180 compatible = "qcom,geni-uart"; 1181 reg = <0 0x0098c000 0 0x4000>; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1183 clock-names = "se"; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1186 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1187 power-domains = <&rpmhpd SC7280_CX>; 1188 operating-points-v2 = <&qup_opp_table>; 1189 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1190 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1191 interconnect-names = "qup-core", "qup-config"; 1192 status = "disabled"; 1193 }; 1194 1195 i2c4: i2c@990000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0 0x00990000 0 0x4000>; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1199 clock-names = "se"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_i2c4_data_clk>; 1202 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1206 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1207 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1208 interconnect-names = "qup-core", "qup-config", 1209 "qup-memory"; 1210 power-domains = <&rpmhpd SC7280_CX>; 1211 required-opps = <&rpmhpd_opp_low_svs>; 1212 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1213 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1214 dma-names = "tx", "rx"; 1215 status = "disabled"; 1216 }; 1217 1218 spi4: spi@990000 { 1219 compatible = "qcom,geni-spi"; 1220 reg = <0 0x00990000 0 0x4000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1222 clock-names = "se"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1225 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 power-domains = <&rpmhpd SC7280_CX>; 1229 operating-points-v2 = <&qup_opp_table>; 1230 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1231 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1232 interconnect-names = "qup-core", "qup-config"; 1233 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1234 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1235 dma-names = "tx", "rx"; 1236 status = "disabled"; 1237 }; 1238 1239 uart4: serial@990000 { 1240 compatible = "qcom,geni-uart"; 1241 reg = <0 0x00990000 0 0x4000>; 1242 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1243 clock-names = "se"; 1244 pinctrl-names = "default"; 1245 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1246 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1247 power-domains = <&rpmhpd SC7280_CX>; 1248 operating-points-v2 = <&qup_opp_table>; 1249 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1250 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1251 interconnect-names = "qup-core", "qup-config"; 1252 status = "disabled"; 1253 }; 1254 1255 i2c5: i2c@994000 { 1256 compatible = "qcom,geni-i2c"; 1257 reg = <0 0x00994000 0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1259 clock-names = "se"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_i2c5_data_clk>; 1262 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1267 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1268 interconnect-names = "qup-core", "qup-config", 1269 "qup-memory"; 1270 power-domains = <&rpmhpd SC7280_CX>; 1271 required-opps = <&rpmhpd_opp_low_svs>; 1272 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1273 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1274 dma-names = "tx", "rx"; 1275 status = "disabled"; 1276 }; 1277 1278 spi5: spi@994000 { 1279 compatible = "qcom,geni-spi"; 1280 reg = <0 0x00994000 0 0x4000>; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1282 clock-names = "se"; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1285 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 power-domains = <&rpmhpd SC7280_CX>; 1289 operating-points-v2 = <&qup_opp_table>; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1291 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1292 interconnect-names = "qup-core", "qup-config"; 1293 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1294 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1295 dma-names = "tx", "rx"; 1296 status = "disabled"; 1297 }; 1298 1299 uart5: serial@994000 { 1300 compatible = "qcom,geni-uart"; 1301 reg = <0 0x00994000 0 0x4000>; 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1303 clock-names = "se"; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1306 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1307 power-domains = <&rpmhpd SC7280_CX>; 1308 operating-points-v2 = <&qup_opp_table>; 1309 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1310 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 status = "disabled"; 1313 }; 1314 1315 i2c6: i2c@998000 { 1316 compatible = "qcom,geni-i2c"; 1317 reg = <0 0x00998000 0 0x4000>; 1318 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1319 clock-names = "se"; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_i2c6_data_clk>; 1322 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1326 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1327 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1328 interconnect-names = "qup-core", "qup-config", 1329 "qup-memory"; 1330 power-domains = <&rpmhpd SC7280_CX>; 1331 required-opps = <&rpmhpd_opp_low_svs>; 1332 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1333 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1334 dma-names = "tx", "rx"; 1335 status = "disabled"; 1336 }; 1337 1338 spi6: spi@998000 { 1339 compatible = "qcom,geni-spi"; 1340 reg = <0 0x00998000 0 0x4000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1342 clock-names = "se"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1345 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 power-domains = <&rpmhpd SC7280_CX>; 1349 operating-points-v2 = <&qup_opp_table>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1351 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1352 interconnect-names = "qup-core", "qup-config"; 1353 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1354 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1355 dma-names = "tx", "rx"; 1356 status = "disabled"; 1357 }; 1358 1359 uart6: serial@998000 { 1360 compatible = "qcom,geni-uart"; 1361 reg = <0 0x00998000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1363 clock-names = "se"; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1366 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1367 power-domains = <&rpmhpd SC7280_CX>; 1368 operating-points-v2 = <&qup_opp_table>; 1369 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1370 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1371 interconnect-names = "qup-core", "qup-config"; 1372 status = "disabled"; 1373 }; 1374 1375 i2c7: i2c@99c000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0 0x0099c000 0 0x4000>; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1379 clock-names = "se"; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_i2c7_data_clk>; 1382 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1386 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1387 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1388 interconnect-names = "qup-core", "qup-config", 1389 "qup-memory"; 1390 power-domains = <&rpmhpd SC7280_CX>; 1391 required-opps = <&rpmhpd_opp_low_svs>; 1392 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1393 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1394 dma-names = "tx", "rx"; 1395 status = "disabled"; 1396 }; 1397 1398 spi7: spi@99c000 { 1399 compatible = "qcom,geni-spi"; 1400 reg = <0 0x0099c000 0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1402 clock-names = "se"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1405 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 power-domains = <&rpmhpd SC7280_CX>; 1409 operating-points-v2 = <&qup_opp_table>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1411 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1412 interconnect-names = "qup-core", "qup-config"; 1413 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1414 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1415 dma-names = "tx", "rx"; 1416 status = "disabled"; 1417 }; 1418 1419 uart7: serial@99c000 { 1420 compatible = "qcom,geni-uart"; 1421 reg = <0 0x0099c000 0 0x4000>; 1422 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1423 clock-names = "se"; 1424 pinctrl-names = "default"; 1425 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1426 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1427 power-domains = <&rpmhpd SC7280_CX>; 1428 operating-points-v2 = <&qup_opp_table>; 1429 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1430 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1431 interconnect-names = "qup-core", "qup-config"; 1432 status = "disabled"; 1433 }; 1434 }; 1435 1436 gpi_dma1: dma-controller@a00000 { 1437 #dma-cells = <3>; 1438 compatible = "qcom,sc7280-gpi-dma"; 1439 reg = <0 0x00a00000 0 0x60000>; 1440 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1452 dma-channels = <12>; 1453 dma-channel-mask = <0x1e>; 1454 iommus = <&apps_smmu 0x56 0x0>; 1455 status = "disabled"; 1456 }; 1457 1458 qupv3_id_1: geniqup@ac0000 { 1459 compatible = "qcom,geni-se-qup"; 1460 reg = <0 0x00ac0000 0 0x2000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1462 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1463 clock-names = "m-ahb", "s-ahb"; 1464 #address-cells = <2>; 1465 #size-cells = <2>; 1466 ranges; 1467 iommus = <&apps_smmu 0x43 0x0>; 1468 status = "disabled"; 1469 1470 i2c8: i2c@a80000 { 1471 compatible = "qcom,geni-i2c"; 1472 reg = <0 0x00a80000 0 0x4000>; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1474 clock-names = "se"; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&qup_i2c8_data_clk>; 1477 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1481 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1482 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1483 interconnect-names = "qup-core", "qup-config", 1484 "qup-memory"; 1485 power-domains = <&rpmhpd SC7280_CX>; 1486 required-opps = <&rpmhpd_opp_low_svs>; 1487 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1488 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1489 dma-names = "tx", "rx"; 1490 status = "disabled"; 1491 }; 1492 1493 spi8: spi@a80000 { 1494 compatible = "qcom,geni-spi"; 1495 reg = <0 0x00a80000 0 0x4000>; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1497 clock-names = "se"; 1498 pinctrl-names = "default"; 1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 power-domains = <&rpmhpd SC7280_CX>; 1504 operating-points-v2 = <&qup_opp_table>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1509 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1510 dma-names = "tx", "rx"; 1511 status = "disabled"; 1512 }; 1513 1514 uart8: serial@a80000 { 1515 compatible = "qcom,geni-uart"; 1516 reg = <0 0x00a80000 0 0x4000>; 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1518 clock-names = "se"; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1521 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1522 power-domains = <&rpmhpd SC7280_CX>; 1523 operating-points-v2 = <&qup_opp_table>; 1524 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1525 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1526 interconnect-names = "qup-core", "qup-config"; 1527 status = "disabled"; 1528 }; 1529 1530 i2c9: i2c@a84000 { 1531 compatible = "qcom,geni-i2c"; 1532 reg = <0 0x00a84000 0 0x4000>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1534 clock-names = "se"; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_i2c9_data_clk>; 1537 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1541 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1543 interconnect-names = "qup-core", "qup-config", 1544 "qup-memory"; 1545 power-domains = <&rpmhpd SC7280_CX>; 1546 required-opps = <&rpmhpd_opp_low_svs>; 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1548 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1549 dma-names = "tx", "rx"; 1550 status = "disabled"; 1551 }; 1552 1553 spi9: spi@a84000 { 1554 compatible = "qcom,geni-spi"; 1555 reg = <0 0x00a84000 0 0x4000>; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1557 clock-names = "se"; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1560 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 power-domains = <&rpmhpd SC7280_CX>; 1564 operating-points-v2 = <&qup_opp_table>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1566 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1567 interconnect-names = "qup-core", "qup-config"; 1568 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1569 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1570 dma-names = "tx", "rx"; 1571 status = "disabled"; 1572 }; 1573 1574 uart9: serial@a84000 { 1575 compatible = "qcom,geni-uart"; 1576 reg = <0 0x00a84000 0 0x4000>; 1577 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1578 clock-names = "se"; 1579 pinctrl-names = "default"; 1580 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1581 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1582 power-domains = <&rpmhpd SC7280_CX>; 1583 operating-points-v2 = <&qup_opp_table>; 1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1585 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1586 interconnect-names = "qup-core", "qup-config"; 1587 status = "disabled"; 1588 }; 1589 1590 i2c10: i2c@a88000 { 1591 compatible = "qcom,geni-i2c"; 1592 reg = <0 0x00a88000 0 0x4000>; 1593 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1594 clock-names = "se"; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_i2c10_data_clk>; 1597 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1601 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1602 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1603 interconnect-names = "qup-core", "qup-config", 1604 "qup-memory"; 1605 power-domains = <&rpmhpd SC7280_CX>; 1606 required-opps = <&rpmhpd_opp_low_svs>; 1607 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1608 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1609 dma-names = "tx", "rx"; 1610 status = "disabled"; 1611 }; 1612 1613 spi10: spi@a88000 { 1614 compatible = "qcom,geni-spi"; 1615 reg = <0 0x00a88000 0 0x4000>; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1617 clock-names = "se"; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1620 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 power-domains = <&rpmhpd SC7280_CX>; 1624 operating-points-v2 = <&qup_opp_table>; 1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1626 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1627 interconnect-names = "qup-core", "qup-config"; 1628 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1629 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1630 dma-names = "tx", "rx"; 1631 status = "disabled"; 1632 }; 1633 1634 uart10: serial@a88000 { 1635 compatible = "qcom,geni-uart"; 1636 reg = <0 0x00a88000 0 0x4000>; 1637 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1638 clock-names = "se"; 1639 pinctrl-names = "default"; 1640 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1641 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1642 power-domains = <&rpmhpd SC7280_CX>; 1643 operating-points-v2 = <&qup_opp_table>; 1644 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1645 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1646 interconnect-names = "qup-core", "qup-config"; 1647 status = "disabled"; 1648 }; 1649 1650 i2c11: i2c@a8c000 { 1651 compatible = "qcom,geni-i2c"; 1652 reg = <0 0x00a8c000 0 0x4000>; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1654 clock-names = "se"; 1655 pinctrl-names = "default"; 1656 pinctrl-0 = <&qup_i2c11_data_clk>; 1657 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1663 interconnect-names = "qup-core", "qup-config", 1664 "qup-memory"; 1665 power-domains = <&rpmhpd SC7280_CX>; 1666 required-opps = <&rpmhpd_opp_low_svs>; 1667 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1668 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1669 dma-names = "tx", "rx"; 1670 status = "disabled"; 1671 }; 1672 1673 spi11: spi@a8c000 { 1674 compatible = "qcom,geni-spi"; 1675 reg = <0 0x00a8c000 0 0x4000>; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1677 clock-names = "se"; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1680 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 power-domains = <&rpmhpd SC7280_CX>; 1684 operating-points-v2 = <&qup_opp_table>; 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1686 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1687 interconnect-names = "qup-core", "qup-config"; 1688 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1689 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1690 dma-names = "tx", "rx"; 1691 status = "disabled"; 1692 }; 1693 1694 uart11: serial@a8c000 { 1695 compatible = "qcom,geni-uart"; 1696 reg = <0 0x00a8c000 0 0x4000>; 1697 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1698 clock-names = "se"; 1699 pinctrl-names = "default"; 1700 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1701 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1702 power-domains = <&rpmhpd SC7280_CX>; 1703 operating-points-v2 = <&qup_opp_table>; 1704 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1705 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1706 interconnect-names = "qup-core", "qup-config"; 1707 status = "disabled"; 1708 }; 1709 1710 i2c12: i2c@a90000 { 1711 compatible = "qcom,geni-i2c"; 1712 reg = <0 0x00a90000 0 0x4000>; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1714 clock-names = "se"; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_i2c12_data_clk>; 1717 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1721 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1723 interconnect-names = "qup-core", "qup-config", 1724 "qup-memory"; 1725 power-domains = <&rpmhpd SC7280_CX>; 1726 required-opps = <&rpmhpd_opp_low_svs>; 1727 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1728 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1729 dma-names = "tx", "rx"; 1730 status = "disabled"; 1731 }; 1732 1733 spi12: spi@a90000 { 1734 compatible = "qcom,geni-spi"; 1735 reg = <0 0x00a90000 0 0x4000>; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1737 clock-names = "se"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1740 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 power-domains = <&rpmhpd SC7280_CX>; 1744 operating-points-v2 = <&qup_opp_table>; 1745 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1746 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1747 interconnect-names = "qup-core", "qup-config"; 1748 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1749 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1750 dma-names = "tx", "rx"; 1751 status = "disabled"; 1752 }; 1753 1754 uart12: serial@a90000 { 1755 compatible = "qcom,geni-uart"; 1756 reg = <0 0x00a90000 0 0x4000>; 1757 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1758 clock-names = "se"; 1759 pinctrl-names = "default"; 1760 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1761 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1762 power-domains = <&rpmhpd SC7280_CX>; 1763 operating-points-v2 = <&qup_opp_table>; 1764 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1765 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1766 interconnect-names = "qup-core", "qup-config"; 1767 status = "disabled"; 1768 }; 1769 1770 i2c13: i2c@a94000 { 1771 compatible = "qcom,geni-i2c"; 1772 reg = <0 0x00a94000 0 0x4000>; 1773 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1774 clock-names = "se"; 1775 pinctrl-names = "default"; 1776 pinctrl-0 = <&qup_i2c13_data_clk>; 1777 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1781 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1782 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1783 interconnect-names = "qup-core", "qup-config", 1784 "qup-memory"; 1785 power-domains = <&rpmhpd SC7280_CX>; 1786 required-opps = <&rpmhpd_opp_low_svs>; 1787 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1788 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1789 dma-names = "tx", "rx"; 1790 status = "disabled"; 1791 }; 1792 1793 spi13: spi@a94000 { 1794 compatible = "qcom,geni-spi"; 1795 reg = <0 0x00a94000 0 0x4000>; 1796 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1797 clock-names = "se"; 1798 pinctrl-names = "default"; 1799 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1800 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 power-domains = <&rpmhpd SC7280_CX>; 1804 operating-points-v2 = <&qup_opp_table>; 1805 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1807 interconnect-names = "qup-core", "qup-config"; 1808 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1809 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1810 dma-names = "tx", "rx"; 1811 status = "disabled"; 1812 }; 1813 1814 uart13: serial@a94000 { 1815 compatible = "qcom,geni-uart"; 1816 reg = <0 0x00a94000 0 0x4000>; 1817 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1818 clock-names = "se"; 1819 pinctrl-names = "default"; 1820 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1821 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1822 power-domains = <&rpmhpd SC7280_CX>; 1823 operating-points-v2 = <&qup_opp_table>; 1824 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1825 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1826 interconnect-names = "qup-core", "qup-config"; 1827 status = "disabled"; 1828 }; 1829 1830 i2c14: i2c@a98000 { 1831 compatible = "qcom,geni-i2c"; 1832 reg = <0 0x00a98000 0 0x4000>; 1833 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1834 clock-names = "se"; 1835 pinctrl-names = "default"; 1836 pinctrl-0 = <&qup_i2c14_data_clk>; 1837 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1841 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1842 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1843 interconnect-names = "qup-core", "qup-config", 1844 "qup-memory"; 1845 power-domains = <&rpmhpd SC7280_CX>; 1846 required-opps = <&rpmhpd_opp_low_svs>; 1847 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1848 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1849 dma-names = "tx", "rx"; 1850 status = "disabled"; 1851 }; 1852 1853 spi14: spi@a98000 { 1854 compatible = "qcom,geni-spi"; 1855 reg = <0 0x00a98000 0 0x4000>; 1856 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1857 clock-names = "se"; 1858 pinctrl-names = "default"; 1859 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1860 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 power-domains = <&rpmhpd SC7280_CX>; 1864 operating-points-v2 = <&qup_opp_table>; 1865 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1866 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1867 interconnect-names = "qup-core", "qup-config"; 1868 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1869 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1870 dma-names = "tx", "rx"; 1871 status = "disabled"; 1872 }; 1873 1874 uart14: serial@a98000 { 1875 compatible = "qcom,geni-uart"; 1876 reg = <0 0x00a98000 0 0x4000>; 1877 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1878 clock-names = "se"; 1879 pinctrl-names = "default"; 1880 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1881 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1882 power-domains = <&rpmhpd SC7280_CX>; 1883 operating-points-v2 = <&qup_opp_table>; 1884 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1885 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1886 interconnect-names = "qup-core", "qup-config"; 1887 status = "disabled"; 1888 }; 1889 1890 i2c15: i2c@a9c000 { 1891 compatible = "qcom,geni-i2c"; 1892 reg = <0 0x00a9c000 0 0x4000>; 1893 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1894 clock-names = "se"; 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&qup_i2c15_data_clk>; 1897 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1901 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1902 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1903 interconnect-names = "qup-core", "qup-config", 1904 "qup-memory"; 1905 power-domains = <&rpmhpd SC7280_CX>; 1906 required-opps = <&rpmhpd_opp_low_svs>; 1907 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1908 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1909 dma-names = "tx", "rx"; 1910 status = "disabled"; 1911 }; 1912 1913 spi15: spi@a9c000 { 1914 compatible = "qcom,geni-spi"; 1915 reg = <0 0x00a9c000 0 0x4000>; 1916 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1917 clock-names = "se"; 1918 pinctrl-names = "default"; 1919 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1920 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 power-domains = <&rpmhpd SC7280_CX>; 1924 operating-points-v2 = <&qup_opp_table>; 1925 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1926 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1927 interconnect-names = "qup-core", "qup-config"; 1928 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1929 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1930 dma-names = "tx", "rx"; 1931 status = "disabled"; 1932 }; 1933 1934 uart15: serial@a9c000 { 1935 compatible = "qcom,geni-uart"; 1936 reg = <0 0x00a9c000 0 0x4000>; 1937 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1938 clock-names = "se"; 1939 pinctrl-names = "default"; 1940 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1941 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1942 power-domains = <&rpmhpd SC7280_CX>; 1943 operating-points-v2 = <&qup_opp_table>; 1944 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1945 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1946 interconnect-names = "qup-core", "qup-config"; 1947 status = "disabled"; 1948 }; 1949 }; 1950 1951 cnoc2: interconnect@1500000 { 1952 reg = <0 0x01500000 0 0x1000>; 1953 compatible = "qcom,sc7280-cnoc2"; 1954 #interconnect-cells = <2>; 1955 qcom,bcm-voters = <&apps_bcm_voter>; 1956 }; 1957 1958 cnoc3: interconnect@1502000 { 1959 reg = <0 0x01502000 0 0x1000>; 1960 compatible = "qcom,sc7280-cnoc3"; 1961 #interconnect-cells = <2>; 1962 qcom,bcm-voters = <&apps_bcm_voter>; 1963 }; 1964 1965 mc_virt: interconnect@1580000 { 1966 reg = <0 0x01580000 0 0x4>; 1967 compatible = "qcom,sc7280-mc-virt"; 1968 #interconnect-cells = <2>; 1969 qcom,bcm-voters = <&apps_bcm_voter>; 1970 }; 1971 1972 system_noc: interconnect@1680000 { 1973 reg = <0 0x01680000 0 0x15480>; 1974 compatible = "qcom,sc7280-system-noc"; 1975 #interconnect-cells = <2>; 1976 qcom,bcm-voters = <&apps_bcm_voter>; 1977 }; 1978 1979 aggre1_noc: interconnect@16e0000 { 1980 compatible = "qcom,sc7280-aggre1-noc"; 1981 reg = <0 0x016e0000 0 0x1c080>; 1982 #interconnect-cells = <2>; 1983 qcom,bcm-voters = <&apps_bcm_voter>; 1984 }; 1985 1986 aggre2_noc: interconnect@1700000 { 1987 reg = <0 0x01700000 0 0x2b080>; 1988 compatible = "qcom,sc7280-aggre2-noc"; 1989 #interconnect-cells = <2>; 1990 qcom,bcm-voters = <&apps_bcm_voter>; 1991 }; 1992 1993 mmss_noc: interconnect@1740000 { 1994 reg = <0 0x01740000 0 0x1e080>; 1995 compatible = "qcom,sc7280-mmss-noc"; 1996 #interconnect-cells = <2>; 1997 qcom,bcm-voters = <&apps_bcm_voter>; 1998 }; 1999 2000 wifi: wifi@17a10040 { 2001 compatible = "qcom,wcn6750-wifi"; 2002 reg = <0 0x17a10040 0 0x0>; 2003 iommus = <&apps_smmu 0x1c00 0x1>; 2004 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2005 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2006 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2007 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2008 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2009 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2010 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2011 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2012 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2013 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2014 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2015 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2016 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2017 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2018 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2019 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2020 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2021 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2022 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2023 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2024 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2025 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2026 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2027 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2028 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2029 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2030 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2031 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2036 qcom,rproc = <&remoteproc_wpss>; 2037 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2038 status = "disabled"; 2039 }; 2040 2041 pcie1: pci@1c08000 { 2042 compatible = "qcom,pcie-sc7280"; 2043 reg = <0 0x01c08000 0 0x3000>, 2044 <0 0x40000000 0 0xf1d>, 2045 <0 0x40000f20 0 0xa8>, 2046 <0 0x40001000 0 0x1000>, 2047 <0 0x40100000 0 0x100000>; 2048 2049 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2050 device_type = "pci"; 2051 linux,pci-domain = <1>; 2052 bus-range = <0x00 0xff>; 2053 num-lanes = <2>; 2054 2055 #address-cells = <3>; 2056 #size-cells = <2>; 2057 2058 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2059 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2060 2061 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2062 interrupt-names = "msi"; 2063 #interrupt-cells = <1>; 2064 interrupt-map-mask = <0 0 0 0x7>; 2065 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2066 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2067 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2068 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2069 2070 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2071 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2072 <&pcie1_lane>, 2073 <&rpmhcc RPMH_CXO_CLK>, 2074 <&gcc GCC_PCIE_1_AUX_CLK>, 2075 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2076 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2077 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2078 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2079 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2080 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2081 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2082 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2083 2084 clock-names = "pipe", 2085 "pipe_mux", 2086 "phy_pipe", 2087 "ref", 2088 "aux", 2089 "cfg", 2090 "bus_master", 2091 "bus_slave", 2092 "slave_q2a", 2093 "tbu", 2094 "ddrss_sf_tbu", 2095 "aggre0", 2096 "aggre1"; 2097 2098 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2099 assigned-clock-rates = <19200000>; 2100 2101 resets = <&gcc GCC_PCIE_1_BCR>; 2102 reset-names = "pci"; 2103 2104 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2105 2106 phys = <&pcie1_lane>; 2107 phy-names = "pciephy"; 2108 2109 pinctrl-names = "default"; 2110 pinctrl-0 = <&pcie1_clkreq_n>; 2111 2112 iommus = <&apps_smmu 0x1c80 0x1>; 2113 2114 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2115 <0x100 &apps_smmu 0x1c81 0x1>; 2116 2117 status = "disabled"; 2118 }; 2119 2120 pcie1_phy: phy@1c0e000 { 2121 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2122 reg = <0 0x01c0e000 0 0x1c0>; 2123 #address-cells = <2>; 2124 #size-cells = <2>; 2125 ranges; 2126 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2127 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2128 <&gcc GCC_PCIE_CLKREF_EN>, 2129 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2130 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2131 2132 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2133 reset-names = "phy"; 2134 2135 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2136 assigned-clock-rates = <100000000>; 2137 2138 status = "disabled"; 2139 2140 pcie1_lane: phy@1c0e200 { 2141 reg = <0 0x01c0e200 0 0x170>, 2142 <0 0x01c0e400 0 0x200>, 2143 <0 0x01c0ea00 0 0x1f0>, 2144 <0 0x01c0e600 0 0x170>, 2145 <0 0x01c0e800 0 0x200>, 2146 <0 0x01c0ee00 0 0xf4>; 2147 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2148 clock-names = "pipe0"; 2149 2150 #phy-cells = <0>; 2151 #clock-cells = <0>; 2152 clock-output-names = "pcie_1_pipe_clk"; 2153 }; 2154 }; 2155 2156 ipa: ipa@1e40000 { 2157 compatible = "qcom,sc7280-ipa"; 2158 2159 iommus = <&apps_smmu 0x480 0x0>, 2160 <&apps_smmu 0x482 0x0>; 2161 reg = <0 0x1e40000 0 0x8000>, 2162 <0 0x1e50000 0 0x4ad0>, 2163 <0 0x1e04000 0 0x23000>; 2164 reg-names = "ipa-reg", 2165 "ipa-shared", 2166 "gsi"; 2167 2168 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2169 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2170 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2171 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2172 interrupt-names = "ipa", 2173 "gsi", 2174 "ipa-clock-query", 2175 "ipa-setup-ready"; 2176 2177 clocks = <&rpmhcc RPMH_IPA_CLK>; 2178 clock-names = "core"; 2179 2180 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2181 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2182 interconnect-names = "memory", 2183 "config"; 2184 2185 qcom,qmp = <&aoss_qmp>; 2186 2187 qcom,smem-states = <&ipa_smp2p_out 0>, 2188 <&ipa_smp2p_out 1>; 2189 qcom,smem-state-names = "ipa-clock-enabled-valid", 2190 "ipa-clock-enabled"; 2191 2192 status = "disabled"; 2193 }; 2194 2195 tcsr_mutex: hwlock@1f40000 { 2196 compatible = "qcom,tcsr-mutex"; 2197 reg = <0 0x01f40000 0 0x20000>; 2198 #hwlock-cells = <1>; 2199 }; 2200 2201 tcsr_1: syscon@1f60000 { 2202 compatible = "qcom,sc7280-tcsr", "syscon"; 2203 reg = <0 0x01f60000 0 0x20000>; 2204 }; 2205 2206 tcsr_2: syscon@1fc0000 { 2207 compatible = "qcom,sc7280-tcsr", "syscon"; 2208 reg = <0 0x01fc0000 0 0x30000>; 2209 }; 2210 2211 lpasscc: lpasscc@3000000 { 2212 compatible = "qcom,sc7280-lpasscc"; 2213 reg = <0 0x03000000 0 0x40>, 2214 <0 0x03c04000 0 0x4>; 2215 reg-names = "qdsp6ss", "top_cc"; 2216 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2217 clock-names = "iface"; 2218 #clock-cells = <1>; 2219 }; 2220 2221 lpass_rx_macro: codec@3200000 { 2222 compatible = "qcom,sc7280-lpass-rx-macro"; 2223 reg = <0 0x03200000 0 0x1000>; 2224 2225 pinctrl-names = "default"; 2226 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2227 2228 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2229 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2230 <&lpass_va_macro>; 2231 clock-names = "mclk", "npl", "fsgen"; 2232 2233 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2234 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2235 power-domain-names = "macro", "dcodec"; 2236 2237 #clock-cells = <0>; 2238 #sound-dai-cells = <1>; 2239 2240 status = "disabled"; 2241 }; 2242 2243 swr0: soundwire@3210000 { 2244 compatible = "qcom,soundwire-v1.6.0"; 2245 reg = <0 0x03210000 0 0x2000>; 2246 2247 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2248 clocks = <&lpass_rx_macro>; 2249 clock-names = "iface"; 2250 2251 qcom,din-ports = <0>; 2252 qcom,dout-ports = <5>; 2253 2254 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2255 reset-names = "swr_audio_cgcr"; 2256 2257 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2258 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2259 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2260 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2261 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2262 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2263 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2264 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2265 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2266 2267 #sound-dai-cells = <1>; 2268 #address-cells = <2>; 2269 #size-cells = <0>; 2270 2271 status = "disabled"; 2272 }; 2273 2274 lpass_tx_macro: codec@3220000 { 2275 compatible = "qcom,sc7280-lpass-tx-macro"; 2276 reg = <0 0x03220000 0 0x1000>; 2277 2278 pinctrl-names = "default"; 2279 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2280 2281 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2282 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2283 <&lpass_va_macro>; 2284 clock-names = "mclk", "npl", "fsgen"; 2285 2286 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2287 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2288 power-domain-names = "macro", "dcodec"; 2289 2290 #clock-cells = <0>; 2291 #sound-dai-cells = <1>; 2292 2293 status = "disabled"; 2294 }; 2295 2296 swr1: soundwire@3230000 { 2297 compatible = "qcom,soundwire-v1.6.0"; 2298 reg = <0 0x03230000 0 0x2000>; 2299 2300 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2301 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&lpass_tx_macro>; 2303 clock-names = "iface"; 2304 2305 qcom,din-ports = <3>; 2306 qcom,dout-ports = <0>; 2307 2308 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2309 reset-names = "swr_audio_cgcr"; 2310 2311 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2312 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2313 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2314 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2315 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2316 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2317 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2318 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2319 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2320 qcom,port-offset = <1>; 2321 2322 #sound-dai-cells = <1>; 2323 #address-cells = <2>; 2324 #size-cells = <0>; 2325 2326 status = "disabled"; 2327 }; 2328 2329 lpass_audiocc: clock-controller@3300000 { 2330 compatible = "qcom,sc7280-lpassaudiocc"; 2331 reg = <0 0x03300000 0 0x30000>; 2332 clocks = <&rpmhcc RPMH_CXO_CLK>, 2333 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2334 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2335 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2336 #clock-cells = <1>; 2337 #power-domain-cells = <1>; 2338 #reset-cells = <1>; 2339 }; 2340 2341 lpass_va_macro: codec@3370000 { 2342 compatible = "qcom,sc7280-lpass-va-macro"; 2343 reg = <0 0x03370000 0 0x1000>; 2344 2345 pinctrl-names = "default"; 2346 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2347 2348 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2349 clock-names = "mclk"; 2350 2351 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2352 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2353 power-domain-names = "macro", "dcodec"; 2354 2355 #clock-cells = <0>; 2356 #sound-dai-cells = <1>; 2357 2358 status = "disabled"; 2359 }; 2360 2361 lpass_aon: clock-controller@3380000 { 2362 compatible = "qcom,sc7280-lpassaoncc"; 2363 reg = <0 0x03380000 0 0x30000>; 2364 clocks = <&rpmhcc RPMH_CXO_CLK>, 2365 <&rpmhcc RPMH_CXO_CLK_A>, 2366 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2367 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2368 #clock-cells = <1>; 2369 #power-domain-cells = <1>; 2370 }; 2371 2372 lpass_core: clock-controller@3900000 { 2373 compatible = "qcom,sc7280-lpasscorecc"; 2374 reg = <0 0x03900000 0 0x50000>; 2375 clocks = <&rpmhcc RPMH_CXO_CLK>; 2376 clock-names = "bi_tcxo"; 2377 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2378 #clock-cells = <1>; 2379 #power-domain-cells = <1>; 2380 }; 2381 2382 lpass_cpu: audio@3987000 { 2383 compatible = "qcom,sc7280-lpass-cpu"; 2384 2385 reg = <0 0x03987000 0 0x68000>, 2386 <0 0x03b00000 0 0x29000>, 2387 <0 0x03260000 0 0xc000>, 2388 <0 0x03280000 0 0x29000>, 2389 <0 0x03340000 0 0x29000>, 2390 <0 0x0336c000 0 0x3000>; 2391 reg-names = "lpass-hdmiif", 2392 "lpass-lpaif", 2393 "lpass-rxtx-cdc-dma-lpm", 2394 "lpass-rxtx-lpaif", 2395 "lpass-va-lpaif", 2396 "lpass-va-cdc-dma-lpm"; 2397 2398 iommus = <&apps_smmu 0x1820 0>, 2399 <&apps_smmu 0x1821 0>, 2400 <&apps_smmu 0x1832 0>; 2401 2402 power-domains = <&rpmhpd SC7280_LCX>; 2403 power-domain-names = "lcx"; 2404 required-opps = <&rpmhpd_opp_nom>; 2405 2406 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2407 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2408 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2409 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2410 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2411 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2412 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2413 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2414 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2415 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2416 clock-names = "aon_cc_audio_hm_h", 2417 "audio_cc_ext_mclk0", 2418 "core_cc_sysnoc_mport_core", 2419 "core_cc_ext_if0_ibit", 2420 "core_cc_ext_if1_ibit", 2421 "audio_cc_codec_mem", 2422 "audio_cc_codec_mem0", 2423 "audio_cc_codec_mem1", 2424 "audio_cc_codec_mem2", 2425 "aon_cc_va_mem0"; 2426 2427 #sound-dai-cells = <1>; 2428 #address-cells = <1>; 2429 #size-cells = <0>; 2430 2431 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2435 interrupt-names = "lpass-irq-lpaif", 2436 "lpass-irq-hdmi", 2437 "lpass-irq-vaif", 2438 "lpass-irq-rxtxif"; 2439 2440 status = "disabled"; 2441 }; 2442 2443 lpass_hm: clock-controller@3c00000 { 2444 compatible = "qcom,sc7280-lpasshm"; 2445 reg = <0 0x3c00000 0 0x28>; 2446 clocks = <&rpmhcc RPMH_CXO_CLK>; 2447 clock-names = "bi_tcxo"; 2448 #clock-cells = <1>; 2449 #power-domain-cells = <1>; 2450 }; 2451 2452 lpass_ag_noc: interconnect@3c40000 { 2453 reg = <0 0x03c40000 0 0xf080>; 2454 compatible = "qcom,sc7280-lpass-ag-noc"; 2455 #interconnect-cells = <2>; 2456 qcom,bcm-voters = <&apps_bcm_voter>; 2457 }; 2458 2459 lpass_tlmm: pinctrl@33c0000 { 2460 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2461 reg = <0 0x033c0000 0x0 0x20000>, 2462 <0 0x03550000 0x0 0x10000>; 2463 qcom,adsp-bypass-mode; 2464 gpio-controller; 2465 #gpio-cells = <2>; 2466 gpio-ranges = <&lpass_tlmm 0 0 15>; 2467 2468 #clock-cells = <1>; 2469 2470 lpass_dmic01_clk: dmic01-clk { 2471 pins = "gpio6"; 2472 function = "dmic1_clk"; 2473 }; 2474 2475 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2476 pins = "gpio6"; 2477 function = "dmic1_clk"; 2478 }; 2479 2480 lpass_dmic01_data: dmic01-data { 2481 pins = "gpio7"; 2482 function = "dmic1_data"; 2483 }; 2484 2485 lpass_dmic01_data_sleep: dmic01-data-sleep { 2486 pins = "gpio7"; 2487 function = "dmic1_data"; 2488 }; 2489 2490 lpass_dmic23_clk: dmic23-clk { 2491 pins = "gpio8"; 2492 function = "dmic2_clk"; 2493 }; 2494 2495 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2496 pins = "gpio8"; 2497 function = "dmic2_clk"; 2498 }; 2499 2500 lpass_dmic23_data: dmic23-data { 2501 pins = "gpio9"; 2502 function = "dmic2_data"; 2503 }; 2504 2505 lpass_dmic23_data_sleep: dmic23-data-sleep { 2506 pins = "gpio9"; 2507 function = "dmic2_data"; 2508 }; 2509 2510 lpass_rx_swr_clk: rx-swr-clk { 2511 pins = "gpio3"; 2512 function = "swr_rx_clk"; 2513 }; 2514 2515 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2516 pins = "gpio3"; 2517 function = "swr_rx_clk"; 2518 }; 2519 2520 lpass_rx_swr_data: rx-swr-data { 2521 pins = "gpio4", "gpio5"; 2522 function = "swr_rx_data"; 2523 }; 2524 2525 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2526 pins = "gpio4", "gpio5"; 2527 function = "swr_rx_data"; 2528 }; 2529 2530 lpass_tx_swr_clk: tx-swr-clk { 2531 pins = "gpio0"; 2532 function = "swr_tx_clk"; 2533 }; 2534 2535 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2536 pins = "gpio0"; 2537 function = "swr_tx_clk"; 2538 }; 2539 2540 lpass_tx_swr_data: tx-swr-data { 2541 pins = "gpio1", "gpio2", "gpio14"; 2542 function = "swr_tx_data"; 2543 }; 2544 2545 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2546 pins = "gpio1", "gpio2", "gpio14"; 2547 function = "swr_tx_data"; 2548 }; 2549 }; 2550 2551 gpu: gpu@3d00000 { 2552 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2553 reg = <0 0x03d00000 0 0x40000>, 2554 <0 0x03d9e000 0 0x1000>, 2555 <0 0x03d61000 0 0x800>; 2556 reg-names = "kgsl_3d0_reg_memory", 2557 "cx_mem", 2558 "cx_dbgc"; 2559 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2560 iommus = <&adreno_smmu 0 0x401>; 2561 operating-points-v2 = <&gpu_opp_table>; 2562 qcom,gmu = <&gmu>; 2563 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2564 interconnect-names = "gfx-mem"; 2565 #cooling-cells = <2>; 2566 2567 nvmem-cells = <&gpu_speed_bin>; 2568 nvmem-cell-names = "speed_bin"; 2569 2570 gpu_opp_table: opp-table { 2571 compatible = "operating-points-v2"; 2572 2573 opp-315000000 { 2574 opp-hz = /bits/ 64 <315000000>; 2575 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2576 opp-peak-kBps = <1804000>; 2577 opp-supported-hw = <0x03>; 2578 }; 2579 2580 opp-450000000 { 2581 opp-hz = /bits/ 64 <450000000>; 2582 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2583 opp-peak-kBps = <4068000>; 2584 opp-supported-hw = <0x03>; 2585 }; 2586 2587 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2588 opp-550000000-0 { 2589 opp-hz = /bits/ 64 <550000000>; 2590 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2591 opp-peak-kBps = <8368000>; 2592 opp-supported-hw = <0x01>; 2593 }; 2594 2595 opp-550000000-1 { 2596 opp-hz = /bits/ 64 <550000000>; 2597 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2598 opp-peak-kBps = <6832000>; 2599 opp-supported-hw = <0x02>; 2600 }; 2601 2602 opp-608000000 { 2603 opp-hz = /bits/ 64 <608000000>; 2604 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2605 opp-peak-kBps = <8368000>; 2606 opp-supported-hw = <0x02>; 2607 }; 2608 2609 opp-700000000 { 2610 opp-hz = /bits/ 64 <700000000>; 2611 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2612 opp-peak-kBps = <8532000>; 2613 opp-supported-hw = <0x02>; 2614 }; 2615 2616 opp-812000000 { 2617 opp-hz = /bits/ 64 <812000000>; 2618 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2619 opp-peak-kBps = <8532000>; 2620 opp-supported-hw = <0x02>; 2621 }; 2622 2623 opp-840000000 { 2624 opp-hz = /bits/ 64 <840000000>; 2625 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2626 opp-peak-kBps = <8532000>; 2627 opp-supported-hw = <0x02>; 2628 }; 2629 2630 opp-900000000 { 2631 opp-hz = /bits/ 64 <900000000>; 2632 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2633 opp-peak-kBps = <8532000>; 2634 opp-supported-hw = <0x02>; 2635 }; 2636 }; 2637 }; 2638 2639 gmu: gmu@3d6a000 { 2640 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2641 reg = <0 0x03d6a000 0 0x34000>, 2642 <0 0x3de0000 0 0x10000>, 2643 <0 0x0b290000 0 0x10000>; 2644 reg-names = "gmu", "rscc", "gmu_pdc"; 2645 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2646 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2647 interrupt-names = "hfi", "gmu"; 2648 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2649 <&gpucc GPU_CC_CXO_CLK>, 2650 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2651 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2652 <&gpucc GPU_CC_AHB_CLK>, 2653 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2654 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2655 clock-names = "gmu", 2656 "cxo", 2657 "axi", 2658 "memnoc", 2659 "ahb", 2660 "hub", 2661 "smmu_vote"; 2662 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2663 <&gpucc GPU_CC_GX_GDSC>; 2664 power-domain-names = "cx", 2665 "gx"; 2666 iommus = <&adreno_smmu 5 0x400>; 2667 operating-points-v2 = <&gmu_opp_table>; 2668 2669 gmu_opp_table: opp-table { 2670 compatible = "operating-points-v2"; 2671 2672 opp-200000000 { 2673 opp-hz = /bits/ 64 <200000000>; 2674 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2675 }; 2676 }; 2677 }; 2678 2679 gpucc: clock-controller@3d90000 { 2680 compatible = "qcom,sc7280-gpucc"; 2681 reg = <0 0x03d90000 0 0x9000>; 2682 clocks = <&rpmhcc RPMH_CXO_CLK>, 2683 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2684 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2685 clock-names = "bi_tcxo", 2686 "gcc_gpu_gpll0_clk_src", 2687 "gcc_gpu_gpll0_div_clk_src"; 2688 #clock-cells = <1>; 2689 #reset-cells = <1>; 2690 #power-domain-cells = <1>; 2691 }; 2692 2693 adreno_smmu: iommu@3da0000 { 2694 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2695 reg = <0 0x03da0000 0 0x20000>; 2696 #iommu-cells = <2>; 2697 #global-interrupts = <2>; 2698 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2710 2711 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2712 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2713 <&gpucc GPU_CC_AHB_CLK>, 2714 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2715 <&gpucc GPU_CC_CX_GMU_CLK>, 2716 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2717 <&gpucc GPU_CC_HUB_AON_CLK>; 2718 clock-names = "gcc_gpu_memnoc_gfx_clk", 2719 "gcc_gpu_snoc_dvm_gfx_clk", 2720 "gpu_cc_ahb_clk", 2721 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2722 "gpu_cc_cx_gmu_clk", 2723 "gpu_cc_hub_cx_int_clk", 2724 "gpu_cc_hub_aon_clk"; 2725 2726 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2727 }; 2728 2729 remoteproc_mpss: remoteproc@4080000 { 2730 compatible = "qcom,sc7280-mpss-pas"; 2731 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2732 reg-names = "qdsp6", "rmb"; 2733 2734 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2735 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2736 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2737 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2738 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2739 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2740 interrupt-names = "wdog", "fatal", "ready", "handover", 2741 "stop-ack", "shutdown-ack"; 2742 2743 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2744 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2745 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2746 <&rpmhcc RPMH_PKA_CLK>, 2747 <&rpmhcc RPMH_CXO_CLK>; 2748 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2749 2750 power-domains = <&rpmhpd SC7280_CX>, 2751 <&rpmhpd SC7280_MSS>; 2752 power-domain-names = "cx", "mss"; 2753 2754 memory-region = <&mpss_mem>; 2755 2756 qcom,qmp = <&aoss_qmp>; 2757 2758 qcom,smem-states = <&modem_smp2p_out 0>; 2759 qcom,smem-state-names = "stop"; 2760 2761 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2762 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2763 reset-names = "mss_restart", "pdc_reset"; 2764 2765 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2766 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2767 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2768 2769 status = "disabled"; 2770 2771 glink-edge { 2772 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2773 IPCC_MPROC_SIGNAL_GLINK_QMP 2774 IRQ_TYPE_EDGE_RISING>; 2775 mboxes = <&ipcc IPCC_CLIENT_MPSS 2776 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2777 label = "modem"; 2778 qcom,remote-pid = <1>; 2779 }; 2780 }; 2781 2782 stm@6002000 { 2783 compatible = "arm,coresight-stm", "arm,primecell"; 2784 reg = <0 0x06002000 0 0x1000>, 2785 <0 0x16280000 0 0x180000>; 2786 reg-names = "stm-base", "stm-stimulus-base"; 2787 2788 clocks = <&aoss_qmp>; 2789 clock-names = "apb_pclk"; 2790 2791 out-ports { 2792 port { 2793 stm_out: endpoint { 2794 remote-endpoint = <&funnel0_in7>; 2795 }; 2796 }; 2797 }; 2798 }; 2799 2800 funnel@6041000 { 2801 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2802 reg = <0 0x06041000 0 0x1000>; 2803 2804 clocks = <&aoss_qmp>; 2805 clock-names = "apb_pclk"; 2806 2807 out-ports { 2808 port { 2809 funnel0_out: endpoint { 2810 remote-endpoint = <&merge_funnel_in0>; 2811 }; 2812 }; 2813 }; 2814 2815 in-ports { 2816 #address-cells = <1>; 2817 #size-cells = <0>; 2818 2819 port@7 { 2820 reg = <7>; 2821 funnel0_in7: endpoint { 2822 remote-endpoint = <&stm_out>; 2823 }; 2824 }; 2825 }; 2826 }; 2827 2828 funnel@6042000 { 2829 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2830 reg = <0 0x06042000 0 0x1000>; 2831 2832 clocks = <&aoss_qmp>; 2833 clock-names = "apb_pclk"; 2834 2835 out-ports { 2836 port { 2837 funnel1_out: endpoint { 2838 remote-endpoint = <&merge_funnel_in1>; 2839 }; 2840 }; 2841 }; 2842 2843 in-ports { 2844 #address-cells = <1>; 2845 #size-cells = <0>; 2846 2847 port@4 { 2848 reg = <4>; 2849 funnel1_in4: endpoint { 2850 remote-endpoint = <&apss_merge_funnel_out>; 2851 }; 2852 }; 2853 }; 2854 }; 2855 2856 funnel@6045000 { 2857 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2858 reg = <0 0x06045000 0 0x1000>; 2859 2860 clocks = <&aoss_qmp>; 2861 clock-names = "apb_pclk"; 2862 2863 out-ports { 2864 port { 2865 merge_funnel_out: endpoint { 2866 remote-endpoint = <&swao_funnel_in>; 2867 }; 2868 }; 2869 }; 2870 2871 in-ports { 2872 #address-cells = <1>; 2873 #size-cells = <0>; 2874 2875 port@0 { 2876 reg = <0>; 2877 merge_funnel_in0: endpoint { 2878 remote-endpoint = <&funnel0_out>; 2879 }; 2880 }; 2881 2882 port@1 { 2883 reg = <1>; 2884 merge_funnel_in1: endpoint { 2885 remote-endpoint = <&funnel1_out>; 2886 }; 2887 }; 2888 }; 2889 }; 2890 2891 replicator@6046000 { 2892 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2893 reg = <0 0x06046000 0 0x1000>; 2894 2895 clocks = <&aoss_qmp>; 2896 clock-names = "apb_pclk"; 2897 2898 out-ports { 2899 port { 2900 replicator_out: endpoint { 2901 remote-endpoint = <&etr_in>; 2902 }; 2903 }; 2904 }; 2905 2906 in-ports { 2907 port { 2908 replicator_in: endpoint { 2909 remote-endpoint = <&swao_replicator_out>; 2910 }; 2911 }; 2912 }; 2913 }; 2914 2915 etr@6048000 { 2916 compatible = "arm,coresight-tmc", "arm,primecell"; 2917 reg = <0 0x06048000 0 0x1000>; 2918 iommus = <&apps_smmu 0x04c0 0>; 2919 2920 clocks = <&aoss_qmp>; 2921 clock-names = "apb_pclk"; 2922 arm,scatter-gather; 2923 2924 in-ports { 2925 port { 2926 etr_in: endpoint { 2927 remote-endpoint = <&replicator_out>; 2928 }; 2929 }; 2930 }; 2931 }; 2932 2933 funnel@6b04000 { 2934 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2935 reg = <0 0x06b04000 0 0x1000>; 2936 2937 clocks = <&aoss_qmp>; 2938 clock-names = "apb_pclk"; 2939 2940 out-ports { 2941 port { 2942 swao_funnel_out: endpoint { 2943 remote-endpoint = <&etf_in>; 2944 }; 2945 }; 2946 }; 2947 2948 in-ports { 2949 #address-cells = <1>; 2950 #size-cells = <0>; 2951 2952 port@7 { 2953 reg = <7>; 2954 swao_funnel_in: endpoint { 2955 remote-endpoint = <&merge_funnel_out>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 etf@6b05000 { 2962 compatible = "arm,coresight-tmc", "arm,primecell"; 2963 reg = <0 0x06b05000 0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 2968 out-ports { 2969 port { 2970 etf_out: endpoint { 2971 remote-endpoint = <&swao_replicator_in>; 2972 }; 2973 }; 2974 }; 2975 2976 in-ports { 2977 port { 2978 etf_in: endpoint { 2979 remote-endpoint = <&swao_funnel_out>; 2980 }; 2981 }; 2982 }; 2983 }; 2984 2985 replicator@6b06000 { 2986 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2987 reg = <0 0x06b06000 0 0x1000>; 2988 2989 clocks = <&aoss_qmp>; 2990 clock-names = "apb_pclk"; 2991 qcom,replicator-loses-context; 2992 2993 out-ports { 2994 port { 2995 swao_replicator_out: endpoint { 2996 remote-endpoint = <&replicator_in>; 2997 }; 2998 }; 2999 }; 3000 3001 in-ports { 3002 port { 3003 swao_replicator_in: endpoint { 3004 remote-endpoint = <&etf_out>; 3005 }; 3006 }; 3007 }; 3008 }; 3009 3010 etm@7040000 { 3011 compatible = "arm,coresight-etm4x", "arm,primecell"; 3012 reg = <0 0x07040000 0 0x1000>; 3013 3014 cpu = <&CPU0>; 3015 3016 clocks = <&aoss_qmp>; 3017 clock-names = "apb_pclk"; 3018 arm,coresight-loses-context-with-cpu; 3019 qcom,skip-power-up; 3020 3021 out-ports { 3022 port { 3023 etm0_out: endpoint { 3024 remote-endpoint = <&apss_funnel_in0>; 3025 }; 3026 }; 3027 }; 3028 }; 3029 3030 etm@7140000 { 3031 compatible = "arm,coresight-etm4x", "arm,primecell"; 3032 reg = <0 0x07140000 0 0x1000>; 3033 3034 cpu = <&CPU1>; 3035 3036 clocks = <&aoss_qmp>; 3037 clock-names = "apb_pclk"; 3038 arm,coresight-loses-context-with-cpu; 3039 qcom,skip-power-up; 3040 3041 out-ports { 3042 port { 3043 etm1_out: endpoint { 3044 remote-endpoint = <&apss_funnel_in1>; 3045 }; 3046 }; 3047 }; 3048 }; 3049 3050 etm@7240000 { 3051 compatible = "arm,coresight-etm4x", "arm,primecell"; 3052 reg = <0 0x07240000 0 0x1000>; 3053 3054 cpu = <&CPU2>; 3055 3056 clocks = <&aoss_qmp>; 3057 clock-names = "apb_pclk"; 3058 arm,coresight-loses-context-with-cpu; 3059 qcom,skip-power-up; 3060 3061 out-ports { 3062 port { 3063 etm2_out: endpoint { 3064 remote-endpoint = <&apss_funnel_in2>; 3065 }; 3066 }; 3067 }; 3068 }; 3069 3070 etm@7340000 { 3071 compatible = "arm,coresight-etm4x", "arm,primecell"; 3072 reg = <0 0x07340000 0 0x1000>; 3073 3074 cpu = <&CPU3>; 3075 3076 clocks = <&aoss_qmp>; 3077 clock-names = "apb_pclk"; 3078 arm,coresight-loses-context-with-cpu; 3079 qcom,skip-power-up; 3080 3081 out-ports { 3082 port { 3083 etm3_out: endpoint { 3084 remote-endpoint = <&apss_funnel_in3>; 3085 }; 3086 }; 3087 }; 3088 }; 3089 3090 etm@7440000 { 3091 compatible = "arm,coresight-etm4x", "arm,primecell"; 3092 reg = <0 0x07440000 0 0x1000>; 3093 3094 cpu = <&CPU4>; 3095 3096 clocks = <&aoss_qmp>; 3097 clock-names = "apb_pclk"; 3098 arm,coresight-loses-context-with-cpu; 3099 qcom,skip-power-up; 3100 3101 out-ports { 3102 port { 3103 etm4_out: endpoint { 3104 remote-endpoint = <&apss_funnel_in4>; 3105 }; 3106 }; 3107 }; 3108 }; 3109 3110 etm@7540000 { 3111 compatible = "arm,coresight-etm4x", "arm,primecell"; 3112 reg = <0 0x07540000 0 0x1000>; 3113 3114 cpu = <&CPU5>; 3115 3116 clocks = <&aoss_qmp>; 3117 clock-names = "apb_pclk"; 3118 arm,coresight-loses-context-with-cpu; 3119 qcom,skip-power-up; 3120 3121 out-ports { 3122 port { 3123 etm5_out: endpoint { 3124 remote-endpoint = <&apss_funnel_in5>; 3125 }; 3126 }; 3127 }; 3128 }; 3129 3130 etm@7640000 { 3131 compatible = "arm,coresight-etm4x", "arm,primecell"; 3132 reg = <0 0x07640000 0 0x1000>; 3133 3134 cpu = <&CPU6>; 3135 3136 clocks = <&aoss_qmp>; 3137 clock-names = "apb_pclk"; 3138 arm,coresight-loses-context-with-cpu; 3139 qcom,skip-power-up; 3140 3141 out-ports { 3142 port { 3143 etm6_out: endpoint { 3144 remote-endpoint = <&apss_funnel_in6>; 3145 }; 3146 }; 3147 }; 3148 }; 3149 3150 etm@7740000 { 3151 compatible = "arm,coresight-etm4x", "arm,primecell"; 3152 reg = <0 0x07740000 0 0x1000>; 3153 3154 cpu = <&CPU7>; 3155 3156 clocks = <&aoss_qmp>; 3157 clock-names = "apb_pclk"; 3158 arm,coresight-loses-context-with-cpu; 3159 qcom,skip-power-up; 3160 3161 out-ports { 3162 port { 3163 etm7_out: endpoint { 3164 remote-endpoint = <&apss_funnel_in7>; 3165 }; 3166 }; 3167 }; 3168 }; 3169 3170 funnel@7800000 { /* APSS Funnel */ 3171 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3172 reg = <0 0x07800000 0 0x1000>; 3173 3174 clocks = <&aoss_qmp>; 3175 clock-names = "apb_pclk"; 3176 3177 out-ports { 3178 port { 3179 apss_funnel_out: endpoint { 3180 remote-endpoint = <&apss_merge_funnel_in>; 3181 }; 3182 }; 3183 }; 3184 3185 in-ports { 3186 #address-cells = <1>; 3187 #size-cells = <0>; 3188 3189 port@0 { 3190 reg = <0>; 3191 apss_funnel_in0: endpoint { 3192 remote-endpoint = <&etm0_out>; 3193 }; 3194 }; 3195 3196 port@1 { 3197 reg = <1>; 3198 apss_funnel_in1: endpoint { 3199 remote-endpoint = <&etm1_out>; 3200 }; 3201 }; 3202 3203 port@2 { 3204 reg = <2>; 3205 apss_funnel_in2: endpoint { 3206 remote-endpoint = <&etm2_out>; 3207 }; 3208 }; 3209 3210 port@3 { 3211 reg = <3>; 3212 apss_funnel_in3: endpoint { 3213 remote-endpoint = <&etm3_out>; 3214 }; 3215 }; 3216 3217 port@4 { 3218 reg = <4>; 3219 apss_funnel_in4: endpoint { 3220 remote-endpoint = <&etm4_out>; 3221 }; 3222 }; 3223 3224 port@5 { 3225 reg = <5>; 3226 apss_funnel_in5: endpoint { 3227 remote-endpoint = <&etm5_out>; 3228 }; 3229 }; 3230 3231 port@6 { 3232 reg = <6>; 3233 apss_funnel_in6: endpoint { 3234 remote-endpoint = <&etm6_out>; 3235 }; 3236 }; 3237 3238 port@7 { 3239 reg = <7>; 3240 apss_funnel_in7: endpoint { 3241 remote-endpoint = <&etm7_out>; 3242 }; 3243 }; 3244 }; 3245 }; 3246 3247 funnel@7810000 { 3248 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3249 reg = <0 0x07810000 0 0x1000>; 3250 3251 clocks = <&aoss_qmp>; 3252 clock-names = "apb_pclk"; 3253 3254 out-ports { 3255 port { 3256 apss_merge_funnel_out: endpoint { 3257 remote-endpoint = <&funnel1_in4>; 3258 }; 3259 }; 3260 }; 3261 3262 in-ports { 3263 port { 3264 apss_merge_funnel_in: endpoint { 3265 remote-endpoint = <&apss_funnel_out>; 3266 }; 3267 }; 3268 }; 3269 }; 3270 3271 sdhc_2: mmc@8804000 { 3272 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3273 pinctrl-names = "default", "sleep"; 3274 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3275 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3276 status = "disabled"; 3277 3278 reg = <0 0x08804000 0 0x1000>; 3279 3280 iommus = <&apps_smmu 0x100 0x0>; 3281 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3283 interrupt-names = "hc_irq", "pwr_irq"; 3284 3285 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3286 <&gcc GCC_SDCC2_APPS_CLK>, 3287 <&rpmhcc RPMH_CXO_CLK>; 3288 clock-names = "iface", "core", "xo"; 3289 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3290 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3291 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3292 power-domains = <&rpmhpd SC7280_CX>; 3293 operating-points-v2 = <&sdhc2_opp_table>; 3294 3295 bus-width = <4>; 3296 3297 qcom,dll-config = <0x0007642c>; 3298 3299 resets = <&gcc GCC_SDCC2_BCR>; 3300 3301 sdhc2_opp_table: opp-table { 3302 compatible = "operating-points-v2"; 3303 3304 opp-100000000 { 3305 opp-hz = /bits/ 64 <100000000>; 3306 required-opps = <&rpmhpd_opp_low_svs>; 3307 opp-peak-kBps = <1800000 400000>; 3308 opp-avg-kBps = <100000 0>; 3309 }; 3310 3311 opp-202000000 { 3312 opp-hz = /bits/ 64 <202000000>; 3313 required-opps = <&rpmhpd_opp_nom>; 3314 opp-peak-kBps = <5400000 1600000>; 3315 opp-avg-kBps = <200000 0>; 3316 }; 3317 }; 3318 3319 }; 3320 3321 usb_1_hsphy: phy@88e3000 { 3322 compatible = "qcom,sc7280-usb-hs-phy", 3323 "qcom,usb-snps-hs-7nm-phy"; 3324 reg = <0 0x088e3000 0 0x400>; 3325 status = "disabled"; 3326 #phy-cells = <0>; 3327 3328 clocks = <&rpmhcc RPMH_CXO_CLK>; 3329 clock-names = "ref"; 3330 3331 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3332 }; 3333 3334 usb_2_hsphy: phy@88e4000 { 3335 compatible = "qcom,sc7280-usb-hs-phy", 3336 "qcom,usb-snps-hs-7nm-phy"; 3337 reg = <0 0x088e4000 0 0x400>; 3338 status = "disabled"; 3339 #phy-cells = <0>; 3340 3341 clocks = <&rpmhcc RPMH_CXO_CLK>; 3342 clock-names = "ref"; 3343 3344 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3345 }; 3346 3347 usb_1_qmpphy: phy-wrapper@88e9000 { 3348 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3349 "qcom,sm8250-qmp-usb3-dp-phy"; 3350 reg = <0 0x088e9000 0 0x200>, 3351 <0 0x088e8000 0 0x40>, 3352 <0 0x088ea000 0 0x200>; 3353 status = "disabled"; 3354 #address-cells = <2>; 3355 #size-cells = <2>; 3356 ranges; 3357 3358 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3359 <&rpmhcc RPMH_CXO_CLK>, 3360 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3361 clock-names = "aux", "ref_clk_src", "com_aux"; 3362 3363 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3364 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3365 reset-names = "phy", "common"; 3366 3367 usb_1_ssphy: usb3-phy@88e9200 { 3368 reg = <0 0x088e9200 0 0x200>, 3369 <0 0x088e9400 0 0x200>, 3370 <0 0x088e9c00 0 0x400>, 3371 <0 0x088e9600 0 0x200>, 3372 <0 0x088e9800 0 0x200>, 3373 <0 0x088e9a00 0 0x100>; 3374 #clock-cells = <0>; 3375 #phy-cells = <0>; 3376 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3377 clock-names = "pipe0"; 3378 clock-output-names = "usb3_phy_pipe_clk_src"; 3379 }; 3380 3381 dp_phy: dp-phy@88ea200 { 3382 reg = <0 0x088ea200 0 0x200>, 3383 <0 0x088ea400 0 0x200>, 3384 <0 0x088eaa00 0 0x200>, 3385 <0 0x088ea600 0 0x200>, 3386 <0 0x088ea800 0 0x200>; 3387 #phy-cells = <0>; 3388 #clock-cells = <1>; 3389 }; 3390 }; 3391 3392 usb_2: usb@8cf8800 { 3393 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3394 reg = <0 0x08cf8800 0 0x400>; 3395 status = "disabled"; 3396 #address-cells = <2>; 3397 #size-cells = <2>; 3398 ranges; 3399 dma-ranges; 3400 3401 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3402 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3403 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3404 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3405 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3406 clock-names = "cfg_noc", 3407 "core", 3408 "iface", 3409 "sleep", 3410 "mock_utmi"; 3411 3412 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3413 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3414 assigned-clock-rates = <19200000>, <200000000>; 3415 3416 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3417 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3418 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3419 interrupt-names = "hs_phy_irq", 3420 "dp_hs_phy_irq", 3421 "dm_hs_phy_irq"; 3422 3423 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3424 required-opps = <&rpmhpd_opp_nom>; 3425 3426 resets = <&gcc GCC_USB30_SEC_BCR>; 3427 3428 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3429 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3430 interconnect-names = "usb-ddr", "apps-usb"; 3431 3432 usb_2_dwc3: usb@8c00000 { 3433 compatible = "snps,dwc3"; 3434 reg = <0 0x08c00000 0 0xe000>; 3435 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3436 iommus = <&apps_smmu 0xa0 0x0>; 3437 snps,dis_u2_susphy_quirk; 3438 snps,dis_enblslpm_quirk; 3439 phys = <&usb_2_hsphy>; 3440 phy-names = "usb2-phy"; 3441 maximum-speed = "high-speed"; 3442 usb-role-switch; 3443 port { 3444 usb2_role_switch: endpoint { 3445 remote-endpoint = <&eud_ep>; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 qspi: spi@88dc000 { 3452 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3453 reg = <0 0x088dc000 0 0x1000>; 3454 #address-cells = <1>; 3455 #size-cells = <0>; 3456 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3457 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3458 <&gcc GCC_QSPI_CORE_CLK>; 3459 clock-names = "iface", "core"; 3460 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3461 &cnoc2 SLAVE_QSPI_0 0>; 3462 interconnect-names = "qspi-config"; 3463 power-domains = <&rpmhpd SC7280_CX>; 3464 operating-points-v2 = <&qspi_opp_table>; 3465 status = "disabled"; 3466 }; 3467 3468 remoteproc_wpss: remoteproc@8a00000 { 3469 compatible = "qcom,sc7280-wpss-pil"; 3470 reg = <0 0x08a00000 0 0x10000>; 3471 3472 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3473 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3474 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3475 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3476 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3477 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3478 interrupt-names = "wdog", "fatal", "ready", "handover", 3479 "stop-ack", "shutdown-ack"; 3480 3481 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3482 <&gcc GCC_WPSS_AHB_CLK>, 3483 <&gcc GCC_WPSS_RSCP_CLK>, 3484 <&rpmhcc RPMH_CXO_CLK>; 3485 clock-names = "ahb_bdg", "ahb", 3486 "rscp", "xo"; 3487 3488 power-domains = <&rpmhpd SC7280_CX>, 3489 <&rpmhpd SC7280_MX>; 3490 power-domain-names = "cx", "mx"; 3491 3492 memory-region = <&wpss_mem>; 3493 3494 qcom,qmp = <&aoss_qmp>; 3495 3496 qcom,smem-states = <&wpss_smp2p_out 0>; 3497 qcom,smem-state-names = "stop"; 3498 3499 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3500 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3501 reset-names = "restart", "pdc_sync"; 3502 3503 qcom,halt-regs = <&tcsr_1 0x17000>; 3504 3505 status = "disabled"; 3506 3507 glink-edge { 3508 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3509 IPCC_MPROC_SIGNAL_GLINK_QMP 3510 IRQ_TYPE_EDGE_RISING>; 3511 mboxes = <&ipcc IPCC_CLIENT_WPSS 3512 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3513 3514 label = "wpss"; 3515 qcom,remote-pid = <13>; 3516 }; 3517 }; 3518 3519 pmu@9091000 { 3520 compatible = "qcom,sc7280-llcc-bwmon"; 3521 reg = <0 0x9091000 0 0x1000>; 3522 3523 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3524 3525 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3526 3527 operating-points-v2 = <&llcc_bwmon_opp_table>; 3528 3529 llcc_bwmon_opp_table: opp-table { 3530 compatible = "operating-points-v2"; 3531 3532 opp-0 { 3533 opp-peak-kBps = <800000>; 3534 }; 3535 opp-1 { 3536 opp-peak-kBps = <1804000>; 3537 }; 3538 opp-2 { 3539 opp-peak-kBps = <2188000>; 3540 }; 3541 opp-3 { 3542 opp-peak-kBps = <3072000>; 3543 }; 3544 opp-4 { 3545 opp-peak-kBps = <4068000>; 3546 }; 3547 opp-5 { 3548 opp-peak-kBps = <6220000>; 3549 }; 3550 opp-6 { 3551 opp-peak-kBps = <6832000>; 3552 }; 3553 opp-7 { 3554 opp-peak-kBps = <8532000>; 3555 }; 3556 }; 3557 }; 3558 3559 pmu@90b6400 { 3560 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3561 reg = <0 0x090b6400 0 0x600>; 3562 3563 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3564 3565 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3566 operating-points-v2 = <&cpu_bwmon_opp_table>; 3567 3568 cpu_bwmon_opp_table: opp-table { 3569 compatible = "operating-points-v2"; 3570 3571 opp-0 { 3572 opp-peak-kBps = <2400000>; 3573 }; 3574 opp-1 { 3575 opp-peak-kBps = <4800000>; 3576 }; 3577 opp-2 { 3578 opp-peak-kBps = <7456000>; 3579 }; 3580 opp-3 { 3581 opp-peak-kBps = <9600000>; 3582 }; 3583 opp-4 { 3584 opp-peak-kBps = <12896000>; 3585 }; 3586 opp-5 { 3587 opp-peak-kBps = <14928000>; 3588 }; 3589 opp-6 { 3590 opp-peak-kBps = <17056000>; 3591 }; 3592 }; 3593 }; 3594 3595 dc_noc: interconnect@90e0000 { 3596 reg = <0 0x090e0000 0 0x5080>; 3597 compatible = "qcom,sc7280-dc-noc"; 3598 #interconnect-cells = <2>; 3599 qcom,bcm-voters = <&apps_bcm_voter>; 3600 }; 3601 3602 gem_noc: interconnect@9100000 { 3603 reg = <0 0x9100000 0 0xe2200>; 3604 compatible = "qcom,sc7280-gem-noc"; 3605 #interconnect-cells = <2>; 3606 qcom,bcm-voters = <&apps_bcm_voter>; 3607 }; 3608 3609 system-cache-controller@9200000 { 3610 compatible = "qcom,sc7280-llcc"; 3611 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3612 reg-names = "llcc_base", "llcc_broadcast_base"; 3613 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3614 }; 3615 3616 eud: eud@88e0000 { 3617 compatible = "qcom,sc7280-eud","qcom,eud"; 3618 reg = <0 0x88e0000 0 0x2000>, 3619 <0 0x88e2000 0 0x1000>; 3620 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3621 ports { 3622 port@0 { 3623 eud_ep: endpoint { 3624 remote-endpoint = <&usb2_role_switch>; 3625 }; 3626 }; 3627 port@1 { 3628 eud_con: endpoint { 3629 remote-endpoint = <&con_eud>; 3630 }; 3631 }; 3632 }; 3633 }; 3634 3635 eud_typec: connector { 3636 compatible = "usb-c-connector"; 3637 ports { 3638 port@0 { 3639 con_eud: endpoint { 3640 remote-endpoint = <&eud_con>; 3641 }; 3642 }; 3643 }; 3644 }; 3645 3646 nsp_noc: interconnect@a0c0000 { 3647 reg = <0 0x0a0c0000 0 0x10000>; 3648 compatible = "qcom,sc7280-nsp-noc"; 3649 #interconnect-cells = <2>; 3650 qcom,bcm-voters = <&apps_bcm_voter>; 3651 }; 3652 3653 usb_1: usb@a6f8800 { 3654 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3655 reg = <0 0x0a6f8800 0 0x400>; 3656 status = "disabled"; 3657 #address-cells = <2>; 3658 #size-cells = <2>; 3659 ranges; 3660 dma-ranges; 3661 3662 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3663 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3664 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3665 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3666 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3667 clock-names = "cfg_noc", 3668 "core", 3669 "iface", 3670 "sleep", 3671 "mock_utmi"; 3672 3673 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3674 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3675 assigned-clock-rates = <19200000>, <200000000>; 3676 3677 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3678 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3679 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3680 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3681 interrupt-names = "hs_phy_irq", 3682 "dp_hs_phy_irq", 3683 "dm_hs_phy_irq", 3684 "ss_phy_irq"; 3685 3686 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3687 required-opps = <&rpmhpd_opp_nom>; 3688 3689 resets = <&gcc GCC_USB30_PRIM_BCR>; 3690 3691 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3692 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3693 interconnect-names = "usb-ddr", "apps-usb"; 3694 3695 wakeup-source; 3696 3697 usb_1_dwc3: usb@a600000 { 3698 compatible = "snps,dwc3"; 3699 reg = <0 0x0a600000 0 0xe000>; 3700 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3701 iommus = <&apps_smmu 0xe0 0x0>; 3702 snps,dis_u2_susphy_quirk; 3703 snps,dis_enblslpm_quirk; 3704 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3705 phy-names = "usb2-phy", "usb3-phy"; 3706 maximum-speed = "super-speed"; 3707 }; 3708 }; 3709 3710 venus: video-codec@aa00000 { 3711 compatible = "qcom,sc7280-venus"; 3712 reg = <0 0x0aa00000 0 0xd0600>; 3713 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3714 3715 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3716 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3717 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3718 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3719 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3720 clock-names = "core", "bus", "iface", 3721 "vcodec_core", "vcodec_bus"; 3722 3723 power-domains = <&videocc MVSC_GDSC>, 3724 <&videocc MVS0_GDSC>, 3725 <&rpmhpd SC7280_CX>; 3726 power-domain-names = "venus", "vcodec0", "cx"; 3727 operating-points-v2 = <&venus_opp_table>; 3728 3729 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3730 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3731 interconnect-names = "cpu-cfg", "video-mem"; 3732 3733 iommus = <&apps_smmu 0x2180 0x20>, 3734 <&apps_smmu 0x2184 0x20>; 3735 memory-region = <&video_mem>; 3736 3737 video-decoder { 3738 compatible = "venus-decoder"; 3739 }; 3740 3741 video-encoder { 3742 compatible = "venus-encoder"; 3743 }; 3744 3745 video-firmware { 3746 iommus = <&apps_smmu 0x21a2 0x0>; 3747 }; 3748 3749 venus_opp_table: opp-table { 3750 compatible = "operating-points-v2"; 3751 3752 opp-133330000 { 3753 opp-hz = /bits/ 64 <133330000>; 3754 required-opps = <&rpmhpd_opp_low_svs>; 3755 }; 3756 3757 opp-240000000 { 3758 opp-hz = /bits/ 64 <240000000>; 3759 required-opps = <&rpmhpd_opp_svs>; 3760 }; 3761 3762 opp-335000000 { 3763 opp-hz = /bits/ 64 <335000000>; 3764 required-opps = <&rpmhpd_opp_svs_l1>; 3765 }; 3766 3767 opp-424000000 { 3768 opp-hz = /bits/ 64 <424000000>; 3769 required-opps = <&rpmhpd_opp_nom>; 3770 }; 3771 3772 opp-460000048 { 3773 opp-hz = /bits/ 64 <460000048>; 3774 required-opps = <&rpmhpd_opp_turbo>; 3775 }; 3776 }; 3777 3778 }; 3779 3780 videocc: clock-controller@aaf0000 { 3781 compatible = "qcom,sc7280-videocc"; 3782 reg = <0 0xaaf0000 0 0x10000>; 3783 clocks = <&rpmhcc RPMH_CXO_CLK>, 3784 <&rpmhcc RPMH_CXO_CLK_A>; 3785 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3786 #clock-cells = <1>; 3787 #reset-cells = <1>; 3788 #power-domain-cells = <1>; 3789 }; 3790 3791 camcc: clock-controller@ad00000 { 3792 compatible = "qcom,sc7280-camcc"; 3793 reg = <0 0x0ad00000 0 0x10000>; 3794 clocks = <&rpmhcc RPMH_CXO_CLK>, 3795 <&rpmhcc RPMH_CXO_CLK_A>, 3796 <&sleep_clk>; 3797 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3798 #clock-cells = <1>; 3799 #reset-cells = <1>; 3800 #power-domain-cells = <1>; 3801 }; 3802 3803 dispcc: clock-controller@af00000 { 3804 compatible = "qcom,sc7280-dispcc"; 3805 reg = <0 0xaf00000 0 0x20000>; 3806 clocks = <&rpmhcc RPMH_CXO_CLK>, 3807 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3808 <&mdss_dsi_phy 0>, 3809 <&mdss_dsi_phy 1>, 3810 <&dp_phy 0>, 3811 <&dp_phy 1>, 3812 <&mdss_edp_phy 0>, 3813 <&mdss_edp_phy 1>; 3814 clock-names = "bi_tcxo", 3815 "gcc_disp_gpll0_clk", 3816 "dsi0_phy_pll_out_byteclk", 3817 "dsi0_phy_pll_out_dsiclk", 3818 "dp_phy_pll_link_clk", 3819 "dp_phy_pll_vco_div_clk", 3820 "edp_phy_pll_link_clk", 3821 "edp_phy_pll_vco_div_clk"; 3822 #clock-cells = <1>; 3823 #reset-cells = <1>; 3824 #power-domain-cells = <1>; 3825 }; 3826 3827 mdss: display-subsystem@ae00000 { 3828 compatible = "qcom,sc7280-mdss"; 3829 reg = <0 0x0ae00000 0 0x1000>; 3830 reg-names = "mdss"; 3831 3832 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3833 3834 clocks = <&gcc GCC_DISP_AHB_CLK>, 3835 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3836 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3837 clock-names = "iface", 3838 "ahb", 3839 "core"; 3840 3841 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3842 interrupt-controller; 3843 #interrupt-cells = <1>; 3844 3845 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3846 interconnect-names = "mdp0-mem"; 3847 3848 iommus = <&apps_smmu 0x900 0x402>; 3849 3850 #address-cells = <2>; 3851 #size-cells = <2>; 3852 ranges; 3853 3854 status = "disabled"; 3855 3856 mdss_mdp: display-controller@ae01000 { 3857 compatible = "qcom,sc7280-dpu"; 3858 reg = <0 0x0ae01000 0 0x8f030>, 3859 <0 0x0aeb0000 0 0x2008>; 3860 reg-names = "mdp", "vbif"; 3861 3862 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3863 <&gcc GCC_DISP_SF_AXI_CLK>, 3864 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3865 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3866 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3867 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3868 clock-names = "bus", 3869 "nrt_bus", 3870 "iface", 3871 "lut", 3872 "core", 3873 "vsync"; 3874 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3875 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3876 assigned-clock-rates = <19200000>, 3877 <19200000>; 3878 operating-points-v2 = <&mdp_opp_table>; 3879 power-domains = <&rpmhpd SC7280_CX>; 3880 3881 interrupt-parent = <&mdss>; 3882 interrupts = <0>; 3883 3884 status = "disabled"; 3885 3886 ports { 3887 #address-cells = <1>; 3888 #size-cells = <0>; 3889 3890 port@0 { 3891 reg = <0>; 3892 dpu_intf1_out: endpoint { 3893 remote-endpoint = <&dsi0_in>; 3894 }; 3895 }; 3896 3897 port@1 { 3898 reg = <1>; 3899 dpu_intf5_out: endpoint { 3900 remote-endpoint = <&edp_in>; 3901 }; 3902 }; 3903 3904 port@2 { 3905 reg = <2>; 3906 dpu_intf0_out: endpoint { 3907 remote-endpoint = <&dp_in>; 3908 }; 3909 }; 3910 }; 3911 3912 mdp_opp_table: opp-table { 3913 compatible = "operating-points-v2"; 3914 3915 opp-200000000 { 3916 opp-hz = /bits/ 64 <200000000>; 3917 required-opps = <&rpmhpd_opp_low_svs>; 3918 }; 3919 3920 opp-300000000 { 3921 opp-hz = /bits/ 64 <300000000>; 3922 required-opps = <&rpmhpd_opp_svs>; 3923 }; 3924 3925 opp-380000000 { 3926 opp-hz = /bits/ 64 <380000000>; 3927 required-opps = <&rpmhpd_opp_svs_l1>; 3928 }; 3929 3930 opp-506666667 { 3931 opp-hz = /bits/ 64 <506666667>; 3932 required-opps = <&rpmhpd_opp_nom>; 3933 }; 3934 }; 3935 }; 3936 3937 mdss_dsi: dsi@ae94000 { 3938 compatible = "qcom,mdss-dsi-ctrl"; 3939 reg = <0 0x0ae94000 0 0x400>; 3940 reg-names = "dsi_ctrl"; 3941 3942 interrupt-parent = <&mdss>; 3943 interrupts = <4>; 3944 3945 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3946 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3947 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3948 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3949 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3950 <&gcc GCC_DISP_HF_AXI_CLK>; 3951 clock-names = "byte", 3952 "byte_intf", 3953 "pixel", 3954 "core", 3955 "iface", 3956 "bus"; 3957 3958 operating-points-v2 = <&dsi_opp_table>; 3959 power-domains = <&rpmhpd SC7280_CX>; 3960 3961 phys = <&mdss_dsi_phy>; 3962 phy-names = "dsi"; 3963 3964 #address-cells = <1>; 3965 #size-cells = <0>; 3966 3967 status = "disabled"; 3968 3969 ports { 3970 #address-cells = <1>; 3971 #size-cells = <0>; 3972 3973 port@0 { 3974 reg = <0>; 3975 dsi0_in: endpoint { 3976 remote-endpoint = <&dpu_intf1_out>; 3977 }; 3978 }; 3979 3980 port@1 { 3981 reg = <1>; 3982 dsi0_out: endpoint { 3983 }; 3984 }; 3985 }; 3986 3987 dsi_opp_table: opp-table { 3988 compatible = "operating-points-v2"; 3989 3990 opp-187500000 { 3991 opp-hz = /bits/ 64 <187500000>; 3992 required-opps = <&rpmhpd_opp_low_svs>; 3993 }; 3994 3995 opp-300000000 { 3996 opp-hz = /bits/ 64 <300000000>; 3997 required-opps = <&rpmhpd_opp_svs>; 3998 }; 3999 4000 opp-358000000 { 4001 opp-hz = /bits/ 64 <358000000>; 4002 required-opps = <&rpmhpd_opp_svs_l1>; 4003 }; 4004 }; 4005 }; 4006 4007 mdss_dsi_phy: phy@ae94400 { 4008 compatible = "qcom,sc7280-dsi-phy-7nm"; 4009 reg = <0 0x0ae94400 0 0x200>, 4010 <0 0x0ae94600 0 0x280>, 4011 <0 0x0ae94900 0 0x280>; 4012 reg-names = "dsi_phy", 4013 "dsi_phy_lane", 4014 "dsi_pll"; 4015 4016 #clock-cells = <1>; 4017 #phy-cells = <0>; 4018 4019 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4020 <&rpmhcc RPMH_CXO_CLK>; 4021 clock-names = "iface", "ref"; 4022 4023 status = "disabled"; 4024 }; 4025 4026 mdss_edp: edp@aea0000 { 4027 compatible = "qcom,sc7280-edp"; 4028 pinctrl-names = "default"; 4029 pinctrl-0 = <&edp_hot_plug_det>; 4030 4031 reg = <0 0xaea0000 0 0x200>, 4032 <0 0xaea0200 0 0x200>, 4033 <0 0xaea0400 0 0xc00>, 4034 <0 0xaea1000 0 0x400>; 4035 4036 interrupt-parent = <&mdss>; 4037 interrupts = <14>; 4038 4039 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4040 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4041 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4042 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4043 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4044 clock-names = "core_iface", 4045 "core_aux", 4046 "ctrl_link", 4047 "ctrl_link_iface", 4048 "stream_pixel"; 4049 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4050 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4051 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4052 4053 phys = <&mdss_edp_phy>; 4054 phy-names = "dp"; 4055 4056 operating-points-v2 = <&edp_opp_table>; 4057 power-domains = <&rpmhpd SC7280_CX>; 4058 4059 status = "disabled"; 4060 4061 ports { 4062 #address-cells = <1>; 4063 #size-cells = <0>; 4064 4065 port@0 { 4066 reg = <0>; 4067 edp_in: endpoint { 4068 remote-endpoint = <&dpu_intf5_out>; 4069 }; 4070 }; 4071 4072 port@1 { 4073 reg = <1>; 4074 mdss_edp_out: endpoint { }; 4075 }; 4076 }; 4077 4078 edp_opp_table: opp-table { 4079 compatible = "operating-points-v2"; 4080 4081 opp-160000000 { 4082 opp-hz = /bits/ 64 <160000000>; 4083 required-opps = <&rpmhpd_opp_low_svs>; 4084 }; 4085 4086 opp-270000000 { 4087 opp-hz = /bits/ 64 <270000000>; 4088 required-opps = <&rpmhpd_opp_svs>; 4089 }; 4090 4091 opp-540000000 { 4092 opp-hz = /bits/ 64 <540000000>; 4093 required-opps = <&rpmhpd_opp_nom>; 4094 }; 4095 4096 opp-810000000 { 4097 opp-hz = /bits/ 64 <810000000>; 4098 required-opps = <&rpmhpd_opp_nom>; 4099 }; 4100 }; 4101 }; 4102 4103 mdss_edp_phy: phy@aec2a00 { 4104 compatible = "qcom,sc7280-edp-phy"; 4105 4106 reg = <0 0xaec2a00 0 0x19c>, 4107 <0 0xaec2200 0 0xa0>, 4108 <0 0xaec2600 0 0xa0>, 4109 <0 0xaec2000 0 0x1c0>; 4110 4111 clocks = <&rpmhcc RPMH_CXO_CLK>, 4112 <&gcc GCC_EDP_CLKREF_EN>; 4113 clock-names = "aux", 4114 "cfg_ahb"; 4115 4116 #clock-cells = <1>; 4117 #phy-cells = <0>; 4118 4119 status = "disabled"; 4120 }; 4121 4122 mdss_dp: displayport-controller@ae90000 { 4123 compatible = "qcom,sc7280-dp"; 4124 4125 reg = <0 0xae90000 0 0x200>, 4126 <0 0xae90200 0 0x200>, 4127 <0 0xae90400 0 0xc00>, 4128 <0 0xae91000 0 0x400>, 4129 <0 0xae91400 0 0x400>; 4130 4131 interrupt-parent = <&mdss>; 4132 interrupts = <12>; 4133 4134 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4135 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4136 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4137 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4138 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4139 clock-names = "core_iface", 4140 "core_aux", 4141 "ctrl_link", 4142 "ctrl_link_iface", 4143 "stream_pixel"; 4144 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4145 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4146 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4147 phys = <&dp_phy>; 4148 phy-names = "dp"; 4149 4150 operating-points-v2 = <&dp_opp_table>; 4151 power-domains = <&rpmhpd SC7280_CX>; 4152 4153 #sound-dai-cells = <0>; 4154 4155 status = "disabled"; 4156 4157 ports { 4158 #address-cells = <1>; 4159 #size-cells = <0>; 4160 4161 port@0 { 4162 reg = <0>; 4163 dp_in: endpoint { 4164 remote-endpoint = <&dpu_intf0_out>; 4165 }; 4166 }; 4167 4168 port@1 { 4169 reg = <1>; 4170 dp_out: endpoint { }; 4171 }; 4172 }; 4173 4174 dp_opp_table: opp-table { 4175 compatible = "operating-points-v2"; 4176 4177 opp-160000000 { 4178 opp-hz = /bits/ 64 <160000000>; 4179 required-opps = <&rpmhpd_opp_low_svs>; 4180 }; 4181 4182 opp-270000000 { 4183 opp-hz = /bits/ 64 <270000000>; 4184 required-opps = <&rpmhpd_opp_svs>; 4185 }; 4186 4187 opp-540000000 { 4188 opp-hz = /bits/ 64 <540000000>; 4189 required-opps = <&rpmhpd_opp_svs_l1>; 4190 }; 4191 4192 opp-810000000 { 4193 opp-hz = /bits/ 64 <810000000>; 4194 required-opps = <&rpmhpd_opp_nom>; 4195 }; 4196 }; 4197 }; 4198 }; 4199 4200 pdc: interrupt-controller@b220000 { 4201 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4202 reg = <0 0x0b220000 0 0x30000>; 4203 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4204 <55 306 4>, <59 312 3>, <62 374 2>, 4205 <64 434 2>, <66 438 3>, <69 86 1>, 4206 <70 520 54>, <124 609 31>, <155 63 1>, 4207 <156 716 12>; 4208 #interrupt-cells = <2>; 4209 interrupt-parent = <&intc>; 4210 interrupt-controller; 4211 }; 4212 4213 pdc_reset: reset-controller@b5e0000 { 4214 compatible = "qcom,sc7280-pdc-global"; 4215 reg = <0 0x0b5e0000 0 0x20000>; 4216 #reset-cells = <1>; 4217 }; 4218 4219 tsens0: thermal-sensor@c263000 { 4220 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4221 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4222 <0 0x0c222000 0 0x1ff>; /* SROT */ 4223 #qcom,sensors = <15>; 4224 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4226 interrupt-names = "uplow","critical"; 4227 #thermal-sensor-cells = <1>; 4228 }; 4229 4230 tsens1: thermal-sensor@c265000 { 4231 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4232 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4233 <0 0x0c223000 0 0x1ff>; /* SROT */ 4234 #qcom,sensors = <12>; 4235 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4237 interrupt-names = "uplow","critical"; 4238 #thermal-sensor-cells = <1>; 4239 }; 4240 4241 aoss_reset: reset-controller@c2a0000 { 4242 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4243 reg = <0 0x0c2a0000 0 0x31000>; 4244 #reset-cells = <1>; 4245 }; 4246 4247 aoss_qmp: power-controller@c300000 { 4248 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4249 reg = <0 0x0c300000 0 0x400>; 4250 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4251 IPCC_MPROC_SIGNAL_GLINK_QMP 4252 IRQ_TYPE_EDGE_RISING>; 4253 mboxes = <&ipcc IPCC_CLIENT_AOP 4254 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4255 4256 #clock-cells = <0>; 4257 }; 4258 4259 sram@c3f0000 { 4260 compatible = "qcom,rpmh-stats"; 4261 reg = <0 0x0c3f0000 0 0x400>; 4262 }; 4263 4264 spmi_bus: spmi@c440000 { 4265 compatible = "qcom,spmi-pmic-arb"; 4266 reg = <0 0x0c440000 0 0x1100>, 4267 <0 0x0c600000 0 0x2000000>, 4268 <0 0x0e600000 0 0x100000>, 4269 <0 0x0e700000 0 0xa0000>, 4270 <0 0x0c40a000 0 0x26000>; 4271 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4272 interrupt-names = "periph_irq"; 4273 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4274 qcom,ee = <0>; 4275 qcom,channel = <0>; 4276 #address-cells = <1>; 4277 #size-cells = <1>; 4278 interrupt-controller; 4279 #interrupt-cells = <4>; 4280 }; 4281 4282 tlmm: pinctrl@f100000 { 4283 compatible = "qcom,sc7280-pinctrl"; 4284 reg = <0 0x0f100000 0 0x300000>; 4285 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4286 gpio-controller; 4287 #gpio-cells = <2>; 4288 interrupt-controller; 4289 #interrupt-cells = <2>; 4290 gpio-ranges = <&tlmm 0 0 175>; 4291 wakeup-parent = <&pdc>; 4292 4293 dp_hot_plug_det: dp-hot-plug-det-state { 4294 pins = "gpio47"; 4295 function = "dp_hot"; 4296 }; 4297 4298 edp_hot_plug_det: edp-hot-plug-det-state { 4299 pins = "gpio60"; 4300 function = "edp_hot"; 4301 }; 4302 4303 mi2s0_data0: mi2s0-data0-state { 4304 pins = "gpio98"; 4305 function = "mi2s0_data0"; 4306 }; 4307 4308 mi2s0_data1: mi2s0-data1-state { 4309 pins = "gpio99"; 4310 function = "mi2s0_data1"; 4311 }; 4312 4313 mi2s0_mclk: mi2s0-mclk-state { 4314 pins = "gpio96"; 4315 function = "pri_mi2s"; 4316 }; 4317 4318 mi2s0_sclk: mi2s0-sclk-state { 4319 pins = "gpio97"; 4320 function = "mi2s0_sck"; 4321 }; 4322 4323 mi2s0_ws: mi2s0-ws-state { 4324 pins = "gpio100"; 4325 function = "mi2s0_ws"; 4326 }; 4327 4328 mi2s1_data0: mi2s1-data0-state { 4329 pins = "gpio107"; 4330 function = "mi2s1_data0"; 4331 }; 4332 4333 mi2s1_sclk: mi2s1-sclk-state { 4334 pins = "gpio106"; 4335 function = "mi2s1_sck"; 4336 }; 4337 4338 mi2s1_ws: mi2s1-ws-state { 4339 pins = "gpio108"; 4340 function = "mi2s1_ws"; 4341 }; 4342 4343 pcie1_clkreq_n: pcie1-clkreq-n-state { 4344 pins = "gpio79"; 4345 function = "pcie1_clkreqn"; 4346 }; 4347 4348 qspi_clk: qspi-clk-state { 4349 pins = "gpio14"; 4350 function = "qspi_clk"; 4351 }; 4352 4353 qspi_cs0: qspi-cs0-state { 4354 pins = "gpio15"; 4355 function = "qspi_cs"; 4356 }; 4357 4358 qspi_cs1: qspi-cs1-state { 4359 pins = "gpio19"; 4360 function = "qspi_cs"; 4361 }; 4362 4363 qspi_data01: qspi-data01-state { 4364 pins = "gpio12", "gpio13"; 4365 function = "qspi_data"; 4366 }; 4367 4368 qspi_data12: qspi-data12-state { 4369 pins = "gpio16", "gpio17"; 4370 function = "qspi_data"; 4371 }; 4372 4373 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4374 pins = "gpio0", "gpio1"; 4375 function = "qup00"; 4376 }; 4377 4378 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4379 pins = "gpio4", "gpio5"; 4380 function = "qup01"; 4381 }; 4382 4383 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4384 pins = "gpio8", "gpio9"; 4385 function = "qup02"; 4386 }; 4387 4388 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4389 pins = "gpio12", "gpio13"; 4390 function = "qup03"; 4391 }; 4392 4393 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4394 pins = "gpio16", "gpio17"; 4395 function = "qup04"; 4396 }; 4397 4398 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4399 pins = "gpio20", "gpio21"; 4400 function = "qup05"; 4401 }; 4402 4403 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4404 pins = "gpio24", "gpio25"; 4405 function = "qup06"; 4406 }; 4407 4408 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4409 pins = "gpio28", "gpio29"; 4410 function = "qup07"; 4411 }; 4412 4413 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4414 pins = "gpio32", "gpio33"; 4415 function = "qup10"; 4416 }; 4417 4418 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4419 pins = "gpio36", "gpio37"; 4420 function = "qup11"; 4421 }; 4422 4423 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4424 pins = "gpio40", "gpio41"; 4425 function = "qup12"; 4426 }; 4427 4428 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4429 pins = "gpio44", "gpio45"; 4430 function = "qup13"; 4431 }; 4432 4433 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4434 pins = "gpio48", "gpio49"; 4435 function = "qup14"; 4436 }; 4437 4438 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4439 pins = "gpio52", "gpio53"; 4440 function = "qup15"; 4441 }; 4442 4443 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4444 pins = "gpio56", "gpio57"; 4445 function = "qup16"; 4446 }; 4447 4448 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4449 pins = "gpio60", "gpio61"; 4450 function = "qup17"; 4451 }; 4452 4453 qup_spi0_data_clk: qup-spi0-data-clk-state { 4454 pins = "gpio0", "gpio1", "gpio2"; 4455 function = "qup00"; 4456 }; 4457 4458 qup_spi0_cs: qup-spi0-cs-state { 4459 pins = "gpio3"; 4460 function = "qup00"; 4461 }; 4462 4463 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4464 pins = "gpio3"; 4465 function = "gpio"; 4466 }; 4467 4468 qup_spi1_data_clk: qup-spi1-data-clk-state { 4469 pins = "gpio4", "gpio5", "gpio6"; 4470 function = "qup01"; 4471 }; 4472 4473 qup_spi1_cs: qup-spi1-cs-state { 4474 pins = "gpio7"; 4475 function = "qup01"; 4476 }; 4477 4478 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4479 pins = "gpio7"; 4480 function = "gpio"; 4481 }; 4482 4483 qup_spi2_data_clk: qup-spi2-data-clk-state { 4484 pins = "gpio8", "gpio9", "gpio10"; 4485 function = "qup02"; 4486 }; 4487 4488 qup_spi2_cs: qup-spi2-cs-state { 4489 pins = "gpio11"; 4490 function = "qup02"; 4491 }; 4492 4493 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4494 pins = "gpio11"; 4495 function = "gpio"; 4496 }; 4497 4498 qup_spi3_data_clk: qup-spi3-data-clk-state { 4499 pins = "gpio12", "gpio13", "gpio14"; 4500 function = "qup03"; 4501 }; 4502 4503 qup_spi3_cs: qup-spi3-cs-state { 4504 pins = "gpio15"; 4505 function = "qup03"; 4506 }; 4507 4508 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4509 pins = "gpio15"; 4510 function = "gpio"; 4511 }; 4512 4513 qup_spi4_data_clk: qup-spi4-data-clk-state { 4514 pins = "gpio16", "gpio17", "gpio18"; 4515 function = "qup04"; 4516 }; 4517 4518 qup_spi4_cs: qup-spi4-cs-state { 4519 pins = "gpio19"; 4520 function = "qup04"; 4521 }; 4522 4523 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4524 pins = "gpio19"; 4525 function = "gpio"; 4526 }; 4527 4528 qup_spi5_data_clk: qup-spi5-data-clk-state { 4529 pins = "gpio20", "gpio21", "gpio22"; 4530 function = "qup05"; 4531 }; 4532 4533 qup_spi5_cs: qup-spi5-cs-state { 4534 pins = "gpio23"; 4535 function = "qup05"; 4536 }; 4537 4538 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4539 pins = "gpio23"; 4540 function = "gpio"; 4541 }; 4542 4543 qup_spi6_data_clk: qup-spi6-data-clk-state { 4544 pins = "gpio24", "gpio25", "gpio26"; 4545 function = "qup06"; 4546 }; 4547 4548 qup_spi6_cs: qup-spi6-cs-state { 4549 pins = "gpio27"; 4550 function = "qup06"; 4551 }; 4552 4553 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4554 pins = "gpio27"; 4555 function = "gpio"; 4556 }; 4557 4558 qup_spi7_data_clk: qup-spi7-data-clk-state { 4559 pins = "gpio28", "gpio29", "gpio30"; 4560 function = "qup07"; 4561 }; 4562 4563 qup_spi7_cs: qup-spi7-cs-state { 4564 pins = "gpio31"; 4565 function = "qup07"; 4566 }; 4567 4568 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4569 pins = "gpio31"; 4570 function = "gpio"; 4571 }; 4572 4573 qup_spi8_data_clk: qup-spi8-data-clk-state { 4574 pins = "gpio32", "gpio33", "gpio34"; 4575 function = "qup10"; 4576 }; 4577 4578 qup_spi8_cs: qup-spi8-cs-state { 4579 pins = "gpio35"; 4580 function = "qup10"; 4581 }; 4582 4583 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4584 pins = "gpio35"; 4585 function = "gpio"; 4586 }; 4587 4588 qup_spi9_data_clk: qup-spi9-data-clk-state { 4589 pins = "gpio36", "gpio37", "gpio38"; 4590 function = "qup11"; 4591 }; 4592 4593 qup_spi9_cs: qup-spi9-cs-state { 4594 pins = "gpio39"; 4595 function = "qup11"; 4596 }; 4597 4598 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4599 pins = "gpio39"; 4600 function = "gpio"; 4601 }; 4602 4603 qup_spi10_data_clk: qup-spi10-data-clk-state { 4604 pins = "gpio40", "gpio41", "gpio42"; 4605 function = "qup12"; 4606 }; 4607 4608 qup_spi10_cs: qup-spi10-cs-state { 4609 pins = "gpio43"; 4610 function = "qup12"; 4611 }; 4612 4613 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4614 pins = "gpio43"; 4615 function = "gpio"; 4616 }; 4617 4618 qup_spi11_data_clk: qup-spi11-data-clk-state { 4619 pins = "gpio44", "gpio45", "gpio46"; 4620 function = "qup13"; 4621 }; 4622 4623 qup_spi11_cs: qup-spi11-cs-state { 4624 pins = "gpio47"; 4625 function = "qup13"; 4626 }; 4627 4628 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4629 pins = "gpio47"; 4630 function = "gpio"; 4631 }; 4632 4633 qup_spi12_data_clk: qup-spi12-data-clk-state { 4634 pins = "gpio48", "gpio49", "gpio50"; 4635 function = "qup14"; 4636 }; 4637 4638 qup_spi12_cs: qup-spi12-cs-state { 4639 pins = "gpio51"; 4640 function = "qup14"; 4641 }; 4642 4643 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4644 pins = "gpio51"; 4645 function = "gpio"; 4646 }; 4647 4648 qup_spi13_data_clk: qup-spi13-data-clk-state { 4649 pins = "gpio52", "gpio53", "gpio54"; 4650 function = "qup15"; 4651 }; 4652 4653 qup_spi13_cs: qup-spi13-cs-state { 4654 pins = "gpio55"; 4655 function = "qup15"; 4656 }; 4657 4658 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4659 pins = "gpio55"; 4660 function = "gpio"; 4661 }; 4662 4663 qup_spi14_data_clk: qup-spi14-data-clk-state { 4664 pins = "gpio56", "gpio57", "gpio58"; 4665 function = "qup16"; 4666 }; 4667 4668 qup_spi14_cs: qup-spi14-cs-state { 4669 pins = "gpio59"; 4670 function = "qup16"; 4671 }; 4672 4673 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4674 pins = "gpio59"; 4675 function = "gpio"; 4676 }; 4677 4678 qup_spi15_data_clk: qup-spi15-data-clk-state { 4679 pins = "gpio60", "gpio61", "gpio62"; 4680 function = "qup17"; 4681 }; 4682 4683 qup_spi15_cs: qup-spi15-cs-state { 4684 pins = "gpio63"; 4685 function = "qup17"; 4686 }; 4687 4688 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4689 pins = "gpio63"; 4690 function = "gpio"; 4691 }; 4692 4693 qup_uart0_cts: qup-uart0-cts-state { 4694 pins = "gpio0"; 4695 function = "qup00"; 4696 }; 4697 4698 qup_uart0_rts: qup-uart0-rts-state { 4699 pins = "gpio1"; 4700 function = "qup00"; 4701 }; 4702 4703 qup_uart0_tx: qup-uart0-tx-state { 4704 pins = "gpio2"; 4705 function = "qup00"; 4706 }; 4707 4708 qup_uart0_rx: qup-uart0-rx-state { 4709 pins = "gpio3"; 4710 function = "qup00"; 4711 }; 4712 4713 qup_uart1_cts: qup-uart1-cts-state { 4714 pins = "gpio4"; 4715 function = "qup01"; 4716 }; 4717 4718 qup_uart1_rts: qup-uart1-rts-state { 4719 pins = "gpio5"; 4720 function = "qup01"; 4721 }; 4722 4723 qup_uart1_tx: qup-uart1-tx-state { 4724 pins = "gpio6"; 4725 function = "qup01"; 4726 }; 4727 4728 qup_uart1_rx: qup-uart1-rx-state { 4729 pins = "gpio7"; 4730 function = "qup01"; 4731 }; 4732 4733 qup_uart2_cts: qup-uart2-cts-state { 4734 pins = "gpio8"; 4735 function = "qup02"; 4736 }; 4737 4738 qup_uart2_rts: qup-uart2-rts-state { 4739 pins = "gpio9"; 4740 function = "qup02"; 4741 }; 4742 4743 qup_uart2_tx: qup-uart2-tx-state { 4744 pins = "gpio10"; 4745 function = "qup02"; 4746 }; 4747 4748 qup_uart2_rx: qup-uart2-rx-state { 4749 pins = "gpio11"; 4750 function = "qup02"; 4751 }; 4752 4753 qup_uart3_cts: qup-uart3-cts-state { 4754 pins = "gpio12"; 4755 function = "qup03"; 4756 }; 4757 4758 qup_uart3_rts: qup-uart3-rts-state { 4759 pins = "gpio13"; 4760 function = "qup03"; 4761 }; 4762 4763 qup_uart3_tx: qup-uart3-tx-state { 4764 pins = "gpio14"; 4765 function = "qup03"; 4766 }; 4767 4768 qup_uart3_rx: qup-uart3-rx-state { 4769 pins = "gpio15"; 4770 function = "qup03"; 4771 }; 4772 4773 qup_uart4_cts: qup-uart4-cts-state { 4774 pins = "gpio16"; 4775 function = "qup04"; 4776 }; 4777 4778 qup_uart4_rts: qup-uart4-rts-state { 4779 pins = "gpio17"; 4780 function = "qup04"; 4781 }; 4782 4783 qup_uart4_tx: qup-uart4-tx-state { 4784 pins = "gpio18"; 4785 function = "qup04"; 4786 }; 4787 4788 qup_uart4_rx: qup-uart4-rx-state { 4789 pins = "gpio19"; 4790 function = "qup04"; 4791 }; 4792 4793 qup_uart5_cts: qup-uart5-cts-state { 4794 pins = "gpio20"; 4795 function = "qup05"; 4796 }; 4797 4798 qup_uart5_rts: qup-uart5-rts-state { 4799 pins = "gpio21"; 4800 function = "qup05"; 4801 }; 4802 4803 qup_uart5_tx: qup-uart5-tx-state { 4804 pins = "gpio22"; 4805 function = "qup05"; 4806 }; 4807 4808 qup_uart5_rx: qup-uart5-rx-state { 4809 pins = "gpio23"; 4810 function = "qup05"; 4811 }; 4812 4813 qup_uart6_cts: qup-uart6-cts-state { 4814 pins = "gpio24"; 4815 function = "qup06"; 4816 }; 4817 4818 qup_uart6_rts: qup-uart6-rts-state { 4819 pins = "gpio25"; 4820 function = "qup06"; 4821 }; 4822 4823 qup_uart6_tx: qup-uart6-tx-state { 4824 pins = "gpio26"; 4825 function = "qup06"; 4826 }; 4827 4828 qup_uart6_rx: qup-uart6-rx-state { 4829 pins = "gpio27"; 4830 function = "qup06"; 4831 }; 4832 4833 qup_uart7_cts: qup-uart7-cts-state { 4834 pins = "gpio28"; 4835 function = "qup07"; 4836 }; 4837 4838 qup_uart7_rts: qup-uart7-rts-state { 4839 pins = "gpio29"; 4840 function = "qup07"; 4841 }; 4842 4843 qup_uart7_tx: qup-uart7-tx-state { 4844 pins = "gpio30"; 4845 function = "qup07"; 4846 }; 4847 4848 qup_uart7_rx: qup-uart7-rx-state { 4849 pins = "gpio31"; 4850 function = "qup07"; 4851 }; 4852 4853 qup_uart8_cts: qup-uart8-cts-state { 4854 pins = "gpio32"; 4855 function = "qup10"; 4856 }; 4857 4858 qup_uart8_rts: qup-uart8-rts-state { 4859 pins = "gpio33"; 4860 function = "qup10"; 4861 }; 4862 4863 qup_uart8_tx: qup-uart8-tx-state { 4864 pins = "gpio34"; 4865 function = "qup10"; 4866 }; 4867 4868 qup_uart8_rx: qup-uart8-rx-state { 4869 pins = "gpio35"; 4870 function = "qup10"; 4871 }; 4872 4873 qup_uart9_cts: qup-uart9-cts-state { 4874 pins = "gpio36"; 4875 function = "qup11"; 4876 }; 4877 4878 qup_uart9_rts: qup-uart9-rts-state { 4879 pins = "gpio37"; 4880 function = "qup11"; 4881 }; 4882 4883 qup_uart9_tx: qup-uart9-tx-state { 4884 pins = "gpio38"; 4885 function = "qup11"; 4886 }; 4887 4888 qup_uart9_rx: qup-uart9-rx-state { 4889 pins = "gpio39"; 4890 function = "qup11"; 4891 }; 4892 4893 qup_uart10_cts: qup-uart10-cts-state { 4894 pins = "gpio40"; 4895 function = "qup12"; 4896 }; 4897 4898 qup_uart10_rts: qup-uart10-rts-state { 4899 pins = "gpio41"; 4900 function = "qup12"; 4901 }; 4902 4903 qup_uart10_tx: qup-uart10-tx-state { 4904 pins = "gpio42"; 4905 function = "qup12"; 4906 }; 4907 4908 qup_uart10_rx: qup-uart10-rx-state { 4909 pins = "gpio43"; 4910 function = "qup12"; 4911 }; 4912 4913 qup_uart11_cts: qup-uart11-cts-state { 4914 pins = "gpio44"; 4915 function = "qup13"; 4916 }; 4917 4918 qup_uart11_rts: qup-uart11-rts-state { 4919 pins = "gpio45"; 4920 function = "qup13"; 4921 }; 4922 4923 qup_uart11_tx: qup-uart11-tx-state { 4924 pins = "gpio46"; 4925 function = "qup13"; 4926 }; 4927 4928 qup_uart11_rx: qup-uart11-rx-state { 4929 pins = "gpio47"; 4930 function = "qup13"; 4931 }; 4932 4933 qup_uart12_cts: qup-uart12-cts-state { 4934 pins = "gpio48"; 4935 function = "qup14"; 4936 }; 4937 4938 qup_uart12_rts: qup-uart12-rts-state { 4939 pins = "gpio49"; 4940 function = "qup14"; 4941 }; 4942 4943 qup_uart12_tx: qup-uart12-tx-state { 4944 pins = "gpio50"; 4945 function = "qup14"; 4946 }; 4947 4948 qup_uart12_rx: qup-uart12-rx-state { 4949 pins = "gpio51"; 4950 function = "qup14"; 4951 }; 4952 4953 qup_uart13_cts: qup-uart13-cts-state { 4954 pins = "gpio52"; 4955 function = "qup15"; 4956 }; 4957 4958 qup_uart13_rts: qup-uart13-rts-state { 4959 pins = "gpio53"; 4960 function = "qup15"; 4961 }; 4962 4963 qup_uart13_tx: qup-uart13-tx-state { 4964 pins = "gpio54"; 4965 function = "qup15"; 4966 }; 4967 4968 qup_uart13_rx: qup-uart13-rx-state { 4969 pins = "gpio55"; 4970 function = "qup15"; 4971 }; 4972 4973 qup_uart14_cts: qup-uart14-cts-state { 4974 pins = "gpio56"; 4975 function = "qup16"; 4976 }; 4977 4978 qup_uart14_rts: qup-uart14-rts-state { 4979 pins = "gpio57"; 4980 function = "qup16"; 4981 }; 4982 4983 qup_uart14_tx: qup-uart14-tx-state { 4984 pins = "gpio58"; 4985 function = "qup16"; 4986 }; 4987 4988 qup_uart14_rx: qup-uart14-rx-state { 4989 pins = "gpio59"; 4990 function = "qup16"; 4991 }; 4992 4993 qup_uart15_cts: qup-uart15-cts-state { 4994 pins = "gpio60"; 4995 function = "qup17"; 4996 }; 4997 4998 qup_uart15_rts: qup-uart15-rts-state { 4999 pins = "gpio61"; 5000 function = "qup17"; 5001 }; 5002 5003 qup_uart15_tx: qup-uart15-tx-state { 5004 pins = "gpio62"; 5005 function = "qup17"; 5006 }; 5007 5008 qup_uart15_rx: qup-uart15-rx-state { 5009 pins = "gpio63"; 5010 function = "qup17"; 5011 }; 5012 5013 sdc1_clk: sdc1-clk-state { 5014 pins = "sdc1_clk"; 5015 }; 5016 5017 sdc1_cmd: sdc1-cmd-state { 5018 pins = "sdc1_cmd"; 5019 }; 5020 5021 sdc1_data: sdc1-data-state { 5022 pins = "sdc1_data"; 5023 }; 5024 5025 sdc1_rclk: sdc1-rclk-state { 5026 pins = "sdc1_rclk"; 5027 }; 5028 5029 sdc1_clk_sleep: sdc1-clk-sleep-state { 5030 pins = "sdc1_clk"; 5031 drive-strength = <2>; 5032 bias-bus-hold; 5033 }; 5034 5035 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5036 pins = "sdc1_cmd"; 5037 drive-strength = <2>; 5038 bias-bus-hold; 5039 }; 5040 5041 sdc1_data_sleep: sdc1-data-sleep-state { 5042 pins = "sdc1_data"; 5043 drive-strength = <2>; 5044 bias-bus-hold; 5045 }; 5046 5047 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5048 pins = "sdc1_rclk"; 5049 drive-strength = <2>; 5050 bias-bus-hold; 5051 }; 5052 5053 sdc2_clk: sdc2-clk-state { 5054 pins = "sdc2_clk"; 5055 }; 5056 5057 sdc2_cmd: sdc2-cmd-state { 5058 pins = "sdc2_cmd"; 5059 }; 5060 5061 sdc2_data: sdc2-data-state { 5062 pins = "sdc2_data"; 5063 }; 5064 5065 sdc2_clk_sleep: sdc2-clk-sleep-state { 5066 pins = "sdc2_clk"; 5067 drive-strength = <2>; 5068 bias-bus-hold; 5069 }; 5070 5071 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5072 pins = "sdc2_cmd"; 5073 drive-strength = <2>; 5074 bias-bus-hold; 5075 }; 5076 5077 sdc2_data_sleep: sdc2-data-sleep-state { 5078 pins = "sdc2_data"; 5079 drive-strength = <2>; 5080 bias-bus-hold; 5081 }; 5082 }; 5083 5084 sram@146a5000 { 5085 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5086 reg = <0 0x146a5000 0 0x6000>; 5087 5088 #address-cells = <1>; 5089 #size-cells = <1>; 5090 5091 ranges = <0 0 0x146a5000 0x6000>; 5092 5093 pil-reloc@594c { 5094 compatible = "qcom,pil-reloc-info"; 5095 reg = <0x594c 0xc8>; 5096 }; 5097 }; 5098 5099 apps_smmu: iommu@15000000 { 5100 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5101 reg = <0 0x15000000 0 0x100000>; 5102 #iommu-cells = <2>; 5103 #global-interrupts = <1>; 5104 dma-coherent; 5105 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5186 }; 5187 5188 intc: interrupt-controller@17a00000 { 5189 compatible = "arm,gic-v3"; 5190 #address-cells = <2>; 5191 #size-cells = <2>; 5192 ranges; 5193 #interrupt-cells = <3>; 5194 interrupt-controller; 5195 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5196 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5197 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5198 5199 gic-its@17a40000 { 5200 compatible = "arm,gic-v3-its"; 5201 msi-controller; 5202 #msi-cells = <1>; 5203 reg = <0 0x17a40000 0 0x20000>; 5204 status = "disabled"; 5205 }; 5206 }; 5207 5208 watchdog@17c10000 { 5209 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5210 reg = <0 0x17c10000 0 0x1000>; 5211 clocks = <&sleep_clk>; 5212 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5213 }; 5214 5215 timer@17c20000 { 5216 #address-cells = <1>; 5217 #size-cells = <1>; 5218 ranges = <0 0 0 0x20000000>; 5219 compatible = "arm,armv7-timer-mem"; 5220 reg = <0 0x17c20000 0 0x1000>; 5221 5222 frame@17c21000 { 5223 frame-number = <0>; 5224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5225 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5226 reg = <0x17c21000 0x1000>, 5227 <0x17c22000 0x1000>; 5228 }; 5229 5230 frame@17c23000 { 5231 frame-number = <1>; 5232 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5233 reg = <0x17c23000 0x1000>; 5234 status = "disabled"; 5235 }; 5236 5237 frame@17c25000 { 5238 frame-number = <2>; 5239 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5240 reg = <0x17c25000 0x1000>; 5241 status = "disabled"; 5242 }; 5243 5244 frame@17c27000 { 5245 frame-number = <3>; 5246 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5247 reg = <0x17c27000 0x1000>; 5248 status = "disabled"; 5249 }; 5250 5251 frame@17c29000 { 5252 frame-number = <4>; 5253 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5254 reg = <0x17c29000 0x1000>; 5255 status = "disabled"; 5256 }; 5257 5258 frame@17c2b000 { 5259 frame-number = <5>; 5260 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5261 reg = <0x17c2b000 0x1000>; 5262 status = "disabled"; 5263 }; 5264 5265 frame@17c2d000 { 5266 frame-number = <6>; 5267 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5268 reg = <0x17c2d000 0x1000>; 5269 status = "disabled"; 5270 }; 5271 }; 5272 5273 apps_rsc: rsc@18200000 { 5274 compatible = "qcom,rpmh-rsc"; 5275 reg = <0 0x18200000 0 0x10000>, 5276 <0 0x18210000 0 0x10000>, 5277 <0 0x18220000 0 0x10000>; 5278 reg-names = "drv-0", "drv-1", "drv-2"; 5279 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5280 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5281 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5282 qcom,tcs-offset = <0xd00>; 5283 qcom,drv-id = <2>; 5284 qcom,tcs-config = <ACTIVE_TCS 2>, 5285 <SLEEP_TCS 3>, 5286 <WAKE_TCS 3>, 5287 <CONTROL_TCS 1>; 5288 5289 apps_bcm_voter: bcm-voter { 5290 compatible = "qcom,bcm-voter"; 5291 }; 5292 5293 rpmhpd: power-controller { 5294 compatible = "qcom,sc7280-rpmhpd"; 5295 #power-domain-cells = <1>; 5296 operating-points-v2 = <&rpmhpd_opp_table>; 5297 5298 rpmhpd_opp_table: opp-table { 5299 compatible = "operating-points-v2"; 5300 5301 rpmhpd_opp_ret: opp1 { 5302 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5303 }; 5304 5305 rpmhpd_opp_low_svs: opp2 { 5306 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5307 }; 5308 5309 rpmhpd_opp_svs: opp3 { 5310 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5311 }; 5312 5313 rpmhpd_opp_svs_l1: opp4 { 5314 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5315 }; 5316 5317 rpmhpd_opp_svs_l2: opp5 { 5318 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5319 }; 5320 5321 rpmhpd_opp_nom: opp6 { 5322 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5323 }; 5324 5325 rpmhpd_opp_nom_l1: opp7 { 5326 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5327 }; 5328 5329 rpmhpd_opp_turbo: opp8 { 5330 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5331 }; 5332 5333 rpmhpd_opp_turbo_l1: opp9 { 5334 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5335 }; 5336 }; 5337 }; 5338 5339 rpmhcc: clock-controller { 5340 compatible = "qcom,sc7280-rpmh-clk"; 5341 clocks = <&xo_board>; 5342 clock-names = "xo"; 5343 #clock-cells = <1>; 5344 }; 5345 }; 5346 5347 epss_l3: interconnect@18590000 { 5348 compatible = "qcom,sc7280-epss-l3"; 5349 reg = <0 0x18590000 0 0x1000>; 5350 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5351 clock-names = "xo", "alternate"; 5352 #interconnect-cells = <1>; 5353 }; 5354 5355 cpufreq_hw: cpufreq@18591000 { 5356 compatible = "qcom,cpufreq-epss"; 5357 reg = <0 0x18591000 0 0x1000>, 5358 <0 0x18592000 0 0x1000>, 5359 <0 0x18593000 0 0x1000>; 5360 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5361 clock-names = "xo", "alternate"; 5362 #freq-domain-cells = <1>; 5363 }; 5364 }; 5365 5366 thermal_zones: thermal-zones { 5367 cpu0-thermal { 5368 polling-delay-passive = <250>; 5369 polling-delay = <0>; 5370 5371 thermal-sensors = <&tsens0 1>; 5372 5373 trips { 5374 cpu0_alert0: trip-point0 { 5375 temperature = <90000>; 5376 hysteresis = <2000>; 5377 type = "passive"; 5378 }; 5379 5380 cpu0_alert1: trip-point1 { 5381 temperature = <95000>; 5382 hysteresis = <2000>; 5383 type = "passive"; 5384 }; 5385 5386 cpu0_crit: cpu-crit { 5387 temperature = <110000>; 5388 hysteresis = <0>; 5389 type = "critical"; 5390 }; 5391 }; 5392 5393 cooling-maps { 5394 map0 { 5395 trip = <&cpu0_alert0>; 5396 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5397 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5398 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5399 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5400 }; 5401 map1 { 5402 trip = <&cpu0_alert1>; 5403 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5407 }; 5408 }; 5409 }; 5410 5411 cpu1-thermal { 5412 polling-delay-passive = <250>; 5413 polling-delay = <0>; 5414 5415 thermal-sensors = <&tsens0 2>; 5416 5417 trips { 5418 cpu1_alert0: trip-point0 { 5419 temperature = <90000>; 5420 hysteresis = <2000>; 5421 type = "passive"; 5422 }; 5423 5424 cpu1_alert1: trip-point1 { 5425 temperature = <95000>; 5426 hysteresis = <2000>; 5427 type = "passive"; 5428 }; 5429 5430 cpu1_crit: cpu-crit { 5431 temperature = <110000>; 5432 hysteresis = <0>; 5433 type = "critical"; 5434 }; 5435 }; 5436 5437 cooling-maps { 5438 map0 { 5439 trip = <&cpu1_alert0>; 5440 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5441 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5442 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5443 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5444 }; 5445 map1 { 5446 trip = <&cpu1_alert1>; 5447 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5451 }; 5452 }; 5453 }; 5454 5455 cpu2-thermal { 5456 polling-delay-passive = <250>; 5457 polling-delay = <0>; 5458 5459 thermal-sensors = <&tsens0 3>; 5460 5461 trips { 5462 cpu2_alert0: trip-point0 { 5463 temperature = <90000>; 5464 hysteresis = <2000>; 5465 type = "passive"; 5466 }; 5467 5468 cpu2_alert1: trip-point1 { 5469 temperature = <95000>; 5470 hysteresis = <2000>; 5471 type = "passive"; 5472 }; 5473 5474 cpu2_crit: cpu-crit { 5475 temperature = <110000>; 5476 hysteresis = <0>; 5477 type = "critical"; 5478 }; 5479 }; 5480 5481 cooling-maps { 5482 map0 { 5483 trip = <&cpu2_alert0>; 5484 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5485 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5486 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5487 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5488 }; 5489 map1 { 5490 trip = <&cpu2_alert1>; 5491 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5495 }; 5496 }; 5497 }; 5498 5499 cpu3-thermal { 5500 polling-delay-passive = <250>; 5501 polling-delay = <0>; 5502 5503 thermal-sensors = <&tsens0 4>; 5504 5505 trips { 5506 cpu3_alert0: trip-point0 { 5507 temperature = <90000>; 5508 hysteresis = <2000>; 5509 type = "passive"; 5510 }; 5511 5512 cpu3_alert1: trip-point1 { 5513 temperature = <95000>; 5514 hysteresis = <2000>; 5515 type = "passive"; 5516 }; 5517 5518 cpu3_crit: cpu-crit { 5519 temperature = <110000>; 5520 hysteresis = <0>; 5521 type = "critical"; 5522 }; 5523 }; 5524 5525 cooling-maps { 5526 map0 { 5527 trip = <&cpu3_alert0>; 5528 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5529 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5530 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5531 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5532 }; 5533 map1 { 5534 trip = <&cpu3_alert1>; 5535 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5539 }; 5540 }; 5541 }; 5542 5543 cpu4-thermal { 5544 polling-delay-passive = <250>; 5545 polling-delay = <0>; 5546 5547 thermal-sensors = <&tsens0 7>; 5548 5549 trips { 5550 cpu4_alert0: trip-point0 { 5551 temperature = <90000>; 5552 hysteresis = <2000>; 5553 type = "passive"; 5554 }; 5555 5556 cpu4_alert1: trip-point1 { 5557 temperature = <95000>; 5558 hysteresis = <2000>; 5559 type = "passive"; 5560 }; 5561 5562 cpu4_crit: cpu-crit { 5563 temperature = <110000>; 5564 hysteresis = <0>; 5565 type = "critical"; 5566 }; 5567 }; 5568 5569 cooling-maps { 5570 map0 { 5571 trip = <&cpu4_alert0>; 5572 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5573 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5574 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5575 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5576 }; 5577 map1 { 5578 trip = <&cpu4_alert1>; 5579 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5583 }; 5584 }; 5585 }; 5586 5587 cpu5-thermal { 5588 polling-delay-passive = <250>; 5589 polling-delay = <0>; 5590 5591 thermal-sensors = <&tsens0 8>; 5592 5593 trips { 5594 cpu5_alert0: trip-point0 { 5595 temperature = <90000>; 5596 hysteresis = <2000>; 5597 type = "passive"; 5598 }; 5599 5600 cpu5_alert1: trip-point1 { 5601 temperature = <95000>; 5602 hysteresis = <2000>; 5603 type = "passive"; 5604 }; 5605 5606 cpu5_crit: cpu-crit { 5607 temperature = <110000>; 5608 hysteresis = <0>; 5609 type = "critical"; 5610 }; 5611 }; 5612 5613 cooling-maps { 5614 map0 { 5615 trip = <&cpu5_alert0>; 5616 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5617 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5618 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5619 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5620 }; 5621 map1 { 5622 trip = <&cpu5_alert1>; 5623 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5627 }; 5628 }; 5629 }; 5630 5631 cpu6-thermal { 5632 polling-delay-passive = <250>; 5633 polling-delay = <0>; 5634 5635 thermal-sensors = <&tsens0 9>; 5636 5637 trips { 5638 cpu6_alert0: trip-point0 { 5639 temperature = <90000>; 5640 hysteresis = <2000>; 5641 type = "passive"; 5642 }; 5643 5644 cpu6_alert1: trip-point1 { 5645 temperature = <95000>; 5646 hysteresis = <2000>; 5647 type = "passive"; 5648 }; 5649 5650 cpu6_crit: cpu-crit { 5651 temperature = <110000>; 5652 hysteresis = <0>; 5653 type = "critical"; 5654 }; 5655 }; 5656 5657 cooling-maps { 5658 map0 { 5659 trip = <&cpu6_alert0>; 5660 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5661 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5662 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5663 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5664 }; 5665 map1 { 5666 trip = <&cpu6_alert1>; 5667 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5671 }; 5672 }; 5673 }; 5674 5675 cpu7-thermal { 5676 polling-delay-passive = <250>; 5677 polling-delay = <0>; 5678 5679 thermal-sensors = <&tsens0 10>; 5680 5681 trips { 5682 cpu7_alert0: trip-point0 { 5683 temperature = <90000>; 5684 hysteresis = <2000>; 5685 type = "passive"; 5686 }; 5687 5688 cpu7_alert1: trip-point1 { 5689 temperature = <95000>; 5690 hysteresis = <2000>; 5691 type = "passive"; 5692 }; 5693 5694 cpu7_crit: cpu-crit { 5695 temperature = <110000>; 5696 hysteresis = <0>; 5697 type = "critical"; 5698 }; 5699 }; 5700 5701 cooling-maps { 5702 map0 { 5703 trip = <&cpu7_alert0>; 5704 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5705 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5706 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5707 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5708 }; 5709 map1 { 5710 trip = <&cpu7_alert1>; 5711 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5715 }; 5716 }; 5717 }; 5718 5719 cpu8-thermal { 5720 polling-delay-passive = <250>; 5721 polling-delay = <0>; 5722 5723 thermal-sensors = <&tsens0 11>; 5724 5725 trips { 5726 cpu8_alert0: trip-point0 { 5727 temperature = <90000>; 5728 hysteresis = <2000>; 5729 type = "passive"; 5730 }; 5731 5732 cpu8_alert1: trip-point1 { 5733 temperature = <95000>; 5734 hysteresis = <2000>; 5735 type = "passive"; 5736 }; 5737 5738 cpu8_crit: cpu-crit { 5739 temperature = <110000>; 5740 hysteresis = <0>; 5741 type = "critical"; 5742 }; 5743 }; 5744 5745 cooling-maps { 5746 map0 { 5747 trip = <&cpu8_alert0>; 5748 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5749 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5750 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5751 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5752 }; 5753 map1 { 5754 trip = <&cpu8_alert1>; 5755 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5759 }; 5760 }; 5761 }; 5762 5763 cpu9-thermal { 5764 polling-delay-passive = <250>; 5765 polling-delay = <0>; 5766 5767 thermal-sensors = <&tsens0 12>; 5768 5769 trips { 5770 cpu9_alert0: trip-point0 { 5771 temperature = <90000>; 5772 hysteresis = <2000>; 5773 type = "passive"; 5774 }; 5775 5776 cpu9_alert1: trip-point1 { 5777 temperature = <95000>; 5778 hysteresis = <2000>; 5779 type = "passive"; 5780 }; 5781 5782 cpu9_crit: cpu-crit { 5783 temperature = <110000>; 5784 hysteresis = <0>; 5785 type = "critical"; 5786 }; 5787 }; 5788 5789 cooling-maps { 5790 map0 { 5791 trip = <&cpu9_alert0>; 5792 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5793 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5794 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5795 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5796 }; 5797 map1 { 5798 trip = <&cpu9_alert1>; 5799 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5803 }; 5804 }; 5805 }; 5806 5807 cpu10-thermal { 5808 polling-delay-passive = <250>; 5809 polling-delay = <0>; 5810 5811 thermal-sensors = <&tsens0 13>; 5812 5813 trips { 5814 cpu10_alert0: trip-point0 { 5815 temperature = <90000>; 5816 hysteresis = <2000>; 5817 type = "passive"; 5818 }; 5819 5820 cpu10_alert1: trip-point1 { 5821 temperature = <95000>; 5822 hysteresis = <2000>; 5823 type = "passive"; 5824 }; 5825 5826 cpu10_crit: cpu-crit { 5827 temperature = <110000>; 5828 hysteresis = <0>; 5829 type = "critical"; 5830 }; 5831 }; 5832 5833 cooling-maps { 5834 map0 { 5835 trip = <&cpu10_alert0>; 5836 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5837 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5838 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5839 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5840 }; 5841 map1 { 5842 trip = <&cpu10_alert1>; 5843 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5847 }; 5848 }; 5849 }; 5850 5851 cpu11-thermal { 5852 polling-delay-passive = <250>; 5853 polling-delay = <0>; 5854 5855 thermal-sensors = <&tsens0 14>; 5856 5857 trips { 5858 cpu11_alert0: trip-point0 { 5859 temperature = <90000>; 5860 hysteresis = <2000>; 5861 type = "passive"; 5862 }; 5863 5864 cpu11_alert1: trip-point1 { 5865 temperature = <95000>; 5866 hysteresis = <2000>; 5867 type = "passive"; 5868 }; 5869 5870 cpu11_crit: cpu-crit { 5871 temperature = <110000>; 5872 hysteresis = <0>; 5873 type = "critical"; 5874 }; 5875 }; 5876 5877 cooling-maps { 5878 map0 { 5879 trip = <&cpu11_alert0>; 5880 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5881 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5882 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5883 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5884 }; 5885 map1 { 5886 trip = <&cpu11_alert1>; 5887 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5891 }; 5892 }; 5893 }; 5894 5895 aoss0-thermal { 5896 polling-delay-passive = <0>; 5897 polling-delay = <0>; 5898 5899 thermal-sensors = <&tsens0 0>; 5900 5901 trips { 5902 aoss0_alert0: trip-point0 { 5903 temperature = <90000>; 5904 hysteresis = <2000>; 5905 type = "hot"; 5906 }; 5907 5908 aoss0_crit: aoss0-crit { 5909 temperature = <110000>; 5910 hysteresis = <0>; 5911 type = "critical"; 5912 }; 5913 }; 5914 }; 5915 5916 aoss1-thermal { 5917 polling-delay-passive = <0>; 5918 polling-delay = <0>; 5919 5920 thermal-sensors = <&tsens1 0>; 5921 5922 trips { 5923 aoss1_alert0: trip-point0 { 5924 temperature = <90000>; 5925 hysteresis = <2000>; 5926 type = "hot"; 5927 }; 5928 5929 aoss1_crit: aoss1-crit { 5930 temperature = <110000>; 5931 hysteresis = <0>; 5932 type = "critical"; 5933 }; 5934 }; 5935 }; 5936 5937 cpuss0-thermal { 5938 polling-delay-passive = <0>; 5939 polling-delay = <0>; 5940 5941 thermal-sensors = <&tsens0 5>; 5942 5943 trips { 5944 cpuss0_alert0: trip-point0 { 5945 temperature = <90000>; 5946 hysteresis = <2000>; 5947 type = "hot"; 5948 }; 5949 cpuss0_crit: cluster0-crit { 5950 temperature = <110000>; 5951 hysteresis = <0>; 5952 type = "critical"; 5953 }; 5954 }; 5955 }; 5956 5957 cpuss1-thermal { 5958 polling-delay-passive = <0>; 5959 polling-delay = <0>; 5960 5961 thermal-sensors = <&tsens0 6>; 5962 5963 trips { 5964 cpuss1_alert0: trip-point0 { 5965 temperature = <90000>; 5966 hysteresis = <2000>; 5967 type = "hot"; 5968 }; 5969 cpuss1_crit: cluster0-crit { 5970 temperature = <110000>; 5971 hysteresis = <0>; 5972 type = "critical"; 5973 }; 5974 }; 5975 }; 5976 5977 gpuss0-thermal { 5978 polling-delay-passive = <100>; 5979 polling-delay = <0>; 5980 5981 thermal-sensors = <&tsens1 1>; 5982 5983 trips { 5984 gpuss0_alert0: trip-point0 { 5985 temperature = <95000>; 5986 hysteresis = <2000>; 5987 type = "passive"; 5988 }; 5989 5990 gpuss0_crit: gpuss0-crit { 5991 temperature = <110000>; 5992 hysteresis = <0>; 5993 type = "critical"; 5994 }; 5995 }; 5996 5997 cooling-maps { 5998 map0 { 5999 trip = <&gpuss0_alert0>; 6000 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6001 }; 6002 }; 6003 }; 6004 6005 gpuss1-thermal { 6006 polling-delay-passive = <100>; 6007 polling-delay = <0>; 6008 6009 thermal-sensors = <&tsens1 2>; 6010 6011 trips { 6012 gpuss1_alert0: trip-point0 { 6013 temperature = <95000>; 6014 hysteresis = <2000>; 6015 type = "passive"; 6016 }; 6017 6018 gpuss1_crit: gpuss1-crit { 6019 temperature = <110000>; 6020 hysteresis = <0>; 6021 type = "critical"; 6022 }; 6023 }; 6024 6025 cooling-maps { 6026 map0 { 6027 trip = <&gpuss1_alert0>; 6028 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6029 }; 6030 }; 6031 }; 6032 6033 nspss0-thermal { 6034 polling-delay-passive = <0>; 6035 polling-delay = <0>; 6036 6037 thermal-sensors = <&tsens1 3>; 6038 6039 trips { 6040 nspss0_alert0: trip-point0 { 6041 temperature = <90000>; 6042 hysteresis = <2000>; 6043 type = "hot"; 6044 }; 6045 6046 nspss0_crit: nspss0-crit { 6047 temperature = <110000>; 6048 hysteresis = <0>; 6049 type = "critical"; 6050 }; 6051 }; 6052 }; 6053 6054 nspss1-thermal { 6055 polling-delay-passive = <0>; 6056 polling-delay = <0>; 6057 6058 thermal-sensors = <&tsens1 4>; 6059 6060 trips { 6061 nspss1_alert0: trip-point0 { 6062 temperature = <90000>; 6063 hysteresis = <2000>; 6064 type = "hot"; 6065 }; 6066 6067 nspss1_crit: nspss1-crit { 6068 temperature = <110000>; 6069 hysteresis = <0>; 6070 type = "critical"; 6071 }; 6072 }; 6073 }; 6074 6075 video-thermal { 6076 polling-delay-passive = <0>; 6077 polling-delay = <0>; 6078 6079 thermal-sensors = <&tsens1 5>; 6080 6081 trips { 6082 video_alert0: trip-point0 { 6083 temperature = <90000>; 6084 hysteresis = <2000>; 6085 type = "hot"; 6086 }; 6087 6088 video_crit: video-crit { 6089 temperature = <110000>; 6090 hysteresis = <0>; 6091 type = "critical"; 6092 }; 6093 }; 6094 }; 6095 6096 ddr-thermal { 6097 polling-delay-passive = <0>; 6098 polling-delay = <0>; 6099 6100 thermal-sensors = <&tsens1 6>; 6101 6102 trips { 6103 ddr_alert0: trip-point0 { 6104 temperature = <90000>; 6105 hysteresis = <2000>; 6106 type = "hot"; 6107 }; 6108 6109 ddr_crit: ddr-crit { 6110 temperature = <110000>; 6111 hysteresis = <0>; 6112 type = "critical"; 6113 }; 6114 }; 6115 }; 6116 6117 mdmss0-thermal { 6118 polling-delay-passive = <0>; 6119 polling-delay = <0>; 6120 6121 thermal-sensors = <&tsens1 7>; 6122 6123 trips { 6124 mdmss0_alert0: trip-point0 { 6125 temperature = <90000>; 6126 hysteresis = <2000>; 6127 type = "hot"; 6128 }; 6129 6130 mdmss0_crit: mdmss0-crit { 6131 temperature = <110000>; 6132 hysteresis = <0>; 6133 type = "critical"; 6134 }; 6135 }; 6136 }; 6137 6138 mdmss1-thermal { 6139 polling-delay-passive = <0>; 6140 polling-delay = <0>; 6141 6142 thermal-sensors = <&tsens1 8>; 6143 6144 trips { 6145 mdmss1_alert0: trip-point0 { 6146 temperature = <90000>; 6147 hysteresis = <2000>; 6148 type = "hot"; 6149 }; 6150 6151 mdmss1_crit: mdmss1-crit { 6152 temperature = <110000>; 6153 hysteresis = <0>; 6154 type = "critical"; 6155 }; 6156 }; 6157 }; 6158 6159 mdmss2-thermal { 6160 polling-delay-passive = <0>; 6161 polling-delay = <0>; 6162 6163 thermal-sensors = <&tsens1 9>; 6164 6165 trips { 6166 mdmss2_alert0: trip-point0 { 6167 temperature = <90000>; 6168 hysteresis = <2000>; 6169 type = "hot"; 6170 }; 6171 6172 mdmss2_crit: mdmss2-crit { 6173 temperature = <110000>; 6174 hysteresis = <0>; 6175 type = "critical"; 6176 }; 6177 }; 6178 }; 6179 6180 mdmss3-thermal { 6181 polling-delay-passive = <0>; 6182 polling-delay = <0>; 6183 6184 thermal-sensors = <&tsens1 10>; 6185 6186 trips { 6187 mdmss3_alert0: trip-point0 { 6188 temperature = <90000>; 6189 hysteresis = <2000>; 6190 type = "hot"; 6191 }; 6192 6193 mdmss3_crit: mdmss3-crit { 6194 temperature = <110000>; 6195 hysteresis = <0>; 6196 type = "critical"; 6197 }; 6198 }; 6199 }; 6200 6201 camera0-thermal { 6202 polling-delay-passive = <0>; 6203 polling-delay = <0>; 6204 6205 thermal-sensors = <&tsens1 11>; 6206 6207 trips { 6208 camera0_alert0: trip-point0 { 6209 temperature = <90000>; 6210 hysteresis = <2000>; 6211 type = "hot"; 6212 }; 6213 6214 camera0_crit: camera0-crit { 6215 temperature = <110000>; 6216 hysteresis = <0>; 6217 type = "critical"; 6218 }; 6219 }; 6220 }; 6221 }; 6222 6223 timer { 6224 compatible = "arm,armv8-timer"; 6225 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6226 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6227 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6228 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6229 }; 6230}; 6231