1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7280.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 mmc1 = &sdhc_1; 50 mmc2 = &sdhc_2; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi2 = &spi2; 54 spi3 = &spi3; 55 spi4 = &spi4; 56 spi5 = &spi5; 57 spi6 = &spi6; 58 spi7 = &spi7; 59 spi8 = &spi8; 60 spi9 = &spi9; 61 spi10 = &spi10; 62 spi11 = &spi11; 63 spi12 = &spi12; 64 spi13 = &spi13; 65 spi14 = &spi14; 66 spi15 = &spi15; 67 }; 68 69 clocks { 70 xo_board: xo-board { 71 compatible = "fixed-clock"; 72 clock-frequency = <76800000>; 73 #clock-cells = <0>; 74 }; 75 76 sleep_clk: sleep-clk { 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 #clock-cells = <0>; 80 }; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 wlan_ce_mem: memory@4cd000 { 89 no-map; 90 reg = <0x0 0x004cd000 0x0 0x1000>; 91 }; 92 93 hyp_mem: memory@80000000 { 94 reg = <0x0 0x80000000 0x0 0x600000>; 95 no-map; 96 }; 97 98 xbl_mem: memory@80600000 { 99 reg = <0x0 0x80600000 0x0 0x200000>; 100 no-map; 101 }; 102 103 aop_mem: memory@80800000 { 104 reg = <0x0 0x80800000 0x0 0x60000>; 105 no-map; 106 }; 107 108 aop_cmd_db_mem: memory@80860000 { 109 reg = <0x0 0x80860000 0x0 0x20000>; 110 compatible = "qcom,cmd-db"; 111 no-map; 112 }; 113 114 reserved_xbl_uefi_log: memory@80880000 { 115 reg = <0x0 0x80884000 0x0 0x10000>; 116 no-map; 117 }; 118 119 sec_apps_mem: memory@808ff000 { 120 reg = <0x0 0x808ff000 0x0 0x1000>; 121 no-map; 122 }; 123 124 smem_mem: memory@80900000 { 125 reg = <0x0 0x80900000 0x0 0x200000>; 126 no-map; 127 }; 128 129 cpucp_mem: memory@80b00000 { 130 no-map; 131 reg = <0x0 0x80b00000 0x0 0x100000>; 132 }; 133 134 wlan_fw_mem: memory@80c00000 { 135 reg = <0x0 0x80c00000 0x0 0xc00000>; 136 no-map; 137 }; 138 139 video_mem: memory@8b200000 { 140 reg = <0x0 0x8b200000 0x0 0x500000>; 141 no-map; 142 }; 143 144 ipa_fw_mem: memory@8b700000 { 145 reg = <0 0x8b700000 0 0x10000>; 146 no-map; 147 }; 148 149 rmtfs_mem: memory@9c900000 { 150 compatible = "qcom,rmtfs-mem"; 151 reg = <0x0 0x9c900000 0x0 0x280000>; 152 no-map; 153 154 qcom,client-id = <1>; 155 qcom,vmid = <15>; 156 }; 157 }; 158 159 cpus { 160 #address-cells = <2>; 161 #size-cells = <0>; 162 163 CPU0: cpu@0 { 164 device_type = "cpu"; 165 compatible = "arm,kryo"; 166 reg = <0x0 0x0>; 167 enable-method = "psci"; 168 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 169 &LITTLE_CPU_SLEEP_1 170 &CLUSTER_SLEEP_0>; 171 next-level-cache = <&L2_0>; 172 operating-points-v2 = <&cpu0_opp_table>; 173 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 174 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 175 qcom,freq-domain = <&cpufreq_hw 0>; 176 #cooling-cells = <2>; 177 L2_0: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 L3_0: l3-cache { 181 compatible = "cache"; 182 }; 183 }; 184 }; 185 186 CPU1: cpu@100 { 187 device_type = "cpu"; 188 compatible = "arm,kryo"; 189 reg = <0x0 0x100>; 190 enable-method = "psci"; 191 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 192 &LITTLE_CPU_SLEEP_1 193 &CLUSTER_SLEEP_0>; 194 next-level-cache = <&L2_100>; 195 operating-points-v2 = <&cpu0_opp_table>; 196 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 197 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 198 qcom,freq-domain = <&cpufreq_hw 0>; 199 #cooling-cells = <2>; 200 L2_100: l2-cache { 201 compatible = "cache"; 202 next-level-cache = <&L3_0>; 203 }; 204 }; 205 206 CPU2: cpu@200 { 207 device_type = "cpu"; 208 compatible = "arm,kryo"; 209 reg = <0x0 0x200>; 210 enable-method = "psci"; 211 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 212 &LITTLE_CPU_SLEEP_1 213 &CLUSTER_SLEEP_0>; 214 next-level-cache = <&L2_200>; 215 operating-points-v2 = <&cpu0_opp_table>; 216 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 217 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 qcom,freq-domain = <&cpufreq_hw 0>; 219 #cooling-cells = <2>; 220 L2_200: l2-cache { 221 compatible = "cache"; 222 next-level-cache = <&L3_0>; 223 }; 224 }; 225 226 CPU3: cpu@300 { 227 device_type = "cpu"; 228 compatible = "arm,kryo"; 229 reg = <0x0 0x300>; 230 enable-method = "psci"; 231 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 232 &LITTLE_CPU_SLEEP_1 233 &CLUSTER_SLEEP_0>; 234 next-level-cache = <&L2_300>; 235 operating-points-v2 = <&cpu0_opp_table>; 236 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 237 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 238 qcom,freq-domain = <&cpufreq_hw 0>; 239 #cooling-cells = <2>; 240 L2_300: l2-cache { 241 compatible = "cache"; 242 next-level-cache = <&L3_0>; 243 }; 244 }; 245 246 CPU4: cpu@400 { 247 device_type = "cpu"; 248 compatible = "arm,kryo"; 249 reg = <0x0 0x400>; 250 enable-method = "psci"; 251 cpu-idle-states = <&BIG_CPU_SLEEP_0 252 &BIG_CPU_SLEEP_1 253 &CLUSTER_SLEEP_0>; 254 next-level-cache = <&L2_400>; 255 operating-points-v2 = <&cpu4_opp_table>; 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 257 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 258 qcom,freq-domain = <&cpufreq_hw 1>; 259 #cooling-cells = <2>; 260 L2_400: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU5: cpu@500 { 267 device_type = "cpu"; 268 compatible = "arm,kryo"; 269 reg = <0x0 0x500>; 270 enable-method = "psci"; 271 cpu-idle-states = <&BIG_CPU_SLEEP_0 272 &BIG_CPU_SLEEP_1 273 &CLUSTER_SLEEP_0>; 274 next-level-cache = <&L2_500>; 275 operating-points-v2 = <&cpu4_opp_table>; 276 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 277 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 278 qcom,freq-domain = <&cpufreq_hw 1>; 279 #cooling-cells = <2>; 280 L2_500: l2-cache { 281 compatible = "cache"; 282 next-level-cache = <&L3_0>; 283 }; 284 }; 285 286 CPU6: cpu@600 { 287 device_type = "cpu"; 288 compatible = "arm,kryo"; 289 reg = <0x0 0x600>; 290 enable-method = "psci"; 291 cpu-idle-states = <&BIG_CPU_SLEEP_0 292 &BIG_CPU_SLEEP_1 293 &CLUSTER_SLEEP_0>; 294 next-level-cache = <&L2_600>; 295 operating-points-v2 = <&cpu4_opp_table>; 296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 297 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 298 qcom,freq-domain = <&cpufreq_hw 1>; 299 #cooling-cells = <2>; 300 L2_600: l2-cache { 301 compatible = "cache"; 302 next-level-cache = <&L3_0>; 303 }; 304 }; 305 306 CPU7: cpu@700 { 307 device_type = "cpu"; 308 compatible = "arm,kryo"; 309 reg = <0x0 0x700>; 310 enable-method = "psci"; 311 cpu-idle-states = <&BIG_CPU_SLEEP_0 312 &BIG_CPU_SLEEP_1 313 &CLUSTER_SLEEP_0>; 314 next-level-cache = <&L2_700>; 315 operating-points-v2 = <&cpu7_opp_table>; 316 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 317 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 318 qcom,freq-domain = <&cpufreq_hw 2>; 319 #cooling-cells = <2>; 320 L2_700: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 cpu-map { 327 cluster0 { 328 core0 { 329 cpu = <&CPU0>; 330 }; 331 332 core1 { 333 cpu = <&CPU1>; 334 }; 335 336 core2 { 337 cpu = <&CPU2>; 338 }; 339 340 core3 { 341 cpu = <&CPU3>; 342 }; 343 344 core4 { 345 cpu = <&CPU4>; 346 }; 347 348 core5 { 349 cpu = <&CPU5>; 350 }; 351 352 core6 { 353 cpu = <&CPU6>; 354 }; 355 356 core7 { 357 cpu = <&CPU7>; 358 }; 359 }; 360 }; 361 362 idle-states { 363 entry-method = "psci"; 364 365 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "little-power-down"; 368 arm,psci-suspend-param = <0x40000003>; 369 entry-latency-us = <549>; 370 exit-latency-us = <901>; 371 min-residency-us = <1774>; 372 local-timer-stop; 373 }; 374 375 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "little-rail-power-down"; 378 arm,psci-suspend-param = <0x40000004>; 379 entry-latency-us = <702>; 380 exit-latency-us = <915>; 381 min-residency-us = <4001>; 382 local-timer-stop; 383 }; 384 385 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 386 compatible = "arm,idle-state"; 387 idle-state-name = "big-power-down"; 388 arm,psci-suspend-param = <0x40000003>; 389 entry-latency-us = <523>; 390 exit-latency-us = <1244>; 391 min-residency-us = <2207>; 392 local-timer-stop; 393 }; 394 395 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "big-rail-power-down"; 398 arm,psci-suspend-param = <0x40000004>; 399 entry-latency-us = <526>; 400 exit-latency-us = <1854>; 401 min-residency-us = <5555>; 402 local-timer-stop; 403 }; 404 405 CLUSTER_SLEEP_0: cluster-sleep-0 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "cluster-power-down"; 408 arm,psci-suspend-param = <0x40003444>; 409 entry-latency-us = <3263>; 410 exit-latency-us = <6562>; 411 min-residency-us = <9926>; 412 local-timer-stop; 413 }; 414 }; 415 }; 416 417 cpu0_opp_table: cpu0-opp-table { 418 compatible = "operating-points-v2"; 419 opp-shared; 420 421 cpu0_opp_300mhz: opp-300000000 { 422 opp-hz = /bits/ 64 <300000000>; 423 opp-peak-kBps = <800000 9600000>; 424 }; 425 426 cpu0_opp_691mhz: opp-691200000 { 427 opp-hz = /bits/ 64 <691200000>; 428 opp-peak-kBps = <800000 17817600>; 429 }; 430 431 cpu0_opp_806mhz: opp-806400000 { 432 opp-hz = /bits/ 64 <806400000>; 433 opp-peak-kBps = <800000 20889600>; 434 }; 435 436 cpu0_opp_941mhz: opp-940800000 { 437 opp-hz = /bits/ 64 <940800000>; 438 opp-peak-kBps = <1804000 24576000>; 439 }; 440 441 cpu0_opp_1152mhz: opp-1152000000 { 442 opp-hz = /bits/ 64 <1152000000>; 443 opp-peak-kBps = <2188000 27033600>; 444 }; 445 446 cpu0_opp_1325mhz: opp-1324800000 { 447 opp-hz = /bits/ 64 <1324800000>; 448 opp-peak-kBps = <2188000 33792000>; 449 }; 450 451 cpu0_opp_1517mhz: opp-1516800000 { 452 opp-hz = /bits/ 64 <1516800000>; 453 opp-peak-kBps = <3072000 38092800>; 454 }; 455 456 cpu0_opp_1651mhz: opp-1651200000 { 457 opp-hz = /bits/ 64 <1651200000>; 458 opp-peak-kBps = <3072000 41779200>; 459 }; 460 461 cpu0_opp_1805mhz: opp-1804800000 { 462 opp-hz = /bits/ 64 <1804800000>; 463 opp-peak-kBps = <4068000 48537600>; 464 }; 465 466 cpu0_opp_1958mhz: opp-1958400000 { 467 opp-hz = /bits/ 64 <1958400000>; 468 opp-peak-kBps = <4068000 48537600>; 469 }; 470 471 cpu0_opp_2016mhz: opp-2016000000 { 472 opp-hz = /bits/ 64 <2016000000>; 473 opp-peak-kBps = <6220000 48537600>; 474 }; 475 }; 476 477 cpu4_opp_table: cpu4-opp-table { 478 compatible = "operating-points-v2"; 479 opp-shared; 480 481 cpu4_opp_691mhz: opp-691200000 { 482 opp-hz = /bits/ 64 <691200000>; 483 opp-peak-kBps = <1804000 9600000>; 484 }; 485 486 cpu4_opp_941mhz: opp-940800000 { 487 opp-hz = /bits/ 64 <940800000>; 488 opp-peak-kBps = <2188000 17817600>; 489 }; 490 491 cpu4_opp_1229mhz: opp-1228800000 { 492 opp-hz = /bits/ 64 <1228800000>; 493 opp-peak-kBps = <4068000 24576000>; 494 }; 495 496 cpu4_opp_1344mhz: opp-1344000000 { 497 opp-hz = /bits/ 64 <1344000000>; 498 opp-peak-kBps = <4068000 24576000>; 499 }; 500 501 cpu4_opp_1517mhz: opp-1516800000 { 502 opp-hz = /bits/ 64 <1516800000>; 503 opp-peak-kBps = <4068000 24576000>; 504 }; 505 506 cpu4_opp_1651mhz: opp-1651200000 { 507 opp-hz = /bits/ 64 <1651200000>; 508 opp-peak-kBps = <6220000 38092800>; 509 }; 510 511 cpu4_opp_1901mhz: opp-1900800000 { 512 opp-hz = /bits/ 64 <1900800000>; 513 opp-peak-kBps = <6220000 44851200>; 514 }; 515 516 cpu4_opp_2054mhz: opp-2054400000 { 517 opp-hz = /bits/ 64 <2054400000>; 518 opp-peak-kBps = <6220000 44851200>; 519 }; 520 521 cpu4_opp_2112mhz: opp-2112000000 { 522 opp-hz = /bits/ 64 <2112000000>; 523 opp-peak-kBps = <6220000 44851200>; 524 }; 525 526 cpu4_opp_2131mhz: opp-2131200000 { 527 opp-hz = /bits/ 64 <2131200000>; 528 opp-peak-kBps = <6220000 44851200>; 529 }; 530 531 cpu4_opp_2208mhz: opp-2208000000 { 532 opp-hz = /bits/ 64 <2208000000>; 533 opp-peak-kBps = <6220000 44851200>; 534 }; 535 536 cpu4_opp_2400mhz: opp-2400000000 { 537 opp-hz = /bits/ 64 <2400000000>; 538 opp-peak-kBps = <8532000 48537600>; 539 }; 540 541 cpu4_opp_2611mhz: opp-2611200000 { 542 opp-hz = /bits/ 64 <2611200000>; 543 opp-peak-kBps = <8532000 48537600>; 544 }; 545 }; 546 547 cpu7_opp_table: cpu7-opp-table { 548 compatible = "operating-points-v2"; 549 opp-shared; 550 551 cpu7_opp_806mhz: opp-806400000 { 552 opp-hz = /bits/ 64 <806400000>; 553 opp-peak-kBps = <1804000 9600000>; 554 }; 555 556 cpu7_opp_1056mhz: opp-1056000000 { 557 opp-hz = /bits/ 64 <1056000000>; 558 opp-peak-kBps = <2188000 17817600>; 559 }; 560 561 cpu7_opp_1325mhz: opp-1324800000 { 562 opp-hz = /bits/ 64 <1324800000>; 563 opp-peak-kBps = <4068000 24576000>; 564 }; 565 566 cpu7_opp_1517mhz: opp-1516800000 { 567 opp-hz = /bits/ 64 <1516800000>; 568 opp-peak-kBps = <4068000 24576000>; 569 }; 570 571 cpu7_opp_1766mhz: opp-1766400000 { 572 opp-hz = /bits/ 64 <1766400000>; 573 opp-peak-kBps = <6220000 38092800>; 574 }; 575 576 cpu7_opp_1862mhz: opp-1862400000 { 577 opp-hz = /bits/ 64 <1862400000>; 578 opp-peak-kBps = <6220000 38092800>; 579 }; 580 581 cpu7_opp_2035mhz: opp-2035200000 { 582 opp-hz = /bits/ 64 <2035200000>; 583 opp-peak-kBps = <6220000 38092800>; 584 }; 585 586 cpu7_opp_2112mhz: opp-2112000000 { 587 opp-hz = /bits/ 64 <2112000000>; 588 opp-peak-kBps = <6220000 44851200>; 589 }; 590 591 cpu7_opp_2208mhz: opp-2208000000 { 592 opp-hz = /bits/ 64 <2208000000>; 593 opp-peak-kBps = <6220000 44851200>; 594 }; 595 596 cpu7_opp_2381mhz: opp-2380800000 { 597 opp-hz = /bits/ 64 <2380800000>; 598 opp-peak-kBps = <6832000 44851200>; 599 }; 600 601 cpu7_opp_2400mhz: opp-2400000000 { 602 opp-hz = /bits/ 64 <2400000000>; 603 opp-peak-kBps = <8532000 48537600>; 604 }; 605 606 cpu7_opp_2515mhz: opp-2515200000 { 607 opp-hz = /bits/ 64 <2515200000>; 608 opp-peak-kBps = <8532000 48537600>; 609 }; 610 611 cpu7_opp_2707mhz: opp-2707200000 { 612 opp-hz = /bits/ 64 <2707200000>; 613 opp-peak-kBps = <8532000 48537600>; 614 }; 615 616 cpu7_opp_3014mhz: opp-3014400000 { 617 opp-hz = /bits/ 64 <3014400000>; 618 opp-peak-kBps = <8532000 48537600>; 619 }; 620 }; 621 622 memory@80000000 { 623 device_type = "memory"; 624 /* We expect the bootloader to fill in the size */ 625 reg = <0 0x80000000 0 0>; 626 }; 627 628 firmware { 629 scm { 630 compatible = "qcom,scm-sc7280", "qcom,scm"; 631 }; 632 }; 633 634 clk_virt: interconnect { 635 compatible = "qcom,sc7280-clk-virt"; 636 #interconnect-cells = <2>; 637 qcom,bcm-voters = <&apps_bcm_voter>; 638 }; 639 640 smem { 641 compatible = "qcom,smem"; 642 memory-region = <&smem_mem>; 643 hwlocks = <&tcsr_mutex 3>; 644 }; 645 646 smp2p-adsp { 647 compatible = "qcom,smp2p"; 648 qcom,smem = <443>, <429>; 649 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 650 IPCC_MPROC_SIGNAL_SMP2P 651 IRQ_TYPE_EDGE_RISING>; 652 mboxes = <&ipcc IPCC_CLIENT_LPASS 653 IPCC_MPROC_SIGNAL_SMP2P>; 654 655 qcom,local-pid = <0>; 656 qcom,remote-pid = <2>; 657 658 adsp_smp2p_out: master-kernel { 659 qcom,entry-name = "master-kernel"; 660 #qcom,smem-state-cells = <1>; 661 }; 662 663 adsp_smp2p_in: slave-kernel { 664 qcom,entry-name = "slave-kernel"; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 }; 668 }; 669 670 smp2p-cdsp { 671 compatible = "qcom,smp2p"; 672 qcom,smem = <94>, <432>; 673 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 674 IPCC_MPROC_SIGNAL_SMP2P 675 IRQ_TYPE_EDGE_RISING>; 676 mboxes = <&ipcc IPCC_CLIENT_CDSP 677 IPCC_MPROC_SIGNAL_SMP2P>; 678 679 qcom,local-pid = <0>; 680 qcom,remote-pid = <5>; 681 682 cdsp_smp2p_out: master-kernel { 683 qcom,entry-name = "master-kernel"; 684 #qcom,smem-state-cells = <1>; 685 }; 686 687 cdsp_smp2p_in: slave-kernel { 688 qcom,entry-name = "slave-kernel"; 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 }; 692 }; 693 694 smp2p-mpss { 695 compatible = "qcom,smp2p"; 696 qcom,smem = <435>, <428>; 697 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 698 IPCC_MPROC_SIGNAL_SMP2P 699 IRQ_TYPE_EDGE_RISING>; 700 mboxes = <&ipcc IPCC_CLIENT_MPSS 701 IPCC_MPROC_SIGNAL_SMP2P>; 702 703 qcom,local-pid = <0>; 704 qcom,remote-pid = <1>; 705 706 modem_smp2p_out: master-kernel { 707 qcom,entry-name = "master-kernel"; 708 #qcom,smem-state-cells = <1>; 709 }; 710 711 modem_smp2p_in: slave-kernel { 712 qcom,entry-name = "slave-kernel"; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 717 ipa_smp2p_out: ipa-ap-to-modem { 718 qcom,entry-name = "ipa"; 719 #qcom,smem-state-cells = <1>; 720 }; 721 722 ipa_smp2p_in: ipa-modem-to-ap { 723 qcom,entry-name = "ipa"; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 }; 728 729 smp2p-wpss { 730 compatible = "qcom,smp2p"; 731 qcom,smem = <617>, <616>; 732 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 733 IPCC_MPROC_SIGNAL_SMP2P 734 IRQ_TYPE_EDGE_RISING>; 735 mboxes = <&ipcc IPCC_CLIENT_WPSS 736 IPCC_MPROC_SIGNAL_SMP2P>; 737 738 qcom,local-pid = <0>; 739 qcom,remote-pid = <13>; 740 741 wpss_smp2p_out: master-kernel { 742 qcom,entry-name = "master-kernel"; 743 #qcom,smem-state-cells = <1>; 744 }; 745 746 wpss_smp2p_in: slave-kernel { 747 qcom,entry-name = "slave-kernel"; 748 interrupt-controller; 749 #interrupt-cells = <2>; 750 }; 751 }; 752 753 pmu { 754 compatible = "arm,armv8-pmuv3"; 755 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 756 }; 757 758 psci { 759 compatible = "arm,psci-1.0"; 760 method = "smc"; 761 }; 762 763 qspi_opp_table: qspi-opp-table { 764 compatible = "operating-points-v2"; 765 766 opp-75000000 { 767 opp-hz = /bits/ 64 <75000000>; 768 required-opps = <&rpmhpd_opp_low_svs>; 769 }; 770 771 opp-150000000 { 772 opp-hz = /bits/ 64 <150000000>; 773 required-opps = <&rpmhpd_opp_svs>; 774 }; 775 776 opp-200000000 { 777 opp-hz = /bits/ 64 <200000000>; 778 required-opps = <&rpmhpd_opp_svs_l1>; 779 }; 780 781 opp-300000000 { 782 opp-hz = /bits/ 64 <300000000>; 783 required-opps = <&rpmhpd_opp_nom>; 784 }; 785 }; 786 787 qup_opp_table: qup-opp-table { 788 compatible = "operating-points-v2"; 789 790 opp-75000000 { 791 opp-hz = /bits/ 64 <75000000>; 792 required-opps = <&rpmhpd_opp_low_svs>; 793 }; 794 795 opp-100000000 { 796 opp-hz = /bits/ 64 <100000000>; 797 required-opps = <&rpmhpd_opp_svs>; 798 }; 799 800 opp-128000000 { 801 opp-hz = /bits/ 64 <128000000>; 802 required-opps = <&rpmhpd_opp_nom>; 803 }; 804 }; 805 806 soc: soc@0 { 807 #address-cells = <2>; 808 #size-cells = <2>; 809 ranges = <0 0 0 0 0x10 0>; 810 dma-ranges = <0 0 0 0 0x10 0>; 811 compatible = "simple-bus"; 812 813 gcc: clock-controller@100000 { 814 compatible = "qcom,gcc-sc7280"; 815 reg = <0 0x00100000 0 0x1f0000>; 816 clocks = <&rpmhcc RPMH_CXO_CLK>, 817 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 818 <0>, <&pcie1_lane 0>, 819 <0>, <0>, <0>, <0>; 820 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 821 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 822 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 823 "ufs_phy_tx_symbol_0_clk", 824 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 825 #clock-cells = <1>; 826 #reset-cells = <1>; 827 #power-domain-cells = <1>; 828 }; 829 830 ipcc: mailbox@408000 { 831 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 832 reg = <0 0x00408000 0 0x1000>; 833 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-controller; 835 #interrupt-cells = <3>; 836 #mbox-cells = <2>; 837 }; 838 839 qfprom: efuse@784000 { 840 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 841 reg = <0 0x00784000 0 0xa20>, 842 <0 0x00780000 0 0xa20>, 843 <0 0x00782000 0 0x120>, 844 <0 0x00786000 0 0x1fff>; 845 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 846 clock-names = "core"; 847 power-domains = <&rpmhpd SC7280_MX>; 848 #address-cells = <1>; 849 #size-cells = <1>; 850 }; 851 852 sdhc_1: sdhci@7c4000 { 853 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 854 pinctrl-names = "default", "sleep"; 855 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 856 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 857 status = "disabled"; 858 859 reg = <0 0x007c4000 0 0x1000>, 860 <0 0x007c5000 0 0x1000>; 861 reg-names = "hc", "cqhci"; 862 863 iommus = <&apps_smmu 0xc0 0x0>; 864 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 866 interrupt-names = "hc_irq", "pwr_irq"; 867 868 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 869 <&gcc GCC_SDCC1_AHB_CLK>, 870 <&rpmhcc RPMH_CXO_CLK>; 871 clock-names = "core", "iface", "xo"; 872 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 874 interconnect-names = "sdhc-ddr","cpu-sdhc"; 875 power-domains = <&rpmhpd SC7280_CX>; 876 operating-points-v2 = <&sdhc1_opp_table>; 877 878 bus-width = <8>; 879 supports-cqe; 880 881 qcom,dll-config = <0x0007642c>; 882 qcom,ddr-config = <0x80040868>; 883 884 mmc-ddr-1_8v; 885 mmc-hs200-1_8v; 886 mmc-hs400-1_8v; 887 mmc-hs400-enhanced-strobe; 888 889 sdhc1_opp_table: opp-table { 890 compatible = "operating-points-v2"; 891 892 opp-100000000 { 893 opp-hz = /bits/ 64 <100000000>; 894 required-opps = <&rpmhpd_opp_low_svs>; 895 opp-peak-kBps = <1800000 400000>; 896 opp-avg-kBps = <100000 0>; 897 }; 898 899 opp-384000000 { 900 opp-hz = /bits/ 64 <384000000>; 901 required-opps = <&rpmhpd_opp_nom>; 902 opp-peak-kBps = <5400000 1600000>; 903 opp-avg-kBps = <390000 0>; 904 }; 905 }; 906 907 }; 908 909 qupv3_id_0: geniqup@9c0000 { 910 compatible = "qcom,geni-se-qup"; 911 reg = <0 0x009c0000 0 0x2000>; 912 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 913 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 914 clock-names = "m-ahb", "s-ahb"; 915 #address-cells = <2>; 916 #size-cells = <2>; 917 ranges; 918 iommus = <&apps_smmu 0x123 0x0>; 919 status = "disabled"; 920 921 i2c0: i2c@980000 { 922 compatible = "qcom,geni-i2c"; 923 reg = <0 0x00980000 0 0x4000>; 924 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 925 clock-names = "se"; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&qup_i2c0_data_clk>; 928 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 932 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 933 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 934 interconnect-names = "qup-core", "qup-config", 935 "qup-memory"; 936 status = "disabled"; 937 }; 938 939 spi0: spi@980000 { 940 compatible = "qcom,geni-spi"; 941 reg = <0 0x00980000 0 0x4000>; 942 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 943 clock-names = "se"; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 946 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 power-domains = <&rpmhpd SC7280_CX>; 950 operating-points-v2 = <&qup_opp_table>; 951 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 952 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 953 interconnect-names = "qup-core", "qup-config"; 954 status = "disabled"; 955 }; 956 957 uart0: serial@980000 { 958 compatible = "qcom,geni-uart"; 959 reg = <0 0x00980000 0 0x4000>; 960 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 961 clock-names = "se"; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 964 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 965 power-domains = <&rpmhpd SC7280_CX>; 966 operating-points-v2 = <&qup_opp_table>; 967 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 968 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 969 interconnect-names = "qup-core", "qup-config"; 970 status = "disabled"; 971 }; 972 973 i2c1: i2c@984000 { 974 compatible = "qcom,geni-i2c"; 975 reg = <0 0x00984000 0 0x4000>; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 977 clock-names = "se"; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&qup_i2c1_data_clk>; 980 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 984 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 985 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 986 interconnect-names = "qup-core", "qup-config", 987 "qup-memory"; 988 status = "disabled"; 989 }; 990 991 spi1: spi@984000 { 992 compatible = "qcom,geni-spi"; 993 reg = <0 0x00984000 0 0x4000>; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 995 clock-names = "se"; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 998 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 power-domains = <&rpmhpd SC7280_CX>; 1002 operating-points-v2 = <&qup_opp_table>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1005 interconnect-names = "qup-core", "qup-config"; 1006 status = "disabled"; 1007 }; 1008 1009 uart1: serial@984000 { 1010 compatible = "qcom,geni-uart"; 1011 reg = <0 0x00984000 0 0x4000>; 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1013 clock-names = "se"; 1014 pinctrl-names = "default"; 1015 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1016 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1017 power-domains = <&rpmhpd SC7280_CX>; 1018 operating-points-v2 = <&qup_opp_table>; 1019 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1020 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1021 interconnect-names = "qup-core", "qup-config"; 1022 status = "disabled"; 1023 }; 1024 1025 i2c2: i2c@988000 { 1026 compatible = "qcom,geni-i2c"; 1027 reg = <0 0x00988000 0 0x4000>; 1028 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1029 clock-names = "se"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&qup_i2c2_data_clk>; 1032 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1036 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1037 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1038 interconnect-names = "qup-core", "qup-config", 1039 "qup-memory"; 1040 status = "disabled"; 1041 }; 1042 1043 spi2: spi@988000 { 1044 compatible = "qcom,geni-spi"; 1045 reg = <0 0x00988000 0 0x4000>; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1047 clock-names = "se"; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1050 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 power-domains = <&rpmhpd SC7280_CX>; 1054 operating-points-v2 = <&qup_opp_table>; 1055 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1056 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1057 interconnect-names = "qup-core", "qup-config"; 1058 status = "disabled"; 1059 }; 1060 1061 uart2: serial@988000 { 1062 compatible = "qcom,geni-uart"; 1063 reg = <0 0x00988000 0 0x4000>; 1064 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1065 clock-names = "se"; 1066 pinctrl-names = "default"; 1067 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1068 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1069 power-domains = <&rpmhpd SC7280_CX>; 1070 operating-points-v2 = <&qup_opp_table>; 1071 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1072 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1073 interconnect-names = "qup-core", "qup-config"; 1074 status = "disabled"; 1075 }; 1076 1077 i2c3: i2c@98c000 { 1078 compatible = "qcom,geni-i2c"; 1079 reg = <0 0x0098c000 0 0x4000>; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1081 clock-names = "se"; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_i2c3_data_clk>; 1084 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1088 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1089 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1090 interconnect-names = "qup-core", "qup-config", 1091 "qup-memory"; 1092 status = "disabled"; 1093 }; 1094 1095 spi3: spi@98c000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0 0x0098c000 0 0x4000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1099 clock-names = "se"; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1102 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 power-domains = <&rpmhpd SC7280_CX>; 1106 operating-points-v2 = <&qup_opp_table>; 1107 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1108 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1109 interconnect-names = "qup-core", "qup-config"; 1110 status = "disabled"; 1111 }; 1112 1113 uart3: serial@98c000 { 1114 compatible = "qcom,geni-uart"; 1115 reg = <0 0x0098c000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1117 clock-names = "se"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1120 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1121 power-domains = <&rpmhpd SC7280_CX>; 1122 operating-points-v2 = <&qup_opp_table>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1125 interconnect-names = "qup-core", "qup-config"; 1126 status = "disabled"; 1127 }; 1128 1129 i2c4: i2c@990000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0 0x00990000 0 0x4000>; 1132 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1133 clock-names = "se"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_i2c4_data_clk>; 1136 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1140 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1142 interconnect-names = "qup-core", "qup-config", 1143 "qup-memory"; 1144 status = "disabled"; 1145 }; 1146 1147 spi4: spi@990000 { 1148 compatible = "qcom,geni-spi"; 1149 reg = <0 0x00990000 0 0x4000>; 1150 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1151 clock-names = "se"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1154 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 power-domains = <&rpmhpd SC7280_CX>; 1158 operating-points-v2 = <&qup_opp_table>; 1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1160 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1161 interconnect-names = "qup-core", "qup-config"; 1162 status = "disabled"; 1163 }; 1164 1165 uart4: serial@990000 { 1166 compatible = "qcom,geni-uart"; 1167 reg = <0 0x00990000 0 0x4000>; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1169 clock-names = "se"; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1172 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1173 power-domains = <&rpmhpd SC7280_CX>; 1174 operating-points-v2 = <&qup_opp_table>; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1176 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1177 interconnect-names = "qup-core", "qup-config"; 1178 status = "disabled"; 1179 }; 1180 1181 i2c5: i2c@994000 { 1182 compatible = "qcom,geni-i2c"; 1183 reg = <0 0x00994000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1185 clock-names = "se"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_i2c5_data_clk>; 1188 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1192 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1193 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1194 interconnect-names = "qup-core", "qup-config", 1195 "qup-memory"; 1196 status = "disabled"; 1197 }; 1198 1199 spi5: spi@994000 { 1200 compatible = "qcom,geni-spi"; 1201 reg = <0 0x00994000 0 0x4000>; 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1203 clock-names = "se"; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1206 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 power-domains = <&rpmhpd SC7280_CX>; 1210 operating-points-v2 = <&qup_opp_table>; 1211 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1212 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1213 interconnect-names = "qup-core", "qup-config"; 1214 status = "disabled"; 1215 }; 1216 1217 uart5: serial@994000 { 1218 compatible = "qcom,geni-uart"; 1219 reg = <0 0x00994000 0 0x4000>; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1221 clock-names = "se"; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1224 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC7280_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c6: i2c@998000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00998000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_i2c6_data_clk>; 1240 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1245 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1246 interconnect-names = "qup-core", "qup-config", 1247 "qup-memory"; 1248 status = "disabled"; 1249 }; 1250 1251 spi6: spi@998000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00998000 0 0x4000>; 1254 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1255 clock-names = "se"; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1258 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 power-domains = <&rpmhpd SC7280_CX>; 1262 operating-points-v2 = <&qup_opp_table>; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1264 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1265 interconnect-names = "qup-core", "qup-config"; 1266 status = "disabled"; 1267 }; 1268 1269 uart6: serial@998000 { 1270 compatible = "qcom,geni-uart"; 1271 reg = <0 0x00998000 0 0x4000>; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1273 clock-names = "se"; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1276 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1277 power-domains = <&rpmhpd SC7280_CX>; 1278 operating-points-v2 = <&qup_opp_table>; 1279 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1280 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 status = "disabled"; 1283 }; 1284 1285 i2c7: i2c@99c000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x0099c000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c7_data_clk>; 1292 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1297 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1298 interconnect-names = "qup-core", "qup-config", 1299 "qup-memory"; 1300 status = "disabled"; 1301 }; 1302 1303 spi7: spi@99c000 { 1304 compatible = "qcom,geni-spi"; 1305 reg = <0 0x0099c000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1310 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&rpmhpd SC7280_CX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1316 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1317 interconnect-names = "qup-core", "qup-config"; 1318 status = "disabled"; 1319 }; 1320 1321 uart7: serial@99c000 { 1322 compatible = "qcom,geni-uart"; 1323 reg = <0 0x0099c000 0 0x4000>; 1324 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1325 clock-names = "se"; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1328 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1329 power-domains = <&rpmhpd SC7280_CX>; 1330 operating-points-v2 = <&qup_opp_table>; 1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1332 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1333 interconnect-names = "qup-core", "qup-config"; 1334 status = "disabled"; 1335 }; 1336 }; 1337 1338 qupv3_id_1: geniqup@ac0000 { 1339 compatible = "qcom,geni-se-qup"; 1340 reg = <0 0x00ac0000 0 0x2000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1342 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1343 clock-names = "m-ahb", "s-ahb"; 1344 #address-cells = <2>; 1345 #size-cells = <2>; 1346 ranges; 1347 iommus = <&apps_smmu 0x43 0x0>; 1348 status = "disabled"; 1349 1350 i2c8: i2c@a80000 { 1351 compatible = "qcom,geni-i2c"; 1352 reg = <0 0x00a80000 0 0x4000>; 1353 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1354 clock-names = "se"; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&qup_i2c8_data_clk>; 1357 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1361 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1362 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1363 interconnect-names = "qup-core", "qup-config", 1364 "qup-memory"; 1365 status = "disabled"; 1366 }; 1367 1368 spi8: spi@a80000 { 1369 compatible = "qcom,geni-spi"; 1370 reg = <0 0x00a80000 0 0x4000>; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1372 clock-names = "se"; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1375 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 power-domains = <&rpmhpd SC7280_CX>; 1379 operating-points-v2 = <&qup_opp_table>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1382 interconnect-names = "qup-core", "qup-config"; 1383 status = "disabled"; 1384 }; 1385 1386 uart8: serial@a80000 { 1387 compatible = "qcom,geni-uart"; 1388 reg = <0 0x00a80000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1393 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1394 power-domains = <&rpmhpd SC7280_CX>; 1395 operating-points-v2 = <&qup_opp_table>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1398 interconnect-names = "qup-core", "qup-config"; 1399 status = "disabled"; 1400 }; 1401 1402 i2c9: i2c@a84000 { 1403 compatible = "qcom,geni-i2c"; 1404 reg = <0 0x00a84000 0 0x4000>; 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1406 clock-names = "se"; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_i2c9_data_clk>; 1409 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1413 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1414 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1415 interconnect-names = "qup-core", "qup-config", 1416 "qup-memory"; 1417 status = "disabled"; 1418 }; 1419 1420 spi9: spi@a84000 { 1421 compatible = "qcom,geni-spi"; 1422 reg = <0 0x00a84000 0 0x4000>; 1423 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1424 clock-names = "se"; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1427 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 power-domains = <&rpmhpd SC7280_CX>; 1431 operating-points-v2 = <&qup_opp_table>; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1433 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1434 interconnect-names = "qup-core", "qup-config"; 1435 status = "disabled"; 1436 }; 1437 1438 uart9: serial@a84000 { 1439 compatible = "qcom,geni-uart"; 1440 reg = <0 0x00a84000 0 0x4000>; 1441 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1442 clock-names = "se"; 1443 pinctrl-names = "default"; 1444 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1445 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1446 power-domains = <&rpmhpd SC7280_CX>; 1447 operating-points-v2 = <&qup_opp_table>; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1449 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1450 interconnect-names = "qup-core", "qup-config"; 1451 status = "disabled"; 1452 }; 1453 1454 i2c10: i2c@a88000 { 1455 compatible = "qcom,geni-i2c"; 1456 reg = <0 0x00a88000 0 0x4000>; 1457 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1458 clock-names = "se"; 1459 pinctrl-names = "default"; 1460 pinctrl-0 = <&qup_i2c10_data_clk>; 1461 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1465 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1466 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1467 interconnect-names = "qup-core", "qup-config", 1468 "qup-memory"; 1469 status = "disabled"; 1470 }; 1471 1472 spi10: spi@a88000 { 1473 compatible = "qcom,geni-spi"; 1474 reg = <0 0x00a88000 0 0x4000>; 1475 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1476 clock-names = "se"; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1479 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 power-domains = <&rpmhpd SC7280_CX>; 1483 operating-points-v2 = <&qup_opp_table>; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1485 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1486 interconnect-names = "qup-core", "qup-config"; 1487 status = "disabled"; 1488 }; 1489 1490 uart10: serial@a88000 { 1491 compatible = "qcom,geni-uart"; 1492 reg = <0 0x00a88000 0 0x4000>; 1493 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1494 clock-names = "se"; 1495 pinctrl-names = "default"; 1496 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1497 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1498 power-domains = <&rpmhpd SC7280_CX>; 1499 operating-points-v2 = <&qup_opp_table>; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1501 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1502 interconnect-names = "qup-core", "qup-config"; 1503 status = "disabled"; 1504 }; 1505 1506 i2c11: i2c@a8c000 { 1507 compatible = "qcom,geni-i2c"; 1508 reg = <0 0x00a8c000 0 0x4000>; 1509 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1510 clock-names = "se"; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_i2c11_data_clk>; 1513 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1518 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1519 interconnect-names = "qup-core", "qup-config", 1520 "qup-memory"; 1521 status = "disabled"; 1522 }; 1523 1524 spi11: spi@a8c000 { 1525 compatible = "qcom,geni-spi"; 1526 reg = <0 0x00a8c000 0 0x4000>; 1527 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1528 clock-names = "se"; 1529 pinctrl-names = "default"; 1530 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1531 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 power-domains = <&rpmhpd SC7280_CX>; 1535 operating-points-v2 = <&qup_opp_table>; 1536 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1537 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1538 interconnect-names = "qup-core", "qup-config"; 1539 status = "disabled"; 1540 }; 1541 1542 uart11: serial@a8c000 { 1543 compatible = "qcom,geni-uart"; 1544 reg = <0 0x00a8c000 0 0x4000>; 1545 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1546 clock-names = "se"; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1549 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1550 power-domains = <&rpmhpd SC7280_CX>; 1551 operating-points-v2 = <&qup_opp_table>; 1552 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1553 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1554 interconnect-names = "qup-core", "qup-config"; 1555 status = "disabled"; 1556 }; 1557 1558 i2c12: i2c@a90000 { 1559 compatible = "qcom,geni-i2c"; 1560 reg = <0 0x00a90000 0 0x4000>; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1562 clock-names = "se"; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_i2c12_data_clk>; 1565 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1570 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1571 interconnect-names = "qup-core", "qup-config", 1572 "qup-memory"; 1573 status = "disabled"; 1574 }; 1575 1576 spi12: spi@a90000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0 0x00a90000 0 0x4000>; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1580 clock-names = "se"; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1583 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 power-domains = <&rpmhpd SC7280_CX>; 1587 operating-points-v2 = <&qup_opp_table>; 1588 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1589 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1590 interconnect-names = "qup-core", "qup-config"; 1591 status = "disabled"; 1592 }; 1593 1594 uart12: serial@a90000 { 1595 compatible = "qcom,geni-uart"; 1596 reg = <0 0x00a90000 0 0x4000>; 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1598 clock-names = "se"; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1601 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1602 power-domains = <&rpmhpd SC7280_CX>; 1603 operating-points-v2 = <&qup_opp_table>; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1606 interconnect-names = "qup-core", "qup-config"; 1607 status = "disabled"; 1608 }; 1609 1610 i2c13: i2c@a94000 { 1611 compatible = "qcom,geni-i2c"; 1612 reg = <0 0x00a94000 0 0x4000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1614 clock-names = "se"; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&qup_i2c13_data_clk>; 1617 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1623 interconnect-names = "qup-core", "qup-config", 1624 "qup-memory"; 1625 status = "disabled"; 1626 }; 1627 1628 spi13: spi@a94000 { 1629 compatible = "qcom,geni-spi"; 1630 reg = <0 0x00a94000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1632 clock-names = "se"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1635 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 power-domains = <&rpmhpd SC7280_CX>; 1639 operating-points-v2 = <&qup_opp_table>; 1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1641 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1642 interconnect-names = "qup-core", "qup-config"; 1643 status = "disabled"; 1644 }; 1645 1646 uart13: serial@a94000 { 1647 compatible = "qcom,geni-uart"; 1648 reg = <0 0x00a94000 0 0x4000>; 1649 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1650 clock-names = "se"; 1651 pinctrl-names = "default"; 1652 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1653 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1654 power-domains = <&rpmhpd SC7280_CX>; 1655 operating-points-v2 = <&qup_opp_table>; 1656 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1657 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1658 interconnect-names = "qup-core", "qup-config"; 1659 status = "disabled"; 1660 }; 1661 1662 i2c14: i2c@a98000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00a98000 0 0x4000>; 1665 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1666 clock-names = "se"; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c14_data_clk>; 1669 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1673 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1674 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1675 interconnect-names = "qup-core", "qup-config", 1676 "qup-memory"; 1677 status = "disabled"; 1678 }; 1679 1680 spi14: spi@a98000 { 1681 compatible = "qcom,geni-spi"; 1682 reg = <0 0x00a98000 0 0x4000>; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1684 clock-names = "se"; 1685 pinctrl-names = "default"; 1686 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1687 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 power-domains = <&rpmhpd SC7280_CX>; 1691 operating-points-v2 = <&qup_opp_table>; 1692 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1694 interconnect-names = "qup-core", "qup-config"; 1695 status = "disabled"; 1696 }; 1697 1698 uart14: serial@a98000 { 1699 compatible = "qcom,geni-uart"; 1700 reg = <0 0x00a98000 0 0x4000>; 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1702 clock-names = "se"; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1705 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1706 power-domains = <&rpmhpd SC7280_CX>; 1707 operating-points-v2 = <&qup_opp_table>; 1708 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1709 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1710 interconnect-names = "qup-core", "qup-config"; 1711 status = "disabled"; 1712 }; 1713 1714 i2c15: i2c@a9c000 { 1715 compatible = "qcom,geni-i2c"; 1716 reg = <0 0x00a9c000 0 0x4000>; 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1718 clock-names = "se"; 1719 pinctrl-names = "default"; 1720 pinctrl-0 = <&qup_i2c15_data_clk>; 1721 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1725 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1726 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1727 interconnect-names = "qup-core", "qup-config", 1728 "qup-memory"; 1729 status = "disabled"; 1730 }; 1731 1732 spi15: spi@a9c000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0 0x00a9c000 0 0x4000>; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1736 clock-names = "se"; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1739 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 power-domains = <&rpmhpd SC7280_CX>; 1743 operating-points-v2 = <&qup_opp_table>; 1744 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1745 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1746 interconnect-names = "qup-core", "qup-config"; 1747 status = "disabled"; 1748 }; 1749 1750 uart15: serial@a9c000 { 1751 compatible = "qcom,geni-uart"; 1752 reg = <0 0x00a9c000 0 0x4000>; 1753 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1754 clock-names = "se"; 1755 pinctrl-names = "default"; 1756 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1757 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1758 power-domains = <&rpmhpd SC7280_CX>; 1759 operating-points-v2 = <&qup_opp_table>; 1760 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1761 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1762 interconnect-names = "qup-core", "qup-config"; 1763 status = "disabled"; 1764 }; 1765 }; 1766 1767 cnoc2: interconnect@1500000 { 1768 reg = <0 0x01500000 0 0x1000>; 1769 compatible = "qcom,sc7280-cnoc2"; 1770 #interconnect-cells = <2>; 1771 qcom,bcm-voters = <&apps_bcm_voter>; 1772 }; 1773 1774 cnoc3: interconnect@1502000 { 1775 reg = <0 0x01502000 0 0x1000>; 1776 compatible = "qcom,sc7280-cnoc3"; 1777 #interconnect-cells = <2>; 1778 qcom,bcm-voters = <&apps_bcm_voter>; 1779 }; 1780 1781 mc_virt: interconnect@1580000 { 1782 reg = <0 0x01580000 0 0x4>; 1783 compatible = "qcom,sc7280-mc-virt"; 1784 #interconnect-cells = <2>; 1785 qcom,bcm-voters = <&apps_bcm_voter>; 1786 }; 1787 1788 system_noc: interconnect@1680000 { 1789 reg = <0 0x01680000 0 0x15480>; 1790 compatible = "qcom,sc7280-system-noc"; 1791 #interconnect-cells = <2>; 1792 qcom,bcm-voters = <&apps_bcm_voter>; 1793 }; 1794 1795 aggre1_noc: interconnect@16e0000 { 1796 compatible = "qcom,sc7280-aggre1-noc"; 1797 reg = <0 0x016e0000 0 0x1c080>; 1798 #interconnect-cells = <2>; 1799 qcom,bcm-voters = <&apps_bcm_voter>; 1800 }; 1801 1802 aggre2_noc: interconnect@1700000 { 1803 reg = <0 0x01700000 0 0x2b080>; 1804 compatible = "qcom,sc7280-aggre2-noc"; 1805 #interconnect-cells = <2>; 1806 qcom,bcm-voters = <&apps_bcm_voter>; 1807 }; 1808 1809 mmss_noc: interconnect@1740000 { 1810 reg = <0 0x01740000 0 0x1e080>; 1811 compatible = "qcom,sc7280-mmss-noc"; 1812 #interconnect-cells = <2>; 1813 qcom,bcm-voters = <&apps_bcm_voter>; 1814 }; 1815 1816 wifi: wifi@17a10040 { 1817 compatible = "qcom,wcn6750-wifi"; 1818 reg = <0 0x17a10040 0 0x0>; 1819 iommus = <&apps_smmu 0x1c00 0x1>; 1820 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1821 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1822 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1823 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1824 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1825 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1826 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1827 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1828 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1829 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1830 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1831 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1832 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1833 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1834 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1835 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1836 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1837 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1838 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1839 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1840 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1841 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1842 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1843 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1844 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1845 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1846 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1847 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1848 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1849 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 1850 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 1851 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 1852 qcom,rproc = <&remoteproc_wpss>; 1853 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 1854 status = "disabled"; 1855 }; 1856 1857 pcie1: pci@1c08000 { 1858 compatible = "qcom,pcie-sc7280"; 1859 reg = <0 0x01c08000 0 0x3000>, 1860 <0 0x40000000 0 0xf1d>, 1861 <0 0x40000f20 0 0xa8>, 1862 <0 0x40001000 0 0x1000>, 1863 <0 0x40100000 0 0x100000>; 1864 1865 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1866 device_type = "pci"; 1867 linux,pci-domain = <1>; 1868 bus-range = <0x00 0xff>; 1869 num-lanes = <2>; 1870 1871 #address-cells = <3>; 1872 #size-cells = <2>; 1873 1874 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1875 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1876 1877 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1878 interrupt-names = "msi"; 1879 #interrupt-cells = <1>; 1880 interrupt-map-mask = <0 0 0 0x7>; 1881 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1882 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1883 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1884 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1885 1886 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1887 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1888 <&pcie1_lane 0>, 1889 <&rpmhcc RPMH_CXO_CLK>, 1890 <&gcc GCC_PCIE_1_AUX_CLK>, 1891 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1892 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1893 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1894 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1895 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1896 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1897 1898 clock-names = "pipe", 1899 "pipe_mux", 1900 "phy_pipe", 1901 "ref", 1902 "aux", 1903 "cfg", 1904 "bus_master", 1905 "bus_slave", 1906 "slave_q2a", 1907 "tbu", 1908 "ddrss_sf_tbu"; 1909 1910 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1911 assigned-clock-rates = <19200000>; 1912 1913 resets = <&gcc GCC_PCIE_1_BCR>; 1914 reset-names = "pci"; 1915 1916 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1917 1918 phys = <&pcie1_lane>; 1919 phy-names = "pciephy"; 1920 1921 pinctrl-names = "default"; 1922 pinctrl-0 = <&pcie1_clkreq_n>; 1923 1924 iommus = <&apps_smmu 0x1c80 0x1>; 1925 1926 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1927 <0x100 &apps_smmu 0x1c81 0x1>; 1928 1929 status = "disabled"; 1930 }; 1931 1932 pcie1_phy: phy@1c0e000 { 1933 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1934 reg = <0 0x01c0e000 0 0x1c0>; 1935 #address-cells = <2>; 1936 #size-cells = <2>; 1937 ranges; 1938 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1939 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1940 <&gcc GCC_PCIE_CLKREF_EN>, 1941 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1942 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1943 1944 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1945 reset-names = "phy"; 1946 1947 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1948 assigned-clock-rates = <100000000>; 1949 1950 status = "disabled"; 1951 1952 pcie1_lane: lanes@1c0e200 { 1953 reg = <0 0x01c0e200 0 0x170>, 1954 <0 0x01c0e400 0 0x200>, 1955 <0 0x01c0ea00 0 0x1f0>, 1956 <0 0x01c0e600 0 0x170>, 1957 <0 0x01c0e800 0 0x200>, 1958 <0 0x01c0ee00 0 0xf4>; 1959 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1960 clock-names = "pipe0"; 1961 1962 #phy-cells = <0>; 1963 #clock-cells = <1>; 1964 clock-output-names = "pcie_1_pipe_clk"; 1965 }; 1966 }; 1967 1968 ipa: ipa@1e40000 { 1969 compatible = "qcom,sc7280-ipa"; 1970 1971 iommus = <&apps_smmu 0x480 0x0>, 1972 <&apps_smmu 0x482 0x0>; 1973 reg = <0 0x1e40000 0 0x8000>, 1974 <0 0x1e50000 0 0x4ad0>, 1975 <0 0x1e04000 0 0x23000>; 1976 reg-names = "ipa-reg", 1977 "ipa-shared", 1978 "gsi"; 1979 1980 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1981 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1982 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1983 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1984 interrupt-names = "ipa", 1985 "gsi", 1986 "ipa-clock-query", 1987 "ipa-setup-ready"; 1988 1989 clocks = <&rpmhcc RPMH_IPA_CLK>; 1990 clock-names = "core"; 1991 1992 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1994 interconnect-names = "memory", 1995 "config"; 1996 1997 qcom,qmp = <&aoss_qmp>; 1998 1999 qcom,smem-states = <&ipa_smp2p_out 0>, 2000 <&ipa_smp2p_out 1>; 2001 qcom,smem-state-names = "ipa-clock-enabled-valid", 2002 "ipa-clock-enabled"; 2003 2004 status = "disabled"; 2005 }; 2006 2007 tcsr_mutex: hwlock@1f40000 { 2008 compatible = "qcom,tcsr-mutex", "syscon"; 2009 reg = <0 0x01f40000 0 0x40000>; 2010 #hwlock-cells = <1>; 2011 }; 2012 2013 tcsr: syscon@1fc0000 { 2014 compatible = "qcom,sc7280-tcsr", "syscon"; 2015 reg = <0 0x01fc0000 0 0x30000>; 2016 }; 2017 2018 lpasscc: lpasscc@3000000 { 2019 compatible = "qcom,sc7280-lpasscc"; 2020 reg = <0 0x03000000 0 0x40>, 2021 <0 0x03c04000 0 0x4>, 2022 <0 0x03389000 0 0x24>; 2023 reg-names = "qdsp6ss", "top_cc", "cc"; 2024 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2025 clock-names = "iface"; 2026 #clock-cells = <1>; 2027 }; 2028 2029 lpass_ag_noc: interconnect@3c40000 { 2030 reg = <0 0x03c40000 0 0xf080>; 2031 compatible = "qcom,sc7280-lpass-ag-noc"; 2032 #interconnect-cells = <2>; 2033 qcom,bcm-voters = <&apps_bcm_voter>; 2034 }; 2035 2036 gpu: gpu@3d00000 { 2037 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2038 reg = <0 0x03d00000 0 0x40000>, 2039 <0 0x03d9e000 0 0x1000>, 2040 <0 0x03d61000 0 0x800>; 2041 reg-names = "kgsl_3d0_reg_memory", 2042 "cx_mem", 2043 "cx_dbgc"; 2044 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2045 iommus = <&adreno_smmu 0 0x401>; 2046 operating-points-v2 = <&gpu_opp_table>; 2047 qcom,gmu = <&gmu>; 2048 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2049 interconnect-names = "gfx-mem"; 2050 #cooling-cells = <2>; 2051 2052 gpu_opp_table: opp-table { 2053 compatible = "operating-points-v2"; 2054 2055 opp-315000000 { 2056 opp-hz = /bits/ 64 <315000000>; 2057 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2058 opp-peak-kBps = <1804000>; 2059 }; 2060 2061 opp-450000000 { 2062 opp-hz = /bits/ 64 <450000000>; 2063 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2064 opp-peak-kBps = <4068000>; 2065 }; 2066 2067 opp-550000000 { 2068 opp-hz = /bits/ 64 <550000000>; 2069 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2070 opp-peak-kBps = <6832000>; 2071 }; 2072 }; 2073 }; 2074 2075 gmu: gmu@3d6a000 { 2076 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2077 reg = <0 0x03d6a000 0 0x34000>, 2078 <0 0x3de0000 0 0x10000>, 2079 <0 0x0b290000 0 0x10000>; 2080 reg-names = "gmu", "rscc", "gmu_pdc"; 2081 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2083 interrupt-names = "hfi", "gmu"; 2084 clocks = <&gpucc 5>, 2085 <&gpucc 8>, 2086 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2087 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2088 <&gpucc 2>, 2089 <&gpucc 15>, 2090 <&gpucc 11>; 2091 clock-names = "gmu", 2092 "cxo", 2093 "axi", 2094 "memnoc", 2095 "ahb", 2096 "hub", 2097 "smmu_vote"; 2098 power-domains = <&gpucc 0>, 2099 <&gpucc 1>; 2100 power-domain-names = "cx", 2101 "gx"; 2102 iommus = <&adreno_smmu 5 0x400>; 2103 operating-points-v2 = <&gmu_opp_table>; 2104 2105 gmu_opp_table: opp-table { 2106 compatible = "operating-points-v2"; 2107 2108 opp-200000000 { 2109 opp-hz = /bits/ 64 <200000000>; 2110 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2111 }; 2112 }; 2113 }; 2114 2115 gpucc: clock-controller@3d90000 { 2116 compatible = "qcom,sc7280-gpucc"; 2117 reg = <0 0x03d90000 0 0x9000>; 2118 clocks = <&rpmhcc RPMH_CXO_CLK>, 2119 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2120 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2121 clock-names = "bi_tcxo", 2122 "gcc_gpu_gpll0_clk_src", 2123 "gcc_gpu_gpll0_div_clk_src"; 2124 #clock-cells = <1>; 2125 #reset-cells = <1>; 2126 #power-domain-cells = <1>; 2127 }; 2128 2129 adreno_smmu: iommu@3da0000 { 2130 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2131 reg = <0 0x03da0000 0 0x20000>; 2132 #iommu-cells = <2>; 2133 #global-interrupts = <2>; 2134 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2146 2147 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2148 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2149 <&gpucc 2>, 2150 <&gpucc 11>, 2151 <&gpucc 5>, 2152 <&gpucc 15>, 2153 <&gpucc 13>; 2154 clock-names = "gcc_gpu_memnoc_gfx_clk", 2155 "gcc_gpu_snoc_dvm_gfx_clk", 2156 "gpu_cc_ahb_clk", 2157 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2158 "gpu_cc_cx_gmu_clk", 2159 "gpu_cc_hub_cx_int_clk", 2160 "gpu_cc_hub_aon_clk"; 2161 2162 power-domains = <&gpucc 0>; 2163 }; 2164 2165 remoteproc_mpss: remoteproc@4080000 { 2166 compatible = "qcom,sc7280-mpss-pas"; 2167 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2168 reg-names = "qdsp6", "rmb"; 2169 2170 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2171 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2172 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2173 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2174 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2175 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2176 interrupt-names = "wdog", "fatal", "ready", "handover", 2177 "stop-ack", "shutdown-ack"; 2178 2179 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2180 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2181 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2182 <&rpmhcc RPMH_PKA_CLK>, 2183 <&rpmhcc RPMH_CXO_CLK>; 2184 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2185 2186 power-domains = <&rpmhpd SC7280_CX>, 2187 <&rpmhpd SC7280_MSS>; 2188 power-domain-names = "cx", "mss"; 2189 2190 memory-region = <&mpss_mem>; 2191 2192 qcom,qmp = <&aoss_qmp>; 2193 2194 qcom,smem-states = <&modem_smp2p_out 0>; 2195 qcom,smem-state-names = "stop"; 2196 2197 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2198 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2199 reset-names = "mss_restart", "pdc_reset"; 2200 2201 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 2202 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 2203 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 2204 2205 status = "disabled"; 2206 2207 glink-edge { 2208 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2209 IPCC_MPROC_SIGNAL_GLINK_QMP 2210 IRQ_TYPE_EDGE_RISING>; 2211 mboxes = <&ipcc IPCC_CLIENT_MPSS 2212 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2213 label = "modem"; 2214 qcom,remote-pid = <1>; 2215 }; 2216 }; 2217 2218 stm@6002000 { 2219 compatible = "arm,coresight-stm", "arm,primecell"; 2220 reg = <0 0x06002000 0 0x1000>, 2221 <0 0x16280000 0 0x180000>; 2222 reg-names = "stm-base", "stm-stimulus-base"; 2223 2224 clocks = <&aoss_qmp>; 2225 clock-names = "apb_pclk"; 2226 2227 out-ports { 2228 port { 2229 stm_out: endpoint { 2230 remote-endpoint = <&funnel0_in7>; 2231 }; 2232 }; 2233 }; 2234 }; 2235 2236 funnel@6041000 { 2237 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2238 reg = <0 0x06041000 0 0x1000>; 2239 2240 clocks = <&aoss_qmp>; 2241 clock-names = "apb_pclk"; 2242 2243 out-ports { 2244 port { 2245 funnel0_out: endpoint { 2246 remote-endpoint = <&merge_funnel_in0>; 2247 }; 2248 }; 2249 }; 2250 2251 in-ports { 2252 #address-cells = <1>; 2253 #size-cells = <0>; 2254 2255 port@7 { 2256 reg = <7>; 2257 funnel0_in7: endpoint { 2258 remote-endpoint = <&stm_out>; 2259 }; 2260 }; 2261 }; 2262 }; 2263 2264 funnel@6042000 { 2265 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2266 reg = <0 0x06042000 0 0x1000>; 2267 2268 clocks = <&aoss_qmp>; 2269 clock-names = "apb_pclk"; 2270 2271 out-ports { 2272 port { 2273 funnel1_out: endpoint { 2274 remote-endpoint = <&merge_funnel_in1>; 2275 }; 2276 }; 2277 }; 2278 2279 in-ports { 2280 #address-cells = <1>; 2281 #size-cells = <0>; 2282 2283 port@4 { 2284 reg = <4>; 2285 funnel1_in4: endpoint { 2286 remote-endpoint = <&apss_merge_funnel_out>; 2287 }; 2288 }; 2289 }; 2290 }; 2291 2292 funnel@6045000 { 2293 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2294 reg = <0 0x06045000 0 0x1000>; 2295 2296 clocks = <&aoss_qmp>; 2297 clock-names = "apb_pclk"; 2298 2299 out-ports { 2300 port { 2301 merge_funnel_out: endpoint { 2302 remote-endpoint = <&swao_funnel_in>; 2303 }; 2304 }; 2305 }; 2306 2307 in-ports { 2308 #address-cells = <1>; 2309 #size-cells = <0>; 2310 2311 port@0 { 2312 reg = <0>; 2313 merge_funnel_in0: endpoint { 2314 remote-endpoint = <&funnel0_out>; 2315 }; 2316 }; 2317 2318 port@1 { 2319 reg = <1>; 2320 merge_funnel_in1: endpoint { 2321 remote-endpoint = <&funnel1_out>; 2322 }; 2323 }; 2324 }; 2325 }; 2326 2327 replicator@6046000 { 2328 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2329 reg = <0 0x06046000 0 0x1000>; 2330 2331 clocks = <&aoss_qmp>; 2332 clock-names = "apb_pclk"; 2333 2334 out-ports { 2335 port { 2336 replicator_out: endpoint { 2337 remote-endpoint = <&etr_in>; 2338 }; 2339 }; 2340 }; 2341 2342 in-ports { 2343 port { 2344 replicator_in: endpoint { 2345 remote-endpoint = <&swao_replicator_out>; 2346 }; 2347 }; 2348 }; 2349 }; 2350 2351 etr@6048000 { 2352 compatible = "arm,coresight-tmc", "arm,primecell"; 2353 reg = <0 0x06048000 0 0x1000>; 2354 iommus = <&apps_smmu 0x04c0 0>; 2355 2356 clocks = <&aoss_qmp>; 2357 clock-names = "apb_pclk"; 2358 arm,scatter-gather; 2359 2360 in-ports { 2361 port { 2362 etr_in: endpoint { 2363 remote-endpoint = <&replicator_out>; 2364 }; 2365 }; 2366 }; 2367 }; 2368 2369 funnel@6b04000 { 2370 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2371 reg = <0 0x06b04000 0 0x1000>; 2372 2373 clocks = <&aoss_qmp>; 2374 clock-names = "apb_pclk"; 2375 2376 out-ports { 2377 port { 2378 swao_funnel_out: endpoint { 2379 remote-endpoint = <&etf_in>; 2380 }; 2381 }; 2382 }; 2383 2384 in-ports { 2385 #address-cells = <1>; 2386 #size-cells = <0>; 2387 2388 port@7 { 2389 reg = <7>; 2390 swao_funnel_in: endpoint { 2391 remote-endpoint = <&merge_funnel_out>; 2392 }; 2393 }; 2394 }; 2395 }; 2396 2397 etf@6b05000 { 2398 compatible = "arm,coresight-tmc", "arm,primecell"; 2399 reg = <0 0x06b05000 0 0x1000>; 2400 2401 clocks = <&aoss_qmp>; 2402 clock-names = "apb_pclk"; 2403 2404 out-ports { 2405 port { 2406 etf_out: endpoint { 2407 remote-endpoint = <&swao_replicator_in>; 2408 }; 2409 }; 2410 }; 2411 2412 in-ports { 2413 port { 2414 etf_in: endpoint { 2415 remote-endpoint = <&swao_funnel_out>; 2416 }; 2417 }; 2418 }; 2419 }; 2420 2421 replicator@6b06000 { 2422 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2423 reg = <0 0x06b06000 0 0x1000>; 2424 2425 clocks = <&aoss_qmp>; 2426 clock-names = "apb_pclk"; 2427 qcom,replicator-loses-context; 2428 2429 out-ports { 2430 port { 2431 swao_replicator_out: endpoint { 2432 remote-endpoint = <&replicator_in>; 2433 }; 2434 }; 2435 }; 2436 2437 in-ports { 2438 port { 2439 swao_replicator_in: endpoint { 2440 remote-endpoint = <&etf_out>; 2441 }; 2442 }; 2443 }; 2444 }; 2445 2446 etm@7040000 { 2447 compatible = "arm,coresight-etm4x", "arm,primecell"; 2448 reg = <0 0x07040000 0 0x1000>; 2449 2450 cpu = <&CPU0>; 2451 2452 clocks = <&aoss_qmp>; 2453 clock-names = "apb_pclk"; 2454 arm,coresight-loses-context-with-cpu; 2455 qcom,skip-power-up; 2456 2457 out-ports { 2458 port { 2459 etm0_out: endpoint { 2460 remote-endpoint = <&apss_funnel_in0>; 2461 }; 2462 }; 2463 }; 2464 }; 2465 2466 etm@7140000 { 2467 compatible = "arm,coresight-etm4x", "arm,primecell"; 2468 reg = <0 0x07140000 0 0x1000>; 2469 2470 cpu = <&CPU1>; 2471 2472 clocks = <&aoss_qmp>; 2473 clock-names = "apb_pclk"; 2474 arm,coresight-loses-context-with-cpu; 2475 qcom,skip-power-up; 2476 2477 out-ports { 2478 port { 2479 etm1_out: endpoint { 2480 remote-endpoint = <&apss_funnel_in1>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 etm@7240000 { 2487 compatible = "arm,coresight-etm4x", "arm,primecell"; 2488 reg = <0 0x07240000 0 0x1000>; 2489 2490 cpu = <&CPU2>; 2491 2492 clocks = <&aoss_qmp>; 2493 clock-names = "apb_pclk"; 2494 arm,coresight-loses-context-with-cpu; 2495 qcom,skip-power-up; 2496 2497 out-ports { 2498 port { 2499 etm2_out: endpoint { 2500 remote-endpoint = <&apss_funnel_in2>; 2501 }; 2502 }; 2503 }; 2504 }; 2505 2506 etm@7340000 { 2507 compatible = "arm,coresight-etm4x", "arm,primecell"; 2508 reg = <0 0x07340000 0 0x1000>; 2509 2510 cpu = <&CPU3>; 2511 2512 clocks = <&aoss_qmp>; 2513 clock-names = "apb_pclk"; 2514 arm,coresight-loses-context-with-cpu; 2515 qcom,skip-power-up; 2516 2517 out-ports { 2518 port { 2519 etm3_out: endpoint { 2520 remote-endpoint = <&apss_funnel_in3>; 2521 }; 2522 }; 2523 }; 2524 }; 2525 2526 etm@7440000 { 2527 compatible = "arm,coresight-etm4x", "arm,primecell"; 2528 reg = <0 0x07440000 0 0x1000>; 2529 2530 cpu = <&CPU4>; 2531 2532 clocks = <&aoss_qmp>; 2533 clock-names = "apb_pclk"; 2534 arm,coresight-loses-context-with-cpu; 2535 qcom,skip-power-up; 2536 2537 out-ports { 2538 port { 2539 etm4_out: endpoint { 2540 remote-endpoint = <&apss_funnel_in4>; 2541 }; 2542 }; 2543 }; 2544 }; 2545 2546 etm@7540000 { 2547 compatible = "arm,coresight-etm4x", "arm,primecell"; 2548 reg = <0 0x07540000 0 0x1000>; 2549 2550 cpu = <&CPU5>; 2551 2552 clocks = <&aoss_qmp>; 2553 clock-names = "apb_pclk"; 2554 arm,coresight-loses-context-with-cpu; 2555 qcom,skip-power-up; 2556 2557 out-ports { 2558 port { 2559 etm5_out: endpoint { 2560 remote-endpoint = <&apss_funnel_in5>; 2561 }; 2562 }; 2563 }; 2564 }; 2565 2566 etm@7640000 { 2567 compatible = "arm,coresight-etm4x", "arm,primecell"; 2568 reg = <0 0x07640000 0 0x1000>; 2569 2570 cpu = <&CPU6>; 2571 2572 clocks = <&aoss_qmp>; 2573 clock-names = "apb_pclk"; 2574 arm,coresight-loses-context-with-cpu; 2575 qcom,skip-power-up; 2576 2577 out-ports { 2578 port { 2579 etm6_out: endpoint { 2580 remote-endpoint = <&apss_funnel_in6>; 2581 }; 2582 }; 2583 }; 2584 }; 2585 2586 etm@7740000 { 2587 compatible = "arm,coresight-etm4x", "arm,primecell"; 2588 reg = <0 0x07740000 0 0x1000>; 2589 2590 cpu = <&CPU7>; 2591 2592 clocks = <&aoss_qmp>; 2593 clock-names = "apb_pclk"; 2594 arm,coresight-loses-context-with-cpu; 2595 qcom,skip-power-up; 2596 2597 out-ports { 2598 port { 2599 etm7_out: endpoint { 2600 remote-endpoint = <&apss_funnel_in7>; 2601 }; 2602 }; 2603 }; 2604 }; 2605 2606 funnel@7800000 { /* APSS Funnel */ 2607 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2608 reg = <0 0x07800000 0 0x1000>; 2609 2610 clocks = <&aoss_qmp>; 2611 clock-names = "apb_pclk"; 2612 2613 out-ports { 2614 port { 2615 apss_funnel_out: endpoint { 2616 remote-endpoint = <&apss_merge_funnel_in>; 2617 }; 2618 }; 2619 }; 2620 2621 in-ports { 2622 #address-cells = <1>; 2623 #size-cells = <0>; 2624 2625 port@0 { 2626 reg = <0>; 2627 apss_funnel_in0: endpoint { 2628 remote-endpoint = <&etm0_out>; 2629 }; 2630 }; 2631 2632 port@1 { 2633 reg = <1>; 2634 apss_funnel_in1: endpoint { 2635 remote-endpoint = <&etm1_out>; 2636 }; 2637 }; 2638 2639 port@2 { 2640 reg = <2>; 2641 apss_funnel_in2: endpoint { 2642 remote-endpoint = <&etm2_out>; 2643 }; 2644 }; 2645 2646 port@3 { 2647 reg = <3>; 2648 apss_funnel_in3: endpoint { 2649 remote-endpoint = <&etm3_out>; 2650 }; 2651 }; 2652 2653 port@4 { 2654 reg = <4>; 2655 apss_funnel_in4: endpoint { 2656 remote-endpoint = <&etm4_out>; 2657 }; 2658 }; 2659 2660 port@5 { 2661 reg = <5>; 2662 apss_funnel_in5: endpoint { 2663 remote-endpoint = <&etm5_out>; 2664 }; 2665 }; 2666 2667 port@6 { 2668 reg = <6>; 2669 apss_funnel_in6: endpoint { 2670 remote-endpoint = <&etm6_out>; 2671 }; 2672 }; 2673 2674 port@7 { 2675 reg = <7>; 2676 apss_funnel_in7: endpoint { 2677 remote-endpoint = <&etm7_out>; 2678 }; 2679 }; 2680 }; 2681 }; 2682 2683 funnel@7810000 { 2684 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2685 reg = <0 0x07810000 0 0x1000>; 2686 2687 clocks = <&aoss_qmp>; 2688 clock-names = "apb_pclk"; 2689 2690 out-ports { 2691 port { 2692 apss_merge_funnel_out: endpoint { 2693 remote-endpoint = <&funnel1_in4>; 2694 }; 2695 }; 2696 }; 2697 2698 in-ports { 2699 port { 2700 apss_merge_funnel_in: endpoint { 2701 remote-endpoint = <&apss_funnel_out>; 2702 }; 2703 }; 2704 }; 2705 }; 2706 2707 sdhc_2: sdhci@8804000 { 2708 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2709 pinctrl-names = "default", "sleep"; 2710 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 2711 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 2712 status = "disabled"; 2713 2714 reg = <0 0x08804000 0 0x1000>; 2715 2716 iommus = <&apps_smmu 0x100 0x0>; 2717 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2719 interrupt-names = "hc_irq", "pwr_irq"; 2720 2721 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2722 <&gcc GCC_SDCC2_AHB_CLK>, 2723 <&rpmhcc RPMH_CXO_CLK>; 2724 clock-names = "core", "iface", "xo"; 2725 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2726 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2727 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2728 power-domains = <&rpmhpd SC7280_CX>; 2729 operating-points-v2 = <&sdhc2_opp_table>; 2730 2731 bus-width = <4>; 2732 2733 qcom,dll-config = <0x0007642c>; 2734 2735 sdhc2_opp_table: opp-table { 2736 compatible = "operating-points-v2"; 2737 2738 opp-100000000 { 2739 opp-hz = /bits/ 64 <100000000>; 2740 required-opps = <&rpmhpd_opp_low_svs>; 2741 opp-peak-kBps = <1800000 400000>; 2742 opp-avg-kBps = <100000 0>; 2743 }; 2744 2745 opp-202000000 { 2746 opp-hz = /bits/ 64 <202000000>; 2747 required-opps = <&rpmhpd_opp_nom>; 2748 opp-peak-kBps = <5400000 1600000>; 2749 opp-avg-kBps = <200000 0>; 2750 }; 2751 }; 2752 2753 }; 2754 2755 usb_1_hsphy: phy@88e3000 { 2756 compatible = "qcom,sc7280-usb-hs-phy", 2757 "qcom,usb-snps-hs-7nm-phy"; 2758 reg = <0 0x088e3000 0 0x400>; 2759 status = "disabled"; 2760 #phy-cells = <0>; 2761 2762 clocks = <&rpmhcc RPMH_CXO_CLK>; 2763 clock-names = "ref"; 2764 2765 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2766 }; 2767 2768 usb_2_hsphy: phy@88e4000 { 2769 compatible = "qcom,sc7280-usb-hs-phy", 2770 "qcom,usb-snps-hs-7nm-phy"; 2771 reg = <0 0x088e4000 0 0x400>; 2772 status = "disabled"; 2773 #phy-cells = <0>; 2774 2775 clocks = <&rpmhcc RPMH_CXO_CLK>; 2776 clock-names = "ref"; 2777 2778 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2779 }; 2780 2781 usb_1_qmpphy: phy-wrapper@88e9000 { 2782 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2783 "qcom,sm8250-qmp-usb3-dp-phy"; 2784 reg = <0 0x088e9000 0 0x200>, 2785 <0 0x088e8000 0 0x40>, 2786 <0 0x088ea000 0 0x200>; 2787 status = "disabled"; 2788 #address-cells = <2>; 2789 #size-cells = <2>; 2790 ranges; 2791 2792 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2793 <&rpmhcc RPMH_CXO_CLK>, 2794 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2795 clock-names = "aux", "ref_clk_src", "com_aux"; 2796 2797 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2798 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2799 reset-names = "phy", "common"; 2800 2801 usb_1_ssphy: usb3-phy@88e9200 { 2802 reg = <0 0x088e9200 0 0x200>, 2803 <0 0x088e9400 0 0x200>, 2804 <0 0x088e9c00 0 0x400>, 2805 <0 0x088e9600 0 0x200>, 2806 <0 0x088e9800 0 0x200>, 2807 <0 0x088e9a00 0 0x100>; 2808 #clock-cells = <0>; 2809 #phy-cells = <0>; 2810 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2811 clock-names = "pipe0"; 2812 clock-output-names = "usb3_phy_pipe_clk_src"; 2813 }; 2814 2815 dp_phy: dp-phy@88ea200 { 2816 reg = <0 0x088ea200 0 0x200>, 2817 <0 0x088ea400 0 0x200>, 2818 <0 0x088eaa00 0 0x200>, 2819 <0 0x088ea600 0 0x200>, 2820 <0 0x088ea800 0 0x200>; 2821 #phy-cells = <0>; 2822 #clock-cells = <1>; 2823 }; 2824 }; 2825 2826 usb_2: usb@8cf8800 { 2827 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2828 reg = <0 0x08cf8800 0 0x400>; 2829 status = "disabled"; 2830 #address-cells = <2>; 2831 #size-cells = <2>; 2832 ranges; 2833 dma-ranges; 2834 2835 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2836 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2837 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2838 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2839 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2840 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2841 "sleep"; 2842 2843 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2844 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2845 assigned-clock-rates = <19200000>, <200000000>; 2846 2847 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2848 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2849 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2850 interrupt-names = "hs_phy_irq", 2851 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2852 2853 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2854 2855 resets = <&gcc GCC_USB30_SEC_BCR>; 2856 2857 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2858 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2859 interconnect-names = "usb-ddr", "apps-usb"; 2860 2861 usb_2_dwc3: usb@8c00000 { 2862 compatible = "snps,dwc3"; 2863 reg = <0 0x08c00000 0 0xe000>; 2864 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2865 iommus = <&apps_smmu 0xa0 0x0>; 2866 snps,dis_u2_susphy_quirk; 2867 snps,dis_enblslpm_quirk; 2868 phys = <&usb_2_hsphy>; 2869 phy-names = "usb2-phy"; 2870 maximum-speed = "high-speed"; 2871 }; 2872 }; 2873 2874 qspi: spi@88dc000 { 2875 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2876 reg = <0 0x088dc000 0 0x1000>; 2877 #address-cells = <1>; 2878 #size-cells = <0>; 2879 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2880 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2881 <&gcc GCC_QSPI_CORE_CLK>; 2882 clock-names = "iface", "core"; 2883 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2884 &cnoc2 SLAVE_QSPI_0 0>; 2885 interconnect-names = "qspi-config"; 2886 power-domains = <&rpmhpd SC7280_CX>; 2887 operating-points-v2 = <&qspi_opp_table>; 2888 status = "disabled"; 2889 }; 2890 2891 remoteproc_wpss: remoteproc@8a00000 { 2892 compatible = "qcom,sc7280-wpss-pil"; 2893 reg = <0 0x08a00000 0 0x10000>; 2894 2895 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 2896 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2897 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2898 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2899 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2900 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2901 interrupt-names = "wdog", "fatal", "ready", "handover", 2902 "stop-ack", "shutdown-ack"; 2903 2904 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 2905 <&gcc GCC_WPSS_AHB_CLK>, 2906 <&gcc GCC_WPSS_RSCP_CLK>, 2907 <&rpmhcc RPMH_CXO_CLK>; 2908 clock-names = "ahb_bdg", "ahb", 2909 "rscp", "xo"; 2910 2911 power-domains = <&rpmhpd SC7280_CX>, 2912 <&rpmhpd SC7280_MX>; 2913 power-domain-names = "cx", "mx"; 2914 2915 memory-region = <&wpss_mem>; 2916 2917 qcom,qmp = <&aoss_qmp>; 2918 2919 qcom,smem-states = <&wpss_smp2p_out 0>; 2920 qcom,smem-state-names = "stop"; 2921 2922 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 2923 <&pdc_reset PDC_WPSS_SYNC_RESET>; 2924 reset-names = "restart", "pdc_sync"; 2925 2926 qcom,halt-regs = <&tcsr_mutex 0x37000>; 2927 2928 status = "disabled"; 2929 2930 glink-edge { 2931 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 2932 IPCC_MPROC_SIGNAL_GLINK_QMP 2933 IRQ_TYPE_EDGE_RISING>; 2934 mboxes = <&ipcc IPCC_CLIENT_WPSS 2935 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2936 2937 label = "wpss"; 2938 qcom,remote-pid = <13>; 2939 }; 2940 }; 2941 2942 dc_noc: interconnect@90e0000 { 2943 reg = <0 0x090e0000 0 0x5080>; 2944 compatible = "qcom,sc7280-dc-noc"; 2945 #interconnect-cells = <2>; 2946 qcom,bcm-voters = <&apps_bcm_voter>; 2947 }; 2948 2949 gem_noc: interconnect@9100000 { 2950 reg = <0 0x9100000 0 0xe2200>; 2951 compatible = "qcom,sc7280-gem-noc"; 2952 #interconnect-cells = <2>; 2953 qcom,bcm-voters = <&apps_bcm_voter>; 2954 }; 2955 2956 system-cache-controller@9200000 { 2957 compatible = "qcom,sc7280-llcc"; 2958 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2959 reg-names = "llcc_base", "llcc_broadcast_base"; 2960 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2961 }; 2962 2963 nsp_noc: interconnect@a0c0000 { 2964 reg = <0 0x0a0c0000 0 0x10000>; 2965 compatible = "qcom,sc7280-nsp-noc"; 2966 #interconnect-cells = <2>; 2967 qcom,bcm-voters = <&apps_bcm_voter>; 2968 }; 2969 2970 usb_1: usb@a6f8800 { 2971 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2972 reg = <0 0x0a6f8800 0 0x400>; 2973 status = "disabled"; 2974 #address-cells = <2>; 2975 #size-cells = <2>; 2976 ranges; 2977 dma-ranges; 2978 2979 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2980 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2981 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2982 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2983 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2984 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2985 "sleep"; 2986 2987 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2988 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2989 assigned-clock-rates = <19200000>, <200000000>; 2990 2991 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2992 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2993 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2994 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2995 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2996 "dm_hs_phy_irq", "ss_phy_irq"; 2997 2998 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2999 3000 resets = <&gcc GCC_USB30_PRIM_BCR>; 3001 3002 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3003 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3004 interconnect-names = "usb-ddr", "apps-usb"; 3005 3006 usb_1_dwc3: usb@a600000 { 3007 compatible = "snps,dwc3"; 3008 reg = <0 0x0a600000 0 0xe000>; 3009 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3010 iommus = <&apps_smmu 0xe0 0x0>; 3011 snps,dis_u2_susphy_quirk; 3012 snps,dis_enblslpm_quirk; 3013 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3014 phy-names = "usb2-phy", "usb3-phy"; 3015 maximum-speed = "super-speed"; 3016 }; 3017 }; 3018 3019 venus: video-codec@aa00000 { 3020 compatible = "qcom,sc7280-venus"; 3021 reg = <0 0x0aa00000 0 0xd0600>; 3022 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3023 3024 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3025 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3026 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3027 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3028 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3029 clock-names = "core", "bus", "iface", 3030 "vcodec_core", "vcodec_bus"; 3031 3032 power-domains = <&videocc MVSC_GDSC>, 3033 <&videocc MVS0_GDSC>, 3034 <&rpmhpd SC7280_CX>; 3035 power-domain-names = "venus", "vcodec0", "cx"; 3036 operating-points-v2 = <&venus_opp_table>; 3037 3038 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3039 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3040 interconnect-names = "cpu-cfg", "video-mem"; 3041 3042 iommus = <&apps_smmu 0x2180 0x20>, 3043 <&apps_smmu 0x2184 0x20>; 3044 memory-region = <&video_mem>; 3045 3046 video-decoder { 3047 compatible = "venus-decoder"; 3048 }; 3049 3050 video-encoder { 3051 compatible = "venus-encoder"; 3052 }; 3053 3054 video-firmware { 3055 iommus = <&apps_smmu 0x21a2 0x0>; 3056 }; 3057 3058 venus_opp_table: venus-opp-table { 3059 compatible = "operating-points-v2"; 3060 3061 opp-133330000 { 3062 opp-hz = /bits/ 64 <133330000>; 3063 required-opps = <&rpmhpd_opp_low_svs>; 3064 }; 3065 3066 opp-240000000 { 3067 opp-hz = /bits/ 64 <240000000>; 3068 required-opps = <&rpmhpd_opp_svs>; 3069 }; 3070 3071 opp-335000000 { 3072 opp-hz = /bits/ 64 <335000000>; 3073 required-opps = <&rpmhpd_opp_svs_l1>; 3074 }; 3075 3076 opp-424000000 { 3077 opp-hz = /bits/ 64 <424000000>; 3078 required-opps = <&rpmhpd_opp_nom>; 3079 }; 3080 3081 opp-460000048 { 3082 opp-hz = /bits/ 64 <460000048>; 3083 required-opps = <&rpmhpd_opp_turbo>; 3084 }; 3085 }; 3086 3087 }; 3088 3089 videocc: clock-controller@aaf0000 { 3090 compatible = "qcom,sc7280-videocc"; 3091 reg = <0 0xaaf0000 0 0x10000>; 3092 clocks = <&rpmhcc RPMH_CXO_CLK>, 3093 <&rpmhcc RPMH_CXO_CLK_A>; 3094 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3095 #clock-cells = <1>; 3096 #reset-cells = <1>; 3097 #power-domain-cells = <1>; 3098 }; 3099 3100 camcc: clock-controller@ad00000 { 3101 compatible = "qcom,sc7280-camcc"; 3102 reg = <0 0x0ad00000 0 0x10000>; 3103 clocks = <&rpmhcc RPMH_CXO_CLK>, 3104 <&rpmhcc RPMH_CXO_CLK_A>, 3105 <&sleep_clk>; 3106 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3107 #clock-cells = <1>; 3108 #reset-cells = <1>; 3109 #power-domain-cells = <1>; 3110 }; 3111 3112 dispcc: clock-controller@af00000 { 3113 compatible = "qcom,sc7280-dispcc"; 3114 reg = <0 0xaf00000 0 0x20000>; 3115 clocks = <&rpmhcc RPMH_CXO_CLK>, 3116 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3117 <&mdss_dsi_phy 0>, 3118 <&mdss_dsi_phy 1>, 3119 <&dp_phy 0>, 3120 <&dp_phy 1>, 3121 <&mdss_edp_phy 0>, 3122 <&mdss_edp_phy 1>; 3123 clock-names = "bi_tcxo", 3124 "gcc_disp_gpll0_clk", 3125 "dsi0_phy_pll_out_byteclk", 3126 "dsi0_phy_pll_out_dsiclk", 3127 "dp_phy_pll_link_clk", 3128 "dp_phy_pll_vco_div_clk", 3129 "edp_phy_pll_link_clk", 3130 "edp_phy_pll_vco_div_clk"; 3131 #clock-cells = <1>; 3132 #reset-cells = <1>; 3133 #power-domain-cells = <1>; 3134 }; 3135 3136 mdss: display-subsystem@ae00000 { 3137 compatible = "qcom,sc7280-mdss"; 3138 reg = <0 0x0ae00000 0 0x1000>; 3139 reg-names = "mdss"; 3140 3141 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3142 3143 clocks = <&gcc GCC_DISP_AHB_CLK>, 3144 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3145 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3146 clock-names = "iface", 3147 "ahb", 3148 "core"; 3149 3150 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3151 assigned-clock-rates = <300000000>; 3152 3153 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3154 interrupt-controller; 3155 #interrupt-cells = <1>; 3156 3157 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3158 interconnect-names = "mdp0-mem"; 3159 3160 iommus = <&apps_smmu 0x900 0x402>; 3161 3162 #address-cells = <2>; 3163 #size-cells = <2>; 3164 ranges; 3165 3166 status = "disabled"; 3167 3168 mdss_mdp: display-controller@ae01000 { 3169 compatible = "qcom,sc7280-dpu"; 3170 reg = <0 0x0ae01000 0 0x8f030>, 3171 <0 0x0aeb0000 0 0x2008>; 3172 reg-names = "mdp", "vbif"; 3173 3174 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3175 <&gcc GCC_DISP_SF_AXI_CLK>, 3176 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3177 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3178 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3179 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3180 clock-names = "bus", 3181 "nrt_bus", 3182 "iface", 3183 "lut", 3184 "core", 3185 "vsync"; 3186 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3187 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3188 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3189 assigned-clock-rates = <300000000>, 3190 <19200000>, 3191 <19200000>; 3192 operating-points-v2 = <&mdp_opp_table>; 3193 power-domains = <&rpmhpd SC7280_CX>; 3194 3195 interrupt-parent = <&mdss>; 3196 interrupts = <0>; 3197 3198 status = "disabled"; 3199 3200 ports { 3201 #address-cells = <1>; 3202 #size-cells = <0>; 3203 3204 port@0 { 3205 reg = <0>; 3206 dpu_intf1_out: endpoint { 3207 remote-endpoint = <&dsi0_in>; 3208 }; 3209 }; 3210 3211 port@1 { 3212 reg = <1>; 3213 dpu_intf5_out: endpoint { 3214 remote-endpoint = <&edp_in>; 3215 }; 3216 }; 3217 3218 port@2 { 3219 reg = <2>; 3220 dpu_intf0_out: endpoint { 3221 remote-endpoint = <&dp_in>; 3222 }; 3223 }; 3224 }; 3225 3226 mdp_opp_table: opp-table { 3227 compatible = "operating-points-v2"; 3228 3229 opp-200000000 { 3230 opp-hz = /bits/ 64 <200000000>; 3231 required-opps = <&rpmhpd_opp_low_svs>; 3232 }; 3233 3234 opp-300000000 { 3235 opp-hz = /bits/ 64 <300000000>; 3236 required-opps = <&rpmhpd_opp_svs>; 3237 }; 3238 3239 opp-380000000 { 3240 opp-hz = /bits/ 64 <380000000>; 3241 required-opps = <&rpmhpd_opp_svs_l1>; 3242 }; 3243 3244 opp-506666667 { 3245 opp-hz = /bits/ 64 <506666667>; 3246 required-opps = <&rpmhpd_opp_nom>; 3247 }; 3248 }; 3249 }; 3250 3251 mdss_dsi: dsi@ae94000 { 3252 compatible = "qcom,mdss-dsi-ctrl"; 3253 reg = <0 0x0ae94000 0 0x400>; 3254 reg-names = "dsi_ctrl"; 3255 3256 interrupt-parent = <&mdss>; 3257 interrupts = <4>; 3258 3259 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3260 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3261 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3262 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3263 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3264 <&gcc GCC_DISP_HF_AXI_CLK>; 3265 clock-names = "byte", 3266 "byte_intf", 3267 "pixel", 3268 "core", 3269 "iface", 3270 "bus"; 3271 3272 operating-points-v2 = <&dsi_opp_table>; 3273 power-domains = <&rpmhpd SC7280_CX>; 3274 3275 phys = <&mdss_dsi_phy>; 3276 phy-names = "dsi"; 3277 3278 #address-cells = <1>; 3279 #size-cells = <0>; 3280 3281 status = "disabled"; 3282 3283 ports { 3284 #address-cells = <1>; 3285 #size-cells = <0>; 3286 3287 port@0 { 3288 reg = <0>; 3289 dsi0_in: endpoint { 3290 remote-endpoint = <&dpu_intf1_out>; 3291 }; 3292 }; 3293 3294 port@1 { 3295 reg = <1>; 3296 dsi0_out: endpoint { 3297 }; 3298 }; 3299 }; 3300 3301 dsi_opp_table: opp-table { 3302 compatible = "operating-points-v2"; 3303 3304 opp-187500000 { 3305 opp-hz = /bits/ 64 <187500000>; 3306 required-opps = <&rpmhpd_opp_low_svs>; 3307 }; 3308 3309 opp-300000000 { 3310 opp-hz = /bits/ 64 <300000000>; 3311 required-opps = <&rpmhpd_opp_svs>; 3312 }; 3313 3314 opp-358000000 { 3315 opp-hz = /bits/ 64 <358000000>; 3316 required-opps = <&rpmhpd_opp_svs_l1>; 3317 }; 3318 }; 3319 }; 3320 3321 mdss_dsi_phy: phy@ae94400 { 3322 compatible = "qcom,sc7280-dsi-phy-7nm"; 3323 reg = <0 0x0ae94400 0 0x200>, 3324 <0 0x0ae94600 0 0x280>, 3325 <0 0x0ae94900 0 0x280>; 3326 reg-names = "dsi_phy", 3327 "dsi_phy_lane", 3328 "dsi_pll"; 3329 3330 #clock-cells = <1>; 3331 #phy-cells = <0>; 3332 3333 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3334 <&rpmhcc RPMH_CXO_CLK>; 3335 clock-names = "iface", "ref"; 3336 3337 status = "disabled"; 3338 }; 3339 3340 mdss_edp: edp@aea0000 { 3341 compatible = "qcom,sc7280-edp"; 3342 pinctrl-names = "default"; 3343 pinctrl-0 = <&edp_hot_plug_det>; 3344 3345 reg = <0 0xaea0000 0 0x200>, 3346 <0 0xaea0200 0 0x200>, 3347 <0 0xaea0400 0 0xc00>, 3348 <0 0xaea1000 0 0x400>; 3349 3350 interrupt-parent = <&mdss>; 3351 interrupts = <14>; 3352 3353 clocks = <&rpmhcc RPMH_CXO_CLK>, 3354 <&gcc GCC_EDP_CLKREF_EN>, 3355 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3356 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3357 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3358 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3359 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3360 clock-names = "core_xo", 3361 "core_ref", 3362 "core_iface", 3363 "core_aux", 3364 "ctrl_link", 3365 "ctrl_link_iface", 3366 "stream_pixel"; 3367 #clock-cells = <1>; 3368 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3369 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3370 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3371 3372 phys = <&mdss_edp_phy>; 3373 phy-names = "dp"; 3374 3375 operating-points-v2 = <&edp_opp_table>; 3376 power-domains = <&rpmhpd SC7280_CX>; 3377 3378 #address-cells = <1>; 3379 #size-cells = <0>; 3380 3381 status = "disabled"; 3382 3383 ports { 3384 #address-cells = <1>; 3385 #size-cells = <0>; 3386 3387 port@0 { 3388 reg = <0>; 3389 edp_in: endpoint { 3390 remote-endpoint = <&dpu_intf5_out>; 3391 }; 3392 }; 3393 3394 port@1 { 3395 reg = <1>; 3396 mdss_edp_out: endpoint { }; 3397 }; 3398 }; 3399 3400 edp_opp_table: opp-table { 3401 compatible = "operating-points-v2"; 3402 3403 opp-160000000 { 3404 opp-hz = /bits/ 64 <160000000>; 3405 required-opps = <&rpmhpd_opp_low_svs>; 3406 }; 3407 3408 opp-270000000 { 3409 opp-hz = /bits/ 64 <270000000>; 3410 required-opps = <&rpmhpd_opp_svs>; 3411 }; 3412 3413 opp-540000000 { 3414 opp-hz = /bits/ 64 <540000000>; 3415 required-opps = <&rpmhpd_opp_nom>; 3416 }; 3417 3418 opp-810000000 { 3419 opp-hz = /bits/ 64 <810000000>; 3420 required-opps = <&rpmhpd_opp_nom>; 3421 }; 3422 }; 3423 }; 3424 3425 mdss_edp_phy: phy@aec2a00 { 3426 compatible = "qcom,sc7280-edp-phy"; 3427 3428 reg = <0 0xaec2a00 0 0x19c>, 3429 <0 0xaec2200 0 0xa0>, 3430 <0 0xaec2600 0 0xa0>, 3431 <0 0xaec2000 0 0x1c0>; 3432 3433 clocks = <&rpmhcc RPMH_CXO_CLK>, 3434 <&gcc GCC_EDP_CLKREF_EN>; 3435 clock-names = "aux", 3436 "cfg_ahb"; 3437 3438 #clock-cells = <1>; 3439 #phy-cells = <0>; 3440 3441 status = "disabled"; 3442 }; 3443 3444 mdss_dp: displayport-controller@ae90000 { 3445 compatible = "qcom,sc7280-dp"; 3446 3447 reg = <0 0x0ae90000 0 0x1400>; 3448 3449 interrupt-parent = <&mdss>; 3450 interrupts = <12>; 3451 3452 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3453 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3454 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3455 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3456 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3457 clock-names = "core_iface", 3458 "core_aux", 3459 "ctrl_link", 3460 "ctrl_link_iface", 3461 "stream_pixel"; 3462 #clock-cells = <1>; 3463 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3464 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3465 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3466 phys = <&dp_phy>; 3467 phy-names = "dp"; 3468 3469 operating-points-v2 = <&dp_opp_table>; 3470 power-domains = <&rpmhpd SC7280_CX>; 3471 3472 #sound-dai-cells = <0>; 3473 3474 status = "disabled"; 3475 3476 ports { 3477 #address-cells = <1>; 3478 #size-cells = <0>; 3479 3480 port@0 { 3481 reg = <0>; 3482 dp_in: endpoint { 3483 remote-endpoint = <&dpu_intf0_out>; 3484 }; 3485 }; 3486 3487 port@1 { 3488 reg = <1>; 3489 dp_out: endpoint { }; 3490 }; 3491 }; 3492 3493 dp_opp_table: opp-table { 3494 compatible = "operating-points-v2"; 3495 3496 opp-160000000 { 3497 opp-hz = /bits/ 64 <160000000>; 3498 required-opps = <&rpmhpd_opp_low_svs>; 3499 }; 3500 3501 opp-270000000 { 3502 opp-hz = /bits/ 64 <270000000>; 3503 required-opps = <&rpmhpd_opp_svs>; 3504 }; 3505 3506 opp-540000000 { 3507 opp-hz = /bits/ 64 <540000000>; 3508 required-opps = <&rpmhpd_opp_svs_l1>; 3509 }; 3510 3511 opp-810000000 { 3512 opp-hz = /bits/ 64 <810000000>; 3513 required-opps = <&rpmhpd_opp_nom>; 3514 }; 3515 }; 3516 }; 3517 }; 3518 3519 pdc: interrupt-controller@b220000 { 3520 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3521 reg = <0 0x0b220000 0 0x30000>; 3522 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3523 <55 306 4>, <59 312 3>, <62 374 2>, 3524 <64 434 2>, <66 438 3>, <69 86 1>, 3525 <70 520 54>, <124 609 31>, <155 63 1>, 3526 <156 716 12>; 3527 #interrupt-cells = <2>; 3528 interrupt-parent = <&intc>; 3529 interrupt-controller; 3530 }; 3531 3532 pdc_reset: reset-controller@b5e0000 { 3533 compatible = "qcom,sc7280-pdc-global"; 3534 reg = <0 0x0b5e0000 0 0x20000>; 3535 #reset-cells = <1>; 3536 }; 3537 3538 tsens0: thermal-sensor@c263000 { 3539 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3540 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3541 <0 0x0c222000 0 0x1ff>; /* SROT */ 3542 #qcom,sensors = <15>; 3543 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3545 interrupt-names = "uplow","critical"; 3546 #thermal-sensor-cells = <1>; 3547 }; 3548 3549 tsens1: thermal-sensor@c265000 { 3550 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3551 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3552 <0 0x0c223000 0 0x1ff>; /* SROT */ 3553 #qcom,sensors = <12>; 3554 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3556 interrupt-names = "uplow","critical"; 3557 #thermal-sensor-cells = <1>; 3558 }; 3559 3560 aoss_reset: reset-controller@c2a0000 { 3561 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3562 reg = <0 0x0c2a0000 0 0x31000>; 3563 #reset-cells = <1>; 3564 }; 3565 3566 aoss_qmp: power-controller@c300000 { 3567 compatible = "qcom,sc7280-aoss-qmp"; 3568 reg = <0 0x0c300000 0 0x400>; 3569 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3570 IPCC_MPROC_SIGNAL_GLINK_QMP 3571 IRQ_TYPE_EDGE_RISING>; 3572 mboxes = <&ipcc IPCC_CLIENT_AOP 3573 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3574 3575 #clock-cells = <0>; 3576 }; 3577 3578 sram@c3f0000 { 3579 compatible = "qcom,rpmh-stats"; 3580 reg = <0 0x0c3f0000 0 0x400>; 3581 }; 3582 3583 spmi_bus: spmi@c440000 { 3584 compatible = "qcom,spmi-pmic-arb"; 3585 reg = <0 0x0c440000 0 0x1100>, 3586 <0 0x0c600000 0 0x2000000>, 3587 <0 0x0e600000 0 0x100000>, 3588 <0 0x0e700000 0 0xa0000>, 3589 <0 0x0c40a000 0 0x26000>; 3590 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3591 interrupt-names = "periph_irq"; 3592 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3593 qcom,ee = <0>; 3594 qcom,channel = <0>; 3595 #address-cells = <1>; 3596 #size-cells = <1>; 3597 interrupt-controller; 3598 #interrupt-cells = <4>; 3599 }; 3600 3601 tlmm: pinctrl@f100000 { 3602 compatible = "qcom,sc7280-pinctrl"; 3603 reg = <0 0x0f100000 0 0x300000>; 3604 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3605 gpio-controller; 3606 #gpio-cells = <2>; 3607 interrupt-controller; 3608 #interrupt-cells = <2>; 3609 gpio-ranges = <&tlmm 0 0 175>; 3610 wakeup-parent = <&pdc>; 3611 3612 dp_hot_plug_det: dp-hot-plug-det { 3613 pins = "gpio47"; 3614 function = "dp_hot"; 3615 }; 3616 3617 edp_hot_plug_det: edp-hot-plug-det { 3618 pins = "gpio60"; 3619 function = "edp_hot"; 3620 }; 3621 3622 pcie1_clkreq_n: pcie1-clkreq-n { 3623 pins = "gpio79"; 3624 function = "pcie1_clkreqn"; 3625 }; 3626 3627 qspi_clk: qspi-clk { 3628 pins = "gpio14"; 3629 function = "qspi_clk"; 3630 }; 3631 3632 qspi_cs0: qspi-cs0 { 3633 pins = "gpio15"; 3634 function = "qspi_cs"; 3635 }; 3636 3637 qspi_cs1: qspi-cs1 { 3638 pins = "gpio19"; 3639 function = "qspi_cs"; 3640 }; 3641 3642 qspi_data01: qspi-data01 { 3643 pins = "gpio12", "gpio13"; 3644 function = "qspi_data"; 3645 }; 3646 3647 qspi_data12: qspi-data12 { 3648 pins = "gpio16", "gpio17"; 3649 function = "qspi_data"; 3650 }; 3651 3652 qup_i2c0_data_clk: qup-i2c0-data-clk { 3653 pins = "gpio0", "gpio1"; 3654 function = "qup00"; 3655 }; 3656 3657 qup_i2c1_data_clk: qup-i2c1-data-clk { 3658 pins = "gpio4", "gpio5"; 3659 function = "qup01"; 3660 }; 3661 3662 qup_i2c2_data_clk: qup-i2c2-data-clk { 3663 pins = "gpio8", "gpio9"; 3664 function = "qup02"; 3665 }; 3666 3667 qup_i2c3_data_clk: qup-i2c3-data-clk { 3668 pins = "gpio12", "gpio13"; 3669 function = "qup03"; 3670 }; 3671 3672 qup_i2c4_data_clk: qup-i2c4-data-clk { 3673 pins = "gpio16", "gpio17"; 3674 function = "qup04"; 3675 }; 3676 3677 qup_i2c5_data_clk: qup-i2c5-data-clk { 3678 pins = "gpio20", "gpio21"; 3679 function = "qup05"; 3680 }; 3681 3682 qup_i2c6_data_clk: qup-i2c6-data-clk { 3683 pins = "gpio24", "gpio25"; 3684 function = "qup06"; 3685 }; 3686 3687 qup_i2c7_data_clk: qup-i2c7-data-clk { 3688 pins = "gpio28", "gpio29"; 3689 function = "qup07"; 3690 }; 3691 3692 qup_i2c8_data_clk: qup-i2c8-data-clk { 3693 pins = "gpio32", "gpio33"; 3694 function = "qup10"; 3695 }; 3696 3697 qup_i2c9_data_clk: qup-i2c9-data-clk { 3698 pins = "gpio36", "gpio37"; 3699 function = "qup11"; 3700 }; 3701 3702 qup_i2c10_data_clk: qup-i2c10-data-clk { 3703 pins = "gpio40", "gpio41"; 3704 function = "qup12"; 3705 }; 3706 3707 qup_i2c11_data_clk: qup-i2c11-data-clk { 3708 pins = "gpio44", "gpio45"; 3709 function = "qup13"; 3710 }; 3711 3712 qup_i2c12_data_clk: qup-i2c12-data-clk { 3713 pins = "gpio48", "gpio49"; 3714 function = "qup14"; 3715 }; 3716 3717 qup_i2c13_data_clk: qup-i2c13-data-clk { 3718 pins = "gpio52", "gpio53"; 3719 function = "qup15"; 3720 }; 3721 3722 qup_i2c14_data_clk: qup-i2c14-data-clk { 3723 pins = "gpio56", "gpio57"; 3724 function = "qup16"; 3725 }; 3726 3727 qup_i2c15_data_clk: qup-i2c15-data-clk { 3728 pins = "gpio60", "gpio61"; 3729 function = "qup17"; 3730 }; 3731 3732 qup_spi0_data_clk: qup-spi0-data-clk { 3733 pins = "gpio0", "gpio1", "gpio2"; 3734 function = "qup00"; 3735 }; 3736 3737 qup_spi0_cs: qup-spi0-cs { 3738 pins = "gpio3"; 3739 function = "qup00"; 3740 }; 3741 3742 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3743 pins = "gpio3"; 3744 function = "gpio"; 3745 }; 3746 3747 qup_spi1_data_clk: qup-spi1-data-clk { 3748 pins = "gpio4", "gpio5", "gpio6"; 3749 function = "qup01"; 3750 }; 3751 3752 qup_spi1_cs: qup-spi1-cs { 3753 pins = "gpio7"; 3754 function = "qup01"; 3755 }; 3756 3757 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3758 pins = "gpio7"; 3759 function = "gpio"; 3760 }; 3761 3762 qup_spi2_data_clk: qup-spi2-data-clk { 3763 pins = "gpio8", "gpio9", "gpio10"; 3764 function = "qup02"; 3765 }; 3766 3767 qup_spi2_cs: qup-spi2-cs { 3768 pins = "gpio11"; 3769 function = "qup02"; 3770 }; 3771 3772 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3773 pins = "gpio11"; 3774 function = "gpio"; 3775 }; 3776 3777 qup_spi3_data_clk: qup-spi3-data-clk { 3778 pins = "gpio12", "gpio13", "gpio14"; 3779 function = "qup03"; 3780 }; 3781 3782 qup_spi3_cs: qup-spi3-cs { 3783 pins = "gpio15"; 3784 function = "qup03"; 3785 }; 3786 3787 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3788 pins = "gpio15"; 3789 function = "gpio"; 3790 }; 3791 3792 qup_spi4_data_clk: qup-spi4-data-clk { 3793 pins = "gpio16", "gpio17", "gpio18"; 3794 function = "qup04"; 3795 }; 3796 3797 qup_spi4_cs: qup-spi4-cs { 3798 pins = "gpio19"; 3799 function = "qup04"; 3800 }; 3801 3802 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3803 pins = "gpio19"; 3804 function = "gpio"; 3805 }; 3806 3807 qup_spi5_data_clk: qup-spi5-data-clk { 3808 pins = "gpio20", "gpio21", "gpio22"; 3809 function = "qup05"; 3810 }; 3811 3812 qup_spi5_cs: qup-spi5-cs { 3813 pins = "gpio23"; 3814 function = "qup05"; 3815 }; 3816 3817 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3818 pins = "gpio23"; 3819 function = "gpio"; 3820 }; 3821 3822 qup_spi6_data_clk: qup-spi6-data-clk { 3823 pins = "gpio24", "gpio25", "gpio26"; 3824 function = "qup06"; 3825 }; 3826 3827 qup_spi6_cs: qup-spi6-cs { 3828 pins = "gpio27"; 3829 function = "qup06"; 3830 }; 3831 3832 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3833 pins = "gpio27"; 3834 function = "gpio"; 3835 }; 3836 3837 qup_spi7_data_clk: qup-spi7-data-clk { 3838 pins = "gpio28", "gpio29", "gpio30"; 3839 function = "qup07"; 3840 }; 3841 3842 qup_spi7_cs: qup-spi7-cs { 3843 pins = "gpio31"; 3844 function = "qup07"; 3845 }; 3846 3847 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3848 pins = "gpio31"; 3849 function = "gpio"; 3850 }; 3851 3852 qup_spi8_data_clk: qup-spi8-data-clk { 3853 pins = "gpio32", "gpio33", "gpio34"; 3854 function = "qup10"; 3855 }; 3856 3857 qup_spi8_cs: qup-spi8-cs { 3858 pins = "gpio35"; 3859 function = "qup10"; 3860 }; 3861 3862 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3863 pins = "gpio35"; 3864 function = "gpio"; 3865 }; 3866 3867 qup_spi9_data_clk: qup-spi9-data-clk { 3868 pins = "gpio36", "gpio37", "gpio38"; 3869 function = "qup11"; 3870 }; 3871 3872 qup_spi9_cs: qup-spi9-cs { 3873 pins = "gpio39"; 3874 function = "qup11"; 3875 }; 3876 3877 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3878 pins = "gpio39"; 3879 function = "gpio"; 3880 }; 3881 3882 qup_spi10_data_clk: qup-spi10-data-clk { 3883 pins = "gpio40", "gpio41", "gpio42"; 3884 function = "qup12"; 3885 }; 3886 3887 qup_spi10_cs: qup-spi10-cs { 3888 pins = "gpio43"; 3889 function = "qup12"; 3890 }; 3891 3892 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3893 pins = "gpio43"; 3894 function = "gpio"; 3895 }; 3896 3897 qup_spi11_data_clk: qup-spi11-data-clk { 3898 pins = "gpio44", "gpio45", "gpio46"; 3899 function = "qup13"; 3900 }; 3901 3902 qup_spi11_cs: qup-spi11-cs { 3903 pins = "gpio47"; 3904 function = "qup13"; 3905 }; 3906 3907 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3908 pins = "gpio47"; 3909 function = "gpio"; 3910 }; 3911 3912 qup_spi12_data_clk: qup-spi12-data-clk { 3913 pins = "gpio48", "gpio49", "gpio50"; 3914 function = "qup14"; 3915 }; 3916 3917 qup_spi12_cs: qup-spi12-cs { 3918 pins = "gpio51"; 3919 function = "qup14"; 3920 }; 3921 3922 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3923 pins = "gpio51"; 3924 function = "gpio"; 3925 }; 3926 3927 qup_spi13_data_clk: qup-spi13-data-clk { 3928 pins = "gpio52", "gpio53", "gpio54"; 3929 function = "qup15"; 3930 }; 3931 3932 qup_spi13_cs: qup-spi13-cs { 3933 pins = "gpio55"; 3934 function = "qup15"; 3935 }; 3936 3937 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3938 pins = "gpio55"; 3939 function = "gpio"; 3940 }; 3941 3942 qup_spi14_data_clk: qup-spi14-data-clk { 3943 pins = "gpio56", "gpio57", "gpio58"; 3944 function = "qup16"; 3945 }; 3946 3947 qup_spi14_cs: qup-spi14-cs { 3948 pins = "gpio59"; 3949 function = "qup16"; 3950 }; 3951 3952 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3953 pins = "gpio59"; 3954 function = "gpio"; 3955 }; 3956 3957 qup_spi15_data_clk: qup-spi15-data-clk { 3958 pins = "gpio60", "gpio61", "gpio62"; 3959 function = "qup17"; 3960 }; 3961 3962 qup_spi15_cs: qup-spi15-cs { 3963 pins = "gpio63"; 3964 function = "qup17"; 3965 }; 3966 3967 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3968 pins = "gpio63"; 3969 function = "gpio"; 3970 }; 3971 3972 qup_uart0_cts: qup-uart0-cts { 3973 pins = "gpio0"; 3974 function = "qup00"; 3975 }; 3976 3977 qup_uart0_rts: qup-uart0-rts { 3978 pins = "gpio1"; 3979 function = "qup00"; 3980 }; 3981 3982 qup_uart0_tx: qup-uart0-tx { 3983 pins = "gpio2"; 3984 function = "qup00"; 3985 }; 3986 3987 qup_uart0_rx: qup-uart0-rx { 3988 pins = "gpio3"; 3989 function = "qup00"; 3990 }; 3991 3992 qup_uart1_cts: qup-uart1-cts { 3993 pins = "gpio4"; 3994 function = "qup01"; 3995 }; 3996 3997 qup_uart1_rts: qup-uart1-rts { 3998 pins = "gpio5"; 3999 function = "qup01"; 4000 }; 4001 4002 qup_uart1_tx: qup-uart1-tx { 4003 pins = "gpio6"; 4004 function = "qup01"; 4005 }; 4006 4007 qup_uart1_rx: qup-uart1-rx { 4008 pins = "gpio7"; 4009 function = "qup01"; 4010 }; 4011 4012 qup_uart2_cts: qup-uart2-cts { 4013 pins = "gpio8"; 4014 function = "qup02"; 4015 }; 4016 4017 qup_uart2_rts: qup-uart2-rts { 4018 pins = "gpio9"; 4019 function = "qup02"; 4020 }; 4021 4022 qup_uart2_tx: qup-uart2-tx { 4023 pins = "gpio10"; 4024 function = "qup02"; 4025 }; 4026 4027 qup_uart2_rx: qup-uart2-rx { 4028 pins = "gpio11"; 4029 function = "qup02"; 4030 }; 4031 4032 qup_uart3_cts: qup-uart3-cts { 4033 pins = "gpio12"; 4034 function = "qup03"; 4035 }; 4036 4037 qup_uart3_rts: qup-uart3-rts { 4038 pins = "gpio13"; 4039 function = "qup03"; 4040 }; 4041 4042 qup_uart3_tx: qup-uart3-tx { 4043 pins = "gpio14"; 4044 function = "qup03"; 4045 }; 4046 4047 qup_uart3_rx: qup-uart3-rx { 4048 pins = "gpio15"; 4049 function = "qup03"; 4050 }; 4051 4052 qup_uart4_cts: qup-uart4-cts { 4053 pins = "gpio16"; 4054 function = "qup04"; 4055 }; 4056 4057 qup_uart4_rts: qup-uart4-rts { 4058 pins = "gpio17"; 4059 function = "qup04"; 4060 }; 4061 4062 qup_uart4_tx: qup-uart4-tx { 4063 pins = "gpio18"; 4064 function = "qup04"; 4065 }; 4066 4067 qup_uart4_rx: qup-uart4-rx { 4068 pins = "gpio19"; 4069 function = "qup04"; 4070 }; 4071 4072 qup_uart5_cts: qup-uart5-cts { 4073 pins = "gpio20"; 4074 function = "qup05"; 4075 }; 4076 4077 qup_uart5_rts: qup-uart5-rts { 4078 pins = "gpio21"; 4079 function = "qup05"; 4080 }; 4081 4082 qup_uart5_tx: qup-uart5-tx { 4083 pins = "gpio22"; 4084 function = "qup05"; 4085 }; 4086 4087 qup_uart5_rx: qup-uart5-rx { 4088 pins = "gpio23"; 4089 function = "qup05"; 4090 }; 4091 4092 qup_uart6_cts: qup-uart6-cts { 4093 pins = "gpio24"; 4094 function = "qup06"; 4095 }; 4096 4097 qup_uart6_rts: qup-uart6-rts { 4098 pins = "gpio25"; 4099 function = "qup06"; 4100 }; 4101 4102 qup_uart6_tx: qup-uart6-tx { 4103 pins = "gpio26"; 4104 function = "qup06"; 4105 }; 4106 4107 qup_uart6_rx: qup-uart6-rx { 4108 pins = "gpio27"; 4109 function = "qup06"; 4110 }; 4111 4112 qup_uart7_cts: qup-uart7-cts { 4113 pins = "gpio28"; 4114 function = "qup07"; 4115 }; 4116 4117 qup_uart7_rts: qup-uart7-rts { 4118 pins = "gpio29"; 4119 function = "qup07"; 4120 }; 4121 4122 qup_uart7_tx: qup-uart7-tx { 4123 pins = "gpio30"; 4124 function = "qup07"; 4125 }; 4126 4127 qup_uart7_rx: qup-uart7-rx { 4128 pins = "gpio31"; 4129 function = "qup07"; 4130 }; 4131 4132 qup_uart8_cts: qup-uart8-cts { 4133 pins = "gpio32"; 4134 function = "qup10"; 4135 }; 4136 4137 qup_uart8_rts: qup-uart8-rts { 4138 pins = "gpio33"; 4139 function = "qup10"; 4140 }; 4141 4142 qup_uart8_tx: qup-uart8-tx { 4143 pins = "gpio34"; 4144 function = "qup10"; 4145 }; 4146 4147 qup_uart8_rx: qup-uart8-rx { 4148 pins = "gpio35"; 4149 function = "qup10"; 4150 }; 4151 4152 qup_uart9_cts: qup-uart9-cts { 4153 pins = "gpio36"; 4154 function = "qup11"; 4155 }; 4156 4157 qup_uart9_rts: qup-uart9-rts { 4158 pins = "gpio37"; 4159 function = "qup11"; 4160 }; 4161 4162 qup_uart9_tx: qup-uart9-tx { 4163 pins = "gpio38"; 4164 function = "qup11"; 4165 }; 4166 4167 qup_uart9_rx: qup-uart9-rx { 4168 pins = "gpio39"; 4169 function = "qup11"; 4170 }; 4171 4172 qup_uart10_cts: qup-uart10-cts { 4173 pins = "gpio40"; 4174 function = "qup12"; 4175 }; 4176 4177 qup_uart10_rts: qup-uart10-rts { 4178 pins = "gpio41"; 4179 function = "qup12"; 4180 }; 4181 4182 qup_uart10_tx: qup-uart10-tx { 4183 pins = "gpio42"; 4184 function = "qup12"; 4185 }; 4186 4187 qup_uart10_rx: qup-uart10-rx { 4188 pins = "gpio43"; 4189 function = "qup12"; 4190 }; 4191 4192 qup_uart11_cts: qup-uart11-cts { 4193 pins = "gpio44"; 4194 function = "qup13"; 4195 }; 4196 4197 qup_uart11_rts: qup-uart11-rts { 4198 pins = "gpio45"; 4199 function = "qup13"; 4200 }; 4201 4202 qup_uart11_tx: qup-uart11-tx { 4203 pins = "gpio46"; 4204 function = "qup13"; 4205 }; 4206 4207 qup_uart11_rx: qup-uart11-rx { 4208 pins = "gpio47"; 4209 function = "qup13"; 4210 }; 4211 4212 qup_uart12_cts: qup-uart12-cts { 4213 pins = "gpio48"; 4214 function = "qup14"; 4215 }; 4216 4217 qup_uart12_rts: qup-uart12-rts { 4218 pins = "gpio49"; 4219 function = "qup14"; 4220 }; 4221 4222 qup_uart12_tx: qup-uart12-tx { 4223 pins = "gpio50"; 4224 function = "qup14"; 4225 }; 4226 4227 qup_uart12_rx: qup-uart12-rx { 4228 pins = "gpio51"; 4229 function = "qup14"; 4230 }; 4231 4232 qup_uart13_cts: qup-uart13-cts { 4233 pins = "gpio52"; 4234 function = "qup15"; 4235 }; 4236 4237 qup_uart13_rts: qup-uart13-rts { 4238 pins = "gpio53"; 4239 function = "qup15"; 4240 }; 4241 4242 qup_uart13_tx: qup-uart13-tx { 4243 pins = "gpio54"; 4244 function = "qup15"; 4245 }; 4246 4247 qup_uart13_rx: qup-uart13-rx { 4248 pins = "gpio55"; 4249 function = "qup15"; 4250 }; 4251 4252 qup_uart14_cts: qup-uart14-cts { 4253 pins = "gpio56"; 4254 function = "qup16"; 4255 }; 4256 4257 qup_uart14_rts: qup-uart14-rts { 4258 pins = "gpio57"; 4259 function = "qup16"; 4260 }; 4261 4262 qup_uart14_tx: qup-uart14-tx { 4263 pins = "gpio58"; 4264 function = "qup16"; 4265 }; 4266 4267 qup_uart14_rx: qup-uart14-rx { 4268 pins = "gpio59"; 4269 function = "qup16"; 4270 }; 4271 4272 qup_uart15_cts: qup-uart15-cts { 4273 pins = "gpio60"; 4274 function = "qup17"; 4275 }; 4276 4277 qup_uart15_rts: qup-uart15-rts { 4278 pins = "gpio61"; 4279 function = "qup17"; 4280 }; 4281 4282 qup_uart15_tx: qup-uart15-tx { 4283 pins = "gpio62"; 4284 function = "qup17"; 4285 }; 4286 4287 qup_uart15_rx: qup-uart15-rx { 4288 pins = "gpio63"; 4289 function = "qup17"; 4290 }; 4291 4292 sdc1_clk: sdc1-clk { 4293 pins = "sdc1_clk"; 4294 }; 4295 4296 sdc1_cmd: sdc1-cmd { 4297 pins = "sdc1_cmd"; 4298 }; 4299 4300 sdc1_data: sdc1-data { 4301 pins = "sdc1_data"; 4302 }; 4303 4304 sdc1_rclk: sdc1-rclk { 4305 pins = "sdc1_rclk"; 4306 }; 4307 4308 sdc1_clk_sleep: sdc1-clk-sleep { 4309 pins = "sdc1_clk"; 4310 drive-strength = <2>; 4311 bias-bus-hold; 4312 }; 4313 4314 sdc1_cmd_sleep: sdc1-cmd-sleep { 4315 pins = "sdc1_cmd"; 4316 drive-strength = <2>; 4317 bias-bus-hold; 4318 }; 4319 4320 sdc1_data_sleep: sdc1-data-sleep { 4321 pins = "sdc1_data"; 4322 drive-strength = <2>; 4323 bias-bus-hold; 4324 }; 4325 4326 sdc1_rclk_sleep: sdc1-rclk-sleep { 4327 pins = "sdc1_rclk"; 4328 drive-strength = <2>; 4329 bias-bus-hold; 4330 }; 4331 4332 sdc2_clk: sdc2-clk { 4333 pins = "sdc2_clk"; 4334 }; 4335 4336 sdc2_cmd: sdc2-cmd { 4337 pins = "sdc2_cmd"; 4338 }; 4339 4340 sdc2_data: sdc2-data { 4341 pins = "sdc2_data"; 4342 }; 4343 4344 sdc2_clk_sleep: sdc2-clk-sleep { 4345 pins = "sdc2_clk"; 4346 drive-strength = <2>; 4347 bias-bus-hold; 4348 }; 4349 4350 sdc2_cmd_sleep: sdc2-cmd-sleep { 4351 pins = "sdc2_cmd"; 4352 drive-strength = <2>; 4353 bias-bus-hold; 4354 }; 4355 4356 sdc2_data_sleep: sdc2-data-sleep { 4357 pins = "sdc2_data"; 4358 drive-strength = <2>; 4359 bias-bus-hold; 4360 }; 4361 }; 4362 4363 imem@146a5000 { 4364 compatible = "qcom,sc7280-imem", "syscon"; 4365 reg = <0 0x146a5000 0 0x6000>; 4366 4367 #address-cells = <1>; 4368 #size-cells = <1>; 4369 4370 ranges = <0 0 0x146a5000 0x6000>; 4371 4372 pil-reloc@594c { 4373 compatible = "qcom,pil-reloc-info"; 4374 reg = <0x594c 0xc8>; 4375 }; 4376 }; 4377 4378 apps_smmu: iommu@15000000 { 4379 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4380 reg = <0 0x15000000 0 0x100000>; 4381 #iommu-cells = <2>; 4382 #global-interrupts = <1>; 4383 dma-coherent; 4384 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4399 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4409 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4410 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4411 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4412 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4413 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4414 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4415 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4416 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4417 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4418 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4419 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4420 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4421 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4422 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4423 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4424 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4425 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4426 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4427 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4428 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4429 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4430 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4431 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4432 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4433 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4434 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4435 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4436 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4437 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4438 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4440 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4441 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4442 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4443 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4444 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4445 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4446 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4447 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4448 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4449 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4450 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4451 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4452 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4453 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4454 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4455 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4456 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4457 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4458 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4459 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4460 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4461 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4462 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4463 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4464 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4465 }; 4466 4467 intc: interrupt-controller@17a00000 { 4468 compatible = "arm,gic-v3"; 4469 #address-cells = <2>; 4470 #size-cells = <2>; 4471 ranges; 4472 #interrupt-cells = <3>; 4473 interrupt-controller; 4474 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4475 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4476 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4477 4478 gic-its@17a40000 { 4479 compatible = "arm,gic-v3-its"; 4480 msi-controller; 4481 #msi-cells = <1>; 4482 reg = <0 0x17a40000 0 0x20000>; 4483 status = "disabled"; 4484 }; 4485 }; 4486 4487 watchdog@17c10000 { 4488 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4489 reg = <0 0x17c10000 0 0x1000>; 4490 clocks = <&sleep_clk>; 4491 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4492 }; 4493 4494 timer@17c20000 { 4495 #address-cells = <2>; 4496 #size-cells = <2>; 4497 ranges; 4498 compatible = "arm,armv7-timer-mem"; 4499 reg = <0 0x17c20000 0 0x1000>; 4500 4501 frame@17c21000 { 4502 frame-number = <0>; 4503 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4504 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4505 reg = <0 0x17c21000 0 0x1000>, 4506 <0 0x17c22000 0 0x1000>; 4507 }; 4508 4509 frame@17c23000 { 4510 frame-number = <1>; 4511 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4512 reg = <0 0x17c23000 0 0x1000>; 4513 status = "disabled"; 4514 }; 4515 4516 frame@17c25000 { 4517 frame-number = <2>; 4518 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4519 reg = <0 0x17c25000 0 0x1000>; 4520 status = "disabled"; 4521 }; 4522 4523 frame@17c27000 { 4524 frame-number = <3>; 4525 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4526 reg = <0 0x17c27000 0 0x1000>; 4527 status = "disabled"; 4528 }; 4529 4530 frame@17c29000 { 4531 frame-number = <4>; 4532 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4533 reg = <0 0x17c29000 0 0x1000>; 4534 status = "disabled"; 4535 }; 4536 4537 frame@17c2b000 { 4538 frame-number = <5>; 4539 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4540 reg = <0 0x17c2b000 0 0x1000>; 4541 status = "disabled"; 4542 }; 4543 4544 frame@17c2d000 { 4545 frame-number = <6>; 4546 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4547 reg = <0 0x17c2d000 0 0x1000>; 4548 status = "disabled"; 4549 }; 4550 }; 4551 4552 apps_rsc: rsc@18200000 { 4553 compatible = "qcom,rpmh-rsc"; 4554 reg = <0 0x18200000 0 0x10000>, 4555 <0 0x18210000 0 0x10000>, 4556 <0 0x18220000 0 0x10000>; 4557 reg-names = "drv-0", "drv-1", "drv-2"; 4558 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4559 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4560 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4561 qcom,tcs-offset = <0xd00>; 4562 qcom,drv-id = <2>; 4563 qcom,tcs-config = <ACTIVE_TCS 2>, 4564 <SLEEP_TCS 3>, 4565 <WAKE_TCS 3>, 4566 <CONTROL_TCS 1>; 4567 4568 apps_bcm_voter: bcm-voter { 4569 compatible = "qcom,bcm-voter"; 4570 }; 4571 4572 rpmhpd: power-controller { 4573 compatible = "qcom,sc7280-rpmhpd"; 4574 #power-domain-cells = <1>; 4575 operating-points-v2 = <&rpmhpd_opp_table>; 4576 4577 rpmhpd_opp_table: opp-table { 4578 compatible = "operating-points-v2"; 4579 4580 rpmhpd_opp_ret: opp1 { 4581 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4582 }; 4583 4584 rpmhpd_opp_low_svs: opp2 { 4585 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4586 }; 4587 4588 rpmhpd_opp_svs: opp3 { 4589 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4590 }; 4591 4592 rpmhpd_opp_svs_l1: opp4 { 4593 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4594 }; 4595 4596 rpmhpd_opp_svs_l2: opp5 { 4597 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4598 }; 4599 4600 rpmhpd_opp_nom: opp6 { 4601 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4602 }; 4603 4604 rpmhpd_opp_nom_l1: opp7 { 4605 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4606 }; 4607 4608 rpmhpd_opp_turbo: opp8 { 4609 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4610 }; 4611 4612 rpmhpd_opp_turbo_l1: opp9 { 4613 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4614 }; 4615 }; 4616 }; 4617 4618 rpmhcc: clock-controller { 4619 compatible = "qcom,sc7280-rpmh-clk"; 4620 clocks = <&xo_board>; 4621 clock-names = "xo"; 4622 #clock-cells = <1>; 4623 }; 4624 }; 4625 4626 epss_l3: interconnect@18590000 { 4627 compatible = "qcom,sc7280-epss-l3"; 4628 reg = <0 0x18590000 0 0x1000>; 4629 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4630 clock-names = "xo", "alternate"; 4631 #interconnect-cells = <1>; 4632 }; 4633 4634 cpufreq_hw: cpufreq@18591000 { 4635 compatible = "qcom,cpufreq-epss"; 4636 reg = <0 0x18591000 0 0x1000>, 4637 <0 0x18592000 0 0x1000>, 4638 <0 0x18593000 0 0x1000>; 4639 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4640 clock-names = "xo", "alternate"; 4641 #freq-domain-cells = <1>; 4642 }; 4643 }; 4644 4645 thermal_zones: thermal-zones { 4646 cpu0-thermal { 4647 polling-delay-passive = <250>; 4648 polling-delay = <0>; 4649 4650 thermal-sensors = <&tsens0 1>; 4651 4652 trips { 4653 cpu0_alert0: trip-point0 { 4654 temperature = <90000>; 4655 hysteresis = <2000>; 4656 type = "passive"; 4657 }; 4658 4659 cpu0_alert1: trip-point1 { 4660 temperature = <95000>; 4661 hysteresis = <2000>; 4662 type = "passive"; 4663 }; 4664 4665 cpu0_crit: cpu-crit { 4666 temperature = <110000>; 4667 hysteresis = <0>; 4668 type = "critical"; 4669 }; 4670 }; 4671 4672 cooling-maps { 4673 map0 { 4674 trip = <&cpu0_alert0>; 4675 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4677 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4678 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4679 }; 4680 map1 { 4681 trip = <&cpu0_alert1>; 4682 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4684 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4686 }; 4687 }; 4688 }; 4689 4690 cpu1-thermal { 4691 polling-delay-passive = <250>; 4692 polling-delay = <0>; 4693 4694 thermal-sensors = <&tsens0 2>; 4695 4696 trips { 4697 cpu1_alert0: trip-point0 { 4698 temperature = <90000>; 4699 hysteresis = <2000>; 4700 type = "passive"; 4701 }; 4702 4703 cpu1_alert1: trip-point1 { 4704 temperature = <95000>; 4705 hysteresis = <2000>; 4706 type = "passive"; 4707 }; 4708 4709 cpu1_crit: cpu-crit { 4710 temperature = <110000>; 4711 hysteresis = <0>; 4712 type = "critical"; 4713 }; 4714 }; 4715 4716 cooling-maps { 4717 map0 { 4718 trip = <&cpu1_alert0>; 4719 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4720 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4721 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4722 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4723 }; 4724 map1 { 4725 trip = <&cpu1_alert1>; 4726 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4727 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4728 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4729 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4730 }; 4731 }; 4732 }; 4733 4734 cpu2-thermal { 4735 polling-delay-passive = <250>; 4736 polling-delay = <0>; 4737 4738 thermal-sensors = <&tsens0 3>; 4739 4740 trips { 4741 cpu2_alert0: trip-point0 { 4742 temperature = <90000>; 4743 hysteresis = <2000>; 4744 type = "passive"; 4745 }; 4746 4747 cpu2_alert1: trip-point1 { 4748 temperature = <95000>; 4749 hysteresis = <2000>; 4750 type = "passive"; 4751 }; 4752 4753 cpu2_crit: cpu-crit { 4754 temperature = <110000>; 4755 hysteresis = <0>; 4756 type = "critical"; 4757 }; 4758 }; 4759 4760 cooling-maps { 4761 map0 { 4762 trip = <&cpu2_alert0>; 4763 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4764 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4766 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4767 }; 4768 map1 { 4769 trip = <&cpu2_alert1>; 4770 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4772 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4773 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4774 }; 4775 }; 4776 }; 4777 4778 cpu3-thermal { 4779 polling-delay-passive = <250>; 4780 polling-delay = <0>; 4781 4782 thermal-sensors = <&tsens0 4>; 4783 4784 trips { 4785 cpu3_alert0: trip-point0 { 4786 temperature = <90000>; 4787 hysteresis = <2000>; 4788 type = "passive"; 4789 }; 4790 4791 cpu3_alert1: trip-point1 { 4792 temperature = <95000>; 4793 hysteresis = <2000>; 4794 type = "passive"; 4795 }; 4796 4797 cpu3_crit: cpu-crit { 4798 temperature = <110000>; 4799 hysteresis = <0>; 4800 type = "critical"; 4801 }; 4802 }; 4803 4804 cooling-maps { 4805 map0 { 4806 trip = <&cpu3_alert0>; 4807 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4808 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4809 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4810 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4811 }; 4812 map1 { 4813 trip = <&cpu3_alert1>; 4814 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4817 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4818 }; 4819 }; 4820 }; 4821 4822 cpu4-thermal { 4823 polling-delay-passive = <250>; 4824 polling-delay = <0>; 4825 4826 thermal-sensors = <&tsens0 7>; 4827 4828 trips { 4829 cpu4_alert0: trip-point0 { 4830 temperature = <90000>; 4831 hysteresis = <2000>; 4832 type = "passive"; 4833 }; 4834 4835 cpu4_alert1: trip-point1 { 4836 temperature = <95000>; 4837 hysteresis = <2000>; 4838 type = "passive"; 4839 }; 4840 4841 cpu4_crit: cpu-crit { 4842 temperature = <110000>; 4843 hysteresis = <0>; 4844 type = "critical"; 4845 }; 4846 }; 4847 4848 cooling-maps { 4849 map0 { 4850 trip = <&cpu4_alert0>; 4851 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4852 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4853 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4855 }; 4856 map1 { 4857 trip = <&cpu4_alert1>; 4858 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4859 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4860 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4861 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4862 }; 4863 }; 4864 }; 4865 4866 cpu5-thermal { 4867 polling-delay-passive = <250>; 4868 polling-delay = <0>; 4869 4870 thermal-sensors = <&tsens0 8>; 4871 4872 trips { 4873 cpu5_alert0: trip-point0 { 4874 temperature = <90000>; 4875 hysteresis = <2000>; 4876 type = "passive"; 4877 }; 4878 4879 cpu5_alert1: trip-point1 { 4880 temperature = <95000>; 4881 hysteresis = <2000>; 4882 type = "passive"; 4883 }; 4884 4885 cpu5_crit: cpu-crit { 4886 temperature = <110000>; 4887 hysteresis = <0>; 4888 type = "critical"; 4889 }; 4890 }; 4891 4892 cooling-maps { 4893 map0 { 4894 trip = <&cpu5_alert0>; 4895 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4897 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4898 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4899 }; 4900 map1 { 4901 trip = <&cpu5_alert1>; 4902 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4903 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4904 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4905 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4906 }; 4907 }; 4908 }; 4909 4910 cpu6-thermal { 4911 polling-delay-passive = <250>; 4912 polling-delay = <0>; 4913 4914 thermal-sensors = <&tsens0 9>; 4915 4916 trips { 4917 cpu6_alert0: trip-point0 { 4918 temperature = <90000>; 4919 hysteresis = <2000>; 4920 type = "passive"; 4921 }; 4922 4923 cpu6_alert1: trip-point1 { 4924 temperature = <95000>; 4925 hysteresis = <2000>; 4926 type = "passive"; 4927 }; 4928 4929 cpu6_crit: cpu-crit { 4930 temperature = <110000>; 4931 hysteresis = <0>; 4932 type = "critical"; 4933 }; 4934 }; 4935 4936 cooling-maps { 4937 map0 { 4938 trip = <&cpu6_alert0>; 4939 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4940 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4941 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4942 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4943 }; 4944 map1 { 4945 trip = <&cpu6_alert1>; 4946 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4947 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4948 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4949 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4950 }; 4951 }; 4952 }; 4953 4954 cpu7-thermal { 4955 polling-delay-passive = <250>; 4956 polling-delay = <0>; 4957 4958 thermal-sensors = <&tsens0 10>; 4959 4960 trips { 4961 cpu7_alert0: trip-point0 { 4962 temperature = <90000>; 4963 hysteresis = <2000>; 4964 type = "passive"; 4965 }; 4966 4967 cpu7_alert1: trip-point1 { 4968 temperature = <95000>; 4969 hysteresis = <2000>; 4970 type = "passive"; 4971 }; 4972 4973 cpu7_crit: cpu-crit { 4974 temperature = <110000>; 4975 hysteresis = <0>; 4976 type = "critical"; 4977 }; 4978 }; 4979 4980 cooling-maps { 4981 map0 { 4982 trip = <&cpu7_alert0>; 4983 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4984 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4985 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4986 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4987 }; 4988 map1 { 4989 trip = <&cpu7_alert1>; 4990 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4991 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4992 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4993 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4994 }; 4995 }; 4996 }; 4997 4998 cpu8-thermal { 4999 polling-delay-passive = <250>; 5000 polling-delay = <0>; 5001 5002 thermal-sensors = <&tsens0 11>; 5003 5004 trips { 5005 cpu8_alert0: trip-point0 { 5006 temperature = <90000>; 5007 hysteresis = <2000>; 5008 type = "passive"; 5009 }; 5010 5011 cpu8_alert1: trip-point1 { 5012 temperature = <95000>; 5013 hysteresis = <2000>; 5014 type = "passive"; 5015 }; 5016 5017 cpu8_crit: cpu-crit { 5018 temperature = <110000>; 5019 hysteresis = <0>; 5020 type = "critical"; 5021 }; 5022 }; 5023 5024 cooling-maps { 5025 map0 { 5026 trip = <&cpu8_alert0>; 5027 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5028 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5029 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5030 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5031 }; 5032 map1 { 5033 trip = <&cpu8_alert1>; 5034 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5035 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5036 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5037 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5038 }; 5039 }; 5040 }; 5041 5042 cpu9-thermal { 5043 polling-delay-passive = <250>; 5044 polling-delay = <0>; 5045 5046 thermal-sensors = <&tsens0 12>; 5047 5048 trips { 5049 cpu9_alert0: trip-point0 { 5050 temperature = <90000>; 5051 hysteresis = <2000>; 5052 type = "passive"; 5053 }; 5054 5055 cpu9_alert1: trip-point1 { 5056 temperature = <95000>; 5057 hysteresis = <2000>; 5058 type = "passive"; 5059 }; 5060 5061 cpu9_crit: cpu-crit { 5062 temperature = <110000>; 5063 hysteresis = <0>; 5064 type = "critical"; 5065 }; 5066 }; 5067 5068 cooling-maps { 5069 map0 { 5070 trip = <&cpu9_alert0>; 5071 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5072 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5073 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5074 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5075 }; 5076 map1 { 5077 trip = <&cpu9_alert1>; 5078 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5079 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5080 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5082 }; 5083 }; 5084 }; 5085 5086 cpu10-thermal { 5087 polling-delay-passive = <250>; 5088 polling-delay = <0>; 5089 5090 thermal-sensors = <&tsens0 13>; 5091 5092 trips { 5093 cpu10_alert0: trip-point0 { 5094 temperature = <90000>; 5095 hysteresis = <2000>; 5096 type = "passive"; 5097 }; 5098 5099 cpu10_alert1: trip-point1 { 5100 temperature = <95000>; 5101 hysteresis = <2000>; 5102 type = "passive"; 5103 }; 5104 5105 cpu10_crit: cpu-crit { 5106 temperature = <110000>; 5107 hysteresis = <0>; 5108 type = "critical"; 5109 }; 5110 }; 5111 5112 cooling-maps { 5113 map0 { 5114 trip = <&cpu10_alert0>; 5115 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5116 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5117 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5118 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5119 }; 5120 map1 { 5121 trip = <&cpu10_alert1>; 5122 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5123 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5124 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5125 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5126 }; 5127 }; 5128 }; 5129 5130 cpu11-thermal { 5131 polling-delay-passive = <250>; 5132 polling-delay = <0>; 5133 5134 thermal-sensors = <&tsens0 14>; 5135 5136 trips { 5137 cpu11_alert0: trip-point0 { 5138 temperature = <90000>; 5139 hysteresis = <2000>; 5140 type = "passive"; 5141 }; 5142 5143 cpu11_alert1: trip-point1 { 5144 temperature = <95000>; 5145 hysteresis = <2000>; 5146 type = "passive"; 5147 }; 5148 5149 cpu11_crit: cpu-crit { 5150 temperature = <110000>; 5151 hysteresis = <0>; 5152 type = "critical"; 5153 }; 5154 }; 5155 5156 cooling-maps { 5157 map0 { 5158 trip = <&cpu11_alert0>; 5159 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5160 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5161 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5162 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5163 }; 5164 map1 { 5165 trip = <&cpu11_alert1>; 5166 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5167 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5168 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5169 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5170 }; 5171 }; 5172 }; 5173 5174 aoss0-thermal { 5175 polling-delay-passive = <0>; 5176 polling-delay = <0>; 5177 5178 thermal-sensors = <&tsens0 0>; 5179 5180 trips { 5181 aoss0_alert0: trip-point0 { 5182 temperature = <90000>; 5183 hysteresis = <2000>; 5184 type = "hot"; 5185 }; 5186 5187 aoss0_crit: aoss0-crit { 5188 temperature = <110000>; 5189 hysteresis = <0>; 5190 type = "critical"; 5191 }; 5192 }; 5193 }; 5194 5195 aoss1-thermal { 5196 polling-delay-passive = <0>; 5197 polling-delay = <0>; 5198 5199 thermal-sensors = <&tsens1 0>; 5200 5201 trips { 5202 aoss1_alert0: trip-point0 { 5203 temperature = <90000>; 5204 hysteresis = <2000>; 5205 type = "hot"; 5206 }; 5207 5208 aoss1_crit: aoss1-crit { 5209 temperature = <110000>; 5210 hysteresis = <0>; 5211 type = "critical"; 5212 }; 5213 }; 5214 }; 5215 5216 cpuss0-thermal { 5217 polling-delay-passive = <0>; 5218 polling-delay = <0>; 5219 5220 thermal-sensors = <&tsens0 5>; 5221 5222 trips { 5223 cpuss0_alert0: trip-point0 { 5224 temperature = <90000>; 5225 hysteresis = <2000>; 5226 type = "hot"; 5227 }; 5228 cpuss0_crit: cluster0-crit { 5229 temperature = <110000>; 5230 hysteresis = <0>; 5231 type = "critical"; 5232 }; 5233 }; 5234 }; 5235 5236 cpuss1-thermal { 5237 polling-delay-passive = <0>; 5238 polling-delay = <0>; 5239 5240 thermal-sensors = <&tsens0 6>; 5241 5242 trips { 5243 cpuss1_alert0: trip-point0 { 5244 temperature = <90000>; 5245 hysteresis = <2000>; 5246 type = "hot"; 5247 }; 5248 cpuss1_crit: cluster0-crit { 5249 temperature = <110000>; 5250 hysteresis = <0>; 5251 type = "critical"; 5252 }; 5253 }; 5254 }; 5255 5256 gpuss0-thermal { 5257 polling-delay-passive = <100>; 5258 polling-delay = <0>; 5259 5260 thermal-sensors = <&tsens1 1>; 5261 5262 trips { 5263 gpuss0_alert0: trip-point0 { 5264 temperature = <95000>; 5265 hysteresis = <2000>; 5266 type = "passive"; 5267 }; 5268 5269 gpuss0_crit: gpuss0-crit { 5270 temperature = <110000>; 5271 hysteresis = <0>; 5272 type = "critical"; 5273 }; 5274 }; 5275 5276 cooling-maps { 5277 map0 { 5278 trip = <&gpuss0_alert0>; 5279 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5280 }; 5281 }; 5282 }; 5283 5284 gpuss1-thermal { 5285 polling-delay-passive = <100>; 5286 polling-delay = <0>; 5287 5288 thermal-sensors = <&tsens1 2>; 5289 5290 trips { 5291 gpuss1_alert0: trip-point0 { 5292 temperature = <95000>; 5293 hysteresis = <2000>; 5294 type = "passive"; 5295 }; 5296 5297 gpuss1_crit: gpuss1-crit { 5298 temperature = <110000>; 5299 hysteresis = <0>; 5300 type = "critical"; 5301 }; 5302 }; 5303 5304 cooling-maps { 5305 map0 { 5306 trip = <&gpuss1_alert0>; 5307 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5308 }; 5309 }; 5310 }; 5311 5312 nspss0-thermal { 5313 polling-delay-passive = <0>; 5314 polling-delay = <0>; 5315 5316 thermal-sensors = <&tsens1 3>; 5317 5318 trips { 5319 nspss0_alert0: trip-point0 { 5320 temperature = <90000>; 5321 hysteresis = <2000>; 5322 type = "hot"; 5323 }; 5324 5325 nspss0_crit: nspss0-crit { 5326 temperature = <110000>; 5327 hysteresis = <0>; 5328 type = "critical"; 5329 }; 5330 }; 5331 }; 5332 5333 nspss1-thermal { 5334 polling-delay-passive = <0>; 5335 polling-delay = <0>; 5336 5337 thermal-sensors = <&tsens1 4>; 5338 5339 trips { 5340 nspss1_alert0: trip-point0 { 5341 temperature = <90000>; 5342 hysteresis = <2000>; 5343 type = "hot"; 5344 }; 5345 5346 nspss1_crit: nspss1-crit { 5347 temperature = <110000>; 5348 hysteresis = <0>; 5349 type = "critical"; 5350 }; 5351 }; 5352 }; 5353 5354 video-thermal { 5355 polling-delay-passive = <0>; 5356 polling-delay = <0>; 5357 5358 thermal-sensors = <&tsens1 5>; 5359 5360 trips { 5361 video_alert0: trip-point0 { 5362 temperature = <90000>; 5363 hysteresis = <2000>; 5364 type = "hot"; 5365 }; 5366 5367 video_crit: video-crit { 5368 temperature = <110000>; 5369 hysteresis = <0>; 5370 type = "critical"; 5371 }; 5372 }; 5373 }; 5374 5375 ddr-thermal { 5376 polling-delay-passive = <0>; 5377 polling-delay = <0>; 5378 5379 thermal-sensors = <&tsens1 6>; 5380 5381 trips { 5382 ddr_alert0: trip-point0 { 5383 temperature = <90000>; 5384 hysteresis = <2000>; 5385 type = "hot"; 5386 }; 5387 5388 ddr_crit: ddr-crit { 5389 temperature = <110000>; 5390 hysteresis = <0>; 5391 type = "critical"; 5392 }; 5393 }; 5394 }; 5395 5396 mdmss0-thermal { 5397 polling-delay-passive = <0>; 5398 polling-delay = <0>; 5399 5400 thermal-sensors = <&tsens1 7>; 5401 5402 trips { 5403 mdmss0_alert0: trip-point0 { 5404 temperature = <90000>; 5405 hysteresis = <2000>; 5406 type = "hot"; 5407 }; 5408 5409 mdmss0_crit: mdmss0-crit { 5410 temperature = <110000>; 5411 hysteresis = <0>; 5412 type = "critical"; 5413 }; 5414 }; 5415 }; 5416 5417 mdmss1-thermal { 5418 polling-delay-passive = <0>; 5419 polling-delay = <0>; 5420 5421 thermal-sensors = <&tsens1 8>; 5422 5423 trips { 5424 mdmss1_alert0: trip-point0 { 5425 temperature = <90000>; 5426 hysteresis = <2000>; 5427 type = "hot"; 5428 }; 5429 5430 mdmss1_crit: mdmss1-crit { 5431 temperature = <110000>; 5432 hysteresis = <0>; 5433 type = "critical"; 5434 }; 5435 }; 5436 }; 5437 5438 mdmss2-thermal { 5439 polling-delay-passive = <0>; 5440 polling-delay = <0>; 5441 5442 thermal-sensors = <&tsens1 9>; 5443 5444 trips { 5445 mdmss2_alert0: trip-point0 { 5446 temperature = <90000>; 5447 hysteresis = <2000>; 5448 type = "hot"; 5449 }; 5450 5451 mdmss2_crit: mdmss2-crit { 5452 temperature = <110000>; 5453 hysteresis = <0>; 5454 type = "critical"; 5455 }; 5456 }; 5457 }; 5458 5459 mdmss3-thermal { 5460 polling-delay-passive = <0>; 5461 polling-delay = <0>; 5462 5463 thermal-sensors = <&tsens1 10>; 5464 5465 trips { 5466 mdmss3_alert0: trip-point0 { 5467 temperature = <90000>; 5468 hysteresis = <2000>; 5469 type = "hot"; 5470 }; 5471 5472 mdmss3_crit: mdmss3-crit { 5473 temperature = <110000>; 5474 hysteresis = <0>; 5475 type = "critical"; 5476 }; 5477 }; 5478 }; 5479 5480 camera0-thermal { 5481 polling-delay-passive = <0>; 5482 polling-delay = <0>; 5483 5484 thermal-sensors = <&tsens1 11>; 5485 5486 trips { 5487 camera0_alert0: trip-point0 { 5488 temperature = <90000>; 5489 hysteresis = <2000>; 5490 type = "hot"; 5491 }; 5492 5493 camera0_crit: camera0-crit { 5494 temperature = <110000>; 5495 hysteresis = <0>; 5496 type = "critical"; 5497 }; 5498 }; 5499 }; 5500 }; 5501 5502 timer { 5503 compatible = "arm,armv8-timer"; 5504 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5505 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5506 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5507 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5508 }; 5509}; 5510