1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 ipa_fw_mem: memory@8b700000 { 133 reg = <0 0x8b700000 0 0x10000>; 134 no-map; 135 }; 136 137 rmtfs_mem: memory@9c900000 { 138 compatible = "qcom,rmtfs-mem"; 139 reg = <0x0 0x9c900000 0x0 0x280000>; 140 no-map; 141 142 qcom,client-id = <1>; 143 qcom,vmid = <15>; 144 }; 145 }; 146 147 cpus { 148 #address-cells = <2>; 149 #size-cells = <0>; 150 151 CPU0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,kryo"; 154 reg = <0x0 0x0>; 155 enable-method = "psci"; 156 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 157 &LITTLE_CPU_SLEEP_1 158 &CLUSTER_SLEEP_0>; 159 next-level-cache = <&L2_0>; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 #cooling-cells = <2>; 162 L2_0: l2-cache { 163 compatible = "cache"; 164 next-level-cache = <&L3_0>; 165 L3_0: l3-cache { 166 compatible = "cache"; 167 }; 168 }; 169 }; 170 171 CPU1: cpu@100 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x100>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_100>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_100: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU2: cpu@200 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x200>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_200>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 #cooling-cells = <2>; 199 L2_200: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU3: cpu@300 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x300>; 209 enable-method = "psci"; 210 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 211 &LITTLE_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_300>; 214 qcom,freq-domain = <&cpufreq_hw 0>; 215 #cooling-cells = <2>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "arm,kryo"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&BIG_CPU_SLEEP_0 228 &BIG_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 next-level-cache = <&L2_400>; 231 qcom,freq-domain = <&cpufreq_hw 1>; 232 #cooling-cells = <2>; 233 L2_400: l2-cache { 234 compatible = "cache"; 235 next-level-cache = <&L3_0>; 236 }; 237 }; 238 239 CPU5: cpu@500 { 240 device_type = "cpu"; 241 compatible = "arm,kryo"; 242 reg = <0x0 0x500>; 243 enable-method = "psci"; 244 cpu-idle-states = <&BIG_CPU_SLEEP_0 245 &BIG_CPU_SLEEP_1 246 &CLUSTER_SLEEP_0>; 247 next-level-cache = <&L2_500>; 248 qcom,freq-domain = <&cpufreq_hw 1>; 249 #cooling-cells = <2>; 250 L2_500: l2-cache { 251 compatible = "cache"; 252 next-level-cache = <&L3_0>; 253 }; 254 }; 255 256 CPU6: cpu@600 { 257 device_type = "cpu"; 258 compatible = "arm,kryo"; 259 reg = <0x0 0x600>; 260 enable-method = "psci"; 261 cpu-idle-states = <&BIG_CPU_SLEEP_0 262 &BIG_CPU_SLEEP_1 263 &CLUSTER_SLEEP_0>; 264 next-level-cache = <&L2_600>; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 #cooling-cells = <2>; 267 L2_600: l2-cache { 268 compatible = "cache"; 269 next-level-cache = <&L3_0>; 270 }; 271 }; 272 273 CPU7: cpu@700 { 274 device_type = "cpu"; 275 compatible = "arm,kryo"; 276 reg = <0x0 0x700>; 277 enable-method = "psci"; 278 cpu-idle-states = <&BIG_CPU_SLEEP_0 279 &BIG_CPU_SLEEP_1 280 &CLUSTER_SLEEP_0>; 281 next-level-cache = <&L2_700>; 282 qcom,freq-domain = <&cpufreq_hw 2>; 283 #cooling-cells = <2>; 284 L2_700: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 cpu-map { 291 cluster0 { 292 core0 { 293 cpu = <&CPU0>; 294 }; 295 296 core1 { 297 cpu = <&CPU1>; 298 }; 299 300 core2 { 301 cpu = <&CPU2>; 302 }; 303 304 core3 { 305 cpu = <&CPU3>; 306 }; 307 308 core4 { 309 cpu = <&CPU4>; 310 }; 311 312 core5 { 313 cpu = <&CPU5>; 314 }; 315 316 core6 { 317 cpu = <&CPU6>; 318 }; 319 320 core7 { 321 cpu = <&CPU7>; 322 }; 323 }; 324 }; 325 326 idle-states { 327 entry-method = "psci"; 328 329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-power-down"; 332 arm,psci-suspend-param = <0x40000003>; 333 entry-latency-us = <549>; 334 exit-latency-us = <901>; 335 min-residency-us = <1774>; 336 local-timer-stop; 337 }; 338 339 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "little-rail-power-down"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <702>; 344 exit-latency-us = <915>; 345 min-residency-us = <4001>; 346 local-timer-stop; 347 }; 348 349 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "big-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <523>; 354 exit-latency-us = <1244>; 355 min-residency-us = <2207>; 356 local-timer-stop; 357 }; 358 359 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "big-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <526>; 364 exit-latency-us = <1854>; 365 min-residency-us = <5555>; 366 local-timer-stop; 367 }; 368 369 CLUSTER_SLEEP_0: cluster-sleep-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "cluster-power-down"; 372 arm,psci-suspend-param = <0x40003444>; 373 entry-latency-us = <3263>; 374 exit-latency-us = <6562>; 375 min-residency-us = <9926>; 376 local-timer-stop; 377 }; 378 }; 379 }; 380 381 memory@80000000 { 382 device_type = "memory"; 383 /* We expect the bootloader to fill in the size */ 384 reg = <0 0x80000000 0 0>; 385 }; 386 387 firmware { 388 scm { 389 compatible = "qcom,scm-sc7280", "qcom,scm"; 390 }; 391 }; 392 393 clk_virt: interconnect { 394 compatible = "qcom,sc7280-clk-virt"; 395 #interconnect-cells = <2>; 396 qcom,bcm-voters = <&apps_bcm_voter>; 397 }; 398 399 smem { 400 compatible = "qcom,smem"; 401 memory-region = <&smem_mem>; 402 hwlocks = <&tcsr_mutex 3>; 403 }; 404 405 smp2p-adsp { 406 compatible = "qcom,smp2p"; 407 qcom,smem = <443>, <429>; 408 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 409 IPCC_MPROC_SIGNAL_SMP2P 410 IRQ_TYPE_EDGE_RISING>; 411 mboxes = <&ipcc IPCC_CLIENT_LPASS 412 IPCC_MPROC_SIGNAL_SMP2P>; 413 414 qcom,local-pid = <0>; 415 qcom,remote-pid = <2>; 416 417 adsp_smp2p_out: master-kernel { 418 qcom,entry-name = "master-kernel"; 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 adsp_smp2p_in: slave-kernel { 423 qcom,entry-name = "slave-kernel"; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 }; 428 429 smp2p-cdsp { 430 compatible = "qcom,smp2p"; 431 qcom,smem = <94>, <432>; 432 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 433 IPCC_MPROC_SIGNAL_SMP2P 434 IRQ_TYPE_EDGE_RISING>; 435 mboxes = <&ipcc IPCC_CLIENT_CDSP 436 IPCC_MPROC_SIGNAL_SMP2P>; 437 438 qcom,local-pid = <0>; 439 qcom,remote-pid = <5>; 440 441 cdsp_smp2p_out: master-kernel { 442 qcom,entry-name = "master-kernel"; 443 #qcom,smem-state-cells = <1>; 444 }; 445 446 cdsp_smp2p_in: slave-kernel { 447 qcom,entry-name = "slave-kernel"; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 }; 451 }; 452 453 smp2p-mpss { 454 compatible = "qcom,smp2p"; 455 qcom,smem = <435>, <428>; 456 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 457 IPCC_MPROC_SIGNAL_SMP2P 458 IRQ_TYPE_EDGE_RISING>; 459 mboxes = <&ipcc IPCC_CLIENT_MPSS 460 IPCC_MPROC_SIGNAL_SMP2P>; 461 462 qcom,local-pid = <0>; 463 qcom,remote-pid = <1>; 464 465 modem_smp2p_out: master-kernel { 466 qcom,entry-name = "master-kernel"; 467 #qcom,smem-state-cells = <1>; 468 }; 469 470 modem_smp2p_in: slave-kernel { 471 qcom,entry-name = "slave-kernel"; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 }; 475 476 ipa_smp2p_out: ipa-ap-to-modem { 477 qcom,entry-name = "ipa"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 ipa_smp2p_in: ipa-modem-to-ap { 482 qcom,entry-name = "ipa"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 smp2p-wpss { 489 compatible = "qcom,smp2p"; 490 qcom,smem = <617>, <616>; 491 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 492 IPCC_MPROC_SIGNAL_SMP2P 493 IRQ_TYPE_EDGE_RISING>; 494 mboxes = <&ipcc IPCC_CLIENT_WPSS 495 IPCC_MPROC_SIGNAL_SMP2P>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <13>; 499 500 wpss_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 wpss_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 pmu { 513 compatible = "arm,armv8-pmuv3"; 514 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 515 }; 516 517 psci { 518 compatible = "arm,psci-1.0"; 519 method = "smc"; 520 }; 521 522 qspi_opp_table: qspi-opp-table { 523 compatible = "operating-points-v2"; 524 525 opp-75000000 { 526 opp-hz = /bits/ 64 <75000000>; 527 required-opps = <&rpmhpd_opp_low_svs>; 528 }; 529 530 opp-150000000 { 531 opp-hz = /bits/ 64 <150000000>; 532 required-opps = <&rpmhpd_opp_svs>; 533 }; 534 535 opp-300000000 { 536 opp-hz = /bits/ 64 <300000000>; 537 required-opps = <&rpmhpd_opp_nom>; 538 }; 539 }; 540 541 qup_opp_table: qup-opp-table { 542 compatible = "operating-points-v2"; 543 544 opp-75000000 { 545 opp-hz = /bits/ 64 <75000000>; 546 required-opps = <&rpmhpd_opp_low_svs>; 547 }; 548 549 opp-100000000 { 550 opp-hz = /bits/ 64 <100000000>; 551 required-opps = <&rpmhpd_opp_svs>; 552 }; 553 554 opp-128000000 { 555 opp-hz = /bits/ 64 <128000000>; 556 required-opps = <&rpmhpd_opp_nom>; 557 }; 558 }; 559 560 soc: soc@0 { 561 #address-cells = <2>; 562 #size-cells = <2>; 563 ranges = <0 0 0 0 0x10 0>; 564 dma-ranges = <0 0 0 0 0x10 0>; 565 compatible = "simple-bus"; 566 567 gcc: clock-controller@100000 { 568 compatible = "qcom,gcc-sc7280"; 569 reg = <0 0x00100000 0 0x1f0000>; 570 clocks = <&rpmhcc RPMH_CXO_CLK>, 571 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 572 <0>, <0>, <0>, <0>, <0>, <0>; 573 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 574 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 575 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 576 "ufs_phy_tx_symbol_0_clk", 577 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 578 #clock-cells = <1>; 579 #reset-cells = <1>; 580 #power-domain-cells = <1>; 581 }; 582 583 ipcc: mailbox@408000 { 584 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 585 reg = <0 0x00408000 0 0x1000>; 586 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-controller; 588 #interrupt-cells = <3>; 589 #mbox-cells = <2>; 590 }; 591 592 qfprom: efuse@784000 { 593 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 594 reg = <0 0x00784000 0 0xa20>, 595 <0 0x00780000 0 0xa20>, 596 <0 0x00782000 0 0x120>, 597 <0 0x00786000 0 0x1fff>; 598 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 599 clock-names = "core"; 600 power-domains = <&rpmhpd SC7280_MX>; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 }; 604 605 sdhc_1: sdhci@7c4000 { 606 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 607 status = "disabled"; 608 609 reg = <0 0x007c4000 0 0x1000>, 610 <0 0x007c5000 0 0x1000>; 611 reg-names = "hc", "cqhci"; 612 613 iommus = <&apps_smmu 0xc0 0x0>; 614 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 616 interrupt-names = "hc_irq", "pwr_irq"; 617 618 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 619 <&gcc GCC_SDCC1_AHB_CLK>, 620 <&rpmhcc RPMH_CXO_CLK>; 621 clock-names = "core", "iface", "xo"; 622 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 624 interconnect-names = "sdhc-ddr","cpu-sdhc"; 625 power-domains = <&rpmhpd SC7280_CX>; 626 operating-points-v2 = <&sdhc1_opp_table>; 627 628 bus-width = <8>; 629 supports-cqe; 630 631 qcom,dll-config = <0x0007642c>; 632 qcom,ddr-config = <0x80040868>; 633 634 mmc-ddr-1_8v; 635 mmc-hs200-1_8v; 636 mmc-hs400-1_8v; 637 mmc-hs400-enhanced-strobe; 638 639 sdhc1_opp_table: opp-table { 640 compatible = "operating-points-v2"; 641 642 opp-100000000 { 643 opp-hz = /bits/ 64 <100000000>; 644 required-opps = <&rpmhpd_opp_low_svs>; 645 opp-peak-kBps = <1800000 400000>; 646 opp-avg-kBps = <100000 0>; 647 }; 648 649 opp-384000000 { 650 opp-hz = /bits/ 64 <384000000>; 651 required-opps = <&rpmhpd_opp_nom>; 652 opp-peak-kBps = <5400000 1600000>; 653 opp-avg-kBps = <390000 0>; 654 }; 655 }; 656 657 }; 658 659 qupv3_id_0: geniqup@9c0000 { 660 compatible = "qcom,geni-se-qup"; 661 reg = <0 0x009c0000 0 0x2000>; 662 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 663 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 664 clock-names = "m-ahb", "s-ahb"; 665 #address-cells = <2>; 666 #size-cells = <2>; 667 ranges; 668 iommus = <&apps_smmu 0x123 0x0>; 669 status = "disabled"; 670 671 i2c0: i2c@980000 { 672 compatible = "qcom,geni-i2c"; 673 reg = <0 0x00980000 0 0x4000>; 674 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 675 clock-names = "se"; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&qup_i2c0_data_clk>; 678 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 683 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 684 interconnect-names = "qup-core", "qup-config", 685 "qup-memory"; 686 status = "disabled"; 687 }; 688 689 spi0: spi@980000 { 690 compatible = "qcom,geni-spi"; 691 reg = <0 0x00980000 0 0x4000>; 692 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 693 clock-names = "se"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 696 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 power-domains = <&rpmhpd SC7280_CX>; 700 operating-points-v2 = <&qup_opp_table>; 701 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 702 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 703 interconnect-names = "qup-core", "qup-config"; 704 status = "disabled"; 705 }; 706 707 uart0: serial@980000 { 708 compatible = "qcom,geni-uart"; 709 reg = <0 0x00980000 0 0x4000>; 710 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 711 clock-names = "se"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 714 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 715 power-domains = <&rpmhpd SC7280_CX>; 716 operating-points-v2 = <&qup_opp_table>; 717 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 719 interconnect-names = "qup-core", "qup-config"; 720 status = "disabled"; 721 }; 722 723 i2c1: i2c@984000 { 724 compatible = "qcom,geni-i2c"; 725 reg = <0 0x00984000 0 0x4000>; 726 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 727 clock-names = "se"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&qup_i2c1_data_clk>; 730 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 735 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 736 interconnect-names = "qup-core", "qup-config", 737 "qup-memory"; 738 status = "disabled"; 739 }; 740 741 spi1: spi@984000 { 742 compatible = "qcom,geni-spi"; 743 reg = <0 0x00984000 0 0x4000>; 744 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 745 clock-names = "se"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 748 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 power-domains = <&rpmhpd SC7280_CX>; 752 operating-points-v2 = <&qup_opp_table>; 753 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 755 interconnect-names = "qup-core", "qup-config"; 756 status = "disabled"; 757 }; 758 759 uart1: serial@984000 { 760 compatible = "qcom,geni-uart"; 761 reg = <0 0x00984000 0 0x4000>; 762 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 763 clock-names = "se"; 764 pinctrl-names = "default"; 765 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 766 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 767 power-domains = <&rpmhpd SC7280_CX>; 768 operating-points-v2 = <&qup_opp_table>; 769 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 770 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 771 interconnect-names = "qup-core", "qup-config"; 772 status = "disabled"; 773 }; 774 775 i2c2: i2c@988000 { 776 compatible = "qcom,geni-i2c"; 777 reg = <0 0x00988000 0 0x4000>; 778 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 779 clock-names = "se"; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&qup_i2c2_data_clk>; 782 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 786 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 787 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 788 interconnect-names = "qup-core", "qup-config", 789 "qup-memory"; 790 status = "disabled"; 791 }; 792 793 spi2: spi@988000 { 794 compatible = "qcom,geni-spi"; 795 reg = <0 0x00988000 0 0x4000>; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 797 clock-names = "se"; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 800 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 power-domains = <&rpmhpd SC7280_CX>; 804 operating-points-v2 = <&qup_opp_table>; 805 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 807 interconnect-names = "qup-core", "qup-config"; 808 status = "disabled"; 809 }; 810 811 uart2: serial@988000 { 812 compatible = "qcom,geni-uart"; 813 reg = <0 0x00988000 0 0x4000>; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 815 clock-names = "se"; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 818 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 819 power-domains = <&rpmhpd SC7280_CX>; 820 operating-points-v2 = <&qup_opp_table>; 821 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 822 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 823 interconnect-names = "qup-core", "qup-config"; 824 status = "disabled"; 825 }; 826 827 i2c3: i2c@98c000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x0098c000 0 0x4000>; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 831 clock-names = "se"; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c3_data_clk>; 834 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 839 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 840 interconnect-names = "qup-core", "qup-config", 841 "qup-memory"; 842 status = "disabled"; 843 }; 844 845 spi3: spi@98c000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0 0x0098c000 0 0x4000>; 848 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 849 clock-names = "se"; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 852 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 power-domains = <&rpmhpd SC7280_CX>; 856 operating-points-v2 = <&qup_opp_table>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 858 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 859 interconnect-names = "qup-core", "qup-config"; 860 status = "disabled"; 861 }; 862 863 uart3: serial@98c000 { 864 compatible = "qcom,geni-uart"; 865 reg = <0 0x0098c000 0 0x4000>; 866 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 867 clock-names = "se"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 870 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 871 power-domains = <&rpmhpd SC7280_CX>; 872 operating-points-v2 = <&qup_opp_table>; 873 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 874 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 875 interconnect-names = "qup-core", "qup-config"; 876 status = "disabled"; 877 }; 878 879 i2c4: i2c@990000 { 880 compatible = "qcom,geni-i2c"; 881 reg = <0 0x00990000 0 0x4000>; 882 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 883 clock-names = "se"; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&qup_i2c4_data_clk>; 886 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 890 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 891 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 892 interconnect-names = "qup-core", "qup-config", 893 "qup-memory"; 894 status = "disabled"; 895 }; 896 897 spi4: spi@990000 { 898 compatible = "qcom,geni-spi"; 899 reg = <0 0x00990000 0 0x4000>; 900 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 901 clock-names = "se"; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 904 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 power-domains = <&rpmhpd SC7280_CX>; 908 operating-points-v2 = <&qup_opp_table>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 910 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 911 interconnect-names = "qup-core", "qup-config"; 912 status = "disabled"; 913 }; 914 915 uart4: serial@990000 { 916 compatible = "qcom,geni-uart"; 917 reg = <0 0x00990000 0 0x4000>; 918 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 919 clock-names = "se"; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 922 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&qup_opp_table>; 925 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 926 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 927 interconnect-names = "qup-core", "qup-config"; 928 status = "disabled"; 929 }; 930 931 i2c5: i2c@994000 { 932 compatible = "qcom,geni-i2c"; 933 reg = <0 0x00994000 0 0x4000>; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 935 clock-names = "se"; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_i2c5_data_clk>; 938 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 943 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 944 interconnect-names = "qup-core", "qup-config", 945 "qup-memory"; 946 status = "disabled"; 947 }; 948 949 spi5: spi@994000 { 950 compatible = "qcom,geni-spi"; 951 reg = <0 0x00994000 0 0x4000>; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 953 clock-names = "se"; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 956 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 power-domains = <&rpmhpd SC7280_CX>; 960 operating-points-v2 = <&qup_opp_table>; 961 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 962 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 963 interconnect-names = "qup-core", "qup-config"; 964 status = "disabled"; 965 }; 966 967 uart5: serial@994000 { 968 compatible = "qcom,geni-uart"; 969 reg = <0 0x00994000 0 0x4000>; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 971 clock-names = "se"; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 974 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 975 power-domains = <&rpmhpd SC7280_CX>; 976 operating-points-v2 = <&qup_opp_table>; 977 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 978 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 979 interconnect-names = "qup-core", "qup-config"; 980 status = "disabled"; 981 }; 982 983 i2c6: i2c@998000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0 0x00998000 0 0x4000>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 987 clock-names = "se"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c6_data_clk>; 990 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 995 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 996 interconnect-names = "qup-core", "qup-config", 997 "qup-memory"; 998 status = "disabled"; 999 }; 1000 1001 spi6: spi@998000 { 1002 compatible = "qcom,geni-spi"; 1003 reg = <0 0x00998000 0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1005 clock-names = "se"; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1008 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 power-domains = <&rpmhpd SC7280_CX>; 1012 operating-points-v2 = <&qup_opp_table>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1015 interconnect-names = "qup-core", "qup-config"; 1016 status = "disabled"; 1017 }; 1018 1019 uart6: serial@998000 { 1020 compatible = "qcom,geni-uart"; 1021 reg = <0 0x00998000 0 0x4000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1023 clock-names = "se"; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1026 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&rpmhpd SC7280_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 status = "disabled"; 1033 }; 1034 1035 i2c7: i2c@99c000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x0099c000 0 0x4000>; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1039 clock-names = "se"; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c7_data_clk>; 1042 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1047 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", 1049 "qup-memory"; 1050 status = "disabled"; 1051 }; 1052 1053 spi7: spi@99c000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0 0x0099c000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1060 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 power-domains = <&rpmhpd SC7280_CX>; 1064 operating-points-v2 = <&qup_opp_table>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1066 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 status = "disabled"; 1069 }; 1070 1071 uart7: serial@99c000 { 1072 compatible = "qcom,geni-uart"; 1073 reg = <0 0x0099c000 0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1075 clock-names = "se"; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1078 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1079 power-domains = <&rpmhpd SC7280_CX>; 1080 operating-points-v2 = <&qup_opp_table>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1082 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1083 interconnect-names = "qup-core", "qup-config"; 1084 status = "disabled"; 1085 }; 1086 }; 1087 1088 qupv3_id_1: geniqup@ac0000 { 1089 compatible = "qcom,geni-se-qup"; 1090 reg = <0 0x00ac0000 0 0x2000>; 1091 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1092 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1093 clock-names = "m-ahb", "s-ahb"; 1094 #address-cells = <2>; 1095 #size-cells = <2>; 1096 ranges; 1097 iommus = <&apps_smmu 0x43 0x0>; 1098 status = "disabled"; 1099 1100 i2c8: i2c@a80000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0 0x00a80000 0 0x4000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1104 clock-names = "se"; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c8_data_clk>; 1107 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1111 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1112 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1113 interconnect-names = "qup-core", "qup-config", 1114 "qup-memory"; 1115 status = "disabled"; 1116 }; 1117 1118 spi8: spi@a80000 { 1119 compatible = "qcom,geni-spi"; 1120 reg = <0 0x00a80000 0 0x4000>; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 clock-names = "se"; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1125 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 operating-points-v2 = <&qup_opp_table>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1132 interconnect-names = "qup-core", "qup-config"; 1133 status = "disabled"; 1134 }; 1135 1136 uart8: serial@a80000 { 1137 compatible = "qcom,geni-uart"; 1138 reg = <0 0x00a80000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1143 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1144 power-domains = <&rpmhpd SC7280_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1148 interconnect-names = "qup-core", "qup-config"; 1149 status = "disabled"; 1150 }; 1151 1152 i2c9: i2c@a84000 { 1153 compatible = "qcom,geni-i2c"; 1154 reg = <0 0x00a84000 0 0x4000>; 1155 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1156 clock-names = "se"; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_i2c9_data_clk>; 1159 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1164 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", 1166 "qup-memory"; 1167 status = "disabled"; 1168 }; 1169 1170 spi9: spi@a84000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0 0x00a84000 0 0x4000>; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1174 clock-names = "se"; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1177 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 power-domains = <&rpmhpd SC7280_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1184 interconnect-names = "qup-core", "qup-config"; 1185 status = "disabled"; 1186 }; 1187 1188 uart9: serial@a84000 { 1189 compatible = "qcom,geni-uart"; 1190 reg = <0 0x00a84000 0 0x4000>; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1192 clock-names = "se"; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1195 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1196 power-domains = <&rpmhpd SC7280_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1200 interconnect-names = "qup-core", "qup-config"; 1201 status = "disabled"; 1202 }; 1203 1204 i2c10: i2c@a88000 { 1205 compatible = "qcom,geni-i2c"; 1206 reg = <0 0x00a88000 0 0x4000>; 1207 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1208 clock-names = "se"; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_i2c10_data_clk>; 1211 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1216 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1217 interconnect-names = "qup-core", "qup-config", 1218 "qup-memory"; 1219 status = "disabled"; 1220 }; 1221 1222 spi10: spi@a88000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0 0x00a88000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1226 clock-names = "se"; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1229 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 power-domains = <&rpmhpd SC7280_CX>; 1233 operating-points-v2 = <&qup_opp_table>; 1234 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1235 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 status = "disabled"; 1238 }; 1239 1240 uart10: serial@a88000 { 1241 compatible = "qcom,geni-uart"; 1242 reg = <0 0x00a88000 0 0x4000>; 1243 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1244 clock-names = "se"; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1247 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 operating-points-v2 = <&qup_opp_table>; 1250 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1251 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1252 interconnect-names = "qup-core", "qup-config"; 1253 status = "disabled"; 1254 }; 1255 1256 i2c11: i2c@a8c000 { 1257 compatible = "qcom,geni-i2c"; 1258 reg = <0 0x00a8c000 0 0x4000>; 1259 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1260 clock-names = "se"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_i2c11_data_clk>; 1263 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1267 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1268 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1269 interconnect-names = "qup-core", "qup-config", 1270 "qup-memory"; 1271 status = "disabled"; 1272 }; 1273 1274 spi11: spi@a8c000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1278 clock-names = "se"; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 power-domains = <&rpmhpd SC7280_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1288 interconnect-names = "qup-core", "qup-config"; 1289 status = "disabled"; 1290 }; 1291 1292 uart11: serial@a8c000 { 1293 compatible = "qcom,geni-uart"; 1294 reg = <0 0x00a8c000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1296 clock-names = "se"; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1299 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1300 power-domains = <&rpmhpd SC7280_CX>; 1301 operating-points-v2 = <&qup_opp_table>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1304 interconnect-names = "qup-core", "qup-config"; 1305 status = "disabled"; 1306 }; 1307 1308 i2c12: i2c@a90000 { 1309 compatible = "qcom,geni-i2c"; 1310 reg = <0 0x00a90000 0 0x4000>; 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1312 clock-names = "se"; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&qup_i2c12_data_clk>; 1315 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1319 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1320 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1321 interconnect-names = "qup-core", "qup-config", 1322 "qup-memory"; 1323 status = "disabled"; 1324 }; 1325 1326 spi12: spi@a90000 { 1327 compatible = "qcom,geni-spi"; 1328 reg = <0 0x00a90000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 power-domains = <&rpmhpd SC7280_CX>; 1337 operating-points-v2 = <&qup_opp_table>; 1338 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1339 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 status = "disabled"; 1342 }; 1343 1344 uart12: serial@a90000 { 1345 compatible = "qcom,geni-uart"; 1346 reg = <0 0x00a90000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1348 clock-names = "se"; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1351 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1352 power-domains = <&rpmhpd SC7280_CX>; 1353 operating-points-v2 = <&qup_opp_table>; 1354 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1355 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1356 interconnect-names = "qup-core", "qup-config"; 1357 status = "disabled"; 1358 }; 1359 1360 i2c13: i2c@a94000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x00a94000 0 0x4000>; 1363 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1364 clock-names = "se"; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c13_data_clk>; 1367 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1372 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", 1374 "qup-memory"; 1375 status = "disabled"; 1376 }; 1377 1378 spi13: spi@a94000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0 0x00a94000 0 0x4000>; 1381 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1382 clock-names = "se"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1385 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 power-domains = <&rpmhpd SC7280_CX>; 1389 operating-points-v2 = <&qup_opp_table>; 1390 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1391 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1392 interconnect-names = "qup-core", "qup-config"; 1393 status = "disabled"; 1394 }; 1395 1396 uart13: serial@a94000 { 1397 compatible = "qcom,geni-uart"; 1398 reg = <0 0x00a94000 0 0x4000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1400 clock-names = "se"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1403 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1404 power-domains = <&rpmhpd SC7280_CX>; 1405 operating-points-v2 = <&qup_opp_table>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1407 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1408 interconnect-names = "qup-core", "qup-config"; 1409 status = "disabled"; 1410 }; 1411 1412 i2c14: i2c@a98000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00a98000 0 0x4000>; 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1416 clock-names = "se"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c14_data_clk>; 1419 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1424 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1425 interconnect-names = "qup-core", "qup-config", 1426 "qup-memory"; 1427 status = "disabled"; 1428 }; 1429 1430 spi14: spi@a98000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00a98000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1437 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 power-domains = <&rpmhpd SC7280_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1443 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 uart14: serial@a98000 { 1449 compatible = "qcom,geni-uart"; 1450 reg = <0 0x00a98000 0 0x4000>; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1452 clock-names = "se"; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1455 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1456 power-domains = <&rpmhpd SC7280_CX>; 1457 operating-points-v2 = <&qup_opp_table>; 1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1459 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1460 interconnect-names = "qup-core", "qup-config"; 1461 status = "disabled"; 1462 }; 1463 1464 i2c15: i2c@a9c000 { 1465 compatible = "qcom,geni-i2c"; 1466 reg = <0 0x00a9c000 0 0x4000>; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1468 clock-names = "se"; 1469 pinctrl-names = "default"; 1470 pinctrl-0 = <&qup_i2c15_data_clk>; 1471 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1475 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1476 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1477 interconnect-names = "qup-core", "qup-config", 1478 "qup-memory"; 1479 status = "disabled"; 1480 }; 1481 1482 spi15: spi@a9c000 { 1483 compatible = "qcom,geni-spi"; 1484 reg = <0 0x00a9c000 0 0x4000>; 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1486 clock-names = "se"; 1487 pinctrl-names = "default"; 1488 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1489 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 power-domains = <&rpmhpd SC7280_CX>; 1493 operating-points-v2 = <&qup_opp_table>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1495 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1496 interconnect-names = "qup-core", "qup-config"; 1497 status = "disabled"; 1498 }; 1499 1500 uart15: serial@a9c000 { 1501 compatible = "qcom,geni-uart"; 1502 reg = <0 0x00a9c000 0 0x4000>; 1503 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1504 clock-names = "se"; 1505 pinctrl-names = "default"; 1506 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1507 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1508 power-domains = <&rpmhpd SC7280_CX>; 1509 operating-points-v2 = <&qup_opp_table>; 1510 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1511 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1512 interconnect-names = "qup-core", "qup-config"; 1513 status = "disabled"; 1514 }; 1515 }; 1516 1517 cnoc2: interconnect@1500000 { 1518 reg = <0 0x01500000 0 0x1000>; 1519 compatible = "qcom,sc7280-cnoc2"; 1520 #interconnect-cells = <2>; 1521 qcom,bcm-voters = <&apps_bcm_voter>; 1522 }; 1523 1524 cnoc3: interconnect@1502000 { 1525 reg = <0 0x01502000 0 0x1000>; 1526 compatible = "qcom,sc7280-cnoc3"; 1527 #interconnect-cells = <2>; 1528 qcom,bcm-voters = <&apps_bcm_voter>; 1529 }; 1530 1531 mc_virt: interconnect@1580000 { 1532 reg = <0 0x01580000 0 0x4>; 1533 compatible = "qcom,sc7280-mc-virt"; 1534 #interconnect-cells = <2>; 1535 qcom,bcm-voters = <&apps_bcm_voter>; 1536 }; 1537 1538 system_noc: interconnect@1680000 { 1539 reg = <0 0x01680000 0 0x15480>; 1540 compatible = "qcom,sc7280-system-noc"; 1541 #interconnect-cells = <2>; 1542 qcom,bcm-voters = <&apps_bcm_voter>; 1543 }; 1544 1545 aggre1_noc: interconnect@16e0000 { 1546 compatible = "qcom,sc7280-aggre1-noc"; 1547 reg = <0 0x016e0000 0 0x1c080>; 1548 #interconnect-cells = <2>; 1549 qcom,bcm-voters = <&apps_bcm_voter>; 1550 }; 1551 1552 aggre2_noc: interconnect@1700000 { 1553 reg = <0 0x01700000 0 0x2b080>; 1554 compatible = "qcom,sc7280-aggre2-noc"; 1555 #interconnect-cells = <2>; 1556 qcom,bcm-voters = <&apps_bcm_voter>; 1557 }; 1558 1559 mmss_noc: interconnect@1740000 { 1560 reg = <0 0x01740000 0 0x1e080>; 1561 compatible = "qcom,sc7280-mmss-noc"; 1562 #interconnect-cells = <2>; 1563 qcom,bcm-voters = <&apps_bcm_voter>; 1564 }; 1565 1566 ipa: ipa@1e40000 { 1567 compatible = "qcom,sc7280-ipa"; 1568 1569 iommus = <&apps_smmu 0x480 0x0>, 1570 <&apps_smmu 0x482 0x0>; 1571 reg = <0 0x1e40000 0 0x8000>, 1572 <0 0x1e50000 0 0x4ad0>, 1573 <0 0x1e04000 0 0x23000>; 1574 reg-names = "ipa-reg", 1575 "ipa-shared", 1576 "gsi"; 1577 1578 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1579 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1580 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1581 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1582 interrupt-names = "ipa", 1583 "gsi", 1584 "ipa-clock-query", 1585 "ipa-setup-ready"; 1586 1587 clocks = <&rpmhcc RPMH_IPA_CLK>; 1588 clock-names = "core"; 1589 1590 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1591 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1592 interconnect-names = "memory", 1593 "config"; 1594 1595 qcom,smem-states = <&ipa_smp2p_out 0>, 1596 <&ipa_smp2p_out 1>; 1597 qcom,smem-state-names = "ipa-clock-enabled-valid", 1598 "ipa-clock-enabled"; 1599 1600 status = "disabled"; 1601 }; 1602 1603 tcsr_mutex: hwlock@1f40000 { 1604 compatible = "qcom,tcsr-mutex", "syscon"; 1605 reg = <0 0x01f40000 0 0x40000>; 1606 #hwlock-cells = <1>; 1607 }; 1608 1609 tcsr: syscon@1fc0000 { 1610 compatible = "qcom,sc7280-tcsr", "syscon"; 1611 reg = <0 0x01fc0000 0 0x30000>; 1612 }; 1613 1614 lpasscc: lpasscc@3000000 { 1615 compatible = "qcom,sc7280-lpasscc"; 1616 reg = <0 0x03000000 0 0x40>, 1617 <0 0x03c04000 0 0x4>, 1618 <0 0x03389000 0 0x24>; 1619 reg-names = "qdsp6ss", "top_cc", "cc"; 1620 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1621 clock-names = "iface"; 1622 #clock-cells = <1>; 1623 }; 1624 1625 lpass_ag_noc: interconnect@3c40000 { 1626 reg = <0 0x03c40000 0 0xf080>; 1627 compatible = "qcom,sc7280-lpass-ag-noc"; 1628 #interconnect-cells = <2>; 1629 qcom,bcm-voters = <&apps_bcm_voter>; 1630 }; 1631 1632 gpu: gpu@3d00000 { 1633 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1634 #stream-id-cells = <16>; 1635 reg = <0 0x03d00000 0 0x40000>, 1636 <0 0x03d9e000 0 0x1000>, 1637 <0 0x03d61000 0 0x800>; 1638 reg-names = "kgsl_3d0_reg_memory", 1639 "cx_mem", 1640 "cx_dbgc"; 1641 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1642 iommus = <&adreno_smmu 0 0x401>; 1643 operating-points-v2 = <&gpu_opp_table>; 1644 qcom,gmu = <&gmu>; 1645 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1646 interconnect-names = "gfx-mem"; 1647 #cooling-cells = <2>; 1648 1649 gpu_opp_table: opp-table { 1650 compatible = "operating-points-v2"; 1651 1652 opp-315000000 { 1653 opp-hz = /bits/ 64 <315000000>; 1654 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1655 opp-peak-kBps = <1804000>; 1656 }; 1657 1658 opp-450000000 { 1659 opp-hz = /bits/ 64 <450000000>; 1660 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1661 opp-peak-kBps = <4068000>; 1662 }; 1663 1664 opp-550000000 { 1665 opp-hz = /bits/ 64 <550000000>; 1666 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1667 opp-peak-kBps = <6832000>; 1668 }; 1669 }; 1670 }; 1671 1672 gmu: gmu@3d69000 { 1673 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1674 reg = <0 0x03d6a000 0 0x34000>, 1675 <0 0x3de0000 0 0x10000>, 1676 <0 0x0b290000 0 0x10000>; 1677 reg-names = "gmu", "rscc", "gmu_pdc"; 1678 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1680 interrupt-names = "hfi", "gmu"; 1681 clocks = <&gpucc 5>, 1682 <&gpucc 8>, 1683 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1684 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1685 <&gpucc 2>, 1686 <&gpucc 15>, 1687 <&gpucc 11>; 1688 clock-names = "gmu", 1689 "cxo", 1690 "axi", 1691 "memnoc", 1692 "ahb", 1693 "hub", 1694 "smmu_vote"; 1695 power-domains = <&gpucc 0>, 1696 <&gpucc 1>; 1697 power-domain-names = "cx", 1698 "gx"; 1699 iommus = <&adreno_smmu 5 0x400>; 1700 operating-points-v2 = <&gmu_opp_table>; 1701 1702 gmu_opp_table: opp-table { 1703 compatible = "operating-points-v2"; 1704 1705 opp-200000000 { 1706 opp-hz = /bits/ 64 <200000000>; 1707 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1708 }; 1709 }; 1710 }; 1711 1712 gpucc: clock-controller@3d90000 { 1713 compatible = "qcom,sc7280-gpucc"; 1714 reg = <0 0x03d90000 0 0x9000>; 1715 clocks = <&rpmhcc RPMH_CXO_CLK>, 1716 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1717 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1718 clock-names = "bi_tcxo", 1719 "gcc_gpu_gpll0_clk_src", 1720 "gcc_gpu_gpll0_div_clk_src"; 1721 #clock-cells = <1>; 1722 #reset-cells = <1>; 1723 #power-domain-cells = <1>; 1724 }; 1725 1726 adreno_smmu: iommu@3da0000 { 1727 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1728 reg = <0 0x03da0000 0 0x20000>; 1729 #iommu-cells = <2>; 1730 #global-interrupts = <2>; 1731 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1745 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1746 <&gpucc 2>, 1747 <&gpucc 11>, 1748 <&gpucc 5>, 1749 <&gpucc 15>, 1750 <&gpucc 13>; 1751 clock-names = "gcc_gpu_memnoc_gfx_clk", 1752 "gcc_gpu_snoc_dvm_gfx_clk", 1753 "gpu_cc_ahb_clk", 1754 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1755 "gpu_cc_cx_gmu_clk", 1756 "gpu_cc_hub_cx_int_clk", 1757 "gpu_cc_hub_aon_clk"; 1758 1759 power-domains = <&gpucc 0>; 1760 }; 1761 1762 stm@6002000 { 1763 compatible = "arm,coresight-stm", "arm,primecell"; 1764 reg = <0 0x06002000 0 0x1000>, 1765 <0 0x16280000 0 0x180000>; 1766 reg-names = "stm-base", "stm-stimulus-base"; 1767 1768 clocks = <&aoss_qmp>; 1769 clock-names = "apb_pclk"; 1770 1771 out-ports { 1772 port { 1773 stm_out: endpoint { 1774 remote-endpoint = <&funnel0_in7>; 1775 }; 1776 }; 1777 }; 1778 }; 1779 1780 funnel@6041000 { 1781 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1782 reg = <0 0x06041000 0 0x1000>; 1783 1784 clocks = <&aoss_qmp>; 1785 clock-names = "apb_pclk"; 1786 1787 out-ports { 1788 port { 1789 funnel0_out: endpoint { 1790 remote-endpoint = <&merge_funnel_in0>; 1791 }; 1792 }; 1793 }; 1794 1795 in-ports { 1796 #address-cells = <1>; 1797 #size-cells = <0>; 1798 1799 port@7 { 1800 reg = <7>; 1801 funnel0_in7: endpoint { 1802 remote-endpoint = <&stm_out>; 1803 }; 1804 }; 1805 }; 1806 }; 1807 1808 funnel@6042000 { 1809 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1810 reg = <0 0x06042000 0 0x1000>; 1811 1812 clocks = <&aoss_qmp>; 1813 clock-names = "apb_pclk"; 1814 1815 out-ports { 1816 port { 1817 funnel1_out: endpoint { 1818 remote-endpoint = <&merge_funnel_in1>; 1819 }; 1820 }; 1821 }; 1822 1823 in-ports { 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 1827 port@4 { 1828 reg = <4>; 1829 funnel1_in4: endpoint { 1830 remote-endpoint = <&apss_merge_funnel_out>; 1831 }; 1832 }; 1833 }; 1834 }; 1835 1836 funnel@6045000 { 1837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1838 reg = <0 0x06045000 0 0x1000>; 1839 1840 clocks = <&aoss_qmp>; 1841 clock-names = "apb_pclk"; 1842 1843 out-ports { 1844 port { 1845 merge_funnel_out: endpoint { 1846 remote-endpoint = <&swao_funnel_in>; 1847 }; 1848 }; 1849 }; 1850 1851 in-ports { 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 1855 port@0 { 1856 reg = <0>; 1857 merge_funnel_in0: endpoint { 1858 remote-endpoint = <&funnel0_out>; 1859 }; 1860 }; 1861 1862 port@1 { 1863 reg = <1>; 1864 merge_funnel_in1: endpoint { 1865 remote-endpoint = <&funnel1_out>; 1866 }; 1867 }; 1868 }; 1869 }; 1870 1871 replicator@6046000 { 1872 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1873 reg = <0 0x06046000 0 0x1000>; 1874 1875 clocks = <&aoss_qmp>; 1876 clock-names = "apb_pclk"; 1877 1878 out-ports { 1879 port { 1880 replicator_out: endpoint { 1881 remote-endpoint = <&etr_in>; 1882 }; 1883 }; 1884 }; 1885 1886 in-ports { 1887 port { 1888 replicator_in: endpoint { 1889 remote-endpoint = <&swao_replicator_out>; 1890 }; 1891 }; 1892 }; 1893 }; 1894 1895 etr@6048000 { 1896 compatible = "arm,coresight-tmc", "arm,primecell"; 1897 reg = <0 0x06048000 0 0x1000>; 1898 iommus = <&apps_smmu 0x04c0 0>; 1899 1900 clocks = <&aoss_qmp>; 1901 clock-names = "apb_pclk"; 1902 arm,scatter-gather; 1903 1904 in-ports { 1905 port { 1906 etr_in: endpoint { 1907 remote-endpoint = <&replicator_out>; 1908 }; 1909 }; 1910 }; 1911 }; 1912 1913 funnel@6b04000 { 1914 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1915 reg = <0 0x06b04000 0 0x1000>; 1916 1917 clocks = <&aoss_qmp>; 1918 clock-names = "apb_pclk"; 1919 1920 out-ports { 1921 port { 1922 swao_funnel_out: endpoint { 1923 remote-endpoint = <&etf_in>; 1924 }; 1925 }; 1926 }; 1927 1928 in-ports { 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 1932 port@7 { 1933 reg = <7>; 1934 swao_funnel_in: endpoint { 1935 remote-endpoint = <&merge_funnel_out>; 1936 }; 1937 }; 1938 }; 1939 }; 1940 1941 etf@6b05000 { 1942 compatible = "arm,coresight-tmc", "arm,primecell"; 1943 reg = <0 0x06b05000 0 0x1000>; 1944 1945 clocks = <&aoss_qmp>; 1946 clock-names = "apb_pclk"; 1947 1948 out-ports { 1949 port { 1950 etf_out: endpoint { 1951 remote-endpoint = <&swao_replicator_in>; 1952 }; 1953 }; 1954 }; 1955 1956 in-ports { 1957 port { 1958 etf_in: endpoint { 1959 remote-endpoint = <&swao_funnel_out>; 1960 }; 1961 }; 1962 }; 1963 }; 1964 1965 replicator@6b06000 { 1966 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1967 reg = <0 0x06b06000 0 0x1000>; 1968 1969 clocks = <&aoss_qmp>; 1970 clock-names = "apb_pclk"; 1971 qcom,replicator-loses-context; 1972 1973 out-ports { 1974 port { 1975 swao_replicator_out: endpoint { 1976 remote-endpoint = <&replicator_in>; 1977 }; 1978 }; 1979 }; 1980 1981 in-ports { 1982 port { 1983 swao_replicator_in: endpoint { 1984 remote-endpoint = <&etf_out>; 1985 }; 1986 }; 1987 }; 1988 }; 1989 1990 etm@7040000 { 1991 compatible = "arm,coresight-etm4x", "arm,primecell"; 1992 reg = <0 0x07040000 0 0x1000>; 1993 1994 cpu = <&CPU0>; 1995 1996 clocks = <&aoss_qmp>; 1997 clock-names = "apb_pclk"; 1998 arm,coresight-loses-context-with-cpu; 1999 qcom,skip-power-up; 2000 2001 out-ports { 2002 port { 2003 etm0_out: endpoint { 2004 remote-endpoint = <&apss_funnel_in0>; 2005 }; 2006 }; 2007 }; 2008 }; 2009 2010 etm@7140000 { 2011 compatible = "arm,coresight-etm4x", "arm,primecell"; 2012 reg = <0 0x07140000 0 0x1000>; 2013 2014 cpu = <&CPU1>; 2015 2016 clocks = <&aoss_qmp>; 2017 clock-names = "apb_pclk"; 2018 arm,coresight-loses-context-with-cpu; 2019 qcom,skip-power-up; 2020 2021 out-ports { 2022 port { 2023 etm1_out: endpoint { 2024 remote-endpoint = <&apss_funnel_in1>; 2025 }; 2026 }; 2027 }; 2028 }; 2029 2030 etm@7240000 { 2031 compatible = "arm,coresight-etm4x", "arm,primecell"; 2032 reg = <0 0x07240000 0 0x1000>; 2033 2034 cpu = <&CPU2>; 2035 2036 clocks = <&aoss_qmp>; 2037 clock-names = "apb_pclk"; 2038 arm,coresight-loses-context-with-cpu; 2039 qcom,skip-power-up; 2040 2041 out-ports { 2042 port { 2043 etm2_out: endpoint { 2044 remote-endpoint = <&apss_funnel_in2>; 2045 }; 2046 }; 2047 }; 2048 }; 2049 2050 etm@7340000 { 2051 compatible = "arm,coresight-etm4x", "arm,primecell"; 2052 reg = <0 0x07340000 0 0x1000>; 2053 2054 cpu = <&CPU3>; 2055 2056 clocks = <&aoss_qmp>; 2057 clock-names = "apb_pclk"; 2058 arm,coresight-loses-context-with-cpu; 2059 qcom,skip-power-up; 2060 2061 out-ports { 2062 port { 2063 etm3_out: endpoint { 2064 remote-endpoint = <&apss_funnel_in3>; 2065 }; 2066 }; 2067 }; 2068 }; 2069 2070 etm@7440000 { 2071 compatible = "arm,coresight-etm4x", "arm,primecell"; 2072 reg = <0 0x07440000 0 0x1000>; 2073 2074 cpu = <&CPU4>; 2075 2076 clocks = <&aoss_qmp>; 2077 clock-names = "apb_pclk"; 2078 arm,coresight-loses-context-with-cpu; 2079 qcom,skip-power-up; 2080 2081 out-ports { 2082 port { 2083 etm4_out: endpoint { 2084 remote-endpoint = <&apss_funnel_in4>; 2085 }; 2086 }; 2087 }; 2088 }; 2089 2090 etm@7540000 { 2091 compatible = "arm,coresight-etm4x", "arm,primecell"; 2092 reg = <0 0x07540000 0 0x1000>; 2093 2094 cpu = <&CPU5>; 2095 2096 clocks = <&aoss_qmp>; 2097 clock-names = "apb_pclk"; 2098 arm,coresight-loses-context-with-cpu; 2099 qcom,skip-power-up; 2100 2101 out-ports { 2102 port { 2103 etm5_out: endpoint { 2104 remote-endpoint = <&apss_funnel_in5>; 2105 }; 2106 }; 2107 }; 2108 }; 2109 2110 etm@7640000 { 2111 compatible = "arm,coresight-etm4x", "arm,primecell"; 2112 reg = <0 0x07640000 0 0x1000>; 2113 2114 cpu = <&CPU6>; 2115 2116 clocks = <&aoss_qmp>; 2117 clock-names = "apb_pclk"; 2118 arm,coresight-loses-context-with-cpu; 2119 qcom,skip-power-up; 2120 2121 out-ports { 2122 port { 2123 etm6_out: endpoint { 2124 remote-endpoint = <&apss_funnel_in6>; 2125 }; 2126 }; 2127 }; 2128 }; 2129 2130 etm@7740000 { 2131 compatible = "arm,coresight-etm4x", "arm,primecell"; 2132 reg = <0 0x07740000 0 0x1000>; 2133 2134 cpu = <&CPU7>; 2135 2136 clocks = <&aoss_qmp>; 2137 clock-names = "apb_pclk"; 2138 arm,coresight-loses-context-with-cpu; 2139 qcom,skip-power-up; 2140 2141 out-ports { 2142 port { 2143 etm7_out: endpoint { 2144 remote-endpoint = <&apss_funnel_in7>; 2145 }; 2146 }; 2147 }; 2148 }; 2149 2150 funnel@7800000 { /* APSS Funnel */ 2151 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2152 reg = <0 0x07800000 0 0x1000>; 2153 2154 clocks = <&aoss_qmp>; 2155 clock-names = "apb_pclk"; 2156 2157 out-ports { 2158 port { 2159 apss_funnel_out: endpoint { 2160 remote-endpoint = <&apss_merge_funnel_in>; 2161 }; 2162 }; 2163 }; 2164 2165 in-ports { 2166 #address-cells = <1>; 2167 #size-cells = <0>; 2168 2169 port@0 { 2170 reg = <0>; 2171 apss_funnel_in0: endpoint { 2172 remote-endpoint = <&etm0_out>; 2173 }; 2174 }; 2175 2176 port@1 { 2177 reg = <1>; 2178 apss_funnel_in1: endpoint { 2179 remote-endpoint = <&etm1_out>; 2180 }; 2181 }; 2182 2183 port@2 { 2184 reg = <2>; 2185 apss_funnel_in2: endpoint { 2186 remote-endpoint = <&etm2_out>; 2187 }; 2188 }; 2189 2190 port@3 { 2191 reg = <3>; 2192 apss_funnel_in3: endpoint { 2193 remote-endpoint = <&etm3_out>; 2194 }; 2195 }; 2196 2197 port@4 { 2198 reg = <4>; 2199 apss_funnel_in4: endpoint { 2200 remote-endpoint = <&etm4_out>; 2201 }; 2202 }; 2203 2204 port@5 { 2205 reg = <5>; 2206 apss_funnel_in5: endpoint { 2207 remote-endpoint = <&etm5_out>; 2208 }; 2209 }; 2210 2211 port@6 { 2212 reg = <6>; 2213 apss_funnel_in6: endpoint { 2214 remote-endpoint = <&etm6_out>; 2215 }; 2216 }; 2217 2218 port@7 { 2219 reg = <7>; 2220 apss_funnel_in7: endpoint { 2221 remote-endpoint = <&etm7_out>; 2222 }; 2223 }; 2224 }; 2225 }; 2226 2227 funnel@7810000 { 2228 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2229 reg = <0 0x07810000 0 0x1000>; 2230 2231 clocks = <&aoss_qmp>; 2232 clock-names = "apb_pclk"; 2233 2234 out-ports { 2235 port { 2236 apss_merge_funnel_out: endpoint { 2237 remote-endpoint = <&funnel1_in4>; 2238 }; 2239 }; 2240 }; 2241 2242 in-ports { 2243 port { 2244 apss_merge_funnel_in: endpoint { 2245 remote-endpoint = <&apss_funnel_out>; 2246 }; 2247 }; 2248 }; 2249 }; 2250 2251 sdhc_2: sdhci@8804000 { 2252 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2253 status = "disabled"; 2254 2255 reg = <0 0x08804000 0 0x1000>; 2256 2257 iommus = <&apps_smmu 0x100 0x0>; 2258 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2260 interrupt-names = "hc_irq", "pwr_irq"; 2261 2262 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2263 <&gcc GCC_SDCC2_AHB_CLK>, 2264 <&rpmhcc RPMH_CXO_CLK>; 2265 clock-names = "core", "iface", "xo"; 2266 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2267 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2268 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2269 power-domains = <&rpmhpd SC7280_CX>; 2270 operating-points-v2 = <&sdhc2_opp_table>; 2271 2272 bus-width = <4>; 2273 2274 qcom,dll-config = <0x0007642c>; 2275 2276 sdhc2_opp_table: opp-table { 2277 compatible = "operating-points-v2"; 2278 2279 opp-100000000 { 2280 opp-hz = /bits/ 64 <100000000>; 2281 required-opps = <&rpmhpd_opp_low_svs>; 2282 opp-peak-kBps = <1800000 400000>; 2283 opp-avg-kBps = <100000 0>; 2284 }; 2285 2286 opp-202000000 { 2287 opp-hz = /bits/ 64 <202000000>; 2288 required-opps = <&rpmhpd_opp_nom>; 2289 opp-peak-kBps = <5400000 1600000>; 2290 opp-avg-kBps = <200000 0>; 2291 }; 2292 }; 2293 2294 }; 2295 2296 usb_1_hsphy: phy@88e3000 { 2297 compatible = "qcom,sc7280-usb-hs-phy", 2298 "qcom,usb-snps-hs-7nm-phy"; 2299 reg = <0 0x088e3000 0 0x400>; 2300 status = "disabled"; 2301 #phy-cells = <0>; 2302 2303 clocks = <&rpmhcc RPMH_CXO_CLK>; 2304 clock-names = "ref"; 2305 2306 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2307 }; 2308 2309 usb_2_hsphy: phy@88e4000 { 2310 compatible = "qcom,sc7280-usb-hs-phy", 2311 "qcom,usb-snps-hs-7nm-phy"; 2312 reg = <0 0x088e4000 0 0x400>; 2313 status = "disabled"; 2314 #phy-cells = <0>; 2315 2316 clocks = <&rpmhcc RPMH_CXO_CLK>; 2317 clock-names = "ref"; 2318 2319 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2320 }; 2321 2322 usb_1_qmpphy: phy-wrapper@88e9000 { 2323 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2324 "qcom,sm8250-qmp-usb3-dp-phy"; 2325 reg = <0 0x088e9000 0 0x200>, 2326 <0 0x088e8000 0 0x40>, 2327 <0 0x088ea000 0 0x200>; 2328 status = "disabled"; 2329 #address-cells = <2>; 2330 #size-cells = <2>; 2331 ranges; 2332 2333 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2334 <&rpmhcc RPMH_CXO_CLK>, 2335 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2336 clock-names = "aux", "ref_clk_src", "com_aux"; 2337 2338 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2339 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2340 reset-names = "phy", "common"; 2341 2342 usb_1_ssphy: usb3-phy@88e9200 { 2343 reg = <0 0x088e9200 0 0x200>, 2344 <0 0x088e9400 0 0x200>, 2345 <0 0x088e9c00 0 0x400>, 2346 <0 0x088e9600 0 0x200>, 2347 <0 0x088e9800 0 0x200>, 2348 <0 0x088e9a00 0 0x100>; 2349 #clock-cells = <0>; 2350 #phy-cells = <0>; 2351 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2352 clock-names = "pipe0"; 2353 clock-output-names = "usb3_phy_pipe_clk_src"; 2354 }; 2355 2356 dp_phy: dp-phy@88ea200 { 2357 reg = <0 0x088ea200 0 0x200>, 2358 <0 0x088ea400 0 0x200>, 2359 <0 0x088eaa00 0 0x200>, 2360 <0 0x088ea600 0 0x200>, 2361 <0 0x088ea800 0 0x200>; 2362 #phy-cells = <0>; 2363 #clock-cells = <1>; 2364 }; 2365 }; 2366 2367 usb_2: usb@8cf8800 { 2368 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2369 reg = <0 0x08cf8800 0 0x400>; 2370 status = "disabled"; 2371 #address-cells = <2>; 2372 #size-cells = <2>; 2373 ranges; 2374 dma-ranges; 2375 2376 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2377 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2378 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2379 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2380 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2381 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2382 "sleep"; 2383 2384 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2385 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2386 assigned-clock-rates = <19200000>, <200000000>; 2387 2388 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2389 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2390 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2391 interrupt-names = "hs_phy_irq", 2392 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2393 2394 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2395 2396 resets = <&gcc GCC_USB30_SEC_BCR>; 2397 2398 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2399 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2400 interconnect-names = "usb-ddr", "apps-usb"; 2401 2402 usb_2_dwc3: usb@8c00000 { 2403 compatible = "snps,dwc3"; 2404 reg = <0 0x08c00000 0 0xe000>; 2405 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2406 iommus = <&apps_smmu 0xa0 0x0>; 2407 snps,dis_u2_susphy_quirk; 2408 snps,dis_enblslpm_quirk; 2409 phys = <&usb_2_hsphy>; 2410 phy-names = "usb2-phy"; 2411 maximum-speed = "high-speed"; 2412 }; 2413 }; 2414 2415 qspi: spi@88dc000 { 2416 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2417 reg = <0 0x088dc000 0 0x1000>; 2418 #address-cells = <1>; 2419 #size-cells = <0>; 2420 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2421 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2422 <&gcc GCC_QSPI_CORE_CLK>; 2423 clock-names = "iface", "core"; 2424 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2425 &cnoc2 SLAVE_QSPI_0 0>; 2426 interconnect-names = "qspi-config"; 2427 power-domains = <&rpmhpd SC7280_CX>; 2428 operating-points-v2 = <&qspi_opp_table>; 2429 status = "disabled"; 2430 }; 2431 2432 dc_noc: interconnect@90e0000 { 2433 reg = <0 0x090e0000 0 0x5080>; 2434 compatible = "qcom,sc7280-dc-noc"; 2435 #interconnect-cells = <2>; 2436 qcom,bcm-voters = <&apps_bcm_voter>; 2437 }; 2438 2439 gem_noc: interconnect@9100000 { 2440 reg = <0 0x9100000 0 0xe2200>; 2441 compatible = "qcom,sc7280-gem-noc"; 2442 #interconnect-cells = <2>; 2443 qcom,bcm-voters = <&apps_bcm_voter>; 2444 }; 2445 2446 system-cache-controller@9200000 { 2447 compatible = "qcom,sc7280-llcc"; 2448 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2449 reg-names = "llcc_base", "llcc_broadcast_base"; 2450 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2451 }; 2452 2453 nsp_noc: interconnect@a0c0000 { 2454 reg = <0 0x0a0c0000 0 0x10000>; 2455 compatible = "qcom,sc7280-nsp-noc"; 2456 #interconnect-cells = <2>; 2457 qcom,bcm-voters = <&apps_bcm_voter>; 2458 }; 2459 2460 usb_1: usb@a6f8800 { 2461 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2462 reg = <0 0x0a6f8800 0 0x400>; 2463 status = "disabled"; 2464 #address-cells = <2>; 2465 #size-cells = <2>; 2466 ranges; 2467 dma-ranges; 2468 2469 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2470 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2471 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2472 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2473 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2474 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2475 "sleep"; 2476 2477 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2478 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2479 assigned-clock-rates = <19200000>, <200000000>; 2480 2481 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2482 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2483 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2484 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2485 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2486 "dm_hs_phy_irq", "ss_phy_irq"; 2487 2488 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2489 2490 resets = <&gcc GCC_USB30_PRIM_BCR>; 2491 2492 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2493 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2494 interconnect-names = "usb-ddr", "apps-usb"; 2495 2496 usb_1_dwc3: usb@a600000 { 2497 compatible = "snps,dwc3"; 2498 reg = <0 0x0a600000 0 0xe000>; 2499 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2500 iommus = <&apps_smmu 0xe0 0x0>; 2501 snps,dis_u2_susphy_quirk; 2502 snps,dis_enblslpm_quirk; 2503 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2504 phy-names = "usb2-phy", "usb3-phy"; 2505 maximum-speed = "super-speed"; 2506 }; 2507 }; 2508 2509 videocc: clock-controller@aaf0000 { 2510 compatible = "qcom,sc7280-videocc"; 2511 reg = <0 0xaaf0000 0 0x10000>; 2512 clocks = <&rpmhcc RPMH_CXO_CLK>, 2513 <&rpmhcc RPMH_CXO_CLK_A>; 2514 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2515 #clock-cells = <1>; 2516 #reset-cells = <1>; 2517 #power-domain-cells = <1>; 2518 }; 2519 2520 dispcc: clock-controller@af00000 { 2521 compatible = "qcom,sc7280-dispcc"; 2522 reg = <0 0xaf00000 0 0x20000>; 2523 clocks = <&rpmhcc RPMH_CXO_CLK>, 2524 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2525 <0>, <0>, <0>, <0>, <0>, <0>; 2526 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2527 "dsi0_phy_pll_out_byteclk", 2528 "dsi0_phy_pll_out_dsiclk", 2529 "dp_phy_pll_link_clk", 2530 "dp_phy_pll_vco_div_clk", 2531 "edp_phy_pll_link_clk", 2532 "edp_phy_pll_vco_div_clk"; 2533 #clock-cells = <1>; 2534 #reset-cells = <1>; 2535 #power-domain-cells = <1>; 2536 }; 2537 2538 pdc: interrupt-controller@b220000 { 2539 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2540 reg = <0 0x0b220000 0 0x30000>; 2541 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2542 <55 306 4>, <59 312 3>, <62 374 2>, 2543 <64 434 2>, <66 438 3>, <69 86 1>, 2544 <70 520 54>, <124 609 31>, <155 63 1>, 2545 <156 716 12>; 2546 #interrupt-cells = <2>; 2547 interrupt-parent = <&intc>; 2548 interrupt-controller; 2549 }; 2550 2551 pdc_reset: reset-controller@b5e0000 { 2552 compatible = "qcom,sc7280-pdc-global"; 2553 reg = <0 0x0b5e0000 0 0x20000>; 2554 #reset-cells = <1>; 2555 }; 2556 2557 tsens0: thermal-sensor@c263000 { 2558 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2559 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2560 <0 0x0c222000 0 0x1ff>; /* SROT */ 2561 #qcom,sensors = <15>; 2562 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2564 interrupt-names = "uplow","critical"; 2565 #thermal-sensor-cells = <1>; 2566 }; 2567 2568 tsens1: thermal-sensor@c265000 { 2569 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2570 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2571 <0 0x0c223000 0 0x1ff>; /* SROT */ 2572 #qcom,sensors = <12>; 2573 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2574 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2575 interrupt-names = "uplow","critical"; 2576 #thermal-sensor-cells = <1>; 2577 }; 2578 2579 aoss_reset: reset-controller@c2a0000 { 2580 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2581 reg = <0 0x0c2a0000 0 0x31000>; 2582 #reset-cells = <1>; 2583 }; 2584 2585 aoss_qmp: power-controller@c300000 { 2586 compatible = "qcom,sc7280-aoss-qmp"; 2587 reg = <0 0x0c300000 0 0x100000>; 2588 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2589 IPCC_MPROC_SIGNAL_GLINK_QMP 2590 IRQ_TYPE_EDGE_RISING>; 2591 mboxes = <&ipcc IPCC_CLIENT_AOP 2592 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2593 2594 #clock-cells = <0>; 2595 }; 2596 2597 spmi_bus: spmi@c440000 { 2598 compatible = "qcom,spmi-pmic-arb"; 2599 reg = <0 0x0c440000 0 0x1100>, 2600 <0 0x0c600000 0 0x2000000>, 2601 <0 0x0e600000 0 0x100000>, 2602 <0 0x0e700000 0 0xa0000>, 2603 <0 0x0c40a000 0 0x26000>; 2604 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2605 interrupt-names = "periph_irq"; 2606 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2607 qcom,ee = <0>; 2608 qcom,channel = <0>; 2609 #address-cells = <1>; 2610 #size-cells = <1>; 2611 interrupt-controller; 2612 #interrupt-cells = <4>; 2613 }; 2614 2615 tlmm: pinctrl@f100000 { 2616 compatible = "qcom,sc7280-pinctrl"; 2617 reg = <0 0x0f100000 0 0x300000>; 2618 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2619 gpio-controller; 2620 #gpio-cells = <2>; 2621 interrupt-controller; 2622 #interrupt-cells = <2>; 2623 gpio-ranges = <&tlmm 0 0 175>; 2624 wakeup-parent = <&pdc>; 2625 2626 qspi_clk: qspi-clk { 2627 pins = "gpio14"; 2628 function = "qspi_clk"; 2629 }; 2630 2631 qspi_cs0: qspi-cs0 { 2632 pins = "gpio15"; 2633 function = "qspi_cs"; 2634 }; 2635 2636 qspi_cs1: qspi-cs1 { 2637 pins = "gpio19"; 2638 function = "qspi_cs"; 2639 }; 2640 2641 qspi_data01: qspi-data01 { 2642 pins = "gpio12", "gpio13"; 2643 function = "qspi_data"; 2644 }; 2645 2646 qspi_data12: qspi-data12 { 2647 pins = "gpio16", "gpio17"; 2648 function = "qspi_data"; 2649 }; 2650 2651 qup_i2c0_data_clk: qup-i2c0-data-clk { 2652 pins = "gpio0", "gpio1"; 2653 function = "qup00"; 2654 }; 2655 2656 qup_i2c1_data_clk: qup-i2c1-data-clk { 2657 pins = "gpio4", "gpio5"; 2658 function = "qup01"; 2659 }; 2660 2661 qup_i2c2_data_clk: qup-i2c2-data-clk { 2662 pins = "gpio8", "gpio9"; 2663 function = "qup02"; 2664 }; 2665 2666 qup_i2c3_data_clk: qup-i2c3-data-clk { 2667 pins = "gpio12", "gpio13"; 2668 function = "qup03"; 2669 }; 2670 2671 qup_i2c4_data_clk: qup-i2c4-data-clk { 2672 pins = "gpio16", "gpio17"; 2673 function = "qup04"; 2674 }; 2675 2676 qup_i2c5_data_clk: qup-i2c5-data-clk { 2677 pins = "gpio20", "gpio21"; 2678 function = "qup05"; 2679 }; 2680 2681 qup_i2c6_data_clk: qup-i2c6-data-clk { 2682 pins = "gpio24", "gpio25"; 2683 function = "qup06"; 2684 }; 2685 2686 qup_i2c7_data_clk: qup-i2c7-data-clk { 2687 pins = "gpio28", "gpio29"; 2688 function = "qup07"; 2689 }; 2690 2691 qup_i2c8_data_clk: qup-i2c8-data-clk { 2692 pins = "gpio32", "gpio33"; 2693 function = "qup10"; 2694 }; 2695 2696 qup_i2c9_data_clk: qup-i2c9-data-clk { 2697 pins = "gpio36", "gpio37"; 2698 function = "qup11"; 2699 }; 2700 2701 qup_i2c10_data_clk: qup-i2c10-data-clk { 2702 pins = "gpio40", "gpio41"; 2703 function = "qup12"; 2704 }; 2705 2706 qup_i2c11_data_clk: qup-i2c11-data-clk { 2707 pins = "gpio44", "gpio45"; 2708 function = "qup13"; 2709 }; 2710 2711 qup_i2c12_data_clk: qup-i2c12-data-clk { 2712 pins = "gpio48", "gpio49"; 2713 function = "qup14"; 2714 }; 2715 2716 qup_i2c13_data_clk: qup-i2c13-data-clk { 2717 pins = "gpio52", "gpio53"; 2718 function = "qup15"; 2719 }; 2720 2721 qup_i2c14_data_clk: qup-i2c14-data-clk { 2722 pins = "gpio56", "gpio57"; 2723 function = "qup16"; 2724 }; 2725 2726 qup_i2c15_data_clk: qup-i2c15-data-clk { 2727 pins = "gpio60", "gpio61"; 2728 function = "qup17"; 2729 }; 2730 2731 qup_spi0_data_clk: qup-spi0-data-clk { 2732 pins = "gpio0", "gpio1", "gpio2"; 2733 function = "qup00"; 2734 }; 2735 2736 qup_spi0_cs: qup-spi0-cs { 2737 pins = "gpio3"; 2738 function = "qup00"; 2739 }; 2740 2741 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2742 pins = "gpio3"; 2743 function = "gpio"; 2744 }; 2745 2746 qup_spi1_data_clk: qup-spi1-data-clk { 2747 pins = "gpio4", "gpio5", "gpio6"; 2748 function = "qup01"; 2749 }; 2750 2751 qup_spi1_cs: qup-spi1-cs { 2752 pins = "gpio7"; 2753 function = "qup01"; 2754 }; 2755 2756 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2757 pins = "gpio7"; 2758 function = "gpio"; 2759 }; 2760 2761 qup_spi2_data_clk: qup-spi2-data-clk { 2762 pins = "gpio8", "gpio9", "gpio10"; 2763 function = "qup02"; 2764 }; 2765 2766 qup_spi2_cs: qup-spi2-cs { 2767 pins = "gpio11"; 2768 function = "qup02"; 2769 }; 2770 2771 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2772 pins = "gpio11"; 2773 function = "gpio"; 2774 }; 2775 2776 qup_spi3_data_clk: qup-spi3-data-clk { 2777 pins = "gpio12", "gpio13", "gpio14"; 2778 function = "qup03"; 2779 }; 2780 2781 qup_spi3_cs: qup-spi3-cs { 2782 pins = "gpio15"; 2783 function = "qup03"; 2784 }; 2785 2786 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2787 pins = "gpio15"; 2788 function = "gpio"; 2789 }; 2790 2791 qup_spi4_data_clk: qup-spi4-data-clk { 2792 pins = "gpio16", "gpio17", "gpio18"; 2793 function = "qup04"; 2794 }; 2795 2796 qup_spi4_cs: qup-spi4-cs { 2797 pins = "gpio19"; 2798 function = "qup04"; 2799 }; 2800 2801 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2802 pins = "gpio19"; 2803 function = "gpio"; 2804 }; 2805 2806 qup_spi5_data_clk: qup-spi5-data-clk { 2807 pins = "gpio20", "gpio21", "gpio22"; 2808 function = "qup05"; 2809 }; 2810 2811 qup_spi5_cs: qup-spi5-cs { 2812 pins = "gpio23"; 2813 function = "qup05"; 2814 }; 2815 2816 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2817 pins = "gpio23"; 2818 function = "gpio"; 2819 }; 2820 2821 qup_spi6_data_clk: qup-spi6-data-clk { 2822 pins = "gpio24", "gpio25", "gpio26"; 2823 function = "qup06"; 2824 }; 2825 2826 qup_spi6_cs: qup-spi6-cs { 2827 pins = "gpio27"; 2828 function = "qup06"; 2829 }; 2830 2831 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2832 pins = "gpio27"; 2833 function = "gpio"; 2834 }; 2835 2836 qup_spi7_data_clk: qup-spi7-data-clk { 2837 pins = "gpio28", "gpio29", "gpio30"; 2838 function = "qup07"; 2839 }; 2840 2841 qup_spi7_cs: qup-spi7-cs { 2842 pins = "gpio31"; 2843 function = "qup07"; 2844 }; 2845 2846 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2847 pins = "gpio31"; 2848 function = "gpio"; 2849 }; 2850 2851 qup_spi8_data_clk: qup-spi8-data-clk { 2852 pins = "gpio32", "gpio33", "gpio34"; 2853 function = "qup10"; 2854 }; 2855 2856 qup_spi8_cs: qup-spi8-cs { 2857 pins = "gpio35"; 2858 function = "qup10"; 2859 }; 2860 2861 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 2862 pins = "gpio35"; 2863 function = "gpio"; 2864 }; 2865 2866 qup_spi9_data_clk: qup-spi9-data-clk { 2867 pins = "gpio36", "gpio37", "gpio38"; 2868 function = "qup11"; 2869 }; 2870 2871 qup_spi9_cs: qup-spi9-cs { 2872 pins = "gpio39"; 2873 function = "qup11"; 2874 }; 2875 2876 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 2877 pins = "gpio39"; 2878 function = "gpio"; 2879 }; 2880 2881 qup_spi10_data_clk: qup-spi10-data-clk { 2882 pins = "gpio40", "gpio41", "gpio42"; 2883 function = "qup12"; 2884 }; 2885 2886 qup_spi10_cs: qup-spi10-cs { 2887 pins = "gpio43"; 2888 function = "qup12"; 2889 }; 2890 2891 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 2892 pins = "gpio43"; 2893 function = "gpio"; 2894 }; 2895 2896 qup_spi11_data_clk: qup-spi11-data-clk { 2897 pins = "gpio44", "gpio45", "gpio46"; 2898 function = "qup13"; 2899 }; 2900 2901 qup_spi11_cs: qup-spi11-cs { 2902 pins = "gpio47"; 2903 function = "qup13"; 2904 }; 2905 2906 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 2907 pins = "gpio47"; 2908 function = "gpio"; 2909 }; 2910 2911 qup_spi12_data_clk: qup-spi12-data-clk { 2912 pins = "gpio48", "gpio49", "gpio50"; 2913 function = "qup14"; 2914 }; 2915 2916 qup_spi12_cs: qup-spi12-cs { 2917 pins = "gpio51"; 2918 function = "qup14"; 2919 }; 2920 2921 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 2922 pins = "gpio51"; 2923 function = "gpio"; 2924 }; 2925 2926 qup_spi13_data_clk: qup-spi13-data-clk { 2927 pins = "gpio52", "gpio53", "gpio54"; 2928 function = "qup15"; 2929 }; 2930 2931 qup_spi13_cs: qup-spi13-cs { 2932 pins = "gpio55"; 2933 function = "qup15"; 2934 }; 2935 2936 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 2937 pins = "gpio55"; 2938 function = "gpio"; 2939 }; 2940 2941 qup_spi14_data_clk: qup-spi14-data-clk { 2942 pins = "gpio56", "gpio57", "gpio58"; 2943 function = "qup16"; 2944 }; 2945 2946 qup_spi14_cs: qup-spi14-cs { 2947 pins = "gpio59"; 2948 function = "qup16"; 2949 }; 2950 2951 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 2952 pins = "gpio59"; 2953 function = "gpio"; 2954 }; 2955 2956 qup_spi15_data_clk: qup-spi15-data-clk { 2957 pins = "gpio60", "gpio61", "gpio62"; 2958 function = "qup17"; 2959 }; 2960 2961 qup_spi15_cs: qup-spi15-cs { 2962 pins = "gpio63"; 2963 function = "qup17"; 2964 }; 2965 2966 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 2967 pins = "gpio63"; 2968 function = "gpio"; 2969 }; 2970 2971 qup_uart0_cts: qup-uart0-cts { 2972 pins = "gpio0"; 2973 function = "qup00"; 2974 }; 2975 2976 qup_uart0_rts: qup-uart0-rts { 2977 pins = "gpio1"; 2978 function = "qup00"; 2979 }; 2980 2981 qup_uart0_tx: qup-uart0-tx { 2982 pins = "gpio2"; 2983 function = "qup00"; 2984 }; 2985 2986 qup_uart0_rx: qup-uart0-rx { 2987 pins = "gpio3"; 2988 function = "qup00"; 2989 }; 2990 2991 qup_uart1_cts: qup-uart1-cts { 2992 pins = "gpio4"; 2993 function = "qup01"; 2994 }; 2995 2996 qup_uart1_rts: qup-uart1-rts { 2997 pins = "gpio5"; 2998 function = "qup01"; 2999 }; 3000 3001 qup_uart1_tx: qup-uart1-tx { 3002 pins = "gpio6"; 3003 function = "qup01"; 3004 }; 3005 3006 qup_uart1_rx: qup-uart1-rx { 3007 pins = "gpio7"; 3008 function = "qup01"; 3009 }; 3010 3011 qup_uart2_cts: qup-uart2-cts { 3012 pins = "gpio8"; 3013 function = "qup02"; 3014 }; 3015 3016 qup_uart2_rts: qup-uart2-rts { 3017 pins = "gpio9"; 3018 function = "qup02"; 3019 }; 3020 3021 qup_uart2_tx: qup-uart2-tx { 3022 pins = "gpio10"; 3023 function = "qup02"; 3024 }; 3025 3026 qup_uart2_rx: qup-uart2-rx { 3027 pins = "gpio11"; 3028 function = "qup02"; 3029 }; 3030 3031 qup_uart3_cts: qup-uart3-cts { 3032 pins = "gpio12"; 3033 function = "qup03"; 3034 }; 3035 3036 qup_uart3_rts: qup-uart3-rts { 3037 pins = "gpio13"; 3038 function = "qup03"; 3039 }; 3040 3041 qup_uart3_tx: qup-uart3-tx { 3042 pins = "gpio14"; 3043 function = "qup03"; 3044 }; 3045 3046 qup_uart3_rx: qup-uart3-rx { 3047 pins = "gpio15"; 3048 function = "qup03"; 3049 }; 3050 3051 qup_uart4_cts: qup-uart4-cts { 3052 pins = "gpio16"; 3053 function = "qup04"; 3054 }; 3055 3056 qup_uart4_rts: qup-uart4-rts { 3057 pins = "gpio17"; 3058 function = "qup04"; 3059 }; 3060 3061 qup_uart4_tx: qup-uart4-tx { 3062 pins = "gpio18"; 3063 function = "qup04"; 3064 }; 3065 3066 qup_uart4_rx: qup-uart4-rx { 3067 pins = "gpio19"; 3068 function = "qup04"; 3069 }; 3070 3071 qup_uart5_cts: qup-uart5-cts { 3072 pins = "gpio20"; 3073 function = "qup05"; 3074 }; 3075 3076 qup_uart5_rts: qup-uart5-rts { 3077 pins = "gpio21"; 3078 function = "qup05"; 3079 }; 3080 3081 qup_uart5_tx: qup-uart5-tx { 3082 pins = "gpio22"; 3083 function = "qup05"; 3084 }; 3085 3086 qup_uart5_rx: qup-uart5-rx { 3087 pins = "gpio23"; 3088 function = "qup05"; 3089 }; 3090 3091 qup_uart6_cts: qup-uart6-cts { 3092 pins = "gpio24"; 3093 function = "qup06"; 3094 }; 3095 3096 qup_uart6_rts: qup-uart6-rts { 3097 pins = "gpio25"; 3098 function = "qup06"; 3099 }; 3100 3101 qup_uart6_tx: qup-uart6-tx { 3102 pins = "gpio26"; 3103 function = "qup06"; 3104 }; 3105 3106 qup_uart6_rx: qup-uart6-rx { 3107 pins = "gpio27"; 3108 function = "qup06"; 3109 }; 3110 3111 qup_uart7_cts: qup-uart7-cts { 3112 pins = "gpio28"; 3113 function = "qup07"; 3114 }; 3115 3116 qup_uart7_rts: qup-uart7-rts { 3117 pins = "gpio29"; 3118 function = "qup07"; 3119 }; 3120 3121 qup_uart7_tx: qup-uart7-tx { 3122 pins = "gpio30"; 3123 function = "qup07"; 3124 }; 3125 3126 qup_uart7_rx: qup-uart7-rx { 3127 pins = "gpio31"; 3128 function = "qup07"; 3129 }; 3130 3131 sdc1_on: sdc1-on { 3132 clk { 3133 pins = "sdc1_clk"; 3134 }; 3135 3136 cmd { 3137 pins = "sdc1_cmd"; 3138 }; 3139 3140 data { 3141 pins = "sdc1_data"; 3142 }; 3143 3144 rclk { 3145 pins = "sdc1_rclk"; 3146 }; 3147 }; 3148 3149 sdc1_off: sdc1-off { 3150 clk { 3151 pins = "sdc1_clk"; 3152 drive-strength = <2>; 3153 bias-bus-hold; 3154 }; 3155 3156 cmd { 3157 pins = "sdc1_cmd"; 3158 drive-strength = <2>; 3159 bias-bus-hold; 3160 }; 3161 3162 data { 3163 pins = "sdc1_data"; 3164 drive-strength = <2>; 3165 bias-bus-hold; 3166 }; 3167 3168 rclk { 3169 pins = "sdc1_rclk"; 3170 bias-bus-hold; 3171 }; 3172 }; 3173 3174 sdc2_on: sdc2-on { 3175 clk { 3176 pins = "sdc2_clk"; 3177 }; 3178 3179 cmd { 3180 pins = "sdc2_cmd"; 3181 }; 3182 3183 data { 3184 pins = "sdc2_data"; 3185 }; 3186 }; 3187 3188 sdc2_off: sdc2-off { 3189 clk { 3190 pins = "sdc2_clk"; 3191 drive-strength = <2>; 3192 bias-bus-hold; 3193 }; 3194 3195 cmd { 3196 pins ="sdc2_cmd"; 3197 drive-strength = <2>; 3198 bias-bus-hold; 3199 }; 3200 3201 data { 3202 pins ="sdc2_data"; 3203 drive-strength = <2>; 3204 bias-bus-hold; 3205 }; 3206 }; 3207 3208 qup_uart8_cts: qup-uart8-cts { 3209 pins = "gpio32"; 3210 function = "qup10"; 3211 }; 3212 3213 qup_uart8_rts: qup-uart8-rts { 3214 pins = "gpio33"; 3215 function = "qup10"; 3216 }; 3217 3218 qup_uart8_tx: qup-uart8-tx { 3219 pins = "gpio34"; 3220 function = "qup10"; 3221 }; 3222 3223 qup_uart8_rx: qup-uart8-rx { 3224 pins = "gpio35"; 3225 function = "qup10"; 3226 }; 3227 3228 qup_uart9_cts: qup-uart9-cts { 3229 pins = "gpio36"; 3230 function = "qup11"; 3231 }; 3232 3233 qup_uart9_rts: qup-uart9-rts { 3234 pins = "gpio37"; 3235 function = "qup11"; 3236 }; 3237 3238 qup_uart9_tx: qup-uart9-tx { 3239 pins = "gpio38"; 3240 function = "qup11"; 3241 }; 3242 3243 qup_uart9_rx: qup-uart9-rx { 3244 pins = "gpio39"; 3245 function = "qup11"; 3246 }; 3247 3248 qup_uart10_cts: qup-uart10-cts { 3249 pins = "gpio40"; 3250 function = "qup12"; 3251 }; 3252 3253 qup_uart10_rts: qup-uart10-rts { 3254 pins = "gpio41"; 3255 function = "qup12"; 3256 }; 3257 3258 qup_uart10_tx: qup-uart10-tx { 3259 pins = "gpio42"; 3260 function = "qup12"; 3261 }; 3262 3263 qup_uart10_rx: qup-uart10-rx { 3264 pins = "gpio43"; 3265 function = "qup12"; 3266 }; 3267 3268 qup_uart11_cts: qup-uart11-cts { 3269 pins = "gpio44"; 3270 function = "qup13"; 3271 }; 3272 3273 qup_uart11_rts: qup-uart11-rts { 3274 pins = "gpio45"; 3275 function = "qup13"; 3276 }; 3277 3278 qup_uart11_tx: qup-uart11-tx { 3279 pins = "gpio46"; 3280 function = "qup13"; 3281 }; 3282 3283 qup_uart11_rx: qup-uart11-rx { 3284 pins = "gpio47"; 3285 function = "qup13"; 3286 }; 3287 3288 qup_uart12_cts: qup-uart12-cts { 3289 pins = "gpio48"; 3290 function = "qup14"; 3291 }; 3292 3293 qup_uart12_rts: qup-uart12-rts { 3294 pins = "gpio49"; 3295 function = "qup14"; 3296 }; 3297 3298 qup_uart12_tx: qup-uart12-tx { 3299 pins = "gpio50"; 3300 function = "qup14"; 3301 }; 3302 3303 qup_uart12_rx: qup-uart12-rx { 3304 pins = "gpio51"; 3305 function = "qup14"; 3306 }; 3307 3308 qup_uart13_cts: qup-uart13-cts { 3309 pins = "gpio52"; 3310 function = "qup15"; 3311 }; 3312 3313 qup_uart13_rts: qup-uart13-rts { 3314 pins = "gpio53"; 3315 function = "qup15"; 3316 }; 3317 3318 qup_uart13_tx: qup-uart13-tx { 3319 pins = "gpio54"; 3320 function = "qup15"; 3321 }; 3322 3323 qup_uart13_rx: qup-uart13-rx { 3324 pins = "gpio55"; 3325 function = "qup15"; 3326 }; 3327 3328 qup_uart14_cts: qup-uart14-cts { 3329 pins = "gpio56"; 3330 function = "qup16"; 3331 }; 3332 3333 qup_uart14_rts: qup-uart14-rts { 3334 pins = "gpio57"; 3335 function = "qup16"; 3336 }; 3337 3338 qup_uart14_tx: qup-uart14-tx { 3339 pins = "gpio58"; 3340 function = "qup16"; 3341 }; 3342 3343 qup_uart14_rx: qup-uart14-rx { 3344 pins = "gpio59"; 3345 function = "qup16"; 3346 }; 3347 3348 qup_uart15_cts: qup-uart15-cts { 3349 pins = "gpio60"; 3350 function = "qup17"; 3351 }; 3352 3353 qup_uart15_rts: qup-uart15-rts { 3354 pins = "gpio61"; 3355 function = "qup17"; 3356 }; 3357 3358 qup_uart15_tx: qup-uart15-tx { 3359 pins = "gpio62"; 3360 function = "qup17"; 3361 }; 3362 3363 qup_uart15_rx: qup-uart15-rx { 3364 pins = "gpio63"; 3365 function = "qup17"; 3366 }; 3367 }; 3368 3369 imem@146a5000 { 3370 compatible = "qcom,sc7280-imem", "syscon"; 3371 reg = <0 0x146a5000 0 0x6000>; 3372 3373 #address-cells = <1>; 3374 #size-cells = <1>; 3375 3376 ranges = <0 0 0x146a5000 0x6000>; 3377 3378 pil-reloc@594c { 3379 compatible = "qcom,pil-reloc-info"; 3380 reg = <0x594c 0xc8>; 3381 }; 3382 }; 3383 3384 apps_smmu: iommu@15000000 { 3385 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3386 reg = <0 0x15000000 0 0x100000>; 3387 #iommu-cells = <2>; 3388 #global-interrupts = <1>; 3389 dma-coherent; 3390 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3471 }; 3472 3473 intc: interrupt-controller@17a00000 { 3474 compatible = "arm,gic-v3"; 3475 #address-cells = <2>; 3476 #size-cells = <2>; 3477 ranges; 3478 #interrupt-cells = <3>; 3479 interrupt-controller; 3480 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3481 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3482 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3483 3484 gic-its@17a40000 { 3485 compatible = "arm,gic-v3-its"; 3486 msi-controller; 3487 #msi-cells = <1>; 3488 reg = <0 0x17a40000 0 0x20000>; 3489 status = "disabled"; 3490 }; 3491 }; 3492 3493 watchdog@17c10000 { 3494 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3495 reg = <0 0x17c10000 0 0x1000>; 3496 clocks = <&sleep_clk>; 3497 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3498 }; 3499 3500 timer@17c20000 { 3501 #address-cells = <2>; 3502 #size-cells = <2>; 3503 ranges; 3504 compatible = "arm,armv7-timer-mem"; 3505 reg = <0 0x17c20000 0 0x1000>; 3506 3507 frame@17c21000 { 3508 frame-number = <0>; 3509 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3511 reg = <0 0x17c21000 0 0x1000>, 3512 <0 0x17c22000 0 0x1000>; 3513 }; 3514 3515 frame@17c23000 { 3516 frame-number = <1>; 3517 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3518 reg = <0 0x17c23000 0 0x1000>; 3519 status = "disabled"; 3520 }; 3521 3522 frame@17c25000 { 3523 frame-number = <2>; 3524 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3525 reg = <0 0x17c25000 0 0x1000>; 3526 status = "disabled"; 3527 }; 3528 3529 frame@17c27000 { 3530 frame-number = <3>; 3531 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3532 reg = <0 0x17c27000 0 0x1000>; 3533 status = "disabled"; 3534 }; 3535 3536 frame@17c29000 { 3537 frame-number = <4>; 3538 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3539 reg = <0 0x17c29000 0 0x1000>; 3540 status = "disabled"; 3541 }; 3542 3543 frame@17c2b000 { 3544 frame-number = <5>; 3545 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3546 reg = <0 0x17c2b000 0 0x1000>; 3547 status = "disabled"; 3548 }; 3549 3550 frame@17c2d000 { 3551 frame-number = <6>; 3552 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3553 reg = <0 0x17c2d000 0 0x1000>; 3554 status = "disabled"; 3555 }; 3556 }; 3557 3558 apps_rsc: rsc@18200000 { 3559 compatible = "qcom,rpmh-rsc"; 3560 reg = <0 0x18200000 0 0x10000>, 3561 <0 0x18210000 0 0x10000>, 3562 <0 0x18220000 0 0x10000>; 3563 reg-names = "drv-0", "drv-1", "drv-2"; 3564 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3565 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3566 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3567 qcom,tcs-offset = <0xd00>; 3568 qcom,drv-id = <2>; 3569 qcom,tcs-config = <ACTIVE_TCS 2>, 3570 <SLEEP_TCS 3>, 3571 <WAKE_TCS 3>, 3572 <CONTROL_TCS 1>; 3573 3574 apps_bcm_voter: bcm-voter { 3575 compatible = "qcom,bcm-voter"; 3576 }; 3577 3578 rpmhpd: power-controller { 3579 compatible = "qcom,sc7280-rpmhpd"; 3580 #power-domain-cells = <1>; 3581 operating-points-v2 = <&rpmhpd_opp_table>; 3582 3583 rpmhpd_opp_table: opp-table { 3584 compatible = "operating-points-v2"; 3585 3586 rpmhpd_opp_ret: opp1 { 3587 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3588 }; 3589 3590 rpmhpd_opp_low_svs: opp2 { 3591 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3592 }; 3593 3594 rpmhpd_opp_svs: opp3 { 3595 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3596 }; 3597 3598 rpmhpd_opp_svs_l1: opp4 { 3599 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3600 }; 3601 3602 rpmhpd_opp_svs_l2: opp5 { 3603 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3604 }; 3605 3606 rpmhpd_opp_nom: opp6 { 3607 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3608 }; 3609 3610 rpmhpd_opp_nom_l1: opp7 { 3611 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3612 }; 3613 3614 rpmhpd_opp_turbo: opp8 { 3615 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3616 }; 3617 3618 rpmhpd_opp_turbo_l1: opp9 { 3619 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3620 }; 3621 }; 3622 }; 3623 3624 rpmhcc: clock-controller { 3625 compatible = "qcom,sc7280-rpmh-clk"; 3626 clocks = <&xo_board>; 3627 clock-names = "xo"; 3628 #clock-cells = <1>; 3629 }; 3630 }; 3631 3632 cpufreq_hw: cpufreq@18591000 { 3633 compatible = "qcom,cpufreq-epss"; 3634 reg = <0 0x18591100 0 0x900>, 3635 <0 0x18592100 0 0x900>, 3636 <0 0x18593100 0 0x900>; 3637 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3638 clock-names = "xo", "alternate"; 3639 #freq-domain-cells = <1>; 3640 }; 3641 }; 3642 3643 thermal_zones: thermal-zones { 3644 cpu0-thermal { 3645 polling-delay-passive = <250>; 3646 polling-delay = <0>; 3647 3648 thermal-sensors = <&tsens0 1>; 3649 3650 trips { 3651 cpu0_alert0: trip-point0 { 3652 temperature = <90000>; 3653 hysteresis = <2000>; 3654 type = "passive"; 3655 }; 3656 3657 cpu0_alert1: trip-point1 { 3658 temperature = <95000>; 3659 hysteresis = <2000>; 3660 type = "passive"; 3661 }; 3662 3663 cpu0_crit: cpu-crit { 3664 temperature = <110000>; 3665 hysteresis = <0>; 3666 type = "critical"; 3667 }; 3668 }; 3669 3670 cooling-maps { 3671 map0 { 3672 trip = <&cpu0_alert0>; 3673 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3674 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3675 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3676 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3677 }; 3678 map1 { 3679 trip = <&cpu0_alert1>; 3680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3681 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3682 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3683 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3684 }; 3685 }; 3686 }; 3687 3688 cpu1-thermal { 3689 polling-delay-passive = <250>; 3690 polling-delay = <0>; 3691 3692 thermal-sensors = <&tsens0 2>; 3693 3694 trips { 3695 cpu1_alert0: trip-point0 { 3696 temperature = <90000>; 3697 hysteresis = <2000>; 3698 type = "passive"; 3699 }; 3700 3701 cpu1_alert1: trip-point1 { 3702 temperature = <95000>; 3703 hysteresis = <2000>; 3704 type = "passive"; 3705 }; 3706 3707 cpu1_crit: cpu-crit { 3708 temperature = <110000>; 3709 hysteresis = <0>; 3710 type = "critical"; 3711 }; 3712 }; 3713 3714 cooling-maps { 3715 map0 { 3716 trip = <&cpu1_alert0>; 3717 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3720 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3721 }; 3722 map1 { 3723 trip = <&cpu1_alert1>; 3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3728 }; 3729 }; 3730 }; 3731 3732 cpu2-thermal { 3733 polling-delay-passive = <250>; 3734 polling-delay = <0>; 3735 3736 thermal-sensors = <&tsens0 3>; 3737 3738 trips { 3739 cpu2_alert0: trip-point0 { 3740 temperature = <90000>; 3741 hysteresis = <2000>; 3742 type = "passive"; 3743 }; 3744 3745 cpu2_alert1: trip-point1 { 3746 temperature = <95000>; 3747 hysteresis = <2000>; 3748 type = "passive"; 3749 }; 3750 3751 cpu2_crit: cpu-crit { 3752 temperature = <110000>; 3753 hysteresis = <0>; 3754 type = "critical"; 3755 }; 3756 }; 3757 3758 cooling-maps { 3759 map0 { 3760 trip = <&cpu2_alert0>; 3761 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3764 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3765 }; 3766 map1 { 3767 trip = <&cpu2_alert1>; 3768 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3772 }; 3773 }; 3774 }; 3775 3776 cpu3-thermal { 3777 polling-delay-passive = <250>; 3778 polling-delay = <0>; 3779 3780 thermal-sensors = <&tsens0 4>; 3781 3782 trips { 3783 cpu3_alert0: trip-point0 { 3784 temperature = <90000>; 3785 hysteresis = <2000>; 3786 type = "passive"; 3787 }; 3788 3789 cpu3_alert1: trip-point1 { 3790 temperature = <95000>; 3791 hysteresis = <2000>; 3792 type = "passive"; 3793 }; 3794 3795 cpu3_crit: cpu-crit { 3796 temperature = <110000>; 3797 hysteresis = <0>; 3798 type = "critical"; 3799 }; 3800 }; 3801 3802 cooling-maps { 3803 map0 { 3804 trip = <&cpu3_alert0>; 3805 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3809 }; 3810 map1 { 3811 trip = <&cpu3_alert1>; 3812 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3816 }; 3817 }; 3818 }; 3819 3820 cpu4-thermal { 3821 polling-delay-passive = <250>; 3822 polling-delay = <0>; 3823 3824 thermal-sensors = <&tsens0 7>; 3825 3826 trips { 3827 cpu4_alert0: trip-point0 { 3828 temperature = <90000>; 3829 hysteresis = <2000>; 3830 type = "passive"; 3831 }; 3832 3833 cpu4_alert1: trip-point1 { 3834 temperature = <95000>; 3835 hysteresis = <2000>; 3836 type = "passive"; 3837 }; 3838 3839 cpu4_crit: cpu-crit { 3840 temperature = <110000>; 3841 hysteresis = <0>; 3842 type = "critical"; 3843 }; 3844 }; 3845 3846 cooling-maps { 3847 map0 { 3848 trip = <&cpu4_alert0>; 3849 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3853 }; 3854 map1 { 3855 trip = <&cpu4_alert1>; 3856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3860 }; 3861 }; 3862 }; 3863 3864 cpu5-thermal { 3865 polling-delay-passive = <250>; 3866 polling-delay = <0>; 3867 3868 thermal-sensors = <&tsens0 8>; 3869 3870 trips { 3871 cpu5_alert0: trip-point0 { 3872 temperature = <90000>; 3873 hysteresis = <2000>; 3874 type = "passive"; 3875 }; 3876 3877 cpu5_alert1: trip-point1 { 3878 temperature = <95000>; 3879 hysteresis = <2000>; 3880 type = "passive"; 3881 }; 3882 3883 cpu5_crit: cpu-crit { 3884 temperature = <110000>; 3885 hysteresis = <0>; 3886 type = "critical"; 3887 }; 3888 }; 3889 3890 cooling-maps { 3891 map0 { 3892 trip = <&cpu5_alert0>; 3893 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3897 }; 3898 map1 { 3899 trip = <&cpu5_alert1>; 3900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3904 }; 3905 }; 3906 }; 3907 3908 cpu6-thermal { 3909 polling-delay-passive = <250>; 3910 polling-delay = <0>; 3911 3912 thermal-sensors = <&tsens0 9>; 3913 3914 trips { 3915 cpu6_alert0: trip-point0 { 3916 temperature = <90000>; 3917 hysteresis = <2000>; 3918 type = "passive"; 3919 }; 3920 3921 cpu6_alert1: trip-point1 { 3922 temperature = <95000>; 3923 hysteresis = <2000>; 3924 type = "passive"; 3925 }; 3926 3927 cpu6_crit: cpu-crit { 3928 temperature = <110000>; 3929 hysteresis = <0>; 3930 type = "critical"; 3931 }; 3932 }; 3933 3934 cooling-maps { 3935 map0 { 3936 trip = <&cpu6_alert0>; 3937 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3940 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3941 }; 3942 map1 { 3943 trip = <&cpu6_alert1>; 3944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3948 }; 3949 }; 3950 }; 3951 3952 cpu7-thermal { 3953 polling-delay-passive = <250>; 3954 polling-delay = <0>; 3955 3956 thermal-sensors = <&tsens0 10>; 3957 3958 trips { 3959 cpu7_alert0: trip-point0 { 3960 temperature = <90000>; 3961 hysteresis = <2000>; 3962 type = "passive"; 3963 }; 3964 3965 cpu7_alert1: trip-point1 { 3966 temperature = <95000>; 3967 hysteresis = <2000>; 3968 type = "passive"; 3969 }; 3970 3971 cpu7_crit: cpu-crit { 3972 temperature = <110000>; 3973 hysteresis = <0>; 3974 type = "critical"; 3975 }; 3976 }; 3977 3978 cooling-maps { 3979 map0 { 3980 trip = <&cpu7_alert0>; 3981 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3984 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3985 }; 3986 map1 { 3987 trip = <&cpu7_alert1>; 3988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3992 }; 3993 }; 3994 }; 3995 3996 cpu8-thermal { 3997 polling-delay-passive = <250>; 3998 polling-delay = <0>; 3999 4000 thermal-sensors = <&tsens0 11>; 4001 4002 trips { 4003 cpu8_alert0: trip-point0 { 4004 temperature = <90000>; 4005 hysteresis = <2000>; 4006 type = "passive"; 4007 }; 4008 4009 cpu8_alert1: trip-point1 { 4010 temperature = <95000>; 4011 hysteresis = <2000>; 4012 type = "passive"; 4013 }; 4014 4015 cpu8_crit: cpu-crit { 4016 temperature = <110000>; 4017 hysteresis = <0>; 4018 type = "critical"; 4019 }; 4020 }; 4021 4022 cooling-maps { 4023 map0 { 4024 trip = <&cpu8_alert0>; 4025 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4029 }; 4030 map1 { 4031 trip = <&cpu8_alert1>; 4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4034 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4036 }; 4037 }; 4038 }; 4039 4040 cpu9-thermal { 4041 polling-delay-passive = <250>; 4042 polling-delay = <0>; 4043 4044 thermal-sensors = <&tsens0 12>; 4045 4046 trips { 4047 cpu9_alert0: trip-point0 { 4048 temperature = <90000>; 4049 hysteresis = <2000>; 4050 type = "passive"; 4051 }; 4052 4053 cpu9_alert1: trip-point1 { 4054 temperature = <95000>; 4055 hysteresis = <2000>; 4056 type = "passive"; 4057 }; 4058 4059 cpu9_crit: cpu-crit { 4060 temperature = <110000>; 4061 hysteresis = <0>; 4062 type = "critical"; 4063 }; 4064 }; 4065 4066 cooling-maps { 4067 map0 { 4068 trip = <&cpu9_alert0>; 4069 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4070 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4073 }; 4074 map1 { 4075 trip = <&cpu9_alert1>; 4076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4079 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4080 }; 4081 }; 4082 }; 4083 4084 cpu10-thermal { 4085 polling-delay-passive = <250>; 4086 polling-delay = <0>; 4087 4088 thermal-sensors = <&tsens0 13>; 4089 4090 trips { 4091 cpu10_alert0: trip-point0 { 4092 temperature = <90000>; 4093 hysteresis = <2000>; 4094 type = "passive"; 4095 }; 4096 4097 cpu10_alert1: trip-point1 { 4098 temperature = <95000>; 4099 hysteresis = <2000>; 4100 type = "passive"; 4101 }; 4102 4103 cpu10_crit: cpu-crit { 4104 temperature = <110000>; 4105 hysteresis = <0>; 4106 type = "critical"; 4107 }; 4108 }; 4109 4110 cooling-maps { 4111 map0 { 4112 trip = <&cpu10_alert0>; 4113 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4117 }; 4118 map1 { 4119 trip = <&cpu10_alert1>; 4120 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4121 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4124 }; 4125 }; 4126 }; 4127 4128 cpu11-thermal { 4129 polling-delay-passive = <250>; 4130 polling-delay = <0>; 4131 4132 thermal-sensors = <&tsens0 14>; 4133 4134 trips { 4135 cpu11_alert0: trip-point0 { 4136 temperature = <90000>; 4137 hysteresis = <2000>; 4138 type = "passive"; 4139 }; 4140 4141 cpu11_alert1: trip-point1 { 4142 temperature = <95000>; 4143 hysteresis = <2000>; 4144 type = "passive"; 4145 }; 4146 4147 cpu11_crit: cpu-crit { 4148 temperature = <110000>; 4149 hysteresis = <0>; 4150 type = "critical"; 4151 }; 4152 }; 4153 4154 cooling-maps { 4155 map0 { 4156 trip = <&cpu11_alert0>; 4157 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4161 }; 4162 map1 { 4163 trip = <&cpu11_alert1>; 4164 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4165 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4166 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4168 }; 4169 }; 4170 }; 4171 4172 aoss0-thermal { 4173 polling-delay-passive = <0>; 4174 polling-delay = <0>; 4175 4176 thermal-sensors = <&tsens0 0>; 4177 4178 trips { 4179 aoss0_alert0: trip-point0 { 4180 temperature = <90000>; 4181 hysteresis = <2000>; 4182 type = "hot"; 4183 }; 4184 4185 aoss0_crit: aoss0-crit { 4186 temperature = <110000>; 4187 hysteresis = <0>; 4188 type = "critical"; 4189 }; 4190 }; 4191 }; 4192 4193 aoss1-thermal { 4194 polling-delay-passive = <0>; 4195 polling-delay = <0>; 4196 4197 thermal-sensors = <&tsens1 0>; 4198 4199 trips { 4200 aoss1_alert0: trip-point0 { 4201 temperature = <90000>; 4202 hysteresis = <2000>; 4203 type = "hot"; 4204 }; 4205 4206 aoss1_crit: aoss1-crit { 4207 temperature = <110000>; 4208 hysteresis = <0>; 4209 type = "critical"; 4210 }; 4211 }; 4212 }; 4213 4214 cpuss0-thermal { 4215 polling-delay-passive = <0>; 4216 polling-delay = <0>; 4217 4218 thermal-sensors = <&tsens0 5>; 4219 4220 trips { 4221 cpuss0_alert0: trip-point0 { 4222 temperature = <90000>; 4223 hysteresis = <2000>; 4224 type = "hot"; 4225 }; 4226 cpuss0_crit: cluster0-crit { 4227 temperature = <110000>; 4228 hysteresis = <0>; 4229 type = "critical"; 4230 }; 4231 }; 4232 }; 4233 4234 cpuss1-thermal { 4235 polling-delay-passive = <0>; 4236 polling-delay = <0>; 4237 4238 thermal-sensors = <&tsens0 6>; 4239 4240 trips { 4241 cpuss1_alert0: trip-point0 { 4242 temperature = <90000>; 4243 hysteresis = <2000>; 4244 type = "hot"; 4245 }; 4246 cpuss1_crit: cluster0-crit { 4247 temperature = <110000>; 4248 hysteresis = <0>; 4249 type = "critical"; 4250 }; 4251 }; 4252 }; 4253 4254 gpuss0-thermal { 4255 polling-delay-passive = <100>; 4256 polling-delay = <0>; 4257 4258 thermal-sensors = <&tsens1 1>; 4259 4260 trips { 4261 gpuss0_alert0: trip-point0 { 4262 temperature = <95000>; 4263 hysteresis = <2000>; 4264 type = "passive"; 4265 }; 4266 4267 gpuss0_crit: gpuss0-crit { 4268 temperature = <110000>; 4269 hysteresis = <0>; 4270 type = "critical"; 4271 }; 4272 }; 4273 4274 cooling-maps { 4275 map0 { 4276 trip = <&gpuss0_alert0>; 4277 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4278 }; 4279 }; 4280 }; 4281 4282 gpuss1-thermal { 4283 polling-delay-passive = <100>; 4284 polling-delay = <0>; 4285 4286 thermal-sensors = <&tsens1 2>; 4287 4288 trips { 4289 gpuss1_alert0: trip-point0 { 4290 temperature = <95000>; 4291 hysteresis = <2000>; 4292 type = "passive"; 4293 }; 4294 4295 gpuss1_crit: gpuss1-crit { 4296 temperature = <110000>; 4297 hysteresis = <0>; 4298 type = "critical"; 4299 }; 4300 }; 4301 4302 cooling-maps { 4303 map0 { 4304 trip = <&gpuss1_alert0>; 4305 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4306 }; 4307 }; 4308 }; 4309 4310 nspss0-thermal { 4311 polling-delay-passive = <0>; 4312 polling-delay = <0>; 4313 4314 thermal-sensors = <&tsens1 3>; 4315 4316 trips { 4317 nspss0_alert0: trip-point0 { 4318 temperature = <90000>; 4319 hysteresis = <2000>; 4320 type = "hot"; 4321 }; 4322 4323 nspss0_crit: nspss0-crit { 4324 temperature = <110000>; 4325 hysteresis = <0>; 4326 type = "critical"; 4327 }; 4328 }; 4329 }; 4330 4331 nspss1-thermal { 4332 polling-delay-passive = <0>; 4333 polling-delay = <0>; 4334 4335 thermal-sensors = <&tsens1 4>; 4336 4337 trips { 4338 nspss1_alert0: trip-point0 { 4339 temperature = <90000>; 4340 hysteresis = <2000>; 4341 type = "hot"; 4342 }; 4343 4344 nspss1_crit: nspss1-crit { 4345 temperature = <110000>; 4346 hysteresis = <0>; 4347 type = "critical"; 4348 }; 4349 }; 4350 }; 4351 4352 video-thermal { 4353 polling-delay-passive = <0>; 4354 polling-delay = <0>; 4355 4356 thermal-sensors = <&tsens1 5>; 4357 4358 trips { 4359 video_alert0: trip-point0 { 4360 temperature = <90000>; 4361 hysteresis = <2000>; 4362 type = "hot"; 4363 }; 4364 4365 video_crit: video-crit { 4366 temperature = <110000>; 4367 hysteresis = <0>; 4368 type = "critical"; 4369 }; 4370 }; 4371 }; 4372 4373 ddr-thermal { 4374 polling-delay-passive = <0>; 4375 polling-delay = <0>; 4376 4377 thermal-sensors = <&tsens1 6>; 4378 4379 trips { 4380 ddr_alert0: trip-point0 { 4381 temperature = <90000>; 4382 hysteresis = <2000>; 4383 type = "hot"; 4384 }; 4385 4386 ddr_crit: ddr-crit { 4387 temperature = <110000>; 4388 hysteresis = <0>; 4389 type = "critical"; 4390 }; 4391 }; 4392 }; 4393 4394 mdmss0-thermal { 4395 polling-delay-passive = <0>; 4396 polling-delay = <0>; 4397 4398 thermal-sensors = <&tsens1 7>; 4399 4400 trips { 4401 mdmss0_alert0: trip-point0 { 4402 temperature = <90000>; 4403 hysteresis = <2000>; 4404 type = "hot"; 4405 }; 4406 4407 mdmss0_crit: mdmss0-crit { 4408 temperature = <110000>; 4409 hysteresis = <0>; 4410 type = "critical"; 4411 }; 4412 }; 4413 }; 4414 4415 mdmss1-thermal { 4416 polling-delay-passive = <0>; 4417 polling-delay = <0>; 4418 4419 thermal-sensors = <&tsens1 8>; 4420 4421 trips { 4422 mdmss1_alert0: trip-point0 { 4423 temperature = <90000>; 4424 hysteresis = <2000>; 4425 type = "hot"; 4426 }; 4427 4428 mdmss1_crit: mdmss1-crit { 4429 temperature = <110000>; 4430 hysteresis = <0>; 4431 type = "critical"; 4432 }; 4433 }; 4434 }; 4435 4436 mdmss2-thermal { 4437 polling-delay-passive = <0>; 4438 polling-delay = <0>; 4439 4440 thermal-sensors = <&tsens1 9>; 4441 4442 trips { 4443 mdmss2_alert0: trip-point0 { 4444 temperature = <90000>; 4445 hysteresis = <2000>; 4446 type = "hot"; 4447 }; 4448 4449 mdmss2_crit: mdmss2-crit { 4450 temperature = <110000>; 4451 hysteresis = <0>; 4452 type = "critical"; 4453 }; 4454 }; 4455 }; 4456 4457 mdmss3-thermal { 4458 polling-delay-passive = <0>; 4459 polling-delay = <0>; 4460 4461 thermal-sensors = <&tsens1 10>; 4462 4463 trips { 4464 mdmss3_alert0: trip-point0 { 4465 temperature = <90000>; 4466 hysteresis = <2000>; 4467 type = "hot"; 4468 }; 4469 4470 mdmss3_crit: mdmss3-crit { 4471 temperature = <110000>; 4472 hysteresis = <0>; 4473 type = "critical"; 4474 }; 4475 }; 4476 }; 4477 4478 camera0-thermal { 4479 polling-delay-passive = <0>; 4480 polling-delay = <0>; 4481 4482 thermal-sensors = <&tsens1 11>; 4483 4484 trips { 4485 camera0_alert0: trip-point0 { 4486 temperature = <90000>; 4487 hysteresis = <2000>; 4488 type = "hot"; 4489 }; 4490 4491 camera0_crit: camera0-crit { 4492 temperature = <110000>; 4493 hysteresis = <0>; 4494 type = "critical"; 4495 }; 4496 }; 4497 }; 4498 }; 4499 4500 timer { 4501 compatible = "arm,armv8-timer"; 4502 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4503 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4504 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4505 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4506 }; 4507}; 4508