1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 aliases { 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 i2c12 = &i2c12; 49 i2c13 = &i2c13; 50 i2c14 = &i2c14; 51 i2c15 = &i2c15; 52 mmc1 = &sdhc_1; 53 mmc2 = &sdhc_2; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 }; 71 72 clocks { 73 xo_board: xo-board { 74 compatible = "fixed-clock"; 75 clock-frequency = <76800000>; 76 #clock-cells = <0>; 77 }; 78 79 sleep_clk: sleep-clk { 80 compatible = "fixed-clock"; 81 clock-frequency = <32000>; 82 #clock-cells = <0>; 83 }; 84 }; 85 86 reserved-memory { 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 wlan_ce_mem: memory@4cd000 { 92 no-map; 93 reg = <0x0 0x004cd000 0x0 0x1000>; 94 }; 95 96 hyp_mem: memory@80000000 { 97 reg = <0x0 0x80000000 0x0 0x600000>; 98 no-map; 99 }; 100 101 xbl_mem: memory@80600000 { 102 reg = <0x0 0x80600000 0x0 0x200000>; 103 no-map; 104 }; 105 106 aop_mem: memory@80800000 { 107 reg = <0x0 0x80800000 0x0 0x60000>; 108 no-map; 109 }; 110 111 aop_cmd_db_mem: memory@80860000 { 112 reg = <0x0 0x80860000 0x0 0x20000>; 113 compatible = "qcom,cmd-db"; 114 no-map; 115 }; 116 117 reserved_xbl_uefi_log: memory@80880000 { 118 reg = <0x0 0x80884000 0x0 0x10000>; 119 no-map; 120 }; 121 122 sec_apps_mem: memory@808ff000 { 123 reg = <0x0 0x808ff000 0x0 0x1000>; 124 no-map; 125 }; 126 127 smem_mem: memory@80900000 { 128 reg = <0x0 0x80900000 0x0 0x200000>; 129 no-map; 130 }; 131 132 cpucp_mem: memory@80b00000 { 133 no-map; 134 reg = <0x0 0x80b00000 0x0 0x100000>; 135 }; 136 137 wlan_fw_mem: memory@80c00000 { 138 reg = <0x0 0x80c00000 0x0 0xc00000>; 139 no-map; 140 }; 141 142 video_mem: memory@8b200000 { 143 reg = <0x0 0x8b200000 0x0 0x500000>; 144 no-map; 145 }; 146 147 ipa_fw_mem: memory@8b700000 { 148 reg = <0 0x8b700000 0 0x10000>; 149 no-map; 150 }; 151 152 rmtfs_mem: memory@9c900000 { 153 compatible = "qcom,rmtfs-mem"; 154 reg = <0x0 0x9c900000 0x0 0x280000>; 155 no-map; 156 157 qcom,client-id = <1>; 158 qcom,vmid = <15>; 159 }; 160 }; 161 162 cpus { 163 #address-cells = <2>; 164 #size-cells = <0>; 165 166 CPU0: cpu@0 { 167 device_type = "cpu"; 168 compatible = "arm,kryo"; 169 reg = <0x0 0x0>; 170 enable-method = "psci"; 171 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 172 &LITTLE_CPU_SLEEP_1 173 &CLUSTER_SLEEP_0>; 174 next-level-cache = <&L2_0>; 175 operating-points-v2 = <&cpu0_opp_table>; 176 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 177 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 178 qcom,freq-domain = <&cpufreq_hw 0>; 179 #cooling-cells = <2>; 180 L2_0: l2-cache { 181 compatible = "cache"; 182 next-level-cache = <&L3_0>; 183 L3_0: l3-cache { 184 compatible = "cache"; 185 }; 186 }; 187 }; 188 189 CPU1: cpu@100 { 190 device_type = "cpu"; 191 compatible = "arm,kryo"; 192 reg = <0x0 0x100>; 193 enable-method = "psci"; 194 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 195 &LITTLE_CPU_SLEEP_1 196 &CLUSTER_SLEEP_0>; 197 next-level-cache = <&L2_100>; 198 operating-points-v2 = <&cpu0_opp_table>; 199 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 200 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 #cooling-cells = <2>; 203 L2_100: l2-cache { 204 compatible = "cache"; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 CPU2: cpu@200 { 210 device_type = "cpu"; 211 compatible = "arm,kryo"; 212 reg = <0x0 0x200>; 213 enable-method = "psci"; 214 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 215 &LITTLE_CPU_SLEEP_1 216 &CLUSTER_SLEEP_0>; 217 next-level-cache = <&L2_200>; 218 operating-points-v2 = <&cpu0_opp_table>; 219 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 220 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 #cooling-cells = <2>; 223 L2_200: l2-cache { 224 compatible = "cache"; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU3: cpu@300 { 230 device_type = "cpu"; 231 compatible = "arm,kryo"; 232 reg = <0x0 0x300>; 233 enable-method = "psci"; 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 235 &LITTLE_CPU_SLEEP_1 236 &CLUSTER_SLEEP_0>; 237 next-level-cache = <&L2_300>; 238 operating-points-v2 = <&cpu0_opp_table>; 239 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 240 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 qcom,freq-domain = <&cpufreq_hw 0>; 242 #cooling-cells = <2>; 243 L2_300: l2-cache { 244 compatible = "cache"; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 CPU4: cpu@400 { 250 device_type = "cpu"; 251 compatible = "arm,kryo"; 252 reg = <0x0 0x400>; 253 enable-method = "psci"; 254 cpu-idle-states = <&BIG_CPU_SLEEP_0 255 &BIG_CPU_SLEEP_1 256 &CLUSTER_SLEEP_0>; 257 next-level-cache = <&L2_400>; 258 operating-points-v2 = <&cpu4_opp_table>; 259 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 260 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 261 qcom,freq-domain = <&cpufreq_hw 1>; 262 #cooling-cells = <2>; 263 L2_400: l2-cache { 264 compatible = "cache"; 265 next-level-cache = <&L3_0>; 266 }; 267 }; 268 269 CPU5: cpu@500 { 270 device_type = "cpu"; 271 compatible = "arm,kryo"; 272 reg = <0x0 0x500>; 273 enable-method = "psci"; 274 cpu-idle-states = <&BIG_CPU_SLEEP_0 275 &BIG_CPU_SLEEP_1 276 &CLUSTER_SLEEP_0>; 277 next-level-cache = <&L2_500>; 278 operating-points-v2 = <&cpu4_opp_table>; 279 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 280 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 281 qcom,freq-domain = <&cpufreq_hw 1>; 282 #cooling-cells = <2>; 283 L2_500: l2-cache { 284 compatible = "cache"; 285 next-level-cache = <&L3_0>; 286 }; 287 }; 288 289 CPU6: cpu@600 { 290 device_type = "cpu"; 291 compatible = "arm,kryo"; 292 reg = <0x0 0x600>; 293 enable-method = "psci"; 294 cpu-idle-states = <&BIG_CPU_SLEEP_0 295 &BIG_CPU_SLEEP_1 296 &CLUSTER_SLEEP_0>; 297 next-level-cache = <&L2_600>; 298 operating-points-v2 = <&cpu4_opp_table>; 299 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 300 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 301 qcom,freq-domain = <&cpufreq_hw 1>; 302 #cooling-cells = <2>; 303 L2_600: l2-cache { 304 compatible = "cache"; 305 next-level-cache = <&L3_0>; 306 }; 307 }; 308 309 CPU7: cpu@700 { 310 device_type = "cpu"; 311 compatible = "arm,kryo"; 312 reg = <0x0 0x700>; 313 enable-method = "psci"; 314 cpu-idle-states = <&BIG_CPU_SLEEP_0 315 &BIG_CPU_SLEEP_1 316 &CLUSTER_SLEEP_0>; 317 next-level-cache = <&L2_700>; 318 operating-points-v2 = <&cpu7_opp_table>; 319 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 320 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 321 qcom,freq-domain = <&cpufreq_hw 2>; 322 #cooling-cells = <2>; 323 L2_700: l2-cache { 324 compatible = "cache"; 325 next-level-cache = <&L3_0>; 326 }; 327 }; 328 329 cpu-map { 330 cluster0 { 331 core0 { 332 cpu = <&CPU0>; 333 }; 334 335 core1 { 336 cpu = <&CPU1>; 337 }; 338 339 core2 { 340 cpu = <&CPU2>; 341 }; 342 343 core3 { 344 cpu = <&CPU3>; 345 }; 346 347 core4 { 348 cpu = <&CPU4>; 349 }; 350 351 core5 { 352 cpu = <&CPU5>; 353 }; 354 355 core6 { 356 cpu = <&CPU6>; 357 }; 358 359 core7 { 360 cpu = <&CPU7>; 361 }; 362 }; 363 }; 364 365 idle-states { 366 entry-method = "psci"; 367 368 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 369 compatible = "arm,idle-state"; 370 idle-state-name = "little-power-down"; 371 arm,psci-suspend-param = <0x40000003>; 372 entry-latency-us = <549>; 373 exit-latency-us = <901>; 374 min-residency-us = <1774>; 375 local-timer-stop; 376 }; 377 378 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 379 compatible = "arm,idle-state"; 380 idle-state-name = "little-rail-power-down"; 381 arm,psci-suspend-param = <0x40000004>; 382 entry-latency-us = <702>; 383 exit-latency-us = <915>; 384 min-residency-us = <4001>; 385 local-timer-stop; 386 }; 387 388 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 389 compatible = "arm,idle-state"; 390 idle-state-name = "big-power-down"; 391 arm,psci-suspend-param = <0x40000003>; 392 entry-latency-us = <523>; 393 exit-latency-us = <1244>; 394 min-residency-us = <2207>; 395 local-timer-stop; 396 }; 397 398 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 399 compatible = "arm,idle-state"; 400 idle-state-name = "big-rail-power-down"; 401 arm,psci-suspend-param = <0x40000004>; 402 entry-latency-us = <526>; 403 exit-latency-us = <1854>; 404 min-residency-us = <5555>; 405 local-timer-stop; 406 }; 407 408 CLUSTER_SLEEP_0: cluster-sleep-0 { 409 compatible = "arm,idle-state"; 410 idle-state-name = "cluster-power-down"; 411 arm,psci-suspend-param = <0x40003444>; 412 entry-latency-us = <3263>; 413 exit-latency-us = <6562>; 414 min-residency-us = <9926>; 415 local-timer-stop; 416 }; 417 }; 418 }; 419 420 cpu0_opp_table: opp-table-cpu0 { 421 compatible = "operating-points-v2"; 422 opp-shared; 423 424 cpu0_opp_300mhz: opp-300000000 { 425 opp-hz = /bits/ 64 <300000000>; 426 opp-peak-kBps = <800000 9600000>; 427 }; 428 429 cpu0_opp_691mhz: opp-691200000 { 430 opp-hz = /bits/ 64 <691200000>; 431 opp-peak-kBps = <800000 17817600>; 432 }; 433 434 cpu0_opp_806mhz: opp-806400000 { 435 opp-hz = /bits/ 64 <806400000>; 436 opp-peak-kBps = <800000 20889600>; 437 }; 438 439 cpu0_opp_941mhz: opp-940800000 { 440 opp-hz = /bits/ 64 <940800000>; 441 opp-peak-kBps = <1804000 24576000>; 442 }; 443 444 cpu0_opp_1152mhz: opp-1152000000 { 445 opp-hz = /bits/ 64 <1152000000>; 446 opp-peak-kBps = <2188000 27033600>; 447 }; 448 449 cpu0_opp_1325mhz: opp-1324800000 { 450 opp-hz = /bits/ 64 <1324800000>; 451 opp-peak-kBps = <2188000 33792000>; 452 }; 453 454 cpu0_opp_1517mhz: opp-1516800000 { 455 opp-hz = /bits/ 64 <1516800000>; 456 opp-peak-kBps = <3072000 38092800>; 457 }; 458 459 cpu0_opp_1651mhz: opp-1651200000 { 460 opp-hz = /bits/ 64 <1651200000>; 461 opp-peak-kBps = <3072000 41779200>; 462 }; 463 464 cpu0_opp_1805mhz: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <4068000 48537600>; 467 }; 468 469 cpu0_opp_1958mhz: opp-1958400000 { 470 opp-hz = /bits/ 64 <1958400000>; 471 opp-peak-kBps = <4068000 48537600>; 472 }; 473 474 cpu0_opp_2016mhz: opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <6220000 48537600>; 477 }; 478 }; 479 480 cpu4_opp_table: opp-table-cpu4 { 481 compatible = "operating-points-v2"; 482 opp-shared; 483 484 cpu4_opp_691mhz: opp-691200000 { 485 opp-hz = /bits/ 64 <691200000>; 486 opp-peak-kBps = <1804000 9600000>; 487 }; 488 489 cpu4_opp_941mhz: opp-940800000 { 490 opp-hz = /bits/ 64 <940800000>; 491 opp-peak-kBps = <2188000 17817600>; 492 }; 493 494 cpu4_opp_1229mhz: opp-1228800000 { 495 opp-hz = /bits/ 64 <1228800000>; 496 opp-peak-kBps = <4068000 24576000>; 497 }; 498 499 cpu4_opp_1344mhz: opp-1344000000 { 500 opp-hz = /bits/ 64 <1344000000>; 501 opp-peak-kBps = <4068000 24576000>; 502 }; 503 504 cpu4_opp_1517mhz: opp-1516800000 { 505 opp-hz = /bits/ 64 <1516800000>; 506 opp-peak-kBps = <4068000 24576000>; 507 }; 508 509 cpu4_opp_1651mhz: opp-1651200000 { 510 opp-hz = /bits/ 64 <1651200000>; 511 opp-peak-kBps = <6220000 38092800>; 512 }; 513 514 cpu4_opp_1901mhz: opp-1900800000 { 515 opp-hz = /bits/ 64 <1900800000>; 516 opp-peak-kBps = <6220000 44851200>; 517 }; 518 519 cpu4_opp_2054mhz: opp-2054400000 { 520 opp-hz = /bits/ 64 <2054400000>; 521 opp-peak-kBps = <6220000 44851200>; 522 }; 523 524 cpu4_opp_2112mhz: opp-2112000000 { 525 opp-hz = /bits/ 64 <2112000000>; 526 opp-peak-kBps = <6220000 44851200>; 527 }; 528 529 cpu4_opp_2131mhz: opp-2131200000 { 530 opp-hz = /bits/ 64 <2131200000>; 531 opp-peak-kBps = <6220000 44851200>; 532 }; 533 534 cpu4_opp_2208mhz: opp-2208000000 { 535 opp-hz = /bits/ 64 <2208000000>; 536 opp-peak-kBps = <6220000 44851200>; 537 }; 538 539 cpu4_opp_2400mhz: opp-2400000000 { 540 opp-hz = /bits/ 64 <2400000000>; 541 opp-peak-kBps = <8532000 48537600>; 542 }; 543 544 cpu4_opp_2611mhz: opp-2611200000 { 545 opp-hz = /bits/ 64 <2611200000>; 546 opp-peak-kBps = <8532000 48537600>; 547 }; 548 }; 549 550 cpu7_opp_table: opp-table-cpu7 { 551 compatible = "operating-points-v2"; 552 opp-shared; 553 554 cpu7_opp_806mhz: opp-806400000 { 555 opp-hz = /bits/ 64 <806400000>; 556 opp-peak-kBps = <1804000 9600000>; 557 }; 558 559 cpu7_opp_1056mhz: opp-1056000000 { 560 opp-hz = /bits/ 64 <1056000000>; 561 opp-peak-kBps = <2188000 17817600>; 562 }; 563 564 cpu7_opp_1325mhz: opp-1324800000 { 565 opp-hz = /bits/ 64 <1324800000>; 566 opp-peak-kBps = <4068000 24576000>; 567 }; 568 569 cpu7_opp_1517mhz: opp-1516800000 { 570 opp-hz = /bits/ 64 <1516800000>; 571 opp-peak-kBps = <4068000 24576000>; 572 }; 573 574 cpu7_opp_1766mhz: opp-1766400000 { 575 opp-hz = /bits/ 64 <1766400000>; 576 opp-peak-kBps = <6220000 38092800>; 577 }; 578 579 cpu7_opp_1862mhz: opp-1862400000 { 580 opp-hz = /bits/ 64 <1862400000>; 581 opp-peak-kBps = <6220000 38092800>; 582 }; 583 584 cpu7_opp_2035mhz: opp-2035200000 { 585 opp-hz = /bits/ 64 <2035200000>; 586 opp-peak-kBps = <6220000 38092800>; 587 }; 588 589 cpu7_opp_2112mhz: opp-2112000000 { 590 opp-hz = /bits/ 64 <2112000000>; 591 opp-peak-kBps = <6220000 44851200>; 592 }; 593 594 cpu7_opp_2208mhz: opp-2208000000 { 595 opp-hz = /bits/ 64 <2208000000>; 596 opp-peak-kBps = <6220000 44851200>; 597 }; 598 599 cpu7_opp_2381mhz: opp-2380800000 { 600 opp-hz = /bits/ 64 <2380800000>; 601 opp-peak-kBps = <6832000 44851200>; 602 }; 603 604 cpu7_opp_2400mhz: opp-2400000000 { 605 opp-hz = /bits/ 64 <2400000000>; 606 opp-peak-kBps = <8532000 48537600>; 607 }; 608 609 cpu7_opp_2515mhz: opp-2515200000 { 610 opp-hz = /bits/ 64 <2515200000>; 611 opp-peak-kBps = <8532000 48537600>; 612 }; 613 614 cpu7_opp_2707mhz: opp-2707200000 { 615 opp-hz = /bits/ 64 <2707200000>; 616 opp-peak-kBps = <8532000 48537600>; 617 }; 618 619 cpu7_opp_3014mhz: opp-3014400000 { 620 opp-hz = /bits/ 64 <3014400000>; 621 opp-peak-kBps = <8532000 48537600>; 622 }; 623 }; 624 625 memory@80000000 { 626 device_type = "memory"; 627 /* We expect the bootloader to fill in the size */ 628 reg = <0 0x80000000 0 0>; 629 }; 630 631 firmware { 632 scm { 633 compatible = "qcom,scm-sc7280", "qcom,scm"; 634 }; 635 }; 636 637 clk_virt: interconnect { 638 compatible = "qcom,sc7280-clk-virt"; 639 #interconnect-cells = <2>; 640 qcom,bcm-voters = <&apps_bcm_voter>; 641 }; 642 643 smem { 644 compatible = "qcom,smem"; 645 memory-region = <&smem_mem>; 646 hwlocks = <&tcsr_mutex 3>; 647 }; 648 649 smp2p-adsp { 650 compatible = "qcom,smp2p"; 651 qcom,smem = <443>, <429>; 652 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 653 IPCC_MPROC_SIGNAL_SMP2P 654 IRQ_TYPE_EDGE_RISING>; 655 mboxes = <&ipcc IPCC_CLIENT_LPASS 656 IPCC_MPROC_SIGNAL_SMP2P>; 657 658 qcom,local-pid = <0>; 659 qcom,remote-pid = <2>; 660 661 adsp_smp2p_out: master-kernel { 662 qcom,entry-name = "master-kernel"; 663 #qcom,smem-state-cells = <1>; 664 }; 665 666 adsp_smp2p_in: slave-kernel { 667 qcom,entry-name = "slave-kernel"; 668 interrupt-controller; 669 #interrupt-cells = <2>; 670 }; 671 }; 672 673 smp2p-cdsp { 674 compatible = "qcom,smp2p"; 675 qcom,smem = <94>, <432>; 676 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 677 IPCC_MPROC_SIGNAL_SMP2P 678 IRQ_TYPE_EDGE_RISING>; 679 mboxes = <&ipcc IPCC_CLIENT_CDSP 680 IPCC_MPROC_SIGNAL_SMP2P>; 681 682 qcom,local-pid = <0>; 683 qcom,remote-pid = <5>; 684 685 cdsp_smp2p_out: master-kernel { 686 qcom,entry-name = "master-kernel"; 687 #qcom,smem-state-cells = <1>; 688 }; 689 690 cdsp_smp2p_in: slave-kernel { 691 qcom,entry-name = "slave-kernel"; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 }; 695 }; 696 697 smp2p-mpss { 698 compatible = "qcom,smp2p"; 699 qcom,smem = <435>, <428>; 700 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 701 IPCC_MPROC_SIGNAL_SMP2P 702 IRQ_TYPE_EDGE_RISING>; 703 mboxes = <&ipcc IPCC_CLIENT_MPSS 704 IPCC_MPROC_SIGNAL_SMP2P>; 705 706 qcom,local-pid = <0>; 707 qcom,remote-pid = <1>; 708 709 modem_smp2p_out: master-kernel { 710 qcom,entry-name = "master-kernel"; 711 #qcom,smem-state-cells = <1>; 712 }; 713 714 modem_smp2p_in: slave-kernel { 715 qcom,entry-name = "slave-kernel"; 716 interrupt-controller; 717 #interrupt-cells = <2>; 718 }; 719 720 ipa_smp2p_out: ipa-ap-to-modem { 721 qcom,entry-name = "ipa"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 ipa_smp2p_in: ipa-modem-to-ap { 726 qcom,entry-name = "ipa"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 }; 731 732 smp2p-wpss { 733 compatible = "qcom,smp2p"; 734 qcom,smem = <617>, <616>; 735 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 736 IPCC_MPROC_SIGNAL_SMP2P 737 IRQ_TYPE_EDGE_RISING>; 738 mboxes = <&ipcc IPCC_CLIENT_WPSS 739 IPCC_MPROC_SIGNAL_SMP2P>; 740 741 qcom,local-pid = <0>; 742 qcom,remote-pid = <13>; 743 744 wpss_smp2p_out: master-kernel { 745 qcom,entry-name = "master-kernel"; 746 #qcom,smem-state-cells = <1>; 747 }; 748 749 wpss_smp2p_in: slave-kernel { 750 qcom,entry-name = "slave-kernel"; 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 }; 754 }; 755 756 pmu { 757 compatible = "arm,armv8-pmuv3"; 758 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 759 }; 760 761 psci { 762 compatible = "arm,psci-1.0"; 763 method = "smc"; 764 }; 765 766 qspi_opp_table: opp-table-qspi { 767 compatible = "operating-points-v2"; 768 769 opp-75000000 { 770 opp-hz = /bits/ 64 <75000000>; 771 required-opps = <&rpmhpd_opp_low_svs>; 772 }; 773 774 opp-150000000 { 775 opp-hz = /bits/ 64 <150000000>; 776 required-opps = <&rpmhpd_opp_svs>; 777 }; 778 779 opp-200000000 { 780 opp-hz = /bits/ 64 <200000000>; 781 required-opps = <&rpmhpd_opp_svs_l1>; 782 }; 783 784 opp-300000000 { 785 opp-hz = /bits/ 64 <300000000>; 786 required-opps = <&rpmhpd_opp_nom>; 787 }; 788 }; 789 790 qup_opp_table: opp-table-qup { 791 compatible = "operating-points-v2"; 792 793 opp-75000000 { 794 opp-hz = /bits/ 64 <75000000>; 795 required-opps = <&rpmhpd_opp_low_svs>; 796 }; 797 798 opp-100000000 { 799 opp-hz = /bits/ 64 <100000000>; 800 required-opps = <&rpmhpd_opp_svs>; 801 }; 802 803 opp-128000000 { 804 opp-hz = /bits/ 64 <128000000>; 805 required-opps = <&rpmhpd_opp_nom>; 806 }; 807 }; 808 809 soc: soc@0 { 810 #address-cells = <2>; 811 #size-cells = <2>; 812 ranges = <0 0 0 0 0x10 0>; 813 dma-ranges = <0 0 0 0 0x10 0>; 814 compatible = "simple-bus"; 815 816 gcc: clock-controller@100000 { 817 compatible = "qcom,gcc-sc7280"; 818 reg = <0 0x00100000 0 0x1f0000>; 819 clocks = <&rpmhcc RPMH_CXO_CLK>, 820 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 821 <0>, <&pcie1_lane>, 822 <0>, <0>, <0>, <0>; 823 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 824 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 825 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 826 "ufs_phy_tx_symbol_0_clk", 827 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 828 #clock-cells = <1>; 829 #reset-cells = <1>; 830 #power-domain-cells = <1>; 831 }; 832 833 ipcc: mailbox@408000 { 834 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 835 reg = <0 0x00408000 0 0x1000>; 836 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 837 interrupt-controller; 838 #interrupt-cells = <3>; 839 #mbox-cells = <2>; 840 }; 841 842 qfprom: efuse@784000 { 843 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 844 reg = <0 0x00784000 0 0xa20>, 845 <0 0x00780000 0 0xa20>, 846 <0 0x00782000 0 0x120>, 847 <0 0x00786000 0 0x1fff>; 848 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 849 clock-names = "core"; 850 power-domains = <&rpmhpd SC7280_MX>; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 854 gpu_speed_bin: gpu_speed_bin@1e9 { 855 reg = <0x1e9 0x2>; 856 bits = <5 8>; 857 }; 858 }; 859 860 sdhc_1: mmc@7c4000 { 861 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 862 pinctrl-names = "default", "sleep"; 863 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 864 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 865 status = "disabled"; 866 867 reg = <0 0x007c4000 0 0x1000>, 868 <0 0x007c5000 0 0x1000>; 869 reg-names = "hc", "cqhci"; 870 871 iommus = <&apps_smmu 0xc0 0x0>; 872 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "hc_irq", "pwr_irq"; 875 876 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 877 <&gcc GCC_SDCC1_APPS_CLK>, 878 <&rpmhcc RPMH_CXO_CLK>; 879 clock-names = "iface", "core", "xo"; 880 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 881 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 882 interconnect-names = "sdhc-ddr","cpu-sdhc"; 883 power-domains = <&rpmhpd SC7280_CX>; 884 operating-points-v2 = <&sdhc1_opp_table>; 885 886 bus-width = <8>; 887 supports-cqe; 888 889 qcom,dll-config = <0x0007642c>; 890 qcom,ddr-config = <0x80040868>; 891 892 mmc-ddr-1_8v; 893 mmc-hs200-1_8v; 894 mmc-hs400-1_8v; 895 mmc-hs400-enhanced-strobe; 896 897 resets = <&gcc GCC_SDCC1_BCR>; 898 899 sdhc1_opp_table: opp-table { 900 compatible = "operating-points-v2"; 901 902 opp-100000000 { 903 opp-hz = /bits/ 64 <100000000>; 904 required-opps = <&rpmhpd_opp_low_svs>; 905 opp-peak-kBps = <1800000 400000>; 906 opp-avg-kBps = <100000 0>; 907 }; 908 909 opp-384000000 { 910 opp-hz = /bits/ 64 <384000000>; 911 required-opps = <&rpmhpd_opp_nom>; 912 opp-peak-kBps = <5400000 1600000>; 913 opp-avg-kBps = <390000 0>; 914 }; 915 }; 916 917 }; 918 919 gpi_dma0: dma-controller@900000 { 920 #dma-cells = <3>; 921 compatible = "qcom,sc7280-gpi-dma"; 922 reg = <0 0x00900000 0 0x60000>; 923 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 935 dma-channels = <12>; 936 dma-channel-mask = <0x7f>; 937 iommus = <&apps_smmu 0x0136 0x0>; 938 status = "disabled"; 939 }; 940 941 qupv3_id_0: geniqup@9c0000 { 942 compatible = "qcom,geni-se-qup"; 943 reg = <0 0x009c0000 0 0x2000>; 944 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 945 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 946 clock-names = "m-ahb", "s-ahb"; 947 #address-cells = <2>; 948 #size-cells = <2>; 949 ranges; 950 iommus = <&apps_smmu 0x123 0x0>; 951 status = "disabled"; 952 953 i2c0: i2c@980000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0 0x00980000 0 0x4000>; 956 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 957 clock-names = "se"; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c0_data_clk>; 960 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 964 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 965 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", 967 "qup-memory"; 968 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 969 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 970 dma-names = "tx", "rx"; 971 status = "disabled"; 972 }; 973 974 spi0: spi@980000 { 975 compatible = "qcom,geni-spi"; 976 reg = <0 0x00980000 0 0x4000>; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 978 clock-names = "se"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 981 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 power-domains = <&rpmhpd SC7280_CX>; 985 operating-points-v2 = <&qup_opp_table>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 988 interconnect-names = "qup-core", "qup-config"; 989 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 990 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 991 dma-names = "tx", "rx"; 992 status = "disabled"; 993 }; 994 995 uart0: serial@980000 { 996 compatible = "qcom,geni-uart"; 997 reg = <0 0x00980000 0 0x4000>; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 999 clock-names = "se"; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1002 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1003 power-domains = <&rpmhpd SC7280_CX>; 1004 operating-points-v2 = <&qup_opp_table>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1007 interconnect-names = "qup-core", "qup-config"; 1008 status = "disabled"; 1009 }; 1010 1011 i2c1: i2c@984000 { 1012 compatible = "qcom,geni-i2c"; 1013 reg = <0 0x00984000 0 0x4000>; 1014 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1015 clock-names = "se"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_i2c1_data_clk>; 1018 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1022 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1023 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1024 interconnect-names = "qup-core", "qup-config", 1025 "qup-memory"; 1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1027 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1028 dma-names = "tx", "rx"; 1029 status = "disabled"; 1030 }; 1031 1032 spi1: spi@984000 { 1033 compatible = "qcom,geni-spi"; 1034 reg = <0 0x00984000 0 0x4000>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1036 clock-names = "se"; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1039 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 power-domains = <&rpmhpd SC7280_CX>; 1043 operating-points-v2 = <&qup_opp_table>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1046 interconnect-names = "qup-core", "qup-config"; 1047 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1048 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1049 dma-names = "tx", "rx"; 1050 status = "disabled"; 1051 }; 1052 1053 uart1: serial@984000 { 1054 compatible = "qcom,geni-uart"; 1055 reg = <0 0x00984000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1060 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&rpmhpd SC7280_CX>; 1062 operating-points-v2 = <&qup_opp_table>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 status = "disabled"; 1067 }; 1068 1069 i2c2: i2c@988000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0 0x00988000 0 0x4000>; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1073 clock-names = "se"; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_i2c2_data_clk>; 1076 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1081 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1082 interconnect-names = "qup-core", "qup-config", 1083 "qup-memory"; 1084 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1085 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1086 dma-names = "tx", "rx"; 1087 status = "disabled"; 1088 }; 1089 1090 spi2: spi@988000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x00988000 0 0x4000>; 1093 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1094 clock-names = "se"; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1097 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 power-domains = <&rpmhpd SC7280_CX>; 1101 operating-points-v2 = <&qup_opp_table>; 1102 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1103 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1104 interconnect-names = "qup-core", "qup-config"; 1105 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1106 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1107 dma-names = "tx", "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 uart2: serial@988000 { 1112 compatible = "qcom,geni-uart"; 1113 reg = <0 0x00988000 0 0x4000>; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1115 clock-names = "se"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1118 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1119 power-domains = <&rpmhpd SC7280_CX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 status = "disabled"; 1125 }; 1126 1127 i2c3: i2c@98c000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x0098c000 0 0x4000>; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1131 clock-names = "se"; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c3_data_clk>; 1134 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1138 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1139 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1140 interconnect-names = "qup-core", "qup-config", 1141 "qup-memory"; 1142 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1143 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1144 dma-names = "tx", "rx"; 1145 status = "disabled"; 1146 }; 1147 1148 spi3: spi@98c000 { 1149 compatible = "qcom,geni-spi"; 1150 reg = <0 0x0098c000 0 0x4000>; 1151 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1152 clock-names = "se"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1155 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 power-domains = <&rpmhpd SC7280_CX>; 1159 operating-points-v2 = <&qup_opp_table>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1161 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1162 interconnect-names = "qup-core", "qup-config"; 1163 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1164 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1165 dma-names = "tx", "rx"; 1166 status = "disabled"; 1167 }; 1168 1169 uart3: serial@98c000 { 1170 compatible = "qcom,geni-uart"; 1171 reg = <0 0x0098c000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1176 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC7280_CX>; 1178 operating-points-v2 = <&qup_opp_table>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1181 interconnect-names = "qup-core", "qup-config"; 1182 status = "disabled"; 1183 }; 1184 1185 i2c4: i2c@990000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x00990000 0 0x4000>; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1189 clock-names = "se"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_i2c4_data_clk>; 1192 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1196 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1197 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1198 interconnect-names = "qup-core", "qup-config", 1199 "qup-memory"; 1200 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 status = "disabled"; 1204 }; 1205 1206 spi4: spi@990000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0 0x00990000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1213 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 power-domains = <&rpmhpd SC7280_CX>; 1217 operating-points-v2 = <&qup_opp_table>; 1218 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1219 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1220 interconnect-names = "qup-core", "qup-config"; 1221 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1222 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1223 dma-names = "tx", "rx"; 1224 status = "disabled"; 1225 }; 1226 1227 uart4: serial@990000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00990000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1234 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC7280_CX>; 1236 operating-points-v2 = <&qup_opp_table>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c5: i2c@994000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0 0x00994000 0 0x4000>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1247 clock-names = "se"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c5_data_clk>; 1250 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1256 interconnect-names = "qup-core", "qup-config", 1257 "qup-memory"; 1258 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1259 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1260 dma-names = "tx", "rx"; 1261 status = "disabled"; 1262 }; 1263 1264 spi5: spi@994000 { 1265 compatible = "qcom,geni-spi"; 1266 reg = <0 0x00994000 0 0x4000>; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1268 clock-names = "se"; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1271 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 power-domains = <&rpmhpd SC7280_CX>; 1275 operating-points-v2 = <&qup_opp_table>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1278 interconnect-names = "qup-core", "qup-config"; 1279 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1280 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1281 dma-names = "tx", "rx"; 1282 status = "disabled"; 1283 }; 1284 1285 uart5: serial@994000 { 1286 compatible = "qcom,geni-uart"; 1287 reg = <0 0x00994000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1292 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd SC7280_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1297 interconnect-names = "qup-core", "qup-config"; 1298 status = "disabled"; 1299 }; 1300 1301 i2c6: i2c@998000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0 0x00998000 0 0x4000>; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1305 clock-names = "se"; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_i2c6_data_clk>; 1308 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1312 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1313 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1314 interconnect-names = "qup-core", "qup-config", 1315 "qup-memory"; 1316 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1317 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1318 dma-names = "tx", "rx"; 1319 status = "disabled"; 1320 }; 1321 1322 spi6: spi@998000 { 1323 compatible = "qcom,geni-spi"; 1324 reg = <0 0x00998000 0 0x4000>; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1326 clock-names = "se"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1329 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 power-domains = <&rpmhpd SC7280_CX>; 1333 operating-points-v2 = <&qup_opp_table>; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1335 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1336 interconnect-names = "qup-core", "qup-config"; 1337 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1338 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1339 dma-names = "tx", "rx"; 1340 status = "disabled"; 1341 }; 1342 1343 uart6: serial@998000 { 1344 compatible = "qcom,geni-uart"; 1345 reg = <0 0x00998000 0 0x4000>; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1347 clock-names = "se"; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1350 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1351 power-domains = <&rpmhpd SC7280_CX>; 1352 operating-points-v2 = <&qup_opp_table>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1355 interconnect-names = "qup-core", "qup-config"; 1356 status = "disabled"; 1357 }; 1358 1359 i2c7: i2c@99c000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x0099c000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1363 clock-names = "se"; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&qup_i2c7_data_clk>; 1366 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1370 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1371 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1372 interconnect-names = "qup-core", "qup-config", 1373 "qup-memory"; 1374 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 status = "disabled"; 1378 }; 1379 1380 spi7: spi@99c000 { 1381 compatible = "qcom,geni-spi"; 1382 reg = <0 0x0099c000 0 0x4000>; 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1384 clock-names = "se"; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1387 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 power-domains = <&rpmhpd SC7280_CX>; 1391 operating-points-v2 = <&qup_opp_table>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1396 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1397 dma-names = "tx", "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 uart7: serial@99c000 { 1402 compatible = "qcom,geni-uart"; 1403 reg = <0 0x0099c000 0 0x4000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1405 clock-names = "se"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC7280_CX>; 1410 operating-points-v2 = <&qup_opp_table>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1413 interconnect-names = "qup-core", "qup-config"; 1414 status = "disabled"; 1415 }; 1416 }; 1417 1418 gpi_dma1: dma-controller@a00000 { 1419 #dma-cells = <3>; 1420 compatible = "qcom,sc7280-gpi-dma"; 1421 reg = <0 0x00a00000 0 0x60000>; 1422 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1434 dma-channels = <12>; 1435 dma-channel-mask = <0x1e>; 1436 iommus = <&apps_smmu 0x56 0x0>; 1437 status = "disabled"; 1438 }; 1439 1440 qupv3_id_1: geniqup@ac0000 { 1441 compatible = "qcom,geni-se-qup"; 1442 reg = <0 0x00ac0000 0 0x2000>; 1443 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1444 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1445 clock-names = "m-ahb", "s-ahb"; 1446 #address-cells = <2>; 1447 #size-cells = <2>; 1448 ranges; 1449 iommus = <&apps_smmu 0x43 0x0>; 1450 status = "disabled"; 1451 1452 i2c8: i2c@a80000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00a80000 0 0x4000>; 1455 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1456 clock-names = "se"; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_i2c8_data_clk>; 1459 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1463 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1464 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1465 interconnect-names = "qup-core", "qup-config", 1466 "qup-memory"; 1467 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1468 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1469 dma-names = "tx", "rx"; 1470 status = "disabled"; 1471 }; 1472 1473 spi8: spi@a80000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0x00a80000 0 0x4000>; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1477 clock-names = "se"; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1480 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 power-domains = <&rpmhpd SC7280_CX>; 1484 operating-points-v2 = <&qup_opp_table>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1487 interconnect-names = "qup-core", "qup-config"; 1488 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1489 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1490 dma-names = "tx", "rx"; 1491 status = "disabled"; 1492 }; 1493 1494 uart8: serial@a80000 { 1495 compatible = "qcom,geni-uart"; 1496 reg = <0 0x00a80000 0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1498 clock-names = "se"; 1499 pinctrl-names = "default"; 1500 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1501 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1502 power-domains = <&rpmhpd SC7280_CX>; 1503 operating-points-v2 = <&qup_opp_table>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1506 interconnect-names = "qup-core", "qup-config"; 1507 status = "disabled"; 1508 }; 1509 1510 i2c9: i2c@a84000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0 0x00a84000 0 0x4000>; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1514 clock-names = "se"; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&qup_i2c9_data_clk>; 1517 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1523 interconnect-names = "qup-core", "qup-config", 1524 "qup-memory"; 1525 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1526 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1527 dma-names = "tx", "rx"; 1528 status = "disabled"; 1529 }; 1530 1531 spi9: spi@a84000 { 1532 compatible = "qcom,geni-spi"; 1533 reg = <0 0x00a84000 0 0x4000>; 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1535 clock-names = "se"; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1538 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 power-domains = <&rpmhpd SC7280_CX>; 1542 operating-points-v2 = <&qup_opp_table>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1545 interconnect-names = "qup-core", "qup-config"; 1546 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1547 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1548 dma-names = "tx", "rx"; 1549 status = "disabled"; 1550 }; 1551 1552 uart9: serial@a84000 { 1553 compatible = "qcom,geni-uart"; 1554 reg = <0 0x00a84000 0 0x4000>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1556 clock-names = "se"; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1559 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1560 power-domains = <&rpmhpd SC7280_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1564 interconnect-names = "qup-core", "qup-config"; 1565 status = "disabled"; 1566 }; 1567 1568 i2c10: i2c@a88000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00a88000 0 0x4000>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1572 clock-names = "se"; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c10_data_clk>; 1575 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1579 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1580 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", 1582 "qup-memory"; 1583 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 status = "disabled"; 1587 }; 1588 1589 spi10: spi@a88000 { 1590 compatible = "qcom,geni-spi"; 1591 reg = <0 0x00a88000 0 0x4000>; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1593 clock-names = "se"; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1596 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 power-domains = <&rpmhpd SC7280_CX>; 1600 operating-points-v2 = <&qup_opp_table>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1603 interconnect-names = "qup-core", "qup-config"; 1604 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1605 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1606 dma-names = "tx", "rx"; 1607 status = "disabled"; 1608 }; 1609 1610 uart10: serial@a88000 { 1611 compatible = "qcom,geni-uart"; 1612 reg = <0 0x00a88000 0 0x4000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1614 clock-names = "se"; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1617 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1618 power-domains = <&rpmhpd SC7280_CX>; 1619 operating-points-v2 = <&qup_opp_table>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1622 interconnect-names = "qup-core", "qup-config"; 1623 status = "disabled"; 1624 }; 1625 1626 i2c11: i2c@a8c000 { 1627 compatible = "qcom,geni-i2c"; 1628 reg = <0 0x00a8c000 0 0x4000>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1630 clock-names = "se"; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_i2c11_data_clk>; 1633 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1638 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1639 interconnect-names = "qup-core", "qup-config", 1640 "qup-memory"; 1641 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1642 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1643 dma-names = "tx", "rx"; 1644 status = "disabled"; 1645 }; 1646 1647 spi11: spi@a8c000 { 1648 compatible = "qcom,geni-spi"; 1649 reg = <0 0x00a8c000 0 0x4000>; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1651 clock-names = "se"; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 power-domains = <&rpmhpd SC7280_CX>; 1658 operating-points-v2 = <&qup_opp_table>; 1659 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1660 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1661 interconnect-names = "qup-core", "qup-config"; 1662 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1663 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1664 dma-names = "tx", "rx"; 1665 status = "disabled"; 1666 }; 1667 1668 uart11: serial@a8c000 { 1669 compatible = "qcom,geni-uart"; 1670 reg = <0 0x00a8c000 0 0x4000>; 1671 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1672 clock-names = "se"; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1675 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1676 power-domains = <&rpmhpd SC7280_CX>; 1677 operating-points-v2 = <&qup_opp_table>; 1678 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1679 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1680 interconnect-names = "qup-core", "qup-config"; 1681 status = "disabled"; 1682 }; 1683 1684 i2c12: i2c@a90000 { 1685 compatible = "qcom,geni-i2c"; 1686 reg = <0 0x00a90000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_i2c12_data_clk>; 1691 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1695 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1696 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1697 interconnect-names = "qup-core", "qup-config", 1698 "qup-memory"; 1699 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1700 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 spi12: spi@a90000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a90000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1712 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 power-domains = <&rpmhpd SC7280_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1721 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1722 dma-names = "tx", "rx"; 1723 status = "disabled"; 1724 }; 1725 1726 uart12: serial@a90000 { 1727 compatible = "qcom,geni-uart"; 1728 reg = <0 0x00a90000 0 0x4000>; 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1730 clock-names = "se"; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SC7280_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1737 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1738 interconnect-names = "qup-core", "qup-config"; 1739 status = "disabled"; 1740 }; 1741 1742 i2c13: i2c@a94000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0 0x00a94000 0 0x4000>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1746 clock-names = "se"; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c13_data_clk>; 1749 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", 1756 "qup-memory"; 1757 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1759 dma-names = "tx", "rx"; 1760 status = "disabled"; 1761 }; 1762 1763 spi13: spi@a94000 { 1764 compatible = "qcom,geni-spi"; 1765 reg = <0 0x00a94000 0 0x4000>; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1767 clock-names = "se"; 1768 pinctrl-names = "default"; 1769 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1770 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1779 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1780 dma-names = "tx", "rx"; 1781 status = "disabled"; 1782 }; 1783 1784 uart13: serial@a94000 { 1785 compatible = "qcom,geni-uart"; 1786 reg = <0 0x00a94000 0 0x4000>; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1788 clock-names = "se"; 1789 pinctrl-names = "default"; 1790 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1791 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1792 power-domains = <&rpmhpd SC7280_CX>; 1793 operating-points-v2 = <&qup_opp_table>; 1794 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1795 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1796 interconnect-names = "qup-core", "qup-config"; 1797 status = "disabled"; 1798 }; 1799 1800 i2c14: i2c@a98000 { 1801 compatible = "qcom,geni-i2c"; 1802 reg = <0 0x00a98000 0 0x4000>; 1803 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1804 clock-names = "se"; 1805 pinctrl-names = "default"; 1806 pinctrl-0 = <&qup_i2c14_data_clk>; 1807 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1811 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1813 interconnect-names = "qup-core", "qup-config", 1814 "qup-memory"; 1815 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1816 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1817 dma-names = "tx", "rx"; 1818 status = "disabled"; 1819 }; 1820 1821 spi14: spi@a98000 { 1822 compatible = "qcom,geni-spi"; 1823 reg = <0 0x00a98000 0 0x4000>; 1824 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1825 clock-names = "se"; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1828 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SC7280_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1835 interconnect-names = "qup-core", "qup-config"; 1836 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1837 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1838 dma-names = "tx", "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 uart14: serial@a98000 { 1843 compatible = "qcom,geni-uart"; 1844 reg = <0 0x00a98000 0 0x4000>; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 clock-names = "se"; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1849 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1850 power-domains = <&rpmhpd SC7280_CX>; 1851 operating-points-v2 = <&qup_opp_table>; 1852 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1853 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1854 interconnect-names = "qup-core", "qup-config"; 1855 status = "disabled"; 1856 }; 1857 1858 i2c15: i2c@a9c000 { 1859 compatible = "qcom,geni-i2c"; 1860 reg = <0 0x00a9c000 0 0x4000>; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1862 clock-names = "se"; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&qup_i2c15_data_clk>; 1865 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1870 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "qup-core", "qup-config", 1872 "qup-memory"; 1873 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1874 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1875 dma-names = "tx", "rx"; 1876 status = "disabled"; 1877 }; 1878 1879 spi15: spi@a9c000 { 1880 compatible = "qcom,geni-spi"; 1881 reg = <0 0x00a9c000 0 0x4000>; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1883 clock-names = "se"; 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1886 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 power-domains = <&rpmhpd SC7280_CX>; 1890 operating-points-v2 = <&qup_opp_table>; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1892 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1893 interconnect-names = "qup-core", "qup-config"; 1894 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1895 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 uart15: serial@a9c000 { 1901 compatible = "qcom,geni-uart"; 1902 reg = <0 0x00a9c000 0 0x4000>; 1903 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1904 clock-names = "se"; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1907 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1908 power-domains = <&rpmhpd SC7280_CX>; 1909 operating-points-v2 = <&qup_opp_table>; 1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 status = "disabled"; 1914 }; 1915 }; 1916 1917 cnoc2: interconnect@1500000 { 1918 reg = <0 0x01500000 0 0x1000>; 1919 compatible = "qcom,sc7280-cnoc2"; 1920 #interconnect-cells = <2>; 1921 qcom,bcm-voters = <&apps_bcm_voter>; 1922 }; 1923 1924 cnoc3: interconnect@1502000 { 1925 reg = <0 0x01502000 0 0x1000>; 1926 compatible = "qcom,sc7280-cnoc3"; 1927 #interconnect-cells = <2>; 1928 qcom,bcm-voters = <&apps_bcm_voter>; 1929 }; 1930 1931 mc_virt: interconnect@1580000 { 1932 reg = <0 0x01580000 0 0x4>; 1933 compatible = "qcom,sc7280-mc-virt"; 1934 #interconnect-cells = <2>; 1935 qcom,bcm-voters = <&apps_bcm_voter>; 1936 }; 1937 1938 system_noc: interconnect@1680000 { 1939 reg = <0 0x01680000 0 0x15480>; 1940 compatible = "qcom,sc7280-system-noc"; 1941 #interconnect-cells = <2>; 1942 qcom,bcm-voters = <&apps_bcm_voter>; 1943 }; 1944 1945 aggre1_noc: interconnect@16e0000 { 1946 compatible = "qcom,sc7280-aggre1-noc"; 1947 reg = <0 0x016e0000 0 0x1c080>; 1948 #interconnect-cells = <2>; 1949 qcom,bcm-voters = <&apps_bcm_voter>; 1950 }; 1951 1952 aggre2_noc: interconnect@1700000 { 1953 reg = <0 0x01700000 0 0x2b080>; 1954 compatible = "qcom,sc7280-aggre2-noc"; 1955 #interconnect-cells = <2>; 1956 qcom,bcm-voters = <&apps_bcm_voter>; 1957 }; 1958 1959 mmss_noc: interconnect@1740000 { 1960 reg = <0 0x01740000 0 0x1e080>; 1961 compatible = "qcom,sc7280-mmss-noc"; 1962 #interconnect-cells = <2>; 1963 qcom,bcm-voters = <&apps_bcm_voter>; 1964 }; 1965 1966 wifi: wifi@17a10040 { 1967 compatible = "qcom,wcn6750-wifi"; 1968 reg = <0 0x17a10040 0 0x0>; 1969 iommus = <&apps_smmu 0x1c00 0x1>; 1970 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1971 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1979 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1980 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1981 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1982 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1983 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1984 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1985 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1986 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1987 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1988 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1989 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1990 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1991 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1992 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1993 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1994 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1995 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1996 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1997 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1998 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2002 qcom,rproc = <&remoteproc_wpss>; 2003 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2004 status = "disabled"; 2005 }; 2006 2007 pcie1: pci@1c08000 { 2008 compatible = "qcom,pcie-sc7280"; 2009 reg = <0 0x01c08000 0 0x3000>, 2010 <0 0x40000000 0 0xf1d>, 2011 <0 0x40000f20 0 0xa8>, 2012 <0 0x40001000 0 0x1000>, 2013 <0 0x40100000 0 0x100000>; 2014 2015 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2016 device_type = "pci"; 2017 linux,pci-domain = <1>; 2018 bus-range = <0x00 0xff>; 2019 num-lanes = <2>; 2020 2021 #address-cells = <3>; 2022 #size-cells = <2>; 2023 2024 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2025 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2026 2027 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2028 interrupt-names = "msi"; 2029 #interrupt-cells = <1>; 2030 interrupt-map-mask = <0 0 0 0x7>; 2031 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2032 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2033 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2034 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2035 2036 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2037 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2038 <&pcie1_lane>, 2039 <&rpmhcc RPMH_CXO_CLK>, 2040 <&gcc GCC_PCIE_1_AUX_CLK>, 2041 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2042 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2043 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2044 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2045 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2046 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 2047 2048 clock-names = "pipe", 2049 "pipe_mux", 2050 "phy_pipe", 2051 "ref", 2052 "aux", 2053 "cfg", 2054 "bus_master", 2055 "bus_slave", 2056 "slave_q2a", 2057 "tbu", 2058 "ddrss_sf_tbu"; 2059 2060 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2061 assigned-clock-rates = <19200000>; 2062 2063 resets = <&gcc GCC_PCIE_1_BCR>; 2064 reset-names = "pci"; 2065 2066 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2067 2068 phys = <&pcie1_lane>; 2069 phy-names = "pciephy"; 2070 2071 pinctrl-names = "default"; 2072 pinctrl-0 = <&pcie1_clkreq_n>; 2073 2074 iommus = <&apps_smmu 0x1c80 0x1>; 2075 2076 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2077 <0x100 &apps_smmu 0x1c81 0x1>; 2078 2079 status = "disabled"; 2080 }; 2081 2082 pcie1_phy: phy@1c0e000 { 2083 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2084 reg = <0 0x01c0e000 0 0x1c0>; 2085 #address-cells = <2>; 2086 #size-cells = <2>; 2087 ranges; 2088 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2089 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2090 <&gcc GCC_PCIE_CLKREF_EN>, 2091 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2092 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2093 2094 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2095 reset-names = "phy"; 2096 2097 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2098 assigned-clock-rates = <100000000>; 2099 2100 status = "disabled"; 2101 2102 pcie1_lane: phy@1c0e200 { 2103 reg = <0 0x01c0e200 0 0x170>, 2104 <0 0x01c0e400 0 0x200>, 2105 <0 0x01c0ea00 0 0x1f0>, 2106 <0 0x01c0e600 0 0x170>, 2107 <0 0x01c0e800 0 0x200>, 2108 <0 0x01c0ee00 0 0xf4>; 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2110 clock-names = "pipe0"; 2111 2112 #phy-cells = <0>; 2113 #clock-cells = <0>; 2114 clock-output-names = "pcie_1_pipe_clk"; 2115 }; 2116 }; 2117 2118 ipa: ipa@1e40000 { 2119 compatible = "qcom,sc7280-ipa"; 2120 2121 iommus = <&apps_smmu 0x480 0x0>, 2122 <&apps_smmu 0x482 0x0>; 2123 reg = <0 0x1e40000 0 0x8000>, 2124 <0 0x1e50000 0 0x4ad0>, 2125 <0 0x1e04000 0 0x23000>; 2126 reg-names = "ipa-reg", 2127 "ipa-shared", 2128 "gsi"; 2129 2130 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2131 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2132 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2133 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2134 interrupt-names = "ipa", 2135 "gsi", 2136 "ipa-clock-query", 2137 "ipa-setup-ready"; 2138 2139 clocks = <&rpmhcc RPMH_IPA_CLK>; 2140 clock-names = "core"; 2141 2142 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2144 interconnect-names = "memory", 2145 "config"; 2146 2147 qcom,qmp = <&aoss_qmp>; 2148 2149 qcom,smem-states = <&ipa_smp2p_out 0>, 2150 <&ipa_smp2p_out 1>; 2151 qcom,smem-state-names = "ipa-clock-enabled-valid", 2152 "ipa-clock-enabled"; 2153 2154 status = "disabled"; 2155 }; 2156 2157 tcsr_mutex: hwlock@1f40000 { 2158 compatible = "qcom,tcsr-mutex"; 2159 reg = <0 0x01f40000 0 0x20000>; 2160 #hwlock-cells = <1>; 2161 }; 2162 2163 tcsr_1: sycon@1f60000 { 2164 compatible = "qcom,sc7280-tcsr", "syscon"; 2165 reg = <0 0x01f60000 0 0x20000>; 2166 }; 2167 2168 tcsr_2: syscon@1fc0000 { 2169 compatible = "qcom,sc7280-tcsr", "syscon"; 2170 reg = <0 0x01fc0000 0 0x30000>; 2171 }; 2172 2173 lpasscc: lpasscc@3000000 { 2174 compatible = "qcom,sc7280-lpasscc"; 2175 reg = <0 0x03000000 0 0x40>, 2176 <0 0x03c04000 0 0x4>; 2177 reg-names = "qdsp6ss", "top_cc"; 2178 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2179 clock-names = "iface"; 2180 #clock-cells = <1>; 2181 }; 2182 2183 lpass_audiocc: clock-controller@3300000 { 2184 compatible = "qcom,sc7280-lpassaudiocc"; 2185 reg = <0 0x03300000 0 0x30000>; 2186 clocks = <&rpmhcc RPMH_CXO_CLK>, 2187 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2188 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2189 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2190 #clock-cells = <1>; 2191 #power-domain-cells = <1>; 2192 #reset-cells = <1>; 2193 }; 2194 2195 lpass_aon: clock-controller@3380000 { 2196 compatible = "qcom,sc7280-lpassaoncc"; 2197 reg = <0 0x03380000 0 0x30000>; 2198 clocks = <&rpmhcc RPMH_CXO_CLK>, 2199 <&rpmhcc RPMH_CXO_CLK_A>, 2200 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2201 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2202 #clock-cells = <1>; 2203 #power-domain-cells = <1>; 2204 }; 2205 2206 lpass_core: clock-controller@3900000 { 2207 compatible = "qcom,sc7280-lpasscorecc"; 2208 reg = <0 0x03900000 0 0x50000>; 2209 clocks = <&rpmhcc RPMH_CXO_CLK>; 2210 clock-names = "bi_tcxo"; 2211 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2212 #clock-cells = <1>; 2213 #power-domain-cells = <1>; 2214 }; 2215 2216 lpass_hm: clock-controller@3c00000 { 2217 compatible = "qcom,sc7280-lpasshm"; 2218 reg = <0 0x3c00000 0 0x28>; 2219 clocks = <&rpmhcc RPMH_CXO_CLK>; 2220 clock-names = "bi_tcxo"; 2221 #clock-cells = <1>; 2222 #power-domain-cells = <1>; 2223 }; 2224 2225 lpass_ag_noc: interconnect@3c40000 { 2226 reg = <0 0x03c40000 0 0xf080>; 2227 compatible = "qcom,sc7280-lpass-ag-noc"; 2228 #interconnect-cells = <2>; 2229 qcom,bcm-voters = <&apps_bcm_voter>; 2230 }; 2231 2232 lpass_tlmm: pinctrl@33c0000 { 2233 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2234 reg = <0 0x033c0000 0x0 0x20000>, 2235 <0 0x03550000 0x0 0x10000>; 2236 qcom,adsp-bypass-mode; 2237 gpio-controller; 2238 #gpio-cells = <2>; 2239 gpio-ranges = <&lpass_tlmm 0 0 15>; 2240 2241 #clock-cells = <1>; 2242 2243 lpass_dmic01_clk: dmic01-clk { 2244 pins = "gpio6"; 2245 function = "dmic1_clk"; 2246 }; 2247 2248 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2249 pins = "gpio6"; 2250 function = "dmic1_clk"; 2251 }; 2252 2253 lpass_dmic01_data: dmic01-data { 2254 pins = "gpio7"; 2255 function = "dmic1_data"; 2256 }; 2257 2258 lpass_dmic01_data_sleep: dmic01-data-sleep { 2259 pins = "gpio7"; 2260 function = "dmic1_data"; 2261 }; 2262 2263 lpass_dmic23_clk: dmic23-clk { 2264 pins = "gpio8"; 2265 function = "dmic2_clk"; 2266 }; 2267 2268 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2269 pins = "gpio8"; 2270 function = "dmic2_clk"; 2271 }; 2272 2273 lpass_dmic23_data: dmic23-data { 2274 pins = "gpio9"; 2275 function = "dmic2_data"; 2276 }; 2277 2278 lpass_dmic23_data_sleep: dmic23-data-sleep { 2279 pins = "gpio9"; 2280 function = "dmic2_data"; 2281 }; 2282 2283 lpass_rx_swr_clk: rx-swr-clk { 2284 pins = "gpio3"; 2285 function = "swr_rx_clk"; 2286 }; 2287 2288 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2289 pins = "gpio3"; 2290 function = "swr_rx_clk"; 2291 }; 2292 2293 lpass_rx_swr_data: rx-swr-data { 2294 pins = "gpio4", "gpio5"; 2295 function = "swr_rx_data"; 2296 }; 2297 2298 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2299 pins = "gpio4", "gpio5"; 2300 function = "swr_rx_data"; 2301 }; 2302 2303 lpass_tx_swr_clk: tx-swr-clk { 2304 pins = "gpio0"; 2305 function = "swr_tx_clk"; 2306 }; 2307 2308 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2309 pins = "gpio0"; 2310 function = "swr_tx_clk"; 2311 }; 2312 2313 lpass_tx_swr_data: tx-swr-data { 2314 pins = "gpio1", "gpio2", "gpio14"; 2315 function = "swr_tx_data"; 2316 }; 2317 2318 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2319 pins = "gpio1", "gpio2", "gpio14"; 2320 function = "swr_tx_data"; 2321 }; 2322 }; 2323 2324 gpu: gpu@3d00000 { 2325 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2326 reg = <0 0x03d00000 0 0x40000>, 2327 <0 0x03d9e000 0 0x1000>, 2328 <0 0x03d61000 0 0x800>; 2329 reg-names = "kgsl_3d0_reg_memory", 2330 "cx_mem", 2331 "cx_dbgc"; 2332 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2333 iommus = <&adreno_smmu 0 0x401>; 2334 operating-points-v2 = <&gpu_opp_table>; 2335 qcom,gmu = <&gmu>; 2336 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2337 interconnect-names = "gfx-mem"; 2338 #cooling-cells = <2>; 2339 2340 nvmem-cells = <&gpu_speed_bin>; 2341 nvmem-cell-names = "speed_bin"; 2342 2343 gpu_opp_table: opp-table { 2344 compatible = "operating-points-v2"; 2345 2346 opp-315000000 { 2347 opp-hz = /bits/ 64 <315000000>; 2348 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2349 opp-peak-kBps = <1804000>; 2350 opp-supported-hw = <0x03>; 2351 }; 2352 2353 opp-450000000 { 2354 opp-hz = /bits/ 64 <450000000>; 2355 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2356 opp-peak-kBps = <4068000>; 2357 opp-supported-hw = <0x03>; 2358 }; 2359 2360 opp-550000000 { 2361 opp-hz = /bits/ 64 <550000000>; 2362 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2363 opp-peak-kBps = <6832000>; 2364 opp-supported-hw = <0x03>; 2365 }; 2366 2367 opp-608000000 { 2368 opp-hz = /bits/ 64 <608000000>; 2369 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2370 opp-peak-kBps = <8368000>; 2371 opp-supported-hw = <0x02>; 2372 }; 2373 2374 opp-700000000 { 2375 opp-hz = /bits/ 64 <700000000>; 2376 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2377 opp-peak-kBps = <8532000>; 2378 opp-supported-hw = <0x02>; 2379 }; 2380 2381 opp-812000000 { 2382 opp-hz = /bits/ 64 <812000000>; 2383 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2384 opp-peak-kBps = <8532000>; 2385 opp-supported-hw = <0x02>; 2386 }; 2387 2388 opp-840000000 { 2389 opp-hz = /bits/ 64 <840000000>; 2390 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2391 opp-peak-kBps = <8532000>; 2392 opp-supported-hw = <0x02>; 2393 }; 2394 2395 opp-900000000 { 2396 opp-hz = /bits/ 64 <900000000>; 2397 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2398 opp-peak-kBps = <8532000>; 2399 opp-supported-hw = <0x02>; 2400 }; 2401 }; 2402 }; 2403 2404 gmu: gmu@3d6a000 { 2405 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2406 reg = <0 0x03d6a000 0 0x34000>, 2407 <0 0x3de0000 0 0x10000>, 2408 <0 0x0b290000 0 0x10000>; 2409 reg-names = "gmu", "rscc", "gmu_pdc"; 2410 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2411 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2412 interrupt-names = "hfi", "gmu"; 2413 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2414 <&gpucc GPU_CC_CXO_CLK>, 2415 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2416 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2417 <&gpucc GPU_CC_AHB_CLK>, 2418 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2419 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2420 clock-names = "gmu", 2421 "cxo", 2422 "axi", 2423 "memnoc", 2424 "ahb", 2425 "hub", 2426 "smmu_vote"; 2427 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2428 <&gpucc GPU_CC_GX_GDSC>; 2429 power-domain-names = "cx", 2430 "gx"; 2431 iommus = <&adreno_smmu 5 0x400>; 2432 operating-points-v2 = <&gmu_opp_table>; 2433 2434 gmu_opp_table: opp-table { 2435 compatible = "operating-points-v2"; 2436 2437 opp-200000000 { 2438 opp-hz = /bits/ 64 <200000000>; 2439 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2440 }; 2441 }; 2442 }; 2443 2444 gpucc: clock-controller@3d90000 { 2445 compatible = "qcom,sc7280-gpucc"; 2446 reg = <0 0x03d90000 0 0x9000>; 2447 clocks = <&rpmhcc RPMH_CXO_CLK>, 2448 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2449 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2450 clock-names = "bi_tcxo", 2451 "gcc_gpu_gpll0_clk_src", 2452 "gcc_gpu_gpll0_div_clk_src"; 2453 #clock-cells = <1>; 2454 #reset-cells = <1>; 2455 #power-domain-cells = <1>; 2456 }; 2457 2458 adreno_smmu: iommu@3da0000 { 2459 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2460 reg = <0 0x03da0000 0 0x20000>; 2461 #iommu-cells = <2>; 2462 #global-interrupts = <2>; 2463 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2475 2476 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2477 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2478 <&gpucc GPU_CC_AHB_CLK>, 2479 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2480 <&gpucc GPU_CC_CX_GMU_CLK>, 2481 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2482 <&gpucc GPU_CC_HUB_AON_CLK>; 2483 clock-names = "gcc_gpu_memnoc_gfx_clk", 2484 "gcc_gpu_snoc_dvm_gfx_clk", 2485 "gpu_cc_ahb_clk", 2486 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2487 "gpu_cc_cx_gmu_clk", 2488 "gpu_cc_hub_cx_int_clk", 2489 "gpu_cc_hub_aon_clk"; 2490 2491 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2492 }; 2493 2494 remoteproc_mpss: remoteproc@4080000 { 2495 compatible = "qcom,sc7280-mpss-pas"; 2496 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2497 reg-names = "qdsp6", "rmb"; 2498 2499 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2500 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2501 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2502 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2503 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2504 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2505 interrupt-names = "wdog", "fatal", "ready", "handover", 2506 "stop-ack", "shutdown-ack"; 2507 2508 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2509 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2510 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2511 <&rpmhcc RPMH_PKA_CLK>, 2512 <&rpmhcc RPMH_CXO_CLK>; 2513 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2514 2515 power-domains = <&rpmhpd SC7280_CX>, 2516 <&rpmhpd SC7280_MSS>; 2517 power-domain-names = "cx", "mss"; 2518 2519 memory-region = <&mpss_mem>; 2520 2521 qcom,qmp = <&aoss_qmp>; 2522 2523 qcom,smem-states = <&modem_smp2p_out 0>; 2524 qcom,smem-state-names = "stop"; 2525 2526 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2527 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2528 reset-names = "mss_restart", "pdc_reset"; 2529 2530 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2531 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2532 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2533 2534 status = "disabled"; 2535 2536 glink-edge { 2537 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2538 IPCC_MPROC_SIGNAL_GLINK_QMP 2539 IRQ_TYPE_EDGE_RISING>; 2540 mboxes = <&ipcc IPCC_CLIENT_MPSS 2541 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2542 label = "modem"; 2543 qcom,remote-pid = <1>; 2544 }; 2545 }; 2546 2547 stm@6002000 { 2548 compatible = "arm,coresight-stm", "arm,primecell"; 2549 reg = <0 0x06002000 0 0x1000>, 2550 <0 0x16280000 0 0x180000>; 2551 reg-names = "stm-base", "stm-stimulus-base"; 2552 2553 clocks = <&aoss_qmp>; 2554 clock-names = "apb_pclk"; 2555 2556 out-ports { 2557 port { 2558 stm_out: endpoint { 2559 remote-endpoint = <&funnel0_in7>; 2560 }; 2561 }; 2562 }; 2563 }; 2564 2565 funnel@6041000 { 2566 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2567 reg = <0 0x06041000 0 0x1000>; 2568 2569 clocks = <&aoss_qmp>; 2570 clock-names = "apb_pclk"; 2571 2572 out-ports { 2573 port { 2574 funnel0_out: endpoint { 2575 remote-endpoint = <&merge_funnel_in0>; 2576 }; 2577 }; 2578 }; 2579 2580 in-ports { 2581 #address-cells = <1>; 2582 #size-cells = <0>; 2583 2584 port@7 { 2585 reg = <7>; 2586 funnel0_in7: endpoint { 2587 remote-endpoint = <&stm_out>; 2588 }; 2589 }; 2590 }; 2591 }; 2592 2593 funnel@6042000 { 2594 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2595 reg = <0 0x06042000 0 0x1000>; 2596 2597 clocks = <&aoss_qmp>; 2598 clock-names = "apb_pclk"; 2599 2600 out-ports { 2601 port { 2602 funnel1_out: endpoint { 2603 remote-endpoint = <&merge_funnel_in1>; 2604 }; 2605 }; 2606 }; 2607 2608 in-ports { 2609 #address-cells = <1>; 2610 #size-cells = <0>; 2611 2612 port@4 { 2613 reg = <4>; 2614 funnel1_in4: endpoint { 2615 remote-endpoint = <&apss_merge_funnel_out>; 2616 }; 2617 }; 2618 }; 2619 }; 2620 2621 funnel@6045000 { 2622 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2623 reg = <0 0x06045000 0 0x1000>; 2624 2625 clocks = <&aoss_qmp>; 2626 clock-names = "apb_pclk"; 2627 2628 out-ports { 2629 port { 2630 merge_funnel_out: endpoint { 2631 remote-endpoint = <&swao_funnel_in>; 2632 }; 2633 }; 2634 }; 2635 2636 in-ports { 2637 #address-cells = <1>; 2638 #size-cells = <0>; 2639 2640 port@0 { 2641 reg = <0>; 2642 merge_funnel_in0: endpoint { 2643 remote-endpoint = <&funnel0_out>; 2644 }; 2645 }; 2646 2647 port@1 { 2648 reg = <1>; 2649 merge_funnel_in1: endpoint { 2650 remote-endpoint = <&funnel1_out>; 2651 }; 2652 }; 2653 }; 2654 }; 2655 2656 replicator@6046000 { 2657 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2658 reg = <0 0x06046000 0 0x1000>; 2659 2660 clocks = <&aoss_qmp>; 2661 clock-names = "apb_pclk"; 2662 2663 out-ports { 2664 port { 2665 replicator_out: endpoint { 2666 remote-endpoint = <&etr_in>; 2667 }; 2668 }; 2669 }; 2670 2671 in-ports { 2672 port { 2673 replicator_in: endpoint { 2674 remote-endpoint = <&swao_replicator_out>; 2675 }; 2676 }; 2677 }; 2678 }; 2679 2680 etr@6048000 { 2681 compatible = "arm,coresight-tmc", "arm,primecell"; 2682 reg = <0 0x06048000 0 0x1000>; 2683 iommus = <&apps_smmu 0x04c0 0>; 2684 2685 clocks = <&aoss_qmp>; 2686 clock-names = "apb_pclk"; 2687 arm,scatter-gather; 2688 2689 in-ports { 2690 port { 2691 etr_in: endpoint { 2692 remote-endpoint = <&replicator_out>; 2693 }; 2694 }; 2695 }; 2696 }; 2697 2698 funnel@6b04000 { 2699 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2700 reg = <0 0x06b04000 0 0x1000>; 2701 2702 clocks = <&aoss_qmp>; 2703 clock-names = "apb_pclk"; 2704 2705 out-ports { 2706 port { 2707 swao_funnel_out: endpoint { 2708 remote-endpoint = <&etf_in>; 2709 }; 2710 }; 2711 }; 2712 2713 in-ports { 2714 #address-cells = <1>; 2715 #size-cells = <0>; 2716 2717 port@7 { 2718 reg = <7>; 2719 swao_funnel_in: endpoint { 2720 remote-endpoint = <&merge_funnel_out>; 2721 }; 2722 }; 2723 }; 2724 }; 2725 2726 etf@6b05000 { 2727 compatible = "arm,coresight-tmc", "arm,primecell"; 2728 reg = <0 0x06b05000 0 0x1000>; 2729 2730 clocks = <&aoss_qmp>; 2731 clock-names = "apb_pclk"; 2732 2733 out-ports { 2734 port { 2735 etf_out: endpoint { 2736 remote-endpoint = <&swao_replicator_in>; 2737 }; 2738 }; 2739 }; 2740 2741 in-ports { 2742 port { 2743 etf_in: endpoint { 2744 remote-endpoint = <&swao_funnel_out>; 2745 }; 2746 }; 2747 }; 2748 }; 2749 2750 replicator@6b06000 { 2751 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2752 reg = <0 0x06b06000 0 0x1000>; 2753 2754 clocks = <&aoss_qmp>; 2755 clock-names = "apb_pclk"; 2756 qcom,replicator-loses-context; 2757 2758 out-ports { 2759 port { 2760 swao_replicator_out: endpoint { 2761 remote-endpoint = <&replicator_in>; 2762 }; 2763 }; 2764 }; 2765 2766 in-ports { 2767 port { 2768 swao_replicator_in: endpoint { 2769 remote-endpoint = <&etf_out>; 2770 }; 2771 }; 2772 }; 2773 }; 2774 2775 etm@7040000 { 2776 compatible = "arm,coresight-etm4x", "arm,primecell"; 2777 reg = <0 0x07040000 0 0x1000>; 2778 2779 cpu = <&CPU0>; 2780 2781 clocks = <&aoss_qmp>; 2782 clock-names = "apb_pclk"; 2783 arm,coresight-loses-context-with-cpu; 2784 qcom,skip-power-up; 2785 2786 out-ports { 2787 port { 2788 etm0_out: endpoint { 2789 remote-endpoint = <&apss_funnel_in0>; 2790 }; 2791 }; 2792 }; 2793 }; 2794 2795 etm@7140000 { 2796 compatible = "arm,coresight-etm4x", "arm,primecell"; 2797 reg = <0 0x07140000 0 0x1000>; 2798 2799 cpu = <&CPU1>; 2800 2801 clocks = <&aoss_qmp>; 2802 clock-names = "apb_pclk"; 2803 arm,coresight-loses-context-with-cpu; 2804 qcom,skip-power-up; 2805 2806 out-ports { 2807 port { 2808 etm1_out: endpoint { 2809 remote-endpoint = <&apss_funnel_in1>; 2810 }; 2811 }; 2812 }; 2813 }; 2814 2815 etm@7240000 { 2816 compatible = "arm,coresight-etm4x", "arm,primecell"; 2817 reg = <0 0x07240000 0 0x1000>; 2818 2819 cpu = <&CPU2>; 2820 2821 clocks = <&aoss_qmp>; 2822 clock-names = "apb_pclk"; 2823 arm,coresight-loses-context-with-cpu; 2824 qcom,skip-power-up; 2825 2826 out-ports { 2827 port { 2828 etm2_out: endpoint { 2829 remote-endpoint = <&apss_funnel_in2>; 2830 }; 2831 }; 2832 }; 2833 }; 2834 2835 etm@7340000 { 2836 compatible = "arm,coresight-etm4x", "arm,primecell"; 2837 reg = <0 0x07340000 0 0x1000>; 2838 2839 cpu = <&CPU3>; 2840 2841 clocks = <&aoss_qmp>; 2842 clock-names = "apb_pclk"; 2843 arm,coresight-loses-context-with-cpu; 2844 qcom,skip-power-up; 2845 2846 out-ports { 2847 port { 2848 etm3_out: endpoint { 2849 remote-endpoint = <&apss_funnel_in3>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 etm@7440000 { 2856 compatible = "arm,coresight-etm4x", "arm,primecell"; 2857 reg = <0 0x07440000 0 0x1000>; 2858 2859 cpu = <&CPU4>; 2860 2861 clocks = <&aoss_qmp>; 2862 clock-names = "apb_pclk"; 2863 arm,coresight-loses-context-with-cpu; 2864 qcom,skip-power-up; 2865 2866 out-ports { 2867 port { 2868 etm4_out: endpoint { 2869 remote-endpoint = <&apss_funnel_in4>; 2870 }; 2871 }; 2872 }; 2873 }; 2874 2875 etm@7540000 { 2876 compatible = "arm,coresight-etm4x", "arm,primecell"; 2877 reg = <0 0x07540000 0 0x1000>; 2878 2879 cpu = <&CPU5>; 2880 2881 clocks = <&aoss_qmp>; 2882 clock-names = "apb_pclk"; 2883 arm,coresight-loses-context-with-cpu; 2884 qcom,skip-power-up; 2885 2886 out-ports { 2887 port { 2888 etm5_out: endpoint { 2889 remote-endpoint = <&apss_funnel_in5>; 2890 }; 2891 }; 2892 }; 2893 }; 2894 2895 etm@7640000 { 2896 compatible = "arm,coresight-etm4x", "arm,primecell"; 2897 reg = <0 0x07640000 0 0x1000>; 2898 2899 cpu = <&CPU6>; 2900 2901 clocks = <&aoss_qmp>; 2902 clock-names = "apb_pclk"; 2903 arm,coresight-loses-context-with-cpu; 2904 qcom,skip-power-up; 2905 2906 out-ports { 2907 port { 2908 etm6_out: endpoint { 2909 remote-endpoint = <&apss_funnel_in6>; 2910 }; 2911 }; 2912 }; 2913 }; 2914 2915 etm@7740000 { 2916 compatible = "arm,coresight-etm4x", "arm,primecell"; 2917 reg = <0 0x07740000 0 0x1000>; 2918 2919 cpu = <&CPU7>; 2920 2921 clocks = <&aoss_qmp>; 2922 clock-names = "apb_pclk"; 2923 arm,coresight-loses-context-with-cpu; 2924 qcom,skip-power-up; 2925 2926 out-ports { 2927 port { 2928 etm7_out: endpoint { 2929 remote-endpoint = <&apss_funnel_in7>; 2930 }; 2931 }; 2932 }; 2933 }; 2934 2935 funnel@7800000 { /* APSS Funnel */ 2936 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2937 reg = <0 0x07800000 0 0x1000>; 2938 2939 clocks = <&aoss_qmp>; 2940 clock-names = "apb_pclk"; 2941 2942 out-ports { 2943 port { 2944 apss_funnel_out: endpoint { 2945 remote-endpoint = <&apss_merge_funnel_in>; 2946 }; 2947 }; 2948 }; 2949 2950 in-ports { 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 2954 port@0 { 2955 reg = <0>; 2956 apss_funnel_in0: endpoint { 2957 remote-endpoint = <&etm0_out>; 2958 }; 2959 }; 2960 2961 port@1 { 2962 reg = <1>; 2963 apss_funnel_in1: endpoint { 2964 remote-endpoint = <&etm1_out>; 2965 }; 2966 }; 2967 2968 port@2 { 2969 reg = <2>; 2970 apss_funnel_in2: endpoint { 2971 remote-endpoint = <&etm2_out>; 2972 }; 2973 }; 2974 2975 port@3 { 2976 reg = <3>; 2977 apss_funnel_in3: endpoint { 2978 remote-endpoint = <&etm3_out>; 2979 }; 2980 }; 2981 2982 port@4 { 2983 reg = <4>; 2984 apss_funnel_in4: endpoint { 2985 remote-endpoint = <&etm4_out>; 2986 }; 2987 }; 2988 2989 port@5 { 2990 reg = <5>; 2991 apss_funnel_in5: endpoint { 2992 remote-endpoint = <&etm5_out>; 2993 }; 2994 }; 2995 2996 port@6 { 2997 reg = <6>; 2998 apss_funnel_in6: endpoint { 2999 remote-endpoint = <&etm6_out>; 3000 }; 3001 }; 3002 3003 port@7 { 3004 reg = <7>; 3005 apss_funnel_in7: endpoint { 3006 remote-endpoint = <&etm7_out>; 3007 }; 3008 }; 3009 }; 3010 }; 3011 3012 funnel@7810000 { 3013 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3014 reg = <0 0x07810000 0 0x1000>; 3015 3016 clocks = <&aoss_qmp>; 3017 clock-names = "apb_pclk"; 3018 3019 out-ports { 3020 port { 3021 apss_merge_funnel_out: endpoint { 3022 remote-endpoint = <&funnel1_in4>; 3023 }; 3024 }; 3025 }; 3026 3027 in-ports { 3028 port { 3029 apss_merge_funnel_in: endpoint { 3030 remote-endpoint = <&apss_funnel_out>; 3031 }; 3032 }; 3033 }; 3034 }; 3035 3036 sdhc_2: mmc@8804000 { 3037 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3038 pinctrl-names = "default", "sleep"; 3039 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3040 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3041 status = "disabled"; 3042 3043 reg = <0 0x08804000 0 0x1000>; 3044 3045 iommus = <&apps_smmu 0x100 0x0>; 3046 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3047 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3048 interrupt-names = "hc_irq", "pwr_irq"; 3049 3050 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3051 <&gcc GCC_SDCC2_APPS_CLK>, 3052 <&rpmhcc RPMH_CXO_CLK>; 3053 clock-names = "iface", "core", "xo"; 3054 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3055 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3056 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3057 power-domains = <&rpmhpd SC7280_CX>; 3058 operating-points-v2 = <&sdhc2_opp_table>; 3059 3060 bus-width = <4>; 3061 3062 qcom,dll-config = <0x0007642c>; 3063 3064 resets = <&gcc GCC_SDCC2_BCR>; 3065 3066 sdhc2_opp_table: opp-table { 3067 compatible = "operating-points-v2"; 3068 3069 opp-100000000 { 3070 opp-hz = /bits/ 64 <100000000>; 3071 required-opps = <&rpmhpd_opp_low_svs>; 3072 opp-peak-kBps = <1800000 400000>; 3073 opp-avg-kBps = <100000 0>; 3074 }; 3075 3076 opp-202000000 { 3077 opp-hz = /bits/ 64 <202000000>; 3078 required-opps = <&rpmhpd_opp_nom>; 3079 opp-peak-kBps = <5400000 1600000>; 3080 opp-avg-kBps = <200000 0>; 3081 }; 3082 }; 3083 3084 }; 3085 3086 usb_1_hsphy: phy@88e3000 { 3087 compatible = "qcom,sc7280-usb-hs-phy", 3088 "qcom,usb-snps-hs-7nm-phy"; 3089 reg = <0 0x088e3000 0 0x400>; 3090 status = "disabled"; 3091 #phy-cells = <0>; 3092 3093 clocks = <&rpmhcc RPMH_CXO_CLK>; 3094 clock-names = "ref"; 3095 3096 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3097 }; 3098 3099 usb_2_hsphy: phy@88e4000 { 3100 compatible = "qcom,sc7280-usb-hs-phy", 3101 "qcom,usb-snps-hs-7nm-phy"; 3102 reg = <0 0x088e4000 0 0x400>; 3103 status = "disabled"; 3104 #phy-cells = <0>; 3105 3106 clocks = <&rpmhcc RPMH_CXO_CLK>; 3107 clock-names = "ref"; 3108 3109 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3110 }; 3111 3112 usb_1_qmpphy: phy-wrapper@88e9000 { 3113 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3114 "qcom,sm8250-qmp-usb3-dp-phy"; 3115 reg = <0 0x088e9000 0 0x200>, 3116 <0 0x088e8000 0 0x40>, 3117 <0 0x088ea000 0 0x200>; 3118 status = "disabled"; 3119 #address-cells = <2>; 3120 #size-cells = <2>; 3121 ranges; 3122 3123 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3124 <&rpmhcc RPMH_CXO_CLK>, 3125 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3126 clock-names = "aux", "ref_clk_src", "com_aux"; 3127 3128 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3129 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3130 reset-names = "phy", "common"; 3131 3132 usb_1_ssphy: usb3-phy@88e9200 { 3133 reg = <0 0x088e9200 0 0x200>, 3134 <0 0x088e9400 0 0x200>, 3135 <0 0x088e9c00 0 0x400>, 3136 <0 0x088e9600 0 0x200>, 3137 <0 0x088e9800 0 0x200>, 3138 <0 0x088e9a00 0 0x100>; 3139 #clock-cells = <0>; 3140 #phy-cells = <0>; 3141 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3142 clock-names = "pipe0"; 3143 clock-output-names = "usb3_phy_pipe_clk_src"; 3144 }; 3145 3146 dp_phy: dp-phy@88ea200 { 3147 reg = <0 0x088ea200 0 0x200>, 3148 <0 0x088ea400 0 0x200>, 3149 <0 0x088eaa00 0 0x200>, 3150 <0 0x088ea600 0 0x200>, 3151 <0 0x088ea800 0 0x200>; 3152 #phy-cells = <0>; 3153 #clock-cells = <1>; 3154 }; 3155 }; 3156 3157 usb_2: usb@8cf8800 { 3158 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3159 reg = <0 0x08cf8800 0 0x400>; 3160 status = "disabled"; 3161 #address-cells = <2>; 3162 #size-cells = <2>; 3163 ranges; 3164 dma-ranges; 3165 3166 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3167 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3168 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3169 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3170 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3171 clock-names = "cfg_noc", 3172 "core", 3173 "iface", 3174 "sleep", 3175 "mock_utmi"; 3176 3177 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3178 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3179 assigned-clock-rates = <19200000>, <200000000>; 3180 3181 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3182 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3183 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3184 interrupt-names = "hs_phy_irq", 3185 "dp_hs_phy_irq", 3186 "dm_hs_phy_irq"; 3187 3188 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3189 3190 resets = <&gcc GCC_USB30_SEC_BCR>; 3191 3192 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3193 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3194 interconnect-names = "usb-ddr", "apps-usb"; 3195 3196 usb_2_dwc3: usb@8c00000 { 3197 compatible = "snps,dwc3"; 3198 reg = <0 0x08c00000 0 0xe000>; 3199 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3200 iommus = <&apps_smmu 0xa0 0x0>; 3201 snps,dis_u2_susphy_quirk; 3202 snps,dis_enblslpm_quirk; 3203 phys = <&usb_2_hsphy>; 3204 phy-names = "usb2-phy"; 3205 maximum-speed = "high-speed"; 3206 usb-role-switch; 3207 port { 3208 usb2_role_switch: endpoint { 3209 remote-endpoint = <&eud_ep>; 3210 }; 3211 }; 3212 }; 3213 }; 3214 3215 qspi: spi@88dc000 { 3216 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3217 reg = <0 0x088dc000 0 0x1000>; 3218 #address-cells = <1>; 3219 #size-cells = <0>; 3220 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3221 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3222 <&gcc GCC_QSPI_CORE_CLK>; 3223 clock-names = "iface", "core"; 3224 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3225 &cnoc2 SLAVE_QSPI_0 0>; 3226 interconnect-names = "qspi-config"; 3227 power-domains = <&rpmhpd SC7280_CX>; 3228 operating-points-v2 = <&qspi_opp_table>; 3229 status = "disabled"; 3230 }; 3231 3232 remoteproc_wpss: remoteproc@8a00000 { 3233 compatible = "qcom,sc7280-wpss-pil"; 3234 reg = <0 0x08a00000 0 0x10000>; 3235 3236 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3237 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3238 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3239 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3240 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3241 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3242 interrupt-names = "wdog", "fatal", "ready", "handover", 3243 "stop-ack", "shutdown-ack"; 3244 3245 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3246 <&gcc GCC_WPSS_AHB_CLK>, 3247 <&gcc GCC_WPSS_RSCP_CLK>, 3248 <&rpmhcc RPMH_CXO_CLK>; 3249 clock-names = "ahb_bdg", "ahb", 3250 "rscp", "xo"; 3251 3252 power-domains = <&rpmhpd SC7280_CX>, 3253 <&rpmhpd SC7280_MX>; 3254 power-domain-names = "cx", "mx"; 3255 3256 memory-region = <&wpss_mem>; 3257 3258 qcom,qmp = <&aoss_qmp>; 3259 3260 qcom,smem-states = <&wpss_smp2p_out 0>; 3261 qcom,smem-state-names = "stop"; 3262 3263 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3264 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3265 reset-names = "restart", "pdc_sync"; 3266 3267 qcom,halt-regs = <&tcsr_1 0x17000>; 3268 3269 status = "disabled"; 3270 3271 glink-edge { 3272 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3273 IPCC_MPROC_SIGNAL_GLINK_QMP 3274 IRQ_TYPE_EDGE_RISING>; 3275 mboxes = <&ipcc IPCC_CLIENT_WPSS 3276 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3277 3278 label = "wpss"; 3279 qcom,remote-pid = <13>; 3280 }; 3281 }; 3282 3283 dc_noc: interconnect@90e0000 { 3284 reg = <0 0x090e0000 0 0x5080>; 3285 compatible = "qcom,sc7280-dc-noc"; 3286 #interconnect-cells = <2>; 3287 qcom,bcm-voters = <&apps_bcm_voter>; 3288 }; 3289 3290 gem_noc: interconnect@9100000 { 3291 reg = <0 0x9100000 0 0xe2200>; 3292 compatible = "qcom,sc7280-gem-noc"; 3293 #interconnect-cells = <2>; 3294 qcom,bcm-voters = <&apps_bcm_voter>; 3295 }; 3296 3297 system-cache-controller@9200000 { 3298 compatible = "qcom,sc7280-llcc"; 3299 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3300 reg-names = "llcc_base", "llcc_broadcast_base"; 3301 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3302 }; 3303 3304 eud: eud@88e0000 { 3305 compatible = "qcom,sc7280-eud","qcom,eud"; 3306 reg = <0 0x88e0000 0 0x2000>, 3307 <0 0x88e2000 0 0x1000>; 3308 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3309 ports { 3310 port@0 { 3311 eud_ep: endpoint { 3312 remote-endpoint = <&usb2_role_switch>; 3313 }; 3314 }; 3315 port@1 { 3316 eud_con: endpoint { 3317 remote-endpoint = <&con_eud>; 3318 }; 3319 }; 3320 }; 3321 }; 3322 3323 eud_typec: connector { 3324 compatible = "usb-c-connector"; 3325 ports { 3326 port@0 { 3327 con_eud: endpoint { 3328 remote-endpoint = <&eud_con>; 3329 }; 3330 }; 3331 }; 3332 }; 3333 3334 nsp_noc: interconnect@a0c0000 { 3335 reg = <0 0x0a0c0000 0 0x10000>; 3336 compatible = "qcom,sc7280-nsp-noc"; 3337 #interconnect-cells = <2>; 3338 qcom,bcm-voters = <&apps_bcm_voter>; 3339 }; 3340 3341 usb_1: usb@a6f8800 { 3342 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3343 reg = <0 0x0a6f8800 0 0x400>; 3344 status = "disabled"; 3345 #address-cells = <2>; 3346 #size-cells = <2>; 3347 ranges; 3348 dma-ranges; 3349 3350 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3351 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3352 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3353 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3354 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3355 clock-names = "cfg_noc", 3356 "core", 3357 "iface", 3358 "sleep", 3359 "mock_utmi"; 3360 3361 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3362 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3363 assigned-clock-rates = <19200000>, <200000000>; 3364 3365 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3366 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3367 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3368 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3369 interrupt-names = "hs_phy_irq", 3370 "dp_hs_phy_irq", 3371 "dm_hs_phy_irq", 3372 "ss_phy_irq"; 3373 3374 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3375 3376 resets = <&gcc GCC_USB30_PRIM_BCR>; 3377 3378 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3379 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3380 interconnect-names = "usb-ddr", "apps-usb"; 3381 3382 usb_1_dwc3: usb@a600000 { 3383 compatible = "snps,dwc3"; 3384 reg = <0 0x0a600000 0 0xe000>; 3385 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3386 iommus = <&apps_smmu 0xe0 0x0>; 3387 snps,dis_u2_susphy_quirk; 3388 snps,dis_enblslpm_quirk; 3389 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3390 phy-names = "usb2-phy", "usb3-phy"; 3391 maximum-speed = "super-speed"; 3392 wakeup-source; 3393 }; 3394 }; 3395 3396 venus: video-codec@aa00000 { 3397 compatible = "qcom,sc7280-venus"; 3398 reg = <0 0x0aa00000 0 0xd0600>; 3399 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3400 3401 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3402 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3403 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3404 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3405 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3406 clock-names = "core", "bus", "iface", 3407 "vcodec_core", "vcodec_bus"; 3408 3409 power-domains = <&videocc MVSC_GDSC>, 3410 <&videocc MVS0_GDSC>, 3411 <&rpmhpd SC7280_CX>; 3412 power-domain-names = "venus", "vcodec0", "cx"; 3413 operating-points-v2 = <&venus_opp_table>; 3414 3415 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3416 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3417 interconnect-names = "cpu-cfg", "video-mem"; 3418 3419 iommus = <&apps_smmu 0x2180 0x20>, 3420 <&apps_smmu 0x2184 0x20>; 3421 memory-region = <&video_mem>; 3422 3423 video-decoder { 3424 compatible = "venus-decoder"; 3425 }; 3426 3427 video-encoder { 3428 compatible = "venus-encoder"; 3429 }; 3430 3431 video-firmware { 3432 iommus = <&apps_smmu 0x21a2 0x0>; 3433 }; 3434 3435 venus_opp_table: opp-table { 3436 compatible = "operating-points-v2"; 3437 3438 opp-133330000 { 3439 opp-hz = /bits/ 64 <133330000>; 3440 required-opps = <&rpmhpd_opp_low_svs>; 3441 }; 3442 3443 opp-240000000 { 3444 opp-hz = /bits/ 64 <240000000>; 3445 required-opps = <&rpmhpd_opp_svs>; 3446 }; 3447 3448 opp-335000000 { 3449 opp-hz = /bits/ 64 <335000000>; 3450 required-opps = <&rpmhpd_opp_svs_l1>; 3451 }; 3452 3453 opp-424000000 { 3454 opp-hz = /bits/ 64 <424000000>; 3455 required-opps = <&rpmhpd_opp_nom>; 3456 }; 3457 3458 opp-460000048 { 3459 opp-hz = /bits/ 64 <460000048>; 3460 required-opps = <&rpmhpd_opp_turbo>; 3461 }; 3462 }; 3463 3464 }; 3465 3466 videocc: clock-controller@aaf0000 { 3467 compatible = "qcom,sc7280-videocc"; 3468 reg = <0 0xaaf0000 0 0x10000>; 3469 clocks = <&rpmhcc RPMH_CXO_CLK>, 3470 <&rpmhcc RPMH_CXO_CLK_A>; 3471 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3472 #clock-cells = <1>; 3473 #reset-cells = <1>; 3474 #power-domain-cells = <1>; 3475 }; 3476 3477 camcc: clock-controller@ad00000 { 3478 compatible = "qcom,sc7280-camcc"; 3479 reg = <0 0x0ad00000 0 0x10000>; 3480 clocks = <&rpmhcc RPMH_CXO_CLK>, 3481 <&rpmhcc RPMH_CXO_CLK_A>, 3482 <&sleep_clk>; 3483 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3484 #clock-cells = <1>; 3485 #reset-cells = <1>; 3486 #power-domain-cells = <1>; 3487 }; 3488 3489 dispcc: clock-controller@af00000 { 3490 compatible = "qcom,sc7280-dispcc"; 3491 reg = <0 0xaf00000 0 0x20000>; 3492 clocks = <&rpmhcc RPMH_CXO_CLK>, 3493 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3494 <&mdss_dsi_phy 0>, 3495 <&mdss_dsi_phy 1>, 3496 <&dp_phy 0>, 3497 <&dp_phy 1>, 3498 <&mdss_edp_phy 0>, 3499 <&mdss_edp_phy 1>; 3500 clock-names = "bi_tcxo", 3501 "gcc_disp_gpll0_clk", 3502 "dsi0_phy_pll_out_byteclk", 3503 "dsi0_phy_pll_out_dsiclk", 3504 "dp_phy_pll_link_clk", 3505 "dp_phy_pll_vco_div_clk", 3506 "edp_phy_pll_link_clk", 3507 "edp_phy_pll_vco_div_clk"; 3508 #clock-cells = <1>; 3509 #reset-cells = <1>; 3510 #power-domain-cells = <1>; 3511 }; 3512 3513 mdss: display-subsystem@ae00000 { 3514 compatible = "qcom,sc7280-mdss"; 3515 reg = <0 0x0ae00000 0 0x1000>; 3516 reg-names = "mdss"; 3517 3518 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3519 3520 clocks = <&gcc GCC_DISP_AHB_CLK>, 3521 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3522 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3523 clock-names = "iface", 3524 "ahb", 3525 "core"; 3526 3527 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3528 interrupt-controller; 3529 #interrupt-cells = <1>; 3530 3531 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3532 interconnect-names = "mdp0-mem"; 3533 3534 iommus = <&apps_smmu 0x900 0x402>; 3535 3536 #address-cells = <2>; 3537 #size-cells = <2>; 3538 ranges; 3539 3540 status = "disabled"; 3541 3542 mdss_mdp: display-controller@ae01000 { 3543 compatible = "qcom,sc7280-dpu"; 3544 reg = <0 0x0ae01000 0 0x8f030>, 3545 <0 0x0aeb0000 0 0x2008>; 3546 reg-names = "mdp", "vbif"; 3547 3548 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3549 <&gcc GCC_DISP_SF_AXI_CLK>, 3550 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3551 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3552 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3553 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3554 clock-names = "bus", 3555 "nrt_bus", 3556 "iface", 3557 "lut", 3558 "core", 3559 "vsync"; 3560 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3561 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3562 assigned-clock-rates = <19200000>, 3563 <19200000>; 3564 operating-points-v2 = <&mdp_opp_table>; 3565 power-domains = <&rpmhpd SC7280_CX>; 3566 3567 interrupt-parent = <&mdss>; 3568 interrupts = <0>; 3569 3570 status = "disabled"; 3571 3572 ports { 3573 #address-cells = <1>; 3574 #size-cells = <0>; 3575 3576 port@0 { 3577 reg = <0>; 3578 dpu_intf1_out: endpoint { 3579 remote-endpoint = <&dsi0_in>; 3580 }; 3581 }; 3582 3583 port@1 { 3584 reg = <1>; 3585 dpu_intf5_out: endpoint { 3586 remote-endpoint = <&edp_in>; 3587 }; 3588 }; 3589 3590 port@2 { 3591 reg = <2>; 3592 dpu_intf0_out: endpoint { 3593 remote-endpoint = <&dp_in>; 3594 }; 3595 }; 3596 }; 3597 3598 mdp_opp_table: opp-table { 3599 compatible = "operating-points-v2"; 3600 3601 opp-200000000 { 3602 opp-hz = /bits/ 64 <200000000>; 3603 required-opps = <&rpmhpd_opp_low_svs>; 3604 }; 3605 3606 opp-300000000 { 3607 opp-hz = /bits/ 64 <300000000>; 3608 required-opps = <&rpmhpd_opp_svs>; 3609 }; 3610 3611 opp-380000000 { 3612 opp-hz = /bits/ 64 <380000000>; 3613 required-opps = <&rpmhpd_opp_svs_l1>; 3614 }; 3615 3616 opp-506666667 { 3617 opp-hz = /bits/ 64 <506666667>; 3618 required-opps = <&rpmhpd_opp_nom>; 3619 }; 3620 }; 3621 }; 3622 3623 mdss_dsi: dsi@ae94000 { 3624 compatible = "qcom,mdss-dsi-ctrl"; 3625 reg = <0 0x0ae94000 0 0x400>; 3626 reg-names = "dsi_ctrl"; 3627 3628 interrupt-parent = <&mdss>; 3629 interrupts = <4>; 3630 3631 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3632 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3633 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3634 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3635 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3636 <&gcc GCC_DISP_HF_AXI_CLK>; 3637 clock-names = "byte", 3638 "byte_intf", 3639 "pixel", 3640 "core", 3641 "iface", 3642 "bus"; 3643 3644 operating-points-v2 = <&dsi_opp_table>; 3645 power-domains = <&rpmhpd SC7280_CX>; 3646 3647 phys = <&mdss_dsi_phy>; 3648 phy-names = "dsi"; 3649 3650 #address-cells = <1>; 3651 #size-cells = <0>; 3652 3653 status = "disabled"; 3654 3655 ports { 3656 #address-cells = <1>; 3657 #size-cells = <0>; 3658 3659 port@0 { 3660 reg = <0>; 3661 dsi0_in: endpoint { 3662 remote-endpoint = <&dpu_intf1_out>; 3663 }; 3664 }; 3665 3666 port@1 { 3667 reg = <1>; 3668 dsi0_out: endpoint { 3669 }; 3670 }; 3671 }; 3672 3673 dsi_opp_table: opp-table { 3674 compatible = "operating-points-v2"; 3675 3676 opp-187500000 { 3677 opp-hz = /bits/ 64 <187500000>; 3678 required-opps = <&rpmhpd_opp_low_svs>; 3679 }; 3680 3681 opp-300000000 { 3682 opp-hz = /bits/ 64 <300000000>; 3683 required-opps = <&rpmhpd_opp_svs>; 3684 }; 3685 3686 opp-358000000 { 3687 opp-hz = /bits/ 64 <358000000>; 3688 required-opps = <&rpmhpd_opp_svs_l1>; 3689 }; 3690 }; 3691 }; 3692 3693 mdss_dsi_phy: phy@ae94400 { 3694 compatible = "qcom,sc7280-dsi-phy-7nm"; 3695 reg = <0 0x0ae94400 0 0x200>, 3696 <0 0x0ae94600 0 0x280>, 3697 <0 0x0ae94900 0 0x280>; 3698 reg-names = "dsi_phy", 3699 "dsi_phy_lane", 3700 "dsi_pll"; 3701 3702 #clock-cells = <1>; 3703 #phy-cells = <0>; 3704 3705 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3706 <&rpmhcc RPMH_CXO_CLK>; 3707 clock-names = "iface", "ref"; 3708 3709 status = "disabled"; 3710 }; 3711 3712 mdss_edp: edp@aea0000 { 3713 compatible = "qcom,sc7280-edp"; 3714 pinctrl-names = "default"; 3715 pinctrl-0 = <&edp_hot_plug_det>; 3716 3717 reg = <0 0xaea0000 0 0x200>, 3718 <0 0xaea0200 0 0x200>, 3719 <0 0xaea0400 0 0xc00>, 3720 <0 0xaea1000 0 0x400>; 3721 3722 interrupt-parent = <&mdss>; 3723 interrupts = <14>; 3724 3725 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3726 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3727 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3728 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3729 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3730 clock-names = "core_iface", 3731 "core_aux", 3732 "ctrl_link", 3733 "ctrl_link_iface", 3734 "stream_pixel"; 3735 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3736 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3737 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3738 3739 phys = <&mdss_edp_phy>; 3740 phy-names = "dp"; 3741 3742 operating-points-v2 = <&edp_opp_table>; 3743 power-domains = <&rpmhpd SC7280_CX>; 3744 3745 status = "disabled"; 3746 3747 ports { 3748 #address-cells = <1>; 3749 #size-cells = <0>; 3750 3751 port@0 { 3752 reg = <0>; 3753 edp_in: endpoint { 3754 remote-endpoint = <&dpu_intf5_out>; 3755 }; 3756 }; 3757 3758 port@1 { 3759 reg = <1>; 3760 mdss_edp_out: endpoint { }; 3761 }; 3762 }; 3763 3764 edp_opp_table: opp-table { 3765 compatible = "operating-points-v2"; 3766 3767 opp-160000000 { 3768 opp-hz = /bits/ 64 <160000000>; 3769 required-opps = <&rpmhpd_opp_low_svs>; 3770 }; 3771 3772 opp-270000000 { 3773 opp-hz = /bits/ 64 <270000000>; 3774 required-opps = <&rpmhpd_opp_svs>; 3775 }; 3776 3777 opp-540000000 { 3778 opp-hz = /bits/ 64 <540000000>; 3779 required-opps = <&rpmhpd_opp_nom>; 3780 }; 3781 3782 opp-810000000 { 3783 opp-hz = /bits/ 64 <810000000>; 3784 required-opps = <&rpmhpd_opp_nom>; 3785 }; 3786 }; 3787 }; 3788 3789 mdss_edp_phy: phy@aec2a00 { 3790 compatible = "qcom,sc7280-edp-phy"; 3791 3792 reg = <0 0xaec2a00 0 0x19c>, 3793 <0 0xaec2200 0 0xa0>, 3794 <0 0xaec2600 0 0xa0>, 3795 <0 0xaec2000 0 0x1c0>; 3796 3797 clocks = <&rpmhcc RPMH_CXO_CLK>, 3798 <&gcc GCC_EDP_CLKREF_EN>; 3799 clock-names = "aux", 3800 "cfg_ahb"; 3801 3802 #clock-cells = <1>; 3803 #phy-cells = <0>; 3804 3805 status = "disabled"; 3806 }; 3807 3808 mdss_dp: displayport-controller@ae90000 { 3809 compatible = "qcom,sc7280-dp"; 3810 3811 reg = <0 0xae90000 0 0x200>, 3812 <0 0xae90200 0 0x200>, 3813 <0 0xae90400 0 0xc00>, 3814 <0 0xae91000 0 0x400>, 3815 <0 0xae91400 0 0x400>; 3816 3817 interrupt-parent = <&mdss>; 3818 interrupts = <12>; 3819 3820 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3821 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3822 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3823 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3824 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3825 clock-names = "core_iface", 3826 "core_aux", 3827 "ctrl_link", 3828 "ctrl_link_iface", 3829 "stream_pixel"; 3830 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3831 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3832 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3833 phys = <&dp_phy>; 3834 phy-names = "dp"; 3835 3836 operating-points-v2 = <&dp_opp_table>; 3837 power-domains = <&rpmhpd SC7280_CX>; 3838 3839 #sound-dai-cells = <0>; 3840 3841 status = "disabled"; 3842 3843 ports { 3844 #address-cells = <1>; 3845 #size-cells = <0>; 3846 3847 port@0 { 3848 reg = <0>; 3849 dp_in: endpoint { 3850 remote-endpoint = <&dpu_intf0_out>; 3851 }; 3852 }; 3853 3854 port@1 { 3855 reg = <1>; 3856 dp_out: endpoint { }; 3857 }; 3858 }; 3859 3860 dp_opp_table: opp-table { 3861 compatible = "operating-points-v2"; 3862 3863 opp-160000000 { 3864 opp-hz = /bits/ 64 <160000000>; 3865 required-opps = <&rpmhpd_opp_low_svs>; 3866 }; 3867 3868 opp-270000000 { 3869 opp-hz = /bits/ 64 <270000000>; 3870 required-opps = <&rpmhpd_opp_svs>; 3871 }; 3872 3873 opp-540000000 { 3874 opp-hz = /bits/ 64 <540000000>; 3875 required-opps = <&rpmhpd_opp_svs_l1>; 3876 }; 3877 3878 opp-810000000 { 3879 opp-hz = /bits/ 64 <810000000>; 3880 required-opps = <&rpmhpd_opp_nom>; 3881 }; 3882 }; 3883 }; 3884 }; 3885 3886 pdc: interrupt-controller@b220000 { 3887 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3888 reg = <0 0x0b220000 0 0x30000>; 3889 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3890 <55 306 4>, <59 312 3>, <62 374 2>, 3891 <64 434 2>, <66 438 3>, <69 86 1>, 3892 <70 520 54>, <124 609 31>, <155 63 1>, 3893 <156 716 12>; 3894 #interrupt-cells = <2>; 3895 interrupt-parent = <&intc>; 3896 interrupt-controller; 3897 }; 3898 3899 pdc_reset: reset-controller@b5e0000 { 3900 compatible = "qcom,sc7280-pdc-global"; 3901 reg = <0 0x0b5e0000 0 0x20000>; 3902 #reset-cells = <1>; 3903 }; 3904 3905 tsens0: thermal-sensor@c263000 { 3906 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3907 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3908 <0 0x0c222000 0 0x1ff>; /* SROT */ 3909 #qcom,sensors = <15>; 3910 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3912 interrupt-names = "uplow","critical"; 3913 #thermal-sensor-cells = <1>; 3914 }; 3915 3916 tsens1: thermal-sensor@c265000 { 3917 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3918 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3919 <0 0x0c223000 0 0x1ff>; /* SROT */ 3920 #qcom,sensors = <12>; 3921 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3923 interrupt-names = "uplow","critical"; 3924 #thermal-sensor-cells = <1>; 3925 }; 3926 3927 aoss_reset: reset-controller@c2a0000 { 3928 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3929 reg = <0 0x0c2a0000 0 0x31000>; 3930 #reset-cells = <1>; 3931 }; 3932 3933 aoss_qmp: power-controller@c300000 { 3934 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 3935 reg = <0 0x0c300000 0 0x400>; 3936 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3937 IPCC_MPROC_SIGNAL_GLINK_QMP 3938 IRQ_TYPE_EDGE_RISING>; 3939 mboxes = <&ipcc IPCC_CLIENT_AOP 3940 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3941 3942 #clock-cells = <0>; 3943 }; 3944 3945 sram@c3f0000 { 3946 compatible = "qcom,rpmh-stats"; 3947 reg = <0 0x0c3f0000 0 0x400>; 3948 }; 3949 3950 spmi_bus: spmi@c440000 { 3951 compatible = "qcom,spmi-pmic-arb"; 3952 reg = <0 0x0c440000 0 0x1100>, 3953 <0 0x0c600000 0 0x2000000>, 3954 <0 0x0e600000 0 0x100000>, 3955 <0 0x0e700000 0 0xa0000>, 3956 <0 0x0c40a000 0 0x26000>; 3957 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3958 interrupt-names = "periph_irq"; 3959 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3960 qcom,ee = <0>; 3961 qcom,channel = <0>; 3962 #address-cells = <1>; 3963 #size-cells = <1>; 3964 interrupt-controller; 3965 #interrupt-cells = <4>; 3966 }; 3967 3968 tlmm: pinctrl@f100000 { 3969 compatible = "qcom,sc7280-pinctrl"; 3970 reg = <0 0x0f100000 0 0x300000>; 3971 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3972 gpio-controller; 3973 #gpio-cells = <2>; 3974 interrupt-controller; 3975 #interrupt-cells = <2>; 3976 gpio-ranges = <&tlmm 0 0 175>; 3977 wakeup-parent = <&pdc>; 3978 3979 dp_hot_plug_det: dp-hot-plug-det { 3980 pins = "gpio47"; 3981 function = "dp_hot"; 3982 }; 3983 3984 edp_hot_plug_det: edp-hot-plug-det { 3985 pins = "gpio60"; 3986 function = "edp_hot"; 3987 }; 3988 3989 mi2s0_data0: mi2s0-data0 { 3990 pins = "gpio98"; 3991 function = "mi2s0_data0"; 3992 }; 3993 3994 mi2s0_data1: mi2s0-data1 { 3995 pins = "gpio99"; 3996 function = "mi2s0_data1"; 3997 }; 3998 3999 mi2s0_mclk: mi2s0-mclk { 4000 pins = "gpio96"; 4001 function = "pri_mi2s"; 4002 }; 4003 4004 mi2s0_sclk: mi2s0-sclk { 4005 pins = "gpio97"; 4006 function = "mi2s0_sck"; 4007 }; 4008 4009 mi2s0_ws: mi2s0-ws { 4010 pins = "gpio100"; 4011 function = "mi2s0_ws"; 4012 }; 4013 4014 mi2s1_data0: mi2s1-data0 { 4015 pins = "gpio107"; 4016 function = "mi2s1_data0"; 4017 }; 4018 4019 mi2s1_sclk: mi2s1-sclk { 4020 pins = "gpio106"; 4021 function = "mi2s1_sck"; 4022 }; 4023 4024 mi2s1_ws: mi2s1-ws { 4025 pins = "gpio108"; 4026 function = "mi2s1_ws"; 4027 }; 4028 4029 pcie1_clkreq_n: pcie1-clkreq-n { 4030 pins = "gpio79"; 4031 function = "pcie1_clkreqn"; 4032 }; 4033 4034 qspi_clk: qspi-clk { 4035 pins = "gpio14"; 4036 function = "qspi_clk"; 4037 }; 4038 4039 qspi_cs0: qspi-cs0 { 4040 pins = "gpio15"; 4041 function = "qspi_cs"; 4042 }; 4043 4044 qspi_cs1: qspi-cs1 { 4045 pins = "gpio19"; 4046 function = "qspi_cs"; 4047 }; 4048 4049 qspi_data01: qspi-data01 { 4050 pins = "gpio12", "gpio13"; 4051 function = "qspi_data"; 4052 }; 4053 4054 qspi_data12: qspi-data12 { 4055 pins = "gpio16", "gpio17"; 4056 function = "qspi_data"; 4057 }; 4058 4059 qup_i2c0_data_clk: qup-i2c0-data-clk { 4060 pins = "gpio0", "gpio1"; 4061 function = "qup00"; 4062 }; 4063 4064 qup_i2c1_data_clk: qup-i2c1-data-clk { 4065 pins = "gpio4", "gpio5"; 4066 function = "qup01"; 4067 }; 4068 4069 qup_i2c2_data_clk: qup-i2c2-data-clk { 4070 pins = "gpio8", "gpio9"; 4071 function = "qup02"; 4072 }; 4073 4074 qup_i2c3_data_clk: qup-i2c3-data-clk { 4075 pins = "gpio12", "gpio13"; 4076 function = "qup03"; 4077 }; 4078 4079 qup_i2c4_data_clk: qup-i2c4-data-clk { 4080 pins = "gpio16", "gpio17"; 4081 function = "qup04"; 4082 }; 4083 4084 qup_i2c5_data_clk: qup-i2c5-data-clk { 4085 pins = "gpio20", "gpio21"; 4086 function = "qup05"; 4087 }; 4088 4089 qup_i2c6_data_clk: qup-i2c6-data-clk { 4090 pins = "gpio24", "gpio25"; 4091 function = "qup06"; 4092 }; 4093 4094 qup_i2c7_data_clk: qup-i2c7-data-clk { 4095 pins = "gpio28", "gpio29"; 4096 function = "qup07"; 4097 }; 4098 4099 qup_i2c8_data_clk: qup-i2c8-data-clk { 4100 pins = "gpio32", "gpio33"; 4101 function = "qup10"; 4102 }; 4103 4104 qup_i2c9_data_clk: qup-i2c9-data-clk { 4105 pins = "gpio36", "gpio37"; 4106 function = "qup11"; 4107 }; 4108 4109 qup_i2c10_data_clk: qup-i2c10-data-clk { 4110 pins = "gpio40", "gpio41"; 4111 function = "qup12"; 4112 }; 4113 4114 qup_i2c11_data_clk: qup-i2c11-data-clk { 4115 pins = "gpio44", "gpio45"; 4116 function = "qup13"; 4117 }; 4118 4119 qup_i2c12_data_clk: qup-i2c12-data-clk { 4120 pins = "gpio48", "gpio49"; 4121 function = "qup14"; 4122 }; 4123 4124 qup_i2c13_data_clk: qup-i2c13-data-clk { 4125 pins = "gpio52", "gpio53"; 4126 function = "qup15"; 4127 }; 4128 4129 qup_i2c14_data_clk: qup-i2c14-data-clk { 4130 pins = "gpio56", "gpio57"; 4131 function = "qup16"; 4132 }; 4133 4134 qup_i2c15_data_clk: qup-i2c15-data-clk { 4135 pins = "gpio60", "gpio61"; 4136 function = "qup17"; 4137 }; 4138 4139 qup_spi0_data_clk: qup-spi0-data-clk { 4140 pins = "gpio0", "gpio1", "gpio2"; 4141 function = "qup00"; 4142 }; 4143 4144 qup_spi0_cs: qup-spi0-cs { 4145 pins = "gpio3"; 4146 function = "qup00"; 4147 }; 4148 4149 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 4150 pins = "gpio3"; 4151 function = "gpio"; 4152 }; 4153 4154 qup_spi1_data_clk: qup-spi1-data-clk { 4155 pins = "gpio4", "gpio5", "gpio6"; 4156 function = "qup01"; 4157 }; 4158 4159 qup_spi1_cs: qup-spi1-cs { 4160 pins = "gpio7"; 4161 function = "qup01"; 4162 }; 4163 4164 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 4165 pins = "gpio7"; 4166 function = "gpio"; 4167 }; 4168 4169 qup_spi2_data_clk: qup-spi2-data-clk { 4170 pins = "gpio8", "gpio9", "gpio10"; 4171 function = "qup02"; 4172 }; 4173 4174 qup_spi2_cs: qup-spi2-cs { 4175 pins = "gpio11"; 4176 function = "qup02"; 4177 }; 4178 4179 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 4180 pins = "gpio11"; 4181 function = "gpio"; 4182 }; 4183 4184 qup_spi3_data_clk: qup-spi3-data-clk { 4185 pins = "gpio12", "gpio13", "gpio14"; 4186 function = "qup03"; 4187 }; 4188 4189 qup_spi3_cs: qup-spi3-cs { 4190 pins = "gpio15"; 4191 function = "qup03"; 4192 }; 4193 4194 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 4195 pins = "gpio15"; 4196 function = "gpio"; 4197 }; 4198 4199 qup_spi4_data_clk: qup-spi4-data-clk { 4200 pins = "gpio16", "gpio17", "gpio18"; 4201 function = "qup04"; 4202 }; 4203 4204 qup_spi4_cs: qup-spi4-cs { 4205 pins = "gpio19"; 4206 function = "qup04"; 4207 }; 4208 4209 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 4210 pins = "gpio19"; 4211 function = "gpio"; 4212 }; 4213 4214 qup_spi5_data_clk: qup-spi5-data-clk { 4215 pins = "gpio20", "gpio21", "gpio22"; 4216 function = "qup05"; 4217 }; 4218 4219 qup_spi5_cs: qup-spi5-cs { 4220 pins = "gpio23"; 4221 function = "qup05"; 4222 }; 4223 4224 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 4225 pins = "gpio23"; 4226 function = "gpio"; 4227 }; 4228 4229 qup_spi6_data_clk: qup-spi6-data-clk { 4230 pins = "gpio24", "gpio25", "gpio26"; 4231 function = "qup06"; 4232 }; 4233 4234 qup_spi6_cs: qup-spi6-cs { 4235 pins = "gpio27"; 4236 function = "qup06"; 4237 }; 4238 4239 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 4240 pins = "gpio27"; 4241 function = "gpio"; 4242 }; 4243 4244 qup_spi7_data_clk: qup-spi7-data-clk { 4245 pins = "gpio28", "gpio29", "gpio30"; 4246 function = "qup07"; 4247 }; 4248 4249 qup_spi7_cs: qup-spi7-cs { 4250 pins = "gpio31"; 4251 function = "qup07"; 4252 }; 4253 4254 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 4255 pins = "gpio31"; 4256 function = "gpio"; 4257 }; 4258 4259 qup_spi8_data_clk: qup-spi8-data-clk { 4260 pins = "gpio32", "gpio33", "gpio34"; 4261 function = "qup10"; 4262 }; 4263 4264 qup_spi8_cs: qup-spi8-cs { 4265 pins = "gpio35"; 4266 function = "qup10"; 4267 }; 4268 4269 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4270 pins = "gpio35"; 4271 function = "gpio"; 4272 }; 4273 4274 qup_spi9_data_clk: qup-spi9-data-clk { 4275 pins = "gpio36", "gpio37", "gpio38"; 4276 function = "qup11"; 4277 }; 4278 4279 qup_spi9_cs: qup-spi9-cs { 4280 pins = "gpio39"; 4281 function = "qup11"; 4282 }; 4283 4284 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4285 pins = "gpio39"; 4286 function = "gpio"; 4287 }; 4288 4289 qup_spi10_data_clk: qup-spi10-data-clk { 4290 pins = "gpio40", "gpio41", "gpio42"; 4291 function = "qup12"; 4292 }; 4293 4294 qup_spi10_cs: qup-spi10-cs { 4295 pins = "gpio43"; 4296 function = "qup12"; 4297 }; 4298 4299 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4300 pins = "gpio43"; 4301 function = "gpio"; 4302 }; 4303 4304 qup_spi11_data_clk: qup-spi11-data-clk { 4305 pins = "gpio44", "gpio45", "gpio46"; 4306 function = "qup13"; 4307 }; 4308 4309 qup_spi11_cs: qup-spi11-cs { 4310 pins = "gpio47"; 4311 function = "qup13"; 4312 }; 4313 4314 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4315 pins = "gpio47"; 4316 function = "gpio"; 4317 }; 4318 4319 qup_spi12_data_clk: qup-spi12-data-clk { 4320 pins = "gpio48", "gpio49", "gpio50"; 4321 function = "qup14"; 4322 }; 4323 4324 qup_spi12_cs: qup-spi12-cs { 4325 pins = "gpio51"; 4326 function = "qup14"; 4327 }; 4328 4329 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4330 pins = "gpio51"; 4331 function = "gpio"; 4332 }; 4333 4334 qup_spi13_data_clk: qup-spi13-data-clk { 4335 pins = "gpio52", "gpio53", "gpio54"; 4336 function = "qup15"; 4337 }; 4338 4339 qup_spi13_cs: qup-spi13-cs { 4340 pins = "gpio55"; 4341 function = "qup15"; 4342 }; 4343 4344 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4345 pins = "gpio55"; 4346 function = "gpio"; 4347 }; 4348 4349 qup_spi14_data_clk: qup-spi14-data-clk { 4350 pins = "gpio56", "gpio57", "gpio58"; 4351 function = "qup16"; 4352 }; 4353 4354 qup_spi14_cs: qup-spi14-cs { 4355 pins = "gpio59"; 4356 function = "qup16"; 4357 }; 4358 4359 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4360 pins = "gpio59"; 4361 function = "gpio"; 4362 }; 4363 4364 qup_spi15_data_clk: qup-spi15-data-clk { 4365 pins = "gpio60", "gpio61", "gpio62"; 4366 function = "qup17"; 4367 }; 4368 4369 qup_spi15_cs: qup-spi15-cs { 4370 pins = "gpio63"; 4371 function = "qup17"; 4372 }; 4373 4374 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4375 pins = "gpio63"; 4376 function = "gpio"; 4377 }; 4378 4379 qup_uart0_cts: qup-uart0-cts { 4380 pins = "gpio0"; 4381 function = "qup00"; 4382 }; 4383 4384 qup_uart0_rts: qup-uart0-rts { 4385 pins = "gpio1"; 4386 function = "qup00"; 4387 }; 4388 4389 qup_uart0_tx: qup-uart0-tx { 4390 pins = "gpio2"; 4391 function = "qup00"; 4392 }; 4393 4394 qup_uart0_rx: qup-uart0-rx { 4395 pins = "gpio3"; 4396 function = "qup00"; 4397 }; 4398 4399 qup_uart1_cts: qup-uart1-cts { 4400 pins = "gpio4"; 4401 function = "qup01"; 4402 }; 4403 4404 qup_uart1_rts: qup-uart1-rts { 4405 pins = "gpio5"; 4406 function = "qup01"; 4407 }; 4408 4409 qup_uart1_tx: qup-uart1-tx { 4410 pins = "gpio6"; 4411 function = "qup01"; 4412 }; 4413 4414 qup_uart1_rx: qup-uart1-rx { 4415 pins = "gpio7"; 4416 function = "qup01"; 4417 }; 4418 4419 qup_uart2_cts: qup-uart2-cts { 4420 pins = "gpio8"; 4421 function = "qup02"; 4422 }; 4423 4424 qup_uart2_rts: qup-uart2-rts { 4425 pins = "gpio9"; 4426 function = "qup02"; 4427 }; 4428 4429 qup_uart2_tx: qup-uart2-tx { 4430 pins = "gpio10"; 4431 function = "qup02"; 4432 }; 4433 4434 qup_uart2_rx: qup-uart2-rx { 4435 pins = "gpio11"; 4436 function = "qup02"; 4437 }; 4438 4439 qup_uart3_cts: qup-uart3-cts { 4440 pins = "gpio12"; 4441 function = "qup03"; 4442 }; 4443 4444 qup_uart3_rts: qup-uart3-rts { 4445 pins = "gpio13"; 4446 function = "qup03"; 4447 }; 4448 4449 qup_uart3_tx: qup-uart3-tx { 4450 pins = "gpio14"; 4451 function = "qup03"; 4452 }; 4453 4454 qup_uart3_rx: qup-uart3-rx { 4455 pins = "gpio15"; 4456 function = "qup03"; 4457 }; 4458 4459 qup_uart4_cts: qup-uart4-cts { 4460 pins = "gpio16"; 4461 function = "qup04"; 4462 }; 4463 4464 qup_uart4_rts: qup-uart4-rts { 4465 pins = "gpio17"; 4466 function = "qup04"; 4467 }; 4468 4469 qup_uart4_tx: qup-uart4-tx { 4470 pins = "gpio18"; 4471 function = "qup04"; 4472 }; 4473 4474 qup_uart4_rx: qup-uart4-rx { 4475 pins = "gpio19"; 4476 function = "qup04"; 4477 }; 4478 4479 qup_uart5_cts: qup-uart5-cts { 4480 pins = "gpio20"; 4481 function = "qup05"; 4482 }; 4483 4484 qup_uart5_rts: qup-uart5-rts { 4485 pins = "gpio21"; 4486 function = "qup05"; 4487 }; 4488 4489 qup_uart5_tx: qup-uart5-tx { 4490 pins = "gpio22"; 4491 function = "qup05"; 4492 }; 4493 4494 qup_uart5_rx: qup-uart5-rx { 4495 pins = "gpio23"; 4496 function = "qup05"; 4497 }; 4498 4499 qup_uart6_cts: qup-uart6-cts { 4500 pins = "gpio24"; 4501 function = "qup06"; 4502 }; 4503 4504 qup_uart6_rts: qup-uart6-rts { 4505 pins = "gpio25"; 4506 function = "qup06"; 4507 }; 4508 4509 qup_uart6_tx: qup-uart6-tx { 4510 pins = "gpio26"; 4511 function = "qup06"; 4512 }; 4513 4514 qup_uart6_rx: qup-uart6-rx { 4515 pins = "gpio27"; 4516 function = "qup06"; 4517 }; 4518 4519 qup_uart7_cts: qup-uart7-cts { 4520 pins = "gpio28"; 4521 function = "qup07"; 4522 }; 4523 4524 qup_uart7_rts: qup-uart7-rts { 4525 pins = "gpio29"; 4526 function = "qup07"; 4527 }; 4528 4529 qup_uart7_tx: qup-uart7-tx { 4530 pins = "gpio30"; 4531 function = "qup07"; 4532 }; 4533 4534 qup_uart7_rx: qup-uart7-rx { 4535 pins = "gpio31"; 4536 function = "qup07"; 4537 }; 4538 4539 qup_uart8_cts: qup-uart8-cts { 4540 pins = "gpio32"; 4541 function = "qup10"; 4542 }; 4543 4544 qup_uart8_rts: qup-uart8-rts { 4545 pins = "gpio33"; 4546 function = "qup10"; 4547 }; 4548 4549 qup_uart8_tx: qup-uart8-tx { 4550 pins = "gpio34"; 4551 function = "qup10"; 4552 }; 4553 4554 qup_uart8_rx: qup-uart8-rx { 4555 pins = "gpio35"; 4556 function = "qup10"; 4557 }; 4558 4559 qup_uart9_cts: qup-uart9-cts { 4560 pins = "gpio36"; 4561 function = "qup11"; 4562 }; 4563 4564 qup_uart9_rts: qup-uart9-rts { 4565 pins = "gpio37"; 4566 function = "qup11"; 4567 }; 4568 4569 qup_uart9_tx: qup-uart9-tx { 4570 pins = "gpio38"; 4571 function = "qup11"; 4572 }; 4573 4574 qup_uart9_rx: qup-uart9-rx { 4575 pins = "gpio39"; 4576 function = "qup11"; 4577 }; 4578 4579 qup_uart10_cts: qup-uart10-cts { 4580 pins = "gpio40"; 4581 function = "qup12"; 4582 }; 4583 4584 qup_uart10_rts: qup-uart10-rts { 4585 pins = "gpio41"; 4586 function = "qup12"; 4587 }; 4588 4589 qup_uart10_tx: qup-uart10-tx { 4590 pins = "gpio42"; 4591 function = "qup12"; 4592 }; 4593 4594 qup_uart10_rx: qup-uart10-rx { 4595 pins = "gpio43"; 4596 function = "qup12"; 4597 }; 4598 4599 qup_uart11_cts: qup-uart11-cts { 4600 pins = "gpio44"; 4601 function = "qup13"; 4602 }; 4603 4604 qup_uart11_rts: qup-uart11-rts { 4605 pins = "gpio45"; 4606 function = "qup13"; 4607 }; 4608 4609 qup_uart11_tx: qup-uart11-tx { 4610 pins = "gpio46"; 4611 function = "qup13"; 4612 }; 4613 4614 qup_uart11_rx: qup-uart11-rx { 4615 pins = "gpio47"; 4616 function = "qup13"; 4617 }; 4618 4619 qup_uart12_cts: qup-uart12-cts { 4620 pins = "gpio48"; 4621 function = "qup14"; 4622 }; 4623 4624 qup_uart12_rts: qup-uart12-rts { 4625 pins = "gpio49"; 4626 function = "qup14"; 4627 }; 4628 4629 qup_uart12_tx: qup-uart12-tx { 4630 pins = "gpio50"; 4631 function = "qup14"; 4632 }; 4633 4634 qup_uart12_rx: qup-uart12-rx { 4635 pins = "gpio51"; 4636 function = "qup14"; 4637 }; 4638 4639 qup_uart13_cts: qup-uart13-cts { 4640 pins = "gpio52"; 4641 function = "qup15"; 4642 }; 4643 4644 qup_uart13_rts: qup-uart13-rts { 4645 pins = "gpio53"; 4646 function = "qup15"; 4647 }; 4648 4649 qup_uart13_tx: qup-uart13-tx { 4650 pins = "gpio54"; 4651 function = "qup15"; 4652 }; 4653 4654 qup_uart13_rx: qup-uart13-rx { 4655 pins = "gpio55"; 4656 function = "qup15"; 4657 }; 4658 4659 qup_uart14_cts: qup-uart14-cts { 4660 pins = "gpio56"; 4661 function = "qup16"; 4662 }; 4663 4664 qup_uart14_rts: qup-uart14-rts { 4665 pins = "gpio57"; 4666 function = "qup16"; 4667 }; 4668 4669 qup_uart14_tx: qup-uart14-tx { 4670 pins = "gpio58"; 4671 function = "qup16"; 4672 }; 4673 4674 qup_uart14_rx: qup-uart14-rx { 4675 pins = "gpio59"; 4676 function = "qup16"; 4677 }; 4678 4679 qup_uart15_cts: qup-uart15-cts { 4680 pins = "gpio60"; 4681 function = "qup17"; 4682 }; 4683 4684 qup_uart15_rts: qup-uart15-rts { 4685 pins = "gpio61"; 4686 function = "qup17"; 4687 }; 4688 4689 qup_uart15_tx: qup-uart15-tx { 4690 pins = "gpio62"; 4691 function = "qup17"; 4692 }; 4693 4694 qup_uart15_rx: qup-uart15-rx { 4695 pins = "gpio63"; 4696 function = "qup17"; 4697 }; 4698 4699 sdc1_clk: sdc1-clk { 4700 pins = "sdc1_clk"; 4701 }; 4702 4703 sdc1_cmd: sdc1-cmd { 4704 pins = "sdc1_cmd"; 4705 }; 4706 4707 sdc1_data: sdc1-data { 4708 pins = "sdc1_data"; 4709 }; 4710 4711 sdc1_rclk: sdc1-rclk { 4712 pins = "sdc1_rclk"; 4713 }; 4714 4715 sdc1_clk_sleep: sdc1-clk-sleep { 4716 pins = "sdc1_clk"; 4717 drive-strength = <2>; 4718 bias-bus-hold; 4719 }; 4720 4721 sdc1_cmd_sleep: sdc1-cmd-sleep { 4722 pins = "sdc1_cmd"; 4723 drive-strength = <2>; 4724 bias-bus-hold; 4725 }; 4726 4727 sdc1_data_sleep: sdc1-data-sleep { 4728 pins = "sdc1_data"; 4729 drive-strength = <2>; 4730 bias-bus-hold; 4731 }; 4732 4733 sdc1_rclk_sleep: sdc1-rclk-sleep { 4734 pins = "sdc1_rclk"; 4735 drive-strength = <2>; 4736 bias-bus-hold; 4737 }; 4738 4739 sdc2_clk: sdc2-clk { 4740 pins = "sdc2_clk"; 4741 }; 4742 4743 sdc2_cmd: sdc2-cmd { 4744 pins = "sdc2_cmd"; 4745 }; 4746 4747 sdc2_data: sdc2-data { 4748 pins = "sdc2_data"; 4749 }; 4750 4751 sdc2_clk_sleep: sdc2-clk-sleep { 4752 pins = "sdc2_clk"; 4753 drive-strength = <2>; 4754 bias-bus-hold; 4755 }; 4756 4757 sdc2_cmd_sleep: sdc2-cmd-sleep { 4758 pins = "sdc2_cmd"; 4759 drive-strength = <2>; 4760 bias-bus-hold; 4761 }; 4762 4763 sdc2_data_sleep: sdc2-data-sleep { 4764 pins = "sdc2_data"; 4765 drive-strength = <2>; 4766 bias-bus-hold; 4767 }; 4768 }; 4769 4770 sram@146a5000 { 4771 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 4772 reg = <0 0x146a5000 0 0x6000>; 4773 4774 #address-cells = <1>; 4775 #size-cells = <1>; 4776 4777 ranges = <0 0 0x146a5000 0x6000>; 4778 4779 pil-reloc@594c { 4780 compatible = "qcom,pil-reloc-info"; 4781 reg = <0x594c 0xc8>; 4782 }; 4783 }; 4784 4785 apps_smmu: iommu@15000000 { 4786 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4787 reg = <0 0x15000000 0 0x100000>; 4788 #iommu-cells = <2>; 4789 #global-interrupts = <1>; 4790 dma-coherent; 4791 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4792 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4793 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4794 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4795 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4796 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4797 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4798 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4799 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4800 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4801 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4802 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4803 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4804 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4805 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4806 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4807 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4808 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4809 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4810 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4811 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4812 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4813 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4814 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4815 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4816 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4817 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4818 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4819 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4820 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4821 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4822 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4823 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4824 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4825 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4826 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4827 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4828 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4829 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4830 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4831 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4832 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4833 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4834 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4835 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4836 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4837 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4838 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4839 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4840 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4841 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4842 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4843 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4844 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4845 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4846 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4847 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4848 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4849 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4850 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4851 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4852 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4853 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4854 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4855 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4856 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4857 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4858 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4859 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4860 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4861 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4862 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4863 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4864 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4865 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4866 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4868 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4869 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4870 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4871 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4872 }; 4873 4874 intc: interrupt-controller@17a00000 { 4875 compatible = "arm,gic-v3"; 4876 #address-cells = <2>; 4877 #size-cells = <2>; 4878 ranges; 4879 #interrupt-cells = <3>; 4880 interrupt-controller; 4881 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4882 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4883 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4884 4885 gic-its@17a40000 { 4886 compatible = "arm,gic-v3-its"; 4887 msi-controller; 4888 #msi-cells = <1>; 4889 reg = <0 0x17a40000 0 0x20000>; 4890 status = "disabled"; 4891 }; 4892 }; 4893 4894 watchdog@17c10000 { 4895 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4896 reg = <0 0x17c10000 0 0x1000>; 4897 clocks = <&sleep_clk>; 4898 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4899 }; 4900 4901 timer@17c20000 { 4902 #address-cells = <1>; 4903 #size-cells = <1>; 4904 ranges = <0 0 0 0x20000000>; 4905 compatible = "arm,armv7-timer-mem"; 4906 reg = <0 0x17c20000 0 0x1000>; 4907 4908 frame@17c21000 { 4909 frame-number = <0>; 4910 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4911 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4912 reg = <0x17c21000 0x1000>, 4913 <0x17c22000 0x1000>; 4914 }; 4915 4916 frame@17c23000 { 4917 frame-number = <1>; 4918 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4919 reg = <0x17c23000 0x1000>; 4920 status = "disabled"; 4921 }; 4922 4923 frame@17c25000 { 4924 frame-number = <2>; 4925 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4926 reg = <0x17c25000 0x1000>; 4927 status = "disabled"; 4928 }; 4929 4930 frame@17c27000 { 4931 frame-number = <3>; 4932 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4933 reg = <0x17c27000 0x1000>; 4934 status = "disabled"; 4935 }; 4936 4937 frame@17c29000 { 4938 frame-number = <4>; 4939 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4940 reg = <0x17c29000 0x1000>; 4941 status = "disabled"; 4942 }; 4943 4944 frame@17c2b000 { 4945 frame-number = <5>; 4946 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4947 reg = <0x17c2b000 0x1000>; 4948 status = "disabled"; 4949 }; 4950 4951 frame@17c2d000 { 4952 frame-number = <6>; 4953 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4954 reg = <0x17c2d000 0x1000>; 4955 status = "disabled"; 4956 }; 4957 }; 4958 4959 apps_rsc: rsc@18200000 { 4960 compatible = "qcom,rpmh-rsc"; 4961 reg = <0 0x18200000 0 0x10000>, 4962 <0 0x18210000 0 0x10000>, 4963 <0 0x18220000 0 0x10000>; 4964 reg-names = "drv-0", "drv-1", "drv-2"; 4965 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4966 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4967 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4968 qcom,tcs-offset = <0xd00>; 4969 qcom,drv-id = <2>; 4970 qcom,tcs-config = <ACTIVE_TCS 2>, 4971 <SLEEP_TCS 3>, 4972 <WAKE_TCS 3>, 4973 <CONTROL_TCS 1>; 4974 4975 apps_bcm_voter: bcm-voter { 4976 compatible = "qcom,bcm-voter"; 4977 }; 4978 4979 rpmhpd: power-controller { 4980 compatible = "qcom,sc7280-rpmhpd"; 4981 #power-domain-cells = <1>; 4982 operating-points-v2 = <&rpmhpd_opp_table>; 4983 4984 rpmhpd_opp_table: opp-table { 4985 compatible = "operating-points-v2"; 4986 4987 rpmhpd_opp_ret: opp1 { 4988 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4989 }; 4990 4991 rpmhpd_opp_low_svs: opp2 { 4992 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4993 }; 4994 4995 rpmhpd_opp_svs: opp3 { 4996 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4997 }; 4998 4999 rpmhpd_opp_svs_l1: opp4 { 5000 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5001 }; 5002 5003 rpmhpd_opp_svs_l2: opp5 { 5004 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5005 }; 5006 5007 rpmhpd_opp_nom: opp6 { 5008 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5009 }; 5010 5011 rpmhpd_opp_nom_l1: opp7 { 5012 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5013 }; 5014 5015 rpmhpd_opp_turbo: opp8 { 5016 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5017 }; 5018 5019 rpmhpd_opp_turbo_l1: opp9 { 5020 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5021 }; 5022 }; 5023 }; 5024 5025 rpmhcc: clock-controller { 5026 compatible = "qcom,sc7280-rpmh-clk"; 5027 clocks = <&xo_board>; 5028 clock-names = "xo"; 5029 #clock-cells = <1>; 5030 }; 5031 }; 5032 5033 epss_l3: interconnect@18590000 { 5034 compatible = "qcom,sc7280-epss-l3"; 5035 reg = <0 0x18590000 0 0x1000>; 5036 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5037 clock-names = "xo", "alternate"; 5038 #interconnect-cells = <1>; 5039 }; 5040 5041 cpufreq_hw: cpufreq@18591000 { 5042 compatible = "qcom,cpufreq-epss"; 5043 reg = <0 0x18591000 0 0x1000>, 5044 <0 0x18592000 0 0x1000>, 5045 <0 0x18593000 0 0x1000>; 5046 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5047 clock-names = "xo", "alternate"; 5048 #freq-domain-cells = <1>; 5049 }; 5050 }; 5051 5052 thermal_zones: thermal-zones { 5053 cpu0-thermal { 5054 polling-delay-passive = <250>; 5055 polling-delay = <0>; 5056 5057 thermal-sensors = <&tsens0 1>; 5058 5059 trips { 5060 cpu0_alert0: trip-point0 { 5061 temperature = <90000>; 5062 hysteresis = <2000>; 5063 type = "passive"; 5064 }; 5065 5066 cpu0_alert1: trip-point1 { 5067 temperature = <95000>; 5068 hysteresis = <2000>; 5069 type = "passive"; 5070 }; 5071 5072 cpu0_crit: cpu-crit { 5073 temperature = <110000>; 5074 hysteresis = <0>; 5075 type = "critical"; 5076 }; 5077 }; 5078 5079 cooling-maps { 5080 map0 { 5081 trip = <&cpu0_alert0>; 5082 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5083 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5084 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5085 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5086 }; 5087 map1 { 5088 trip = <&cpu0_alert1>; 5089 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5090 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5091 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5092 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5093 }; 5094 }; 5095 }; 5096 5097 cpu1-thermal { 5098 polling-delay-passive = <250>; 5099 polling-delay = <0>; 5100 5101 thermal-sensors = <&tsens0 2>; 5102 5103 trips { 5104 cpu1_alert0: trip-point0 { 5105 temperature = <90000>; 5106 hysteresis = <2000>; 5107 type = "passive"; 5108 }; 5109 5110 cpu1_alert1: trip-point1 { 5111 temperature = <95000>; 5112 hysteresis = <2000>; 5113 type = "passive"; 5114 }; 5115 5116 cpu1_crit: cpu-crit { 5117 temperature = <110000>; 5118 hysteresis = <0>; 5119 type = "critical"; 5120 }; 5121 }; 5122 5123 cooling-maps { 5124 map0 { 5125 trip = <&cpu1_alert0>; 5126 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5127 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5128 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5129 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5130 }; 5131 map1 { 5132 trip = <&cpu1_alert1>; 5133 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5134 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5135 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5136 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5137 }; 5138 }; 5139 }; 5140 5141 cpu2-thermal { 5142 polling-delay-passive = <250>; 5143 polling-delay = <0>; 5144 5145 thermal-sensors = <&tsens0 3>; 5146 5147 trips { 5148 cpu2_alert0: trip-point0 { 5149 temperature = <90000>; 5150 hysteresis = <2000>; 5151 type = "passive"; 5152 }; 5153 5154 cpu2_alert1: trip-point1 { 5155 temperature = <95000>; 5156 hysteresis = <2000>; 5157 type = "passive"; 5158 }; 5159 5160 cpu2_crit: cpu-crit { 5161 temperature = <110000>; 5162 hysteresis = <0>; 5163 type = "critical"; 5164 }; 5165 }; 5166 5167 cooling-maps { 5168 map0 { 5169 trip = <&cpu2_alert0>; 5170 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5171 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5172 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5173 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5174 }; 5175 map1 { 5176 trip = <&cpu2_alert1>; 5177 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5178 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5179 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5180 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5181 }; 5182 }; 5183 }; 5184 5185 cpu3-thermal { 5186 polling-delay-passive = <250>; 5187 polling-delay = <0>; 5188 5189 thermal-sensors = <&tsens0 4>; 5190 5191 trips { 5192 cpu3_alert0: trip-point0 { 5193 temperature = <90000>; 5194 hysteresis = <2000>; 5195 type = "passive"; 5196 }; 5197 5198 cpu3_alert1: trip-point1 { 5199 temperature = <95000>; 5200 hysteresis = <2000>; 5201 type = "passive"; 5202 }; 5203 5204 cpu3_crit: cpu-crit { 5205 temperature = <110000>; 5206 hysteresis = <0>; 5207 type = "critical"; 5208 }; 5209 }; 5210 5211 cooling-maps { 5212 map0 { 5213 trip = <&cpu3_alert0>; 5214 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5215 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5216 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5217 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5218 }; 5219 map1 { 5220 trip = <&cpu3_alert1>; 5221 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5222 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5223 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5224 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5225 }; 5226 }; 5227 }; 5228 5229 cpu4-thermal { 5230 polling-delay-passive = <250>; 5231 polling-delay = <0>; 5232 5233 thermal-sensors = <&tsens0 7>; 5234 5235 trips { 5236 cpu4_alert0: trip-point0 { 5237 temperature = <90000>; 5238 hysteresis = <2000>; 5239 type = "passive"; 5240 }; 5241 5242 cpu4_alert1: trip-point1 { 5243 temperature = <95000>; 5244 hysteresis = <2000>; 5245 type = "passive"; 5246 }; 5247 5248 cpu4_crit: cpu-crit { 5249 temperature = <110000>; 5250 hysteresis = <0>; 5251 type = "critical"; 5252 }; 5253 }; 5254 5255 cooling-maps { 5256 map0 { 5257 trip = <&cpu4_alert0>; 5258 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5259 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5260 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5261 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5262 }; 5263 map1 { 5264 trip = <&cpu4_alert1>; 5265 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5266 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5267 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5268 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5269 }; 5270 }; 5271 }; 5272 5273 cpu5-thermal { 5274 polling-delay-passive = <250>; 5275 polling-delay = <0>; 5276 5277 thermal-sensors = <&tsens0 8>; 5278 5279 trips { 5280 cpu5_alert0: trip-point0 { 5281 temperature = <90000>; 5282 hysteresis = <2000>; 5283 type = "passive"; 5284 }; 5285 5286 cpu5_alert1: trip-point1 { 5287 temperature = <95000>; 5288 hysteresis = <2000>; 5289 type = "passive"; 5290 }; 5291 5292 cpu5_crit: cpu-crit { 5293 temperature = <110000>; 5294 hysteresis = <0>; 5295 type = "critical"; 5296 }; 5297 }; 5298 5299 cooling-maps { 5300 map0 { 5301 trip = <&cpu5_alert0>; 5302 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5303 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5304 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5305 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5306 }; 5307 map1 { 5308 trip = <&cpu5_alert1>; 5309 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5310 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5311 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5312 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5313 }; 5314 }; 5315 }; 5316 5317 cpu6-thermal { 5318 polling-delay-passive = <250>; 5319 polling-delay = <0>; 5320 5321 thermal-sensors = <&tsens0 9>; 5322 5323 trips { 5324 cpu6_alert0: trip-point0 { 5325 temperature = <90000>; 5326 hysteresis = <2000>; 5327 type = "passive"; 5328 }; 5329 5330 cpu6_alert1: trip-point1 { 5331 temperature = <95000>; 5332 hysteresis = <2000>; 5333 type = "passive"; 5334 }; 5335 5336 cpu6_crit: cpu-crit { 5337 temperature = <110000>; 5338 hysteresis = <0>; 5339 type = "critical"; 5340 }; 5341 }; 5342 5343 cooling-maps { 5344 map0 { 5345 trip = <&cpu6_alert0>; 5346 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5347 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5348 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5349 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5350 }; 5351 map1 { 5352 trip = <&cpu6_alert1>; 5353 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5354 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5355 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5356 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5357 }; 5358 }; 5359 }; 5360 5361 cpu7-thermal { 5362 polling-delay-passive = <250>; 5363 polling-delay = <0>; 5364 5365 thermal-sensors = <&tsens0 10>; 5366 5367 trips { 5368 cpu7_alert0: trip-point0 { 5369 temperature = <90000>; 5370 hysteresis = <2000>; 5371 type = "passive"; 5372 }; 5373 5374 cpu7_alert1: trip-point1 { 5375 temperature = <95000>; 5376 hysteresis = <2000>; 5377 type = "passive"; 5378 }; 5379 5380 cpu7_crit: cpu-crit { 5381 temperature = <110000>; 5382 hysteresis = <0>; 5383 type = "critical"; 5384 }; 5385 }; 5386 5387 cooling-maps { 5388 map0 { 5389 trip = <&cpu7_alert0>; 5390 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5391 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5392 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5393 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5394 }; 5395 map1 { 5396 trip = <&cpu7_alert1>; 5397 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5398 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5399 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5400 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5401 }; 5402 }; 5403 }; 5404 5405 cpu8-thermal { 5406 polling-delay-passive = <250>; 5407 polling-delay = <0>; 5408 5409 thermal-sensors = <&tsens0 11>; 5410 5411 trips { 5412 cpu8_alert0: trip-point0 { 5413 temperature = <90000>; 5414 hysteresis = <2000>; 5415 type = "passive"; 5416 }; 5417 5418 cpu8_alert1: trip-point1 { 5419 temperature = <95000>; 5420 hysteresis = <2000>; 5421 type = "passive"; 5422 }; 5423 5424 cpu8_crit: cpu-crit { 5425 temperature = <110000>; 5426 hysteresis = <0>; 5427 type = "critical"; 5428 }; 5429 }; 5430 5431 cooling-maps { 5432 map0 { 5433 trip = <&cpu8_alert0>; 5434 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5435 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5436 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5437 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5438 }; 5439 map1 { 5440 trip = <&cpu8_alert1>; 5441 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5442 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5443 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5444 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5445 }; 5446 }; 5447 }; 5448 5449 cpu9-thermal { 5450 polling-delay-passive = <250>; 5451 polling-delay = <0>; 5452 5453 thermal-sensors = <&tsens0 12>; 5454 5455 trips { 5456 cpu9_alert0: trip-point0 { 5457 temperature = <90000>; 5458 hysteresis = <2000>; 5459 type = "passive"; 5460 }; 5461 5462 cpu9_alert1: trip-point1 { 5463 temperature = <95000>; 5464 hysteresis = <2000>; 5465 type = "passive"; 5466 }; 5467 5468 cpu9_crit: cpu-crit { 5469 temperature = <110000>; 5470 hysteresis = <0>; 5471 type = "critical"; 5472 }; 5473 }; 5474 5475 cooling-maps { 5476 map0 { 5477 trip = <&cpu9_alert0>; 5478 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5479 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5480 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5481 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5482 }; 5483 map1 { 5484 trip = <&cpu9_alert1>; 5485 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5486 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5487 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5488 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5489 }; 5490 }; 5491 }; 5492 5493 cpu10-thermal { 5494 polling-delay-passive = <250>; 5495 polling-delay = <0>; 5496 5497 thermal-sensors = <&tsens0 13>; 5498 5499 trips { 5500 cpu10_alert0: trip-point0 { 5501 temperature = <90000>; 5502 hysteresis = <2000>; 5503 type = "passive"; 5504 }; 5505 5506 cpu10_alert1: trip-point1 { 5507 temperature = <95000>; 5508 hysteresis = <2000>; 5509 type = "passive"; 5510 }; 5511 5512 cpu10_crit: cpu-crit { 5513 temperature = <110000>; 5514 hysteresis = <0>; 5515 type = "critical"; 5516 }; 5517 }; 5518 5519 cooling-maps { 5520 map0 { 5521 trip = <&cpu10_alert0>; 5522 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5523 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5524 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5525 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5526 }; 5527 map1 { 5528 trip = <&cpu10_alert1>; 5529 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5530 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5531 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5532 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5533 }; 5534 }; 5535 }; 5536 5537 cpu11-thermal { 5538 polling-delay-passive = <250>; 5539 polling-delay = <0>; 5540 5541 thermal-sensors = <&tsens0 14>; 5542 5543 trips { 5544 cpu11_alert0: trip-point0 { 5545 temperature = <90000>; 5546 hysteresis = <2000>; 5547 type = "passive"; 5548 }; 5549 5550 cpu11_alert1: trip-point1 { 5551 temperature = <95000>; 5552 hysteresis = <2000>; 5553 type = "passive"; 5554 }; 5555 5556 cpu11_crit: cpu-crit { 5557 temperature = <110000>; 5558 hysteresis = <0>; 5559 type = "critical"; 5560 }; 5561 }; 5562 5563 cooling-maps { 5564 map0 { 5565 trip = <&cpu11_alert0>; 5566 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5567 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5568 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5569 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5570 }; 5571 map1 { 5572 trip = <&cpu11_alert1>; 5573 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5574 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5575 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5576 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5577 }; 5578 }; 5579 }; 5580 5581 aoss0-thermal { 5582 polling-delay-passive = <0>; 5583 polling-delay = <0>; 5584 5585 thermal-sensors = <&tsens0 0>; 5586 5587 trips { 5588 aoss0_alert0: trip-point0 { 5589 temperature = <90000>; 5590 hysteresis = <2000>; 5591 type = "hot"; 5592 }; 5593 5594 aoss0_crit: aoss0-crit { 5595 temperature = <110000>; 5596 hysteresis = <0>; 5597 type = "critical"; 5598 }; 5599 }; 5600 }; 5601 5602 aoss1-thermal { 5603 polling-delay-passive = <0>; 5604 polling-delay = <0>; 5605 5606 thermal-sensors = <&tsens1 0>; 5607 5608 trips { 5609 aoss1_alert0: trip-point0 { 5610 temperature = <90000>; 5611 hysteresis = <2000>; 5612 type = "hot"; 5613 }; 5614 5615 aoss1_crit: aoss1-crit { 5616 temperature = <110000>; 5617 hysteresis = <0>; 5618 type = "critical"; 5619 }; 5620 }; 5621 }; 5622 5623 cpuss0-thermal { 5624 polling-delay-passive = <0>; 5625 polling-delay = <0>; 5626 5627 thermal-sensors = <&tsens0 5>; 5628 5629 trips { 5630 cpuss0_alert0: trip-point0 { 5631 temperature = <90000>; 5632 hysteresis = <2000>; 5633 type = "hot"; 5634 }; 5635 cpuss0_crit: cluster0-crit { 5636 temperature = <110000>; 5637 hysteresis = <0>; 5638 type = "critical"; 5639 }; 5640 }; 5641 }; 5642 5643 cpuss1-thermal { 5644 polling-delay-passive = <0>; 5645 polling-delay = <0>; 5646 5647 thermal-sensors = <&tsens0 6>; 5648 5649 trips { 5650 cpuss1_alert0: trip-point0 { 5651 temperature = <90000>; 5652 hysteresis = <2000>; 5653 type = "hot"; 5654 }; 5655 cpuss1_crit: cluster0-crit { 5656 temperature = <110000>; 5657 hysteresis = <0>; 5658 type = "critical"; 5659 }; 5660 }; 5661 }; 5662 5663 gpuss0-thermal { 5664 polling-delay-passive = <100>; 5665 polling-delay = <0>; 5666 5667 thermal-sensors = <&tsens1 1>; 5668 5669 trips { 5670 gpuss0_alert0: trip-point0 { 5671 temperature = <95000>; 5672 hysteresis = <2000>; 5673 type = "passive"; 5674 }; 5675 5676 gpuss0_crit: gpuss0-crit { 5677 temperature = <110000>; 5678 hysteresis = <0>; 5679 type = "critical"; 5680 }; 5681 }; 5682 5683 cooling-maps { 5684 map0 { 5685 trip = <&gpuss0_alert0>; 5686 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5687 }; 5688 }; 5689 }; 5690 5691 gpuss1-thermal { 5692 polling-delay-passive = <100>; 5693 polling-delay = <0>; 5694 5695 thermal-sensors = <&tsens1 2>; 5696 5697 trips { 5698 gpuss1_alert0: trip-point0 { 5699 temperature = <95000>; 5700 hysteresis = <2000>; 5701 type = "passive"; 5702 }; 5703 5704 gpuss1_crit: gpuss1-crit { 5705 temperature = <110000>; 5706 hysteresis = <0>; 5707 type = "critical"; 5708 }; 5709 }; 5710 5711 cooling-maps { 5712 map0 { 5713 trip = <&gpuss1_alert0>; 5714 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5715 }; 5716 }; 5717 }; 5718 5719 nspss0-thermal { 5720 polling-delay-passive = <0>; 5721 polling-delay = <0>; 5722 5723 thermal-sensors = <&tsens1 3>; 5724 5725 trips { 5726 nspss0_alert0: trip-point0 { 5727 temperature = <90000>; 5728 hysteresis = <2000>; 5729 type = "hot"; 5730 }; 5731 5732 nspss0_crit: nspss0-crit { 5733 temperature = <110000>; 5734 hysteresis = <0>; 5735 type = "critical"; 5736 }; 5737 }; 5738 }; 5739 5740 nspss1-thermal { 5741 polling-delay-passive = <0>; 5742 polling-delay = <0>; 5743 5744 thermal-sensors = <&tsens1 4>; 5745 5746 trips { 5747 nspss1_alert0: trip-point0 { 5748 temperature = <90000>; 5749 hysteresis = <2000>; 5750 type = "hot"; 5751 }; 5752 5753 nspss1_crit: nspss1-crit { 5754 temperature = <110000>; 5755 hysteresis = <0>; 5756 type = "critical"; 5757 }; 5758 }; 5759 }; 5760 5761 video-thermal { 5762 polling-delay-passive = <0>; 5763 polling-delay = <0>; 5764 5765 thermal-sensors = <&tsens1 5>; 5766 5767 trips { 5768 video_alert0: trip-point0 { 5769 temperature = <90000>; 5770 hysteresis = <2000>; 5771 type = "hot"; 5772 }; 5773 5774 video_crit: video-crit { 5775 temperature = <110000>; 5776 hysteresis = <0>; 5777 type = "critical"; 5778 }; 5779 }; 5780 }; 5781 5782 ddr-thermal { 5783 polling-delay-passive = <0>; 5784 polling-delay = <0>; 5785 5786 thermal-sensors = <&tsens1 6>; 5787 5788 trips { 5789 ddr_alert0: trip-point0 { 5790 temperature = <90000>; 5791 hysteresis = <2000>; 5792 type = "hot"; 5793 }; 5794 5795 ddr_crit: ddr-crit { 5796 temperature = <110000>; 5797 hysteresis = <0>; 5798 type = "critical"; 5799 }; 5800 }; 5801 }; 5802 5803 mdmss0-thermal { 5804 polling-delay-passive = <0>; 5805 polling-delay = <0>; 5806 5807 thermal-sensors = <&tsens1 7>; 5808 5809 trips { 5810 mdmss0_alert0: trip-point0 { 5811 temperature = <90000>; 5812 hysteresis = <2000>; 5813 type = "hot"; 5814 }; 5815 5816 mdmss0_crit: mdmss0-crit { 5817 temperature = <110000>; 5818 hysteresis = <0>; 5819 type = "critical"; 5820 }; 5821 }; 5822 }; 5823 5824 mdmss1-thermal { 5825 polling-delay-passive = <0>; 5826 polling-delay = <0>; 5827 5828 thermal-sensors = <&tsens1 8>; 5829 5830 trips { 5831 mdmss1_alert0: trip-point0 { 5832 temperature = <90000>; 5833 hysteresis = <2000>; 5834 type = "hot"; 5835 }; 5836 5837 mdmss1_crit: mdmss1-crit { 5838 temperature = <110000>; 5839 hysteresis = <0>; 5840 type = "critical"; 5841 }; 5842 }; 5843 }; 5844 5845 mdmss2-thermal { 5846 polling-delay-passive = <0>; 5847 polling-delay = <0>; 5848 5849 thermal-sensors = <&tsens1 9>; 5850 5851 trips { 5852 mdmss2_alert0: trip-point0 { 5853 temperature = <90000>; 5854 hysteresis = <2000>; 5855 type = "hot"; 5856 }; 5857 5858 mdmss2_crit: mdmss2-crit { 5859 temperature = <110000>; 5860 hysteresis = <0>; 5861 type = "critical"; 5862 }; 5863 }; 5864 }; 5865 5866 mdmss3-thermal { 5867 polling-delay-passive = <0>; 5868 polling-delay = <0>; 5869 5870 thermal-sensors = <&tsens1 10>; 5871 5872 trips { 5873 mdmss3_alert0: trip-point0 { 5874 temperature = <90000>; 5875 hysteresis = <2000>; 5876 type = "hot"; 5877 }; 5878 5879 mdmss3_crit: mdmss3-crit { 5880 temperature = <110000>; 5881 hysteresis = <0>; 5882 type = "critical"; 5883 }; 5884 }; 5885 }; 5886 5887 camera0-thermal { 5888 polling-delay-passive = <0>; 5889 polling-delay = <0>; 5890 5891 thermal-sensors = <&tsens1 11>; 5892 5893 trips { 5894 camera0_alert0: trip-point0 { 5895 temperature = <90000>; 5896 hysteresis = <2000>; 5897 type = "hot"; 5898 }; 5899 5900 camera0_crit: camera0-crit { 5901 temperature = <110000>; 5902 hysteresis = <0>; 5903 type = "critical"; 5904 }; 5905 }; 5906 }; 5907 }; 5908 5909 timer { 5910 compatible = "arm,armv8-timer"; 5911 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5912 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5913 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5914 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5915 }; 5916}; 5917