1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 L3_0: l3-cache { 188 compatible = "cache"; 189 cache-level = <3>; 190 cache-unified; 191 }; 192 }; 193 }; 194 195 CPU1: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x100>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 &LITTLE_CPU_SLEEP_1 226 &CLUSTER_SLEEP_0>; 227 next-level-cache = <&L2_200>; 228 operating-points-v2 = <&cpu0_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 #cooling-cells = <2>; 233 L2_200: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU3: cpu@300 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo"; 244 reg = <0x0 0x300>; 245 clocks = <&cpufreq_hw 0>; 246 enable-method = "psci"; 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 248 &LITTLE_CPU_SLEEP_1 249 &CLUSTER_SLEEP_0>; 250 next-level-cache = <&L2_300>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 254 qcom,freq-domain = <&cpufreq_hw 0>; 255 #cooling-cells = <2>; 256 L2_300: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-unified; 260 next-level-cache = <&L3_0>; 261 }; 262 }; 263 264 CPU4: cpu@400 { 265 device_type = "cpu"; 266 compatible = "qcom,kryo"; 267 reg = <0x0 0x400>; 268 clocks = <&cpufreq_hw 1>; 269 enable-method = "psci"; 270 cpu-idle-states = <&BIG_CPU_SLEEP_0 271 &BIG_CPU_SLEEP_1 272 &CLUSTER_SLEEP_0>; 273 next-level-cache = <&L2_400>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 276 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 L2_400: l2-cache { 280 compatible = "cache"; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo"; 290 reg = <0x0 0x500>; 291 clocks = <&cpufreq_hw 1>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_500>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_500: l2-cache { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-unified; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU6: cpu@600 { 311 device_type = "cpu"; 312 compatible = "qcom,kryo"; 313 reg = <0x0 0x600>; 314 clocks = <&cpufreq_hw 1>; 315 enable-method = "psci"; 316 cpu-idle-states = <&BIG_CPU_SLEEP_0 317 &BIG_CPU_SLEEP_1 318 &CLUSTER_SLEEP_0>; 319 next-level-cache = <&L2_600>; 320 operating-points-v2 = <&cpu4_opp_table>; 321 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 322 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 323 qcom,freq-domain = <&cpufreq_hw 1>; 324 #cooling-cells = <2>; 325 L2_600: l2-cache { 326 compatible = "cache"; 327 cache-level = <2>; 328 cache-unified; 329 next-level-cache = <&L3_0>; 330 }; 331 }; 332 333 CPU7: cpu@700 { 334 device_type = "cpu"; 335 compatible = "qcom,kryo"; 336 reg = <0x0 0x700>; 337 clocks = <&cpufreq_hw 2>; 338 enable-method = "psci"; 339 cpu-idle-states = <&BIG_CPU_SLEEP_0 340 &BIG_CPU_SLEEP_1 341 &CLUSTER_SLEEP_0>; 342 next-level-cache = <&L2_700>; 343 operating-points-v2 = <&cpu7_opp_table>; 344 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 345 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 346 qcom,freq-domain = <&cpufreq_hw 2>; 347 #cooling-cells = <2>; 348 L2_700: l2-cache { 349 compatible = "cache"; 350 cache-level = <2>; 351 cache-unified; 352 next-level-cache = <&L3_0>; 353 }; 354 }; 355 356 cpu-map { 357 cluster0 { 358 core0 { 359 cpu = <&CPU0>; 360 }; 361 362 core1 { 363 cpu = <&CPU1>; 364 }; 365 366 core2 { 367 cpu = <&CPU2>; 368 }; 369 370 core3 { 371 cpu = <&CPU3>; 372 }; 373 374 core4 { 375 cpu = <&CPU4>; 376 }; 377 378 core5 { 379 cpu = <&CPU5>; 380 }; 381 382 core6 { 383 cpu = <&CPU6>; 384 }; 385 386 core7 { 387 cpu = <&CPU7>; 388 }; 389 }; 390 }; 391 392 idle-states { 393 entry-method = "psci"; 394 395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "little-power-down"; 398 arm,psci-suspend-param = <0x40000003>; 399 entry-latency-us = <549>; 400 exit-latency-us = <901>; 401 min-residency-us = <1774>; 402 local-timer-stop; 403 }; 404 405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-down"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <702>; 410 exit-latency-us = <915>; 411 min-residency-us = <4001>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-power-down"; 418 arm,psci-suspend-param = <0x40000003>; 419 entry-latency-us = <523>; 420 exit-latency-us = <1244>; 421 min-residency-us = <2207>; 422 local-timer-stop; 423 }; 424 425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 426 compatible = "arm,idle-state"; 427 idle-state-name = "big-rail-power-down"; 428 arm,psci-suspend-param = <0x40000004>; 429 entry-latency-us = <526>; 430 exit-latency-us = <1854>; 431 min-residency-us = <5555>; 432 local-timer-stop; 433 }; 434 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "cluster-power-down"; 438 arm,psci-suspend-param = <0x40003444>; 439 entry-latency-us = <3263>; 440 exit-latency-us = <6562>; 441 min-residency-us = <9926>; 442 local-timer-stop; 443 }; 444 }; 445 }; 446 447 cpu0_opp_table: opp-table-cpu0 { 448 compatible = "operating-points-v2"; 449 opp-shared; 450 451 cpu0_opp_300mhz: opp-300000000 { 452 opp-hz = /bits/ 64 <300000000>; 453 opp-peak-kBps = <800000 9600000>; 454 }; 455 456 cpu0_opp_691mhz: opp-691200000 { 457 opp-hz = /bits/ 64 <691200000>; 458 opp-peak-kBps = <800000 17817600>; 459 }; 460 461 cpu0_opp_806mhz: opp-806400000 { 462 opp-hz = /bits/ 64 <806400000>; 463 opp-peak-kBps = <800000 20889600>; 464 }; 465 466 cpu0_opp_941mhz: opp-940800000 { 467 opp-hz = /bits/ 64 <940800000>; 468 opp-peak-kBps = <1804000 24576000>; 469 }; 470 471 cpu0_opp_1152mhz: opp-1152000000 { 472 opp-hz = /bits/ 64 <1152000000>; 473 opp-peak-kBps = <2188000 27033600>; 474 }; 475 476 cpu0_opp_1325mhz: opp-1324800000 { 477 opp-hz = /bits/ 64 <1324800000>; 478 opp-peak-kBps = <2188000 33792000>; 479 }; 480 481 cpu0_opp_1517mhz: opp-1516800000 { 482 opp-hz = /bits/ 64 <1516800000>; 483 opp-peak-kBps = <3072000 38092800>; 484 }; 485 486 cpu0_opp_1651mhz: opp-1651200000 { 487 opp-hz = /bits/ 64 <1651200000>; 488 opp-peak-kBps = <3072000 41779200>; 489 }; 490 491 cpu0_opp_1805mhz: opp-1804800000 { 492 opp-hz = /bits/ 64 <1804800000>; 493 opp-peak-kBps = <4068000 48537600>; 494 }; 495 496 cpu0_opp_1958mhz: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <4068000 48537600>; 499 }; 500 501 cpu0_opp_2016mhz: opp-2016000000 { 502 opp-hz = /bits/ 64 <2016000000>; 503 opp-peak-kBps = <6220000 48537600>; 504 }; 505 }; 506 507 cpu4_opp_table: opp-table-cpu4 { 508 compatible = "operating-points-v2"; 509 opp-shared; 510 511 cpu4_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <1804000 9600000>; 514 }; 515 516 cpu4_opp_941mhz: opp-940800000 { 517 opp-hz = /bits/ 64 <940800000>; 518 opp-peak-kBps = <2188000 17817600>; 519 }; 520 521 cpu4_opp_1229mhz: opp-1228800000 { 522 opp-hz = /bits/ 64 <1228800000>; 523 opp-peak-kBps = <4068000 24576000>; 524 }; 525 526 cpu4_opp_1344mhz: opp-1344000000 { 527 opp-hz = /bits/ 64 <1344000000>; 528 opp-peak-kBps = <4068000 24576000>; 529 }; 530 531 cpu4_opp_1517mhz: opp-1516800000 { 532 opp-hz = /bits/ 64 <1516800000>; 533 opp-peak-kBps = <4068000 24576000>; 534 }; 535 536 cpu4_opp_1651mhz: opp-1651200000 { 537 opp-hz = /bits/ 64 <1651200000>; 538 opp-peak-kBps = <6220000 38092800>; 539 }; 540 541 cpu4_opp_1901mhz: opp-1900800000 { 542 opp-hz = /bits/ 64 <1900800000>; 543 opp-peak-kBps = <6220000 44851200>; 544 }; 545 546 cpu4_opp_2054mhz: opp-2054400000 { 547 opp-hz = /bits/ 64 <2054400000>; 548 opp-peak-kBps = <6220000 44851200>; 549 }; 550 551 cpu4_opp_2112mhz: opp-2112000000 { 552 opp-hz = /bits/ 64 <2112000000>; 553 opp-peak-kBps = <6220000 44851200>; 554 }; 555 556 cpu4_opp_2131mhz: opp-2131200000 { 557 opp-hz = /bits/ 64 <2131200000>; 558 opp-peak-kBps = <6220000 44851200>; 559 }; 560 561 cpu4_opp_2208mhz: opp-2208000000 { 562 opp-hz = /bits/ 64 <2208000000>; 563 opp-peak-kBps = <6220000 44851200>; 564 }; 565 566 cpu4_opp_2400mhz: opp-2400000000 { 567 opp-hz = /bits/ 64 <2400000000>; 568 opp-peak-kBps = <8532000 48537600>; 569 }; 570 571 cpu4_opp_2611mhz: opp-2611200000 { 572 opp-hz = /bits/ 64 <2611200000>; 573 opp-peak-kBps = <8532000 48537600>; 574 }; 575 }; 576 577 cpu7_opp_table: opp-table-cpu7 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 cpu7_opp_806mhz: opp-806400000 { 582 opp-hz = /bits/ 64 <806400000>; 583 opp-peak-kBps = <1804000 9600000>; 584 }; 585 586 cpu7_opp_1056mhz: opp-1056000000 { 587 opp-hz = /bits/ 64 <1056000000>; 588 opp-peak-kBps = <2188000 17817600>; 589 }; 590 591 cpu7_opp_1325mhz: opp-1324800000 { 592 opp-hz = /bits/ 64 <1324800000>; 593 opp-peak-kBps = <4068000 24576000>; 594 }; 595 596 cpu7_opp_1517mhz: opp-1516800000 { 597 opp-hz = /bits/ 64 <1516800000>; 598 opp-peak-kBps = <4068000 24576000>; 599 }; 600 601 cpu7_opp_1766mhz: opp-1766400000 { 602 opp-hz = /bits/ 64 <1766400000>; 603 opp-peak-kBps = <6220000 38092800>; 604 }; 605 606 cpu7_opp_1862mhz: opp-1862400000 { 607 opp-hz = /bits/ 64 <1862400000>; 608 opp-peak-kBps = <6220000 38092800>; 609 }; 610 611 cpu7_opp_2035mhz: opp-2035200000 { 612 opp-hz = /bits/ 64 <2035200000>; 613 opp-peak-kBps = <6220000 38092800>; 614 }; 615 616 cpu7_opp_2112mhz: opp-2112000000 { 617 opp-hz = /bits/ 64 <2112000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu7_opp_2208mhz: opp-2208000000 { 622 opp-hz = /bits/ 64 <2208000000>; 623 opp-peak-kBps = <6220000 44851200>; 624 }; 625 626 cpu7_opp_2381mhz: opp-2380800000 { 627 opp-hz = /bits/ 64 <2380800000>; 628 opp-peak-kBps = <6832000 44851200>; 629 }; 630 631 cpu7_opp_2400mhz: opp-2400000000 { 632 opp-hz = /bits/ 64 <2400000000>; 633 opp-peak-kBps = <8532000 48537600>; 634 }; 635 636 cpu7_opp_2515mhz: opp-2515200000 { 637 opp-hz = /bits/ 64 <2515200000>; 638 opp-peak-kBps = <8532000 48537600>; 639 }; 640 641 cpu7_opp_2707mhz: opp-2707200000 { 642 opp-hz = /bits/ 64 <2707200000>; 643 opp-peak-kBps = <8532000 48537600>; 644 }; 645 646 cpu7_opp_3014mhz: opp-3014400000 { 647 opp-hz = /bits/ 64 <3014400000>; 648 opp-peak-kBps = <8532000 48537600>; 649 }; 650 }; 651 652 memory@80000000 { 653 device_type = "memory"; 654 /* We expect the bootloader to fill in the size */ 655 reg = <0 0x80000000 0 0>; 656 }; 657 658 firmware { 659 scm: scm { 660 compatible = "qcom,scm-sc7280", "qcom,scm"; 661 }; 662 }; 663 664 clk_virt: interconnect { 665 compatible = "qcom,sc7280-clk-virt"; 666 #interconnect-cells = <2>; 667 qcom,bcm-voters = <&apps_bcm_voter>; 668 }; 669 670 smem { 671 compatible = "qcom,smem"; 672 memory-region = <&smem_mem>; 673 hwlocks = <&tcsr_mutex 3>; 674 }; 675 676 smp2p-adsp { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 680 IPCC_MPROC_SIGNAL_SMP2P 681 IRQ_TYPE_EDGE_RISING>; 682 mboxes = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <2>; 687 688 adsp_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 adsp_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-cdsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <94>, <432>; 703 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 mboxes = <&ipcc IPCC_CLIENT_CDSP 707 IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-mpss { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <435>, <428>; 727 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 mboxes = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <1>; 735 736 modem_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 modem_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 ipa_smp2p_out: ipa-ap-to-modem { 748 qcom,entry-name = "ipa"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 ipa_smp2p_in: ipa-modem-to-ap { 753 qcom,entry-name = "ipa"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-wpss { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <617>, <616>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_WPSS 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <13>; 770 771 wpss_smp2p_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 wpss_smp2p_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 782 wlan_smp2p_out: wlan-ap-to-wpss { 783 qcom,entry-name = "wlan"; 784 #qcom,smem-state-cells = <1>; 785 }; 786 787 wlan_smp2p_in: wlan-wpss-to-ap { 788 qcom,entry-name = "wlan"; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 }; 792 }; 793 794 pmu { 795 compatible = "arm,armv8-pmuv3"; 796 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 797 }; 798 799 psci { 800 compatible = "arm,psci-1.0"; 801 method = "smc"; 802 }; 803 804 qspi_opp_table: opp-table-qspi { 805 compatible = "operating-points-v2"; 806 807 opp-75000000 { 808 opp-hz = /bits/ 64 <75000000>; 809 required-opps = <&rpmhpd_opp_low_svs>; 810 }; 811 812 opp-150000000 { 813 opp-hz = /bits/ 64 <150000000>; 814 required-opps = <&rpmhpd_opp_svs>; 815 }; 816 817 opp-200000000 { 818 opp-hz = /bits/ 64 <200000000>; 819 required-opps = <&rpmhpd_opp_svs_l1>; 820 }; 821 822 opp-300000000 { 823 opp-hz = /bits/ 64 <300000000>; 824 required-opps = <&rpmhpd_opp_nom>; 825 }; 826 }; 827 828 qup_opp_table: opp-table-qup { 829 compatible = "operating-points-v2"; 830 831 opp-75000000 { 832 opp-hz = /bits/ 64 <75000000>; 833 required-opps = <&rpmhpd_opp_low_svs>; 834 }; 835 836 opp-100000000 { 837 opp-hz = /bits/ 64 <100000000>; 838 required-opps = <&rpmhpd_opp_svs>; 839 }; 840 841 opp-128000000 { 842 opp-hz = /bits/ 64 <128000000>; 843 required-opps = <&rpmhpd_opp_nom>; 844 }; 845 }; 846 847 soc: soc@0 { 848 #address-cells = <2>; 849 #size-cells = <2>; 850 ranges = <0 0 0 0 0x10 0>; 851 dma-ranges = <0 0 0 0 0x10 0>; 852 compatible = "simple-bus"; 853 854 gcc: clock-controller@100000 { 855 compatible = "qcom,gcc-sc7280"; 856 reg = <0 0x00100000 0 0x1f0000>; 857 clocks = <&rpmhcc RPMH_CXO_CLK>, 858 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 859 <0>, <&pcie1_lane>, 860 <0>, <0>, <0>, 861 <&usb_1_ssphy>; 862 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 863 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 864 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 865 "ufs_phy_tx_symbol_0_clk", 866 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 #power-domain-cells = <1>; 870 power-domains = <&rpmhpd SC7280_CX>; 871 }; 872 873 ipcc: mailbox@408000 { 874 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 875 reg = <0 0x00408000 0 0x1000>; 876 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-controller; 878 #interrupt-cells = <3>; 879 #mbox-cells = <2>; 880 }; 881 882 qfprom: efuse@784000 { 883 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 884 reg = <0 0x00784000 0 0xa20>, 885 <0 0x00780000 0 0xa20>, 886 <0 0x00782000 0 0x120>, 887 <0 0x00786000 0 0x1fff>; 888 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 889 clock-names = "core"; 890 power-domains = <&rpmhpd SC7280_MX>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 894 gpu_speed_bin: gpu_speed_bin@1e9 { 895 reg = <0x1e9 0x2>; 896 bits = <5 8>; 897 }; 898 }; 899 900 sdhc_1: mmc@7c4000 { 901 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 902 pinctrl-names = "default", "sleep"; 903 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 904 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 905 status = "disabled"; 906 907 reg = <0 0x007c4000 0 0x1000>, 908 <0 0x007c5000 0 0x1000>; 909 reg-names = "hc", "cqhci"; 910 911 iommus = <&apps_smmu 0xc0 0x0>; 912 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "hc_irq", "pwr_irq"; 915 916 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 917 <&gcc GCC_SDCC1_APPS_CLK>, 918 <&rpmhcc RPMH_CXO_CLK>; 919 clock-names = "iface", "core", "xo"; 920 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 922 interconnect-names = "sdhc-ddr","cpu-sdhc"; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&sdhc1_opp_table>; 925 926 bus-width = <8>; 927 supports-cqe; 928 929 qcom,dll-config = <0x0007642c>; 930 qcom,ddr-config = <0x80040868>; 931 932 mmc-ddr-1_8v; 933 mmc-hs200-1_8v; 934 mmc-hs400-1_8v; 935 mmc-hs400-enhanced-strobe; 936 937 resets = <&gcc GCC_SDCC1_BCR>; 938 939 sdhc1_opp_table: opp-table { 940 compatible = "operating-points-v2"; 941 942 opp-100000000 { 943 opp-hz = /bits/ 64 <100000000>; 944 required-opps = <&rpmhpd_opp_low_svs>; 945 opp-peak-kBps = <1800000 400000>; 946 opp-avg-kBps = <100000 0>; 947 }; 948 949 opp-384000000 { 950 opp-hz = /bits/ 64 <384000000>; 951 required-opps = <&rpmhpd_opp_nom>; 952 opp-peak-kBps = <5400000 1600000>; 953 opp-avg-kBps = <390000 0>; 954 }; 955 }; 956 }; 957 958 gpi_dma0: dma-controller@900000 { 959 #dma-cells = <3>; 960 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 961 reg = <0 0x00900000 0 0x60000>; 962 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 974 dma-channels = <12>; 975 dma-channel-mask = <0x7f>; 976 iommus = <&apps_smmu 0x0136 0x0>; 977 status = "disabled"; 978 }; 979 980 qupv3_id_0: geniqup@9c0000 { 981 compatible = "qcom,geni-se-qup"; 982 reg = <0 0x009c0000 0 0x2000>; 983 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 984 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 985 clock-names = "m-ahb", "s-ahb"; 986 #address-cells = <2>; 987 #size-cells = <2>; 988 ranges; 989 iommus = <&apps_smmu 0x123 0x0>; 990 status = "disabled"; 991 992 i2c0: i2c@980000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0 0x00980000 0 0x4000>; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 996 clock-names = "se"; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_i2c0_data_clk>; 999 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1003 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1004 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1005 interconnect-names = "qup-core", "qup-config", 1006 "qup-memory"; 1007 power-domains = <&rpmhpd SC7280_CX>; 1008 required-opps = <&rpmhpd_opp_low_svs>; 1009 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1010 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1011 dma-names = "tx", "rx"; 1012 status = "disabled"; 1013 }; 1014 1015 spi0: spi@980000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00980000 0 0x4000>; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1019 clock-names = "se"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1022 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 power-domains = <&rpmhpd SC7280_CX>; 1026 operating-points-v2 = <&qup_opp_table>; 1027 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1028 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1029 interconnect-names = "qup-core", "qup-config"; 1030 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1031 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1032 dma-names = "tx", "rx"; 1033 status = "disabled"; 1034 }; 1035 1036 uart0: serial@980000 { 1037 compatible = "qcom,geni-uart"; 1038 reg = <0 0x00980000 0 0x4000>; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1040 clock-names = "se"; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1043 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SC7280_CX>; 1045 operating-points-v2 = <&qup_opp_table>; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1048 interconnect-names = "qup-core", "qup-config"; 1049 status = "disabled"; 1050 }; 1051 1052 i2c1: i2c@984000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x00984000 0 0x4000>; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1056 clock-names = "se"; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_i2c1_data_clk>; 1059 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1063 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1064 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1065 interconnect-names = "qup-core", "qup-config", 1066 "qup-memory"; 1067 power-domains = <&rpmhpd SC7280_CX>; 1068 required-opps = <&rpmhpd_opp_low_svs>; 1069 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1070 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1071 dma-names = "tx", "rx"; 1072 status = "disabled"; 1073 }; 1074 1075 spi1: spi@984000 { 1076 compatible = "qcom,geni-spi"; 1077 reg = <0 0x00984000 0 0x4000>; 1078 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1079 clock-names = "se"; 1080 pinctrl-names = "default"; 1081 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1082 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 power-domains = <&rpmhpd SC7280_CX>; 1086 operating-points-v2 = <&qup_opp_table>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1088 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1089 interconnect-names = "qup-core", "qup-config"; 1090 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1091 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1092 dma-names = "tx", "rx"; 1093 status = "disabled"; 1094 }; 1095 1096 uart1: serial@984000 { 1097 compatible = "qcom,geni-uart"; 1098 reg = <0 0x00984000 0 0x4000>; 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1100 clock-names = "se"; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1103 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd SC7280_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1107 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1108 interconnect-names = "qup-core", "qup-config"; 1109 status = "disabled"; 1110 }; 1111 1112 i2c2: i2c@988000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00988000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1116 clock-names = "se"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c2_data_clk>; 1119 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1124 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1125 interconnect-names = "qup-core", "qup-config", 1126 "qup-memory"; 1127 power-domains = <&rpmhpd SC7280_CX>; 1128 required-opps = <&rpmhpd_opp_low_svs>; 1129 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1130 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1131 dma-names = "tx", "rx"; 1132 status = "disabled"; 1133 }; 1134 1135 spi2: spi@988000 { 1136 compatible = "qcom,geni-spi"; 1137 reg = <0 0x00988000 0 0x4000>; 1138 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1139 clock-names = "se"; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1142 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 power-domains = <&rpmhpd SC7280_CX>; 1146 operating-points-v2 = <&qup_opp_table>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1148 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1149 interconnect-names = "qup-core", "qup-config"; 1150 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1151 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1152 dma-names = "tx", "rx"; 1153 status = "disabled"; 1154 }; 1155 1156 uart2: serial@988000 { 1157 compatible = "qcom,geni-uart"; 1158 reg = <0 0x00988000 0 0x4000>; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1160 clock-names = "se"; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1163 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1164 power-domains = <&rpmhpd SC7280_CX>; 1165 operating-points-v2 = <&qup_opp_table>; 1166 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1167 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1168 interconnect-names = "qup-core", "qup-config"; 1169 status = "disabled"; 1170 }; 1171 1172 i2c3: i2c@98c000 { 1173 compatible = "qcom,geni-i2c"; 1174 reg = <0 0x0098c000 0 0x4000>; 1175 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1176 clock-names = "se"; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&qup_i2c3_data_clk>; 1179 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1184 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1185 interconnect-names = "qup-core", "qup-config", 1186 "qup-memory"; 1187 power-domains = <&rpmhpd SC7280_CX>; 1188 required-opps = <&rpmhpd_opp_low_svs>; 1189 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1190 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1191 dma-names = "tx", "rx"; 1192 status = "disabled"; 1193 }; 1194 1195 spi3: spi@98c000 { 1196 compatible = "qcom,geni-spi"; 1197 reg = <0 0x0098c000 0 0x4000>; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1199 clock-names = "se"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1202 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 power-domains = <&rpmhpd SC7280_CX>; 1206 operating-points-v2 = <&qup_opp_table>; 1207 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1208 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1209 interconnect-names = "qup-core", "qup-config"; 1210 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1211 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1212 dma-names = "tx", "rx"; 1213 status = "disabled"; 1214 }; 1215 1216 uart3: serial@98c000 { 1217 compatible = "qcom,geni-uart"; 1218 reg = <0 0x0098c000 0 0x4000>; 1219 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1220 clock-names = "se"; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1223 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1224 power-domains = <&rpmhpd SC7280_CX>; 1225 operating-points-v2 = <&qup_opp_table>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1228 interconnect-names = "qup-core", "qup-config"; 1229 status = "disabled"; 1230 }; 1231 1232 i2c4: i2c@990000 { 1233 compatible = "qcom,geni-i2c"; 1234 reg = <0 0x00990000 0 0x4000>; 1235 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1236 clock-names = "se"; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_i2c4_data_clk>; 1239 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1244 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", 1246 "qup-memory"; 1247 power-domains = <&rpmhpd SC7280_CX>; 1248 required-opps = <&rpmhpd_opp_low_svs>; 1249 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1250 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1251 dma-names = "tx", "rx"; 1252 status = "disabled"; 1253 }; 1254 1255 spi4: spi@990000 { 1256 compatible = "qcom,geni-spi"; 1257 reg = <0 0x00990000 0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1259 clock-names = "se"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1262 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 power-domains = <&rpmhpd SC7280_CX>; 1266 operating-points-v2 = <&qup_opp_table>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1271 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1272 dma-names = "tx", "rx"; 1273 status = "disabled"; 1274 }; 1275 1276 uart4: serial@990000 { 1277 compatible = "qcom,geni-uart"; 1278 reg = <0 0x00990000 0 0x4000>; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1280 clock-names = "se"; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1283 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1284 power-domains = <&rpmhpd SC7280_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1288 interconnect-names = "qup-core", "qup-config"; 1289 status = "disabled"; 1290 }; 1291 1292 i2c5: i2c@994000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00994000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1296 clock-names = "se"; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c5_data_clk>; 1299 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1304 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1305 interconnect-names = "qup-core", "qup-config", 1306 "qup-memory"; 1307 power-domains = <&rpmhpd SC7280_CX>; 1308 required-opps = <&rpmhpd_opp_low_svs>; 1309 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 spi5: spi@994000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0 0x00994000 0 0x4000>; 1318 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1319 clock-names = "se"; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1322 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 power-domains = <&rpmhpd SC7280_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1328 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1329 interconnect-names = "qup-core", "qup-config"; 1330 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1331 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1332 dma-names = "tx", "rx"; 1333 status = "disabled"; 1334 }; 1335 1336 uart5: serial@994000 { 1337 compatible = "qcom,geni-uart"; 1338 reg = <0 0x00994000 0 0x4000>; 1339 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1340 clock-names = "se"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1343 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd SC7280_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1348 interconnect-names = "qup-core", "qup-config"; 1349 status = "disabled"; 1350 }; 1351 1352 i2c6: i2c@998000 { 1353 compatible = "qcom,geni-i2c"; 1354 reg = <0 0x00998000 0 0x4000>; 1355 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1356 clock-names = "se"; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_i2c6_data_clk>; 1359 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", 1366 "qup-memory"; 1367 power-domains = <&rpmhpd SC7280_CX>; 1368 required-opps = <&rpmhpd_opp_low_svs>; 1369 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1370 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 spi6: spi@998000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0 0x00998000 0 0x4000>; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1379 clock-names = "se"; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1382 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 power-domains = <&rpmhpd SC7280_CX>; 1386 operating-points-v2 = <&qup_opp_table>; 1387 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1388 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1389 interconnect-names = "qup-core", "qup-config"; 1390 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1391 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1392 dma-names = "tx", "rx"; 1393 status = "disabled"; 1394 }; 1395 1396 uart6: serial@998000 { 1397 compatible = "qcom,geni-uart"; 1398 reg = <0 0x00998000 0 0x4000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1400 clock-names = "se"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1403 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1404 power-domains = <&rpmhpd SC7280_CX>; 1405 operating-points-v2 = <&qup_opp_table>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1407 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1408 interconnect-names = "qup-core", "qup-config"; 1409 status = "disabled"; 1410 }; 1411 1412 i2c7: i2c@99c000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x0099c000 0 0x4000>; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1416 clock-names = "se"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c7_data_clk>; 1419 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1424 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1425 interconnect-names = "qup-core", "qup-config", 1426 "qup-memory"; 1427 power-domains = <&rpmhpd SC7280_CX>; 1428 required-opps = <&rpmhpd_opp_low_svs>; 1429 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1430 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1431 dma-names = "tx", "rx"; 1432 status = "disabled"; 1433 }; 1434 1435 spi7: spi@99c000 { 1436 compatible = "qcom,geni-spi"; 1437 reg = <0 0x0099c000 0 0x4000>; 1438 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1439 clock-names = "se"; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1442 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 power-domains = <&rpmhpd SC7280_CX>; 1446 operating-points-v2 = <&qup_opp_table>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1451 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1452 dma-names = "tx", "rx"; 1453 status = "disabled"; 1454 }; 1455 1456 uart7: serial@99c000 { 1457 compatible = "qcom,geni-uart"; 1458 reg = <0 0x0099c000 0 0x4000>; 1459 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1460 clock-names = "se"; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1463 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1464 power-domains = <&rpmhpd SC7280_CX>; 1465 operating-points-v2 = <&qup_opp_table>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1467 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1468 interconnect-names = "qup-core", "qup-config"; 1469 status = "disabled"; 1470 }; 1471 }; 1472 1473 gpi_dma1: dma-controller@a00000 { 1474 #dma-cells = <3>; 1475 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1476 reg = <0 0x00a00000 0 0x60000>; 1477 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1489 dma-channels = <12>; 1490 dma-channel-mask = <0x1e>; 1491 iommus = <&apps_smmu 0x56 0x0>; 1492 status = "disabled"; 1493 }; 1494 1495 qupv3_id_1: geniqup@ac0000 { 1496 compatible = "qcom,geni-se-qup"; 1497 reg = <0 0x00ac0000 0 0x2000>; 1498 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1499 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1500 clock-names = "m-ahb", "s-ahb"; 1501 #address-cells = <2>; 1502 #size-cells = <2>; 1503 ranges; 1504 iommus = <&apps_smmu 0x43 0x0>; 1505 status = "disabled"; 1506 1507 i2c8: i2c@a80000 { 1508 compatible = "qcom,geni-i2c"; 1509 reg = <0 0x00a80000 0 0x4000>; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1511 clock-names = "se"; 1512 pinctrl-names = "default"; 1513 pinctrl-0 = <&qup_i2c8_data_clk>; 1514 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1518 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1519 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", 1521 "qup-memory"; 1522 power-domains = <&rpmhpd SC7280_CX>; 1523 required-opps = <&rpmhpd_opp_low_svs>; 1524 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1525 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1526 dma-names = "tx", "rx"; 1527 status = "disabled"; 1528 }; 1529 1530 spi8: spi@a80000 { 1531 compatible = "qcom,geni-spi"; 1532 reg = <0 0x00a80000 0 0x4000>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1534 clock-names = "se"; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1537 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 power-domains = <&rpmhpd SC7280_CX>; 1541 operating-points-v2 = <&qup_opp_table>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1543 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1544 interconnect-names = "qup-core", "qup-config"; 1545 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1546 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1547 dma-names = "tx", "rx"; 1548 status = "disabled"; 1549 }; 1550 1551 uart8: serial@a80000 { 1552 compatible = "qcom,geni-uart"; 1553 reg = <0 0x00a80000 0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1555 clock-names = "se"; 1556 pinctrl-names = "default"; 1557 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1559 power-domains = <&rpmhpd SC7280_CX>; 1560 operating-points-v2 = <&qup_opp_table>; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1562 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1563 interconnect-names = "qup-core", "qup-config"; 1564 status = "disabled"; 1565 }; 1566 1567 i2c9: i2c@a84000 { 1568 compatible = "qcom,geni-i2c"; 1569 reg = <0 0x00a84000 0 0x4000>; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 clock-names = "se"; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_i2c9_data_clk>; 1574 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1578 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1579 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1580 interconnect-names = "qup-core", "qup-config", 1581 "qup-memory"; 1582 power-domains = <&rpmhpd SC7280_CX>; 1583 required-opps = <&rpmhpd_opp_low_svs>; 1584 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1585 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1586 dma-names = "tx", "rx"; 1587 status = "disabled"; 1588 }; 1589 1590 spi9: spi@a84000 { 1591 compatible = "qcom,geni-spi"; 1592 reg = <0 0x00a84000 0 0x4000>; 1593 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1594 clock-names = "se"; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1597 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 power-domains = <&rpmhpd SC7280_CX>; 1601 operating-points-v2 = <&qup_opp_table>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1604 interconnect-names = "qup-core", "qup-config"; 1605 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 status = "disabled"; 1609 }; 1610 1611 uart9: serial@a84000 { 1612 compatible = "qcom,geni-uart"; 1613 reg = <0 0x00a84000 0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1615 clock-names = "se"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1618 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1619 power-domains = <&rpmhpd SC7280_CX>; 1620 operating-points-v2 = <&qup_opp_table>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1623 interconnect-names = "qup-core", "qup-config"; 1624 status = "disabled"; 1625 }; 1626 1627 i2c10: i2c@a88000 { 1628 compatible = "qcom,geni-i2c"; 1629 reg = <0 0x00a88000 0 0x4000>; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1631 clock-names = "se"; 1632 pinctrl-names = "default"; 1633 pinctrl-0 = <&qup_i2c10_data_clk>; 1634 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1639 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1640 interconnect-names = "qup-core", "qup-config", 1641 "qup-memory"; 1642 power-domains = <&rpmhpd SC7280_CX>; 1643 required-opps = <&rpmhpd_opp_low_svs>; 1644 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1645 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1646 dma-names = "tx", "rx"; 1647 status = "disabled"; 1648 }; 1649 1650 spi10: spi@a88000 { 1651 compatible = "qcom,geni-spi"; 1652 reg = <0 0x00a88000 0 0x4000>; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1654 clock-names = "se"; 1655 pinctrl-names = "default"; 1656 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1657 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 power-domains = <&rpmhpd SC7280_CX>; 1661 operating-points-v2 = <&qup_opp_table>; 1662 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1663 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1664 interconnect-names = "qup-core", "qup-config"; 1665 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1666 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1667 dma-names = "tx", "rx"; 1668 status = "disabled"; 1669 }; 1670 1671 uart10: serial@a88000 { 1672 compatible = "qcom,geni-uart"; 1673 reg = <0 0x00a88000 0 0x4000>; 1674 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1675 clock-names = "se"; 1676 pinctrl-names = "default"; 1677 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1678 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1679 power-domains = <&rpmhpd SC7280_CX>; 1680 operating-points-v2 = <&qup_opp_table>; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1683 interconnect-names = "qup-core", "qup-config"; 1684 status = "disabled"; 1685 }; 1686 1687 i2c11: i2c@a8c000 { 1688 compatible = "qcom,geni-i2c"; 1689 reg = <0 0x00a8c000 0 0x4000>; 1690 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1691 clock-names = "se"; 1692 pinctrl-names = "default"; 1693 pinctrl-0 = <&qup_i2c11_data_clk>; 1694 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1699 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", 1701 "qup-memory"; 1702 power-domains = <&rpmhpd SC7280_CX>; 1703 required-opps = <&rpmhpd_opp_low_svs>; 1704 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1705 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1706 dma-names = "tx", "rx"; 1707 status = "disabled"; 1708 }; 1709 1710 spi11: spi@a8c000 { 1711 compatible = "qcom,geni-spi"; 1712 reg = <0 0x00a8c000 0 0x4000>; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1714 clock-names = "se"; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1717 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 power-domains = <&rpmhpd SC7280_CX>; 1721 operating-points-v2 = <&qup_opp_table>; 1722 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1723 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1724 interconnect-names = "qup-core", "qup-config"; 1725 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1726 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1727 dma-names = "tx", "rx"; 1728 status = "disabled"; 1729 }; 1730 1731 uart11: serial@a8c000 { 1732 compatible = "qcom,geni-uart"; 1733 reg = <0 0x00a8c000 0 0x4000>; 1734 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1735 clock-names = "se"; 1736 pinctrl-names = "default"; 1737 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1738 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1739 power-domains = <&rpmhpd SC7280_CX>; 1740 operating-points-v2 = <&qup_opp_table>; 1741 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1742 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1743 interconnect-names = "qup-core", "qup-config"; 1744 status = "disabled"; 1745 }; 1746 1747 i2c12: i2c@a90000 { 1748 compatible = "qcom,geni-i2c"; 1749 reg = <0 0x00a90000 0 0x4000>; 1750 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1751 clock-names = "se"; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&qup_i2c12_data_clk>; 1754 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1758 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1759 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1760 interconnect-names = "qup-core", "qup-config", 1761 "qup-memory"; 1762 power-domains = <&rpmhpd SC7280_CX>; 1763 required-opps = <&rpmhpd_opp_low_svs>; 1764 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1765 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1766 dma-names = "tx", "rx"; 1767 status = "disabled"; 1768 }; 1769 1770 spi12: spi@a90000 { 1771 compatible = "qcom,geni-spi"; 1772 reg = <0 0x00a90000 0 0x4000>; 1773 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1774 clock-names = "se"; 1775 pinctrl-names = "default"; 1776 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1777 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 power-domains = <&rpmhpd SC7280_CX>; 1781 operating-points-v2 = <&qup_opp_table>; 1782 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1783 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1784 interconnect-names = "qup-core", "qup-config"; 1785 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1786 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1787 dma-names = "tx", "rx"; 1788 status = "disabled"; 1789 }; 1790 1791 uart12: serial@a90000 { 1792 compatible = "qcom,geni-uart"; 1793 reg = <0 0x00a90000 0 0x4000>; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1795 clock-names = "se"; 1796 pinctrl-names = "default"; 1797 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1798 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1799 power-domains = <&rpmhpd SC7280_CX>; 1800 operating-points-v2 = <&qup_opp_table>; 1801 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1802 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1803 interconnect-names = "qup-core", "qup-config"; 1804 status = "disabled"; 1805 }; 1806 1807 i2c13: i2c@a94000 { 1808 compatible = "qcom,geni-i2c"; 1809 reg = <0 0x00a94000 0 0x4000>; 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1811 clock-names = "se"; 1812 pinctrl-names = "default"; 1813 pinctrl-0 = <&qup_i2c13_data_clk>; 1814 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1818 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1819 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1820 interconnect-names = "qup-core", "qup-config", 1821 "qup-memory"; 1822 power-domains = <&rpmhpd SC7280_CX>; 1823 required-opps = <&rpmhpd_opp_low_svs>; 1824 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1825 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1826 dma-names = "tx", "rx"; 1827 status = "disabled"; 1828 }; 1829 1830 spi13: spi@a94000 { 1831 compatible = "qcom,geni-spi"; 1832 reg = <0 0x00a94000 0 0x4000>; 1833 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1834 clock-names = "se"; 1835 pinctrl-names = "default"; 1836 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1837 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 power-domains = <&rpmhpd SC7280_CX>; 1841 operating-points-v2 = <&qup_opp_table>; 1842 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1843 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1844 interconnect-names = "qup-core", "qup-config"; 1845 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1846 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1847 dma-names = "tx", "rx"; 1848 status = "disabled"; 1849 }; 1850 1851 uart13: serial@a94000 { 1852 compatible = "qcom,geni-uart"; 1853 reg = <0 0x00a94000 0 0x4000>; 1854 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1855 clock-names = "se"; 1856 pinctrl-names = "default"; 1857 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1858 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1859 power-domains = <&rpmhpd SC7280_CX>; 1860 operating-points-v2 = <&qup_opp_table>; 1861 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1862 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1863 interconnect-names = "qup-core", "qup-config"; 1864 status = "disabled"; 1865 }; 1866 1867 i2c14: i2c@a98000 { 1868 compatible = "qcom,geni-i2c"; 1869 reg = <0 0x00a98000 0 0x4000>; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1871 clock-names = "se"; 1872 pinctrl-names = "default"; 1873 pinctrl-0 = <&qup_i2c14_data_clk>; 1874 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1878 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1879 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1880 interconnect-names = "qup-core", "qup-config", 1881 "qup-memory"; 1882 power-domains = <&rpmhpd SC7280_CX>; 1883 required-opps = <&rpmhpd_opp_low_svs>; 1884 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1885 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1886 dma-names = "tx", "rx"; 1887 status = "disabled"; 1888 }; 1889 1890 spi14: spi@a98000 { 1891 compatible = "qcom,geni-spi"; 1892 reg = <0 0x00a98000 0 0x4000>; 1893 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1894 clock-names = "se"; 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1897 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 power-domains = <&rpmhpd SC7280_CX>; 1901 operating-points-v2 = <&qup_opp_table>; 1902 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1903 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1904 interconnect-names = "qup-core", "qup-config"; 1905 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1906 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1907 dma-names = "tx", "rx"; 1908 status = "disabled"; 1909 }; 1910 1911 uart14: serial@a98000 { 1912 compatible = "qcom,geni-uart"; 1913 reg = <0 0x00a98000 0 0x4000>; 1914 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1915 clock-names = "se"; 1916 pinctrl-names = "default"; 1917 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1918 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1919 power-domains = <&rpmhpd SC7280_CX>; 1920 operating-points-v2 = <&qup_opp_table>; 1921 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1922 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1923 interconnect-names = "qup-core", "qup-config"; 1924 status = "disabled"; 1925 }; 1926 1927 i2c15: i2c@a9c000 { 1928 compatible = "qcom,geni-i2c"; 1929 reg = <0 0x00a9c000 0 0x4000>; 1930 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1931 clock-names = "se"; 1932 pinctrl-names = "default"; 1933 pinctrl-0 = <&qup_i2c15_data_clk>; 1934 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1938 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1939 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1940 interconnect-names = "qup-core", "qup-config", 1941 "qup-memory"; 1942 power-domains = <&rpmhpd SC7280_CX>; 1943 required-opps = <&rpmhpd_opp_low_svs>; 1944 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1945 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1946 dma-names = "tx", "rx"; 1947 status = "disabled"; 1948 }; 1949 1950 spi15: spi@a9c000 { 1951 compatible = "qcom,geni-spi"; 1952 reg = <0 0x00a9c000 0 0x4000>; 1953 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1954 clock-names = "se"; 1955 pinctrl-names = "default"; 1956 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1957 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1958 #address-cells = <1>; 1959 #size-cells = <0>; 1960 power-domains = <&rpmhpd SC7280_CX>; 1961 operating-points-v2 = <&qup_opp_table>; 1962 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1963 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1964 interconnect-names = "qup-core", "qup-config"; 1965 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1966 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1967 dma-names = "tx", "rx"; 1968 status = "disabled"; 1969 }; 1970 1971 uart15: serial@a9c000 { 1972 compatible = "qcom,geni-uart"; 1973 reg = <0 0x00a9c000 0 0x4000>; 1974 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1975 clock-names = "se"; 1976 pinctrl-names = "default"; 1977 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1978 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1979 power-domains = <&rpmhpd SC7280_CX>; 1980 operating-points-v2 = <&qup_opp_table>; 1981 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1982 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1983 interconnect-names = "qup-core", "qup-config"; 1984 status = "disabled"; 1985 }; 1986 }; 1987 1988 cnoc2: interconnect@1500000 { 1989 reg = <0 0x01500000 0 0x1000>; 1990 compatible = "qcom,sc7280-cnoc2"; 1991 #interconnect-cells = <2>; 1992 qcom,bcm-voters = <&apps_bcm_voter>; 1993 }; 1994 1995 cnoc3: interconnect@1502000 { 1996 reg = <0 0x01502000 0 0x1000>; 1997 compatible = "qcom,sc7280-cnoc3"; 1998 #interconnect-cells = <2>; 1999 qcom,bcm-voters = <&apps_bcm_voter>; 2000 }; 2001 2002 mc_virt: interconnect@1580000 { 2003 reg = <0 0x01580000 0 0x4>; 2004 compatible = "qcom,sc7280-mc-virt"; 2005 #interconnect-cells = <2>; 2006 qcom,bcm-voters = <&apps_bcm_voter>; 2007 }; 2008 2009 system_noc: interconnect@1680000 { 2010 reg = <0 0x01680000 0 0x15480>; 2011 compatible = "qcom,sc7280-system-noc"; 2012 #interconnect-cells = <2>; 2013 qcom,bcm-voters = <&apps_bcm_voter>; 2014 }; 2015 2016 aggre1_noc: interconnect@16e0000 { 2017 compatible = "qcom,sc7280-aggre1-noc"; 2018 reg = <0 0x016e0000 0 0x1c080>; 2019 #interconnect-cells = <2>; 2020 qcom,bcm-voters = <&apps_bcm_voter>; 2021 }; 2022 2023 aggre2_noc: interconnect@1700000 { 2024 reg = <0 0x01700000 0 0x2b080>; 2025 compatible = "qcom,sc7280-aggre2-noc"; 2026 #interconnect-cells = <2>; 2027 qcom,bcm-voters = <&apps_bcm_voter>; 2028 }; 2029 2030 mmss_noc: interconnect@1740000 { 2031 reg = <0 0x01740000 0 0x1e080>; 2032 compatible = "qcom,sc7280-mmss-noc"; 2033 #interconnect-cells = <2>; 2034 qcom,bcm-voters = <&apps_bcm_voter>; 2035 }; 2036 2037 wifi: wifi@17a10040 { 2038 compatible = "qcom,wcn6750-wifi"; 2039 reg = <0 0x17a10040 0 0x0>; 2040 iommus = <&apps_smmu 0x1c00 0x1>; 2041 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2073 qcom,rproc = <&remoteproc_wpss>; 2074 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2075 status = "disabled"; 2076 qcom,smem-states = <&wlan_smp2p_out 0>; 2077 qcom,smem-state-names = "wlan-smp2p-out"; 2078 }; 2079 2080 pcie1: pci@1c08000 { 2081 compatible = "qcom,pcie-sc7280"; 2082 reg = <0 0x01c08000 0 0x3000>, 2083 <0 0x40000000 0 0xf1d>, 2084 <0 0x40000f20 0 0xa8>, 2085 <0 0x40001000 0 0x1000>, 2086 <0 0x40100000 0 0x100000>; 2087 2088 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2089 device_type = "pci"; 2090 linux,pci-domain = <1>; 2091 bus-range = <0x00 0xff>; 2092 num-lanes = <2>; 2093 2094 #address-cells = <3>; 2095 #size-cells = <2>; 2096 2097 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2098 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2099 2100 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2101 interrupt-names = "msi"; 2102 #interrupt-cells = <1>; 2103 interrupt-map-mask = <0 0 0 0x7>; 2104 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2105 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2106 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2107 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2108 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2110 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2111 <&pcie1_lane>, 2112 <&rpmhcc RPMH_CXO_CLK>, 2113 <&gcc GCC_PCIE_1_AUX_CLK>, 2114 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2115 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2116 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2117 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2118 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2119 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2120 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2121 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2122 2123 clock-names = "pipe", 2124 "pipe_mux", 2125 "phy_pipe", 2126 "ref", 2127 "aux", 2128 "cfg", 2129 "bus_master", 2130 "bus_slave", 2131 "slave_q2a", 2132 "tbu", 2133 "ddrss_sf_tbu", 2134 "aggre0", 2135 "aggre1"; 2136 2137 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2138 assigned-clock-rates = <19200000>; 2139 2140 resets = <&gcc GCC_PCIE_1_BCR>; 2141 reset-names = "pci"; 2142 2143 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2144 2145 phys = <&pcie1_lane>; 2146 phy-names = "pciephy"; 2147 2148 pinctrl-names = "default"; 2149 pinctrl-0 = <&pcie1_clkreq_n>; 2150 2151 dma-coherent; 2152 2153 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2154 <0x100 &apps_smmu 0x1c81 0x1>; 2155 2156 status = "disabled"; 2157 }; 2158 2159 pcie1_phy: phy@1c0e000 { 2160 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2161 reg = <0 0x01c0e000 0 0x1c0>; 2162 #address-cells = <2>; 2163 #size-cells = <2>; 2164 ranges; 2165 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2166 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2167 <&gcc GCC_PCIE_CLKREF_EN>, 2168 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2169 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2170 2171 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2172 reset-names = "phy"; 2173 2174 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2175 assigned-clock-rates = <100000000>; 2176 2177 status = "disabled"; 2178 2179 pcie1_lane: phy@1c0e200 { 2180 reg = <0 0x01c0e200 0 0x170>, 2181 <0 0x01c0e400 0 0x200>, 2182 <0 0x01c0ea00 0 0x1f0>, 2183 <0 0x01c0e600 0 0x170>, 2184 <0 0x01c0e800 0 0x200>, 2185 <0 0x01c0ee00 0 0xf4>; 2186 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2187 clock-names = "pipe0"; 2188 2189 #phy-cells = <0>; 2190 #clock-cells = <0>; 2191 clock-output-names = "pcie_1_pipe_clk"; 2192 }; 2193 }; 2194 2195 ipa: ipa@1e40000 { 2196 compatible = "qcom,sc7280-ipa"; 2197 2198 iommus = <&apps_smmu 0x480 0x0>, 2199 <&apps_smmu 0x482 0x0>; 2200 reg = <0 0x01e40000 0 0x8000>, 2201 <0 0x01e50000 0 0x4ad0>, 2202 <0 0x01e04000 0 0x23000>; 2203 reg-names = "ipa-reg", 2204 "ipa-shared", 2205 "gsi"; 2206 2207 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2208 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2209 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2210 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2211 interrupt-names = "ipa", 2212 "gsi", 2213 "ipa-clock-query", 2214 "ipa-setup-ready"; 2215 2216 clocks = <&rpmhcc RPMH_IPA_CLK>; 2217 clock-names = "core"; 2218 2219 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2221 interconnect-names = "memory", 2222 "config"; 2223 2224 qcom,qmp = <&aoss_qmp>; 2225 2226 qcom,smem-states = <&ipa_smp2p_out 0>, 2227 <&ipa_smp2p_out 1>; 2228 qcom,smem-state-names = "ipa-clock-enabled-valid", 2229 "ipa-clock-enabled"; 2230 2231 status = "disabled"; 2232 }; 2233 2234 tcsr_mutex: hwlock@1f40000 { 2235 compatible = "qcom,tcsr-mutex"; 2236 reg = <0 0x01f40000 0 0x20000>; 2237 #hwlock-cells = <1>; 2238 }; 2239 2240 tcsr_1: syscon@1f60000 { 2241 compatible = "qcom,sc7280-tcsr", "syscon"; 2242 reg = <0 0x01f60000 0 0x20000>; 2243 }; 2244 2245 tcsr_2: syscon@1fc0000 { 2246 compatible = "qcom,sc7280-tcsr", "syscon"; 2247 reg = <0 0x01fc0000 0 0x30000>; 2248 }; 2249 2250 lpasscc: lpasscc@3000000 { 2251 compatible = "qcom,sc7280-lpasscc"; 2252 reg = <0 0x03000000 0 0x40>, 2253 <0 0x03c04000 0 0x4>; 2254 reg-names = "qdsp6ss", "top_cc"; 2255 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2256 clock-names = "iface"; 2257 #clock-cells = <1>; 2258 status = "reserved"; /* Owned by ADSP firmware */ 2259 }; 2260 2261 lpass_rx_macro: codec@3200000 { 2262 compatible = "qcom,sc7280-lpass-rx-macro"; 2263 reg = <0 0x03200000 0 0x1000>; 2264 2265 pinctrl-names = "default"; 2266 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2267 2268 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2269 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2270 <&lpass_va_macro>; 2271 clock-names = "mclk", "npl", "fsgen"; 2272 2273 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2274 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2275 power-domain-names = "macro", "dcodec"; 2276 2277 #clock-cells = <0>; 2278 #sound-dai-cells = <1>; 2279 2280 status = "disabled"; 2281 }; 2282 2283 swr0: soundwire@3210000 { 2284 compatible = "qcom,soundwire-v1.6.0"; 2285 reg = <0 0x03210000 0 0x2000>; 2286 2287 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&lpass_rx_macro>; 2289 clock-names = "iface"; 2290 2291 qcom,din-ports = <0>; 2292 qcom,dout-ports = <5>; 2293 2294 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2295 reset-names = "swr_audio_cgcr"; 2296 2297 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2298 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2299 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2300 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2301 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2302 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2303 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2304 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2305 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2306 2307 #sound-dai-cells = <1>; 2308 #address-cells = <2>; 2309 #size-cells = <0>; 2310 2311 status = "disabled"; 2312 }; 2313 2314 lpass_tx_macro: codec@3220000 { 2315 compatible = "qcom,sc7280-lpass-tx-macro"; 2316 reg = <0 0x03220000 0 0x1000>; 2317 2318 pinctrl-names = "default"; 2319 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2320 2321 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2322 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2323 <&lpass_va_macro>; 2324 clock-names = "mclk", "npl", "fsgen"; 2325 2326 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2327 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2328 power-domain-names = "macro", "dcodec"; 2329 2330 #clock-cells = <0>; 2331 #sound-dai-cells = <1>; 2332 2333 status = "disabled"; 2334 }; 2335 2336 swr1: soundwire@3230000 { 2337 compatible = "qcom,soundwire-v1.6.0"; 2338 reg = <0 0x03230000 0 0x2000>; 2339 2340 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2341 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2342 clocks = <&lpass_tx_macro>; 2343 clock-names = "iface"; 2344 2345 qcom,din-ports = <3>; 2346 qcom,dout-ports = <0>; 2347 2348 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2349 reset-names = "swr_audio_cgcr"; 2350 2351 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2352 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2353 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2354 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2355 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2356 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2357 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2358 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2359 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2360 2361 #sound-dai-cells = <1>; 2362 #address-cells = <2>; 2363 #size-cells = <0>; 2364 2365 status = "disabled"; 2366 }; 2367 2368 lpass_audiocc: clock-controller@3300000 { 2369 compatible = "qcom,sc7280-lpassaudiocc"; 2370 reg = <0 0x03300000 0 0x30000>, 2371 <0 0x032a9000 0 0x1000>; 2372 clocks = <&rpmhcc RPMH_CXO_CLK>, 2373 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2374 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2375 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2376 #clock-cells = <1>; 2377 #power-domain-cells = <1>; 2378 #reset-cells = <1>; 2379 }; 2380 2381 lpass_va_macro: codec@3370000 { 2382 compatible = "qcom,sc7280-lpass-va-macro"; 2383 reg = <0 0x03370000 0 0x1000>; 2384 2385 pinctrl-names = "default"; 2386 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2387 2388 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2389 clock-names = "mclk"; 2390 2391 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2392 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2393 power-domain-names = "macro", "dcodec"; 2394 2395 #clock-cells = <0>; 2396 #sound-dai-cells = <1>; 2397 2398 status = "disabled"; 2399 }; 2400 2401 lpass_aon: clock-controller@3380000 { 2402 compatible = "qcom,sc7280-lpassaoncc"; 2403 reg = <0 0x03380000 0 0x30000>; 2404 clocks = <&rpmhcc RPMH_CXO_CLK>, 2405 <&rpmhcc RPMH_CXO_CLK_A>, 2406 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2407 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2408 #clock-cells = <1>; 2409 #power-domain-cells = <1>; 2410 status = "reserved"; /* Owned by ADSP firmware */ 2411 }; 2412 2413 lpass_core: clock-controller@3900000 { 2414 compatible = "qcom,sc7280-lpasscorecc"; 2415 reg = <0 0x03900000 0 0x50000>; 2416 clocks = <&rpmhcc RPMH_CXO_CLK>; 2417 clock-names = "bi_tcxo"; 2418 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2419 #clock-cells = <1>; 2420 #power-domain-cells = <1>; 2421 status = "reserved"; /* Owned by ADSP firmware */ 2422 }; 2423 2424 lpass_cpu: audio@3987000 { 2425 compatible = "qcom,sc7280-lpass-cpu"; 2426 2427 reg = <0 0x03987000 0 0x68000>, 2428 <0 0x03b00000 0 0x29000>, 2429 <0 0x03260000 0 0xc000>, 2430 <0 0x03280000 0 0x29000>, 2431 <0 0x03340000 0 0x29000>, 2432 <0 0x0336c000 0 0x3000>; 2433 reg-names = "lpass-hdmiif", 2434 "lpass-lpaif", 2435 "lpass-rxtx-cdc-dma-lpm", 2436 "lpass-rxtx-lpaif", 2437 "lpass-va-lpaif", 2438 "lpass-va-cdc-dma-lpm"; 2439 2440 iommus = <&apps_smmu 0x1820 0>, 2441 <&apps_smmu 0x1821 0>, 2442 <&apps_smmu 0x1832 0>; 2443 2444 power-domains = <&rpmhpd SC7280_LCX>; 2445 power-domain-names = "lcx"; 2446 required-opps = <&rpmhpd_opp_nom>; 2447 2448 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2449 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2450 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2451 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2452 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2453 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2454 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2455 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2456 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2457 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2458 clock-names = "aon_cc_audio_hm_h", 2459 "audio_cc_ext_mclk0", 2460 "core_cc_sysnoc_mport_core", 2461 "core_cc_ext_if0_ibit", 2462 "core_cc_ext_if1_ibit", 2463 "audio_cc_codec_mem", 2464 "audio_cc_codec_mem0", 2465 "audio_cc_codec_mem1", 2466 "audio_cc_codec_mem2", 2467 "aon_cc_va_mem0"; 2468 2469 #sound-dai-cells = <1>; 2470 #address-cells = <1>; 2471 #size-cells = <0>; 2472 2473 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2477 interrupt-names = "lpass-irq-lpaif", 2478 "lpass-irq-hdmi", 2479 "lpass-irq-vaif", 2480 "lpass-irq-rxtxif"; 2481 2482 status = "disabled"; 2483 }; 2484 2485 lpass_hm: clock-controller@3c00000 { 2486 compatible = "qcom,sc7280-lpasshm"; 2487 reg = <0 0x03c00000 0 0x28>; 2488 clocks = <&rpmhcc RPMH_CXO_CLK>; 2489 clock-names = "bi_tcxo"; 2490 #clock-cells = <1>; 2491 #power-domain-cells = <1>; 2492 status = "reserved"; /* Owned by ADSP firmware */ 2493 }; 2494 2495 lpass_ag_noc: interconnect@3c40000 { 2496 reg = <0 0x03c40000 0 0xf080>; 2497 compatible = "qcom,sc7280-lpass-ag-noc"; 2498 #interconnect-cells = <2>; 2499 qcom,bcm-voters = <&apps_bcm_voter>; 2500 }; 2501 2502 lpass_tlmm: pinctrl@33c0000 { 2503 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2504 reg = <0 0x033c0000 0x0 0x20000>, 2505 <0 0x03550000 0x0 0x10000>; 2506 qcom,adsp-bypass-mode; 2507 gpio-controller; 2508 #gpio-cells = <2>; 2509 gpio-ranges = <&lpass_tlmm 0 0 15>; 2510 2511 lpass_dmic01_clk: dmic01-clk-state { 2512 pins = "gpio6"; 2513 function = "dmic1_clk"; 2514 }; 2515 2516 lpass_dmic01_data: dmic01-data-state { 2517 pins = "gpio7"; 2518 function = "dmic1_data"; 2519 }; 2520 2521 lpass_dmic23_clk: dmic23-clk-state { 2522 pins = "gpio8"; 2523 function = "dmic2_clk"; 2524 }; 2525 2526 lpass_dmic23_data: dmic23-data-state { 2527 pins = "gpio9"; 2528 function = "dmic2_data"; 2529 }; 2530 2531 lpass_rx_swr_clk: rx-swr-clk-state { 2532 pins = "gpio3"; 2533 function = "swr_rx_clk"; 2534 }; 2535 2536 lpass_rx_swr_data: rx-swr-data-state { 2537 pins = "gpio4", "gpio5"; 2538 function = "swr_rx_data"; 2539 }; 2540 2541 lpass_tx_swr_clk: tx-swr-clk-state { 2542 pins = "gpio0"; 2543 function = "swr_tx_clk"; 2544 }; 2545 2546 lpass_tx_swr_data: tx-swr-data-state { 2547 pins = "gpio1", "gpio2", "gpio14"; 2548 function = "swr_tx_data"; 2549 }; 2550 }; 2551 2552 gpu: gpu@3d00000 { 2553 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2554 reg = <0 0x03d00000 0 0x40000>, 2555 <0 0x03d9e000 0 0x1000>, 2556 <0 0x03d61000 0 0x800>; 2557 reg-names = "kgsl_3d0_reg_memory", 2558 "cx_mem", 2559 "cx_dbgc"; 2560 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2561 iommus = <&adreno_smmu 0 0x400>, 2562 <&adreno_smmu 1 0x400>; 2563 operating-points-v2 = <&gpu_opp_table>; 2564 qcom,gmu = <&gmu>; 2565 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2566 interconnect-names = "gfx-mem"; 2567 #cooling-cells = <2>; 2568 2569 nvmem-cells = <&gpu_speed_bin>; 2570 nvmem-cell-names = "speed_bin"; 2571 2572 gpu_opp_table: opp-table { 2573 compatible = "operating-points-v2"; 2574 2575 opp-315000000 { 2576 opp-hz = /bits/ 64 <315000000>; 2577 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2578 opp-peak-kBps = <1804000>; 2579 opp-supported-hw = <0x03>; 2580 }; 2581 2582 opp-450000000 { 2583 opp-hz = /bits/ 64 <450000000>; 2584 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2585 opp-peak-kBps = <4068000>; 2586 opp-supported-hw = <0x03>; 2587 }; 2588 2589 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2590 opp-550000000-0 { 2591 opp-hz = /bits/ 64 <550000000>; 2592 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2593 opp-peak-kBps = <8368000>; 2594 opp-supported-hw = <0x01>; 2595 }; 2596 2597 opp-550000000-1 { 2598 opp-hz = /bits/ 64 <550000000>; 2599 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2600 opp-peak-kBps = <6832000>; 2601 opp-supported-hw = <0x02>; 2602 }; 2603 2604 opp-608000000 { 2605 opp-hz = /bits/ 64 <608000000>; 2606 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2607 opp-peak-kBps = <8368000>; 2608 opp-supported-hw = <0x02>; 2609 }; 2610 2611 opp-700000000 { 2612 opp-hz = /bits/ 64 <700000000>; 2613 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2614 opp-peak-kBps = <8532000>; 2615 opp-supported-hw = <0x02>; 2616 }; 2617 2618 opp-812000000 { 2619 opp-hz = /bits/ 64 <812000000>; 2620 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2621 opp-peak-kBps = <8532000>; 2622 opp-supported-hw = <0x02>; 2623 }; 2624 2625 opp-840000000 { 2626 opp-hz = /bits/ 64 <840000000>; 2627 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2628 opp-peak-kBps = <8532000>; 2629 opp-supported-hw = <0x02>; 2630 }; 2631 2632 opp-900000000 { 2633 opp-hz = /bits/ 64 <900000000>; 2634 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2635 opp-peak-kBps = <8532000>; 2636 opp-supported-hw = <0x02>; 2637 }; 2638 }; 2639 }; 2640 2641 gmu: gmu@3d6a000 { 2642 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2643 reg = <0 0x03d6a000 0 0x34000>, 2644 <0 0x3de0000 0 0x10000>, 2645 <0 0x0b290000 0 0x10000>; 2646 reg-names = "gmu", "rscc", "gmu_pdc"; 2647 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2648 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2649 interrupt-names = "hfi", "gmu"; 2650 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2651 <&gpucc GPU_CC_CXO_CLK>, 2652 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2653 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2654 <&gpucc GPU_CC_AHB_CLK>, 2655 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2656 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2657 clock-names = "gmu", 2658 "cxo", 2659 "axi", 2660 "memnoc", 2661 "ahb", 2662 "hub", 2663 "smmu_vote"; 2664 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2665 <&gpucc GPU_CC_GX_GDSC>; 2666 power-domain-names = "cx", 2667 "gx"; 2668 iommus = <&adreno_smmu 5 0x400>; 2669 operating-points-v2 = <&gmu_opp_table>; 2670 2671 gmu_opp_table: opp-table { 2672 compatible = "operating-points-v2"; 2673 2674 opp-200000000 { 2675 opp-hz = /bits/ 64 <200000000>; 2676 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2677 }; 2678 }; 2679 }; 2680 2681 gpucc: clock-controller@3d90000 { 2682 compatible = "qcom,sc7280-gpucc"; 2683 reg = <0 0x03d90000 0 0x9000>; 2684 clocks = <&rpmhcc RPMH_CXO_CLK>, 2685 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2686 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2687 clock-names = "bi_tcxo", 2688 "gcc_gpu_gpll0_clk_src", 2689 "gcc_gpu_gpll0_div_clk_src"; 2690 #clock-cells = <1>; 2691 #reset-cells = <1>; 2692 #power-domain-cells = <1>; 2693 }; 2694 2695 dma@117f000 { 2696 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2697 reg = <0x0 0x0117f000 0x0 0x1000>, 2698 <0x0 0x01112000 0x0 0x6000>; 2699 }; 2700 2701 adreno_smmu: iommu@3da0000 { 2702 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2703 "qcom,smmu-500", "arm,mmu-500"; 2704 reg = <0 0x03da0000 0 0x20000>; 2705 #iommu-cells = <2>; 2706 #global-interrupts = <2>; 2707 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2719 2720 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2721 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2722 <&gpucc GPU_CC_AHB_CLK>, 2723 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2724 <&gpucc GPU_CC_CX_GMU_CLK>, 2725 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2726 <&gpucc GPU_CC_HUB_AON_CLK>; 2727 clock-names = "gcc_gpu_memnoc_gfx_clk", 2728 "gcc_gpu_snoc_dvm_gfx_clk", 2729 "gpu_cc_ahb_clk", 2730 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2731 "gpu_cc_cx_gmu_clk", 2732 "gpu_cc_hub_cx_int_clk", 2733 "gpu_cc_hub_aon_clk"; 2734 2735 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2736 dma-coherent; 2737 }; 2738 2739 remoteproc_mpss: remoteproc@4080000 { 2740 compatible = "qcom,sc7280-mpss-pas"; 2741 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2742 reg-names = "qdsp6", "rmb"; 2743 2744 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2745 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2746 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2747 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2748 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2749 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2750 interrupt-names = "wdog", "fatal", "ready", "handover", 2751 "stop-ack", "shutdown-ack"; 2752 2753 clocks = <&rpmhcc RPMH_CXO_CLK>; 2754 clock-names = "xo"; 2755 2756 power-domains = <&rpmhpd SC7280_CX>, 2757 <&rpmhpd SC7280_MSS>; 2758 power-domain-names = "cx", "mss"; 2759 2760 memory-region = <&mpss_mem>; 2761 2762 qcom,qmp = <&aoss_qmp>; 2763 2764 qcom,smem-states = <&modem_smp2p_out 0>; 2765 qcom,smem-state-names = "stop"; 2766 2767 status = "disabled"; 2768 2769 glink-edge { 2770 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2771 IPCC_MPROC_SIGNAL_GLINK_QMP 2772 IRQ_TYPE_EDGE_RISING>; 2773 mboxes = <&ipcc IPCC_CLIENT_MPSS 2774 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2775 label = "modem"; 2776 qcom,remote-pid = <1>; 2777 }; 2778 }; 2779 2780 stm@6002000 { 2781 compatible = "arm,coresight-stm", "arm,primecell"; 2782 reg = <0 0x06002000 0 0x1000>, 2783 <0 0x16280000 0 0x180000>; 2784 reg-names = "stm-base", "stm-stimulus-base"; 2785 2786 clocks = <&aoss_qmp>; 2787 clock-names = "apb_pclk"; 2788 2789 out-ports { 2790 port { 2791 stm_out: endpoint { 2792 remote-endpoint = <&funnel0_in7>; 2793 }; 2794 }; 2795 }; 2796 }; 2797 2798 funnel@6041000 { 2799 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2800 reg = <0 0x06041000 0 0x1000>; 2801 2802 clocks = <&aoss_qmp>; 2803 clock-names = "apb_pclk"; 2804 2805 out-ports { 2806 port { 2807 funnel0_out: endpoint { 2808 remote-endpoint = <&merge_funnel_in0>; 2809 }; 2810 }; 2811 }; 2812 2813 in-ports { 2814 #address-cells = <1>; 2815 #size-cells = <0>; 2816 2817 port@7 { 2818 reg = <7>; 2819 funnel0_in7: endpoint { 2820 remote-endpoint = <&stm_out>; 2821 }; 2822 }; 2823 }; 2824 }; 2825 2826 funnel@6042000 { 2827 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2828 reg = <0 0x06042000 0 0x1000>; 2829 2830 clocks = <&aoss_qmp>; 2831 clock-names = "apb_pclk"; 2832 2833 out-ports { 2834 port { 2835 funnel1_out: endpoint { 2836 remote-endpoint = <&merge_funnel_in1>; 2837 }; 2838 }; 2839 }; 2840 2841 in-ports { 2842 #address-cells = <1>; 2843 #size-cells = <0>; 2844 2845 port@4 { 2846 reg = <4>; 2847 funnel1_in4: endpoint { 2848 remote-endpoint = <&apss_merge_funnel_out>; 2849 }; 2850 }; 2851 }; 2852 }; 2853 2854 funnel@6045000 { 2855 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2856 reg = <0 0x06045000 0 0x1000>; 2857 2858 clocks = <&aoss_qmp>; 2859 clock-names = "apb_pclk"; 2860 2861 out-ports { 2862 port { 2863 merge_funnel_out: endpoint { 2864 remote-endpoint = <&swao_funnel_in>; 2865 }; 2866 }; 2867 }; 2868 2869 in-ports { 2870 #address-cells = <1>; 2871 #size-cells = <0>; 2872 2873 port@0 { 2874 reg = <0>; 2875 merge_funnel_in0: endpoint { 2876 remote-endpoint = <&funnel0_out>; 2877 }; 2878 }; 2879 2880 port@1 { 2881 reg = <1>; 2882 merge_funnel_in1: endpoint { 2883 remote-endpoint = <&funnel1_out>; 2884 }; 2885 }; 2886 }; 2887 }; 2888 2889 replicator@6046000 { 2890 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2891 reg = <0 0x06046000 0 0x1000>; 2892 2893 clocks = <&aoss_qmp>; 2894 clock-names = "apb_pclk"; 2895 2896 out-ports { 2897 port { 2898 replicator_out: endpoint { 2899 remote-endpoint = <&etr_in>; 2900 }; 2901 }; 2902 }; 2903 2904 in-ports { 2905 port { 2906 replicator_in: endpoint { 2907 remote-endpoint = <&swao_replicator_out>; 2908 }; 2909 }; 2910 }; 2911 }; 2912 2913 etr@6048000 { 2914 compatible = "arm,coresight-tmc", "arm,primecell"; 2915 reg = <0 0x06048000 0 0x1000>; 2916 iommus = <&apps_smmu 0x04c0 0>; 2917 2918 clocks = <&aoss_qmp>; 2919 clock-names = "apb_pclk"; 2920 arm,scatter-gather; 2921 2922 in-ports { 2923 port { 2924 etr_in: endpoint { 2925 remote-endpoint = <&replicator_out>; 2926 }; 2927 }; 2928 }; 2929 }; 2930 2931 funnel@6b04000 { 2932 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2933 reg = <0 0x06b04000 0 0x1000>; 2934 2935 clocks = <&aoss_qmp>; 2936 clock-names = "apb_pclk"; 2937 2938 out-ports { 2939 port { 2940 swao_funnel_out: endpoint { 2941 remote-endpoint = <&etf_in>; 2942 }; 2943 }; 2944 }; 2945 2946 in-ports { 2947 #address-cells = <1>; 2948 #size-cells = <0>; 2949 2950 port@7 { 2951 reg = <7>; 2952 swao_funnel_in: endpoint { 2953 remote-endpoint = <&merge_funnel_out>; 2954 }; 2955 }; 2956 }; 2957 }; 2958 2959 etf@6b05000 { 2960 compatible = "arm,coresight-tmc", "arm,primecell"; 2961 reg = <0 0x06b05000 0 0x1000>; 2962 2963 clocks = <&aoss_qmp>; 2964 clock-names = "apb_pclk"; 2965 2966 out-ports { 2967 port { 2968 etf_out: endpoint { 2969 remote-endpoint = <&swao_replicator_in>; 2970 }; 2971 }; 2972 }; 2973 2974 in-ports { 2975 port { 2976 etf_in: endpoint { 2977 remote-endpoint = <&swao_funnel_out>; 2978 }; 2979 }; 2980 }; 2981 }; 2982 2983 replicator@6b06000 { 2984 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2985 reg = <0 0x06b06000 0 0x1000>; 2986 2987 clocks = <&aoss_qmp>; 2988 clock-names = "apb_pclk"; 2989 qcom,replicator-loses-context; 2990 2991 out-ports { 2992 port { 2993 swao_replicator_out: endpoint { 2994 remote-endpoint = <&replicator_in>; 2995 }; 2996 }; 2997 }; 2998 2999 in-ports { 3000 port { 3001 swao_replicator_in: endpoint { 3002 remote-endpoint = <&etf_out>; 3003 }; 3004 }; 3005 }; 3006 }; 3007 3008 etm@7040000 { 3009 compatible = "arm,coresight-etm4x", "arm,primecell"; 3010 reg = <0 0x07040000 0 0x1000>; 3011 3012 cpu = <&CPU0>; 3013 3014 clocks = <&aoss_qmp>; 3015 clock-names = "apb_pclk"; 3016 arm,coresight-loses-context-with-cpu; 3017 qcom,skip-power-up; 3018 3019 out-ports { 3020 port { 3021 etm0_out: endpoint { 3022 remote-endpoint = <&apss_funnel_in0>; 3023 }; 3024 }; 3025 }; 3026 }; 3027 3028 etm@7140000 { 3029 compatible = "arm,coresight-etm4x", "arm,primecell"; 3030 reg = <0 0x07140000 0 0x1000>; 3031 3032 cpu = <&CPU1>; 3033 3034 clocks = <&aoss_qmp>; 3035 clock-names = "apb_pclk"; 3036 arm,coresight-loses-context-with-cpu; 3037 qcom,skip-power-up; 3038 3039 out-ports { 3040 port { 3041 etm1_out: endpoint { 3042 remote-endpoint = <&apss_funnel_in1>; 3043 }; 3044 }; 3045 }; 3046 }; 3047 3048 etm@7240000 { 3049 compatible = "arm,coresight-etm4x", "arm,primecell"; 3050 reg = <0 0x07240000 0 0x1000>; 3051 3052 cpu = <&CPU2>; 3053 3054 clocks = <&aoss_qmp>; 3055 clock-names = "apb_pclk"; 3056 arm,coresight-loses-context-with-cpu; 3057 qcom,skip-power-up; 3058 3059 out-ports { 3060 port { 3061 etm2_out: endpoint { 3062 remote-endpoint = <&apss_funnel_in2>; 3063 }; 3064 }; 3065 }; 3066 }; 3067 3068 etm@7340000 { 3069 compatible = "arm,coresight-etm4x", "arm,primecell"; 3070 reg = <0 0x07340000 0 0x1000>; 3071 3072 cpu = <&CPU3>; 3073 3074 clocks = <&aoss_qmp>; 3075 clock-names = "apb_pclk"; 3076 arm,coresight-loses-context-with-cpu; 3077 qcom,skip-power-up; 3078 3079 out-ports { 3080 port { 3081 etm3_out: endpoint { 3082 remote-endpoint = <&apss_funnel_in3>; 3083 }; 3084 }; 3085 }; 3086 }; 3087 3088 etm@7440000 { 3089 compatible = "arm,coresight-etm4x", "arm,primecell"; 3090 reg = <0 0x07440000 0 0x1000>; 3091 3092 cpu = <&CPU4>; 3093 3094 clocks = <&aoss_qmp>; 3095 clock-names = "apb_pclk"; 3096 arm,coresight-loses-context-with-cpu; 3097 qcom,skip-power-up; 3098 3099 out-ports { 3100 port { 3101 etm4_out: endpoint { 3102 remote-endpoint = <&apss_funnel_in4>; 3103 }; 3104 }; 3105 }; 3106 }; 3107 3108 etm@7540000 { 3109 compatible = "arm,coresight-etm4x", "arm,primecell"; 3110 reg = <0 0x07540000 0 0x1000>; 3111 3112 cpu = <&CPU5>; 3113 3114 clocks = <&aoss_qmp>; 3115 clock-names = "apb_pclk"; 3116 arm,coresight-loses-context-with-cpu; 3117 qcom,skip-power-up; 3118 3119 out-ports { 3120 port { 3121 etm5_out: endpoint { 3122 remote-endpoint = <&apss_funnel_in5>; 3123 }; 3124 }; 3125 }; 3126 }; 3127 3128 etm@7640000 { 3129 compatible = "arm,coresight-etm4x", "arm,primecell"; 3130 reg = <0 0x07640000 0 0x1000>; 3131 3132 cpu = <&CPU6>; 3133 3134 clocks = <&aoss_qmp>; 3135 clock-names = "apb_pclk"; 3136 arm,coresight-loses-context-with-cpu; 3137 qcom,skip-power-up; 3138 3139 out-ports { 3140 port { 3141 etm6_out: endpoint { 3142 remote-endpoint = <&apss_funnel_in6>; 3143 }; 3144 }; 3145 }; 3146 }; 3147 3148 etm@7740000 { 3149 compatible = "arm,coresight-etm4x", "arm,primecell"; 3150 reg = <0 0x07740000 0 0x1000>; 3151 3152 cpu = <&CPU7>; 3153 3154 clocks = <&aoss_qmp>; 3155 clock-names = "apb_pclk"; 3156 arm,coresight-loses-context-with-cpu; 3157 qcom,skip-power-up; 3158 3159 out-ports { 3160 port { 3161 etm7_out: endpoint { 3162 remote-endpoint = <&apss_funnel_in7>; 3163 }; 3164 }; 3165 }; 3166 }; 3167 3168 funnel@7800000 { /* APSS Funnel */ 3169 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3170 reg = <0 0x07800000 0 0x1000>; 3171 3172 clocks = <&aoss_qmp>; 3173 clock-names = "apb_pclk"; 3174 3175 out-ports { 3176 port { 3177 apss_funnel_out: endpoint { 3178 remote-endpoint = <&apss_merge_funnel_in>; 3179 }; 3180 }; 3181 }; 3182 3183 in-ports { 3184 #address-cells = <1>; 3185 #size-cells = <0>; 3186 3187 port@0 { 3188 reg = <0>; 3189 apss_funnel_in0: endpoint { 3190 remote-endpoint = <&etm0_out>; 3191 }; 3192 }; 3193 3194 port@1 { 3195 reg = <1>; 3196 apss_funnel_in1: endpoint { 3197 remote-endpoint = <&etm1_out>; 3198 }; 3199 }; 3200 3201 port@2 { 3202 reg = <2>; 3203 apss_funnel_in2: endpoint { 3204 remote-endpoint = <&etm2_out>; 3205 }; 3206 }; 3207 3208 port@3 { 3209 reg = <3>; 3210 apss_funnel_in3: endpoint { 3211 remote-endpoint = <&etm3_out>; 3212 }; 3213 }; 3214 3215 port@4 { 3216 reg = <4>; 3217 apss_funnel_in4: endpoint { 3218 remote-endpoint = <&etm4_out>; 3219 }; 3220 }; 3221 3222 port@5 { 3223 reg = <5>; 3224 apss_funnel_in5: endpoint { 3225 remote-endpoint = <&etm5_out>; 3226 }; 3227 }; 3228 3229 port@6 { 3230 reg = <6>; 3231 apss_funnel_in6: endpoint { 3232 remote-endpoint = <&etm6_out>; 3233 }; 3234 }; 3235 3236 port@7 { 3237 reg = <7>; 3238 apss_funnel_in7: endpoint { 3239 remote-endpoint = <&etm7_out>; 3240 }; 3241 }; 3242 }; 3243 }; 3244 3245 funnel@7810000 { 3246 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3247 reg = <0 0x07810000 0 0x1000>; 3248 3249 clocks = <&aoss_qmp>; 3250 clock-names = "apb_pclk"; 3251 3252 out-ports { 3253 port { 3254 apss_merge_funnel_out: endpoint { 3255 remote-endpoint = <&funnel1_in4>; 3256 }; 3257 }; 3258 }; 3259 3260 in-ports { 3261 port { 3262 apss_merge_funnel_in: endpoint { 3263 remote-endpoint = <&apss_funnel_out>; 3264 }; 3265 }; 3266 }; 3267 }; 3268 3269 sdhc_2: mmc@8804000 { 3270 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3271 pinctrl-names = "default", "sleep"; 3272 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3273 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3274 status = "disabled"; 3275 3276 reg = <0 0x08804000 0 0x1000>; 3277 3278 iommus = <&apps_smmu 0x100 0x0>; 3279 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3281 interrupt-names = "hc_irq", "pwr_irq"; 3282 3283 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3284 <&gcc GCC_SDCC2_APPS_CLK>, 3285 <&rpmhcc RPMH_CXO_CLK>; 3286 clock-names = "iface", "core", "xo"; 3287 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3288 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3289 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3290 power-domains = <&rpmhpd SC7280_CX>; 3291 operating-points-v2 = <&sdhc2_opp_table>; 3292 3293 bus-width = <4>; 3294 3295 qcom,dll-config = <0x0007642c>; 3296 3297 resets = <&gcc GCC_SDCC2_BCR>; 3298 3299 sdhc2_opp_table: opp-table { 3300 compatible = "operating-points-v2"; 3301 3302 opp-100000000 { 3303 opp-hz = /bits/ 64 <100000000>; 3304 required-opps = <&rpmhpd_opp_low_svs>; 3305 opp-peak-kBps = <1800000 400000>; 3306 opp-avg-kBps = <100000 0>; 3307 }; 3308 3309 opp-202000000 { 3310 opp-hz = /bits/ 64 <202000000>; 3311 required-opps = <&rpmhpd_opp_nom>; 3312 opp-peak-kBps = <5400000 1600000>; 3313 opp-avg-kBps = <200000 0>; 3314 }; 3315 }; 3316 }; 3317 3318 usb_1_hsphy: phy@88e3000 { 3319 compatible = "qcom,sc7280-usb-hs-phy", 3320 "qcom,usb-snps-hs-7nm-phy"; 3321 reg = <0 0x088e3000 0 0x400>; 3322 status = "disabled"; 3323 #phy-cells = <0>; 3324 3325 clocks = <&rpmhcc RPMH_CXO_CLK>; 3326 clock-names = "ref"; 3327 3328 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3329 }; 3330 3331 usb_2_hsphy: phy@88e4000 { 3332 compatible = "qcom,sc7280-usb-hs-phy", 3333 "qcom,usb-snps-hs-7nm-phy"; 3334 reg = <0 0x088e4000 0 0x400>; 3335 status = "disabled"; 3336 #phy-cells = <0>; 3337 3338 clocks = <&rpmhcc RPMH_CXO_CLK>; 3339 clock-names = "ref"; 3340 3341 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3342 }; 3343 3344 usb_1_qmpphy: phy-wrapper@88e9000 { 3345 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3346 "qcom,sm8250-qmp-usb3-dp-phy"; 3347 reg = <0 0x088e9000 0 0x200>, 3348 <0 0x088e8000 0 0x40>, 3349 <0 0x088ea000 0 0x200>; 3350 status = "disabled"; 3351 #address-cells = <2>; 3352 #size-cells = <2>; 3353 ranges; 3354 3355 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3356 <&rpmhcc RPMH_CXO_CLK>, 3357 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3358 clock-names = "aux", "ref_clk_src", "com_aux"; 3359 3360 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3361 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3362 reset-names = "phy", "common"; 3363 3364 usb_1_ssphy: usb3-phy@88e9200 { 3365 reg = <0 0x088e9200 0 0x200>, 3366 <0 0x088e9400 0 0x200>, 3367 <0 0x088e9c00 0 0x400>, 3368 <0 0x088e9600 0 0x200>, 3369 <0 0x088e9800 0 0x200>, 3370 <0 0x088e9a00 0 0x100>; 3371 #clock-cells = <0>; 3372 #phy-cells = <0>; 3373 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3374 clock-names = "pipe0"; 3375 clock-output-names = "usb3_phy_pipe_clk_src"; 3376 }; 3377 3378 dp_phy: dp-phy@88ea200 { 3379 reg = <0 0x088ea200 0 0x200>, 3380 <0 0x088ea400 0 0x200>, 3381 <0 0x088eaa00 0 0x200>, 3382 <0 0x088ea600 0 0x200>, 3383 <0 0x088ea800 0 0x200>; 3384 #phy-cells = <0>; 3385 #clock-cells = <1>; 3386 }; 3387 }; 3388 3389 usb_2: usb@8cf8800 { 3390 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3391 reg = <0 0x08cf8800 0 0x400>; 3392 status = "disabled"; 3393 #address-cells = <2>; 3394 #size-cells = <2>; 3395 ranges; 3396 dma-ranges; 3397 3398 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3399 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3400 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3401 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3402 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3403 clock-names = "cfg_noc", 3404 "core", 3405 "iface", 3406 "sleep", 3407 "mock_utmi"; 3408 3409 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3410 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3411 assigned-clock-rates = <19200000>, <200000000>; 3412 3413 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3414 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3415 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3416 interrupt-names = "hs_phy_irq", 3417 "dp_hs_phy_irq", 3418 "dm_hs_phy_irq"; 3419 3420 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3421 required-opps = <&rpmhpd_opp_nom>; 3422 3423 resets = <&gcc GCC_USB30_SEC_BCR>; 3424 3425 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3426 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3427 interconnect-names = "usb-ddr", "apps-usb"; 3428 3429 usb_2_dwc3: usb@8c00000 { 3430 compatible = "snps,dwc3"; 3431 reg = <0 0x08c00000 0 0xe000>; 3432 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3433 iommus = <&apps_smmu 0xa0 0x0>; 3434 snps,dis_u2_susphy_quirk; 3435 snps,dis_enblslpm_quirk; 3436 phys = <&usb_2_hsphy>; 3437 phy-names = "usb2-phy"; 3438 maximum-speed = "high-speed"; 3439 usb-role-switch; 3440 3441 port { 3442 usb2_role_switch: endpoint { 3443 remote-endpoint = <&eud_ep>; 3444 }; 3445 }; 3446 }; 3447 }; 3448 3449 qspi: spi@88dc000 { 3450 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3451 reg = <0 0x088dc000 0 0x1000>; 3452 iommus = <&apps_smmu 0x20 0x0>; 3453 #address-cells = <1>; 3454 #size-cells = <0>; 3455 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3456 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3457 <&gcc GCC_QSPI_CORE_CLK>; 3458 clock-names = "iface", "core"; 3459 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3460 &cnoc2 SLAVE_QSPI_0 0>; 3461 interconnect-names = "qspi-config"; 3462 power-domains = <&rpmhpd SC7280_CX>; 3463 operating-points-v2 = <&qspi_opp_table>; 3464 status = "disabled"; 3465 }; 3466 3467 remoteproc_wpss: remoteproc@8a00000 { 3468 compatible = "qcom,sc7280-wpss-pil"; 3469 reg = <0 0x08a00000 0 0x10000>; 3470 3471 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3472 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3473 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3474 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3475 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3476 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3477 interrupt-names = "wdog", "fatal", "ready", "handover", 3478 "stop-ack", "shutdown-ack"; 3479 3480 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3481 <&gcc GCC_WPSS_AHB_CLK>, 3482 <&gcc GCC_WPSS_RSCP_CLK>, 3483 <&rpmhcc RPMH_CXO_CLK>; 3484 clock-names = "ahb_bdg", "ahb", 3485 "rscp", "xo"; 3486 3487 power-domains = <&rpmhpd SC7280_CX>, 3488 <&rpmhpd SC7280_MX>; 3489 power-domain-names = "cx", "mx"; 3490 3491 memory-region = <&wpss_mem>; 3492 3493 qcom,qmp = <&aoss_qmp>; 3494 3495 qcom,smem-states = <&wpss_smp2p_out 0>; 3496 qcom,smem-state-names = "stop"; 3497 3498 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3499 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3500 reset-names = "restart", "pdc_sync"; 3501 3502 qcom,halt-regs = <&tcsr_1 0x17000>; 3503 3504 status = "disabled"; 3505 3506 glink-edge { 3507 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3508 IPCC_MPROC_SIGNAL_GLINK_QMP 3509 IRQ_TYPE_EDGE_RISING>; 3510 mboxes = <&ipcc IPCC_CLIENT_WPSS 3511 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3512 3513 label = "wpss"; 3514 qcom,remote-pid = <13>; 3515 }; 3516 }; 3517 3518 pmu@9091000 { 3519 compatible = "qcom,sc7280-llcc-bwmon"; 3520 reg = <0 0x09091000 0 0x1000>; 3521 3522 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3523 3524 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3525 3526 operating-points-v2 = <&llcc_bwmon_opp_table>; 3527 3528 llcc_bwmon_opp_table: opp-table { 3529 compatible = "operating-points-v2"; 3530 3531 opp-0 { 3532 opp-peak-kBps = <800000>; 3533 }; 3534 opp-1 { 3535 opp-peak-kBps = <1804000>; 3536 }; 3537 opp-2 { 3538 opp-peak-kBps = <2188000>; 3539 }; 3540 opp-3 { 3541 opp-peak-kBps = <3072000>; 3542 }; 3543 opp-4 { 3544 opp-peak-kBps = <4068000>; 3545 }; 3546 opp-5 { 3547 opp-peak-kBps = <6220000>; 3548 }; 3549 opp-6 { 3550 opp-peak-kBps = <6832000>; 3551 }; 3552 opp-7 { 3553 opp-peak-kBps = <8532000>; 3554 }; 3555 }; 3556 }; 3557 3558 pmu@90b6400 { 3559 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3560 reg = <0 0x090b6400 0 0x600>; 3561 3562 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3563 3564 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3565 operating-points-v2 = <&cpu_bwmon_opp_table>; 3566 3567 cpu_bwmon_opp_table: opp-table { 3568 compatible = "operating-points-v2"; 3569 3570 opp-0 { 3571 opp-peak-kBps = <2400000>; 3572 }; 3573 opp-1 { 3574 opp-peak-kBps = <4800000>; 3575 }; 3576 opp-2 { 3577 opp-peak-kBps = <7456000>; 3578 }; 3579 opp-3 { 3580 opp-peak-kBps = <9600000>; 3581 }; 3582 opp-4 { 3583 opp-peak-kBps = <12896000>; 3584 }; 3585 opp-5 { 3586 opp-peak-kBps = <14928000>; 3587 }; 3588 opp-6 { 3589 opp-peak-kBps = <17056000>; 3590 }; 3591 }; 3592 }; 3593 3594 dc_noc: interconnect@90e0000 { 3595 reg = <0 0x090e0000 0 0x5080>; 3596 compatible = "qcom,sc7280-dc-noc"; 3597 #interconnect-cells = <2>; 3598 qcom,bcm-voters = <&apps_bcm_voter>; 3599 }; 3600 3601 gem_noc: interconnect@9100000 { 3602 reg = <0 0x09100000 0 0xe2200>; 3603 compatible = "qcom,sc7280-gem-noc"; 3604 #interconnect-cells = <2>; 3605 qcom,bcm-voters = <&apps_bcm_voter>; 3606 }; 3607 3608 system-cache-controller@9200000 { 3609 compatible = "qcom,sc7280-llcc"; 3610 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3611 <0 0x09600000 0 0x58000>; 3612 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3613 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3614 }; 3615 3616 eud: eud@88e0000 { 3617 compatible = "qcom,sc7280-eud", "qcom,eud"; 3618 reg = <0 0x88e0000 0 0x2000>, 3619 <0 0x88e2000 0 0x1000>; 3620 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3621 3622 status = "disabled"; 3623 3624 ports { 3625 #address-cells = <1>; 3626 #size-cells = <0>; 3627 3628 port@0 { 3629 reg = <0>; 3630 eud_ep: endpoint { 3631 remote-endpoint = <&usb2_role_switch>; 3632 }; 3633 }; 3634 }; 3635 }; 3636 3637 nsp_noc: interconnect@a0c0000 { 3638 reg = <0 0x0a0c0000 0 0x10000>; 3639 compatible = "qcom,sc7280-nsp-noc"; 3640 #interconnect-cells = <2>; 3641 qcom,bcm-voters = <&apps_bcm_voter>; 3642 }; 3643 3644 usb_1: usb@a6f8800 { 3645 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3646 reg = <0 0x0a6f8800 0 0x400>; 3647 status = "disabled"; 3648 #address-cells = <2>; 3649 #size-cells = <2>; 3650 ranges; 3651 dma-ranges; 3652 3653 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3654 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3655 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3656 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3657 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3658 clock-names = "cfg_noc", 3659 "core", 3660 "iface", 3661 "sleep", 3662 "mock_utmi"; 3663 3664 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3665 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3666 assigned-clock-rates = <19200000>, <200000000>; 3667 3668 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3669 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3670 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3671 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3672 interrupt-names = "hs_phy_irq", 3673 "dp_hs_phy_irq", 3674 "dm_hs_phy_irq", 3675 "ss_phy_irq"; 3676 3677 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3678 required-opps = <&rpmhpd_opp_nom>; 3679 3680 resets = <&gcc GCC_USB30_PRIM_BCR>; 3681 3682 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3683 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3684 interconnect-names = "usb-ddr", "apps-usb"; 3685 3686 wakeup-source; 3687 3688 usb_1_dwc3: usb@a600000 { 3689 compatible = "snps,dwc3"; 3690 reg = <0 0x0a600000 0 0xe000>; 3691 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3692 iommus = <&apps_smmu 0xe0 0x0>; 3693 snps,dis_u2_susphy_quirk; 3694 snps,dis_enblslpm_quirk; 3695 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3696 phy-names = "usb2-phy", "usb3-phy"; 3697 maximum-speed = "super-speed"; 3698 }; 3699 }; 3700 3701 venus: video-codec@aa00000 { 3702 compatible = "qcom,sc7280-venus"; 3703 reg = <0 0x0aa00000 0 0xd0600>; 3704 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3705 3706 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3707 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3708 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3709 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3710 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3711 clock-names = "core", "bus", "iface", 3712 "vcodec_core", "vcodec_bus"; 3713 3714 power-domains = <&videocc MVSC_GDSC>, 3715 <&videocc MVS0_GDSC>, 3716 <&rpmhpd SC7280_CX>; 3717 power-domain-names = "venus", "vcodec0", "cx"; 3718 operating-points-v2 = <&venus_opp_table>; 3719 3720 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3721 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3722 interconnect-names = "cpu-cfg", "video-mem"; 3723 3724 iommus = <&apps_smmu 0x2180 0x20>, 3725 <&apps_smmu 0x2184 0x20>; 3726 memory-region = <&video_mem>; 3727 3728 video-decoder { 3729 compatible = "venus-decoder"; 3730 }; 3731 3732 video-encoder { 3733 compatible = "venus-encoder"; 3734 }; 3735 3736 video-firmware { 3737 iommus = <&apps_smmu 0x21a2 0x0>; 3738 }; 3739 3740 venus_opp_table: opp-table { 3741 compatible = "operating-points-v2"; 3742 3743 opp-133330000 { 3744 opp-hz = /bits/ 64 <133330000>; 3745 required-opps = <&rpmhpd_opp_low_svs>; 3746 }; 3747 3748 opp-240000000 { 3749 opp-hz = /bits/ 64 <240000000>; 3750 required-opps = <&rpmhpd_opp_svs>; 3751 }; 3752 3753 opp-335000000 { 3754 opp-hz = /bits/ 64 <335000000>; 3755 required-opps = <&rpmhpd_opp_svs_l1>; 3756 }; 3757 3758 opp-424000000 { 3759 opp-hz = /bits/ 64 <424000000>; 3760 required-opps = <&rpmhpd_opp_nom>; 3761 }; 3762 3763 opp-460000048 { 3764 opp-hz = /bits/ 64 <460000048>; 3765 required-opps = <&rpmhpd_opp_turbo>; 3766 }; 3767 }; 3768 }; 3769 3770 videocc: clock-controller@aaf0000 { 3771 compatible = "qcom,sc7280-videocc"; 3772 reg = <0 0x0aaf0000 0 0x10000>; 3773 clocks = <&rpmhcc RPMH_CXO_CLK>, 3774 <&rpmhcc RPMH_CXO_CLK_A>; 3775 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3776 #clock-cells = <1>; 3777 #reset-cells = <1>; 3778 #power-domain-cells = <1>; 3779 }; 3780 3781 camcc: clock-controller@ad00000 { 3782 compatible = "qcom,sc7280-camcc"; 3783 reg = <0 0x0ad00000 0 0x10000>; 3784 clocks = <&rpmhcc RPMH_CXO_CLK>, 3785 <&rpmhcc RPMH_CXO_CLK_A>, 3786 <&sleep_clk>; 3787 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3788 #clock-cells = <1>; 3789 #reset-cells = <1>; 3790 #power-domain-cells = <1>; 3791 }; 3792 3793 dispcc: clock-controller@af00000 { 3794 compatible = "qcom,sc7280-dispcc"; 3795 reg = <0 0x0af00000 0 0x20000>; 3796 clocks = <&rpmhcc RPMH_CXO_CLK>, 3797 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3798 <&mdss_dsi_phy 0>, 3799 <&mdss_dsi_phy 1>, 3800 <&dp_phy 0>, 3801 <&dp_phy 1>, 3802 <&mdss_edp_phy 0>, 3803 <&mdss_edp_phy 1>; 3804 clock-names = "bi_tcxo", 3805 "gcc_disp_gpll0_clk", 3806 "dsi0_phy_pll_out_byteclk", 3807 "dsi0_phy_pll_out_dsiclk", 3808 "dp_phy_pll_link_clk", 3809 "dp_phy_pll_vco_div_clk", 3810 "edp_phy_pll_link_clk", 3811 "edp_phy_pll_vco_div_clk"; 3812 #clock-cells = <1>; 3813 #reset-cells = <1>; 3814 #power-domain-cells = <1>; 3815 }; 3816 3817 mdss: display-subsystem@ae00000 { 3818 compatible = "qcom,sc7280-mdss"; 3819 reg = <0 0x0ae00000 0 0x1000>; 3820 reg-names = "mdss"; 3821 3822 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3823 3824 clocks = <&gcc GCC_DISP_AHB_CLK>, 3825 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3826 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3827 clock-names = "iface", 3828 "ahb", 3829 "core"; 3830 3831 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3832 interrupt-controller; 3833 #interrupt-cells = <1>; 3834 3835 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3836 interconnect-names = "mdp0-mem"; 3837 3838 iommus = <&apps_smmu 0x900 0x402>; 3839 3840 #address-cells = <2>; 3841 #size-cells = <2>; 3842 ranges; 3843 3844 status = "disabled"; 3845 3846 mdss_mdp: display-controller@ae01000 { 3847 compatible = "qcom,sc7280-dpu"; 3848 reg = <0 0x0ae01000 0 0x8f030>, 3849 <0 0x0aeb0000 0 0x2008>; 3850 reg-names = "mdp", "vbif"; 3851 3852 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3853 <&gcc GCC_DISP_SF_AXI_CLK>, 3854 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3855 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3856 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3857 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3858 clock-names = "bus", 3859 "nrt_bus", 3860 "iface", 3861 "lut", 3862 "core", 3863 "vsync"; 3864 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3865 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3866 assigned-clock-rates = <19200000>, 3867 <19200000>; 3868 operating-points-v2 = <&mdp_opp_table>; 3869 power-domains = <&rpmhpd SC7280_CX>; 3870 3871 interrupt-parent = <&mdss>; 3872 interrupts = <0>; 3873 3874 ports { 3875 #address-cells = <1>; 3876 #size-cells = <0>; 3877 3878 port@0 { 3879 reg = <0>; 3880 dpu_intf1_out: endpoint { 3881 remote-endpoint = <&mdss_dsi0_in>; 3882 }; 3883 }; 3884 3885 port@1 { 3886 reg = <1>; 3887 dpu_intf5_out: endpoint { 3888 remote-endpoint = <&edp_in>; 3889 }; 3890 }; 3891 3892 port@2 { 3893 reg = <2>; 3894 dpu_intf0_out: endpoint { 3895 remote-endpoint = <&dp_in>; 3896 }; 3897 }; 3898 }; 3899 3900 mdp_opp_table: opp-table { 3901 compatible = "operating-points-v2"; 3902 3903 opp-200000000 { 3904 opp-hz = /bits/ 64 <200000000>; 3905 required-opps = <&rpmhpd_opp_low_svs>; 3906 }; 3907 3908 opp-300000000 { 3909 opp-hz = /bits/ 64 <300000000>; 3910 required-opps = <&rpmhpd_opp_svs>; 3911 }; 3912 3913 opp-380000000 { 3914 opp-hz = /bits/ 64 <380000000>; 3915 required-opps = <&rpmhpd_opp_svs_l1>; 3916 }; 3917 3918 opp-506666667 { 3919 opp-hz = /bits/ 64 <506666667>; 3920 required-opps = <&rpmhpd_opp_nom>; 3921 }; 3922 }; 3923 }; 3924 3925 mdss_dsi: dsi@ae94000 { 3926 compatible = "qcom,sc7280-dsi-ctrl", 3927 "qcom,mdss-dsi-ctrl"; 3928 reg = <0 0x0ae94000 0 0x400>; 3929 reg-names = "dsi_ctrl"; 3930 3931 interrupt-parent = <&mdss>; 3932 interrupts = <4>; 3933 3934 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3935 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3936 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3937 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3938 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3939 <&gcc GCC_DISP_HF_AXI_CLK>; 3940 clock-names = "byte", 3941 "byte_intf", 3942 "pixel", 3943 "core", 3944 "iface", 3945 "bus"; 3946 3947 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3948 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3949 3950 operating-points-v2 = <&dsi_opp_table>; 3951 power-domains = <&rpmhpd SC7280_CX>; 3952 3953 phys = <&mdss_dsi_phy>; 3954 3955 #address-cells = <1>; 3956 #size-cells = <0>; 3957 3958 status = "disabled"; 3959 3960 ports { 3961 #address-cells = <1>; 3962 #size-cells = <0>; 3963 3964 port@0 { 3965 reg = <0>; 3966 mdss_dsi0_in: endpoint { 3967 remote-endpoint = <&dpu_intf1_out>; 3968 }; 3969 }; 3970 3971 port@1 { 3972 reg = <1>; 3973 mdss_dsi0_out: endpoint { 3974 }; 3975 }; 3976 }; 3977 3978 dsi_opp_table: opp-table { 3979 compatible = "operating-points-v2"; 3980 3981 opp-187500000 { 3982 opp-hz = /bits/ 64 <187500000>; 3983 required-opps = <&rpmhpd_opp_low_svs>; 3984 }; 3985 3986 opp-300000000 { 3987 opp-hz = /bits/ 64 <300000000>; 3988 required-opps = <&rpmhpd_opp_svs>; 3989 }; 3990 3991 opp-358000000 { 3992 opp-hz = /bits/ 64 <358000000>; 3993 required-opps = <&rpmhpd_opp_svs_l1>; 3994 }; 3995 }; 3996 }; 3997 3998 mdss_dsi_phy: phy@ae94400 { 3999 compatible = "qcom,sc7280-dsi-phy-7nm"; 4000 reg = <0 0x0ae94400 0 0x200>, 4001 <0 0x0ae94600 0 0x280>, 4002 <0 0x0ae94900 0 0x280>; 4003 reg-names = "dsi_phy", 4004 "dsi_phy_lane", 4005 "dsi_pll"; 4006 4007 #clock-cells = <1>; 4008 #phy-cells = <0>; 4009 4010 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4011 <&rpmhcc RPMH_CXO_CLK>; 4012 clock-names = "iface", "ref"; 4013 4014 status = "disabled"; 4015 }; 4016 4017 mdss_edp: edp@aea0000 { 4018 compatible = "qcom,sc7280-edp"; 4019 pinctrl-names = "default"; 4020 pinctrl-0 = <&edp_hot_plug_det>; 4021 4022 reg = <0 0x0aea0000 0 0x200>, 4023 <0 0x0aea0200 0 0x200>, 4024 <0 0x0aea0400 0 0xc00>, 4025 <0 0x0aea1000 0 0x400>; 4026 4027 interrupt-parent = <&mdss>; 4028 interrupts = <14>; 4029 4030 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4031 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4032 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4033 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4034 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4035 clock-names = "core_iface", 4036 "core_aux", 4037 "ctrl_link", 4038 "ctrl_link_iface", 4039 "stream_pixel"; 4040 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4041 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4042 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4043 4044 phys = <&mdss_edp_phy>; 4045 phy-names = "dp"; 4046 4047 operating-points-v2 = <&edp_opp_table>; 4048 power-domains = <&rpmhpd SC7280_CX>; 4049 4050 status = "disabled"; 4051 4052 ports { 4053 #address-cells = <1>; 4054 #size-cells = <0>; 4055 4056 port@0 { 4057 reg = <0>; 4058 edp_in: endpoint { 4059 remote-endpoint = <&dpu_intf5_out>; 4060 }; 4061 }; 4062 4063 port@1 { 4064 reg = <1>; 4065 mdss_edp_out: endpoint { }; 4066 }; 4067 }; 4068 4069 edp_opp_table: opp-table { 4070 compatible = "operating-points-v2"; 4071 4072 opp-160000000 { 4073 opp-hz = /bits/ 64 <160000000>; 4074 required-opps = <&rpmhpd_opp_low_svs>; 4075 }; 4076 4077 opp-270000000 { 4078 opp-hz = /bits/ 64 <270000000>; 4079 required-opps = <&rpmhpd_opp_svs>; 4080 }; 4081 4082 opp-540000000 { 4083 opp-hz = /bits/ 64 <540000000>; 4084 required-opps = <&rpmhpd_opp_nom>; 4085 }; 4086 4087 opp-810000000 { 4088 opp-hz = /bits/ 64 <810000000>; 4089 required-opps = <&rpmhpd_opp_nom>; 4090 }; 4091 }; 4092 }; 4093 4094 mdss_edp_phy: phy@aec2a00 { 4095 compatible = "qcom,sc7280-edp-phy"; 4096 4097 reg = <0 0x0aec2a00 0 0x19c>, 4098 <0 0x0aec2200 0 0xa0>, 4099 <0 0x0aec2600 0 0xa0>, 4100 <0 0x0aec2000 0 0x1c0>; 4101 4102 clocks = <&rpmhcc RPMH_CXO_CLK>, 4103 <&gcc GCC_EDP_CLKREF_EN>; 4104 clock-names = "aux", 4105 "cfg_ahb"; 4106 4107 #clock-cells = <1>; 4108 #phy-cells = <0>; 4109 4110 status = "disabled"; 4111 }; 4112 4113 mdss_dp: displayport-controller@ae90000 { 4114 compatible = "qcom,sc7280-dp"; 4115 4116 reg = <0 0x0ae90000 0 0x200>, 4117 <0 0x0ae90200 0 0x200>, 4118 <0 0x0ae90400 0 0xc00>, 4119 <0 0x0ae91000 0 0x400>, 4120 <0 0x0ae91400 0 0x400>; 4121 4122 interrupt-parent = <&mdss>; 4123 interrupts = <12>; 4124 4125 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4126 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4127 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4128 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4129 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4130 clock-names = "core_iface", 4131 "core_aux", 4132 "ctrl_link", 4133 "ctrl_link_iface", 4134 "stream_pixel"; 4135 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4136 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4137 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4138 phys = <&dp_phy>; 4139 phy-names = "dp"; 4140 4141 operating-points-v2 = <&dp_opp_table>; 4142 power-domains = <&rpmhpd SC7280_CX>; 4143 4144 #sound-dai-cells = <0>; 4145 4146 status = "disabled"; 4147 4148 ports { 4149 #address-cells = <1>; 4150 #size-cells = <0>; 4151 4152 port@0 { 4153 reg = <0>; 4154 dp_in: endpoint { 4155 remote-endpoint = <&dpu_intf0_out>; 4156 }; 4157 }; 4158 4159 port@1 { 4160 reg = <1>; 4161 mdss_dp_out: endpoint { }; 4162 }; 4163 }; 4164 4165 dp_opp_table: opp-table { 4166 compatible = "operating-points-v2"; 4167 4168 opp-160000000 { 4169 opp-hz = /bits/ 64 <160000000>; 4170 required-opps = <&rpmhpd_opp_low_svs>; 4171 }; 4172 4173 opp-270000000 { 4174 opp-hz = /bits/ 64 <270000000>; 4175 required-opps = <&rpmhpd_opp_svs>; 4176 }; 4177 4178 opp-540000000 { 4179 opp-hz = /bits/ 64 <540000000>; 4180 required-opps = <&rpmhpd_opp_svs_l1>; 4181 }; 4182 4183 opp-810000000 { 4184 opp-hz = /bits/ 64 <810000000>; 4185 required-opps = <&rpmhpd_opp_nom>; 4186 }; 4187 }; 4188 }; 4189 }; 4190 4191 pdc: interrupt-controller@b220000 { 4192 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4193 reg = <0 0x0b220000 0 0x30000>; 4194 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4195 <55 306 4>, <59 312 3>, <62 374 2>, 4196 <64 434 2>, <66 438 3>, <69 86 1>, 4197 <70 520 54>, <124 609 31>, <155 63 1>, 4198 <156 716 12>; 4199 #interrupt-cells = <2>; 4200 interrupt-parent = <&intc>; 4201 interrupt-controller; 4202 }; 4203 4204 pdc_reset: reset-controller@b5e0000 { 4205 compatible = "qcom,sc7280-pdc-global"; 4206 reg = <0 0x0b5e0000 0 0x20000>; 4207 #reset-cells = <1>; 4208 status = "reserved"; /* Owned by firmware */ 4209 }; 4210 4211 tsens0: thermal-sensor@c263000 { 4212 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4213 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4214 <0 0x0c222000 0 0x1ff>; /* SROT */ 4215 #qcom,sensors = <15>; 4216 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4218 interrupt-names = "uplow","critical"; 4219 #thermal-sensor-cells = <1>; 4220 }; 4221 4222 tsens1: thermal-sensor@c265000 { 4223 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4224 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4225 <0 0x0c223000 0 0x1ff>; /* SROT */ 4226 #qcom,sensors = <12>; 4227 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4229 interrupt-names = "uplow","critical"; 4230 #thermal-sensor-cells = <1>; 4231 }; 4232 4233 aoss_reset: reset-controller@c2a0000 { 4234 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4235 reg = <0 0x0c2a0000 0 0x31000>; 4236 #reset-cells = <1>; 4237 }; 4238 4239 aoss_qmp: power-management@c300000 { 4240 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4241 reg = <0 0x0c300000 0 0x400>; 4242 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4243 IPCC_MPROC_SIGNAL_GLINK_QMP 4244 IRQ_TYPE_EDGE_RISING>; 4245 mboxes = <&ipcc IPCC_CLIENT_AOP 4246 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4247 4248 #clock-cells = <0>; 4249 }; 4250 4251 sram@c3f0000 { 4252 compatible = "qcom,rpmh-stats"; 4253 reg = <0 0x0c3f0000 0 0x400>; 4254 }; 4255 4256 spmi_bus: spmi@c440000 { 4257 compatible = "qcom,spmi-pmic-arb"; 4258 reg = <0 0x0c440000 0 0x1100>, 4259 <0 0x0c600000 0 0x2000000>, 4260 <0 0x0e600000 0 0x100000>, 4261 <0 0x0e700000 0 0xa0000>, 4262 <0 0x0c40a000 0 0x26000>; 4263 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4264 interrupt-names = "periph_irq"; 4265 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4266 qcom,ee = <0>; 4267 qcom,channel = <0>; 4268 #address-cells = <2>; 4269 #size-cells = <0>; 4270 interrupt-controller; 4271 #interrupt-cells = <4>; 4272 }; 4273 4274 tlmm: pinctrl@f100000 { 4275 compatible = "qcom,sc7280-pinctrl"; 4276 reg = <0 0x0f100000 0 0x300000>; 4277 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4278 gpio-controller; 4279 #gpio-cells = <2>; 4280 interrupt-controller; 4281 #interrupt-cells = <2>; 4282 gpio-ranges = <&tlmm 0 0 175>; 4283 wakeup-parent = <&pdc>; 4284 4285 dp_hot_plug_det: dp-hot-plug-det-state { 4286 pins = "gpio47"; 4287 function = "dp_hot"; 4288 }; 4289 4290 edp_hot_plug_det: edp-hot-plug-det-state { 4291 pins = "gpio60"; 4292 function = "edp_hot"; 4293 }; 4294 4295 mi2s0_data0: mi2s0-data0-state { 4296 pins = "gpio98"; 4297 function = "mi2s0_data0"; 4298 }; 4299 4300 mi2s0_data1: mi2s0-data1-state { 4301 pins = "gpio99"; 4302 function = "mi2s0_data1"; 4303 }; 4304 4305 mi2s0_mclk: mi2s0-mclk-state { 4306 pins = "gpio96"; 4307 function = "pri_mi2s"; 4308 }; 4309 4310 mi2s0_sclk: mi2s0-sclk-state { 4311 pins = "gpio97"; 4312 function = "mi2s0_sck"; 4313 }; 4314 4315 mi2s0_ws: mi2s0-ws-state { 4316 pins = "gpio100"; 4317 function = "mi2s0_ws"; 4318 }; 4319 4320 mi2s1_data0: mi2s1-data0-state { 4321 pins = "gpio107"; 4322 function = "mi2s1_data0"; 4323 }; 4324 4325 mi2s1_sclk: mi2s1-sclk-state { 4326 pins = "gpio106"; 4327 function = "mi2s1_sck"; 4328 }; 4329 4330 mi2s1_ws: mi2s1-ws-state { 4331 pins = "gpio108"; 4332 function = "mi2s1_ws"; 4333 }; 4334 4335 pcie1_clkreq_n: pcie1-clkreq-n-state { 4336 pins = "gpio79"; 4337 function = "pcie1_clkreqn"; 4338 }; 4339 4340 qspi_clk: qspi-clk-state { 4341 pins = "gpio14"; 4342 function = "qspi_clk"; 4343 }; 4344 4345 qspi_cs0: qspi-cs0-state { 4346 pins = "gpio15"; 4347 function = "qspi_cs"; 4348 }; 4349 4350 qspi_cs1: qspi-cs1-state { 4351 pins = "gpio19"; 4352 function = "qspi_cs"; 4353 }; 4354 4355 qspi_data0: qspi-data0-state { 4356 pins = "gpio12"; 4357 function = "qspi_data"; 4358 }; 4359 4360 qspi_data1: qspi-data1-state { 4361 pins = "gpio13"; 4362 function = "qspi_data"; 4363 }; 4364 4365 qspi_data23: qspi-data23-state { 4366 pins = "gpio16", "gpio17"; 4367 function = "qspi_data"; 4368 }; 4369 4370 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4371 pins = "gpio0", "gpio1"; 4372 function = "qup00"; 4373 }; 4374 4375 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4376 pins = "gpio4", "gpio5"; 4377 function = "qup01"; 4378 }; 4379 4380 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4381 pins = "gpio8", "gpio9"; 4382 function = "qup02"; 4383 }; 4384 4385 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4386 pins = "gpio12", "gpio13"; 4387 function = "qup03"; 4388 }; 4389 4390 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4391 pins = "gpio16", "gpio17"; 4392 function = "qup04"; 4393 }; 4394 4395 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4396 pins = "gpio20", "gpio21"; 4397 function = "qup05"; 4398 }; 4399 4400 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4401 pins = "gpio24", "gpio25"; 4402 function = "qup06"; 4403 }; 4404 4405 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4406 pins = "gpio28", "gpio29"; 4407 function = "qup07"; 4408 }; 4409 4410 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4411 pins = "gpio32", "gpio33"; 4412 function = "qup10"; 4413 }; 4414 4415 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4416 pins = "gpio36", "gpio37"; 4417 function = "qup11"; 4418 }; 4419 4420 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4421 pins = "gpio40", "gpio41"; 4422 function = "qup12"; 4423 }; 4424 4425 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4426 pins = "gpio44", "gpio45"; 4427 function = "qup13"; 4428 }; 4429 4430 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4431 pins = "gpio48", "gpio49"; 4432 function = "qup14"; 4433 }; 4434 4435 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4436 pins = "gpio52", "gpio53"; 4437 function = "qup15"; 4438 }; 4439 4440 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4441 pins = "gpio56", "gpio57"; 4442 function = "qup16"; 4443 }; 4444 4445 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4446 pins = "gpio60", "gpio61"; 4447 function = "qup17"; 4448 }; 4449 4450 qup_spi0_data_clk: qup-spi0-data-clk-state { 4451 pins = "gpio0", "gpio1", "gpio2"; 4452 function = "qup00"; 4453 }; 4454 4455 qup_spi0_cs: qup-spi0-cs-state { 4456 pins = "gpio3"; 4457 function = "qup00"; 4458 }; 4459 4460 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4461 pins = "gpio3"; 4462 function = "gpio"; 4463 }; 4464 4465 qup_spi1_data_clk: qup-spi1-data-clk-state { 4466 pins = "gpio4", "gpio5", "gpio6"; 4467 function = "qup01"; 4468 }; 4469 4470 qup_spi1_cs: qup-spi1-cs-state { 4471 pins = "gpio7"; 4472 function = "qup01"; 4473 }; 4474 4475 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4476 pins = "gpio7"; 4477 function = "gpio"; 4478 }; 4479 4480 qup_spi2_data_clk: qup-spi2-data-clk-state { 4481 pins = "gpio8", "gpio9", "gpio10"; 4482 function = "qup02"; 4483 }; 4484 4485 qup_spi2_cs: qup-spi2-cs-state { 4486 pins = "gpio11"; 4487 function = "qup02"; 4488 }; 4489 4490 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4491 pins = "gpio11"; 4492 function = "gpio"; 4493 }; 4494 4495 qup_spi3_data_clk: qup-spi3-data-clk-state { 4496 pins = "gpio12", "gpio13", "gpio14"; 4497 function = "qup03"; 4498 }; 4499 4500 qup_spi3_cs: qup-spi3-cs-state { 4501 pins = "gpio15"; 4502 function = "qup03"; 4503 }; 4504 4505 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4506 pins = "gpio15"; 4507 function = "gpio"; 4508 }; 4509 4510 qup_spi4_data_clk: qup-spi4-data-clk-state { 4511 pins = "gpio16", "gpio17", "gpio18"; 4512 function = "qup04"; 4513 }; 4514 4515 qup_spi4_cs: qup-spi4-cs-state { 4516 pins = "gpio19"; 4517 function = "qup04"; 4518 }; 4519 4520 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4521 pins = "gpio19"; 4522 function = "gpio"; 4523 }; 4524 4525 qup_spi5_data_clk: qup-spi5-data-clk-state { 4526 pins = "gpio20", "gpio21", "gpio22"; 4527 function = "qup05"; 4528 }; 4529 4530 qup_spi5_cs: qup-spi5-cs-state { 4531 pins = "gpio23"; 4532 function = "qup05"; 4533 }; 4534 4535 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4536 pins = "gpio23"; 4537 function = "gpio"; 4538 }; 4539 4540 qup_spi6_data_clk: qup-spi6-data-clk-state { 4541 pins = "gpio24", "gpio25", "gpio26"; 4542 function = "qup06"; 4543 }; 4544 4545 qup_spi6_cs: qup-spi6-cs-state { 4546 pins = "gpio27"; 4547 function = "qup06"; 4548 }; 4549 4550 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4551 pins = "gpio27"; 4552 function = "gpio"; 4553 }; 4554 4555 qup_spi7_data_clk: qup-spi7-data-clk-state { 4556 pins = "gpio28", "gpio29", "gpio30"; 4557 function = "qup07"; 4558 }; 4559 4560 qup_spi7_cs: qup-spi7-cs-state { 4561 pins = "gpio31"; 4562 function = "qup07"; 4563 }; 4564 4565 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4566 pins = "gpio31"; 4567 function = "gpio"; 4568 }; 4569 4570 qup_spi8_data_clk: qup-spi8-data-clk-state { 4571 pins = "gpio32", "gpio33", "gpio34"; 4572 function = "qup10"; 4573 }; 4574 4575 qup_spi8_cs: qup-spi8-cs-state { 4576 pins = "gpio35"; 4577 function = "qup10"; 4578 }; 4579 4580 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4581 pins = "gpio35"; 4582 function = "gpio"; 4583 }; 4584 4585 qup_spi9_data_clk: qup-spi9-data-clk-state { 4586 pins = "gpio36", "gpio37", "gpio38"; 4587 function = "qup11"; 4588 }; 4589 4590 qup_spi9_cs: qup-spi9-cs-state { 4591 pins = "gpio39"; 4592 function = "qup11"; 4593 }; 4594 4595 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4596 pins = "gpio39"; 4597 function = "gpio"; 4598 }; 4599 4600 qup_spi10_data_clk: qup-spi10-data-clk-state { 4601 pins = "gpio40", "gpio41", "gpio42"; 4602 function = "qup12"; 4603 }; 4604 4605 qup_spi10_cs: qup-spi10-cs-state { 4606 pins = "gpio43"; 4607 function = "qup12"; 4608 }; 4609 4610 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4611 pins = "gpio43"; 4612 function = "gpio"; 4613 }; 4614 4615 qup_spi11_data_clk: qup-spi11-data-clk-state { 4616 pins = "gpio44", "gpio45", "gpio46"; 4617 function = "qup13"; 4618 }; 4619 4620 qup_spi11_cs: qup-spi11-cs-state { 4621 pins = "gpio47"; 4622 function = "qup13"; 4623 }; 4624 4625 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4626 pins = "gpio47"; 4627 function = "gpio"; 4628 }; 4629 4630 qup_spi12_data_clk: qup-spi12-data-clk-state { 4631 pins = "gpio48", "gpio49", "gpio50"; 4632 function = "qup14"; 4633 }; 4634 4635 qup_spi12_cs: qup-spi12-cs-state { 4636 pins = "gpio51"; 4637 function = "qup14"; 4638 }; 4639 4640 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4641 pins = "gpio51"; 4642 function = "gpio"; 4643 }; 4644 4645 qup_spi13_data_clk: qup-spi13-data-clk-state { 4646 pins = "gpio52", "gpio53", "gpio54"; 4647 function = "qup15"; 4648 }; 4649 4650 qup_spi13_cs: qup-spi13-cs-state { 4651 pins = "gpio55"; 4652 function = "qup15"; 4653 }; 4654 4655 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4656 pins = "gpio55"; 4657 function = "gpio"; 4658 }; 4659 4660 qup_spi14_data_clk: qup-spi14-data-clk-state { 4661 pins = "gpio56", "gpio57", "gpio58"; 4662 function = "qup16"; 4663 }; 4664 4665 qup_spi14_cs: qup-spi14-cs-state { 4666 pins = "gpio59"; 4667 function = "qup16"; 4668 }; 4669 4670 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4671 pins = "gpio59"; 4672 function = "gpio"; 4673 }; 4674 4675 qup_spi15_data_clk: qup-spi15-data-clk-state { 4676 pins = "gpio60", "gpio61", "gpio62"; 4677 function = "qup17"; 4678 }; 4679 4680 qup_spi15_cs: qup-spi15-cs-state { 4681 pins = "gpio63"; 4682 function = "qup17"; 4683 }; 4684 4685 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4686 pins = "gpio63"; 4687 function = "gpio"; 4688 }; 4689 4690 qup_uart0_cts: qup-uart0-cts-state { 4691 pins = "gpio0"; 4692 function = "qup00"; 4693 }; 4694 4695 qup_uart0_rts: qup-uart0-rts-state { 4696 pins = "gpio1"; 4697 function = "qup00"; 4698 }; 4699 4700 qup_uart0_tx: qup-uart0-tx-state { 4701 pins = "gpio2"; 4702 function = "qup00"; 4703 }; 4704 4705 qup_uart0_rx: qup-uart0-rx-state { 4706 pins = "gpio3"; 4707 function = "qup00"; 4708 }; 4709 4710 qup_uart1_cts: qup-uart1-cts-state { 4711 pins = "gpio4"; 4712 function = "qup01"; 4713 }; 4714 4715 qup_uart1_rts: qup-uart1-rts-state { 4716 pins = "gpio5"; 4717 function = "qup01"; 4718 }; 4719 4720 qup_uart1_tx: qup-uart1-tx-state { 4721 pins = "gpio6"; 4722 function = "qup01"; 4723 }; 4724 4725 qup_uart1_rx: qup-uart1-rx-state { 4726 pins = "gpio7"; 4727 function = "qup01"; 4728 }; 4729 4730 qup_uart2_cts: qup-uart2-cts-state { 4731 pins = "gpio8"; 4732 function = "qup02"; 4733 }; 4734 4735 qup_uart2_rts: qup-uart2-rts-state { 4736 pins = "gpio9"; 4737 function = "qup02"; 4738 }; 4739 4740 qup_uart2_tx: qup-uart2-tx-state { 4741 pins = "gpio10"; 4742 function = "qup02"; 4743 }; 4744 4745 qup_uart2_rx: qup-uart2-rx-state { 4746 pins = "gpio11"; 4747 function = "qup02"; 4748 }; 4749 4750 qup_uart3_cts: qup-uart3-cts-state { 4751 pins = "gpio12"; 4752 function = "qup03"; 4753 }; 4754 4755 qup_uart3_rts: qup-uart3-rts-state { 4756 pins = "gpio13"; 4757 function = "qup03"; 4758 }; 4759 4760 qup_uart3_tx: qup-uart3-tx-state { 4761 pins = "gpio14"; 4762 function = "qup03"; 4763 }; 4764 4765 qup_uart3_rx: qup-uart3-rx-state { 4766 pins = "gpio15"; 4767 function = "qup03"; 4768 }; 4769 4770 qup_uart4_cts: qup-uart4-cts-state { 4771 pins = "gpio16"; 4772 function = "qup04"; 4773 }; 4774 4775 qup_uart4_rts: qup-uart4-rts-state { 4776 pins = "gpio17"; 4777 function = "qup04"; 4778 }; 4779 4780 qup_uart4_tx: qup-uart4-tx-state { 4781 pins = "gpio18"; 4782 function = "qup04"; 4783 }; 4784 4785 qup_uart4_rx: qup-uart4-rx-state { 4786 pins = "gpio19"; 4787 function = "qup04"; 4788 }; 4789 4790 qup_uart5_cts: qup-uart5-cts-state { 4791 pins = "gpio20"; 4792 function = "qup05"; 4793 }; 4794 4795 qup_uart5_rts: qup-uart5-rts-state { 4796 pins = "gpio21"; 4797 function = "qup05"; 4798 }; 4799 4800 qup_uart5_tx: qup-uart5-tx-state { 4801 pins = "gpio22"; 4802 function = "qup05"; 4803 }; 4804 4805 qup_uart5_rx: qup-uart5-rx-state { 4806 pins = "gpio23"; 4807 function = "qup05"; 4808 }; 4809 4810 qup_uart6_cts: qup-uart6-cts-state { 4811 pins = "gpio24"; 4812 function = "qup06"; 4813 }; 4814 4815 qup_uart6_rts: qup-uart6-rts-state { 4816 pins = "gpio25"; 4817 function = "qup06"; 4818 }; 4819 4820 qup_uart6_tx: qup-uart6-tx-state { 4821 pins = "gpio26"; 4822 function = "qup06"; 4823 }; 4824 4825 qup_uart6_rx: qup-uart6-rx-state { 4826 pins = "gpio27"; 4827 function = "qup06"; 4828 }; 4829 4830 qup_uart7_cts: qup-uart7-cts-state { 4831 pins = "gpio28"; 4832 function = "qup07"; 4833 }; 4834 4835 qup_uart7_rts: qup-uart7-rts-state { 4836 pins = "gpio29"; 4837 function = "qup07"; 4838 }; 4839 4840 qup_uart7_tx: qup-uart7-tx-state { 4841 pins = "gpio30"; 4842 function = "qup07"; 4843 }; 4844 4845 qup_uart7_rx: qup-uart7-rx-state { 4846 pins = "gpio31"; 4847 function = "qup07"; 4848 }; 4849 4850 qup_uart8_cts: qup-uart8-cts-state { 4851 pins = "gpio32"; 4852 function = "qup10"; 4853 }; 4854 4855 qup_uart8_rts: qup-uart8-rts-state { 4856 pins = "gpio33"; 4857 function = "qup10"; 4858 }; 4859 4860 qup_uart8_tx: qup-uart8-tx-state { 4861 pins = "gpio34"; 4862 function = "qup10"; 4863 }; 4864 4865 qup_uart8_rx: qup-uart8-rx-state { 4866 pins = "gpio35"; 4867 function = "qup10"; 4868 }; 4869 4870 qup_uart9_cts: qup-uart9-cts-state { 4871 pins = "gpio36"; 4872 function = "qup11"; 4873 }; 4874 4875 qup_uart9_rts: qup-uart9-rts-state { 4876 pins = "gpio37"; 4877 function = "qup11"; 4878 }; 4879 4880 qup_uart9_tx: qup-uart9-tx-state { 4881 pins = "gpio38"; 4882 function = "qup11"; 4883 }; 4884 4885 qup_uart9_rx: qup-uart9-rx-state { 4886 pins = "gpio39"; 4887 function = "qup11"; 4888 }; 4889 4890 qup_uart10_cts: qup-uart10-cts-state { 4891 pins = "gpio40"; 4892 function = "qup12"; 4893 }; 4894 4895 qup_uart10_rts: qup-uart10-rts-state { 4896 pins = "gpio41"; 4897 function = "qup12"; 4898 }; 4899 4900 qup_uart10_tx: qup-uart10-tx-state { 4901 pins = "gpio42"; 4902 function = "qup12"; 4903 }; 4904 4905 qup_uart10_rx: qup-uart10-rx-state { 4906 pins = "gpio43"; 4907 function = "qup12"; 4908 }; 4909 4910 qup_uart11_cts: qup-uart11-cts-state { 4911 pins = "gpio44"; 4912 function = "qup13"; 4913 }; 4914 4915 qup_uart11_rts: qup-uart11-rts-state { 4916 pins = "gpio45"; 4917 function = "qup13"; 4918 }; 4919 4920 qup_uart11_tx: qup-uart11-tx-state { 4921 pins = "gpio46"; 4922 function = "qup13"; 4923 }; 4924 4925 qup_uart11_rx: qup-uart11-rx-state { 4926 pins = "gpio47"; 4927 function = "qup13"; 4928 }; 4929 4930 qup_uart12_cts: qup-uart12-cts-state { 4931 pins = "gpio48"; 4932 function = "qup14"; 4933 }; 4934 4935 qup_uart12_rts: qup-uart12-rts-state { 4936 pins = "gpio49"; 4937 function = "qup14"; 4938 }; 4939 4940 qup_uart12_tx: qup-uart12-tx-state { 4941 pins = "gpio50"; 4942 function = "qup14"; 4943 }; 4944 4945 qup_uart12_rx: qup-uart12-rx-state { 4946 pins = "gpio51"; 4947 function = "qup14"; 4948 }; 4949 4950 qup_uart13_cts: qup-uart13-cts-state { 4951 pins = "gpio52"; 4952 function = "qup15"; 4953 }; 4954 4955 qup_uart13_rts: qup-uart13-rts-state { 4956 pins = "gpio53"; 4957 function = "qup15"; 4958 }; 4959 4960 qup_uart13_tx: qup-uart13-tx-state { 4961 pins = "gpio54"; 4962 function = "qup15"; 4963 }; 4964 4965 qup_uart13_rx: qup-uart13-rx-state { 4966 pins = "gpio55"; 4967 function = "qup15"; 4968 }; 4969 4970 qup_uart14_cts: qup-uart14-cts-state { 4971 pins = "gpio56"; 4972 function = "qup16"; 4973 }; 4974 4975 qup_uart14_rts: qup-uart14-rts-state { 4976 pins = "gpio57"; 4977 function = "qup16"; 4978 }; 4979 4980 qup_uart14_tx: qup-uart14-tx-state { 4981 pins = "gpio58"; 4982 function = "qup16"; 4983 }; 4984 4985 qup_uart14_rx: qup-uart14-rx-state { 4986 pins = "gpio59"; 4987 function = "qup16"; 4988 }; 4989 4990 qup_uart15_cts: qup-uart15-cts-state { 4991 pins = "gpio60"; 4992 function = "qup17"; 4993 }; 4994 4995 qup_uart15_rts: qup-uart15-rts-state { 4996 pins = "gpio61"; 4997 function = "qup17"; 4998 }; 4999 5000 qup_uart15_tx: qup-uart15-tx-state { 5001 pins = "gpio62"; 5002 function = "qup17"; 5003 }; 5004 5005 qup_uart15_rx: qup-uart15-rx-state { 5006 pins = "gpio63"; 5007 function = "qup17"; 5008 }; 5009 5010 sdc1_clk: sdc1-clk-state { 5011 pins = "sdc1_clk"; 5012 }; 5013 5014 sdc1_cmd: sdc1-cmd-state { 5015 pins = "sdc1_cmd"; 5016 }; 5017 5018 sdc1_data: sdc1-data-state { 5019 pins = "sdc1_data"; 5020 }; 5021 5022 sdc1_rclk: sdc1-rclk-state { 5023 pins = "sdc1_rclk"; 5024 }; 5025 5026 sdc1_clk_sleep: sdc1-clk-sleep-state { 5027 pins = "sdc1_clk"; 5028 drive-strength = <2>; 5029 bias-bus-hold; 5030 }; 5031 5032 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5033 pins = "sdc1_cmd"; 5034 drive-strength = <2>; 5035 bias-bus-hold; 5036 }; 5037 5038 sdc1_data_sleep: sdc1-data-sleep-state { 5039 pins = "sdc1_data"; 5040 drive-strength = <2>; 5041 bias-bus-hold; 5042 }; 5043 5044 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5045 pins = "sdc1_rclk"; 5046 drive-strength = <2>; 5047 bias-bus-hold; 5048 }; 5049 5050 sdc2_clk: sdc2-clk-state { 5051 pins = "sdc2_clk"; 5052 }; 5053 5054 sdc2_cmd: sdc2-cmd-state { 5055 pins = "sdc2_cmd"; 5056 }; 5057 5058 sdc2_data: sdc2-data-state { 5059 pins = "sdc2_data"; 5060 }; 5061 5062 sdc2_clk_sleep: sdc2-clk-sleep-state { 5063 pins = "sdc2_clk"; 5064 drive-strength = <2>; 5065 bias-bus-hold; 5066 }; 5067 5068 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5069 pins = "sdc2_cmd"; 5070 drive-strength = <2>; 5071 bias-bus-hold; 5072 }; 5073 5074 sdc2_data_sleep: sdc2-data-sleep-state { 5075 pins = "sdc2_data"; 5076 drive-strength = <2>; 5077 bias-bus-hold; 5078 }; 5079 }; 5080 5081 sram@146a5000 { 5082 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5083 reg = <0 0x146a5000 0 0x6000>; 5084 5085 #address-cells = <1>; 5086 #size-cells = <1>; 5087 5088 ranges = <0 0 0x146a5000 0x6000>; 5089 5090 pil-reloc@594c { 5091 compatible = "qcom,pil-reloc-info"; 5092 reg = <0x594c 0xc8>; 5093 }; 5094 }; 5095 5096 apps_smmu: iommu@15000000 { 5097 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5098 reg = <0 0x15000000 0 0x100000>; 5099 #iommu-cells = <2>; 5100 #global-interrupts = <1>; 5101 dma-coherent; 5102 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5183 }; 5184 5185 intc: interrupt-controller@17a00000 { 5186 compatible = "arm,gic-v3"; 5187 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5188 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5189 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5190 #interrupt-cells = <3>; 5191 interrupt-controller; 5192 #address-cells = <2>; 5193 #size-cells = <2>; 5194 ranges; 5195 5196 msi-controller@17a40000 { 5197 compatible = "arm,gic-v3-its"; 5198 reg = <0 0x17a40000 0 0x20000>; 5199 msi-controller; 5200 #msi-cells = <1>; 5201 status = "disabled"; 5202 }; 5203 }; 5204 5205 watchdog: watchdog@17c10000 { 5206 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5207 reg = <0 0x17c10000 0 0x1000>; 5208 clocks = <&sleep_clk>; 5209 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5210 status = "reserved"; /* Owned by Gunyah hyp */ 5211 }; 5212 5213 timer@17c20000 { 5214 #address-cells = <1>; 5215 #size-cells = <1>; 5216 ranges = <0 0 0 0x20000000>; 5217 compatible = "arm,armv7-timer-mem"; 5218 reg = <0 0x17c20000 0 0x1000>; 5219 5220 frame@17c21000 { 5221 frame-number = <0>; 5222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5223 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5224 reg = <0x17c21000 0x1000>, 5225 <0x17c22000 0x1000>; 5226 }; 5227 5228 frame@17c23000 { 5229 frame-number = <1>; 5230 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5231 reg = <0x17c23000 0x1000>; 5232 status = "disabled"; 5233 }; 5234 5235 frame@17c25000 { 5236 frame-number = <2>; 5237 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5238 reg = <0x17c25000 0x1000>; 5239 status = "disabled"; 5240 }; 5241 5242 frame@17c27000 { 5243 frame-number = <3>; 5244 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5245 reg = <0x17c27000 0x1000>; 5246 status = "disabled"; 5247 }; 5248 5249 frame@17c29000 { 5250 frame-number = <4>; 5251 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5252 reg = <0x17c29000 0x1000>; 5253 status = "disabled"; 5254 }; 5255 5256 frame@17c2b000 { 5257 frame-number = <5>; 5258 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5259 reg = <0x17c2b000 0x1000>; 5260 status = "disabled"; 5261 }; 5262 5263 frame@17c2d000 { 5264 frame-number = <6>; 5265 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5266 reg = <0x17c2d000 0x1000>; 5267 status = "disabled"; 5268 }; 5269 }; 5270 5271 apps_rsc: rsc@18200000 { 5272 compatible = "qcom,rpmh-rsc"; 5273 reg = <0 0x18200000 0 0x10000>, 5274 <0 0x18210000 0 0x10000>, 5275 <0 0x18220000 0 0x10000>; 5276 reg-names = "drv-0", "drv-1", "drv-2"; 5277 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5278 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5279 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5280 qcom,tcs-offset = <0xd00>; 5281 qcom,drv-id = <2>; 5282 qcom,tcs-config = <ACTIVE_TCS 2>, 5283 <SLEEP_TCS 3>, 5284 <WAKE_TCS 3>, 5285 <CONTROL_TCS 1>; 5286 5287 apps_bcm_voter: bcm-voter { 5288 compatible = "qcom,bcm-voter"; 5289 }; 5290 5291 rpmhpd: power-controller { 5292 compatible = "qcom,sc7280-rpmhpd"; 5293 #power-domain-cells = <1>; 5294 operating-points-v2 = <&rpmhpd_opp_table>; 5295 5296 rpmhpd_opp_table: opp-table { 5297 compatible = "operating-points-v2"; 5298 5299 rpmhpd_opp_ret: opp1 { 5300 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5301 }; 5302 5303 rpmhpd_opp_low_svs: opp2 { 5304 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5305 }; 5306 5307 rpmhpd_opp_svs: opp3 { 5308 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5309 }; 5310 5311 rpmhpd_opp_svs_l1: opp4 { 5312 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5313 }; 5314 5315 rpmhpd_opp_svs_l2: opp5 { 5316 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5317 }; 5318 5319 rpmhpd_opp_nom: opp6 { 5320 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5321 }; 5322 5323 rpmhpd_opp_nom_l1: opp7 { 5324 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5325 }; 5326 5327 rpmhpd_opp_turbo: opp8 { 5328 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5329 }; 5330 5331 rpmhpd_opp_turbo_l1: opp9 { 5332 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5333 }; 5334 }; 5335 }; 5336 5337 rpmhcc: clock-controller { 5338 compatible = "qcom,sc7280-rpmh-clk"; 5339 clocks = <&xo_board>; 5340 clock-names = "xo"; 5341 #clock-cells = <1>; 5342 }; 5343 }; 5344 5345 epss_l3: interconnect@18590000 { 5346 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5347 reg = <0 0x18590000 0 0x1000>; 5348 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5349 clock-names = "xo", "alternate"; 5350 #interconnect-cells = <1>; 5351 }; 5352 5353 cpufreq_hw: cpufreq@18591000 { 5354 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5355 reg = <0 0x18591000 0 0x1000>, 5356 <0 0x18592000 0 0x1000>, 5357 <0 0x18593000 0 0x1000>; 5358 5359 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5360 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5361 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5362 interrupt-names = "dcvsh-irq-0", 5363 "dcvsh-irq-1", 5364 "dcvsh-irq-2"; 5365 5366 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5367 clock-names = "xo", "alternate"; 5368 #freq-domain-cells = <1>; 5369 #clock-cells = <1>; 5370 }; 5371 }; 5372 5373 thermal_zones: thermal-zones { 5374 cpu0-thermal { 5375 polling-delay-passive = <250>; 5376 polling-delay = <0>; 5377 5378 thermal-sensors = <&tsens0 1>; 5379 5380 trips { 5381 cpu0_alert0: trip-point0 { 5382 temperature = <90000>; 5383 hysteresis = <2000>; 5384 type = "passive"; 5385 }; 5386 5387 cpu0_alert1: trip-point1 { 5388 temperature = <95000>; 5389 hysteresis = <2000>; 5390 type = "passive"; 5391 }; 5392 5393 cpu0_crit: cpu-crit { 5394 temperature = <110000>; 5395 hysteresis = <0>; 5396 type = "critical"; 5397 }; 5398 }; 5399 5400 cooling-maps { 5401 map0 { 5402 trip = <&cpu0_alert0>; 5403 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5407 }; 5408 map1 { 5409 trip = <&cpu0_alert1>; 5410 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5412 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5413 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5414 }; 5415 }; 5416 }; 5417 5418 cpu1-thermal { 5419 polling-delay-passive = <250>; 5420 polling-delay = <0>; 5421 5422 thermal-sensors = <&tsens0 2>; 5423 5424 trips { 5425 cpu1_alert0: trip-point0 { 5426 temperature = <90000>; 5427 hysteresis = <2000>; 5428 type = "passive"; 5429 }; 5430 5431 cpu1_alert1: trip-point1 { 5432 temperature = <95000>; 5433 hysteresis = <2000>; 5434 type = "passive"; 5435 }; 5436 5437 cpu1_crit: cpu-crit { 5438 temperature = <110000>; 5439 hysteresis = <0>; 5440 type = "critical"; 5441 }; 5442 }; 5443 5444 cooling-maps { 5445 map0 { 5446 trip = <&cpu1_alert0>; 5447 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5451 }; 5452 map1 { 5453 trip = <&cpu1_alert1>; 5454 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5456 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5457 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5458 }; 5459 }; 5460 }; 5461 5462 cpu2-thermal { 5463 polling-delay-passive = <250>; 5464 polling-delay = <0>; 5465 5466 thermal-sensors = <&tsens0 3>; 5467 5468 trips { 5469 cpu2_alert0: trip-point0 { 5470 temperature = <90000>; 5471 hysteresis = <2000>; 5472 type = "passive"; 5473 }; 5474 5475 cpu2_alert1: trip-point1 { 5476 temperature = <95000>; 5477 hysteresis = <2000>; 5478 type = "passive"; 5479 }; 5480 5481 cpu2_crit: cpu-crit { 5482 temperature = <110000>; 5483 hysteresis = <0>; 5484 type = "critical"; 5485 }; 5486 }; 5487 5488 cooling-maps { 5489 map0 { 5490 trip = <&cpu2_alert0>; 5491 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5495 }; 5496 map1 { 5497 trip = <&cpu2_alert1>; 5498 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5500 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5501 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5502 }; 5503 }; 5504 }; 5505 5506 cpu3-thermal { 5507 polling-delay-passive = <250>; 5508 polling-delay = <0>; 5509 5510 thermal-sensors = <&tsens0 4>; 5511 5512 trips { 5513 cpu3_alert0: trip-point0 { 5514 temperature = <90000>; 5515 hysteresis = <2000>; 5516 type = "passive"; 5517 }; 5518 5519 cpu3_alert1: trip-point1 { 5520 temperature = <95000>; 5521 hysteresis = <2000>; 5522 type = "passive"; 5523 }; 5524 5525 cpu3_crit: cpu-crit { 5526 temperature = <110000>; 5527 hysteresis = <0>; 5528 type = "critical"; 5529 }; 5530 }; 5531 5532 cooling-maps { 5533 map0 { 5534 trip = <&cpu3_alert0>; 5535 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5539 }; 5540 map1 { 5541 trip = <&cpu3_alert1>; 5542 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5544 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5545 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5546 }; 5547 }; 5548 }; 5549 5550 cpu4-thermal { 5551 polling-delay-passive = <250>; 5552 polling-delay = <0>; 5553 5554 thermal-sensors = <&tsens0 7>; 5555 5556 trips { 5557 cpu4_alert0: trip-point0 { 5558 temperature = <90000>; 5559 hysteresis = <2000>; 5560 type = "passive"; 5561 }; 5562 5563 cpu4_alert1: trip-point1 { 5564 temperature = <95000>; 5565 hysteresis = <2000>; 5566 type = "passive"; 5567 }; 5568 5569 cpu4_crit: cpu-crit { 5570 temperature = <110000>; 5571 hysteresis = <0>; 5572 type = "critical"; 5573 }; 5574 }; 5575 5576 cooling-maps { 5577 map0 { 5578 trip = <&cpu4_alert0>; 5579 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5583 }; 5584 map1 { 5585 trip = <&cpu4_alert1>; 5586 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5588 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5589 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5590 }; 5591 }; 5592 }; 5593 5594 cpu5-thermal { 5595 polling-delay-passive = <250>; 5596 polling-delay = <0>; 5597 5598 thermal-sensors = <&tsens0 8>; 5599 5600 trips { 5601 cpu5_alert0: trip-point0 { 5602 temperature = <90000>; 5603 hysteresis = <2000>; 5604 type = "passive"; 5605 }; 5606 5607 cpu5_alert1: trip-point1 { 5608 temperature = <95000>; 5609 hysteresis = <2000>; 5610 type = "passive"; 5611 }; 5612 5613 cpu5_crit: cpu-crit { 5614 temperature = <110000>; 5615 hysteresis = <0>; 5616 type = "critical"; 5617 }; 5618 }; 5619 5620 cooling-maps { 5621 map0 { 5622 trip = <&cpu5_alert0>; 5623 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5627 }; 5628 map1 { 5629 trip = <&cpu5_alert1>; 5630 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5632 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5633 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5634 }; 5635 }; 5636 }; 5637 5638 cpu6-thermal { 5639 polling-delay-passive = <250>; 5640 polling-delay = <0>; 5641 5642 thermal-sensors = <&tsens0 9>; 5643 5644 trips { 5645 cpu6_alert0: trip-point0 { 5646 temperature = <90000>; 5647 hysteresis = <2000>; 5648 type = "passive"; 5649 }; 5650 5651 cpu6_alert1: trip-point1 { 5652 temperature = <95000>; 5653 hysteresis = <2000>; 5654 type = "passive"; 5655 }; 5656 5657 cpu6_crit: cpu-crit { 5658 temperature = <110000>; 5659 hysteresis = <0>; 5660 type = "critical"; 5661 }; 5662 }; 5663 5664 cooling-maps { 5665 map0 { 5666 trip = <&cpu6_alert0>; 5667 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5671 }; 5672 map1 { 5673 trip = <&cpu6_alert1>; 5674 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5676 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5677 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5678 }; 5679 }; 5680 }; 5681 5682 cpu7-thermal { 5683 polling-delay-passive = <250>; 5684 polling-delay = <0>; 5685 5686 thermal-sensors = <&tsens0 10>; 5687 5688 trips { 5689 cpu7_alert0: trip-point0 { 5690 temperature = <90000>; 5691 hysteresis = <2000>; 5692 type = "passive"; 5693 }; 5694 5695 cpu7_alert1: trip-point1 { 5696 temperature = <95000>; 5697 hysteresis = <2000>; 5698 type = "passive"; 5699 }; 5700 5701 cpu7_crit: cpu-crit { 5702 temperature = <110000>; 5703 hysteresis = <0>; 5704 type = "critical"; 5705 }; 5706 }; 5707 5708 cooling-maps { 5709 map0 { 5710 trip = <&cpu7_alert0>; 5711 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5715 }; 5716 map1 { 5717 trip = <&cpu7_alert1>; 5718 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5720 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5721 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5722 }; 5723 }; 5724 }; 5725 5726 cpu8-thermal { 5727 polling-delay-passive = <250>; 5728 polling-delay = <0>; 5729 5730 thermal-sensors = <&tsens0 11>; 5731 5732 trips { 5733 cpu8_alert0: trip-point0 { 5734 temperature = <90000>; 5735 hysteresis = <2000>; 5736 type = "passive"; 5737 }; 5738 5739 cpu8_alert1: trip-point1 { 5740 temperature = <95000>; 5741 hysteresis = <2000>; 5742 type = "passive"; 5743 }; 5744 5745 cpu8_crit: cpu-crit { 5746 temperature = <110000>; 5747 hysteresis = <0>; 5748 type = "critical"; 5749 }; 5750 }; 5751 5752 cooling-maps { 5753 map0 { 5754 trip = <&cpu8_alert0>; 5755 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5759 }; 5760 map1 { 5761 trip = <&cpu8_alert1>; 5762 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5764 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5765 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5766 }; 5767 }; 5768 }; 5769 5770 cpu9-thermal { 5771 polling-delay-passive = <250>; 5772 polling-delay = <0>; 5773 5774 thermal-sensors = <&tsens0 12>; 5775 5776 trips { 5777 cpu9_alert0: trip-point0 { 5778 temperature = <90000>; 5779 hysteresis = <2000>; 5780 type = "passive"; 5781 }; 5782 5783 cpu9_alert1: trip-point1 { 5784 temperature = <95000>; 5785 hysteresis = <2000>; 5786 type = "passive"; 5787 }; 5788 5789 cpu9_crit: cpu-crit { 5790 temperature = <110000>; 5791 hysteresis = <0>; 5792 type = "critical"; 5793 }; 5794 }; 5795 5796 cooling-maps { 5797 map0 { 5798 trip = <&cpu9_alert0>; 5799 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5803 }; 5804 map1 { 5805 trip = <&cpu9_alert1>; 5806 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5808 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5809 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5810 }; 5811 }; 5812 }; 5813 5814 cpu10-thermal { 5815 polling-delay-passive = <250>; 5816 polling-delay = <0>; 5817 5818 thermal-sensors = <&tsens0 13>; 5819 5820 trips { 5821 cpu10_alert0: trip-point0 { 5822 temperature = <90000>; 5823 hysteresis = <2000>; 5824 type = "passive"; 5825 }; 5826 5827 cpu10_alert1: trip-point1 { 5828 temperature = <95000>; 5829 hysteresis = <2000>; 5830 type = "passive"; 5831 }; 5832 5833 cpu10_crit: cpu-crit { 5834 temperature = <110000>; 5835 hysteresis = <0>; 5836 type = "critical"; 5837 }; 5838 }; 5839 5840 cooling-maps { 5841 map0 { 5842 trip = <&cpu10_alert0>; 5843 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5847 }; 5848 map1 { 5849 trip = <&cpu10_alert1>; 5850 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5852 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5853 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5854 }; 5855 }; 5856 }; 5857 5858 cpu11-thermal { 5859 polling-delay-passive = <250>; 5860 polling-delay = <0>; 5861 5862 thermal-sensors = <&tsens0 14>; 5863 5864 trips { 5865 cpu11_alert0: trip-point0 { 5866 temperature = <90000>; 5867 hysteresis = <2000>; 5868 type = "passive"; 5869 }; 5870 5871 cpu11_alert1: trip-point1 { 5872 temperature = <95000>; 5873 hysteresis = <2000>; 5874 type = "passive"; 5875 }; 5876 5877 cpu11_crit: cpu-crit { 5878 temperature = <110000>; 5879 hysteresis = <0>; 5880 type = "critical"; 5881 }; 5882 }; 5883 5884 cooling-maps { 5885 map0 { 5886 trip = <&cpu11_alert0>; 5887 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5889 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5890 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5891 }; 5892 map1 { 5893 trip = <&cpu11_alert1>; 5894 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5895 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5896 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5897 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5898 }; 5899 }; 5900 }; 5901 5902 aoss0-thermal { 5903 polling-delay-passive = <0>; 5904 polling-delay = <0>; 5905 5906 thermal-sensors = <&tsens0 0>; 5907 5908 trips { 5909 aoss0_alert0: trip-point0 { 5910 temperature = <90000>; 5911 hysteresis = <2000>; 5912 type = "hot"; 5913 }; 5914 5915 aoss0_crit: aoss0-crit { 5916 temperature = <110000>; 5917 hysteresis = <0>; 5918 type = "critical"; 5919 }; 5920 }; 5921 }; 5922 5923 aoss1-thermal { 5924 polling-delay-passive = <0>; 5925 polling-delay = <0>; 5926 5927 thermal-sensors = <&tsens1 0>; 5928 5929 trips { 5930 aoss1_alert0: trip-point0 { 5931 temperature = <90000>; 5932 hysteresis = <2000>; 5933 type = "hot"; 5934 }; 5935 5936 aoss1_crit: aoss1-crit { 5937 temperature = <110000>; 5938 hysteresis = <0>; 5939 type = "critical"; 5940 }; 5941 }; 5942 }; 5943 5944 cpuss0-thermal { 5945 polling-delay-passive = <0>; 5946 polling-delay = <0>; 5947 5948 thermal-sensors = <&tsens0 5>; 5949 5950 trips { 5951 cpuss0_alert0: trip-point0 { 5952 temperature = <90000>; 5953 hysteresis = <2000>; 5954 type = "hot"; 5955 }; 5956 cpuss0_crit: cluster0-crit { 5957 temperature = <110000>; 5958 hysteresis = <0>; 5959 type = "critical"; 5960 }; 5961 }; 5962 }; 5963 5964 cpuss1-thermal { 5965 polling-delay-passive = <0>; 5966 polling-delay = <0>; 5967 5968 thermal-sensors = <&tsens0 6>; 5969 5970 trips { 5971 cpuss1_alert0: trip-point0 { 5972 temperature = <90000>; 5973 hysteresis = <2000>; 5974 type = "hot"; 5975 }; 5976 cpuss1_crit: cluster0-crit { 5977 temperature = <110000>; 5978 hysteresis = <0>; 5979 type = "critical"; 5980 }; 5981 }; 5982 }; 5983 5984 gpuss0-thermal { 5985 polling-delay-passive = <100>; 5986 polling-delay = <0>; 5987 5988 thermal-sensors = <&tsens1 1>; 5989 5990 trips { 5991 gpuss0_alert0: trip-point0 { 5992 temperature = <95000>; 5993 hysteresis = <2000>; 5994 type = "passive"; 5995 }; 5996 5997 gpuss0_crit: gpuss0-crit { 5998 temperature = <110000>; 5999 hysteresis = <0>; 6000 type = "critical"; 6001 }; 6002 }; 6003 6004 cooling-maps { 6005 map0 { 6006 trip = <&gpuss0_alert0>; 6007 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6008 }; 6009 }; 6010 }; 6011 6012 gpuss1-thermal { 6013 polling-delay-passive = <100>; 6014 polling-delay = <0>; 6015 6016 thermal-sensors = <&tsens1 2>; 6017 6018 trips { 6019 gpuss1_alert0: trip-point0 { 6020 temperature = <95000>; 6021 hysteresis = <2000>; 6022 type = "passive"; 6023 }; 6024 6025 gpuss1_crit: gpuss1-crit { 6026 temperature = <110000>; 6027 hysteresis = <0>; 6028 type = "critical"; 6029 }; 6030 }; 6031 6032 cooling-maps { 6033 map0 { 6034 trip = <&gpuss1_alert0>; 6035 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6036 }; 6037 }; 6038 }; 6039 6040 nspss0-thermal { 6041 polling-delay-passive = <0>; 6042 polling-delay = <0>; 6043 6044 thermal-sensors = <&tsens1 3>; 6045 6046 trips { 6047 nspss0_alert0: trip-point0 { 6048 temperature = <90000>; 6049 hysteresis = <2000>; 6050 type = "hot"; 6051 }; 6052 6053 nspss0_crit: nspss0-crit { 6054 temperature = <110000>; 6055 hysteresis = <0>; 6056 type = "critical"; 6057 }; 6058 }; 6059 }; 6060 6061 nspss1-thermal { 6062 polling-delay-passive = <0>; 6063 polling-delay = <0>; 6064 6065 thermal-sensors = <&tsens1 4>; 6066 6067 trips { 6068 nspss1_alert0: trip-point0 { 6069 temperature = <90000>; 6070 hysteresis = <2000>; 6071 type = "hot"; 6072 }; 6073 6074 nspss1_crit: nspss1-crit { 6075 temperature = <110000>; 6076 hysteresis = <0>; 6077 type = "critical"; 6078 }; 6079 }; 6080 }; 6081 6082 video-thermal { 6083 polling-delay-passive = <0>; 6084 polling-delay = <0>; 6085 6086 thermal-sensors = <&tsens1 5>; 6087 6088 trips { 6089 video_alert0: trip-point0 { 6090 temperature = <90000>; 6091 hysteresis = <2000>; 6092 type = "hot"; 6093 }; 6094 6095 video_crit: video-crit { 6096 temperature = <110000>; 6097 hysteresis = <0>; 6098 type = "critical"; 6099 }; 6100 }; 6101 }; 6102 6103 ddr-thermal { 6104 polling-delay-passive = <0>; 6105 polling-delay = <0>; 6106 6107 thermal-sensors = <&tsens1 6>; 6108 6109 trips { 6110 ddr_alert0: trip-point0 { 6111 temperature = <90000>; 6112 hysteresis = <2000>; 6113 type = "hot"; 6114 }; 6115 6116 ddr_crit: ddr-crit { 6117 temperature = <110000>; 6118 hysteresis = <0>; 6119 type = "critical"; 6120 }; 6121 }; 6122 }; 6123 6124 mdmss0-thermal { 6125 polling-delay-passive = <0>; 6126 polling-delay = <0>; 6127 6128 thermal-sensors = <&tsens1 7>; 6129 6130 trips { 6131 mdmss0_alert0: trip-point0 { 6132 temperature = <90000>; 6133 hysteresis = <2000>; 6134 type = "hot"; 6135 }; 6136 6137 mdmss0_crit: mdmss0-crit { 6138 temperature = <110000>; 6139 hysteresis = <0>; 6140 type = "critical"; 6141 }; 6142 }; 6143 }; 6144 6145 mdmss1-thermal { 6146 polling-delay-passive = <0>; 6147 polling-delay = <0>; 6148 6149 thermal-sensors = <&tsens1 8>; 6150 6151 trips { 6152 mdmss1_alert0: trip-point0 { 6153 temperature = <90000>; 6154 hysteresis = <2000>; 6155 type = "hot"; 6156 }; 6157 6158 mdmss1_crit: mdmss1-crit { 6159 temperature = <110000>; 6160 hysteresis = <0>; 6161 type = "critical"; 6162 }; 6163 }; 6164 }; 6165 6166 mdmss2-thermal { 6167 polling-delay-passive = <0>; 6168 polling-delay = <0>; 6169 6170 thermal-sensors = <&tsens1 9>; 6171 6172 trips { 6173 mdmss2_alert0: trip-point0 { 6174 temperature = <90000>; 6175 hysteresis = <2000>; 6176 type = "hot"; 6177 }; 6178 6179 mdmss2_crit: mdmss2-crit { 6180 temperature = <110000>; 6181 hysteresis = <0>; 6182 type = "critical"; 6183 }; 6184 }; 6185 }; 6186 6187 mdmss3-thermal { 6188 polling-delay-passive = <0>; 6189 polling-delay = <0>; 6190 6191 thermal-sensors = <&tsens1 10>; 6192 6193 trips { 6194 mdmss3_alert0: trip-point0 { 6195 temperature = <90000>; 6196 hysteresis = <2000>; 6197 type = "hot"; 6198 }; 6199 6200 mdmss3_crit: mdmss3-crit { 6201 temperature = <110000>; 6202 hysteresis = <0>; 6203 type = "critical"; 6204 }; 6205 }; 6206 }; 6207 6208 camera0-thermal { 6209 polling-delay-passive = <0>; 6210 polling-delay = <0>; 6211 6212 thermal-sensors = <&tsens1 11>; 6213 6214 trips { 6215 camera0_alert0: trip-point0 { 6216 temperature = <90000>; 6217 hysteresis = <2000>; 6218 type = "hot"; 6219 }; 6220 6221 camera0_crit: camera0-crit { 6222 temperature = <110000>; 6223 hysteresis = <0>; 6224 type = "critical"; 6225 }; 6226 }; 6227 }; 6228 }; 6229 6230 timer { 6231 compatible = "arm,armv8-timer"; 6232 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6233 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6234 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6235 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6236 }; 6237}; 6238