1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 aop_mem: memory@80800000 { 56 reg = <0x0 0x80800000 0x0 0x60000>; 57 no-map; 58 }; 59 60 aop_cmd_db_mem: memory@80860000 { 61 reg = <0x0 0x80860000 0x0 0x20000>; 62 compatible = "qcom,cmd-db"; 63 no-map; 64 }; 65 66 smem_mem: memory@80900000 { 67 reg = <0x0 0x80900000 0x0 0x200000>; 68 no-map; 69 }; 70 71 cpucp_mem: memory@80b00000 { 72 no-map; 73 reg = <0x0 0x80b00000 0x0 0x100000>; 74 }; 75 76 ipa_fw_mem: memory@8b700000 { 77 reg = <0 0x8b700000 0 0x10000>; 78 no-map; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <2>; 84 #size-cells = <0>; 85 86 CPU0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,kryo"; 89 reg = <0x0 0x0>; 90 enable-method = "psci"; 91 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 92 &LITTLE_CPU_SLEEP_1 93 &CLUSTER_SLEEP_0>; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_0: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 L3_0: l3-cache { 101 compatible = "cache"; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,kryo"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_100>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "arm,kryo"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_200>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_200: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x300>; 144 enable-method = "psci"; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 146 &LITTLE_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_300>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x400>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "arm,kryo"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 cpu-idle-states = <&BIG_CPU_SLEEP_0 180 &BIG_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,kryo"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 197 &BIG_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 cpu-idle-states = <&BIG_CPU_SLEEP_0 214 &BIG_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-power-down"; 267 arm,psci-suspend-param = <0x40000003>; 268 entry-latency-us = <549>; 269 exit-latency-us = <901>; 270 min-residency-us = <1774>; 271 local-timer-stop; 272 }; 273 274 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-down"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <702>; 279 exit-latency-us = <915>; 280 min-residency-us = <4001>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-power-down"; 287 arm,psci-suspend-param = <0x40000003>; 288 entry-latency-us = <523>; 289 exit-latency-us = <1244>; 290 min-residency-us = <2207>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "big-rail-power-down"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <526>; 299 exit-latency-us = <1854>; 300 min-residency-us = <5555>; 301 local-timer-stop; 302 }; 303 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "cluster-power-down"; 307 arm,psci-suspend-param = <0x40003444>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9926>; 311 local-timer-stop; 312 }; 313 }; 314 }; 315 316 memory@80000000 { 317 device_type = "memory"; 318 /* We expect the bootloader to fill in the size */ 319 reg = <0 0x80000000 0 0>; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-sc7280", "qcom,scm"; 325 }; 326 }; 327 328 clk_virt: interconnect { 329 compatible = "qcom,sc7280-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 smem { 335 compatible = "qcom,smem"; 336 memory-region = <&smem_mem>; 337 hwlocks = <&tcsr_mutex 3>; 338 }; 339 340 smp2p-adsp { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <443>, <429>; 343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P 345 IRQ_TYPE_EDGE_RISING>; 346 mboxes = <&ipcc IPCC_CLIENT_LPASS 347 IPCC_MPROC_SIGNAL_SMP2P>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <2>; 351 352 adsp_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 adsp_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 }; 363 364 smp2p-cdsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <94>, <432>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_CDSP 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <5>; 375 376 cdsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 cdsp_smp2p_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-mpss { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <435>, <428>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_MPSS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <1>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 ipa_smp2p_out: ipa-ap-to-modem { 412 qcom,entry-name = "ipa"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 ipa_smp2p_in: ipa-modem-to-ap { 417 qcom,entry-name = "ipa"; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smp2p-wpss { 424 compatible = "qcom,smp2p"; 425 qcom,smem = <617>, <616>; 426 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P 428 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&ipcc IPCC_CLIENT_WPSS 430 IPCC_MPROC_SIGNAL_SMP2P>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <13>; 434 435 wpss_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 wpss_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 }; 446 447 pmu { 448 compatible = "arm,armv8-pmuv3"; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 450 }; 451 452 psci { 453 compatible = "arm,psci-1.0"; 454 method = "smc"; 455 }; 456 457 soc: soc@0 { 458 #address-cells = <2>; 459 #size-cells = <2>; 460 ranges = <0 0 0 0 0x10 0>; 461 dma-ranges = <0 0 0 0 0x10 0>; 462 compatible = "simple-bus"; 463 464 gcc: clock-controller@100000 { 465 compatible = "qcom,gcc-sc7280"; 466 reg = <0 0x00100000 0 0x1f0000>; 467 clocks = <&rpmhcc RPMH_CXO_CLK>, 468 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 469 <0>, <0>, <0>, <0>, <0>, <0>; 470 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 471 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 472 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 473 "ufs_phy_tx_symbol_0_clk", 474 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 475 #clock-cells = <1>; 476 #reset-cells = <1>; 477 #power-domain-cells = <1>; 478 }; 479 480 ipcc: mailbox@408000 { 481 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 482 reg = <0 0x00408000 0 0x1000>; 483 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-controller; 485 #interrupt-cells = <3>; 486 #mbox-cells = <2>; 487 }; 488 489 qfprom: efuse@784000 { 490 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 491 reg = <0 0x00784000 0 0xa20>, 492 <0 0x00780000 0 0xa20>, 493 <0 0x00782000 0 0x120>, 494 <0 0x00786000 0 0x1fff>; 495 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 496 clock-names = "core"; 497 power-domains = <&rpmhpd SC7280_MX>; 498 #address-cells = <1>; 499 #size-cells = <1>; 500 }; 501 502 sdhc_1: sdhci@7c4000 { 503 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 504 status = "disabled"; 505 506 reg = <0 0x007c4000 0 0x1000>, 507 <0 0x007c5000 0 0x1000>; 508 reg-names = "hc", "cqhci"; 509 510 iommus = <&apps_smmu 0xc0 0x0>; 511 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "hc_irq", "pwr_irq"; 514 515 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 516 <&gcc GCC_SDCC1_AHB_CLK>, 517 <&rpmhcc RPMH_CXO_CLK>; 518 clock-names = "core", "iface", "xo"; 519 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 521 interconnect-names = "sdhc-ddr","cpu-sdhc"; 522 power-domains = <&rpmhpd SC7280_CX>; 523 operating-points-v2 = <&sdhc1_opp_table>; 524 525 bus-width = <8>; 526 supports-cqe; 527 528 qcom,dll-config = <0x0007642c>; 529 qcom,ddr-config = <0x80040868>; 530 531 mmc-ddr-1_8v; 532 mmc-hs200-1_8v; 533 mmc-hs400-1_8v; 534 mmc-hs400-enhanced-strobe; 535 536 sdhc1_opp_table: opp-table { 537 compatible = "operating-points-v2"; 538 539 opp-100000000 { 540 opp-hz = /bits/ 64 <100000000>; 541 required-opps = <&rpmhpd_opp_low_svs>; 542 opp-peak-kBps = <1800000 400000>; 543 opp-avg-kBps = <100000 0>; 544 }; 545 546 opp-384000000 { 547 opp-hz = /bits/ 64 <384000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 opp-peak-kBps = <5400000 1600000>; 550 opp-avg-kBps = <390000 0>; 551 }; 552 }; 553 554 }; 555 556 qupv3_id_0: geniqup@9c0000 { 557 compatible = "qcom,geni-se-qup"; 558 reg = <0 0x009c0000 0 0x2000>; 559 clock-names = "m-ahb", "s-ahb"; 560 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 561 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 562 #address-cells = <2>; 563 #size-cells = <2>; 564 ranges; 565 status = "disabled"; 566 567 uart5: serial@994000 { 568 compatible = "qcom,geni-debug-uart"; 569 reg = <0 0x00994000 0 0x4000>; 570 clock-names = "se"; 571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&qup_uart5_default>; 574 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 575 status = "disabled"; 576 }; 577 }; 578 579 cnoc2: interconnect@1500000 { 580 reg = <0 0x01500000 0 0x1000>; 581 compatible = "qcom,sc7280-cnoc2"; 582 #interconnect-cells = <2>; 583 qcom,bcm-voters = <&apps_bcm_voter>; 584 }; 585 586 cnoc3: interconnect@1502000 { 587 reg = <0 0x01502000 0 0x1000>; 588 compatible = "qcom,sc7280-cnoc3"; 589 #interconnect-cells = <2>; 590 qcom,bcm-voters = <&apps_bcm_voter>; 591 }; 592 593 mc_virt: interconnect@1580000 { 594 reg = <0 0x01580000 0 0x4>; 595 compatible = "qcom,sc7280-mc-virt"; 596 #interconnect-cells = <2>; 597 qcom,bcm-voters = <&apps_bcm_voter>; 598 }; 599 600 system_noc: interconnect@1680000 { 601 reg = <0 0x01680000 0 0x15480>; 602 compatible = "qcom,sc7280-system-noc"; 603 #interconnect-cells = <2>; 604 qcom,bcm-voters = <&apps_bcm_voter>; 605 }; 606 607 aggre1_noc: interconnect@16e0000 { 608 compatible = "qcom,sc7280-aggre1-noc"; 609 reg = <0 0x016e0000 0 0x1c080>; 610 #interconnect-cells = <2>; 611 qcom,bcm-voters = <&apps_bcm_voter>; 612 }; 613 614 aggre2_noc: interconnect@1700000 { 615 reg = <0 0x01700000 0 0x2b080>; 616 compatible = "qcom,sc7280-aggre2-noc"; 617 #interconnect-cells = <2>; 618 qcom,bcm-voters = <&apps_bcm_voter>; 619 }; 620 621 mmss_noc: interconnect@1740000 { 622 reg = <0 0x01740000 0 0x1e080>; 623 compatible = "qcom,sc7280-mmss-noc"; 624 #interconnect-cells = <2>; 625 qcom,bcm-voters = <&apps_bcm_voter>; 626 }; 627 628 ipa: ipa@1e40000 { 629 compatible = "qcom,sc7280-ipa"; 630 631 iommus = <&apps_smmu 0x480 0x0>, 632 <&apps_smmu 0x482 0x0>; 633 reg = <0 0x1e40000 0 0x8000>, 634 <0 0x1e50000 0 0x4ad0>, 635 <0 0x1e04000 0 0x23000>; 636 reg-names = "ipa-reg", 637 "ipa-shared", 638 "gsi"; 639 640 interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, 641 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 642 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 643 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 644 interrupt-names = "ipa", 645 "gsi", 646 "ipa-clock-query", 647 "ipa-setup-ready"; 648 649 clocks = <&rpmhcc RPMH_IPA_CLK>; 650 clock-names = "core"; 651 652 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 654 interconnect-names = "memory", 655 "config"; 656 657 qcom,smem-states = <&ipa_smp2p_out 0>, 658 <&ipa_smp2p_out 1>; 659 qcom,smem-state-names = "ipa-clock-enabled-valid", 660 "ipa-clock-enabled"; 661 662 status = "disabled"; 663 }; 664 665 tcsr_mutex: hwlock@1f40000 { 666 compatible = "qcom,tcsr-mutex", "syscon"; 667 reg = <0 0x01f40000 0 0x40000>; 668 #hwlock-cells = <1>; 669 }; 670 671 lpasscc: lpasscc@3000000 { 672 compatible = "qcom,sc7280-lpasscc"; 673 reg = <0 0x03000000 0 0x40>, 674 <0 0x03c04000 0 0x4>, 675 <0 0x03389000 0 0x24>; 676 reg-names = "qdsp6ss", "top_cc", "cc"; 677 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 678 clock-names = "iface"; 679 #clock-cells = <1>; 680 }; 681 682 lpass_ag_noc: interconnect@3c40000 { 683 reg = <0 0x03c40000 0 0xf080>; 684 compatible = "qcom,sc7280-lpass-ag-noc"; 685 #interconnect-cells = <2>; 686 qcom,bcm-voters = <&apps_bcm_voter>; 687 }; 688 689 gpucc: clock-controller@3d90000 { 690 compatible = "qcom,sc7280-gpucc"; 691 reg = <0 0x03d90000 0 0x9000>; 692 clocks = <&rpmhcc RPMH_CXO_CLK>, 693 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 694 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 695 clock-names = "bi_tcxo", 696 "gcc_gpu_gpll0_clk_src", 697 "gcc_gpu_gpll0_div_clk_src"; 698 #clock-cells = <1>; 699 #reset-cells = <1>; 700 #power-domain-cells = <1>; 701 }; 702 703 stm@6002000 { 704 compatible = "arm,coresight-stm", "arm,primecell"; 705 reg = <0 0x06002000 0 0x1000>, 706 <0 0x16280000 0 0x180000>; 707 reg-names = "stm-base", "stm-stimulus-base"; 708 709 clocks = <&aoss_qmp>; 710 clock-names = "apb_pclk"; 711 712 out-ports { 713 port { 714 stm_out: endpoint { 715 remote-endpoint = <&funnel0_in7>; 716 }; 717 }; 718 }; 719 }; 720 721 funnel@6041000 { 722 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 723 reg = <0 0x06041000 0 0x1000>; 724 725 clocks = <&aoss_qmp>; 726 clock-names = "apb_pclk"; 727 728 out-ports { 729 port { 730 funnel0_out: endpoint { 731 remote-endpoint = <&merge_funnel_in0>; 732 }; 733 }; 734 }; 735 736 in-ports { 737 #address-cells = <1>; 738 #size-cells = <0>; 739 740 port@7 { 741 reg = <7>; 742 funnel0_in7: endpoint { 743 remote-endpoint = <&stm_out>; 744 }; 745 }; 746 }; 747 }; 748 749 funnel@6042000 { 750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 751 reg = <0 0x06042000 0 0x1000>; 752 753 clocks = <&aoss_qmp>; 754 clock-names = "apb_pclk"; 755 756 out-ports { 757 port { 758 funnel1_out: endpoint { 759 remote-endpoint = <&merge_funnel_in1>; 760 }; 761 }; 762 }; 763 764 in-ports { 765 #address-cells = <1>; 766 #size-cells = <0>; 767 768 port@4 { 769 reg = <4>; 770 funnel1_in4: endpoint { 771 remote-endpoint = <&apss_merge_funnel_out>; 772 }; 773 }; 774 }; 775 }; 776 777 funnel@6045000 { 778 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 779 reg = <0 0x06045000 0 0x1000>; 780 781 clocks = <&aoss_qmp>; 782 clock-names = "apb_pclk"; 783 784 out-ports { 785 port { 786 merge_funnel_out: endpoint { 787 remote-endpoint = <&swao_funnel_in>; 788 }; 789 }; 790 }; 791 792 in-ports { 793 #address-cells = <1>; 794 #size-cells = <0>; 795 796 port@0 { 797 reg = <0>; 798 merge_funnel_in0: endpoint { 799 remote-endpoint = <&funnel0_out>; 800 }; 801 }; 802 803 port@1 { 804 reg = <1>; 805 merge_funnel_in1: endpoint { 806 remote-endpoint = <&funnel1_out>; 807 }; 808 }; 809 }; 810 }; 811 812 replicator@6046000 { 813 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 814 reg = <0 0x06046000 0 0x1000>; 815 816 clocks = <&aoss_qmp>; 817 clock-names = "apb_pclk"; 818 819 out-ports { 820 port { 821 replicator_out: endpoint { 822 remote-endpoint = <&etr_in>; 823 }; 824 }; 825 }; 826 827 in-ports { 828 port { 829 replicator_in: endpoint { 830 remote-endpoint = <&swao_replicator_out>; 831 }; 832 }; 833 }; 834 }; 835 836 etr@6048000 { 837 compatible = "arm,coresight-tmc", "arm,primecell"; 838 reg = <0 0x06048000 0 0x1000>; 839 iommus = <&apps_smmu 0x04c0 0>; 840 841 clocks = <&aoss_qmp>; 842 clock-names = "apb_pclk"; 843 arm,scatter-gather; 844 845 in-ports { 846 port { 847 etr_in: endpoint { 848 remote-endpoint = <&replicator_out>; 849 }; 850 }; 851 }; 852 }; 853 854 funnel@6b04000 { 855 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 856 reg = <0 0x06b04000 0 0x1000>; 857 858 clocks = <&aoss_qmp>; 859 clock-names = "apb_pclk"; 860 861 out-ports { 862 port { 863 swao_funnel_out: endpoint { 864 remote-endpoint = <&etf_in>; 865 }; 866 }; 867 }; 868 869 in-ports { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 port@7 { 874 reg = <7>; 875 swao_funnel_in: endpoint { 876 remote-endpoint = <&merge_funnel_out>; 877 }; 878 }; 879 }; 880 }; 881 882 etf@6b05000 { 883 compatible = "arm,coresight-tmc", "arm,primecell"; 884 reg = <0 0x06b05000 0 0x1000>; 885 886 clocks = <&aoss_qmp>; 887 clock-names = "apb_pclk"; 888 889 out-ports { 890 port { 891 etf_out: endpoint { 892 remote-endpoint = <&swao_replicator_in>; 893 }; 894 }; 895 }; 896 897 in-ports { 898 port { 899 etf_in: endpoint { 900 remote-endpoint = <&swao_funnel_out>; 901 }; 902 }; 903 }; 904 }; 905 906 replicator@6b06000 { 907 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 908 reg = <0 0x06b06000 0 0x1000>; 909 910 clocks = <&aoss_qmp>; 911 clock-names = "apb_pclk"; 912 qcom,replicator-loses-context; 913 914 out-ports { 915 port { 916 swao_replicator_out: endpoint { 917 remote-endpoint = <&replicator_in>; 918 }; 919 }; 920 }; 921 922 in-ports { 923 port { 924 swao_replicator_in: endpoint { 925 remote-endpoint = <&etf_out>; 926 }; 927 }; 928 }; 929 }; 930 931 etm@7040000 { 932 compatible = "arm,coresight-etm4x", "arm,primecell"; 933 reg = <0 0x07040000 0 0x1000>; 934 935 cpu = <&CPU0>; 936 937 clocks = <&aoss_qmp>; 938 clock-names = "apb_pclk"; 939 arm,coresight-loses-context-with-cpu; 940 qcom,skip-power-up; 941 942 out-ports { 943 port { 944 etm0_out: endpoint { 945 remote-endpoint = <&apss_funnel_in0>; 946 }; 947 }; 948 }; 949 }; 950 951 etm@7140000 { 952 compatible = "arm,coresight-etm4x", "arm,primecell"; 953 reg = <0 0x07140000 0 0x1000>; 954 955 cpu = <&CPU1>; 956 957 clocks = <&aoss_qmp>; 958 clock-names = "apb_pclk"; 959 arm,coresight-loses-context-with-cpu; 960 qcom,skip-power-up; 961 962 out-ports { 963 port { 964 etm1_out: endpoint { 965 remote-endpoint = <&apss_funnel_in1>; 966 }; 967 }; 968 }; 969 }; 970 971 etm@7240000 { 972 compatible = "arm,coresight-etm4x", "arm,primecell"; 973 reg = <0 0x07240000 0 0x1000>; 974 975 cpu = <&CPU2>; 976 977 clocks = <&aoss_qmp>; 978 clock-names = "apb_pclk"; 979 arm,coresight-loses-context-with-cpu; 980 qcom,skip-power-up; 981 982 out-ports { 983 port { 984 etm2_out: endpoint { 985 remote-endpoint = <&apss_funnel_in2>; 986 }; 987 }; 988 }; 989 }; 990 991 etm@7340000 { 992 compatible = "arm,coresight-etm4x", "arm,primecell"; 993 reg = <0 0x07340000 0 0x1000>; 994 995 cpu = <&CPU3>; 996 997 clocks = <&aoss_qmp>; 998 clock-names = "apb_pclk"; 999 arm,coresight-loses-context-with-cpu; 1000 qcom,skip-power-up; 1001 1002 out-ports { 1003 port { 1004 etm3_out: endpoint { 1005 remote-endpoint = <&apss_funnel_in3>; 1006 }; 1007 }; 1008 }; 1009 }; 1010 1011 etm@7440000 { 1012 compatible = "arm,coresight-etm4x", "arm,primecell"; 1013 reg = <0 0x07440000 0 0x1000>; 1014 1015 cpu = <&CPU4>; 1016 1017 clocks = <&aoss_qmp>; 1018 clock-names = "apb_pclk"; 1019 arm,coresight-loses-context-with-cpu; 1020 qcom,skip-power-up; 1021 1022 out-ports { 1023 port { 1024 etm4_out: endpoint { 1025 remote-endpoint = <&apss_funnel_in4>; 1026 }; 1027 }; 1028 }; 1029 }; 1030 1031 etm@7540000 { 1032 compatible = "arm,coresight-etm4x", "arm,primecell"; 1033 reg = <0 0x07540000 0 0x1000>; 1034 1035 cpu = <&CPU5>; 1036 1037 clocks = <&aoss_qmp>; 1038 clock-names = "apb_pclk"; 1039 arm,coresight-loses-context-with-cpu; 1040 qcom,skip-power-up; 1041 1042 out-ports { 1043 port { 1044 etm5_out: endpoint { 1045 remote-endpoint = <&apss_funnel_in5>; 1046 }; 1047 }; 1048 }; 1049 }; 1050 1051 etm@7640000 { 1052 compatible = "arm,coresight-etm4x", "arm,primecell"; 1053 reg = <0 0x07640000 0 0x1000>; 1054 1055 cpu = <&CPU6>; 1056 1057 clocks = <&aoss_qmp>; 1058 clock-names = "apb_pclk"; 1059 arm,coresight-loses-context-with-cpu; 1060 qcom,skip-power-up; 1061 1062 out-ports { 1063 port { 1064 etm6_out: endpoint { 1065 remote-endpoint = <&apss_funnel_in6>; 1066 }; 1067 }; 1068 }; 1069 }; 1070 1071 etm@7740000 { 1072 compatible = "arm,coresight-etm4x", "arm,primecell"; 1073 reg = <0 0x07740000 0 0x1000>; 1074 1075 cpu = <&CPU7>; 1076 1077 clocks = <&aoss_qmp>; 1078 clock-names = "apb_pclk"; 1079 arm,coresight-loses-context-with-cpu; 1080 qcom,skip-power-up; 1081 1082 out-ports { 1083 port { 1084 etm7_out: endpoint { 1085 remote-endpoint = <&apss_funnel_in7>; 1086 }; 1087 }; 1088 }; 1089 }; 1090 1091 funnel@7800000 { /* APSS Funnel */ 1092 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1093 reg = <0 0x07800000 0 0x1000>; 1094 1095 clocks = <&aoss_qmp>; 1096 clock-names = "apb_pclk"; 1097 1098 out-ports { 1099 port { 1100 apss_funnel_out: endpoint { 1101 remote-endpoint = <&apss_merge_funnel_in>; 1102 }; 1103 }; 1104 }; 1105 1106 in-ports { 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 1110 port@0 { 1111 reg = <0>; 1112 apss_funnel_in0: endpoint { 1113 remote-endpoint = <&etm0_out>; 1114 }; 1115 }; 1116 1117 port@1 { 1118 reg = <1>; 1119 apss_funnel_in1: endpoint { 1120 remote-endpoint = <&etm1_out>; 1121 }; 1122 }; 1123 1124 port@2 { 1125 reg = <2>; 1126 apss_funnel_in2: endpoint { 1127 remote-endpoint = <&etm2_out>; 1128 }; 1129 }; 1130 1131 port@3 { 1132 reg = <3>; 1133 apss_funnel_in3: endpoint { 1134 remote-endpoint = <&etm3_out>; 1135 }; 1136 }; 1137 1138 port@4 { 1139 reg = <4>; 1140 apss_funnel_in4: endpoint { 1141 remote-endpoint = <&etm4_out>; 1142 }; 1143 }; 1144 1145 port@5 { 1146 reg = <5>; 1147 apss_funnel_in5: endpoint { 1148 remote-endpoint = <&etm5_out>; 1149 }; 1150 }; 1151 1152 port@6 { 1153 reg = <6>; 1154 apss_funnel_in6: endpoint { 1155 remote-endpoint = <&etm6_out>; 1156 }; 1157 }; 1158 1159 port@7 { 1160 reg = <7>; 1161 apss_funnel_in7: endpoint { 1162 remote-endpoint = <&etm7_out>; 1163 }; 1164 }; 1165 }; 1166 }; 1167 1168 funnel@7810000 { 1169 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1170 reg = <0 0x07810000 0 0x1000>; 1171 1172 clocks = <&aoss_qmp>; 1173 clock-names = "apb_pclk"; 1174 1175 out-ports { 1176 port { 1177 apss_merge_funnel_out: endpoint { 1178 remote-endpoint = <&funnel1_in4>; 1179 }; 1180 }; 1181 }; 1182 1183 in-ports { 1184 port { 1185 apss_merge_funnel_in: endpoint { 1186 remote-endpoint = <&apss_funnel_out>; 1187 }; 1188 }; 1189 }; 1190 }; 1191 1192 sdhc_2: sdhci@8804000 { 1193 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1194 status = "disabled"; 1195 1196 reg = <0 0x08804000 0 0x1000>; 1197 1198 iommus = <&apps_smmu 0x100 0x0>; 1199 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1201 interrupt-names = "hc_irq", "pwr_irq"; 1202 1203 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1204 <&gcc GCC_SDCC2_AHB_CLK>, 1205 <&rpmhcc RPMH_CXO_CLK>; 1206 clock-names = "core", "iface", "xo"; 1207 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1208 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1209 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1210 power-domains = <&rpmhpd SC7280_CX>; 1211 operating-points-v2 = <&sdhc2_opp_table>; 1212 1213 bus-width = <4>; 1214 1215 qcom,dll-config = <0x0007642c>; 1216 1217 sdhc2_opp_table: opp-table { 1218 compatible = "operating-points-v2"; 1219 1220 opp-100000000 { 1221 opp-hz = /bits/ 64 <100000000>; 1222 required-opps = <&rpmhpd_opp_low_svs>; 1223 opp-peak-kBps = <1800000 400000>; 1224 opp-avg-kBps = <100000 0>; 1225 }; 1226 1227 opp-202000000 { 1228 opp-hz = /bits/ 64 <202000000>; 1229 required-opps = <&rpmhpd_opp_nom>; 1230 opp-peak-kBps = <5400000 1600000>; 1231 opp-avg-kBps = <200000 0>; 1232 }; 1233 }; 1234 1235 }; 1236 1237 usb_1_hsphy: phy@88e3000 { 1238 compatible = "qcom,sc7280-usb-hs-phy", 1239 "qcom,usb-snps-hs-7nm-phy"; 1240 reg = <0 0x088e3000 0 0x400>; 1241 status = "disabled"; 1242 #phy-cells = <0>; 1243 1244 clocks = <&rpmhcc RPMH_CXO_CLK>; 1245 clock-names = "ref"; 1246 1247 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1248 }; 1249 1250 usb_2_hsphy: phy@88e4000 { 1251 compatible = "qcom,sc7280-usb-hs-phy", 1252 "qcom,usb-snps-hs-7nm-phy"; 1253 reg = <0 0x088e4000 0 0x400>; 1254 status = "disabled"; 1255 #phy-cells = <0>; 1256 1257 clocks = <&rpmhcc RPMH_CXO_CLK>; 1258 clock-names = "ref"; 1259 1260 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1261 }; 1262 1263 usb_1_qmpphy: phy-wrapper@88e9000 { 1264 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1265 "qcom,sm8250-qmp-usb3-dp-phy"; 1266 reg = <0 0x088e9000 0 0x200>, 1267 <0 0x088e8000 0 0x40>, 1268 <0 0x088ea000 0 0x200>; 1269 status = "disabled"; 1270 #address-cells = <2>; 1271 #size-cells = <2>; 1272 ranges; 1273 1274 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1275 <&rpmhcc RPMH_CXO_CLK>, 1276 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1277 clock-names = "aux", "ref_clk_src", "com_aux"; 1278 1279 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1280 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1281 reset-names = "phy", "common"; 1282 1283 usb_1_ssphy: usb3-phy@88e9200 { 1284 reg = <0 0x088e9200 0 0x200>, 1285 <0 0x088e9400 0 0x200>, 1286 <0 0x088e9c00 0 0x400>, 1287 <0 0x088e9600 0 0x200>, 1288 <0 0x088e9800 0 0x200>, 1289 <0 0x088e9a00 0 0x100>; 1290 #clock-cells = <0>; 1291 #phy-cells = <0>; 1292 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1293 clock-names = "pipe0"; 1294 clock-output-names = "usb3_phy_pipe_clk_src"; 1295 }; 1296 1297 dp_phy: dp-phy@88ea200 { 1298 reg = <0 0x088ea200 0 0x200>, 1299 <0 0x088ea400 0 0x200>, 1300 <0 0x088eaa00 0 0x200>, 1301 <0 0x088ea600 0 0x200>, 1302 <0 0x088ea800 0 0x200>; 1303 #phy-cells = <0>; 1304 #clock-cells = <1>; 1305 }; 1306 }; 1307 1308 usb_2: usb@8cf8800 { 1309 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1310 reg = <0 0x08cf8800 0 0x400>; 1311 status = "disabled"; 1312 #address-cells = <2>; 1313 #size-cells = <2>; 1314 ranges; 1315 dma-ranges; 1316 1317 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1318 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1319 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1320 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1321 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1322 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1323 "sleep"; 1324 1325 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1326 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1327 assigned-clock-rates = <19200000>, <200000000>; 1328 1329 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1330 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1331 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1332 interrupt-names = "hs_phy_irq", 1333 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1334 1335 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1336 1337 resets = <&gcc GCC_USB30_SEC_BCR>; 1338 1339 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1340 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1341 interconnect-names = "usb-ddr", "apps-usb"; 1342 1343 usb_2_dwc3: usb@8c00000 { 1344 compatible = "snps,dwc3"; 1345 reg = <0 0x08c00000 0 0xe000>; 1346 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1347 iommus = <&apps_smmu 0xa0 0x0>; 1348 snps,dis_u2_susphy_quirk; 1349 snps,dis_enblslpm_quirk; 1350 phys = <&usb_2_hsphy>; 1351 phy-names = "usb2-phy"; 1352 maximum-speed = "high-speed"; 1353 }; 1354 }; 1355 1356 dc_noc: interconnect@90e0000 { 1357 reg = <0 0x090e0000 0 0x5080>; 1358 compatible = "qcom,sc7280-dc-noc"; 1359 #interconnect-cells = <2>; 1360 qcom,bcm-voters = <&apps_bcm_voter>; 1361 }; 1362 1363 gem_noc: interconnect@9100000 { 1364 reg = <0 0x9100000 0 0xe2200>; 1365 compatible = "qcom,sc7280-gem-noc"; 1366 #interconnect-cells = <2>; 1367 qcom,bcm-voters = <&apps_bcm_voter>; 1368 }; 1369 1370 system-cache-controller@9200000 { 1371 compatible = "qcom,sc7280-llcc"; 1372 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1373 reg-names = "llcc_base", "llcc_broadcast_base"; 1374 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1375 }; 1376 1377 nsp_noc: interconnect@a0c0000 { 1378 reg = <0 0x0a0c0000 0 0x10000>; 1379 compatible = "qcom,sc7280-nsp-noc"; 1380 #interconnect-cells = <2>; 1381 qcom,bcm-voters = <&apps_bcm_voter>; 1382 }; 1383 1384 usb_1: usb@a6f8800 { 1385 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1386 reg = <0 0x0a6f8800 0 0x400>; 1387 status = "disabled"; 1388 #address-cells = <2>; 1389 #size-cells = <2>; 1390 ranges; 1391 dma-ranges; 1392 1393 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1394 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1395 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1396 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1397 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1398 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1399 "sleep"; 1400 1401 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1402 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1403 assigned-clock-rates = <19200000>, <200000000>; 1404 1405 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1406 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1407 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1408 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1409 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1410 "dm_hs_phy_irq", "ss_phy_irq"; 1411 1412 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1413 1414 resets = <&gcc GCC_USB30_PRIM_BCR>; 1415 1416 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1418 interconnect-names = "usb-ddr", "apps-usb"; 1419 1420 usb_1_dwc3: usb@a600000 { 1421 compatible = "snps,dwc3"; 1422 reg = <0 0x0a600000 0 0xe000>; 1423 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1424 iommus = <&apps_smmu 0xe0 0x0>; 1425 snps,dis_u2_susphy_quirk; 1426 snps,dis_enblslpm_quirk; 1427 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1428 phy-names = "usb2-phy", "usb3-phy"; 1429 maximum-speed = "super-speed"; 1430 }; 1431 }; 1432 1433 videocc: clock-controller@aaf0000 { 1434 compatible = "qcom,sc7280-videocc"; 1435 reg = <0 0xaaf0000 0 0x10000>; 1436 clocks = <&rpmhcc RPMH_CXO_CLK>, 1437 <&rpmhcc RPMH_CXO_CLK_A>; 1438 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1439 #clock-cells = <1>; 1440 #reset-cells = <1>; 1441 #power-domain-cells = <1>; 1442 }; 1443 1444 dispcc: clock-controller@af00000 { 1445 compatible = "qcom,sc7280-dispcc"; 1446 reg = <0 0xaf00000 0 0x20000>; 1447 clocks = <&rpmhcc RPMH_CXO_CLK>, 1448 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1449 <0>, <0>, <0>, <0>, <0>, <0>; 1450 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1451 "dsi0_phy_pll_out_byteclk", 1452 "dsi0_phy_pll_out_dsiclk", 1453 "dp_phy_pll_link_clk", 1454 "dp_phy_pll_vco_div_clk", 1455 "edp_phy_pll_link_clk", 1456 "edp_phy_pll_vco_div_clk"; 1457 #clock-cells = <1>; 1458 #reset-cells = <1>; 1459 #power-domain-cells = <1>; 1460 }; 1461 1462 pdc: interrupt-controller@b220000 { 1463 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1464 reg = <0 0x0b220000 0 0x30000>; 1465 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1466 <55 306 4>, <59 312 3>, <62 374 2>, 1467 <64 434 2>, <66 438 3>, <69 86 1>, 1468 <70 520 54>, <124 609 31>, <155 63 1>, 1469 <156 716 12>; 1470 #interrupt-cells = <2>; 1471 interrupt-parent = <&intc>; 1472 interrupt-controller; 1473 }; 1474 1475 pdc_reset: reset-controller@b5e0000 { 1476 compatible = "qcom,sc7280-pdc-global"; 1477 reg = <0 0x0b5e0000 0 0x20000>; 1478 #reset-cells = <1>; 1479 }; 1480 1481 tsens0: thermal-sensor@c263000 { 1482 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1483 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1484 <0 0x0c222000 0 0x1ff>; /* SROT */ 1485 #qcom,sensors = <15>; 1486 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1488 interrupt-names = "uplow","critical"; 1489 #thermal-sensor-cells = <1>; 1490 }; 1491 1492 tsens1: thermal-sensor@c265000 { 1493 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1494 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1495 <0 0x0c223000 0 0x1ff>; /* SROT */ 1496 #qcom,sensors = <12>; 1497 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1499 interrupt-names = "uplow","critical"; 1500 #thermal-sensor-cells = <1>; 1501 }; 1502 1503 aoss_reset: reset-controller@c2a0000 { 1504 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1505 reg = <0 0x0c2a0000 0 0x31000>; 1506 #reset-cells = <1>; 1507 }; 1508 1509 aoss_qmp: power-controller@c300000 { 1510 compatible = "qcom,sc7280-aoss-qmp"; 1511 reg = <0 0x0c300000 0 0x100000>; 1512 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1513 IPCC_MPROC_SIGNAL_GLINK_QMP 1514 IRQ_TYPE_EDGE_RISING>; 1515 mboxes = <&ipcc IPCC_CLIENT_AOP 1516 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1517 1518 #clock-cells = <0>; 1519 #power-domain-cells = <1>; 1520 }; 1521 1522 spmi_bus: spmi@c440000 { 1523 compatible = "qcom,spmi-pmic-arb"; 1524 reg = <0 0x0c440000 0 0x1100>, 1525 <0 0x0c600000 0 0x2000000>, 1526 <0 0x0e600000 0 0x100000>, 1527 <0 0x0e700000 0 0xa0000>, 1528 <0 0x0c40a000 0 0x26000>; 1529 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1530 interrupt-names = "periph_irq"; 1531 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1532 qcom,ee = <0>; 1533 qcom,channel = <0>; 1534 #address-cells = <1>; 1535 #size-cells = <1>; 1536 interrupt-controller; 1537 #interrupt-cells = <4>; 1538 }; 1539 1540 tlmm: pinctrl@f100000 { 1541 compatible = "qcom,sc7280-pinctrl"; 1542 reg = <0 0x0f100000 0 0x300000>; 1543 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1544 gpio-controller; 1545 #gpio-cells = <2>; 1546 interrupt-controller; 1547 #interrupt-cells = <2>; 1548 gpio-ranges = <&tlmm 0 0 175>; 1549 wakeup-parent = <&pdc>; 1550 1551 qup_uart5_default: qup-uart5-default { 1552 pins = "gpio46", "gpio47"; 1553 function = "qup13"; 1554 }; 1555 1556 sdc1_on: sdc1-on { 1557 clk { 1558 pins = "sdc1_clk"; 1559 }; 1560 1561 cmd { 1562 pins = "sdc1_cmd"; 1563 }; 1564 1565 data { 1566 pins = "sdc1_data"; 1567 }; 1568 1569 rclk { 1570 pins = "sdc1_rclk"; 1571 }; 1572 }; 1573 1574 sdc1_off: sdc1-off { 1575 clk { 1576 pins = "sdc1_clk"; 1577 drive-strength = <2>; 1578 bias-bus-hold; 1579 }; 1580 1581 cmd { 1582 pins = "sdc1_cmd"; 1583 drive-strength = <2>; 1584 bias-bus-hold; 1585 }; 1586 1587 data { 1588 pins = "sdc1_data"; 1589 drive-strength = <2>; 1590 bias-bus-hold; 1591 }; 1592 1593 rclk { 1594 pins = "sdc1_rclk"; 1595 bias-bus-hold; 1596 }; 1597 }; 1598 1599 sdc2_on: sdc2-on { 1600 clk { 1601 pins = "sdc2_clk"; 1602 }; 1603 1604 cmd { 1605 pins = "sdc2_cmd"; 1606 }; 1607 1608 data { 1609 pins = "sdc2_data"; 1610 }; 1611 }; 1612 1613 sdc2_off: sdc2-off { 1614 clk { 1615 pins = "sdc2_clk"; 1616 drive-strength = <2>; 1617 bias-bus-hold; 1618 }; 1619 1620 cmd { 1621 pins ="sdc2_cmd"; 1622 drive-strength = <2>; 1623 bias-bus-hold; 1624 }; 1625 1626 data { 1627 pins ="sdc2_data"; 1628 drive-strength = <2>; 1629 bias-bus-hold; 1630 }; 1631 }; 1632 }; 1633 1634 apps_smmu: iommu@15000000 { 1635 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1636 reg = <0 0x15000000 0 0x100000>; 1637 #iommu-cells = <2>; 1638 #global-interrupts = <1>; 1639 dma-coherent; 1640 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1721 }; 1722 1723 intc: interrupt-controller@17a00000 { 1724 compatible = "arm,gic-v3"; 1725 #address-cells = <2>; 1726 #size-cells = <2>; 1727 ranges; 1728 #interrupt-cells = <3>; 1729 interrupt-controller; 1730 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1731 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1732 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1733 1734 gic-its@17a40000 { 1735 compatible = "arm,gic-v3-its"; 1736 msi-controller; 1737 #msi-cells = <1>; 1738 reg = <0 0x17a40000 0 0x20000>; 1739 status = "disabled"; 1740 }; 1741 }; 1742 1743 watchdog@17c10000 { 1744 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1745 reg = <0 0x17c10000 0 0x1000>; 1746 clocks = <&sleep_clk>; 1747 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1748 }; 1749 1750 timer@17c20000 { 1751 #address-cells = <2>; 1752 #size-cells = <2>; 1753 ranges; 1754 compatible = "arm,armv7-timer-mem"; 1755 reg = <0 0x17c20000 0 0x1000>; 1756 1757 frame@17c21000 { 1758 frame-number = <0>; 1759 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1761 reg = <0 0x17c21000 0 0x1000>, 1762 <0 0x17c22000 0 0x1000>; 1763 }; 1764 1765 frame@17c23000 { 1766 frame-number = <1>; 1767 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1768 reg = <0 0x17c23000 0 0x1000>; 1769 status = "disabled"; 1770 }; 1771 1772 frame@17c25000 { 1773 frame-number = <2>; 1774 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1775 reg = <0 0x17c25000 0 0x1000>; 1776 status = "disabled"; 1777 }; 1778 1779 frame@17c27000 { 1780 frame-number = <3>; 1781 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1782 reg = <0 0x17c27000 0 0x1000>; 1783 status = "disabled"; 1784 }; 1785 1786 frame@17c29000 { 1787 frame-number = <4>; 1788 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1789 reg = <0 0x17c29000 0 0x1000>; 1790 status = "disabled"; 1791 }; 1792 1793 frame@17c2b000 { 1794 frame-number = <5>; 1795 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1796 reg = <0 0x17c2b000 0 0x1000>; 1797 status = "disabled"; 1798 }; 1799 1800 frame@17c2d000 { 1801 frame-number = <6>; 1802 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1803 reg = <0 0x17c2d000 0 0x1000>; 1804 status = "disabled"; 1805 }; 1806 }; 1807 1808 apps_rsc: rsc@18200000 { 1809 compatible = "qcom,rpmh-rsc"; 1810 reg = <0 0x18200000 0 0x10000>, 1811 <0 0x18210000 0 0x10000>, 1812 <0 0x18220000 0 0x10000>; 1813 reg-names = "drv-0", "drv-1", "drv-2"; 1814 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1817 qcom,tcs-offset = <0xd00>; 1818 qcom,drv-id = <2>; 1819 qcom,tcs-config = <ACTIVE_TCS 2>, 1820 <SLEEP_TCS 3>, 1821 <WAKE_TCS 3>, 1822 <CONTROL_TCS 1>; 1823 1824 apps_bcm_voter: bcm-voter { 1825 compatible = "qcom,bcm-voter"; 1826 }; 1827 1828 rpmhpd: power-controller { 1829 compatible = "qcom,sc7280-rpmhpd"; 1830 #power-domain-cells = <1>; 1831 operating-points-v2 = <&rpmhpd_opp_table>; 1832 1833 rpmhpd_opp_table: opp-table { 1834 compatible = "operating-points-v2"; 1835 1836 rpmhpd_opp_ret: opp1 { 1837 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1838 }; 1839 1840 rpmhpd_opp_low_svs: opp2 { 1841 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1842 }; 1843 1844 rpmhpd_opp_svs: opp3 { 1845 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1846 }; 1847 1848 rpmhpd_opp_svs_l1: opp4 { 1849 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1850 }; 1851 1852 rpmhpd_opp_svs_l2: opp5 { 1853 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1854 }; 1855 1856 rpmhpd_opp_nom: opp6 { 1857 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1858 }; 1859 1860 rpmhpd_opp_nom_l1: opp7 { 1861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1862 }; 1863 1864 rpmhpd_opp_turbo: opp8 { 1865 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1866 }; 1867 1868 rpmhpd_opp_turbo_l1: opp9 { 1869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1870 }; 1871 }; 1872 }; 1873 1874 rpmhcc: clock-controller { 1875 compatible = "qcom,sc7280-rpmh-clk"; 1876 clocks = <&xo_board>; 1877 clock-names = "xo"; 1878 #clock-cells = <1>; 1879 }; 1880 }; 1881 1882 cpufreq_hw: cpufreq@18591000 { 1883 compatible = "qcom,cpufreq-epss"; 1884 reg = <0 0x18591100 0 0x900>, 1885 <0 0x18592100 0 0x900>, 1886 <0 0x18593100 0 0x900>; 1887 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1888 clock-names = "xo", "alternate"; 1889 #freq-domain-cells = <1>; 1890 }; 1891 }; 1892 1893 thermal_zones: thermal-zones { 1894 cpu0-thermal { 1895 polling-delay-passive = <250>; 1896 polling-delay = <0>; 1897 1898 thermal-sensors = <&tsens0 1>; 1899 1900 trips { 1901 cpu0_alert0: trip-point0 { 1902 temperature = <90000>; 1903 hysteresis = <2000>; 1904 type = "passive"; 1905 }; 1906 1907 cpu0_alert1: trip-point1 { 1908 temperature = <95000>; 1909 hysteresis = <2000>; 1910 type = "passive"; 1911 }; 1912 1913 cpu0_crit: cpu-crit { 1914 temperature = <110000>; 1915 hysteresis = <0>; 1916 type = "critical"; 1917 }; 1918 }; 1919 1920 cooling-maps { 1921 map0 { 1922 trip = <&cpu0_alert0>; 1923 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1924 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1925 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1926 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1927 }; 1928 map1 { 1929 trip = <&cpu0_alert1>; 1930 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1931 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1932 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1933 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1934 }; 1935 }; 1936 }; 1937 1938 cpu1-thermal { 1939 polling-delay-passive = <250>; 1940 polling-delay = <0>; 1941 1942 thermal-sensors = <&tsens0 2>; 1943 1944 trips { 1945 cpu1_alert0: trip-point0 { 1946 temperature = <90000>; 1947 hysteresis = <2000>; 1948 type = "passive"; 1949 }; 1950 1951 cpu1_alert1: trip-point1 { 1952 temperature = <95000>; 1953 hysteresis = <2000>; 1954 type = "passive"; 1955 }; 1956 1957 cpu1_crit: cpu-crit { 1958 temperature = <110000>; 1959 hysteresis = <0>; 1960 type = "critical"; 1961 }; 1962 }; 1963 1964 cooling-maps { 1965 map0 { 1966 trip = <&cpu1_alert0>; 1967 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1968 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1969 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1970 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1971 }; 1972 map1 { 1973 trip = <&cpu1_alert1>; 1974 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1975 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1976 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1977 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1978 }; 1979 }; 1980 }; 1981 1982 cpu2-thermal { 1983 polling-delay-passive = <250>; 1984 polling-delay = <0>; 1985 1986 thermal-sensors = <&tsens0 3>; 1987 1988 trips { 1989 cpu2_alert0: trip-point0 { 1990 temperature = <90000>; 1991 hysteresis = <2000>; 1992 type = "passive"; 1993 }; 1994 1995 cpu2_alert1: trip-point1 { 1996 temperature = <95000>; 1997 hysteresis = <2000>; 1998 type = "passive"; 1999 }; 2000 2001 cpu2_crit: cpu-crit { 2002 temperature = <110000>; 2003 hysteresis = <0>; 2004 type = "critical"; 2005 }; 2006 }; 2007 2008 cooling-maps { 2009 map0 { 2010 trip = <&cpu2_alert0>; 2011 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2012 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2013 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2014 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2015 }; 2016 map1 { 2017 trip = <&cpu2_alert1>; 2018 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2019 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2020 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2021 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2022 }; 2023 }; 2024 }; 2025 2026 cpu3-thermal { 2027 polling-delay-passive = <250>; 2028 polling-delay = <0>; 2029 2030 thermal-sensors = <&tsens0 4>; 2031 2032 trips { 2033 cpu3_alert0: trip-point0 { 2034 temperature = <90000>; 2035 hysteresis = <2000>; 2036 type = "passive"; 2037 }; 2038 2039 cpu3_alert1: trip-point1 { 2040 temperature = <95000>; 2041 hysteresis = <2000>; 2042 type = "passive"; 2043 }; 2044 2045 cpu3_crit: cpu-crit { 2046 temperature = <110000>; 2047 hysteresis = <0>; 2048 type = "critical"; 2049 }; 2050 }; 2051 2052 cooling-maps { 2053 map0 { 2054 trip = <&cpu3_alert0>; 2055 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2056 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2057 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2058 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2059 }; 2060 map1 { 2061 trip = <&cpu3_alert1>; 2062 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2063 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2064 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2065 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2066 }; 2067 }; 2068 }; 2069 2070 cpu4-thermal { 2071 polling-delay-passive = <250>; 2072 polling-delay = <0>; 2073 2074 thermal-sensors = <&tsens0 7>; 2075 2076 trips { 2077 cpu4_alert0: trip-point0 { 2078 temperature = <90000>; 2079 hysteresis = <2000>; 2080 type = "passive"; 2081 }; 2082 2083 cpu4_alert1: trip-point1 { 2084 temperature = <95000>; 2085 hysteresis = <2000>; 2086 type = "passive"; 2087 }; 2088 2089 cpu4_crit: cpu-crit { 2090 temperature = <110000>; 2091 hysteresis = <0>; 2092 type = "critical"; 2093 }; 2094 }; 2095 2096 cooling-maps { 2097 map0 { 2098 trip = <&cpu4_alert0>; 2099 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2100 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2101 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2102 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2103 }; 2104 map1 { 2105 trip = <&cpu4_alert1>; 2106 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2107 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2108 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2110 }; 2111 }; 2112 }; 2113 2114 cpu5-thermal { 2115 polling-delay-passive = <250>; 2116 polling-delay = <0>; 2117 2118 thermal-sensors = <&tsens0 8>; 2119 2120 trips { 2121 cpu5_alert0: trip-point0 { 2122 temperature = <90000>; 2123 hysteresis = <2000>; 2124 type = "passive"; 2125 }; 2126 2127 cpu5_alert1: trip-point1 { 2128 temperature = <95000>; 2129 hysteresis = <2000>; 2130 type = "passive"; 2131 }; 2132 2133 cpu5_crit: cpu-crit { 2134 temperature = <110000>; 2135 hysteresis = <0>; 2136 type = "critical"; 2137 }; 2138 }; 2139 2140 cooling-maps { 2141 map0 { 2142 trip = <&cpu5_alert0>; 2143 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2144 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2145 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2146 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2147 }; 2148 map1 { 2149 trip = <&cpu5_alert1>; 2150 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2151 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2152 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2153 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2154 }; 2155 }; 2156 }; 2157 2158 cpu6-thermal { 2159 polling-delay-passive = <250>; 2160 polling-delay = <0>; 2161 2162 thermal-sensors = <&tsens0 9>; 2163 2164 trips { 2165 cpu6_alert0: trip-point0 { 2166 temperature = <90000>; 2167 hysteresis = <2000>; 2168 type = "passive"; 2169 }; 2170 2171 cpu6_alert1: trip-point1 { 2172 temperature = <95000>; 2173 hysteresis = <2000>; 2174 type = "passive"; 2175 }; 2176 2177 cpu6_crit: cpu-crit { 2178 temperature = <110000>; 2179 hysteresis = <0>; 2180 type = "critical"; 2181 }; 2182 }; 2183 2184 cooling-maps { 2185 map0 { 2186 trip = <&cpu6_alert0>; 2187 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2188 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2189 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2190 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2191 }; 2192 map1 { 2193 trip = <&cpu6_alert1>; 2194 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2195 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2196 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2197 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2198 }; 2199 }; 2200 }; 2201 2202 cpu7-thermal { 2203 polling-delay-passive = <250>; 2204 polling-delay = <0>; 2205 2206 thermal-sensors = <&tsens0 10>; 2207 2208 trips { 2209 cpu7_alert0: trip-point0 { 2210 temperature = <90000>; 2211 hysteresis = <2000>; 2212 type = "passive"; 2213 }; 2214 2215 cpu7_alert1: trip-point1 { 2216 temperature = <95000>; 2217 hysteresis = <2000>; 2218 type = "passive"; 2219 }; 2220 2221 cpu7_crit: cpu-crit { 2222 temperature = <110000>; 2223 hysteresis = <0>; 2224 type = "critical"; 2225 }; 2226 }; 2227 2228 cooling-maps { 2229 map0 { 2230 trip = <&cpu7_alert0>; 2231 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2232 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2233 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2234 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2235 }; 2236 map1 { 2237 trip = <&cpu7_alert1>; 2238 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2239 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2240 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2241 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2242 }; 2243 }; 2244 }; 2245 2246 cpu8-thermal { 2247 polling-delay-passive = <250>; 2248 polling-delay = <0>; 2249 2250 thermal-sensors = <&tsens0 11>; 2251 2252 trips { 2253 cpu8_alert0: trip-point0 { 2254 temperature = <90000>; 2255 hysteresis = <2000>; 2256 type = "passive"; 2257 }; 2258 2259 cpu8_alert1: trip-point1 { 2260 temperature = <95000>; 2261 hysteresis = <2000>; 2262 type = "passive"; 2263 }; 2264 2265 cpu8_crit: cpu-crit { 2266 temperature = <110000>; 2267 hysteresis = <0>; 2268 type = "critical"; 2269 }; 2270 }; 2271 2272 cooling-maps { 2273 map0 { 2274 trip = <&cpu8_alert0>; 2275 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2276 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2277 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2278 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2279 }; 2280 map1 { 2281 trip = <&cpu8_alert1>; 2282 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2283 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2284 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2285 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2286 }; 2287 }; 2288 }; 2289 2290 cpu9-thermal { 2291 polling-delay-passive = <250>; 2292 polling-delay = <0>; 2293 2294 thermal-sensors = <&tsens0 12>; 2295 2296 trips { 2297 cpu9_alert0: trip-point0 { 2298 temperature = <90000>; 2299 hysteresis = <2000>; 2300 type = "passive"; 2301 }; 2302 2303 cpu9_alert1: trip-point1 { 2304 temperature = <95000>; 2305 hysteresis = <2000>; 2306 type = "passive"; 2307 }; 2308 2309 cpu9_crit: cpu-crit { 2310 temperature = <110000>; 2311 hysteresis = <0>; 2312 type = "critical"; 2313 }; 2314 }; 2315 2316 cooling-maps { 2317 map0 { 2318 trip = <&cpu9_alert0>; 2319 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2320 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2321 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2322 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2323 }; 2324 map1 { 2325 trip = <&cpu9_alert1>; 2326 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2327 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2328 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2329 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2330 }; 2331 }; 2332 }; 2333 2334 cpu10-thermal { 2335 polling-delay-passive = <250>; 2336 polling-delay = <0>; 2337 2338 thermal-sensors = <&tsens0 13>; 2339 2340 trips { 2341 cpu10_alert0: trip-point0 { 2342 temperature = <90000>; 2343 hysteresis = <2000>; 2344 type = "passive"; 2345 }; 2346 2347 cpu10_alert1: trip-point1 { 2348 temperature = <95000>; 2349 hysteresis = <2000>; 2350 type = "passive"; 2351 }; 2352 2353 cpu10_crit: cpu-crit { 2354 temperature = <110000>; 2355 hysteresis = <0>; 2356 type = "critical"; 2357 }; 2358 }; 2359 2360 cooling-maps { 2361 map0 { 2362 trip = <&cpu10_alert0>; 2363 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2364 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2365 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2366 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2367 }; 2368 map1 { 2369 trip = <&cpu10_alert1>; 2370 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2371 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2372 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2373 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2374 }; 2375 }; 2376 }; 2377 2378 cpu11-thermal { 2379 polling-delay-passive = <250>; 2380 polling-delay = <0>; 2381 2382 thermal-sensors = <&tsens0 14>; 2383 2384 trips { 2385 cpu11_alert0: trip-point0 { 2386 temperature = <90000>; 2387 hysteresis = <2000>; 2388 type = "passive"; 2389 }; 2390 2391 cpu11_alert1: trip-point1 { 2392 temperature = <95000>; 2393 hysteresis = <2000>; 2394 type = "passive"; 2395 }; 2396 2397 cpu11_crit: cpu-crit { 2398 temperature = <110000>; 2399 hysteresis = <0>; 2400 type = "critical"; 2401 }; 2402 }; 2403 2404 cooling-maps { 2405 map0 { 2406 trip = <&cpu11_alert0>; 2407 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2408 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2409 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2410 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2411 }; 2412 map1 { 2413 trip = <&cpu11_alert1>; 2414 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2415 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2416 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2417 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2418 }; 2419 }; 2420 }; 2421 2422 aoss0-thermal { 2423 polling-delay-passive = <0>; 2424 polling-delay = <0>; 2425 2426 thermal-sensors = <&tsens0 0>; 2427 2428 trips { 2429 aoss0_alert0: trip-point0 { 2430 temperature = <90000>; 2431 hysteresis = <2000>; 2432 type = "hot"; 2433 }; 2434 2435 aoss0_crit: aoss0-crit { 2436 temperature = <110000>; 2437 hysteresis = <0>; 2438 type = "critical"; 2439 }; 2440 }; 2441 }; 2442 2443 aoss1-thermal { 2444 polling-delay-passive = <0>; 2445 polling-delay = <0>; 2446 2447 thermal-sensors = <&tsens1 0>; 2448 2449 trips { 2450 aoss1_alert0: trip-point0 { 2451 temperature = <90000>; 2452 hysteresis = <2000>; 2453 type = "hot"; 2454 }; 2455 2456 aoss1_crit: aoss1-crit { 2457 temperature = <110000>; 2458 hysteresis = <0>; 2459 type = "critical"; 2460 }; 2461 }; 2462 }; 2463 2464 cpuss0-thermal { 2465 polling-delay-passive = <0>; 2466 polling-delay = <0>; 2467 2468 thermal-sensors = <&tsens0 5>; 2469 2470 trips { 2471 cpuss0_alert0: trip-point0 { 2472 temperature = <90000>; 2473 hysteresis = <2000>; 2474 type = "hot"; 2475 }; 2476 cpuss0_crit: cluster0-crit { 2477 temperature = <110000>; 2478 hysteresis = <0>; 2479 type = "critical"; 2480 }; 2481 }; 2482 }; 2483 2484 cpuss1-thermal { 2485 polling-delay-passive = <0>; 2486 polling-delay = <0>; 2487 2488 thermal-sensors = <&tsens0 6>; 2489 2490 trips { 2491 cpuss1_alert0: trip-point0 { 2492 temperature = <90000>; 2493 hysteresis = <2000>; 2494 type = "hot"; 2495 }; 2496 cpuss1_crit: cluster0-crit { 2497 temperature = <110000>; 2498 hysteresis = <0>; 2499 type = "critical"; 2500 }; 2501 }; 2502 }; 2503 2504 gpuss0-thermal { 2505 polling-delay-passive = <0>; 2506 polling-delay = <0>; 2507 2508 thermal-sensors = <&tsens1 1>; 2509 2510 trips { 2511 gpuss0_alert0: trip-point0 { 2512 temperature = <90000>; 2513 hysteresis = <2000>; 2514 type = "hot"; 2515 }; 2516 2517 gpuss0_crit: gpuss0-crit { 2518 temperature = <110000>; 2519 hysteresis = <0>; 2520 type = "critical"; 2521 }; 2522 }; 2523 }; 2524 2525 gpuss1-thermal { 2526 polling-delay-passive = <0>; 2527 polling-delay = <0>; 2528 2529 thermal-sensors = <&tsens1 2>; 2530 2531 trips { 2532 gpuss1_alert0: trip-point0 { 2533 temperature = <90000>; 2534 hysteresis = <2000>; 2535 type = "hot"; 2536 }; 2537 2538 gpuss1_crit: gpuss1-crit { 2539 temperature = <110000>; 2540 hysteresis = <0>; 2541 type = "critical"; 2542 }; 2543 }; 2544 }; 2545 2546 nspss0-thermal { 2547 polling-delay-passive = <0>; 2548 polling-delay = <0>; 2549 2550 thermal-sensors = <&tsens1 3>; 2551 2552 trips { 2553 nspss0_alert0: trip-point0 { 2554 temperature = <90000>; 2555 hysteresis = <2000>; 2556 type = "hot"; 2557 }; 2558 2559 nspss0_crit: nspss0-crit { 2560 temperature = <110000>; 2561 hysteresis = <0>; 2562 type = "critical"; 2563 }; 2564 }; 2565 }; 2566 2567 nspss1-thermal { 2568 polling-delay-passive = <0>; 2569 polling-delay = <0>; 2570 2571 thermal-sensors = <&tsens1 4>; 2572 2573 trips { 2574 nspss1_alert0: trip-point0 { 2575 temperature = <90000>; 2576 hysteresis = <2000>; 2577 type = "hot"; 2578 }; 2579 2580 nspss1_crit: nspss1-crit { 2581 temperature = <110000>; 2582 hysteresis = <0>; 2583 type = "critical"; 2584 }; 2585 }; 2586 }; 2587 2588 video-thermal { 2589 polling-delay-passive = <0>; 2590 polling-delay = <0>; 2591 2592 thermal-sensors = <&tsens1 5>; 2593 2594 trips { 2595 video_alert0: trip-point0 { 2596 temperature = <90000>; 2597 hysteresis = <2000>; 2598 type = "hot"; 2599 }; 2600 2601 video_crit: video-crit { 2602 temperature = <110000>; 2603 hysteresis = <0>; 2604 type = "critical"; 2605 }; 2606 }; 2607 }; 2608 2609 ddr-thermal { 2610 polling-delay-passive = <0>; 2611 polling-delay = <0>; 2612 2613 thermal-sensors = <&tsens1 6>; 2614 2615 trips { 2616 ddr_alert0: trip-point0 { 2617 temperature = <90000>; 2618 hysteresis = <2000>; 2619 type = "hot"; 2620 }; 2621 2622 ddr_crit: ddr-crit { 2623 temperature = <110000>; 2624 hysteresis = <0>; 2625 type = "critical"; 2626 }; 2627 }; 2628 }; 2629 2630 mdmss0-thermal { 2631 polling-delay-passive = <0>; 2632 polling-delay = <0>; 2633 2634 thermal-sensors = <&tsens1 7>; 2635 2636 trips { 2637 mdmss0_alert0: trip-point0 { 2638 temperature = <90000>; 2639 hysteresis = <2000>; 2640 type = "hot"; 2641 }; 2642 2643 mdmss0_crit: mdmss0-crit { 2644 temperature = <110000>; 2645 hysteresis = <0>; 2646 type = "critical"; 2647 }; 2648 }; 2649 }; 2650 2651 mdmss1-thermal { 2652 polling-delay-passive = <0>; 2653 polling-delay = <0>; 2654 2655 thermal-sensors = <&tsens1 8>; 2656 2657 trips { 2658 mdmss1_alert0: trip-point0 { 2659 temperature = <90000>; 2660 hysteresis = <2000>; 2661 type = "hot"; 2662 }; 2663 2664 mdmss1_crit: mdmss1-crit { 2665 temperature = <110000>; 2666 hysteresis = <0>; 2667 type = "critical"; 2668 }; 2669 }; 2670 }; 2671 2672 mdmss2-thermal { 2673 polling-delay-passive = <0>; 2674 polling-delay = <0>; 2675 2676 thermal-sensors = <&tsens1 9>; 2677 2678 trips { 2679 mdmss2_alert0: trip-point0 { 2680 temperature = <90000>; 2681 hysteresis = <2000>; 2682 type = "hot"; 2683 }; 2684 2685 mdmss2_crit: mdmss2-crit { 2686 temperature = <110000>; 2687 hysteresis = <0>; 2688 type = "critical"; 2689 }; 2690 }; 2691 }; 2692 2693 mdmss3-thermal { 2694 polling-delay-passive = <0>; 2695 polling-delay = <0>; 2696 2697 thermal-sensors = <&tsens1 10>; 2698 2699 trips { 2700 mdmss3_alert0: trip-point0 { 2701 temperature = <90000>; 2702 hysteresis = <2000>; 2703 type = "hot"; 2704 }; 2705 2706 mdmss3_crit: mdmss3-crit { 2707 temperature = <110000>; 2708 hysteresis = <0>; 2709 type = "critical"; 2710 }; 2711 }; 2712 }; 2713 2714 camera0-thermal { 2715 polling-delay-passive = <0>; 2716 polling-delay = <0>; 2717 2718 thermal-sensors = <&tsens1 11>; 2719 2720 trips { 2721 camera0_alert0: trip-point0 { 2722 temperature = <90000>; 2723 hysteresis = <2000>; 2724 type = "hot"; 2725 }; 2726 2727 camera0_crit: camera0-crit { 2728 temperature = <110000>; 2729 hysteresis = <0>; 2730 type = "critical"; 2731 }; 2732 }; 2733 }; 2734 }; 2735 2736 timer { 2737 compatible = "arm,armv8-timer"; 2738 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2739 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2740 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2741 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2742 }; 2743}; 2744