1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-aoss-qmp.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/reset/qcom,sdm845-aoss.h> 15#include <dt-bindings/reset/qcom,sdm845-pdc.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 clock-frequency = <76800000>; 31 #clock-cells = <0>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32000>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 reserved-memory { 42 #address-cells = <2>; 43 #size-cells = <2>; 44 ranges; 45 46 aop_mem: memory@80800000 { 47 reg = <0x0 0x80800000 0x0 0x60000>; 48 no-map; 49 }; 50 51 aop_cmd_db_mem: memory@80860000 { 52 reg = <0x0 0x80860000 0x0 0x20000>; 53 compatible = "qcom,cmd-db"; 54 no-map; 55 }; 56 57 smem_mem: memory@80900000 { 58 reg = <0x0 0x80900000 0x0 0x200000>; 59 no-map; 60 }; 61 62 cpucp_mem: memory@80b00000 { 63 no-map; 64 reg = <0x0 0x80b00000 0x0 0x100000>; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <2>; 70 #size-cells = <0>; 71 72 CPU0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,kryo"; 75 reg = <0x0 0x0>; 76 enable-method = "psci"; 77 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 78 &LITTLE_CPU_SLEEP_1 79 &CLUSTER_SLEEP_0>; 80 next-level-cache = <&L2_0>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 L2_0: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 L3_0: l3-cache { 87 compatible = "cache"; 88 }; 89 }; 90 }; 91 92 CPU1: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,kryo"; 95 reg = <0x0 0x100>; 96 enable-method = "psci"; 97 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 98 &LITTLE_CPU_SLEEP_1 99 &CLUSTER_SLEEP_0>; 100 next-level-cache = <&L2_100>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 #cooling-cells = <2>; 103 L2_100: l2-cache { 104 compatible = "cache"; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU2: cpu@200 { 110 device_type = "cpu"; 111 compatible = "arm,kryo"; 112 reg = <0x0 0x200>; 113 enable-method = "psci"; 114 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 115 &LITTLE_CPU_SLEEP_1 116 &CLUSTER_SLEEP_0>; 117 next-level-cache = <&L2_200>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 #cooling-cells = <2>; 120 L2_200: l2-cache { 121 compatible = "cache"; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "arm,kryo"; 129 reg = <0x0 0x300>; 130 enable-method = "psci"; 131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 132 &LITTLE_CPU_SLEEP_1 133 &CLUSTER_SLEEP_0>; 134 next-level-cache = <&L2_300>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 #cooling-cells = <2>; 137 L2_300: l2-cache { 138 compatible = "cache"; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU4: cpu@400 { 144 device_type = "cpu"; 145 compatible = "arm,kryo"; 146 reg = <0x0 0x400>; 147 enable-method = "psci"; 148 cpu-idle-states = <&BIG_CPU_SLEEP_0 149 &BIG_CPU_SLEEP_1 150 &CLUSTER_SLEEP_0>; 151 next-level-cache = <&L2_400>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 #cooling-cells = <2>; 154 L2_400: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU5: cpu@500 { 161 device_type = "cpu"; 162 compatible = "arm,kryo"; 163 reg = <0x0 0x500>; 164 enable-method = "psci"; 165 cpu-idle-states = <&BIG_CPU_SLEEP_0 166 &BIG_CPU_SLEEP_1 167 &CLUSTER_SLEEP_0>; 168 next-level-cache = <&L2_500>; 169 qcom,freq-domain = <&cpufreq_hw 1>; 170 #cooling-cells = <2>; 171 L2_500: l2-cache { 172 compatible = "cache"; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU6: cpu@600 { 178 device_type = "cpu"; 179 compatible = "arm,kryo"; 180 reg = <0x0 0x600>; 181 enable-method = "psci"; 182 cpu-idle-states = <&BIG_CPU_SLEEP_0 183 &BIG_CPU_SLEEP_1 184 &CLUSTER_SLEEP_0>; 185 next-level-cache = <&L2_600>; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 #cooling-cells = <2>; 188 L2_600: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "arm,kryo"; 197 reg = <0x0 0x700>; 198 enable-method = "psci"; 199 cpu-idle-states = <&BIG_CPU_SLEEP_0 200 &BIG_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_700>; 203 qcom,freq-domain = <&cpufreq_hw 1>; 204 #cooling-cells = <2>; 205 L2_700: l2-cache { 206 compatible = "cache"; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 215 compatible = "arm,idle-state"; 216 idle-state-name = "little-power-down"; 217 arm,psci-suspend-param = <0x40000003>; 218 entry-latency-us = <549>; 219 exit-latency-us = <901>; 220 min-residency-us = <1774>; 221 local-timer-stop; 222 }; 223 224 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 225 compatible = "arm,idle-state"; 226 idle-state-name = "little-rail-power-down"; 227 arm,psci-suspend-param = <0x40000004>; 228 entry-latency-us = <702>; 229 exit-latency-us = <915>; 230 min-residency-us = <4001>; 231 local-timer-stop; 232 }; 233 234 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 235 compatible = "arm,idle-state"; 236 idle-state-name = "big-power-down"; 237 arm,psci-suspend-param = <0x40000003>; 238 entry-latency-us = <523>; 239 exit-latency-us = <1244>; 240 min-residency-us = <2207>; 241 local-timer-stop; 242 }; 243 244 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 245 compatible = "arm,idle-state"; 246 idle-state-name = "big-rail-power-down"; 247 arm,psci-suspend-param = <0x40000004>; 248 entry-latency-us = <526>; 249 exit-latency-us = <1854>; 250 min-residency-us = <5555>; 251 local-timer-stop; 252 }; 253 254 CLUSTER_SLEEP_0: cluster-sleep-0 { 255 compatible = "arm,idle-state"; 256 idle-state-name = "cluster-power-down"; 257 arm,psci-suspend-param = <0x40003444>; 258 entry-latency-us = <3263>; 259 exit-latency-us = <6562>; 260 min-residency-us = <9926>; 261 local-timer-stop; 262 }; 263 }; 264 }; 265 266 memory@80000000 { 267 device_type = "memory"; 268 /* We expect the bootloader to fill in the size */ 269 reg = <0 0x80000000 0 0>; 270 }; 271 272 firmware { 273 scm { 274 compatible = "qcom,scm-sc7280", "qcom,scm"; 275 }; 276 }; 277 278 smem { 279 compatible = "qcom,smem"; 280 memory-region = <&smem_mem>; 281 hwlocks = <&tcsr_mutex 3>; 282 }; 283 284 smp2p-adsp { 285 compatible = "qcom,smp2p"; 286 qcom,smem = <443>, <429>; 287 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 288 IPCC_MPROC_SIGNAL_SMP2P 289 IRQ_TYPE_EDGE_RISING>; 290 mboxes = <&ipcc IPCC_CLIENT_LPASS 291 IPCC_MPROC_SIGNAL_SMP2P>; 292 293 qcom,local-pid = <0>; 294 qcom,remote-pid = <2>; 295 296 adsp_smp2p_out: master-kernel { 297 qcom,entry-name = "master-kernel"; 298 #qcom,smem-state-cells = <1>; 299 }; 300 301 adsp_smp2p_in: slave-kernel { 302 qcom,entry-name = "slave-kernel"; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 }; 306 }; 307 308 smp2p-cdsp { 309 compatible = "qcom,smp2p"; 310 qcom,smem = <94>, <432>; 311 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 312 IPCC_MPROC_SIGNAL_SMP2P 313 IRQ_TYPE_EDGE_RISING>; 314 mboxes = <&ipcc IPCC_CLIENT_CDSP 315 IPCC_MPROC_SIGNAL_SMP2P>; 316 317 qcom,local-pid = <0>; 318 qcom,remote-pid = <5>; 319 320 cdsp_smp2p_out: master-kernel { 321 qcom,entry-name = "master-kernel"; 322 #qcom,smem-state-cells = <1>; 323 }; 324 325 cdsp_smp2p_in: slave-kernel { 326 qcom,entry-name = "slave-kernel"; 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 }; 330 }; 331 332 smp2p-mpss { 333 compatible = "qcom,smp2p"; 334 qcom,smem = <435>, <428>; 335 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 336 IPCC_MPROC_SIGNAL_SMP2P 337 IRQ_TYPE_EDGE_RISING>; 338 mboxes = <&ipcc IPCC_CLIENT_MPSS 339 IPCC_MPROC_SIGNAL_SMP2P>; 340 341 qcom,local-pid = <0>; 342 qcom,remote-pid = <1>; 343 344 modem_smp2p_out: master-kernel { 345 qcom,entry-name = "master-kernel"; 346 #qcom,smem-state-cells = <1>; 347 }; 348 349 modem_smp2p_in: slave-kernel { 350 qcom,entry-name = "slave-kernel"; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 }; 354 355 ipa_smp2p_out: ipa-ap-to-modem { 356 qcom,entry-name = "ipa"; 357 #qcom,smem-state-cells = <1>; 358 }; 359 360 ipa_smp2p_in: ipa-modem-to-ap { 361 qcom,entry-name = "ipa"; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 }; 365 }; 366 367 smp2p-wpss { 368 compatible = "qcom,smp2p"; 369 qcom,smem = <617>, <616>; 370 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 371 IPCC_MPROC_SIGNAL_SMP2P 372 IRQ_TYPE_EDGE_RISING>; 373 mboxes = <&ipcc IPCC_CLIENT_WPSS 374 IPCC_MPROC_SIGNAL_SMP2P>; 375 376 qcom,local-pid = <0>; 377 qcom,remote-pid = <13>; 378 379 wpss_smp2p_out: master-kernel { 380 qcom,entry-name = "master-kernel"; 381 #qcom,smem-state-cells = <1>; 382 }; 383 384 wpss_smp2p_in: slave-kernel { 385 qcom,entry-name = "slave-kernel"; 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 }; 389 }; 390 391 pmu { 392 compatible = "arm,armv8-pmuv3"; 393 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 394 }; 395 396 psci { 397 compatible = "arm,psci-1.0"; 398 method = "smc"; 399 }; 400 401 soc: soc@0 { 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges = <0 0 0 0 0x10 0>; 405 dma-ranges = <0 0 0 0 0x10 0>; 406 compatible = "simple-bus"; 407 408 gcc: clock-controller@100000 { 409 compatible = "qcom,gcc-sc7280"; 410 reg = <0 0x00100000 0 0x1f0000>; 411 clocks = <&rpmhcc RPMH_CXO_CLK>, 412 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 413 <0>, <0>, <0>, <0>, <0>, <0>; 414 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 415 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 416 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 417 "ufs_phy_tx_symbol_0_clk", 418 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 419 #clock-cells = <1>; 420 #reset-cells = <1>; 421 #power-domain-cells = <1>; 422 }; 423 424 ipcc: mailbox@408000 { 425 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 426 reg = <0 0x00408000 0 0x1000>; 427 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-controller; 429 #interrupt-cells = <3>; 430 #mbox-cells = <2>; 431 }; 432 433 qupv3_id_0: geniqup@9c0000 { 434 compatible = "qcom,geni-se-qup"; 435 reg = <0 0x009c0000 0 0x2000>; 436 clock-names = "m-ahb", "s-ahb"; 437 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 438 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 439 #address-cells = <2>; 440 #size-cells = <2>; 441 ranges; 442 status = "disabled"; 443 444 uart5: serial@994000 { 445 compatible = "qcom,geni-debug-uart"; 446 reg = <0 0x00994000 0 0x4000>; 447 clock-names = "se"; 448 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&qup_uart5_default>; 451 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 452 status = "disabled"; 453 }; 454 }; 455 456 tcsr_mutex: hwlock@1f40000 { 457 compatible = "qcom,tcsr-mutex", "syscon"; 458 reg = <0 0x01f40000 0 0x40000>; 459 #hwlock-cells = <1>; 460 }; 461 462 lpasscc: lpasscc@3000000 { 463 compatible = "qcom,sc7280-lpasscc"; 464 reg = <0 0x03000000 0 0x40>, 465 <0 0x03c04000 0 0x4>, 466 <0 0x03389000 0 0x24>; 467 reg-names = "qdsp6ss", "top_cc", "cc"; 468 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 469 clock-names = "iface"; 470 #clock-cells = <1>; 471 }; 472 473 gpucc: clock-controller@3d90000 { 474 compatible = "qcom,sc7280-gpucc"; 475 reg = <0 0x03d90000 0 0x9000>; 476 clocks = <&rpmhcc RPMH_CXO_CLK>, 477 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 478 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 479 clock-names = "bi_tcxo", 480 "gcc_gpu_gpll0_clk_src", 481 "gcc_gpu_gpll0_div_clk_src"; 482 #clock-cells = <1>; 483 #reset-cells = <1>; 484 #power-domain-cells = <1>; 485 }; 486 487 stm@6002000 { 488 compatible = "arm,coresight-stm", "arm,primecell"; 489 reg = <0 0x06002000 0 0x1000>, 490 <0 0x16280000 0 0x180000>; 491 reg-names = "stm-base", "stm-stimulus-base"; 492 493 clocks = <&aoss_qmp>; 494 clock-names = "apb_pclk"; 495 496 out-ports { 497 port { 498 stm_out: endpoint { 499 remote-endpoint = <&funnel0_in7>; 500 }; 501 }; 502 }; 503 }; 504 505 funnel@6041000 { 506 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 507 reg = <0 0x06041000 0 0x1000>; 508 509 clocks = <&aoss_qmp>; 510 clock-names = "apb_pclk"; 511 512 out-ports { 513 port { 514 funnel0_out: endpoint { 515 remote-endpoint = <&merge_funnel_in0>; 516 }; 517 }; 518 }; 519 520 in-ports { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 524 port@7 { 525 reg = <7>; 526 funnel0_in7: endpoint { 527 remote-endpoint = <&stm_out>; 528 }; 529 }; 530 }; 531 }; 532 533 funnel@6042000 { 534 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 535 reg = <0 0x06042000 0 0x1000>; 536 537 clocks = <&aoss_qmp>; 538 clock-names = "apb_pclk"; 539 540 out-ports { 541 port { 542 funnel1_out: endpoint { 543 remote-endpoint = <&merge_funnel_in1>; 544 }; 545 }; 546 }; 547 548 in-ports { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 552 port@4 { 553 reg = <4>; 554 funnel1_in4: endpoint { 555 remote-endpoint = <&apss_merge_funnel_out>; 556 }; 557 }; 558 }; 559 }; 560 561 funnel@6045000 { 562 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 563 reg = <0 0x06045000 0 0x1000>; 564 565 clocks = <&aoss_qmp>; 566 clock-names = "apb_pclk"; 567 568 out-ports { 569 port { 570 merge_funnel_out: endpoint { 571 remote-endpoint = <&swao_funnel_in>; 572 }; 573 }; 574 }; 575 576 in-ports { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 580 port@0 { 581 reg = <0>; 582 merge_funnel_in0: endpoint { 583 remote-endpoint = <&funnel0_out>; 584 }; 585 }; 586 587 port@1 { 588 reg = <1>; 589 merge_funnel_in1: endpoint { 590 remote-endpoint = <&funnel1_out>; 591 }; 592 }; 593 }; 594 }; 595 596 replicator@6046000 { 597 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 598 reg = <0 0x06046000 0 0x1000>; 599 600 clocks = <&aoss_qmp>; 601 clock-names = "apb_pclk"; 602 603 out-ports { 604 port { 605 replicator_out: endpoint { 606 remote-endpoint = <&etr_in>; 607 }; 608 }; 609 }; 610 611 in-ports { 612 port { 613 replicator_in: endpoint { 614 remote-endpoint = <&swao_replicator_out>; 615 }; 616 }; 617 }; 618 }; 619 620 etr@6048000 { 621 compatible = "arm,coresight-tmc", "arm,primecell"; 622 reg = <0 0x06048000 0 0x1000>; 623 iommus = <&apps_smmu 0x04c0 0>; 624 625 clocks = <&aoss_qmp>; 626 clock-names = "apb_pclk"; 627 arm,scatter-gather; 628 629 in-ports { 630 port { 631 etr_in: endpoint { 632 remote-endpoint = <&replicator_out>; 633 }; 634 }; 635 }; 636 }; 637 638 funnel@6b04000 { 639 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 640 reg = <0 0x06b04000 0 0x1000>; 641 642 clocks = <&aoss_qmp>; 643 clock-names = "apb_pclk"; 644 645 out-ports { 646 port { 647 swao_funnel_out: endpoint { 648 remote-endpoint = <&etf_in>; 649 }; 650 }; 651 }; 652 653 in-ports { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 657 port@7 { 658 reg = <7>; 659 swao_funnel_in: endpoint { 660 remote-endpoint = <&merge_funnel_out>; 661 }; 662 }; 663 }; 664 }; 665 666 etf@6b05000 { 667 compatible = "arm,coresight-tmc", "arm,primecell"; 668 reg = <0 0x06b05000 0 0x1000>; 669 670 clocks = <&aoss_qmp>; 671 clock-names = "apb_pclk"; 672 673 out-ports { 674 port { 675 etf_out: endpoint { 676 remote-endpoint = <&swao_replicator_in>; 677 }; 678 }; 679 }; 680 681 in-ports { 682 port { 683 etf_in: endpoint { 684 remote-endpoint = <&swao_funnel_out>; 685 }; 686 }; 687 }; 688 }; 689 690 replicator@6b06000 { 691 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 692 reg = <0 0x06b06000 0 0x1000>; 693 694 clocks = <&aoss_qmp>; 695 clock-names = "apb_pclk"; 696 qcom,replicator-loses-context; 697 698 out-ports { 699 port { 700 swao_replicator_out: endpoint { 701 remote-endpoint = <&replicator_in>; 702 }; 703 }; 704 }; 705 706 in-ports { 707 port { 708 swao_replicator_in: endpoint { 709 remote-endpoint = <&etf_out>; 710 }; 711 }; 712 }; 713 }; 714 715 etm@7040000 { 716 compatible = "arm,coresight-etm4x", "arm,primecell"; 717 reg = <0 0x07040000 0 0x1000>; 718 719 cpu = <&CPU0>; 720 721 clocks = <&aoss_qmp>; 722 clock-names = "apb_pclk"; 723 arm,coresight-loses-context-with-cpu; 724 qcom,skip-power-up; 725 726 out-ports { 727 port { 728 etm0_out: endpoint { 729 remote-endpoint = <&apss_funnel_in0>; 730 }; 731 }; 732 }; 733 }; 734 735 etm@7140000 { 736 compatible = "arm,coresight-etm4x", "arm,primecell"; 737 reg = <0 0x07140000 0 0x1000>; 738 739 cpu = <&CPU1>; 740 741 clocks = <&aoss_qmp>; 742 clock-names = "apb_pclk"; 743 arm,coresight-loses-context-with-cpu; 744 qcom,skip-power-up; 745 746 out-ports { 747 port { 748 etm1_out: endpoint { 749 remote-endpoint = <&apss_funnel_in1>; 750 }; 751 }; 752 }; 753 }; 754 755 etm@7240000 { 756 compatible = "arm,coresight-etm4x", "arm,primecell"; 757 reg = <0 0x07240000 0 0x1000>; 758 759 cpu = <&CPU2>; 760 761 clocks = <&aoss_qmp>; 762 clock-names = "apb_pclk"; 763 arm,coresight-loses-context-with-cpu; 764 qcom,skip-power-up; 765 766 out-ports { 767 port { 768 etm2_out: endpoint { 769 remote-endpoint = <&apss_funnel_in2>; 770 }; 771 }; 772 }; 773 }; 774 775 etm@7340000 { 776 compatible = "arm,coresight-etm4x", "arm,primecell"; 777 reg = <0 0x07340000 0 0x1000>; 778 779 cpu = <&CPU3>; 780 781 clocks = <&aoss_qmp>; 782 clock-names = "apb_pclk"; 783 arm,coresight-loses-context-with-cpu; 784 qcom,skip-power-up; 785 786 out-ports { 787 port { 788 etm3_out: endpoint { 789 remote-endpoint = <&apss_funnel_in3>; 790 }; 791 }; 792 }; 793 }; 794 795 etm@7440000 { 796 compatible = "arm,coresight-etm4x", "arm,primecell"; 797 reg = <0 0x07440000 0 0x1000>; 798 799 cpu = <&CPU4>; 800 801 clocks = <&aoss_qmp>; 802 clock-names = "apb_pclk"; 803 arm,coresight-loses-context-with-cpu; 804 qcom,skip-power-up; 805 806 out-ports { 807 port { 808 etm4_out: endpoint { 809 remote-endpoint = <&apss_funnel_in4>; 810 }; 811 }; 812 }; 813 }; 814 815 etm@7540000 { 816 compatible = "arm,coresight-etm4x", "arm,primecell"; 817 reg = <0 0x07540000 0 0x1000>; 818 819 cpu = <&CPU5>; 820 821 clocks = <&aoss_qmp>; 822 clock-names = "apb_pclk"; 823 arm,coresight-loses-context-with-cpu; 824 qcom,skip-power-up; 825 826 out-ports { 827 port { 828 etm5_out: endpoint { 829 remote-endpoint = <&apss_funnel_in5>; 830 }; 831 }; 832 }; 833 }; 834 835 etm@7640000 { 836 compatible = "arm,coresight-etm4x", "arm,primecell"; 837 reg = <0 0x07640000 0 0x1000>; 838 839 cpu = <&CPU6>; 840 841 clocks = <&aoss_qmp>; 842 clock-names = "apb_pclk"; 843 arm,coresight-loses-context-with-cpu; 844 qcom,skip-power-up; 845 846 out-ports { 847 port { 848 etm6_out: endpoint { 849 remote-endpoint = <&apss_funnel_in6>; 850 }; 851 }; 852 }; 853 }; 854 855 etm@7740000 { 856 compatible = "arm,coresight-etm4x", "arm,primecell"; 857 reg = <0 0x07740000 0 0x1000>; 858 859 cpu = <&CPU7>; 860 861 clocks = <&aoss_qmp>; 862 clock-names = "apb_pclk"; 863 arm,coresight-loses-context-with-cpu; 864 qcom,skip-power-up; 865 866 out-ports { 867 port { 868 etm7_out: endpoint { 869 remote-endpoint = <&apss_funnel_in7>; 870 }; 871 }; 872 }; 873 }; 874 875 funnel@7800000 { /* APSS Funnel */ 876 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 877 reg = <0 0x07800000 0 0x1000>; 878 879 clocks = <&aoss_qmp>; 880 clock-names = "apb_pclk"; 881 882 out-ports { 883 port { 884 apss_funnel_out: endpoint { 885 remote-endpoint = <&apss_merge_funnel_in>; 886 }; 887 }; 888 }; 889 890 in-ports { 891 #address-cells = <1>; 892 #size-cells = <0>; 893 894 port@0 { 895 reg = <0>; 896 apss_funnel_in0: endpoint { 897 remote-endpoint = <&etm0_out>; 898 }; 899 }; 900 901 port@1 { 902 reg = <1>; 903 apss_funnel_in1: endpoint { 904 remote-endpoint = <&etm1_out>; 905 }; 906 }; 907 908 port@2 { 909 reg = <2>; 910 apss_funnel_in2: endpoint { 911 remote-endpoint = <&etm2_out>; 912 }; 913 }; 914 915 port@3 { 916 reg = <3>; 917 apss_funnel_in3: endpoint { 918 remote-endpoint = <&etm3_out>; 919 }; 920 }; 921 922 port@4 { 923 reg = <4>; 924 apss_funnel_in4: endpoint { 925 remote-endpoint = <&etm4_out>; 926 }; 927 }; 928 929 port@5 { 930 reg = <5>; 931 apss_funnel_in5: endpoint { 932 remote-endpoint = <&etm5_out>; 933 }; 934 }; 935 936 port@6 { 937 reg = <6>; 938 apss_funnel_in6: endpoint { 939 remote-endpoint = <&etm6_out>; 940 }; 941 }; 942 943 port@7 { 944 reg = <7>; 945 apss_funnel_in7: endpoint { 946 remote-endpoint = <&etm7_out>; 947 }; 948 }; 949 }; 950 }; 951 952 funnel@7810000 { 953 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 954 reg = <0 0x07810000 0 0x1000>; 955 956 clocks = <&aoss_qmp>; 957 clock-names = "apb_pclk"; 958 959 out-ports { 960 port { 961 apss_merge_funnel_out: endpoint { 962 remote-endpoint = <&funnel1_in4>; 963 }; 964 }; 965 }; 966 967 in-ports { 968 port { 969 apss_merge_funnel_in: endpoint { 970 remote-endpoint = <&apss_funnel_out>; 971 }; 972 }; 973 }; 974 }; 975 976 system-cache-controller@9200000 { 977 compatible = "qcom,sc7280-llcc"; 978 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 979 reg-names = "llcc_base", "llcc_broadcast_base"; 980 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 981 }; 982 983 videocc: clock-controller@aaf0000 { 984 compatible = "qcom,sc7280-videocc"; 985 reg = <0 0xaaf0000 0 0x10000>; 986 clocks = <&rpmhcc RPMH_CXO_CLK>, 987 <&rpmhcc RPMH_CXO_CLK_A>; 988 clock-names = "bi_tcxo", "bi_tcxo_ao"; 989 #clock-cells = <1>; 990 #reset-cells = <1>; 991 #power-domain-cells = <1>; 992 }; 993 994 dispcc: clock-controller@af00000 { 995 compatible = "qcom,sc7280-dispcc"; 996 reg = <0 0xaf00000 0 0x20000>; 997 clocks = <&rpmhcc RPMH_CXO_CLK>, 998 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 999 <0>, <0>, <0>, <0>, <0>, <0>; 1000 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1001 "dsi0_phy_pll_out_byteclk", 1002 "dsi0_phy_pll_out_dsiclk", 1003 "dp_phy_pll_link_clk", 1004 "dp_phy_pll_vco_div_clk", 1005 "edp_phy_pll_link_clk", 1006 "edp_phy_pll_vco_div_clk"; 1007 #clock-cells = <1>; 1008 #reset-cells = <1>; 1009 #power-domain-cells = <1>; 1010 }; 1011 1012 pdc: interrupt-controller@b220000 { 1013 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1014 reg = <0 0x0b220000 0 0x30000>; 1015 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1016 <55 306 4>, <59 312 3>, <62 374 2>, 1017 <64 434 2>, <66 438 3>, <69 86 1>, 1018 <70 520 54>, <124 609 31>, <155 63 1>, 1019 <156 716 12>; 1020 #interrupt-cells = <2>; 1021 interrupt-parent = <&intc>; 1022 interrupt-controller; 1023 }; 1024 1025 pdc_reset: reset-controller@b5e0000 { 1026 compatible = "qcom,sc7280-pdc-global"; 1027 reg = <0 0x0b5e0000 0 0x20000>; 1028 #reset-cells = <1>; 1029 }; 1030 1031 tsens0: thermal-sensor@c263000 { 1032 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1033 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1034 <0 0x0c222000 0 0x1ff>; /* SROT */ 1035 #qcom,sensors = <15>; 1036 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1038 interrupt-names = "uplow","critical"; 1039 #thermal-sensor-cells = <1>; 1040 }; 1041 1042 tsens1: thermal-sensor@c265000 { 1043 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1044 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1045 <0 0x0c223000 0 0x1ff>; /* SROT */ 1046 #qcom,sensors = <12>; 1047 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1049 interrupt-names = "uplow","critical"; 1050 #thermal-sensor-cells = <1>; 1051 }; 1052 1053 aoss_reset: reset-controller@c2a0000 { 1054 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1055 reg = <0 0x0c2a0000 0 0x31000>; 1056 #reset-cells = <1>; 1057 }; 1058 1059 aoss_qmp: power-controller@c300000 { 1060 compatible = "qcom,sc7280-aoss-qmp"; 1061 reg = <0 0x0c300000 0 0x100000>; 1062 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1063 IPCC_MPROC_SIGNAL_GLINK_QMP 1064 IRQ_TYPE_EDGE_RISING>; 1065 mboxes = <&ipcc IPCC_CLIENT_AOP 1066 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1067 1068 #clock-cells = <0>; 1069 #power-domain-cells = <1>; 1070 }; 1071 1072 spmi_bus: spmi@c440000 { 1073 compatible = "qcom,spmi-pmic-arb"; 1074 reg = <0 0x0c440000 0 0x1100>, 1075 <0 0x0c600000 0 0x2000000>, 1076 <0 0x0e600000 0 0x100000>, 1077 <0 0x0e700000 0 0xa0000>, 1078 <0 0x0c40a000 0 0x26000>; 1079 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1080 interrupt-names = "periph_irq"; 1081 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1082 qcom,ee = <0>; 1083 qcom,channel = <0>; 1084 #address-cells = <1>; 1085 #size-cells = <1>; 1086 interrupt-controller; 1087 #interrupt-cells = <4>; 1088 }; 1089 1090 tlmm: pinctrl@f100000 { 1091 compatible = "qcom,sc7280-pinctrl"; 1092 reg = <0 0x0f100000 0 0x300000>; 1093 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1094 gpio-controller; 1095 #gpio-cells = <2>; 1096 interrupt-controller; 1097 #interrupt-cells = <2>; 1098 gpio-ranges = <&tlmm 0 0 175>; 1099 wakeup-parent = <&pdc>; 1100 1101 qup_uart5_default: qup-uart5-default { 1102 pins = "gpio46", "gpio47"; 1103 function = "qup13"; 1104 }; 1105 }; 1106 1107 apps_smmu: iommu@15000000 { 1108 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1109 reg = <0 0x15000000 0 0x100000>; 1110 #iommu-cells = <2>; 1111 #global-interrupts = <1>; 1112 dma-coherent; 1113 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1194 }; 1195 1196 intc: interrupt-controller@17a00000 { 1197 compatible = "arm,gic-v3"; 1198 #address-cells = <2>; 1199 #size-cells = <2>; 1200 ranges; 1201 #interrupt-cells = <3>; 1202 interrupt-controller; 1203 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1204 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1206 1207 gic-its@17a40000 { 1208 compatible = "arm,gic-v3-its"; 1209 msi-controller; 1210 #msi-cells = <1>; 1211 reg = <0 0x17a40000 0 0x20000>; 1212 status = "disabled"; 1213 }; 1214 }; 1215 1216 watchdog@17c10000 { 1217 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1218 reg = <0 0x17c10000 0 0x1000>; 1219 clocks = <&sleep_clk>; 1220 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1221 }; 1222 1223 timer@17c20000 { 1224 #address-cells = <2>; 1225 #size-cells = <2>; 1226 ranges; 1227 compatible = "arm,armv7-timer-mem"; 1228 reg = <0 0x17c20000 0 0x1000>; 1229 1230 frame@17c21000 { 1231 frame-number = <0>; 1232 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1234 reg = <0 0x17c21000 0 0x1000>, 1235 <0 0x17c22000 0 0x1000>; 1236 }; 1237 1238 frame@17c23000 { 1239 frame-number = <1>; 1240 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1241 reg = <0 0x17c23000 0 0x1000>; 1242 status = "disabled"; 1243 }; 1244 1245 frame@17c25000 { 1246 frame-number = <2>; 1247 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1248 reg = <0 0x17c25000 0 0x1000>; 1249 status = "disabled"; 1250 }; 1251 1252 frame@17c27000 { 1253 frame-number = <3>; 1254 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1255 reg = <0 0x17c27000 0 0x1000>; 1256 status = "disabled"; 1257 }; 1258 1259 frame@17c29000 { 1260 frame-number = <4>; 1261 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1262 reg = <0 0x17c29000 0 0x1000>; 1263 status = "disabled"; 1264 }; 1265 1266 frame@17c2b000 { 1267 frame-number = <5>; 1268 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1269 reg = <0 0x17c2b000 0 0x1000>; 1270 status = "disabled"; 1271 }; 1272 1273 frame@17c2d000 { 1274 frame-number = <6>; 1275 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1276 reg = <0 0x17c2d000 0 0x1000>; 1277 status = "disabled"; 1278 }; 1279 }; 1280 1281 apps_rsc: rsc@18200000 { 1282 compatible = "qcom,rpmh-rsc"; 1283 reg = <0 0x18200000 0 0x10000>, 1284 <0 0x18210000 0 0x10000>, 1285 <0 0x18220000 0 0x10000>; 1286 reg-names = "drv-0", "drv-1", "drv-2"; 1287 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1290 qcom,tcs-offset = <0xd00>; 1291 qcom,drv-id = <2>; 1292 qcom,tcs-config = <ACTIVE_TCS 2>, 1293 <SLEEP_TCS 3>, 1294 <WAKE_TCS 3>, 1295 <CONTROL_TCS 1>; 1296 1297 rpmhpd: power-controller { 1298 compatible = "qcom,sc7280-rpmhpd"; 1299 #power-domain-cells = <1>; 1300 operating-points-v2 = <&rpmhpd_opp_table>; 1301 1302 rpmhpd_opp_table: opp-table { 1303 compatible = "operating-points-v2"; 1304 1305 rpmhpd_opp_ret: opp1 { 1306 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1307 }; 1308 1309 rpmhpd_opp_low_svs: opp2 { 1310 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1311 }; 1312 1313 rpmhpd_opp_svs: opp3 { 1314 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1315 }; 1316 1317 rpmhpd_opp_svs_l1: opp4 { 1318 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1319 }; 1320 1321 rpmhpd_opp_svs_l2: opp5 { 1322 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1323 }; 1324 1325 rpmhpd_opp_nom: opp6 { 1326 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1327 }; 1328 1329 rpmhpd_opp_nom_l1: opp7 { 1330 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1331 }; 1332 1333 rpmhpd_opp_turbo: opp8 { 1334 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1335 }; 1336 1337 rpmhpd_opp_turbo_l1: opp9 { 1338 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1339 }; 1340 }; 1341 }; 1342 1343 rpmhcc: clock-controller { 1344 compatible = "qcom,sc7280-rpmh-clk"; 1345 clocks = <&xo_board>; 1346 clock-names = "xo"; 1347 #clock-cells = <1>; 1348 }; 1349 }; 1350 1351 cpufreq_hw: cpufreq@18591000 { 1352 compatible = "qcom,cpufreq-epss"; 1353 reg = <0 0x18591000 0 0x1000>, 1354 <0 0x18592000 0 0x1000>, 1355 <0 0x18593000 0 0x1000>; 1356 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1357 clock-names = "xo", "alternate"; 1358 #freq-domain-cells = <1>; 1359 }; 1360 }; 1361 1362 thermal_zones: thermal-zones { 1363 cpu0-thermal { 1364 polling-delay-passive = <250>; 1365 polling-delay = <0>; 1366 1367 thermal-sensors = <&tsens0 1>; 1368 1369 trips { 1370 cpu0_alert0: trip-point0 { 1371 temperature = <90000>; 1372 hysteresis = <2000>; 1373 type = "passive"; 1374 }; 1375 1376 cpu0_alert1: trip-point1 { 1377 temperature = <95000>; 1378 hysteresis = <2000>; 1379 type = "passive"; 1380 }; 1381 1382 cpu0_crit: cpu-crit { 1383 temperature = <110000>; 1384 hysteresis = <0>; 1385 type = "critical"; 1386 }; 1387 }; 1388 1389 cooling-maps { 1390 map0 { 1391 trip = <&cpu0_alert0>; 1392 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1393 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1394 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1395 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1396 }; 1397 map1 { 1398 trip = <&cpu0_alert1>; 1399 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1400 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1401 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1402 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1403 }; 1404 }; 1405 }; 1406 1407 cpu1-thermal { 1408 polling-delay-passive = <250>; 1409 polling-delay = <0>; 1410 1411 thermal-sensors = <&tsens0 2>; 1412 1413 trips { 1414 cpu1_alert0: trip-point0 { 1415 temperature = <90000>; 1416 hysteresis = <2000>; 1417 type = "passive"; 1418 }; 1419 1420 cpu1_alert1: trip-point1 { 1421 temperature = <95000>; 1422 hysteresis = <2000>; 1423 type = "passive"; 1424 }; 1425 1426 cpu1_crit: cpu-crit { 1427 temperature = <110000>; 1428 hysteresis = <0>; 1429 type = "critical"; 1430 }; 1431 }; 1432 1433 cooling-maps { 1434 map0 { 1435 trip = <&cpu1_alert0>; 1436 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1437 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1438 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1439 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1440 }; 1441 map1 { 1442 trip = <&cpu1_alert1>; 1443 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1444 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1445 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1446 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1447 }; 1448 }; 1449 }; 1450 1451 cpu2-thermal { 1452 polling-delay-passive = <250>; 1453 polling-delay = <0>; 1454 1455 thermal-sensors = <&tsens0 3>; 1456 1457 trips { 1458 cpu2_alert0: trip-point0 { 1459 temperature = <90000>; 1460 hysteresis = <2000>; 1461 type = "passive"; 1462 }; 1463 1464 cpu2_alert1: trip-point1 { 1465 temperature = <95000>; 1466 hysteresis = <2000>; 1467 type = "passive"; 1468 }; 1469 1470 cpu2_crit: cpu-crit { 1471 temperature = <110000>; 1472 hysteresis = <0>; 1473 type = "critical"; 1474 }; 1475 }; 1476 1477 cooling-maps { 1478 map0 { 1479 trip = <&cpu2_alert0>; 1480 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1481 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1482 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1483 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1484 }; 1485 map1 { 1486 trip = <&cpu2_alert1>; 1487 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1488 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1489 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1490 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1491 }; 1492 }; 1493 }; 1494 1495 cpu3-thermal { 1496 polling-delay-passive = <250>; 1497 polling-delay = <0>; 1498 1499 thermal-sensors = <&tsens0 4>; 1500 1501 trips { 1502 cpu3_alert0: trip-point0 { 1503 temperature = <90000>; 1504 hysteresis = <2000>; 1505 type = "passive"; 1506 }; 1507 1508 cpu3_alert1: trip-point1 { 1509 temperature = <95000>; 1510 hysteresis = <2000>; 1511 type = "passive"; 1512 }; 1513 1514 cpu3_crit: cpu-crit { 1515 temperature = <110000>; 1516 hysteresis = <0>; 1517 type = "critical"; 1518 }; 1519 }; 1520 1521 cooling-maps { 1522 map0 { 1523 trip = <&cpu3_alert0>; 1524 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1525 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1526 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1527 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1528 }; 1529 map1 { 1530 trip = <&cpu3_alert1>; 1531 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1532 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1533 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1534 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1535 }; 1536 }; 1537 }; 1538 1539 cpu4-thermal { 1540 polling-delay-passive = <250>; 1541 polling-delay = <0>; 1542 1543 thermal-sensors = <&tsens0 7>; 1544 1545 trips { 1546 cpu4_alert0: trip-point0 { 1547 temperature = <90000>; 1548 hysteresis = <2000>; 1549 type = "passive"; 1550 }; 1551 1552 cpu4_alert1: trip-point1 { 1553 temperature = <95000>; 1554 hysteresis = <2000>; 1555 type = "passive"; 1556 }; 1557 1558 cpu4_crit: cpu-crit { 1559 temperature = <110000>; 1560 hysteresis = <0>; 1561 type = "critical"; 1562 }; 1563 }; 1564 1565 cooling-maps { 1566 map0 { 1567 trip = <&cpu4_alert0>; 1568 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1569 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1570 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1571 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1572 }; 1573 map1 { 1574 trip = <&cpu4_alert1>; 1575 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1576 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1577 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1578 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1579 }; 1580 }; 1581 }; 1582 1583 cpu5-thermal { 1584 polling-delay-passive = <250>; 1585 polling-delay = <0>; 1586 1587 thermal-sensors = <&tsens0 8>; 1588 1589 trips { 1590 cpu5_alert0: trip-point0 { 1591 temperature = <90000>; 1592 hysteresis = <2000>; 1593 type = "passive"; 1594 }; 1595 1596 cpu5_alert1: trip-point1 { 1597 temperature = <95000>; 1598 hysteresis = <2000>; 1599 type = "passive"; 1600 }; 1601 1602 cpu5_crit: cpu-crit { 1603 temperature = <110000>; 1604 hysteresis = <0>; 1605 type = "critical"; 1606 }; 1607 }; 1608 1609 cooling-maps { 1610 map0 { 1611 trip = <&cpu5_alert0>; 1612 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1613 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1614 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1615 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1616 }; 1617 map1 { 1618 trip = <&cpu5_alert1>; 1619 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1620 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1621 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1622 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1623 }; 1624 }; 1625 }; 1626 1627 cpu6-thermal { 1628 polling-delay-passive = <250>; 1629 polling-delay = <0>; 1630 1631 thermal-sensors = <&tsens0 9>; 1632 1633 trips { 1634 cpu6_alert0: trip-point0 { 1635 temperature = <90000>; 1636 hysteresis = <2000>; 1637 type = "passive"; 1638 }; 1639 1640 cpu6_alert1: trip-point1 { 1641 temperature = <95000>; 1642 hysteresis = <2000>; 1643 type = "passive"; 1644 }; 1645 1646 cpu6_crit: cpu-crit { 1647 temperature = <110000>; 1648 hysteresis = <0>; 1649 type = "critical"; 1650 }; 1651 }; 1652 1653 cooling-maps { 1654 map0 { 1655 trip = <&cpu6_alert0>; 1656 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1657 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1658 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1659 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1660 }; 1661 map1 { 1662 trip = <&cpu6_alert1>; 1663 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1664 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1665 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1666 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1667 }; 1668 }; 1669 }; 1670 1671 cpu7-thermal { 1672 polling-delay-passive = <250>; 1673 polling-delay = <0>; 1674 1675 thermal-sensors = <&tsens0 10>; 1676 1677 trips { 1678 cpu7_alert0: trip-point0 { 1679 temperature = <90000>; 1680 hysteresis = <2000>; 1681 type = "passive"; 1682 }; 1683 1684 cpu7_alert1: trip-point1 { 1685 temperature = <95000>; 1686 hysteresis = <2000>; 1687 type = "passive"; 1688 }; 1689 1690 cpu7_crit: cpu-crit { 1691 temperature = <110000>; 1692 hysteresis = <0>; 1693 type = "critical"; 1694 }; 1695 }; 1696 1697 cooling-maps { 1698 map0 { 1699 trip = <&cpu7_alert0>; 1700 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1701 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1702 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1703 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1704 }; 1705 map1 { 1706 trip = <&cpu7_alert1>; 1707 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1708 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1709 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1710 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1711 }; 1712 }; 1713 }; 1714 1715 cpu8-thermal { 1716 polling-delay-passive = <250>; 1717 polling-delay = <0>; 1718 1719 thermal-sensors = <&tsens0 11>; 1720 1721 trips { 1722 cpu8_alert0: trip-point0 { 1723 temperature = <90000>; 1724 hysteresis = <2000>; 1725 type = "passive"; 1726 }; 1727 1728 cpu8_alert1: trip-point1 { 1729 temperature = <95000>; 1730 hysteresis = <2000>; 1731 type = "passive"; 1732 }; 1733 1734 cpu8_crit: cpu-crit { 1735 temperature = <110000>; 1736 hysteresis = <0>; 1737 type = "critical"; 1738 }; 1739 }; 1740 1741 cooling-maps { 1742 map0 { 1743 trip = <&cpu8_alert0>; 1744 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1745 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1746 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1747 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1748 }; 1749 map1 { 1750 trip = <&cpu8_alert1>; 1751 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1752 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1753 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1754 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1755 }; 1756 }; 1757 }; 1758 1759 cpu9-thermal { 1760 polling-delay-passive = <250>; 1761 polling-delay = <0>; 1762 1763 thermal-sensors = <&tsens0 12>; 1764 1765 trips { 1766 cpu9_alert0: trip-point0 { 1767 temperature = <90000>; 1768 hysteresis = <2000>; 1769 type = "passive"; 1770 }; 1771 1772 cpu9_alert1: trip-point1 { 1773 temperature = <95000>; 1774 hysteresis = <2000>; 1775 type = "passive"; 1776 }; 1777 1778 cpu9_crit: cpu-crit { 1779 temperature = <110000>; 1780 hysteresis = <0>; 1781 type = "critical"; 1782 }; 1783 }; 1784 1785 cooling-maps { 1786 map0 { 1787 trip = <&cpu9_alert0>; 1788 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1789 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1790 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1791 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1792 }; 1793 map1 { 1794 trip = <&cpu9_alert1>; 1795 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1796 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1797 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1798 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1799 }; 1800 }; 1801 }; 1802 1803 cpu10-thermal { 1804 polling-delay-passive = <250>; 1805 polling-delay = <0>; 1806 1807 thermal-sensors = <&tsens0 13>; 1808 1809 trips { 1810 cpu10_alert0: trip-point0 { 1811 temperature = <90000>; 1812 hysteresis = <2000>; 1813 type = "passive"; 1814 }; 1815 1816 cpu10_alert1: trip-point1 { 1817 temperature = <95000>; 1818 hysteresis = <2000>; 1819 type = "passive"; 1820 }; 1821 1822 cpu10_crit: cpu-crit { 1823 temperature = <110000>; 1824 hysteresis = <0>; 1825 type = "critical"; 1826 }; 1827 }; 1828 1829 cooling-maps { 1830 map0 { 1831 trip = <&cpu10_alert0>; 1832 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1833 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1834 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1835 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1836 }; 1837 map1 { 1838 trip = <&cpu10_alert1>; 1839 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1840 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1841 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1842 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1843 }; 1844 }; 1845 }; 1846 1847 cpu11-thermal { 1848 polling-delay-passive = <250>; 1849 polling-delay = <0>; 1850 1851 thermal-sensors = <&tsens0 14>; 1852 1853 trips { 1854 cpu11_alert0: trip-point0 { 1855 temperature = <90000>; 1856 hysteresis = <2000>; 1857 type = "passive"; 1858 }; 1859 1860 cpu11_alert1: trip-point1 { 1861 temperature = <95000>; 1862 hysteresis = <2000>; 1863 type = "passive"; 1864 }; 1865 1866 cpu11_crit: cpu-crit { 1867 temperature = <110000>; 1868 hysteresis = <0>; 1869 type = "critical"; 1870 }; 1871 }; 1872 1873 cooling-maps { 1874 map0 { 1875 trip = <&cpu11_alert0>; 1876 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1877 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1878 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1879 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1880 }; 1881 map1 { 1882 trip = <&cpu11_alert1>; 1883 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1884 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1885 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1886 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1887 }; 1888 }; 1889 }; 1890 1891 aoss0-thermal { 1892 polling-delay-passive = <0>; 1893 polling-delay = <0>; 1894 1895 thermal-sensors = <&tsens0 0>; 1896 1897 trips { 1898 aoss0_alert0: trip-point0 { 1899 temperature = <90000>; 1900 hysteresis = <2000>; 1901 type = "hot"; 1902 }; 1903 1904 aoss0_crit: aoss0-crit { 1905 temperature = <110000>; 1906 hysteresis = <0>; 1907 type = "critical"; 1908 }; 1909 }; 1910 }; 1911 1912 aoss1-thermal { 1913 polling-delay-passive = <0>; 1914 polling-delay = <0>; 1915 1916 thermal-sensors = <&tsens1 0>; 1917 1918 trips { 1919 aoss1_alert0: trip-point0 { 1920 temperature = <90000>; 1921 hysteresis = <2000>; 1922 type = "hot"; 1923 }; 1924 1925 aoss1_crit: aoss1-crit { 1926 temperature = <110000>; 1927 hysteresis = <0>; 1928 type = "critical"; 1929 }; 1930 }; 1931 }; 1932 1933 cpuss0-thermal { 1934 polling-delay-passive = <0>; 1935 polling-delay = <0>; 1936 1937 thermal-sensors = <&tsens0 5>; 1938 1939 trips { 1940 cpuss0_alert0: trip-point0 { 1941 temperature = <90000>; 1942 hysteresis = <2000>; 1943 type = "hot"; 1944 }; 1945 cpuss0_crit: cluster0-crit { 1946 temperature = <110000>; 1947 hysteresis = <0>; 1948 type = "critical"; 1949 }; 1950 }; 1951 }; 1952 1953 cpuss1-thermal { 1954 polling-delay-passive = <0>; 1955 polling-delay = <0>; 1956 1957 thermal-sensors = <&tsens0 6>; 1958 1959 trips { 1960 cpuss1_alert0: trip-point0 { 1961 temperature = <90000>; 1962 hysteresis = <2000>; 1963 type = "hot"; 1964 }; 1965 cpuss1_crit: cluster0-crit { 1966 temperature = <110000>; 1967 hysteresis = <0>; 1968 type = "critical"; 1969 }; 1970 }; 1971 }; 1972 1973 gpuss0-thermal { 1974 polling-delay-passive = <0>; 1975 polling-delay = <0>; 1976 1977 thermal-sensors = <&tsens1 1>; 1978 1979 trips { 1980 gpuss0_alert0: trip-point0 { 1981 temperature = <90000>; 1982 hysteresis = <2000>; 1983 type = "hot"; 1984 }; 1985 1986 gpuss0_crit: gpuss0-crit { 1987 temperature = <110000>; 1988 hysteresis = <0>; 1989 type = "critical"; 1990 }; 1991 }; 1992 }; 1993 1994 gpuss1-thermal { 1995 polling-delay-passive = <0>; 1996 polling-delay = <0>; 1997 1998 thermal-sensors = <&tsens1 2>; 1999 2000 trips { 2001 gpuss1_alert0: trip-point0 { 2002 temperature = <90000>; 2003 hysteresis = <2000>; 2004 type = "hot"; 2005 }; 2006 2007 gpuss1_crit: gpuss1-crit { 2008 temperature = <110000>; 2009 hysteresis = <0>; 2010 type = "critical"; 2011 }; 2012 }; 2013 }; 2014 2015 nspss0-thermal { 2016 polling-delay-passive = <0>; 2017 polling-delay = <0>; 2018 2019 thermal-sensors = <&tsens1 3>; 2020 2021 trips { 2022 nspss0_alert0: trip-point0 { 2023 temperature = <90000>; 2024 hysteresis = <2000>; 2025 type = "hot"; 2026 }; 2027 2028 nspss0_crit: nspss0-crit { 2029 temperature = <110000>; 2030 hysteresis = <0>; 2031 type = "critical"; 2032 }; 2033 }; 2034 }; 2035 2036 nspss1-thermal { 2037 polling-delay-passive = <0>; 2038 polling-delay = <0>; 2039 2040 thermal-sensors = <&tsens1 4>; 2041 2042 trips { 2043 nspss1_alert0: trip-point0 { 2044 temperature = <90000>; 2045 hysteresis = <2000>; 2046 type = "hot"; 2047 }; 2048 2049 nspss1_crit: nspss1-crit { 2050 temperature = <110000>; 2051 hysteresis = <0>; 2052 type = "critical"; 2053 }; 2054 }; 2055 }; 2056 2057 video-thermal { 2058 polling-delay-passive = <0>; 2059 polling-delay = <0>; 2060 2061 thermal-sensors = <&tsens1 5>; 2062 2063 trips { 2064 video_alert0: trip-point0 { 2065 temperature = <90000>; 2066 hysteresis = <2000>; 2067 type = "hot"; 2068 }; 2069 2070 video_crit: video-crit { 2071 temperature = <110000>; 2072 hysteresis = <0>; 2073 type = "critical"; 2074 }; 2075 }; 2076 }; 2077 2078 ddr-thermal { 2079 polling-delay-passive = <0>; 2080 polling-delay = <0>; 2081 2082 thermal-sensors = <&tsens1 6>; 2083 2084 trips { 2085 ddr_alert0: trip-point0 { 2086 temperature = <90000>; 2087 hysteresis = <2000>; 2088 type = "hot"; 2089 }; 2090 2091 ddr_crit: ddr-crit { 2092 temperature = <110000>; 2093 hysteresis = <0>; 2094 type = "critical"; 2095 }; 2096 }; 2097 }; 2098 2099 mdmss0-thermal { 2100 polling-delay-passive = <0>; 2101 polling-delay = <0>; 2102 2103 thermal-sensors = <&tsens1 7>; 2104 2105 trips { 2106 mdmss0_alert0: trip-point0 { 2107 temperature = <90000>; 2108 hysteresis = <2000>; 2109 type = "hot"; 2110 }; 2111 2112 mdmss0_crit: mdmss0-crit { 2113 temperature = <110000>; 2114 hysteresis = <0>; 2115 type = "critical"; 2116 }; 2117 }; 2118 }; 2119 2120 mdmss1-thermal { 2121 polling-delay-passive = <0>; 2122 polling-delay = <0>; 2123 2124 thermal-sensors = <&tsens1 8>; 2125 2126 trips { 2127 mdmss1_alert0: trip-point0 { 2128 temperature = <90000>; 2129 hysteresis = <2000>; 2130 type = "hot"; 2131 }; 2132 2133 mdmss1_crit: mdmss1-crit { 2134 temperature = <110000>; 2135 hysteresis = <0>; 2136 type = "critical"; 2137 }; 2138 }; 2139 }; 2140 2141 mdmss2-thermal { 2142 polling-delay-passive = <0>; 2143 polling-delay = <0>; 2144 2145 thermal-sensors = <&tsens1 9>; 2146 2147 trips { 2148 mdmss2_alert0: trip-point0 { 2149 temperature = <90000>; 2150 hysteresis = <2000>; 2151 type = "hot"; 2152 }; 2153 2154 mdmss2_crit: mdmss2-crit { 2155 temperature = <110000>; 2156 hysteresis = <0>; 2157 type = "critical"; 2158 }; 2159 }; 2160 }; 2161 2162 mdmss3-thermal { 2163 polling-delay-passive = <0>; 2164 polling-delay = <0>; 2165 2166 thermal-sensors = <&tsens1 10>; 2167 2168 trips { 2169 mdmss3_alert0: trip-point0 { 2170 temperature = <90000>; 2171 hysteresis = <2000>; 2172 type = "hot"; 2173 }; 2174 2175 mdmss3_crit: mdmss3-crit { 2176 temperature = <110000>; 2177 hysteresis = <0>; 2178 type = "critical"; 2179 }; 2180 }; 2181 }; 2182 2183 camera0-thermal { 2184 polling-delay-passive = <0>; 2185 polling-delay = <0>; 2186 2187 thermal-sensors = <&tsens1 11>; 2188 2189 trips { 2190 camera0_alert0: trip-point0 { 2191 temperature = <90000>; 2192 hysteresis = <2000>; 2193 type = "hot"; 2194 }; 2195 2196 camera0_crit: camera0-crit { 2197 temperature = <110000>; 2198 hysteresis = <0>; 2199 type = "critical"; 2200 }; 2201 }; 2202 }; 2203 }; 2204 2205 timer { 2206 compatible = "arm,armv8-timer"; 2207 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2209 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2210 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2211 }; 2212}; 2213