1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,sc7280.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-aoss-qmp.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/reset/qcom,sdm845-aoss.h> 16#include <dt-bindings/reset/qcom,sdm845-pdc.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 aliases { 29 mmc1 = &sdhc_1; 30 mmc2 = &sdhc_2; 31 }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32000>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 aop_mem: memory@80800000 { 53 reg = <0x0 0x80800000 0x0 0x60000>; 54 no-map; 55 }; 56 57 aop_cmd_db_mem: memory@80860000 { 58 reg = <0x0 0x80860000 0x0 0x20000>; 59 compatible = "qcom,cmd-db"; 60 no-map; 61 }; 62 63 smem_mem: memory@80900000 { 64 reg = <0x0 0x80900000 0x0 0x200000>; 65 no-map; 66 }; 67 68 cpucp_mem: memory@80b00000 { 69 no-map; 70 reg = <0x0 0x80b00000 0x0 0x100000>; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <2>; 76 #size-cells = <0>; 77 78 CPU0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,kryo"; 81 reg = <0x0 0x0>; 82 enable-method = "psci"; 83 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 84 &LITTLE_CPU_SLEEP_1 85 &CLUSTER_SLEEP_0>; 86 next-level-cache = <&L2_0>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 #cooling-cells = <2>; 89 L2_0: l2-cache { 90 compatible = "cache"; 91 next-level-cache = <&L3_0>; 92 L3_0: l3-cache { 93 compatible = "cache"; 94 }; 95 }; 96 }; 97 98 CPU1: cpu@100 { 99 device_type = "cpu"; 100 compatible = "arm,kryo"; 101 reg = <0x0 0x100>; 102 enable-method = "psci"; 103 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 104 &LITTLE_CPU_SLEEP_1 105 &CLUSTER_SLEEP_0>; 106 next-level-cache = <&L2_100>; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 #cooling-cells = <2>; 109 L2_100: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,kryo"; 118 reg = <0x0 0x200>; 119 enable-method = "psci"; 120 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 121 &LITTLE_CPU_SLEEP_1 122 &CLUSTER_SLEEP_0>; 123 next-level-cache = <&L2_200>; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 L2_200: l2-cache { 127 compatible = "cache"; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU3: cpu@300 { 133 device_type = "cpu"; 134 compatible = "arm,kryo"; 135 reg = <0x0 0x300>; 136 enable-method = "psci"; 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 138 &LITTLE_CPU_SLEEP_1 139 &CLUSTER_SLEEP_0>; 140 next-level-cache = <&L2_300>; 141 qcom,freq-domain = <&cpufreq_hw 0>; 142 #cooling-cells = <2>; 143 L2_300: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 }; 147 }; 148 149 CPU4: cpu@400 { 150 device_type = "cpu"; 151 compatible = "arm,kryo"; 152 reg = <0x0 0x400>; 153 enable-method = "psci"; 154 cpu-idle-states = <&BIG_CPU_SLEEP_0 155 &BIG_CPU_SLEEP_1 156 &CLUSTER_SLEEP_0>; 157 next-level-cache = <&L2_400>; 158 qcom,freq-domain = <&cpufreq_hw 1>; 159 #cooling-cells = <2>; 160 L2_400: l2-cache { 161 compatible = "cache"; 162 next-level-cache = <&L3_0>; 163 }; 164 }; 165 166 CPU5: cpu@500 { 167 device_type = "cpu"; 168 compatible = "arm,kryo"; 169 reg = <0x0 0x500>; 170 enable-method = "psci"; 171 cpu-idle-states = <&BIG_CPU_SLEEP_0 172 &BIG_CPU_SLEEP_1 173 &CLUSTER_SLEEP_0>; 174 next-level-cache = <&L2_500>; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 #cooling-cells = <2>; 177 L2_500: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,kryo"; 186 reg = <0x0 0x600>; 187 enable-method = "psci"; 188 cpu-idle-states = <&BIG_CPU_SLEEP_0 189 &BIG_CPU_SLEEP_1 190 &CLUSTER_SLEEP_0>; 191 next-level-cache = <&L2_600>; 192 qcom,freq-domain = <&cpufreq_hw 1>; 193 #cooling-cells = <2>; 194 L2_600: l2-cache { 195 compatible = "cache"; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU7: cpu@700 { 201 device_type = "cpu"; 202 compatible = "arm,kryo"; 203 reg = <0x0 0x700>; 204 enable-method = "psci"; 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 206 &BIG_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 next-level-cache = <&L2_700>; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 #cooling-cells = <2>; 211 L2_700: l2-cache { 212 compatible = "cache"; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 idle-states { 218 entry-method = "psci"; 219 220 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 221 compatible = "arm,idle-state"; 222 idle-state-name = "little-power-down"; 223 arm,psci-suspend-param = <0x40000003>; 224 entry-latency-us = <549>; 225 exit-latency-us = <901>; 226 min-residency-us = <1774>; 227 local-timer-stop; 228 }; 229 230 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "little-rail-power-down"; 233 arm,psci-suspend-param = <0x40000004>; 234 entry-latency-us = <702>; 235 exit-latency-us = <915>; 236 min-residency-us = <4001>; 237 local-timer-stop; 238 }; 239 240 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 241 compatible = "arm,idle-state"; 242 idle-state-name = "big-power-down"; 243 arm,psci-suspend-param = <0x40000003>; 244 entry-latency-us = <523>; 245 exit-latency-us = <1244>; 246 min-residency-us = <2207>; 247 local-timer-stop; 248 }; 249 250 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "big-rail-power-down"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <526>; 255 exit-latency-us = <1854>; 256 min-residency-us = <5555>; 257 local-timer-stop; 258 }; 259 260 CLUSTER_SLEEP_0: cluster-sleep-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "cluster-power-down"; 263 arm,psci-suspend-param = <0x40003444>; 264 entry-latency-us = <3263>; 265 exit-latency-us = <6562>; 266 min-residency-us = <9926>; 267 local-timer-stop; 268 }; 269 }; 270 }; 271 272 memory@80000000 { 273 device_type = "memory"; 274 /* We expect the bootloader to fill in the size */ 275 reg = <0 0x80000000 0 0>; 276 }; 277 278 firmware { 279 scm { 280 compatible = "qcom,scm-sc7280", "qcom,scm"; 281 }; 282 }; 283 284 clk_virt: interconnect { 285 compatible = "qcom,sc7280-clk-virt"; 286 #interconnect-cells = <2>; 287 qcom,bcm-voters = <&apps_bcm_voter>; 288 }; 289 290 smem { 291 compatible = "qcom,smem"; 292 memory-region = <&smem_mem>; 293 hwlocks = <&tcsr_mutex 3>; 294 }; 295 296 smp2p-adsp { 297 compatible = "qcom,smp2p"; 298 qcom,smem = <443>, <429>; 299 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 300 IPCC_MPROC_SIGNAL_SMP2P 301 IRQ_TYPE_EDGE_RISING>; 302 mboxes = <&ipcc IPCC_CLIENT_LPASS 303 IPCC_MPROC_SIGNAL_SMP2P>; 304 305 qcom,local-pid = <0>; 306 qcom,remote-pid = <2>; 307 308 adsp_smp2p_out: master-kernel { 309 qcom,entry-name = "master-kernel"; 310 #qcom,smem-state-cells = <1>; 311 }; 312 313 adsp_smp2p_in: slave-kernel { 314 qcom,entry-name = "slave-kernel"; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 }; 319 320 smp2p-cdsp { 321 compatible = "qcom,smp2p"; 322 qcom,smem = <94>, <432>; 323 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 324 IPCC_MPROC_SIGNAL_SMP2P 325 IRQ_TYPE_EDGE_RISING>; 326 mboxes = <&ipcc IPCC_CLIENT_CDSP 327 IPCC_MPROC_SIGNAL_SMP2P>; 328 329 qcom,local-pid = <0>; 330 qcom,remote-pid = <5>; 331 332 cdsp_smp2p_out: master-kernel { 333 qcom,entry-name = "master-kernel"; 334 #qcom,smem-state-cells = <1>; 335 }; 336 337 cdsp_smp2p_in: slave-kernel { 338 qcom,entry-name = "slave-kernel"; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 }; 342 }; 343 344 smp2p-mpss { 345 compatible = "qcom,smp2p"; 346 qcom,smem = <435>, <428>; 347 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 348 IPCC_MPROC_SIGNAL_SMP2P 349 IRQ_TYPE_EDGE_RISING>; 350 mboxes = <&ipcc IPCC_CLIENT_MPSS 351 IPCC_MPROC_SIGNAL_SMP2P>; 352 353 qcom,local-pid = <0>; 354 qcom,remote-pid = <1>; 355 356 modem_smp2p_out: master-kernel { 357 qcom,entry-name = "master-kernel"; 358 #qcom,smem-state-cells = <1>; 359 }; 360 361 modem_smp2p_in: slave-kernel { 362 qcom,entry-name = "slave-kernel"; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 }; 366 367 ipa_smp2p_out: ipa-ap-to-modem { 368 qcom,entry-name = "ipa"; 369 #qcom,smem-state-cells = <1>; 370 }; 371 372 ipa_smp2p_in: ipa-modem-to-ap { 373 qcom,entry-name = "ipa"; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 }; 377 }; 378 379 smp2p-wpss { 380 compatible = "qcom,smp2p"; 381 qcom,smem = <617>, <616>; 382 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 383 IPCC_MPROC_SIGNAL_SMP2P 384 IRQ_TYPE_EDGE_RISING>; 385 mboxes = <&ipcc IPCC_CLIENT_WPSS 386 IPCC_MPROC_SIGNAL_SMP2P>; 387 388 qcom,local-pid = <0>; 389 qcom,remote-pid = <13>; 390 391 wpss_smp2p_out: master-kernel { 392 qcom,entry-name = "master-kernel"; 393 #qcom,smem-state-cells = <1>; 394 }; 395 396 wpss_smp2p_in: slave-kernel { 397 qcom,entry-name = "slave-kernel"; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 }; 402 403 pmu { 404 compatible = "arm,armv8-pmuv3"; 405 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 406 }; 407 408 psci { 409 compatible = "arm,psci-1.0"; 410 method = "smc"; 411 }; 412 413 soc: soc@0 { 414 #address-cells = <2>; 415 #size-cells = <2>; 416 ranges = <0 0 0 0 0x10 0>; 417 dma-ranges = <0 0 0 0 0x10 0>; 418 compatible = "simple-bus"; 419 420 gcc: clock-controller@100000 { 421 compatible = "qcom,gcc-sc7280"; 422 reg = <0 0x00100000 0 0x1f0000>; 423 clocks = <&rpmhcc RPMH_CXO_CLK>, 424 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 425 <0>, <0>, <0>, <0>, <0>, <0>; 426 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 427 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 428 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 429 "ufs_phy_tx_symbol_0_clk", 430 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 431 #clock-cells = <1>; 432 #reset-cells = <1>; 433 #power-domain-cells = <1>; 434 }; 435 436 ipcc: mailbox@408000 { 437 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 438 reg = <0 0x00408000 0 0x1000>; 439 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-controller; 441 #interrupt-cells = <3>; 442 #mbox-cells = <2>; 443 }; 444 445 qfprom: efuse@784000 { 446 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 447 reg = <0 0x00784000 0 0xa20>, 448 <0 0x00780000 0 0xa20>, 449 <0 0x00782000 0 0x120>, 450 <0 0x00786000 0 0x1fff>; 451 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 452 clock-names = "core"; 453 power-domains = <&rpmhpd SC7280_MX>; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 }; 457 458 sdhc_1: sdhci@7c4000 { 459 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 460 status = "disabled"; 461 462 reg = <0 0x007c4000 0 0x1000>, 463 <0 0x007c5000 0 0x1000>; 464 reg-names = "hc", "cqhci"; 465 466 iommus = <&apps_smmu 0xc0 0x0>; 467 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-names = "hc_irq", "pwr_irq"; 470 471 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 472 <&gcc GCC_SDCC1_AHB_CLK>, 473 <&rpmhcc RPMH_CXO_CLK>; 474 clock-names = "core", "iface", "xo"; 475 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 476 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 477 interconnect-names = "sdhc-ddr","cpu-sdhc"; 478 power-domains = <&rpmhpd SC7280_CX>; 479 operating-points-v2 = <&sdhc1_opp_table>; 480 481 bus-width = <8>; 482 supports-cqe; 483 484 qcom,dll-config = <0x0007642c>; 485 qcom,ddr-config = <0x80040868>; 486 487 mmc-ddr-1_8v; 488 mmc-hs200-1_8v; 489 mmc-hs400-1_8v; 490 mmc-hs400-enhanced-strobe; 491 492 sdhc1_opp_table: opp-table { 493 compatible = "operating-points-v2"; 494 495 opp-100000000 { 496 opp-hz = /bits/ 64 <100000000>; 497 required-opps = <&rpmhpd_opp_low_svs>; 498 opp-peak-kBps = <1800000 400000>; 499 opp-avg-kBps = <100000 0>; 500 }; 501 502 opp-384000000 { 503 opp-hz = /bits/ 64 <384000000>; 504 required-opps = <&rpmhpd_opp_nom>; 505 opp-peak-kBps = <5400000 1600000>; 506 opp-avg-kBps = <390000 0>; 507 }; 508 }; 509 510 }; 511 512 qupv3_id_0: geniqup@9c0000 { 513 compatible = "qcom,geni-se-qup"; 514 reg = <0 0x009c0000 0 0x2000>; 515 clock-names = "m-ahb", "s-ahb"; 516 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 517 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 518 #address-cells = <2>; 519 #size-cells = <2>; 520 ranges; 521 status = "disabled"; 522 523 uart5: serial@994000 { 524 compatible = "qcom,geni-debug-uart"; 525 reg = <0 0x00994000 0 0x4000>; 526 clock-names = "se"; 527 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&qup_uart5_default>; 530 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 531 status = "disabled"; 532 }; 533 }; 534 535 cnoc2: interconnect@1500000 { 536 reg = <0 0x01500000 0 0x1000>; 537 compatible = "qcom,sc7280-cnoc2"; 538 #interconnect-cells = <2>; 539 qcom,bcm-voters = <&apps_bcm_voter>; 540 }; 541 542 cnoc3: interconnect@1502000 { 543 reg = <0 0x01502000 0 0x1000>; 544 compatible = "qcom,sc7280-cnoc3"; 545 #interconnect-cells = <2>; 546 qcom,bcm-voters = <&apps_bcm_voter>; 547 }; 548 549 mc_virt: interconnect@1580000 { 550 reg = <0 0x01580000 0 0x4>; 551 compatible = "qcom,sc7280-mc-virt"; 552 #interconnect-cells = <2>; 553 qcom,bcm-voters = <&apps_bcm_voter>; 554 }; 555 556 system_noc: interconnect@1680000 { 557 reg = <0 0x01680000 0 0x15480>; 558 compatible = "qcom,sc7280-system-noc"; 559 #interconnect-cells = <2>; 560 qcom,bcm-voters = <&apps_bcm_voter>; 561 }; 562 563 aggre1_noc: interconnect@16e0000 { 564 compatible = "qcom,sc7280-aggre1-noc"; 565 reg = <0 0x016e0000 0 0x1c080>; 566 #interconnect-cells = <2>; 567 qcom,bcm-voters = <&apps_bcm_voter>; 568 }; 569 570 aggre2_noc: interconnect@1700000 { 571 reg = <0 0x01700000 0 0x2b080>; 572 compatible = "qcom,sc7280-aggre2-noc"; 573 #interconnect-cells = <2>; 574 qcom,bcm-voters = <&apps_bcm_voter>; 575 }; 576 577 mmss_noc: interconnect@1740000 { 578 reg = <0 0x01740000 0 0x1e080>; 579 compatible = "qcom,sc7280-mmss-noc"; 580 #interconnect-cells = <2>; 581 qcom,bcm-voters = <&apps_bcm_voter>; 582 }; 583 584 tcsr_mutex: hwlock@1f40000 { 585 compatible = "qcom,tcsr-mutex", "syscon"; 586 reg = <0 0x01f40000 0 0x40000>; 587 #hwlock-cells = <1>; 588 }; 589 590 lpasscc: lpasscc@3000000 { 591 compatible = "qcom,sc7280-lpasscc"; 592 reg = <0 0x03000000 0 0x40>, 593 <0 0x03c04000 0 0x4>, 594 <0 0x03389000 0 0x24>; 595 reg-names = "qdsp6ss", "top_cc", "cc"; 596 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 597 clock-names = "iface"; 598 #clock-cells = <1>; 599 }; 600 601 lpass_ag_noc: interconnect@3c40000 { 602 reg = <0 0x03c40000 0 0xf080>; 603 compatible = "qcom,sc7280-lpass-ag-noc"; 604 #interconnect-cells = <2>; 605 qcom,bcm-voters = <&apps_bcm_voter>; 606 }; 607 608 gpucc: clock-controller@3d90000 { 609 compatible = "qcom,sc7280-gpucc"; 610 reg = <0 0x03d90000 0 0x9000>; 611 clocks = <&rpmhcc RPMH_CXO_CLK>, 612 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 613 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 614 clock-names = "bi_tcxo", 615 "gcc_gpu_gpll0_clk_src", 616 "gcc_gpu_gpll0_div_clk_src"; 617 #clock-cells = <1>; 618 #reset-cells = <1>; 619 #power-domain-cells = <1>; 620 }; 621 622 stm@6002000 { 623 compatible = "arm,coresight-stm", "arm,primecell"; 624 reg = <0 0x06002000 0 0x1000>, 625 <0 0x16280000 0 0x180000>; 626 reg-names = "stm-base", "stm-stimulus-base"; 627 628 clocks = <&aoss_qmp>; 629 clock-names = "apb_pclk"; 630 631 out-ports { 632 port { 633 stm_out: endpoint { 634 remote-endpoint = <&funnel0_in7>; 635 }; 636 }; 637 }; 638 }; 639 640 funnel@6041000 { 641 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 642 reg = <0 0x06041000 0 0x1000>; 643 644 clocks = <&aoss_qmp>; 645 clock-names = "apb_pclk"; 646 647 out-ports { 648 port { 649 funnel0_out: endpoint { 650 remote-endpoint = <&merge_funnel_in0>; 651 }; 652 }; 653 }; 654 655 in-ports { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 659 port@7 { 660 reg = <7>; 661 funnel0_in7: endpoint { 662 remote-endpoint = <&stm_out>; 663 }; 664 }; 665 }; 666 }; 667 668 funnel@6042000 { 669 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 670 reg = <0 0x06042000 0 0x1000>; 671 672 clocks = <&aoss_qmp>; 673 clock-names = "apb_pclk"; 674 675 out-ports { 676 port { 677 funnel1_out: endpoint { 678 remote-endpoint = <&merge_funnel_in1>; 679 }; 680 }; 681 }; 682 683 in-ports { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 687 port@4 { 688 reg = <4>; 689 funnel1_in4: endpoint { 690 remote-endpoint = <&apss_merge_funnel_out>; 691 }; 692 }; 693 }; 694 }; 695 696 funnel@6045000 { 697 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 698 reg = <0 0x06045000 0 0x1000>; 699 700 clocks = <&aoss_qmp>; 701 clock-names = "apb_pclk"; 702 703 out-ports { 704 port { 705 merge_funnel_out: endpoint { 706 remote-endpoint = <&swao_funnel_in>; 707 }; 708 }; 709 }; 710 711 in-ports { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 715 port@0 { 716 reg = <0>; 717 merge_funnel_in0: endpoint { 718 remote-endpoint = <&funnel0_out>; 719 }; 720 }; 721 722 port@1 { 723 reg = <1>; 724 merge_funnel_in1: endpoint { 725 remote-endpoint = <&funnel1_out>; 726 }; 727 }; 728 }; 729 }; 730 731 replicator@6046000 { 732 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 733 reg = <0 0x06046000 0 0x1000>; 734 735 clocks = <&aoss_qmp>; 736 clock-names = "apb_pclk"; 737 738 out-ports { 739 port { 740 replicator_out: endpoint { 741 remote-endpoint = <&etr_in>; 742 }; 743 }; 744 }; 745 746 in-ports { 747 port { 748 replicator_in: endpoint { 749 remote-endpoint = <&swao_replicator_out>; 750 }; 751 }; 752 }; 753 }; 754 755 etr@6048000 { 756 compatible = "arm,coresight-tmc", "arm,primecell"; 757 reg = <0 0x06048000 0 0x1000>; 758 iommus = <&apps_smmu 0x04c0 0>; 759 760 clocks = <&aoss_qmp>; 761 clock-names = "apb_pclk"; 762 arm,scatter-gather; 763 764 in-ports { 765 port { 766 etr_in: endpoint { 767 remote-endpoint = <&replicator_out>; 768 }; 769 }; 770 }; 771 }; 772 773 funnel@6b04000 { 774 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 775 reg = <0 0x06b04000 0 0x1000>; 776 777 clocks = <&aoss_qmp>; 778 clock-names = "apb_pclk"; 779 780 out-ports { 781 port { 782 swao_funnel_out: endpoint { 783 remote-endpoint = <&etf_in>; 784 }; 785 }; 786 }; 787 788 in-ports { 789 #address-cells = <1>; 790 #size-cells = <0>; 791 792 port@7 { 793 reg = <7>; 794 swao_funnel_in: endpoint { 795 remote-endpoint = <&merge_funnel_out>; 796 }; 797 }; 798 }; 799 }; 800 801 etf@6b05000 { 802 compatible = "arm,coresight-tmc", "arm,primecell"; 803 reg = <0 0x06b05000 0 0x1000>; 804 805 clocks = <&aoss_qmp>; 806 clock-names = "apb_pclk"; 807 808 out-ports { 809 port { 810 etf_out: endpoint { 811 remote-endpoint = <&swao_replicator_in>; 812 }; 813 }; 814 }; 815 816 in-ports { 817 port { 818 etf_in: endpoint { 819 remote-endpoint = <&swao_funnel_out>; 820 }; 821 }; 822 }; 823 }; 824 825 replicator@6b06000 { 826 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 827 reg = <0 0x06b06000 0 0x1000>; 828 829 clocks = <&aoss_qmp>; 830 clock-names = "apb_pclk"; 831 qcom,replicator-loses-context; 832 833 out-ports { 834 port { 835 swao_replicator_out: endpoint { 836 remote-endpoint = <&replicator_in>; 837 }; 838 }; 839 }; 840 841 in-ports { 842 port { 843 swao_replicator_in: endpoint { 844 remote-endpoint = <&etf_out>; 845 }; 846 }; 847 }; 848 }; 849 850 etm@7040000 { 851 compatible = "arm,coresight-etm4x", "arm,primecell"; 852 reg = <0 0x07040000 0 0x1000>; 853 854 cpu = <&CPU0>; 855 856 clocks = <&aoss_qmp>; 857 clock-names = "apb_pclk"; 858 arm,coresight-loses-context-with-cpu; 859 qcom,skip-power-up; 860 861 out-ports { 862 port { 863 etm0_out: endpoint { 864 remote-endpoint = <&apss_funnel_in0>; 865 }; 866 }; 867 }; 868 }; 869 870 etm@7140000 { 871 compatible = "arm,coresight-etm4x", "arm,primecell"; 872 reg = <0 0x07140000 0 0x1000>; 873 874 cpu = <&CPU1>; 875 876 clocks = <&aoss_qmp>; 877 clock-names = "apb_pclk"; 878 arm,coresight-loses-context-with-cpu; 879 qcom,skip-power-up; 880 881 out-ports { 882 port { 883 etm1_out: endpoint { 884 remote-endpoint = <&apss_funnel_in1>; 885 }; 886 }; 887 }; 888 }; 889 890 etm@7240000 { 891 compatible = "arm,coresight-etm4x", "arm,primecell"; 892 reg = <0 0x07240000 0 0x1000>; 893 894 cpu = <&CPU2>; 895 896 clocks = <&aoss_qmp>; 897 clock-names = "apb_pclk"; 898 arm,coresight-loses-context-with-cpu; 899 qcom,skip-power-up; 900 901 out-ports { 902 port { 903 etm2_out: endpoint { 904 remote-endpoint = <&apss_funnel_in2>; 905 }; 906 }; 907 }; 908 }; 909 910 etm@7340000 { 911 compatible = "arm,coresight-etm4x", "arm,primecell"; 912 reg = <0 0x07340000 0 0x1000>; 913 914 cpu = <&CPU3>; 915 916 clocks = <&aoss_qmp>; 917 clock-names = "apb_pclk"; 918 arm,coresight-loses-context-with-cpu; 919 qcom,skip-power-up; 920 921 out-ports { 922 port { 923 etm3_out: endpoint { 924 remote-endpoint = <&apss_funnel_in3>; 925 }; 926 }; 927 }; 928 }; 929 930 etm@7440000 { 931 compatible = "arm,coresight-etm4x", "arm,primecell"; 932 reg = <0 0x07440000 0 0x1000>; 933 934 cpu = <&CPU4>; 935 936 clocks = <&aoss_qmp>; 937 clock-names = "apb_pclk"; 938 arm,coresight-loses-context-with-cpu; 939 qcom,skip-power-up; 940 941 out-ports { 942 port { 943 etm4_out: endpoint { 944 remote-endpoint = <&apss_funnel_in4>; 945 }; 946 }; 947 }; 948 }; 949 950 etm@7540000 { 951 compatible = "arm,coresight-etm4x", "arm,primecell"; 952 reg = <0 0x07540000 0 0x1000>; 953 954 cpu = <&CPU5>; 955 956 clocks = <&aoss_qmp>; 957 clock-names = "apb_pclk"; 958 arm,coresight-loses-context-with-cpu; 959 qcom,skip-power-up; 960 961 out-ports { 962 port { 963 etm5_out: endpoint { 964 remote-endpoint = <&apss_funnel_in5>; 965 }; 966 }; 967 }; 968 }; 969 970 etm@7640000 { 971 compatible = "arm,coresight-etm4x", "arm,primecell"; 972 reg = <0 0x07640000 0 0x1000>; 973 974 cpu = <&CPU6>; 975 976 clocks = <&aoss_qmp>; 977 clock-names = "apb_pclk"; 978 arm,coresight-loses-context-with-cpu; 979 qcom,skip-power-up; 980 981 out-ports { 982 port { 983 etm6_out: endpoint { 984 remote-endpoint = <&apss_funnel_in6>; 985 }; 986 }; 987 }; 988 }; 989 990 etm@7740000 { 991 compatible = "arm,coresight-etm4x", "arm,primecell"; 992 reg = <0 0x07740000 0 0x1000>; 993 994 cpu = <&CPU7>; 995 996 clocks = <&aoss_qmp>; 997 clock-names = "apb_pclk"; 998 arm,coresight-loses-context-with-cpu; 999 qcom,skip-power-up; 1000 1001 out-ports { 1002 port { 1003 etm7_out: endpoint { 1004 remote-endpoint = <&apss_funnel_in7>; 1005 }; 1006 }; 1007 }; 1008 }; 1009 1010 funnel@7800000 { /* APSS Funnel */ 1011 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1012 reg = <0 0x07800000 0 0x1000>; 1013 1014 clocks = <&aoss_qmp>; 1015 clock-names = "apb_pclk"; 1016 1017 out-ports { 1018 port { 1019 apss_funnel_out: endpoint { 1020 remote-endpoint = <&apss_merge_funnel_in>; 1021 }; 1022 }; 1023 }; 1024 1025 in-ports { 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 1029 port@0 { 1030 reg = <0>; 1031 apss_funnel_in0: endpoint { 1032 remote-endpoint = <&etm0_out>; 1033 }; 1034 }; 1035 1036 port@1 { 1037 reg = <1>; 1038 apss_funnel_in1: endpoint { 1039 remote-endpoint = <&etm1_out>; 1040 }; 1041 }; 1042 1043 port@2 { 1044 reg = <2>; 1045 apss_funnel_in2: endpoint { 1046 remote-endpoint = <&etm2_out>; 1047 }; 1048 }; 1049 1050 port@3 { 1051 reg = <3>; 1052 apss_funnel_in3: endpoint { 1053 remote-endpoint = <&etm3_out>; 1054 }; 1055 }; 1056 1057 port@4 { 1058 reg = <4>; 1059 apss_funnel_in4: endpoint { 1060 remote-endpoint = <&etm4_out>; 1061 }; 1062 }; 1063 1064 port@5 { 1065 reg = <5>; 1066 apss_funnel_in5: endpoint { 1067 remote-endpoint = <&etm5_out>; 1068 }; 1069 }; 1070 1071 port@6 { 1072 reg = <6>; 1073 apss_funnel_in6: endpoint { 1074 remote-endpoint = <&etm6_out>; 1075 }; 1076 }; 1077 1078 port@7 { 1079 reg = <7>; 1080 apss_funnel_in7: endpoint { 1081 remote-endpoint = <&etm7_out>; 1082 }; 1083 }; 1084 }; 1085 }; 1086 1087 funnel@7810000 { 1088 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1089 reg = <0 0x07810000 0 0x1000>; 1090 1091 clocks = <&aoss_qmp>; 1092 clock-names = "apb_pclk"; 1093 1094 out-ports { 1095 port { 1096 apss_merge_funnel_out: endpoint { 1097 remote-endpoint = <&funnel1_in4>; 1098 }; 1099 }; 1100 }; 1101 1102 in-ports { 1103 port { 1104 apss_merge_funnel_in: endpoint { 1105 remote-endpoint = <&apss_funnel_out>; 1106 }; 1107 }; 1108 }; 1109 }; 1110 1111 sdhc_2: sdhci@8804000 { 1112 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1113 status = "disabled"; 1114 1115 reg = <0 0x08804000 0 0x1000>; 1116 1117 iommus = <&apps_smmu 0x100 0x0>; 1118 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1120 interrupt-names = "hc_irq", "pwr_irq"; 1121 1122 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1123 <&gcc GCC_SDCC2_AHB_CLK>, 1124 <&rpmhcc RPMH_CXO_CLK>; 1125 clock-names = "core", "iface", "xo"; 1126 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1127 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1128 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1129 power-domains = <&rpmhpd SC7280_CX>; 1130 operating-points-v2 = <&sdhc2_opp_table>; 1131 1132 bus-width = <4>; 1133 1134 qcom,dll-config = <0x0007642c>; 1135 1136 sdhc2_opp_table: opp-table { 1137 compatible = "operating-points-v2"; 1138 1139 opp-100000000 { 1140 opp-hz = /bits/ 64 <100000000>; 1141 required-opps = <&rpmhpd_opp_low_svs>; 1142 opp-peak-kBps = <1800000 400000>; 1143 opp-avg-kBps = <100000 0>; 1144 }; 1145 1146 opp-202000000 { 1147 opp-hz = /bits/ 64 <202000000>; 1148 required-opps = <&rpmhpd_opp_nom>; 1149 opp-peak-kBps = <5400000 1600000>; 1150 opp-avg-kBps = <200000 0>; 1151 }; 1152 }; 1153 1154 }; 1155 1156 usb_1_hsphy: phy@88e3000 { 1157 compatible = "qcom,sc7280-usb-hs-phy", 1158 "qcom,usb-snps-hs-7nm-phy"; 1159 reg = <0 0x088e3000 0 0x400>; 1160 status = "disabled"; 1161 #phy-cells = <0>; 1162 1163 clocks = <&rpmhcc RPMH_CXO_CLK>; 1164 clock-names = "ref"; 1165 1166 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1167 }; 1168 1169 usb_2_hsphy: phy@88e4000 { 1170 compatible = "qcom,sc7280-usb-hs-phy", 1171 "qcom,usb-snps-hs-7nm-phy"; 1172 reg = <0 0x088e4000 0 0x400>; 1173 status = "disabled"; 1174 #phy-cells = <0>; 1175 1176 clocks = <&rpmhcc RPMH_CXO_CLK>; 1177 clock-names = "ref"; 1178 1179 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1180 }; 1181 1182 usb_1_qmpphy: phy-wrapper@88e9000 { 1183 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1184 "qcom,sm8250-qmp-usb3-dp-phy"; 1185 reg = <0 0x088e9000 0 0x200>, 1186 <0 0x088e8000 0 0x40>, 1187 <0 0x088ea000 0 0x200>; 1188 status = "disabled"; 1189 #address-cells = <2>; 1190 #size-cells = <2>; 1191 ranges; 1192 1193 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1194 <&rpmhcc RPMH_CXO_CLK>, 1195 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1196 clock-names = "aux", "ref_clk_src", "com_aux"; 1197 1198 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1199 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1200 reset-names = "phy", "common"; 1201 1202 usb_1_ssphy: usb3-phy@88e9200 { 1203 reg = <0 0x088e9200 0 0x200>, 1204 <0 0x088e9400 0 0x200>, 1205 <0 0x088e9c00 0 0x400>, 1206 <0 0x088e9600 0 0x200>, 1207 <0 0x088e9800 0 0x200>, 1208 <0 0x088e9a00 0 0x100>; 1209 #clock-cells = <0>; 1210 #phy-cells = <0>; 1211 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1212 clock-names = "pipe0"; 1213 clock-output-names = "usb3_phy_pipe_clk_src"; 1214 }; 1215 1216 dp_phy: dp-phy@88ea200 { 1217 reg = <0 0x088ea200 0 0x200>, 1218 <0 0x088ea400 0 0x200>, 1219 <0 0x088eac00 0 0x400>, 1220 <0 0x088ea600 0 0x200>, 1221 <0 0x088ea800 0 0x200>, 1222 <0 0x088eaa00 0 0x100>; 1223 #phy-cells = <0>; 1224 #clock-cells = <1>; 1225 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1226 clock-names = "pipe0"; 1227 clock-output-names = "usb3_phy_pipe_clk_src"; 1228 }; 1229 }; 1230 1231 usb_2: usb@8cf8800 { 1232 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1233 reg = <0 0x08cf8800 0 0x400>; 1234 status = "disabled"; 1235 #address-cells = <2>; 1236 #size-cells = <2>; 1237 ranges; 1238 dma-ranges; 1239 1240 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1241 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1242 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1243 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1244 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1245 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1246 "sleep"; 1247 1248 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1249 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1250 assigned-clock-rates = <19200000>, <200000000>; 1251 1252 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1253 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1254 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1255 interrupt-names = "hs_phy_irq", 1256 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1257 1258 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1259 1260 resets = <&gcc GCC_USB30_SEC_BCR>; 1261 1262 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1263 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1264 interconnect-names = "usb-ddr", "apps-usb"; 1265 1266 usb_2_dwc3: usb@8c00000 { 1267 compatible = "snps,dwc3"; 1268 reg = <0 0x08c00000 0 0xe000>; 1269 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1270 iommus = <&apps_smmu 0xa0 0x0>; 1271 snps,dis_u2_susphy_quirk; 1272 snps,dis_enblslpm_quirk; 1273 phys = <&usb_2_hsphy>; 1274 phy-names = "usb2-phy"; 1275 maximum-speed = "high-speed"; 1276 }; 1277 }; 1278 1279 dc_noc: interconnect@90e0000 { 1280 reg = <0 0x090e0000 0 0x5080>; 1281 compatible = "qcom,sc7280-dc-noc"; 1282 #interconnect-cells = <2>; 1283 qcom,bcm-voters = <&apps_bcm_voter>; 1284 }; 1285 1286 gem_noc: interconnect@9100000 { 1287 reg = <0 0x9100000 0 0xe2200>; 1288 compatible = "qcom,sc7280-gem-noc"; 1289 #interconnect-cells = <2>; 1290 qcom,bcm-voters = <&apps_bcm_voter>; 1291 }; 1292 1293 system-cache-controller@9200000 { 1294 compatible = "qcom,sc7280-llcc"; 1295 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1296 reg-names = "llcc_base", "llcc_broadcast_base"; 1297 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1298 }; 1299 1300 nsp_noc: interconnect@a0c0000 { 1301 reg = <0 0x0a0c0000 0 0x10000>; 1302 compatible = "qcom,sc7280-nsp-noc"; 1303 #interconnect-cells = <2>; 1304 qcom,bcm-voters = <&apps_bcm_voter>; 1305 }; 1306 1307 usb_1: usb@a6f8800 { 1308 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1309 reg = <0 0x0a6f8800 0 0x400>; 1310 status = "disabled"; 1311 #address-cells = <2>; 1312 #size-cells = <2>; 1313 ranges; 1314 dma-ranges; 1315 1316 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1317 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1318 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1319 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1320 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1321 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1322 "sleep"; 1323 1324 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1325 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1326 assigned-clock-rates = <19200000>, <200000000>; 1327 1328 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1329 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1330 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1331 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1332 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1333 "dm_hs_phy_irq", "ss_phy_irq"; 1334 1335 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1336 1337 resets = <&gcc GCC_USB30_PRIM_BCR>; 1338 1339 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1340 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1341 interconnect-names = "usb-ddr", "apps-usb"; 1342 1343 usb_1_dwc3: usb@a600000 { 1344 compatible = "snps,dwc3"; 1345 reg = <0 0x0a600000 0 0xe000>; 1346 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1347 iommus = <&apps_smmu 0xe0 0x0>; 1348 snps,dis_u2_susphy_quirk; 1349 snps,dis_enblslpm_quirk; 1350 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1351 phy-names = "usb2-phy", "usb3-phy"; 1352 maximum-speed = "super-speed"; 1353 }; 1354 }; 1355 1356 videocc: clock-controller@aaf0000 { 1357 compatible = "qcom,sc7280-videocc"; 1358 reg = <0 0xaaf0000 0 0x10000>; 1359 clocks = <&rpmhcc RPMH_CXO_CLK>, 1360 <&rpmhcc RPMH_CXO_CLK_A>; 1361 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1362 #clock-cells = <1>; 1363 #reset-cells = <1>; 1364 #power-domain-cells = <1>; 1365 }; 1366 1367 dispcc: clock-controller@af00000 { 1368 compatible = "qcom,sc7280-dispcc"; 1369 reg = <0 0xaf00000 0 0x20000>; 1370 clocks = <&rpmhcc RPMH_CXO_CLK>, 1371 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1372 <0>, <0>, <0>, <0>, <0>, <0>; 1373 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1374 "dsi0_phy_pll_out_byteclk", 1375 "dsi0_phy_pll_out_dsiclk", 1376 "dp_phy_pll_link_clk", 1377 "dp_phy_pll_vco_div_clk", 1378 "edp_phy_pll_link_clk", 1379 "edp_phy_pll_vco_div_clk"; 1380 #clock-cells = <1>; 1381 #reset-cells = <1>; 1382 #power-domain-cells = <1>; 1383 }; 1384 1385 pdc: interrupt-controller@b220000 { 1386 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1387 reg = <0 0x0b220000 0 0x30000>; 1388 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1389 <55 306 4>, <59 312 3>, <62 374 2>, 1390 <64 434 2>, <66 438 3>, <69 86 1>, 1391 <70 520 54>, <124 609 31>, <155 63 1>, 1392 <156 716 12>; 1393 #interrupt-cells = <2>; 1394 interrupt-parent = <&intc>; 1395 interrupt-controller; 1396 }; 1397 1398 pdc_reset: reset-controller@b5e0000 { 1399 compatible = "qcom,sc7280-pdc-global"; 1400 reg = <0 0x0b5e0000 0 0x20000>; 1401 #reset-cells = <1>; 1402 }; 1403 1404 tsens0: thermal-sensor@c263000 { 1405 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1406 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1407 <0 0x0c222000 0 0x1ff>; /* SROT */ 1408 #qcom,sensors = <15>; 1409 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1411 interrupt-names = "uplow","critical"; 1412 #thermal-sensor-cells = <1>; 1413 }; 1414 1415 tsens1: thermal-sensor@c265000 { 1416 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1417 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1418 <0 0x0c223000 0 0x1ff>; /* SROT */ 1419 #qcom,sensors = <12>; 1420 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1422 interrupt-names = "uplow","critical"; 1423 #thermal-sensor-cells = <1>; 1424 }; 1425 1426 aoss_reset: reset-controller@c2a0000 { 1427 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1428 reg = <0 0x0c2a0000 0 0x31000>; 1429 #reset-cells = <1>; 1430 }; 1431 1432 aoss_qmp: power-controller@c300000 { 1433 compatible = "qcom,sc7280-aoss-qmp"; 1434 reg = <0 0x0c300000 0 0x100000>; 1435 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1436 IPCC_MPROC_SIGNAL_GLINK_QMP 1437 IRQ_TYPE_EDGE_RISING>; 1438 mboxes = <&ipcc IPCC_CLIENT_AOP 1439 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1440 1441 #clock-cells = <0>; 1442 #power-domain-cells = <1>; 1443 }; 1444 1445 spmi_bus: spmi@c440000 { 1446 compatible = "qcom,spmi-pmic-arb"; 1447 reg = <0 0x0c440000 0 0x1100>, 1448 <0 0x0c600000 0 0x2000000>, 1449 <0 0x0e600000 0 0x100000>, 1450 <0 0x0e700000 0 0xa0000>, 1451 <0 0x0c40a000 0 0x26000>; 1452 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1453 interrupt-names = "periph_irq"; 1454 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1455 qcom,ee = <0>; 1456 qcom,channel = <0>; 1457 #address-cells = <1>; 1458 #size-cells = <1>; 1459 interrupt-controller; 1460 #interrupt-cells = <4>; 1461 }; 1462 1463 tlmm: pinctrl@f100000 { 1464 compatible = "qcom,sc7280-pinctrl"; 1465 reg = <0 0x0f100000 0 0x300000>; 1466 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1467 gpio-controller; 1468 #gpio-cells = <2>; 1469 interrupt-controller; 1470 #interrupt-cells = <2>; 1471 gpio-ranges = <&tlmm 0 0 175>; 1472 wakeup-parent = <&pdc>; 1473 1474 qup_uart5_default: qup-uart5-default { 1475 pins = "gpio46", "gpio47"; 1476 function = "qup13"; 1477 }; 1478 1479 sdc1_on: sdc1-on { 1480 clk { 1481 pins = "sdc1_clk"; 1482 }; 1483 1484 cmd { 1485 pins = "sdc1_cmd"; 1486 }; 1487 1488 data { 1489 pins = "sdc1_data"; 1490 }; 1491 1492 rclk { 1493 pins = "sdc1_rclk"; 1494 }; 1495 }; 1496 1497 sdc1_off: sdc1-off { 1498 clk { 1499 pins = "sdc1_clk"; 1500 drive-strength = <2>; 1501 bias-bus-hold; 1502 }; 1503 1504 cmd { 1505 pins = "sdc1_cmd"; 1506 drive-strength = <2>; 1507 bias-bus-hold; 1508 }; 1509 1510 data { 1511 pins = "sdc1_data"; 1512 drive-strength = <2>; 1513 bias-bus-hold; 1514 }; 1515 1516 rclk { 1517 pins = "sdc1_rclk"; 1518 bias-bus-hold; 1519 }; 1520 }; 1521 1522 sdc2_on: sdc2-on { 1523 clk { 1524 pins = "sdc2_clk"; 1525 }; 1526 1527 cmd { 1528 pins = "sdc2_cmd"; 1529 }; 1530 1531 data { 1532 pins = "sdc2_data"; 1533 }; 1534 1535 sd-cd { 1536 pins = "gpio91"; 1537 }; 1538 }; 1539 1540 sdc2_off: sdc2-off { 1541 clk { 1542 pins = "sdc2_clk"; 1543 drive-strength = <2>; 1544 bias-bus-hold; 1545 }; 1546 1547 cmd { 1548 pins ="sdc2_cmd"; 1549 drive-strength = <2>; 1550 bias-bus-hold; 1551 }; 1552 1553 data { 1554 pins ="sdc2_data"; 1555 drive-strength = <2>; 1556 bias-bus-hold; 1557 }; 1558 }; 1559 }; 1560 1561 apps_smmu: iommu@15000000 { 1562 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1563 reg = <0 0x15000000 0 0x100000>; 1564 #iommu-cells = <2>; 1565 #global-interrupts = <1>; 1566 dma-coherent; 1567 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1648 }; 1649 1650 intc: interrupt-controller@17a00000 { 1651 compatible = "arm,gic-v3"; 1652 #address-cells = <2>; 1653 #size-cells = <2>; 1654 ranges; 1655 #interrupt-cells = <3>; 1656 interrupt-controller; 1657 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1658 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1659 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1660 1661 gic-its@17a40000 { 1662 compatible = "arm,gic-v3-its"; 1663 msi-controller; 1664 #msi-cells = <1>; 1665 reg = <0 0x17a40000 0 0x20000>; 1666 status = "disabled"; 1667 }; 1668 }; 1669 1670 watchdog@17c10000 { 1671 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1672 reg = <0 0x17c10000 0 0x1000>; 1673 clocks = <&sleep_clk>; 1674 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1675 }; 1676 1677 timer@17c20000 { 1678 #address-cells = <2>; 1679 #size-cells = <2>; 1680 ranges; 1681 compatible = "arm,armv7-timer-mem"; 1682 reg = <0 0x17c20000 0 0x1000>; 1683 1684 frame@17c21000 { 1685 frame-number = <0>; 1686 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1688 reg = <0 0x17c21000 0 0x1000>, 1689 <0 0x17c22000 0 0x1000>; 1690 }; 1691 1692 frame@17c23000 { 1693 frame-number = <1>; 1694 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1695 reg = <0 0x17c23000 0 0x1000>; 1696 status = "disabled"; 1697 }; 1698 1699 frame@17c25000 { 1700 frame-number = <2>; 1701 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1702 reg = <0 0x17c25000 0 0x1000>; 1703 status = "disabled"; 1704 }; 1705 1706 frame@17c27000 { 1707 frame-number = <3>; 1708 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1709 reg = <0 0x17c27000 0 0x1000>; 1710 status = "disabled"; 1711 }; 1712 1713 frame@17c29000 { 1714 frame-number = <4>; 1715 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1716 reg = <0 0x17c29000 0 0x1000>; 1717 status = "disabled"; 1718 }; 1719 1720 frame@17c2b000 { 1721 frame-number = <5>; 1722 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1723 reg = <0 0x17c2b000 0 0x1000>; 1724 status = "disabled"; 1725 }; 1726 1727 frame@17c2d000 { 1728 frame-number = <6>; 1729 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1730 reg = <0 0x17c2d000 0 0x1000>; 1731 status = "disabled"; 1732 }; 1733 }; 1734 1735 apps_rsc: rsc@18200000 { 1736 compatible = "qcom,rpmh-rsc"; 1737 reg = <0 0x18200000 0 0x10000>, 1738 <0 0x18210000 0 0x10000>, 1739 <0 0x18220000 0 0x10000>; 1740 reg-names = "drv-0", "drv-1", "drv-2"; 1741 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1744 qcom,tcs-offset = <0xd00>; 1745 qcom,drv-id = <2>; 1746 qcom,tcs-config = <ACTIVE_TCS 2>, 1747 <SLEEP_TCS 3>, 1748 <WAKE_TCS 3>, 1749 <CONTROL_TCS 1>; 1750 1751 apps_bcm_voter: bcm-voter { 1752 compatible = "qcom,bcm-voter"; 1753 }; 1754 1755 rpmhpd: power-controller { 1756 compatible = "qcom,sc7280-rpmhpd"; 1757 #power-domain-cells = <1>; 1758 operating-points-v2 = <&rpmhpd_opp_table>; 1759 1760 rpmhpd_opp_table: opp-table { 1761 compatible = "operating-points-v2"; 1762 1763 rpmhpd_opp_ret: opp1 { 1764 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1765 }; 1766 1767 rpmhpd_opp_low_svs: opp2 { 1768 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1769 }; 1770 1771 rpmhpd_opp_svs: opp3 { 1772 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1773 }; 1774 1775 rpmhpd_opp_svs_l1: opp4 { 1776 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1777 }; 1778 1779 rpmhpd_opp_svs_l2: opp5 { 1780 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1781 }; 1782 1783 rpmhpd_opp_nom: opp6 { 1784 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1785 }; 1786 1787 rpmhpd_opp_nom_l1: opp7 { 1788 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1789 }; 1790 1791 rpmhpd_opp_turbo: opp8 { 1792 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1793 }; 1794 1795 rpmhpd_opp_turbo_l1: opp9 { 1796 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1797 }; 1798 }; 1799 }; 1800 1801 rpmhcc: clock-controller { 1802 compatible = "qcom,sc7280-rpmh-clk"; 1803 clocks = <&xo_board>; 1804 clock-names = "xo"; 1805 #clock-cells = <1>; 1806 }; 1807 }; 1808 1809 cpufreq_hw: cpufreq@18591000 { 1810 compatible = "qcom,cpufreq-epss"; 1811 reg = <0 0x18591100 0 0x900>, 1812 <0 0x18592100 0 0x900>, 1813 <0 0x18593100 0 0x900>; 1814 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1815 clock-names = "xo", "alternate"; 1816 #freq-domain-cells = <1>; 1817 }; 1818 }; 1819 1820 thermal_zones: thermal-zones { 1821 cpu0-thermal { 1822 polling-delay-passive = <250>; 1823 polling-delay = <0>; 1824 1825 thermal-sensors = <&tsens0 1>; 1826 1827 trips { 1828 cpu0_alert0: trip-point0 { 1829 temperature = <90000>; 1830 hysteresis = <2000>; 1831 type = "passive"; 1832 }; 1833 1834 cpu0_alert1: trip-point1 { 1835 temperature = <95000>; 1836 hysteresis = <2000>; 1837 type = "passive"; 1838 }; 1839 1840 cpu0_crit: cpu-crit { 1841 temperature = <110000>; 1842 hysteresis = <0>; 1843 type = "critical"; 1844 }; 1845 }; 1846 1847 cooling-maps { 1848 map0 { 1849 trip = <&cpu0_alert0>; 1850 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1851 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1852 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1853 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1854 }; 1855 map1 { 1856 trip = <&cpu0_alert1>; 1857 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1858 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1859 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1860 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1861 }; 1862 }; 1863 }; 1864 1865 cpu1-thermal { 1866 polling-delay-passive = <250>; 1867 polling-delay = <0>; 1868 1869 thermal-sensors = <&tsens0 2>; 1870 1871 trips { 1872 cpu1_alert0: trip-point0 { 1873 temperature = <90000>; 1874 hysteresis = <2000>; 1875 type = "passive"; 1876 }; 1877 1878 cpu1_alert1: trip-point1 { 1879 temperature = <95000>; 1880 hysteresis = <2000>; 1881 type = "passive"; 1882 }; 1883 1884 cpu1_crit: cpu-crit { 1885 temperature = <110000>; 1886 hysteresis = <0>; 1887 type = "critical"; 1888 }; 1889 }; 1890 1891 cooling-maps { 1892 map0 { 1893 trip = <&cpu1_alert0>; 1894 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1895 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1896 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1897 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1898 }; 1899 map1 { 1900 trip = <&cpu1_alert1>; 1901 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1902 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1903 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1904 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1905 }; 1906 }; 1907 }; 1908 1909 cpu2-thermal { 1910 polling-delay-passive = <250>; 1911 polling-delay = <0>; 1912 1913 thermal-sensors = <&tsens0 3>; 1914 1915 trips { 1916 cpu2_alert0: trip-point0 { 1917 temperature = <90000>; 1918 hysteresis = <2000>; 1919 type = "passive"; 1920 }; 1921 1922 cpu2_alert1: trip-point1 { 1923 temperature = <95000>; 1924 hysteresis = <2000>; 1925 type = "passive"; 1926 }; 1927 1928 cpu2_crit: cpu-crit { 1929 temperature = <110000>; 1930 hysteresis = <0>; 1931 type = "critical"; 1932 }; 1933 }; 1934 1935 cooling-maps { 1936 map0 { 1937 trip = <&cpu2_alert0>; 1938 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1939 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1940 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1941 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1942 }; 1943 map1 { 1944 trip = <&cpu2_alert1>; 1945 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1946 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1947 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1948 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1949 }; 1950 }; 1951 }; 1952 1953 cpu3-thermal { 1954 polling-delay-passive = <250>; 1955 polling-delay = <0>; 1956 1957 thermal-sensors = <&tsens0 4>; 1958 1959 trips { 1960 cpu3_alert0: trip-point0 { 1961 temperature = <90000>; 1962 hysteresis = <2000>; 1963 type = "passive"; 1964 }; 1965 1966 cpu3_alert1: trip-point1 { 1967 temperature = <95000>; 1968 hysteresis = <2000>; 1969 type = "passive"; 1970 }; 1971 1972 cpu3_crit: cpu-crit { 1973 temperature = <110000>; 1974 hysteresis = <0>; 1975 type = "critical"; 1976 }; 1977 }; 1978 1979 cooling-maps { 1980 map0 { 1981 trip = <&cpu3_alert0>; 1982 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1983 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1984 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1985 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1986 }; 1987 map1 { 1988 trip = <&cpu3_alert1>; 1989 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1990 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1991 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1992 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1993 }; 1994 }; 1995 }; 1996 1997 cpu4-thermal { 1998 polling-delay-passive = <250>; 1999 polling-delay = <0>; 2000 2001 thermal-sensors = <&tsens0 7>; 2002 2003 trips { 2004 cpu4_alert0: trip-point0 { 2005 temperature = <90000>; 2006 hysteresis = <2000>; 2007 type = "passive"; 2008 }; 2009 2010 cpu4_alert1: trip-point1 { 2011 temperature = <95000>; 2012 hysteresis = <2000>; 2013 type = "passive"; 2014 }; 2015 2016 cpu4_crit: cpu-crit { 2017 temperature = <110000>; 2018 hysteresis = <0>; 2019 type = "critical"; 2020 }; 2021 }; 2022 2023 cooling-maps { 2024 map0 { 2025 trip = <&cpu4_alert0>; 2026 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2027 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2028 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2029 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2030 }; 2031 map1 { 2032 trip = <&cpu4_alert1>; 2033 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2034 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2035 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2036 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2037 }; 2038 }; 2039 }; 2040 2041 cpu5-thermal { 2042 polling-delay-passive = <250>; 2043 polling-delay = <0>; 2044 2045 thermal-sensors = <&tsens0 8>; 2046 2047 trips { 2048 cpu5_alert0: trip-point0 { 2049 temperature = <90000>; 2050 hysteresis = <2000>; 2051 type = "passive"; 2052 }; 2053 2054 cpu5_alert1: trip-point1 { 2055 temperature = <95000>; 2056 hysteresis = <2000>; 2057 type = "passive"; 2058 }; 2059 2060 cpu5_crit: cpu-crit { 2061 temperature = <110000>; 2062 hysteresis = <0>; 2063 type = "critical"; 2064 }; 2065 }; 2066 2067 cooling-maps { 2068 map0 { 2069 trip = <&cpu5_alert0>; 2070 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2071 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2072 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2073 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2074 }; 2075 map1 { 2076 trip = <&cpu5_alert1>; 2077 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2078 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2079 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2080 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2081 }; 2082 }; 2083 }; 2084 2085 cpu6-thermal { 2086 polling-delay-passive = <250>; 2087 polling-delay = <0>; 2088 2089 thermal-sensors = <&tsens0 9>; 2090 2091 trips { 2092 cpu6_alert0: trip-point0 { 2093 temperature = <90000>; 2094 hysteresis = <2000>; 2095 type = "passive"; 2096 }; 2097 2098 cpu6_alert1: trip-point1 { 2099 temperature = <95000>; 2100 hysteresis = <2000>; 2101 type = "passive"; 2102 }; 2103 2104 cpu6_crit: cpu-crit { 2105 temperature = <110000>; 2106 hysteresis = <0>; 2107 type = "critical"; 2108 }; 2109 }; 2110 2111 cooling-maps { 2112 map0 { 2113 trip = <&cpu6_alert0>; 2114 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2115 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2116 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2117 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2118 }; 2119 map1 { 2120 trip = <&cpu6_alert1>; 2121 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2122 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2123 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2124 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2125 }; 2126 }; 2127 }; 2128 2129 cpu7-thermal { 2130 polling-delay-passive = <250>; 2131 polling-delay = <0>; 2132 2133 thermal-sensors = <&tsens0 10>; 2134 2135 trips { 2136 cpu7_alert0: trip-point0 { 2137 temperature = <90000>; 2138 hysteresis = <2000>; 2139 type = "passive"; 2140 }; 2141 2142 cpu7_alert1: trip-point1 { 2143 temperature = <95000>; 2144 hysteresis = <2000>; 2145 type = "passive"; 2146 }; 2147 2148 cpu7_crit: cpu-crit { 2149 temperature = <110000>; 2150 hysteresis = <0>; 2151 type = "critical"; 2152 }; 2153 }; 2154 2155 cooling-maps { 2156 map0 { 2157 trip = <&cpu7_alert0>; 2158 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2159 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2160 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2161 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2162 }; 2163 map1 { 2164 trip = <&cpu7_alert1>; 2165 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2166 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2167 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2168 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2169 }; 2170 }; 2171 }; 2172 2173 cpu8-thermal { 2174 polling-delay-passive = <250>; 2175 polling-delay = <0>; 2176 2177 thermal-sensors = <&tsens0 11>; 2178 2179 trips { 2180 cpu8_alert0: trip-point0 { 2181 temperature = <90000>; 2182 hysteresis = <2000>; 2183 type = "passive"; 2184 }; 2185 2186 cpu8_alert1: trip-point1 { 2187 temperature = <95000>; 2188 hysteresis = <2000>; 2189 type = "passive"; 2190 }; 2191 2192 cpu8_crit: cpu-crit { 2193 temperature = <110000>; 2194 hysteresis = <0>; 2195 type = "critical"; 2196 }; 2197 }; 2198 2199 cooling-maps { 2200 map0 { 2201 trip = <&cpu8_alert0>; 2202 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2203 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2204 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2205 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2206 }; 2207 map1 { 2208 trip = <&cpu8_alert1>; 2209 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2210 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2211 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2212 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2213 }; 2214 }; 2215 }; 2216 2217 cpu9-thermal { 2218 polling-delay-passive = <250>; 2219 polling-delay = <0>; 2220 2221 thermal-sensors = <&tsens0 12>; 2222 2223 trips { 2224 cpu9_alert0: trip-point0 { 2225 temperature = <90000>; 2226 hysteresis = <2000>; 2227 type = "passive"; 2228 }; 2229 2230 cpu9_alert1: trip-point1 { 2231 temperature = <95000>; 2232 hysteresis = <2000>; 2233 type = "passive"; 2234 }; 2235 2236 cpu9_crit: cpu-crit { 2237 temperature = <110000>; 2238 hysteresis = <0>; 2239 type = "critical"; 2240 }; 2241 }; 2242 2243 cooling-maps { 2244 map0 { 2245 trip = <&cpu9_alert0>; 2246 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2247 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2248 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2249 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2250 }; 2251 map1 { 2252 trip = <&cpu9_alert1>; 2253 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2254 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2255 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2256 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2257 }; 2258 }; 2259 }; 2260 2261 cpu10-thermal { 2262 polling-delay-passive = <250>; 2263 polling-delay = <0>; 2264 2265 thermal-sensors = <&tsens0 13>; 2266 2267 trips { 2268 cpu10_alert0: trip-point0 { 2269 temperature = <90000>; 2270 hysteresis = <2000>; 2271 type = "passive"; 2272 }; 2273 2274 cpu10_alert1: trip-point1 { 2275 temperature = <95000>; 2276 hysteresis = <2000>; 2277 type = "passive"; 2278 }; 2279 2280 cpu10_crit: cpu-crit { 2281 temperature = <110000>; 2282 hysteresis = <0>; 2283 type = "critical"; 2284 }; 2285 }; 2286 2287 cooling-maps { 2288 map0 { 2289 trip = <&cpu10_alert0>; 2290 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2291 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2292 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2293 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2294 }; 2295 map1 { 2296 trip = <&cpu10_alert1>; 2297 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2298 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2299 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2300 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2301 }; 2302 }; 2303 }; 2304 2305 cpu11-thermal { 2306 polling-delay-passive = <250>; 2307 polling-delay = <0>; 2308 2309 thermal-sensors = <&tsens0 14>; 2310 2311 trips { 2312 cpu11_alert0: trip-point0 { 2313 temperature = <90000>; 2314 hysteresis = <2000>; 2315 type = "passive"; 2316 }; 2317 2318 cpu11_alert1: trip-point1 { 2319 temperature = <95000>; 2320 hysteresis = <2000>; 2321 type = "passive"; 2322 }; 2323 2324 cpu11_crit: cpu-crit { 2325 temperature = <110000>; 2326 hysteresis = <0>; 2327 type = "critical"; 2328 }; 2329 }; 2330 2331 cooling-maps { 2332 map0 { 2333 trip = <&cpu11_alert0>; 2334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2338 }; 2339 map1 { 2340 trip = <&cpu11_alert1>; 2341 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2342 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2343 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2344 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2345 }; 2346 }; 2347 }; 2348 2349 aoss0-thermal { 2350 polling-delay-passive = <0>; 2351 polling-delay = <0>; 2352 2353 thermal-sensors = <&tsens0 0>; 2354 2355 trips { 2356 aoss0_alert0: trip-point0 { 2357 temperature = <90000>; 2358 hysteresis = <2000>; 2359 type = "hot"; 2360 }; 2361 2362 aoss0_crit: aoss0-crit { 2363 temperature = <110000>; 2364 hysteresis = <0>; 2365 type = "critical"; 2366 }; 2367 }; 2368 }; 2369 2370 aoss1-thermal { 2371 polling-delay-passive = <0>; 2372 polling-delay = <0>; 2373 2374 thermal-sensors = <&tsens1 0>; 2375 2376 trips { 2377 aoss1_alert0: trip-point0 { 2378 temperature = <90000>; 2379 hysteresis = <2000>; 2380 type = "hot"; 2381 }; 2382 2383 aoss1_crit: aoss1-crit { 2384 temperature = <110000>; 2385 hysteresis = <0>; 2386 type = "critical"; 2387 }; 2388 }; 2389 }; 2390 2391 cpuss0-thermal { 2392 polling-delay-passive = <0>; 2393 polling-delay = <0>; 2394 2395 thermal-sensors = <&tsens0 5>; 2396 2397 trips { 2398 cpuss0_alert0: trip-point0 { 2399 temperature = <90000>; 2400 hysteresis = <2000>; 2401 type = "hot"; 2402 }; 2403 cpuss0_crit: cluster0-crit { 2404 temperature = <110000>; 2405 hysteresis = <0>; 2406 type = "critical"; 2407 }; 2408 }; 2409 }; 2410 2411 cpuss1-thermal { 2412 polling-delay-passive = <0>; 2413 polling-delay = <0>; 2414 2415 thermal-sensors = <&tsens0 6>; 2416 2417 trips { 2418 cpuss1_alert0: trip-point0 { 2419 temperature = <90000>; 2420 hysteresis = <2000>; 2421 type = "hot"; 2422 }; 2423 cpuss1_crit: cluster0-crit { 2424 temperature = <110000>; 2425 hysteresis = <0>; 2426 type = "critical"; 2427 }; 2428 }; 2429 }; 2430 2431 gpuss0-thermal { 2432 polling-delay-passive = <0>; 2433 polling-delay = <0>; 2434 2435 thermal-sensors = <&tsens1 1>; 2436 2437 trips { 2438 gpuss0_alert0: trip-point0 { 2439 temperature = <90000>; 2440 hysteresis = <2000>; 2441 type = "hot"; 2442 }; 2443 2444 gpuss0_crit: gpuss0-crit { 2445 temperature = <110000>; 2446 hysteresis = <0>; 2447 type = "critical"; 2448 }; 2449 }; 2450 }; 2451 2452 gpuss1-thermal { 2453 polling-delay-passive = <0>; 2454 polling-delay = <0>; 2455 2456 thermal-sensors = <&tsens1 2>; 2457 2458 trips { 2459 gpuss1_alert0: trip-point0 { 2460 temperature = <90000>; 2461 hysteresis = <2000>; 2462 type = "hot"; 2463 }; 2464 2465 gpuss1_crit: gpuss1-crit { 2466 temperature = <110000>; 2467 hysteresis = <0>; 2468 type = "critical"; 2469 }; 2470 }; 2471 }; 2472 2473 nspss0-thermal { 2474 polling-delay-passive = <0>; 2475 polling-delay = <0>; 2476 2477 thermal-sensors = <&tsens1 3>; 2478 2479 trips { 2480 nspss0_alert0: trip-point0 { 2481 temperature = <90000>; 2482 hysteresis = <2000>; 2483 type = "hot"; 2484 }; 2485 2486 nspss0_crit: nspss0-crit { 2487 temperature = <110000>; 2488 hysteresis = <0>; 2489 type = "critical"; 2490 }; 2491 }; 2492 }; 2493 2494 nspss1-thermal { 2495 polling-delay-passive = <0>; 2496 polling-delay = <0>; 2497 2498 thermal-sensors = <&tsens1 4>; 2499 2500 trips { 2501 nspss1_alert0: trip-point0 { 2502 temperature = <90000>; 2503 hysteresis = <2000>; 2504 type = "hot"; 2505 }; 2506 2507 nspss1_crit: nspss1-crit { 2508 temperature = <110000>; 2509 hysteresis = <0>; 2510 type = "critical"; 2511 }; 2512 }; 2513 }; 2514 2515 video-thermal { 2516 polling-delay-passive = <0>; 2517 polling-delay = <0>; 2518 2519 thermal-sensors = <&tsens1 5>; 2520 2521 trips { 2522 video_alert0: trip-point0 { 2523 temperature = <90000>; 2524 hysteresis = <2000>; 2525 type = "hot"; 2526 }; 2527 2528 video_crit: video-crit { 2529 temperature = <110000>; 2530 hysteresis = <0>; 2531 type = "critical"; 2532 }; 2533 }; 2534 }; 2535 2536 ddr-thermal { 2537 polling-delay-passive = <0>; 2538 polling-delay = <0>; 2539 2540 thermal-sensors = <&tsens1 6>; 2541 2542 trips { 2543 ddr_alert0: trip-point0 { 2544 temperature = <90000>; 2545 hysteresis = <2000>; 2546 type = "hot"; 2547 }; 2548 2549 ddr_crit: ddr-crit { 2550 temperature = <110000>; 2551 hysteresis = <0>; 2552 type = "critical"; 2553 }; 2554 }; 2555 }; 2556 2557 mdmss0-thermal { 2558 polling-delay-passive = <0>; 2559 polling-delay = <0>; 2560 2561 thermal-sensors = <&tsens1 7>; 2562 2563 trips { 2564 mdmss0_alert0: trip-point0 { 2565 temperature = <90000>; 2566 hysteresis = <2000>; 2567 type = "hot"; 2568 }; 2569 2570 mdmss0_crit: mdmss0-crit { 2571 temperature = <110000>; 2572 hysteresis = <0>; 2573 type = "critical"; 2574 }; 2575 }; 2576 }; 2577 2578 mdmss1-thermal { 2579 polling-delay-passive = <0>; 2580 polling-delay = <0>; 2581 2582 thermal-sensors = <&tsens1 8>; 2583 2584 trips { 2585 mdmss1_alert0: trip-point0 { 2586 temperature = <90000>; 2587 hysteresis = <2000>; 2588 type = "hot"; 2589 }; 2590 2591 mdmss1_crit: mdmss1-crit { 2592 temperature = <110000>; 2593 hysteresis = <0>; 2594 type = "critical"; 2595 }; 2596 }; 2597 }; 2598 2599 mdmss2-thermal { 2600 polling-delay-passive = <0>; 2601 polling-delay = <0>; 2602 2603 thermal-sensors = <&tsens1 9>; 2604 2605 trips { 2606 mdmss2_alert0: trip-point0 { 2607 temperature = <90000>; 2608 hysteresis = <2000>; 2609 type = "hot"; 2610 }; 2611 2612 mdmss2_crit: mdmss2-crit { 2613 temperature = <110000>; 2614 hysteresis = <0>; 2615 type = "critical"; 2616 }; 2617 }; 2618 }; 2619 2620 mdmss3-thermal { 2621 polling-delay-passive = <0>; 2622 polling-delay = <0>; 2623 2624 thermal-sensors = <&tsens1 10>; 2625 2626 trips { 2627 mdmss3_alert0: trip-point0 { 2628 temperature = <90000>; 2629 hysteresis = <2000>; 2630 type = "hot"; 2631 }; 2632 2633 mdmss3_crit: mdmss3-crit { 2634 temperature = <110000>; 2635 hysteresis = <0>; 2636 type = "critical"; 2637 }; 2638 }; 2639 }; 2640 2641 camera0-thermal { 2642 polling-delay-passive = <0>; 2643 polling-delay = <0>; 2644 2645 thermal-sensors = <&tsens1 11>; 2646 2647 trips { 2648 camera0_alert0: trip-point0 { 2649 temperature = <90000>; 2650 hysteresis = <2000>; 2651 type = "hot"; 2652 }; 2653 2654 camera0_crit: camera0-crit { 2655 temperature = <110000>; 2656 hysteresis = <0>; 2657 type = "critical"; 2658 }; 2659 }; 2660 }; 2661 }; 2662 2663 timer { 2664 compatible = "arm,armv8-timer"; 2665 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2666 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2667 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2668 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2669 }; 2670}; 2671