1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sc7280.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/reset/qcom,sdm845-aoss.h> 22#include <dt-bindings/reset/qcom,sdm845-pdc.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 aliases { 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 i2c12 = &i2c12; 48 i2c13 = &i2c13; 49 i2c14 = &i2c14; 50 i2c15 = &i2c15; 51 mmc1 = &sdhc_1; 52 mmc2 = &sdhc_2; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 }; 70 71 clocks { 72 xo_board: xo-board { 73 compatible = "fixed-clock"; 74 clock-frequency = <76800000>; 75 #clock-cells = <0>; 76 }; 77 78 sleep_clk: sleep-clk { 79 compatible = "fixed-clock"; 80 clock-frequency = <32000>; 81 #clock-cells = <0>; 82 }; 83 }; 84 85 reserved-memory { 86 #address-cells = <2>; 87 #size-cells = <2>; 88 ranges; 89 90 wlan_ce_mem: memory@4cd000 { 91 no-map; 92 reg = <0x0 0x004cd000 0x0 0x1000>; 93 }; 94 95 hyp_mem: memory@80000000 { 96 reg = <0x0 0x80000000 0x0 0x600000>; 97 no-map; 98 }; 99 100 xbl_mem: memory@80600000 { 101 reg = <0x0 0x80600000 0x0 0x200000>; 102 no-map; 103 }; 104 105 aop_mem: memory@80800000 { 106 reg = <0x0 0x80800000 0x0 0x60000>; 107 no-map; 108 }; 109 110 aop_cmd_db_mem: memory@80860000 { 111 reg = <0x0 0x80860000 0x0 0x20000>; 112 compatible = "qcom,cmd-db"; 113 no-map; 114 }; 115 116 reserved_xbl_uefi_log: memory@80880000 { 117 reg = <0x0 0x80884000 0x0 0x10000>; 118 no-map; 119 }; 120 121 sec_apps_mem: memory@808ff000 { 122 reg = <0x0 0x808ff000 0x0 0x1000>; 123 no-map; 124 }; 125 126 smem_mem: memory@80900000 { 127 reg = <0x0 0x80900000 0x0 0x200000>; 128 no-map; 129 }; 130 131 cpucp_mem: memory@80b00000 { 132 no-map; 133 reg = <0x0 0x80b00000 0x0 0x100000>; 134 }; 135 136 wlan_fw_mem: memory@80c00000 { 137 reg = <0x0 0x80c00000 0x0 0xc00000>; 138 no-map; 139 }; 140 141 video_mem: memory@8b200000 { 142 reg = <0x0 0x8b200000 0x0 0x500000>; 143 no-map; 144 }; 145 146 ipa_fw_mem: memory@8b700000 { 147 reg = <0 0x8b700000 0 0x10000>; 148 no-map; 149 }; 150 151 rmtfs_mem: memory@9c900000 { 152 compatible = "qcom,rmtfs-mem"; 153 reg = <0x0 0x9c900000 0x0 0x280000>; 154 no-map; 155 156 qcom,client-id = <1>; 157 qcom,vmid = <15>; 158 }; 159 }; 160 161 cpus { 162 #address-cells = <2>; 163 #size-cells = <0>; 164 165 CPU0: cpu@0 { 166 device_type = "cpu"; 167 compatible = "arm,kryo"; 168 reg = <0x0 0x0>; 169 enable-method = "psci"; 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 171 &LITTLE_CPU_SLEEP_1 172 &CLUSTER_SLEEP_0>; 173 next-level-cache = <&L2_0>; 174 operating-points-v2 = <&cpu0_opp_table>; 175 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 176 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 177 qcom,freq-domain = <&cpufreq_hw 0>; 178 #cooling-cells = <2>; 179 L2_0: l2-cache { 180 compatible = "cache"; 181 next-level-cache = <&L3_0>; 182 L3_0: l3-cache { 183 compatible = "cache"; 184 }; 185 }; 186 }; 187 188 CPU1: cpu@100 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x100>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_100>; 197 operating-points-v2 = <&cpu0_opp_table>; 198 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 199 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 200 qcom,freq-domain = <&cpufreq_hw 0>; 201 #cooling-cells = <2>; 202 L2_100: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU2: cpu@200 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x200>; 212 enable-method = "psci"; 213 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 214 &LITTLE_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_200>; 217 operating-points-v2 = <&cpu0_opp_table>; 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 219 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 L2_200: l2-cache { 223 compatible = "cache"; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU3: cpu@300 { 229 device_type = "cpu"; 230 compatible = "arm,kryo"; 231 reg = <0x0 0x300>; 232 enable-method = "psci"; 233 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 234 &LITTLE_CPU_SLEEP_1 235 &CLUSTER_SLEEP_0>; 236 next-level-cache = <&L2_300>; 237 operating-points-v2 = <&cpu0_opp_table>; 238 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 239 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 240 qcom,freq-domain = <&cpufreq_hw 0>; 241 #cooling-cells = <2>; 242 L2_300: l2-cache { 243 compatible = "cache"; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU4: cpu@400 { 249 device_type = "cpu"; 250 compatible = "arm,kryo"; 251 reg = <0x0 0x400>; 252 enable-method = "psci"; 253 cpu-idle-states = <&BIG_CPU_SLEEP_0 254 &BIG_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 next-level-cache = <&L2_400>; 257 operating-points-v2 = <&cpu4_opp_table>; 258 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 259 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 260 qcom,freq-domain = <&cpufreq_hw 1>; 261 #cooling-cells = <2>; 262 L2_400: l2-cache { 263 compatible = "cache"; 264 next-level-cache = <&L3_0>; 265 }; 266 }; 267 268 CPU5: cpu@500 { 269 device_type = "cpu"; 270 compatible = "arm,kryo"; 271 reg = <0x0 0x500>; 272 enable-method = "psci"; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276 next-level-cache = <&L2_500>; 277 operating-points-v2 = <&cpu4_opp_table>; 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 279 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 280 qcom,freq-domain = <&cpufreq_hw 1>; 281 #cooling-cells = <2>; 282 L2_500: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU6: cpu@600 { 289 device_type = "cpu"; 290 compatible = "arm,kryo"; 291 reg = <0x0 0x600>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_600>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_600: l2-cache { 303 compatible = "cache"; 304 next-level-cache = <&L3_0>; 305 }; 306 }; 307 308 CPU7: cpu@700 { 309 device_type = "cpu"; 310 compatible = "arm,kryo"; 311 reg = <0x0 0x700>; 312 enable-method = "psci"; 313 cpu-idle-states = <&BIG_CPU_SLEEP_0 314 &BIG_CPU_SLEEP_1 315 &CLUSTER_SLEEP_0>; 316 next-level-cache = <&L2_700>; 317 operating-points-v2 = <&cpu7_opp_table>; 318 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 319 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 320 qcom,freq-domain = <&cpufreq_hw 2>; 321 #cooling-cells = <2>; 322 L2_700: l2-cache { 323 compatible = "cache"; 324 next-level-cache = <&L3_0>; 325 }; 326 }; 327 328 cpu-map { 329 cluster0 { 330 core0 { 331 cpu = <&CPU0>; 332 }; 333 334 core1 { 335 cpu = <&CPU1>; 336 }; 337 338 core2 { 339 cpu = <&CPU2>; 340 }; 341 342 core3 { 343 cpu = <&CPU3>; 344 }; 345 346 core4 { 347 cpu = <&CPU4>; 348 }; 349 350 core5 { 351 cpu = <&CPU5>; 352 }; 353 354 core6 { 355 cpu = <&CPU6>; 356 }; 357 358 core7 { 359 cpu = <&CPU7>; 360 }; 361 }; 362 }; 363 364 idle-states { 365 entry-method = "psci"; 366 367 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 368 compatible = "arm,idle-state"; 369 idle-state-name = "little-power-down"; 370 arm,psci-suspend-param = <0x40000003>; 371 entry-latency-us = <549>; 372 exit-latency-us = <901>; 373 min-residency-us = <1774>; 374 local-timer-stop; 375 }; 376 377 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 378 compatible = "arm,idle-state"; 379 idle-state-name = "little-rail-power-down"; 380 arm,psci-suspend-param = <0x40000004>; 381 entry-latency-us = <702>; 382 exit-latency-us = <915>; 383 min-residency-us = <4001>; 384 local-timer-stop; 385 }; 386 387 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 388 compatible = "arm,idle-state"; 389 idle-state-name = "big-power-down"; 390 arm,psci-suspend-param = <0x40000003>; 391 entry-latency-us = <523>; 392 exit-latency-us = <1244>; 393 min-residency-us = <2207>; 394 local-timer-stop; 395 }; 396 397 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 398 compatible = "arm,idle-state"; 399 idle-state-name = "big-rail-power-down"; 400 arm,psci-suspend-param = <0x40000004>; 401 entry-latency-us = <526>; 402 exit-latency-us = <1854>; 403 min-residency-us = <5555>; 404 local-timer-stop; 405 }; 406 407 CLUSTER_SLEEP_0: cluster-sleep-0 { 408 compatible = "arm,idle-state"; 409 idle-state-name = "cluster-power-down"; 410 arm,psci-suspend-param = <0x40003444>; 411 entry-latency-us = <3263>; 412 exit-latency-us = <6562>; 413 min-residency-us = <9926>; 414 local-timer-stop; 415 }; 416 }; 417 }; 418 419 cpu0_opp_table: cpu0-opp-table { 420 compatible = "operating-points-v2"; 421 opp-shared; 422 423 cpu0_opp_300mhz: opp-300000000 { 424 opp-hz = /bits/ 64 <300000000>; 425 opp-peak-kBps = <800000 9600000>; 426 }; 427 428 cpu0_opp_691mhz: opp-691200000 { 429 opp-hz = /bits/ 64 <691200000>; 430 opp-peak-kBps = <800000 17817600>; 431 }; 432 433 cpu0_opp_806mhz: opp-806400000 { 434 opp-hz = /bits/ 64 <806400000>; 435 opp-peak-kBps = <800000 20889600>; 436 }; 437 438 cpu0_opp_941mhz: opp-940800000 { 439 opp-hz = /bits/ 64 <940800000>; 440 opp-peak-kBps = <1804000 24576000>; 441 }; 442 443 cpu0_opp_1152mhz: opp-1152000000 { 444 opp-hz = /bits/ 64 <1152000000>; 445 opp-peak-kBps = <2188000 27033600>; 446 }; 447 448 cpu0_opp_1325mhz: opp-1324800000 { 449 opp-hz = /bits/ 64 <1324800000>; 450 opp-peak-kBps = <2188000 33792000>; 451 }; 452 453 cpu0_opp_1517mhz: opp-1516800000 { 454 opp-hz = /bits/ 64 <1516800000>; 455 opp-peak-kBps = <3072000 38092800>; 456 }; 457 458 cpu0_opp_1651mhz: opp-1651200000 { 459 opp-hz = /bits/ 64 <1651200000>; 460 opp-peak-kBps = <3072000 41779200>; 461 }; 462 463 cpu0_opp_1805mhz: opp-1804800000 { 464 opp-hz = /bits/ 64 <1804800000>; 465 opp-peak-kBps = <4068000 48537600>; 466 }; 467 468 cpu0_opp_1958mhz: opp-1958400000 { 469 opp-hz = /bits/ 64 <1958400000>; 470 opp-peak-kBps = <4068000 48537600>; 471 }; 472 473 cpu0_opp_2016mhz: opp-2016000000 { 474 opp-hz = /bits/ 64 <2016000000>; 475 opp-peak-kBps = <6220000 48537600>; 476 }; 477 }; 478 479 cpu4_opp_table: cpu4-opp-table { 480 compatible = "operating-points-v2"; 481 opp-shared; 482 483 cpu4_opp_691mhz: opp-691200000 { 484 opp-hz = /bits/ 64 <691200000>; 485 opp-peak-kBps = <1804000 9600000>; 486 }; 487 488 cpu4_opp_941mhz: opp-940800000 { 489 opp-hz = /bits/ 64 <940800000>; 490 opp-peak-kBps = <2188000 17817600>; 491 }; 492 493 cpu4_opp_1229mhz: opp-1228800000 { 494 opp-hz = /bits/ 64 <1228800000>; 495 opp-peak-kBps = <4068000 24576000>; 496 }; 497 498 cpu4_opp_1344mhz: opp-1344000000 { 499 opp-hz = /bits/ 64 <1344000000>; 500 opp-peak-kBps = <4068000 24576000>; 501 }; 502 503 cpu4_opp_1517mhz: opp-1516800000 { 504 opp-hz = /bits/ 64 <1516800000>; 505 opp-peak-kBps = <4068000 24576000>; 506 }; 507 508 cpu4_opp_1651mhz: opp-1651200000 { 509 opp-hz = /bits/ 64 <1651200000>; 510 opp-peak-kBps = <6220000 38092800>; 511 }; 512 513 cpu4_opp_1901mhz: opp-1900800000 { 514 opp-hz = /bits/ 64 <1900800000>; 515 opp-peak-kBps = <6220000 44851200>; 516 }; 517 518 cpu4_opp_2054mhz: opp-2054400000 { 519 opp-hz = /bits/ 64 <2054400000>; 520 opp-peak-kBps = <6220000 44851200>; 521 }; 522 523 cpu4_opp_2112mhz: opp-2112000000 { 524 opp-hz = /bits/ 64 <2112000000>; 525 opp-peak-kBps = <6220000 44851200>; 526 }; 527 528 cpu4_opp_2131mhz: opp-2131200000 { 529 opp-hz = /bits/ 64 <2131200000>; 530 opp-peak-kBps = <6220000 44851200>; 531 }; 532 533 cpu4_opp_2208mhz: opp-2208000000 { 534 opp-hz = /bits/ 64 <2208000000>; 535 opp-peak-kBps = <6220000 44851200>; 536 }; 537 538 cpu4_opp_2400mhz: opp-2400000000 { 539 opp-hz = /bits/ 64 <2400000000>; 540 opp-peak-kBps = <8532000 48537600>; 541 }; 542 543 cpu4_opp_2611mhz: opp-2611200000 { 544 opp-hz = /bits/ 64 <2611200000>; 545 opp-peak-kBps = <8532000 48537600>; 546 }; 547 }; 548 549 cpu7_opp_table: cpu7-opp-table { 550 compatible = "operating-points-v2"; 551 opp-shared; 552 553 cpu7_opp_806mhz: opp-806400000 { 554 opp-hz = /bits/ 64 <806400000>; 555 opp-peak-kBps = <1804000 9600000>; 556 }; 557 558 cpu7_opp_1056mhz: opp-1056000000 { 559 opp-hz = /bits/ 64 <1056000000>; 560 opp-peak-kBps = <2188000 17817600>; 561 }; 562 563 cpu7_opp_1325mhz: opp-1324800000 { 564 opp-hz = /bits/ 64 <1324800000>; 565 opp-peak-kBps = <4068000 24576000>; 566 }; 567 568 cpu7_opp_1517mhz: opp-1516800000 { 569 opp-hz = /bits/ 64 <1516800000>; 570 opp-peak-kBps = <4068000 24576000>; 571 }; 572 573 cpu7_opp_1766mhz: opp-1766400000 { 574 opp-hz = /bits/ 64 <1766400000>; 575 opp-peak-kBps = <6220000 38092800>; 576 }; 577 578 cpu7_opp_1862mhz: opp-1862400000 { 579 opp-hz = /bits/ 64 <1862400000>; 580 opp-peak-kBps = <6220000 38092800>; 581 }; 582 583 cpu7_opp_2035mhz: opp-2035200000 { 584 opp-hz = /bits/ 64 <2035200000>; 585 opp-peak-kBps = <6220000 38092800>; 586 }; 587 588 cpu7_opp_2112mhz: opp-2112000000 { 589 opp-hz = /bits/ 64 <2112000000>; 590 opp-peak-kBps = <6220000 44851200>; 591 }; 592 593 cpu7_opp_2208mhz: opp-2208000000 { 594 opp-hz = /bits/ 64 <2208000000>; 595 opp-peak-kBps = <6220000 44851200>; 596 }; 597 598 cpu7_opp_2381mhz: opp-2380800000 { 599 opp-hz = /bits/ 64 <2380800000>; 600 opp-peak-kBps = <6832000 44851200>; 601 }; 602 603 cpu7_opp_2400mhz: opp-2400000000 { 604 opp-hz = /bits/ 64 <2400000000>; 605 opp-peak-kBps = <8532000 48537600>; 606 }; 607 608 cpu7_opp_2515mhz: opp-2515200000 { 609 opp-hz = /bits/ 64 <2515200000>; 610 opp-peak-kBps = <8532000 48537600>; 611 }; 612 613 cpu7_opp_2707mhz: opp-2707200000 { 614 opp-hz = /bits/ 64 <2707200000>; 615 opp-peak-kBps = <8532000 48537600>; 616 }; 617 618 cpu7_opp_3014mhz: opp-3014400000 { 619 opp-hz = /bits/ 64 <3014400000>; 620 opp-peak-kBps = <8532000 48537600>; 621 }; 622 }; 623 624 memory@80000000 { 625 device_type = "memory"; 626 /* We expect the bootloader to fill in the size */ 627 reg = <0 0x80000000 0 0>; 628 }; 629 630 firmware { 631 scm { 632 compatible = "qcom,scm-sc7280", "qcom,scm"; 633 }; 634 }; 635 636 clk_virt: interconnect { 637 compatible = "qcom,sc7280-clk-virt"; 638 #interconnect-cells = <2>; 639 qcom,bcm-voters = <&apps_bcm_voter>; 640 }; 641 642 smem { 643 compatible = "qcom,smem"; 644 memory-region = <&smem_mem>; 645 hwlocks = <&tcsr_mutex 3>; 646 }; 647 648 smp2p-adsp { 649 compatible = "qcom,smp2p"; 650 qcom,smem = <443>, <429>; 651 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 652 IPCC_MPROC_SIGNAL_SMP2P 653 IRQ_TYPE_EDGE_RISING>; 654 mboxes = <&ipcc IPCC_CLIENT_LPASS 655 IPCC_MPROC_SIGNAL_SMP2P>; 656 657 qcom,local-pid = <0>; 658 qcom,remote-pid = <2>; 659 660 adsp_smp2p_out: master-kernel { 661 qcom,entry-name = "master-kernel"; 662 #qcom,smem-state-cells = <1>; 663 }; 664 665 adsp_smp2p_in: slave-kernel { 666 qcom,entry-name = "slave-kernel"; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 }; 670 }; 671 672 smp2p-cdsp { 673 compatible = "qcom,smp2p"; 674 qcom,smem = <94>, <432>; 675 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 676 IPCC_MPROC_SIGNAL_SMP2P 677 IRQ_TYPE_EDGE_RISING>; 678 mboxes = <&ipcc IPCC_CLIENT_CDSP 679 IPCC_MPROC_SIGNAL_SMP2P>; 680 681 qcom,local-pid = <0>; 682 qcom,remote-pid = <5>; 683 684 cdsp_smp2p_out: master-kernel { 685 qcom,entry-name = "master-kernel"; 686 #qcom,smem-state-cells = <1>; 687 }; 688 689 cdsp_smp2p_in: slave-kernel { 690 qcom,entry-name = "slave-kernel"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 }; 695 696 smp2p-mpss { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <435>, <428>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_MPSS 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <1>; 707 708 modem_smp2p_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 modem_smp2p_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 719 ipa_smp2p_out: ipa-ap-to-modem { 720 qcom,entry-name = "ipa"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 ipa_smp2p_in: ipa-modem-to-ap { 725 qcom,entry-name = "ipa"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 }; 730 731 smp2p-wpss { 732 compatible = "qcom,smp2p"; 733 qcom,smem = <617>, <616>; 734 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 735 IPCC_MPROC_SIGNAL_SMP2P 736 IRQ_TYPE_EDGE_RISING>; 737 mboxes = <&ipcc IPCC_CLIENT_WPSS 738 IPCC_MPROC_SIGNAL_SMP2P>; 739 740 qcom,local-pid = <0>; 741 qcom,remote-pid = <13>; 742 743 wpss_smp2p_out: master-kernel { 744 qcom,entry-name = "master-kernel"; 745 #qcom,smem-state-cells = <1>; 746 }; 747 748 wpss_smp2p_in: slave-kernel { 749 qcom,entry-name = "slave-kernel"; 750 interrupt-controller; 751 #interrupt-cells = <2>; 752 }; 753 }; 754 755 pmu { 756 compatible = "arm,armv8-pmuv3"; 757 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 758 }; 759 760 psci { 761 compatible = "arm,psci-1.0"; 762 method = "smc"; 763 }; 764 765 qspi_opp_table: qspi-opp-table { 766 compatible = "operating-points-v2"; 767 768 opp-75000000 { 769 opp-hz = /bits/ 64 <75000000>; 770 required-opps = <&rpmhpd_opp_low_svs>; 771 }; 772 773 opp-150000000 { 774 opp-hz = /bits/ 64 <150000000>; 775 required-opps = <&rpmhpd_opp_svs>; 776 }; 777 778 opp-200000000 { 779 opp-hz = /bits/ 64 <200000000>; 780 required-opps = <&rpmhpd_opp_svs_l1>; 781 }; 782 783 opp-300000000 { 784 opp-hz = /bits/ 64 <300000000>; 785 required-opps = <&rpmhpd_opp_nom>; 786 }; 787 }; 788 789 qup_opp_table: qup-opp-table { 790 compatible = "operating-points-v2"; 791 792 opp-75000000 { 793 opp-hz = /bits/ 64 <75000000>; 794 required-opps = <&rpmhpd_opp_low_svs>; 795 }; 796 797 opp-100000000 { 798 opp-hz = /bits/ 64 <100000000>; 799 required-opps = <&rpmhpd_opp_svs>; 800 }; 801 802 opp-128000000 { 803 opp-hz = /bits/ 64 <128000000>; 804 required-opps = <&rpmhpd_opp_nom>; 805 }; 806 }; 807 808 soc: soc@0 { 809 #address-cells = <2>; 810 #size-cells = <2>; 811 ranges = <0 0 0 0 0x10 0>; 812 dma-ranges = <0 0 0 0 0x10 0>; 813 compatible = "simple-bus"; 814 815 gcc: clock-controller@100000 { 816 compatible = "qcom,gcc-sc7280"; 817 reg = <0 0x00100000 0 0x1f0000>; 818 clocks = <&rpmhcc RPMH_CXO_CLK>, 819 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 820 <0>, <&pcie1_lane 0>, 821 <0>, <0>, <0>, <0>; 822 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 823 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 824 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 825 "ufs_phy_tx_symbol_0_clk", 826 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 827 #clock-cells = <1>; 828 #reset-cells = <1>; 829 #power-domain-cells = <1>; 830 }; 831 832 ipcc: mailbox@408000 { 833 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 834 reg = <0 0x00408000 0 0x1000>; 835 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-controller; 837 #interrupt-cells = <3>; 838 #mbox-cells = <2>; 839 }; 840 841 qfprom: efuse@784000 { 842 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 843 reg = <0 0x00784000 0 0xa20>, 844 <0 0x00780000 0 0xa20>, 845 <0 0x00782000 0 0x120>, 846 <0 0x00786000 0 0x1fff>; 847 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 848 clock-names = "core"; 849 power-domains = <&rpmhpd SC7280_MX>; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 853 gpu_speed_bin: gpu_speed_bin@1e9 { 854 reg = <0x1e9 0x2>; 855 bits = <5 8>; 856 }; 857 }; 858 859 sdhc_1: sdhci@7c4000 { 860 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 861 pinctrl-names = "default", "sleep"; 862 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 863 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 864 status = "disabled"; 865 866 reg = <0 0x007c4000 0 0x1000>, 867 <0 0x007c5000 0 0x1000>; 868 reg-names = "hc", "cqhci"; 869 870 iommus = <&apps_smmu 0xc0 0x0>; 871 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "hc_irq", "pwr_irq"; 874 875 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 876 <&gcc GCC_SDCC1_AHB_CLK>, 877 <&rpmhcc RPMH_CXO_CLK>; 878 clock-names = "core", "iface", "xo"; 879 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 880 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 881 interconnect-names = "sdhc-ddr","cpu-sdhc"; 882 power-domains = <&rpmhpd SC7280_CX>; 883 operating-points-v2 = <&sdhc1_opp_table>; 884 885 bus-width = <8>; 886 supports-cqe; 887 888 qcom,dll-config = <0x0007642c>; 889 qcom,ddr-config = <0x80040868>; 890 891 mmc-ddr-1_8v; 892 mmc-hs200-1_8v; 893 mmc-hs400-1_8v; 894 mmc-hs400-enhanced-strobe; 895 896 resets = <&gcc GCC_SDCC1_BCR>; 897 898 sdhc1_opp_table: opp-table { 899 compatible = "operating-points-v2"; 900 901 opp-100000000 { 902 opp-hz = /bits/ 64 <100000000>; 903 required-opps = <&rpmhpd_opp_low_svs>; 904 opp-peak-kBps = <1800000 400000>; 905 opp-avg-kBps = <100000 0>; 906 }; 907 908 opp-384000000 { 909 opp-hz = /bits/ 64 <384000000>; 910 required-opps = <&rpmhpd_opp_nom>; 911 opp-peak-kBps = <5400000 1600000>; 912 opp-avg-kBps = <390000 0>; 913 }; 914 }; 915 916 }; 917 918 gpi_dma0: dma-controller@900000 { 919 #dma-cells = <3>; 920 compatible = "qcom,sc7280-gpi-dma"; 921 reg = <0 0x00900000 0 0x60000>; 922 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 934 dma-channels = <12>; 935 dma-channel-mask = <0x7f>; 936 iommus = <&apps_smmu 0x0136 0x0>; 937 status = "disabled"; 938 }; 939 940 qupv3_id_0: geniqup@9c0000 { 941 compatible = "qcom,geni-se-qup"; 942 reg = <0 0x009c0000 0 0x2000>; 943 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 944 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 945 clock-names = "m-ahb", "s-ahb"; 946 #address-cells = <2>; 947 #size-cells = <2>; 948 ranges; 949 iommus = <&apps_smmu 0x123 0x0>; 950 status = "disabled"; 951 952 i2c0: i2c@980000 { 953 compatible = "qcom,geni-i2c"; 954 reg = <0 0x00980000 0 0x4000>; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 956 clock-names = "se"; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&qup_i2c0_data_clk>; 959 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 963 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 964 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 965 interconnect-names = "qup-core", "qup-config", 966 "qup-memory"; 967 status = "disabled"; 968 }; 969 970 spi0: spi@980000 { 971 compatible = "qcom,geni-spi"; 972 reg = <0 0x00980000 0 0x4000>; 973 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 974 clock-names = "se"; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 977 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 power-domains = <&rpmhpd SC7280_CX>; 981 operating-points-v2 = <&qup_opp_table>; 982 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 983 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 984 interconnect-names = "qup-core", "qup-config"; 985 status = "disabled"; 986 }; 987 988 uart0: serial@980000 { 989 compatible = "qcom,geni-uart"; 990 reg = <0 0x00980000 0 0x4000>; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 992 clock-names = "se"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 995 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 996 power-domains = <&rpmhpd SC7280_CX>; 997 operating-points-v2 = <&qup_opp_table>; 998 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 999 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1000 interconnect-names = "qup-core", "qup-config"; 1001 status = "disabled"; 1002 }; 1003 1004 i2c1: i2c@984000 { 1005 compatible = "qcom,geni-i2c"; 1006 reg = <0 0x00984000 0 0x4000>; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1008 clock-names = "se"; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&qup_i2c1_data_clk>; 1011 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1015 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1016 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1017 interconnect-names = "qup-core", "qup-config", 1018 "qup-memory"; 1019 status = "disabled"; 1020 }; 1021 1022 spi1: spi@984000 { 1023 compatible = "qcom,geni-spi"; 1024 reg = <0 0x00984000 0 0x4000>; 1025 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1026 clock-names = "se"; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1029 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 power-domains = <&rpmhpd SC7280_CX>; 1033 operating-points-v2 = <&qup_opp_table>; 1034 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1036 interconnect-names = "qup-core", "qup-config"; 1037 status = "disabled"; 1038 }; 1039 1040 uart1: serial@984000 { 1041 compatible = "qcom,geni-uart"; 1042 reg = <0 0x00984000 0 0x4000>; 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1044 clock-names = "se"; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1047 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1048 power-domains = <&rpmhpd SC7280_CX>; 1049 operating-points-v2 = <&qup_opp_table>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1052 interconnect-names = "qup-core", "qup-config"; 1053 status = "disabled"; 1054 }; 1055 1056 i2c2: i2c@988000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x00988000 0 0x4000>; 1059 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1060 clock-names = "se"; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_i2c2_data_clk>; 1063 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1067 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1068 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", 1070 "qup-memory"; 1071 status = "disabled"; 1072 }; 1073 1074 spi2: spi@988000 { 1075 compatible = "qcom,geni-spi"; 1076 reg = <0 0x00988000 0 0x4000>; 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1078 clock-names = "se"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1081 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 power-domains = <&rpmhpd SC7280_CX>; 1085 operating-points-v2 = <&qup_opp_table>; 1086 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1087 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1088 interconnect-names = "qup-core", "qup-config"; 1089 status = "disabled"; 1090 }; 1091 1092 uart2: serial@988000 { 1093 compatible = "qcom,geni-uart"; 1094 reg = <0 0x00988000 0 0x4000>; 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1096 clock-names = "se"; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1099 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1100 power-domains = <&rpmhpd SC7280_CX>; 1101 operating-points-v2 = <&qup_opp_table>; 1102 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1103 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1104 interconnect-names = "qup-core", "qup-config"; 1105 status = "disabled"; 1106 }; 1107 1108 i2c3: i2c@98c000 { 1109 compatible = "qcom,geni-i2c"; 1110 reg = <0 0x0098c000 0 0x4000>; 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1112 clock-names = "se"; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_i2c3_data_clk>; 1115 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1119 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1120 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1121 interconnect-names = "qup-core", "qup-config", 1122 "qup-memory"; 1123 status = "disabled"; 1124 }; 1125 1126 spi3: spi@98c000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0 0x0098c000 0 0x4000>; 1129 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1130 clock-names = "se"; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1133 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 power-domains = <&rpmhpd SC7280_CX>; 1137 operating-points-v2 = <&qup_opp_table>; 1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1139 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1140 interconnect-names = "qup-core", "qup-config"; 1141 status = "disabled"; 1142 }; 1143 1144 uart3: serial@98c000 { 1145 compatible = "qcom,geni-uart"; 1146 reg = <0 0x0098c000 0 0x4000>; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1148 clock-names = "se"; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1151 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1152 power-domains = <&rpmhpd SC7280_CX>; 1153 operating-points-v2 = <&qup_opp_table>; 1154 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1155 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1156 interconnect-names = "qup-core", "qup-config"; 1157 status = "disabled"; 1158 }; 1159 1160 i2c4: i2c@990000 { 1161 compatible = "qcom,geni-i2c"; 1162 reg = <0 0x00990000 0 0x4000>; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1164 clock-names = "se"; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&qup_i2c4_data_clk>; 1167 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1172 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1173 interconnect-names = "qup-core", "qup-config", 1174 "qup-memory"; 1175 status = "disabled"; 1176 }; 1177 1178 spi4: spi@990000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0 0x00990000 0 0x4000>; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1182 clock-names = "se"; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1185 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 power-domains = <&rpmhpd SC7280_CX>; 1189 operating-points-v2 = <&qup_opp_table>; 1190 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1191 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1192 interconnect-names = "qup-core", "qup-config"; 1193 status = "disabled"; 1194 }; 1195 1196 uart4: serial@990000 { 1197 compatible = "qcom,geni-uart"; 1198 reg = <0 0x00990000 0 0x4000>; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1200 clock-names = "se"; 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1203 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1204 power-domains = <&rpmhpd SC7280_CX>; 1205 operating-points-v2 = <&qup_opp_table>; 1206 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1207 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1208 interconnect-names = "qup-core", "qup-config"; 1209 status = "disabled"; 1210 }; 1211 1212 i2c5: i2c@994000 { 1213 compatible = "qcom,geni-i2c"; 1214 reg = <0 0x00994000 0 0x4000>; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1216 clock-names = "se"; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_i2c5_data_clk>; 1219 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1223 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1224 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1225 interconnect-names = "qup-core", "qup-config", 1226 "qup-memory"; 1227 status = "disabled"; 1228 }; 1229 1230 spi5: spi@994000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0 0x00994000 0 0x4000>; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1234 clock-names = "se"; 1235 pinctrl-names = "default"; 1236 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1237 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 power-domains = <&rpmhpd SC7280_CX>; 1241 operating-points-v2 = <&qup_opp_table>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1244 interconnect-names = "qup-core", "qup-config"; 1245 status = "disabled"; 1246 }; 1247 1248 uart5: serial@994000 { 1249 compatible = "qcom,geni-uart"; 1250 reg = <0 0x00994000 0 0x4000>; 1251 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1252 clock-names = "se"; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1255 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1256 power-domains = <&rpmhpd SC7280_CX>; 1257 operating-points-v2 = <&qup_opp_table>; 1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1260 interconnect-names = "qup-core", "qup-config"; 1261 status = "disabled"; 1262 }; 1263 1264 i2c6: i2c@998000 { 1265 compatible = "qcom,geni-i2c"; 1266 reg = <0 0x00998000 0 0x4000>; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1268 clock-names = "se"; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_i2c6_data_clk>; 1271 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1275 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1276 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1277 interconnect-names = "qup-core", "qup-config", 1278 "qup-memory"; 1279 status = "disabled"; 1280 }; 1281 1282 spi6: spi@998000 { 1283 compatible = "qcom,geni-spi"; 1284 reg = <0 0x00998000 0 0x4000>; 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1286 clock-names = "se"; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1289 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 power-domains = <&rpmhpd SC7280_CX>; 1293 operating-points-v2 = <&qup_opp_table>; 1294 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1295 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1296 interconnect-names = "qup-core", "qup-config"; 1297 status = "disabled"; 1298 }; 1299 1300 uart6: serial@998000 { 1301 compatible = "qcom,geni-uart"; 1302 reg = <0 0x00998000 0 0x4000>; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1304 clock-names = "se"; 1305 pinctrl-names = "default"; 1306 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1307 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1308 power-domains = <&rpmhpd SC7280_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1311 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1312 interconnect-names = "qup-core", "qup-config"; 1313 status = "disabled"; 1314 }; 1315 1316 i2c7: i2c@99c000 { 1317 compatible = "qcom,geni-i2c"; 1318 reg = <0 0x0099c000 0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1320 clock-names = "se"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_i2c7_data_clk>; 1323 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1327 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1328 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1329 interconnect-names = "qup-core", "qup-config", 1330 "qup-memory"; 1331 status = "disabled"; 1332 }; 1333 1334 spi7: spi@99c000 { 1335 compatible = "qcom,geni-spi"; 1336 reg = <0 0x0099c000 0 0x4000>; 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1338 clock-names = "se"; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1341 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 power-domains = <&rpmhpd SC7280_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1348 interconnect-names = "qup-core", "qup-config"; 1349 status = "disabled"; 1350 }; 1351 1352 uart7: serial@99c000 { 1353 compatible = "qcom,geni-uart"; 1354 reg = <0 0x0099c000 0 0x4000>; 1355 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1356 clock-names = "se"; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1359 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1360 power-domains = <&rpmhpd SC7280_CX>; 1361 operating-points-v2 = <&qup_opp_table>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1364 interconnect-names = "qup-core", "qup-config"; 1365 status = "disabled"; 1366 }; 1367 }; 1368 1369 gpi_dma1: dma-controller@a00000 { 1370 #dma-cells = <3>; 1371 compatible = "qcom,sc7280-gpi-dma"; 1372 reg = <0 0x00a00000 0 0x60000>; 1373 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1385 dma-channels = <12>; 1386 dma-channel-mask = <0x1e>; 1387 iommus = <&apps_smmu 0x56 0x0>; 1388 status = "disabled"; 1389 }; 1390 1391 qupv3_id_1: geniqup@ac0000 { 1392 compatible = "qcom,geni-se-qup"; 1393 reg = <0 0x00ac0000 0 0x2000>; 1394 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1395 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1396 clock-names = "m-ahb", "s-ahb"; 1397 #address-cells = <2>; 1398 #size-cells = <2>; 1399 ranges; 1400 iommus = <&apps_smmu 0x43 0x0>; 1401 status = "disabled"; 1402 1403 i2c8: i2c@a80000 { 1404 compatible = "qcom,geni-i2c"; 1405 reg = <0 0x00a80000 0 0x4000>; 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1407 clock-names = "se"; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_i2c8_data_clk>; 1410 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1415 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1416 interconnect-names = "qup-core", "qup-config", 1417 "qup-memory"; 1418 status = "disabled"; 1419 }; 1420 1421 spi8: spi@a80000 { 1422 compatible = "qcom,geni-spi"; 1423 reg = <0 0x00a80000 0 0x4000>; 1424 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1425 clock-names = "se"; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1428 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 power-domains = <&rpmhpd SC7280_CX>; 1432 operating-points-v2 = <&qup_opp_table>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1435 interconnect-names = "qup-core", "qup-config"; 1436 status = "disabled"; 1437 }; 1438 1439 uart8: serial@a80000 { 1440 compatible = "qcom,geni-uart"; 1441 reg = <0 0x00a80000 0 0x4000>; 1442 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1443 clock-names = "se"; 1444 pinctrl-names = "default"; 1445 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1446 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1447 power-domains = <&rpmhpd SC7280_CX>; 1448 operating-points-v2 = <&qup_opp_table>; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1451 interconnect-names = "qup-core", "qup-config"; 1452 status = "disabled"; 1453 }; 1454 1455 i2c9: i2c@a84000 { 1456 compatible = "qcom,geni-i2c"; 1457 reg = <0 0x00a84000 0 0x4000>; 1458 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1459 clock-names = "se"; 1460 pinctrl-names = "default"; 1461 pinctrl-0 = <&qup_i2c9_data_clk>; 1462 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1466 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1467 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1468 interconnect-names = "qup-core", "qup-config", 1469 "qup-memory"; 1470 status = "disabled"; 1471 }; 1472 1473 spi9: spi@a84000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0x00a84000 0 0x4000>; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1477 clock-names = "se"; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1480 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 power-domains = <&rpmhpd SC7280_CX>; 1484 operating-points-v2 = <&qup_opp_table>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1487 interconnect-names = "qup-core", "qup-config"; 1488 status = "disabled"; 1489 }; 1490 1491 uart9: serial@a84000 { 1492 compatible = "qcom,geni-uart"; 1493 reg = <0 0x00a84000 0 0x4000>; 1494 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1495 clock-names = "se"; 1496 pinctrl-names = "default"; 1497 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1498 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1499 power-domains = <&rpmhpd SC7280_CX>; 1500 operating-points-v2 = <&qup_opp_table>; 1501 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1502 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1503 interconnect-names = "qup-core", "qup-config"; 1504 status = "disabled"; 1505 }; 1506 1507 i2c10: i2c@a88000 { 1508 compatible = "qcom,geni-i2c"; 1509 reg = <0 0x00a88000 0 0x4000>; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1511 clock-names = "se"; 1512 pinctrl-names = "default"; 1513 pinctrl-0 = <&qup_i2c10_data_clk>; 1514 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1518 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1519 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", 1521 "qup-memory"; 1522 status = "disabled"; 1523 }; 1524 1525 spi10: spi@a88000 { 1526 compatible = "qcom,geni-spi"; 1527 reg = <0 0x00a88000 0 0x4000>; 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1529 clock-names = "se"; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1532 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 power-domains = <&rpmhpd SC7280_CX>; 1536 operating-points-v2 = <&qup_opp_table>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1538 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1539 interconnect-names = "qup-core", "qup-config"; 1540 status = "disabled"; 1541 }; 1542 1543 uart10: serial@a88000 { 1544 compatible = "qcom,geni-uart"; 1545 reg = <0 0x00a88000 0 0x4000>; 1546 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1547 clock-names = "se"; 1548 pinctrl-names = "default"; 1549 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1550 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1551 power-domains = <&rpmhpd SC7280_CX>; 1552 operating-points-v2 = <&qup_opp_table>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1555 interconnect-names = "qup-core", "qup-config"; 1556 status = "disabled"; 1557 }; 1558 1559 i2c11: i2c@a8c000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00a8c000 0 0x4000>; 1562 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1563 clock-names = "se"; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_i2c11_data_clk>; 1566 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1570 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1571 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1572 interconnect-names = "qup-core", "qup-config", 1573 "qup-memory"; 1574 status = "disabled"; 1575 }; 1576 1577 spi11: spi@a8c000 { 1578 compatible = "qcom,geni-spi"; 1579 reg = <0 0x00a8c000 0 0x4000>; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1581 clock-names = "se"; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1584 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 power-domains = <&rpmhpd SC7280_CX>; 1588 operating-points-v2 = <&qup_opp_table>; 1589 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1590 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1591 interconnect-names = "qup-core", "qup-config"; 1592 status = "disabled"; 1593 }; 1594 1595 uart11: serial@a8c000 { 1596 compatible = "qcom,geni-uart"; 1597 reg = <0 0x00a8c000 0 0x4000>; 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1599 clock-names = "se"; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1603 power-domains = <&rpmhpd SC7280_CX>; 1604 operating-points-v2 = <&qup_opp_table>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1606 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1607 interconnect-names = "qup-core", "qup-config"; 1608 status = "disabled"; 1609 }; 1610 1611 i2c12: i2c@a90000 { 1612 compatible = "qcom,geni-i2c"; 1613 reg = <0 0x00a90000 0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1615 clock-names = "se"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_i2c12_data_clk>; 1618 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1623 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1624 interconnect-names = "qup-core", "qup-config", 1625 "qup-memory"; 1626 status = "disabled"; 1627 }; 1628 1629 spi12: spi@a90000 { 1630 compatible = "qcom,geni-spi"; 1631 reg = <0 0x00a90000 0 0x4000>; 1632 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1633 clock-names = "se"; 1634 pinctrl-names = "default"; 1635 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1636 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 power-domains = <&rpmhpd SC7280_CX>; 1640 operating-points-v2 = <&qup_opp_table>; 1641 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1642 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1643 interconnect-names = "qup-core", "qup-config"; 1644 status = "disabled"; 1645 }; 1646 1647 uart12: serial@a90000 { 1648 compatible = "qcom,geni-uart"; 1649 reg = <0 0x00a90000 0 0x4000>; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1651 clock-names = "se"; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1654 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1655 power-domains = <&rpmhpd SC7280_CX>; 1656 operating-points-v2 = <&qup_opp_table>; 1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1658 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1659 interconnect-names = "qup-core", "qup-config"; 1660 status = "disabled"; 1661 }; 1662 1663 i2c13: i2c@a94000 { 1664 compatible = "qcom,geni-i2c"; 1665 reg = <0 0x00a94000 0 0x4000>; 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1667 clock-names = "se"; 1668 pinctrl-names = "default"; 1669 pinctrl-0 = <&qup_i2c13_data_clk>; 1670 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1674 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1675 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1676 interconnect-names = "qup-core", "qup-config", 1677 "qup-memory"; 1678 status = "disabled"; 1679 }; 1680 1681 spi13: spi@a94000 { 1682 compatible = "qcom,geni-spi"; 1683 reg = <0 0x00a94000 0 0x4000>; 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1685 clock-names = "se"; 1686 pinctrl-names = "default"; 1687 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1688 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 power-domains = <&rpmhpd SC7280_CX>; 1692 operating-points-v2 = <&qup_opp_table>; 1693 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1694 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1695 interconnect-names = "qup-core", "qup-config"; 1696 status = "disabled"; 1697 }; 1698 1699 uart13: serial@a94000 { 1700 compatible = "qcom,geni-uart"; 1701 reg = <0 0x00a94000 0 0x4000>; 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1703 clock-names = "se"; 1704 pinctrl-names = "default"; 1705 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1706 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1707 power-domains = <&rpmhpd SC7280_CX>; 1708 operating-points-v2 = <&qup_opp_table>; 1709 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1710 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1711 interconnect-names = "qup-core", "qup-config"; 1712 status = "disabled"; 1713 }; 1714 1715 i2c14: i2c@a98000 { 1716 compatible = "qcom,geni-i2c"; 1717 reg = <0 0x00a98000 0 0x4000>; 1718 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1719 clock-names = "se"; 1720 pinctrl-names = "default"; 1721 pinctrl-0 = <&qup_i2c14_data_clk>; 1722 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1726 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1727 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1728 interconnect-names = "qup-core", "qup-config", 1729 "qup-memory"; 1730 status = "disabled"; 1731 }; 1732 1733 spi14: spi@a98000 { 1734 compatible = "qcom,geni-spi"; 1735 reg = <0 0x00a98000 0 0x4000>; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1737 clock-names = "se"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1740 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 power-domains = <&rpmhpd SC7280_CX>; 1744 operating-points-v2 = <&qup_opp_table>; 1745 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1746 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1747 interconnect-names = "qup-core", "qup-config"; 1748 status = "disabled"; 1749 }; 1750 1751 uart14: serial@a98000 { 1752 compatible = "qcom,geni-uart"; 1753 reg = <0 0x00a98000 0 0x4000>; 1754 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1755 clock-names = "se"; 1756 pinctrl-names = "default"; 1757 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1758 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1759 power-domains = <&rpmhpd SC7280_CX>; 1760 operating-points-v2 = <&qup_opp_table>; 1761 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1762 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1763 interconnect-names = "qup-core", "qup-config"; 1764 status = "disabled"; 1765 }; 1766 1767 i2c15: i2c@a9c000 { 1768 compatible = "qcom,geni-i2c"; 1769 reg = <0 0x00a9c000 0 0x4000>; 1770 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1771 clock-names = "se"; 1772 pinctrl-names = "default"; 1773 pinctrl-0 = <&qup_i2c15_data_clk>; 1774 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1778 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1779 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1780 interconnect-names = "qup-core", "qup-config", 1781 "qup-memory"; 1782 status = "disabled"; 1783 }; 1784 1785 spi15: spi@a9c000 { 1786 compatible = "qcom,geni-spi"; 1787 reg = <0 0x00a9c000 0 0x4000>; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1789 clock-names = "se"; 1790 pinctrl-names = "default"; 1791 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1792 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 power-domains = <&rpmhpd SC7280_CX>; 1796 operating-points-v2 = <&qup_opp_table>; 1797 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1798 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1799 interconnect-names = "qup-core", "qup-config"; 1800 status = "disabled"; 1801 }; 1802 1803 uart15: serial@a9c000 { 1804 compatible = "qcom,geni-uart"; 1805 reg = <0 0x00a9c000 0 0x4000>; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1807 clock-names = "se"; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1810 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1811 power-domains = <&rpmhpd SC7280_CX>; 1812 operating-points-v2 = <&qup_opp_table>; 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1814 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1815 interconnect-names = "qup-core", "qup-config"; 1816 status = "disabled"; 1817 }; 1818 }; 1819 1820 cnoc2: interconnect@1500000 { 1821 reg = <0 0x01500000 0 0x1000>; 1822 compatible = "qcom,sc7280-cnoc2"; 1823 #interconnect-cells = <2>; 1824 qcom,bcm-voters = <&apps_bcm_voter>; 1825 }; 1826 1827 cnoc3: interconnect@1502000 { 1828 reg = <0 0x01502000 0 0x1000>; 1829 compatible = "qcom,sc7280-cnoc3"; 1830 #interconnect-cells = <2>; 1831 qcom,bcm-voters = <&apps_bcm_voter>; 1832 }; 1833 1834 mc_virt: interconnect@1580000 { 1835 reg = <0 0x01580000 0 0x4>; 1836 compatible = "qcom,sc7280-mc-virt"; 1837 #interconnect-cells = <2>; 1838 qcom,bcm-voters = <&apps_bcm_voter>; 1839 }; 1840 1841 system_noc: interconnect@1680000 { 1842 reg = <0 0x01680000 0 0x15480>; 1843 compatible = "qcom,sc7280-system-noc"; 1844 #interconnect-cells = <2>; 1845 qcom,bcm-voters = <&apps_bcm_voter>; 1846 }; 1847 1848 aggre1_noc: interconnect@16e0000 { 1849 compatible = "qcom,sc7280-aggre1-noc"; 1850 reg = <0 0x016e0000 0 0x1c080>; 1851 #interconnect-cells = <2>; 1852 qcom,bcm-voters = <&apps_bcm_voter>; 1853 }; 1854 1855 aggre2_noc: interconnect@1700000 { 1856 reg = <0 0x01700000 0 0x2b080>; 1857 compatible = "qcom,sc7280-aggre2-noc"; 1858 #interconnect-cells = <2>; 1859 qcom,bcm-voters = <&apps_bcm_voter>; 1860 }; 1861 1862 mmss_noc: interconnect@1740000 { 1863 reg = <0 0x01740000 0 0x1e080>; 1864 compatible = "qcom,sc7280-mmss-noc"; 1865 #interconnect-cells = <2>; 1866 qcom,bcm-voters = <&apps_bcm_voter>; 1867 }; 1868 1869 wifi: wifi@17a10040 { 1870 compatible = "qcom,wcn6750-wifi"; 1871 reg = <0 0x17a10040 0 0x0>; 1872 iommus = <&apps_smmu 0x1c00 0x1>; 1873 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1874 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1875 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1876 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1877 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1878 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1879 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1880 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1881 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1882 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1883 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1884 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1885 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1886 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1887 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1888 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1889 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1890 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1891 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1892 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1893 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1894 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1895 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1896 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1897 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1898 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1899 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1900 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1901 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1902 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 1903 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 1904 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 1905 qcom,rproc = <&remoteproc_wpss>; 1906 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 1907 status = "disabled"; 1908 }; 1909 1910 pcie1: pci@1c08000 { 1911 compatible = "qcom,pcie-sc7280"; 1912 reg = <0 0x01c08000 0 0x3000>, 1913 <0 0x40000000 0 0xf1d>, 1914 <0 0x40000f20 0 0xa8>, 1915 <0 0x40001000 0 0x1000>, 1916 <0 0x40100000 0 0x100000>; 1917 1918 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1919 device_type = "pci"; 1920 linux,pci-domain = <1>; 1921 bus-range = <0x00 0xff>; 1922 num-lanes = <2>; 1923 1924 #address-cells = <3>; 1925 #size-cells = <2>; 1926 1927 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1928 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1929 1930 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1931 interrupt-names = "msi"; 1932 #interrupt-cells = <1>; 1933 interrupt-map-mask = <0 0 0 0x7>; 1934 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1935 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1936 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1937 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1938 1939 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1940 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1941 <&pcie1_lane 0>, 1942 <&rpmhcc RPMH_CXO_CLK>, 1943 <&gcc GCC_PCIE_1_AUX_CLK>, 1944 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1945 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1946 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1947 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1948 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1949 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1950 1951 clock-names = "pipe", 1952 "pipe_mux", 1953 "phy_pipe", 1954 "ref", 1955 "aux", 1956 "cfg", 1957 "bus_master", 1958 "bus_slave", 1959 "slave_q2a", 1960 "tbu", 1961 "ddrss_sf_tbu"; 1962 1963 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1964 assigned-clock-rates = <19200000>; 1965 1966 resets = <&gcc GCC_PCIE_1_BCR>; 1967 reset-names = "pci"; 1968 1969 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1970 1971 phys = <&pcie1_lane>; 1972 phy-names = "pciephy"; 1973 1974 pinctrl-names = "default"; 1975 pinctrl-0 = <&pcie1_clkreq_n>; 1976 1977 iommus = <&apps_smmu 0x1c80 0x1>; 1978 1979 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1980 <0x100 &apps_smmu 0x1c81 0x1>; 1981 1982 status = "disabled"; 1983 }; 1984 1985 pcie1_phy: phy@1c0e000 { 1986 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1987 reg = <0 0x01c0e000 0 0x1c0>; 1988 #address-cells = <2>; 1989 #size-cells = <2>; 1990 ranges; 1991 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1992 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1993 <&gcc GCC_PCIE_CLKREF_EN>, 1994 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1995 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1996 1997 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1998 reset-names = "phy"; 1999 2000 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2001 assigned-clock-rates = <100000000>; 2002 2003 status = "disabled"; 2004 2005 pcie1_lane: phy@1c0e200 { 2006 reg = <0 0x01c0e200 0 0x170>, 2007 <0 0x01c0e400 0 0x200>, 2008 <0 0x01c0ea00 0 0x1f0>, 2009 <0 0x01c0e600 0 0x170>, 2010 <0 0x01c0e800 0 0x200>, 2011 <0 0x01c0ee00 0 0xf4>; 2012 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2013 clock-names = "pipe0"; 2014 2015 #phy-cells = <0>; 2016 #clock-cells = <1>; 2017 clock-output-names = "pcie_1_pipe_clk"; 2018 }; 2019 }; 2020 2021 ipa: ipa@1e40000 { 2022 compatible = "qcom,sc7280-ipa"; 2023 2024 iommus = <&apps_smmu 0x480 0x0>, 2025 <&apps_smmu 0x482 0x0>; 2026 reg = <0 0x1e40000 0 0x8000>, 2027 <0 0x1e50000 0 0x4ad0>, 2028 <0 0x1e04000 0 0x23000>; 2029 reg-names = "ipa-reg", 2030 "ipa-shared", 2031 "gsi"; 2032 2033 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2034 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2035 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2036 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2037 interrupt-names = "ipa", 2038 "gsi", 2039 "ipa-clock-query", 2040 "ipa-setup-ready"; 2041 2042 clocks = <&rpmhcc RPMH_IPA_CLK>; 2043 clock-names = "core"; 2044 2045 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2047 interconnect-names = "memory", 2048 "config"; 2049 2050 qcom,qmp = <&aoss_qmp>; 2051 2052 qcom,smem-states = <&ipa_smp2p_out 0>, 2053 <&ipa_smp2p_out 1>; 2054 qcom,smem-state-names = "ipa-clock-enabled-valid", 2055 "ipa-clock-enabled"; 2056 2057 status = "disabled"; 2058 }; 2059 2060 tcsr_mutex: hwlock@1f40000 { 2061 compatible = "qcom,tcsr-mutex", "syscon"; 2062 reg = <0 0x01f40000 0 0x40000>; 2063 #hwlock-cells = <1>; 2064 }; 2065 2066 tcsr: syscon@1fc0000 { 2067 compatible = "qcom,sc7280-tcsr", "syscon"; 2068 reg = <0 0x01fc0000 0 0x30000>; 2069 }; 2070 2071 lpasscc: lpasscc@3000000 { 2072 compatible = "qcom,sc7280-lpasscc"; 2073 reg = <0 0x03000000 0 0x40>, 2074 <0 0x03c04000 0 0x4>, 2075 <0 0x03389000 0 0x24>; 2076 reg-names = "qdsp6ss", "top_cc", "cc"; 2077 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2078 clock-names = "iface"; 2079 #clock-cells = <1>; 2080 }; 2081 2082 lpass_audiocc: clock-controller@3300000 { 2083 compatible = "qcom,sc7280-lpassaudiocc"; 2084 reg = <0 0x03300000 0 0x30000>; 2085 clocks = <&rpmhcc RPMH_CXO_CLK>, 2086 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2087 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2088 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2089 #clock-cells = <1>; 2090 #power-domain-cells = <1>; 2091 }; 2092 2093 lpass_aon: clock-controller@3380000 { 2094 compatible = "qcom,sc7280-lpassaoncc"; 2095 reg = <0 0x03380000 0 0x30000>; 2096 clocks = <&rpmhcc RPMH_CXO_CLK>, 2097 <&rpmhcc RPMH_CXO_CLK_A>, 2098 <&lpasscore LPASS_CORE_CC_CORE_CLK>; 2099 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2100 #clock-cells = <1>; 2101 #power-domain-cells = <1>; 2102 }; 2103 2104 lpasscore: clock-controller@3900000 { 2105 compatible = "qcom,sc7280-lpasscorecc"; 2106 reg = <0 0x03900000 0 0x50000>; 2107 clocks = <&rpmhcc RPMH_CXO_CLK>; 2108 clock-names = "bi_tcxo"; 2109 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2110 #clock-cells = <1>; 2111 #power-domain-cells = <1>; 2112 }; 2113 2114 lpass_hm: clock-controller@3c00000 { 2115 compatible = "qcom,sc7280-lpasshm"; 2116 reg = <0 0x3c00000 0 0x28>; 2117 clocks = <&rpmhcc RPMH_CXO_CLK>; 2118 clock-names = "bi_tcxo"; 2119 #clock-cells = <1>; 2120 #power-domain-cells = <1>; 2121 }; 2122 2123 lpass_ag_noc: interconnect@3c40000 { 2124 reg = <0 0x03c40000 0 0xf080>; 2125 compatible = "qcom,sc7280-lpass-ag-noc"; 2126 #interconnect-cells = <2>; 2127 qcom,bcm-voters = <&apps_bcm_voter>; 2128 }; 2129 2130 gpu: gpu@3d00000 { 2131 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2132 reg = <0 0x03d00000 0 0x40000>, 2133 <0 0x03d9e000 0 0x1000>, 2134 <0 0x03d61000 0 0x800>; 2135 reg-names = "kgsl_3d0_reg_memory", 2136 "cx_mem", 2137 "cx_dbgc"; 2138 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2139 iommus = <&adreno_smmu 0 0x401>; 2140 operating-points-v2 = <&gpu_opp_table>; 2141 qcom,gmu = <&gmu>; 2142 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2143 interconnect-names = "gfx-mem"; 2144 #cooling-cells = <2>; 2145 2146 nvmem-cells = <&gpu_speed_bin>; 2147 nvmem-cell-names = "speed_bin"; 2148 2149 gpu_opp_table: opp-table { 2150 compatible = "operating-points-v2"; 2151 2152 opp-315000000 { 2153 opp-hz = /bits/ 64 <315000000>; 2154 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2155 opp-peak-kBps = <1804000>; 2156 opp-supported-hw = <0x03>; 2157 }; 2158 2159 opp-450000000 { 2160 opp-hz = /bits/ 64 <450000000>; 2161 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2162 opp-peak-kBps = <4068000>; 2163 opp-supported-hw = <0x03>; 2164 }; 2165 2166 opp-550000000 { 2167 opp-hz = /bits/ 64 <550000000>; 2168 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2169 opp-peak-kBps = <6832000>; 2170 opp-supported-hw = <0x03>; 2171 }; 2172 2173 opp-608000000 { 2174 opp-hz = /bits/ 64 <608000000>; 2175 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2176 opp-peak-kBps = <8368000>; 2177 opp-supported-hw = <0x02>; 2178 }; 2179 2180 opp-700000000 { 2181 opp-hz = /bits/ 64 <700000000>; 2182 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2183 opp-peak-kBps = <8532000>; 2184 opp-supported-hw = <0x02>; 2185 }; 2186 2187 opp-812000000 { 2188 opp-hz = /bits/ 64 <812000000>; 2189 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2190 opp-peak-kBps = <8532000>; 2191 opp-supported-hw = <0x02>; 2192 }; 2193 2194 opp-840000000 { 2195 opp-hz = /bits/ 64 <840000000>; 2196 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2197 opp-peak-kBps = <8532000>; 2198 opp-supported-hw = <0x02>; 2199 }; 2200 2201 opp-900000000 { 2202 opp-hz = /bits/ 64 <900000000>; 2203 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2204 opp-peak-kBps = <8532000>; 2205 opp-supported-hw = <0x02>; 2206 }; 2207 }; 2208 }; 2209 2210 gmu: gmu@3d6a000 { 2211 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2212 reg = <0 0x03d6a000 0 0x34000>, 2213 <0 0x3de0000 0 0x10000>, 2214 <0 0x0b290000 0 0x10000>; 2215 reg-names = "gmu", "rscc", "gmu_pdc"; 2216 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2218 interrupt-names = "hfi", "gmu"; 2219 clocks = <&gpucc 5>, 2220 <&gpucc 8>, 2221 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2222 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2223 <&gpucc 2>, 2224 <&gpucc 15>, 2225 <&gpucc 11>; 2226 clock-names = "gmu", 2227 "cxo", 2228 "axi", 2229 "memnoc", 2230 "ahb", 2231 "hub", 2232 "smmu_vote"; 2233 power-domains = <&gpucc 0>, 2234 <&gpucc 1>; 2235 power-domain-names = "cx", 2236 "gx"; 2237 iommus = <&adreno_smmu 5 0x400>; 2238 operating-points-v2 = <&gmu_opp_table>; 2239 2240 gmu_opp_table: opp-table { 2241 compatible = "operating-points-v2"; 2242 2243 opp-200000000 { 2244 opp-hz = /bits/ 64 <200000000>; 2245 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2246 }; 2247 }; 2248 }; 2249 2250 gpucc: clock-controller@3d90000 { 2251 compatible = "qcom,sc7280-gpucc"; 2252 reg = <0 0x03d90000 0 0x9000>; 2253 clocks = <&rpmhcc RPMH_CXO_CLK>, 2254 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2255 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2256 clock-names = "bi_tcxo", 2257 "gcc_gpu_gpll0_clk_src", 2258 "gcc_gpu_gpll0_div_clk_src"; 2259 #clock-cells = <1>; 2260 #reset-cells = <1>; 2261 #power-domain-cells = <1>; 2262 }; 2263 2264 adreno_smmu: iommu@3da0000 { 2265 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2266 reg = <0 0x03da0000 0 0x20000>; 2267 #iommu-cells = <2>; 2268 #global-interrupts = <2>; 2269 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2275 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2277 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2278 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2279 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2281 2282 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2283 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2284 <&gpucc 2>, 2285 <&gpucc 11>, 2286 <&gpucc 5>, 2287 <&gpucc 15>, 2288 <&gpucc 13>; 2289 clock-names = "gcc_gpu_memnoc_gfx_clk", 2290 "gcc_gpu_snoc_dvm_gfx_clk", 2291 "gpu_cc_ahb_clk", 2292 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2293 "gpu_cc_cx_gmu_clk", 2294 "gpu_cc_hub_cx_int_clk", 2295 "gpu_cc_hub_aon_clk"; 2296 2297 power-domains = <&gpucc 0>; 2298 }; 2299 2300 remoteproc_mpss: remoteproc@4080000 { 2301 compatible = "qcom,sc7280-mpss-pas"; 2302 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2303 reg-names = "qdsp6", "rmb"; 2304 2305 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2306 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2307 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2308 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2309 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2310 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2311 interrupt-names = "wdog", "fatal", "ready", "handover", 2312 "stop-ack", "shutdown-ack"; 2313 2314 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2315 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2316 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2317 <&rpmhcc RPMH_PKA_CLK>, 2318 <&rpmhcc RPMH_CXO_CLK>; 2319 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2320 2321 power-domains = <&rpmhpd SC7280_CX>, 2322 <&rpmhpd SC7280_MSS>; 2323 power-domain-names = "cx", "mss"; 2324 2325 memory-region = <&mpss_mem>; 2326 2327 qcom,qmp = <&aoss_qmp>; 2328 2329 qcom,smem-states = <&modem_smp2p_out 0>; 2330 qcom,smem-state-names = "stop"; 2331 2332 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2333 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2334 reset-names = "mss_restart", "pdc_reset"; 2335 2336 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 2337 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 2338 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 2339 2340 status = "disabled"; 2341 2342 glink-edge { 2343 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2344 IPCC_MPROC_SIGNAL_GLINK_QMP 2345 IRQ_TYPE_EDGE_RISING>; 2346 mboxes = <&ipcc IPCC_CLIENT_MPSS 2347 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2348 label = "modem"; 2349 qcom,remote-pid = <1>; 2350 }; 2351 }; 2352 2353 stm@6002000 { 2354 compatible = "arm,coresight-stm", "arm,primecell"; 2355 reg = <0 0x06002000 0 0x1000>, 2356 <0 0x16280000 0 0x180000>; 2357 reg-names = "stm-base", "stm-stimulus-base"; 2358 2359 clocks = <&aoss_qmp>; 2360 clock-names = "apb_pclk"; 2361 2362 out-ports { 2363 port { 2364 stm_out: endpoint { 2365 remote-endpoint = <&funnel0_in7>; 2366 }; 2367 }; 2368 }; 2369 }; 2370 2371 funnel@6041000 { 2372 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2373 reg = <0 0x06041000 0 0x1000>; 2374 2375 clocks = <&aoss_qmp>; 2376 clock-names = "apb_pclk"; 2377 2378 out-ports { 2379 port { 2380 funnel0_out: endpoint { 2381 remote-endpoint = <&merge_funnel_in0>; 2382 }; 2383 }; 2384 }; 2385 2386 in-ports { 2387 #address-cells = <1>; 2388 #size-cells = <0>; 2389 2390 port@7 { 2391 reg = <7>; 2392 funnel0_in7: endpoint { 2393 remote-endpoint = <&stm_out>; 2394 }; 2395 }; 2396 }; 2397 }; 2398 2399 funnel@6042000 { 2400 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2401 reg = <0 0x06042000 0 0x1000>; 2402 2403 clocks = <&aoss_qmp>; 2404 clock-names = "apb_pclk"; 2405 2406 out-ports { 2407 port { 2408 funnel1_out: endpoint { 2409 remote-endpoint = <&merge_funnel_in1>; 2410 }; 2411 }; 2412 }; 2413 2414 in-ports { 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 2418 port@4 { 2419 reg = <4>; 2420 funnel1_in4: endpoint { 2421 remote-endpoint = <&apss_merge_funnel_out>; 2422 }; 2423 }; 2424 }; 2425 }; 2426 2427 funnel@6045000 { 2428 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2429 reg = <0 0x06045000 0 0x1000>; 2430 2431 clocks = <&aoss_qmp>; 2432 clock-names = "apb_pclk"; 2433 2434 out-ports { 2435 port { 2436 merge_funnel_out: endpoint { 2437 remote-endpoint = <&swao_funnel_in>; 2438 }; 2439 }; 2440 }; 2441 2442 in-ports { 2443 #address-cells = <1>; 2444 #size-cells = <0>; 2445 2446 port@0 { 2447 reg = <0>; 2448 merge_funnel_in0: endpoint { 2449 remote-endpoint = <&funnel0_out>; 2450 }; 2451 }; 2452 2453 port@1 { 2454 reg = <1>; 2455 merge_funnel_in1: endpoint { 2456 remote-endpoint = <&funnel1_out>; 2457 }; 2458 }; 2459 }; 2460 }; 2461 2462 replicator@6046000 { 2463 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2464 reg = <0 0x06046000 0 0x1000>; 2465 2466 clocks = <&aoss_qmp>; 2467 clock-names = "apb_pclk"; 2468 2469 out-ports { 2470 port { 2471 replicator_out: endpoint { 2472 remote-endpoint = <&etr_in>; 2473 }; 2474 }; 2475 }; 2476 2477 in-ports { 2478 port { 2479 replicator_in: endpoint { 2480 remote-endpoint = <&swao_replicator_out>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 etr@6048000 { 2487 compatible = "arm,coresight-tmc", "arm,primecell"; 2488 reg = <0 0x06048000 0 0x1000>; 2489 iommus = <&apps_smmu 0x04c0 0>; 2490 2491 clocks = <&aoss_qmp>; 2492 clock-names = "apb_pclk"; 2493 arm,scatter-gather; 2494 2495 in-ports { 2496 port { 2497 etr_in: endpoint { 2498 remote-endpoint = <&replicator_out>; 2499 }; 2500 }; 2501 }; 2502 }; 2503 2504 funnel@6b04000 { 2505 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2506 reg = <0 0x06b04000 0 0x1000>; 2507 2508 clocks = <&aoss_qmp>; 2509 clock-names = "apb_pclk"; 2510 2511 out-ports { 2512 port { 2513 swao_funnel_out: endpoint { 2514 remote-endpoint = <&etf_in>; 2515 }; 2516 }; 2517 }; 2518 2519 in-ports { 2520 #address-cells = <1>; 2521 #size-cells = <0>; 2522 2523 port@7 { 2524 reg = <7>; 2525 swao_funnel_in: endpoint { 2526 remote-endpoint = <&merge_funnel_out>; 2527 }; 2528 }; 2529 }; 2530 }; 2531 2532 etf@6b05000 { 2533 compatible = "arm,coresight-tmc", "arm,primecell"; 2534 reg = <0 0x06b05000 0 0x1000>; 2535 2536 clocks = <&aoss_qmp>; 2537 clock-names = "apb_pclk"; 2538 2539 out-ports { 2540 port { 2541 etf_out: endpoint { 2542 remote-endpoint = <&swao_replicator_in>; 2543 }; 2544 }; 2545 }; 2546 2547 in-ports { 2548 port { 2549 etf_in: endpoint { 2550 remote-endpoint = <&swao_funnel_out>; 2551 }; 2552 }; 2553 }; 2554 }; 2555 2556 replicator@6b06000 { 2557 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2558 reg = <0 0x06b06000 0 0x1000>; 2559 2560 clocks = <&aoss_qmp>; 2561 clock-names = "apb_pclk"; 2562 qcom,replicator-loses-context; 2563 2564 out-ports { 2565 port { 2566 swao_replicator_out: endpoint { 2567 remote-endpoint = <&replicator_in>; 2568 }; 2569 }; 2570 }; 2571 2572 in-ports { 2573 port { 2574 swao_replicator_in: endpoint { 2575 remote-endpoint = <&etf_out>; 2576 }; 2577 }; 2578 }; 2579 }; 2580 2581 etm@7040000 { 2582 compatible = "arm,coresight-etm4x", "arm,primecell"; 2583 reg = <0 0x07040000 0 0x1000>; 2584 2585 cpu = <&CPU0>; 2586 2587 clocks = <&aoss_qmp>; 2588 clock-names = "apb_pclk"; 2589 arm,coresight-loses-context-with-cpu; 2590 qcom,skip-power-up; 2591 2592 out-ports { 2593 port { 2594 etm0_out: endpoint { 2595 remote-endpoint = <&apss_funnel_in0>; 2596 }; 2597 }; 2598 }; 2599 }; 2600 2601 etm@7140000 { 2602 compatible = "arm,coresight-etm4x", "arm,primecell"; 2603 reg = <0 0x07140000 0 0x1000>; 2604 2605 cpu = <&CPU1>; 2606 2607 clocks = <&aoss_qmp>; 2608 clock-names = "apb_pclk"; 2609 arm,coresight-loses-context-with-cpu; 2610 qcom,skip-power-up; 2611 2612 out-ports { 2613 port { 2614 etm1_out: endpoint { 2615 remote-endpoint = <&apss_funnel_in1>; 2616 }; 2617 }; 2618 }; 2619 }; 2620 2621 etm@7240000 { 2622 compatible = "arm,coresight-etm4x", "arm,primecell"; 2623 reg = <0 0x07240000 0 0x1000>; 2624 2625 cpu = <&CPU2>; 2626 2627 clocks = <&aoss_qmp>; 2628 clock-names = "apb_pclk"; 2629 arm,coresight-loses-context-with-cpu; 2630 qcom,skip-power-up; 2631 2632 out-ports { 2633 port { 2634 etm2_out: endpoint { 2635 remote-endpoint = <&apss_funnel_in2>; 2636 }; 2637 }; 2638 }; 2639 }; 2640 2641 etm@7340000 { 2642 compatible = "arm,coresight-etm4x", "arm,primecell"; 2643 reg = <0 0x07340000 0 0x1000>; 2644 2645 cpu = <&CPU3>; 2646 2647 clocks = <&aoss_qmp>; 2648 clock-names = "apb_pclk"; 2649 arm,coresight-loses-context-with-cpu; 2650 qcom,skip-power-up; 2651 2652 out-ports { 2653 port { 2654 etm3_out: endpoint { 2655 remote-endpoint = <&apss_funnel_in3>; 2656 }; 2657 }; 2658 }; 2659 }; 2660 2661 etm@7440000 { 2662 compatible = "arm,coresight-etm4x", "arm,primecell"; 2663 reg = <0 0x07440000 0 0x1000>; 2664 2665 cpu = <&CPU4>; 2666 2667 clocks = <&aoss_qmp>; 2668 clock-names = "apb_pclk"; 2669 arm,coresight-loses-context-with-cpu; 2670 qcom,skip-power-up; 2671 2672 out-ports { 2673 port { 2674 etm4_out: endpoint { 2675 remote-endpoint = <&apss_funnel_in4>; 2676 }; 2677 }; 2678 }; 2679 }; 2680 2681 etm@7540000 { 2682 compatible = "arm,coresight-etm4x", "arm,primecell"; 2683 reg = <0 0x07540000 0 0x1000>; 2684 2685 cpu = <&CPU5>; 2686 2687 clocks = <&aoss_qmp>; 2688 clock-names = "apb_pclk"; 2689 arm,coresight-loses-context-with-cpu; 2690 qcom,skip-power-up; 2691 2692 out-ports { 2693 port { 2694 etm5_out: endpoint { 2695 remote-endpoint = <&apss_funnel_in5>; 2696 }; 2697 }; 2698 }; 2699 }; 2700 2701 etm@7640000 { 2702 compatible = "arm,coresight-etm4x", "arm,primecell"; 2703 reg = <0 0x07640000 0 0x1000>; 2704 2705 cpu = <&CPU6>; 2706 2707 clocks = <&aoss_qmp>; 2708 clock-names = "apb_pclk"; 2709 arm,coresight-loses-context-with-cpu; 2710 qcom,skip-power-up; 2711 2712 out-ports { 2713 port { 2714 etm6_out: endpoint { 2715 remote-endpoint = <&apss_funnel_in6>; 2716 }; 2717 }; 2718 }; 2719 }; 2720 2721 etm@7740000 { 2722 compatible = "arm,coresight-etm4x", "arm,primecell"; 2723 reg = <0 0x07740000 0 0x1000>; 2724 2725 cpu = <&CPU7>; 2726 2727 clocks = <&aoss_qmp>; 2728 clock-names = "apb_pclk"; 2729 arm,coresight-loses-context-with-cpu; 2730 qcom,skip-power-up; 2731 2732 out-ports { 2733 port { 2734 etm7_out: endpoint { 2735 remote-endpoint = <&apss_funnel_in7>; 2736 }; 2737 }; 2738 }; 2739 }; 2740 2741 funnel@7800000 { /* APSS Funnel */ 2742 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2743 reg = <0 0x07800000 0 0x1000>; 2744 2745 clocks = <&aoss_qmp>; 2746 clock-names = "apb_pclk"; 2747 2748 out-ports { 2749 port { 2750 apss_funnel_out: endpoint { 2751 remote-endpoint = <&apss_merge_funnel_in>; 2752 }; 2753 }; 2754 }; 2755 2756 in-ports { 2757 #address-cells = <1>; 2758 #size-cells = <0>; 2759 2760 port@0 { 2761 reg = <0>; 2762 apss_funnel_in0: endpoint { 2763 remote-endpoint = <&etm0_out>; 2764 }; 2765 }; 2766 2767 port@1 { 2768 reg = <1>; 2769 apss_funnel_in1: endpoint { 2770 remote-endpoint = <&etm1_out>; 2771 }; 2772 }; 2773 2774 port@2 { 2775 reg = <2>; 2776 apss_funnel_in2: endpoint { 2777 remote-endpoint = <&etm2_out>; 2778 }; 2779 }; 2780 2781 port@3 { 2782 reg = <3>; 2783 apss_funnel_in3: endpoint { 2784 remote-endpoint = <&etm3_out>; 2785 }; 2786 }; 2787 2788 port@4 { 2789 reg = <4>; 2790 apss_funnel_in4: endpoint { 2791 remote-endpoint = <&etm4_out>; 2792 }; 2793 }; 2794 2795 port@5 { 2796 reg = <5>; 2797 apss_funnel_in5: endpoint { 2798 remote-endpoint = <&etm5_out>; 2799 }; 2800 }; 2801 2802 port@6 { 2803 reg = <6>; 2804 apss_funnel_in6: endpoint { 2805 remote-endpoint = <&etm6_out>; 2806 }; 2807 }; 2808 2809 port@7 { 2810 reg = <7>; 2811 apss_funnel_in7: endpoint { 2812 remote-endpoint = <&etm7_out>; 2813 }; 2814 }; 2815 }; 2816 }; 2817 2818 funnel@7810000 { 2819 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2820 reg = <0 0x07810000 0 0x1000>; 2821 2822 clocks = <&aoss_qmp>; 2823 clock-names = "apb_pclk"; 2824 2825 out-ports { 2826 port { 2827 apss_merge_funnel_out: endpoint { 2828 remote-endpoint = <&funnel1_in4>; 2829 }; 2830 }; 2831 }; 2832 2833 in-ports { 2834 port { 2835 apss_merge_funnel_in: endpoint { 2836 remote-endpoint = <&apss_funnel_out>; 2837 }; 2838 }; 2839 }; 2840 }; 2841 2842 sdhc_2: sdhci@8804000 { 2843 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2844 pinctrl-names = "default", "sleep"; 2845 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 2846 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 2847 status = "disabled"; 2848 2849 reg = <0 0x08804000 0 0x1000>; 2850 2851 iommus = <&apps_smmu 0x100 0x0>; 2852 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2854 interrupt-names = "hc_irq", "pwr_irq"; 2855 2856 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2857 <&gcc GCC_SDCC2_AHB_CLK>, 2858 <&rpmhcc RPMH_CXO_CLK>; 2859 clock-names = "core", "iface", "xo"; 2860 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2861 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2862 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2863 power-domains = <&rpmhpd SC7280_CX>; 2864 operating-points-v2 = <&sdhc2_opp_table>; 2865 2866 bus-width = <4>; 2867 2868 qcom,dll-config = <0x0007642c>; 2869 2870 resets = <&gcc GCC_SDCC2_BCR>; 2871 2872 sdhc2_opp_table: opp-table { 2873 compatible = "operating-points-v2"; 2874 2875 opp-100000000 { 2876 opp-hz = /bits/ 64 <100000000>; 2877 required-opps = <&rpmhpd_opp_low_svs>; 2878 opp-peak-kBps = <1800000 400000>; 2879 opp-avg-kBps = <100000 0>; 2880 }; 2881 2882 opp-202000000 { 2883 opp-hz = /bits/ 64 <202000000>; 2884 required-opps = <&rpmhpd_opp_nom>; 2885 opp-peak-kBps = <5400000 1600000>; 2886 opp-avg-kBps = <200000 0>; 2887 }; 2888 }; 2889 2890 }; 2891 2892 usb_1_hsphy: phy@88e3000 { 2893 compatible = "qcom,sc7280-usb-hs-phy", 2894 "qcom,usb-snps-hs-7nm-phy"; 2895 reg = <0 0x088e3000 0 0x400>; 2896 status = "disabled"; 2897 #phy-cells = <0>; 2898 2899 clocks = <&rpmhcc RPMH_CXO_CLK>; 2900 clock-names = "ref"; 2901 2902 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2903 }; 2904 2905 usb_2_hsphy: phy@88e4000 { 2906 compatible = "qcom,sc7280-usb-hs-phy", 2907 "qcom,usb-snps-hs-7nm-phy"; 2908 reg = <0 0x088e4000 0 0x400>; 2909 status = "disabled"; 2910 #phy-cells = <0>; 2911 2912 clocks = <&rpmhcc RPMH_CXO_CLK>; 2913 clock-names = "ref"; 2914 2915 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2916 }; 2917 2918 usb_1_qmpphy: phy-wrapper@88e9000 { 2919 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2920 "qcom,sm8250-qmp-usb3-dp-phy"; 2921 reg = <0 0x088e9000 0 0x200>, 2922 <0 0x088e8000 0 0x40>, 2923 <0 0x088ea000 0 0x200>; 2924 status = "disabled"; 2925 #address-cells = <2>; 2926 #size-cells = <2>; 2927 ranges; 2928 2929 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2930 <&rpmhcc RPMH_CXO_CLK>, 2931 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2932 clock-names = "aux", "ref_clk_src", "com_aux"; 2933 2934 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2935 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2936 reset-names = "phy", "common"; 2937 2938 usb_1_ssphy: usb3-phy@88e9200 { 2939 reg = <0 0x088e9200 0 0x200>, 2940 <0 0x088e9400 0 0x200>, 2941 <0 0x088e9c00 0 0x400>, 2942 <0 0x088e9600 0 0x200>, 2943 <0 0x088e9800 0 0x200>, 2944 <0 0x088e9a00 0 0x100>; 2945 #clock-cells = <0>; 2946 #phy-cells = <0>; 2947 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2948 clock-names = "pipe0"; 2949 clock-output-names = "usb3_phy_pipe_clk_src"; 2950 }; 2951 2952 dp_phy: dp-phy@88ea200 { 2953 reg = <0 0x088ea200 0 0x200>, 2954 <0 0x088ea400 0 0x200>, 2955 <0 0x088eaa00 0 0x200>, 2956 <0 0x088ea600 0 0x200>, 2957 <0 0x088ea800 0 0x200>; 2958 #phy-cells = <0>; 2959 #clock-cells = <1>; 2960 }; 2961 }; 2962 2963 usb_2: usb@8cf8800 { 2964 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2965 reg = <0 0x08cf8800 0 0x400>; 2966 status = "disabled"; 2967 #address-cells = <2>; 2968 #size-cells = <2>; 2969 ranges; 2970 dma-ranges; 2971 2972 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2973 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2974 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2975 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2976 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2977 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2978 "sleep"; 2979 2980 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2981 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2982 assigned-clock-rates = <19200000>, <200000000>; 2983 2984 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2985 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2986 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2987 interrupt-names = "hs_phy_irq", 2988 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2989 2990 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2991 2992 resets = <&gcc GCC_USB30_SEC_BCR>; 2993 2994 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2995 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2996 interconnect-names = "usb-ddr", "apps-usb"; 2997 2998 usb_2_dwc3: usb@8c00000 { 2999 compatible = "snps,dwc3"; 3000 reg = <0 0x08c00000 0 0xe000>; 3001 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3002 iommus = <&apps_smmu 0xa0 0x0>; 3003 snps,dis_u2_susphy_quirk; 3004 snps,dis_enblslpm_quirk; 3005 phys = <&usb_2_hsphy>; 3006 phy-names = "usb2-phy"; 3007 maximum-speed = "high-speed"; 3008 }; 3009 }; 3010 3011 qspi: spi@88dc000 { 3012 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3013 reg = <0 0x088dc000 0 0x1000>; 3014 #address-cells = <1>; 3015 #size-cells = <0>; 3016 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3017 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3018 <&gcc GCC_QSPI_CORE_CLK>; 3019 clock-names = "iface", "core"; 3020 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3021 &cnoc2 SLAVE_QSPI_0 0>; 3022 interconnect-names = "qspi-config"; 3023 power-domains = <&rpmhpd SC7280_CX>; 3024 operating-points-v2 = <&qspi_opp_table>; 3025 status = "disabled"; 3026 }; 3027 3028 remoteproc_wpss: remoteproc@8a00000 { 3029 compatible = "qcom,sc7280-wpss-pil"; 3030 reg = <0 0x08a00000 0 0x10000>; 3031 3032 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3033 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3034 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3035 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3036 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3037 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3038 interrupt-names = "wdog", "fatal", "ready", "handover", 3039 "stop-ack", "shutdown-ack"; 3040 3041 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3042 <&gcc GCC_WPSS_AHB_CLK>, 3043 <&gcc GCC_WPSS_RSCP_CLK>, 3044 <&rpmhcc RPMH_CXO_CLK>; 3045 clock-names = "ahb_bdg", "ahb", 3046 "rscp", "xo"; 3047 3048 power-domains = <&rpmhpd SC7280_CX>, 3049 <&rpmhpd SC7280_MX>; 3050 power-domain-names = "cx", "mx"; 3051 3052 memory-region = <&wpss_mem>; 3053 3054 qcom,qmp = <&aoss_qmp>; 3055 3056 qcom,smem-states = <&wpss_smp2p_out 0>; 3057 qcom,smem-state-names = "stop"; 3058 3059 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3060 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3061 reset-names = "restart", "pdc_sync"; 3062 3063 qcom,halt-regs = <&tcsr_mutex 0x37000>; 3064 3065 status = "disabled"; 3066 3067 glink-edge { 3068 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3069 IPCC_MPROC_SIGNAL_GLINK_QMP 3070 IRQ_TYPE_EDGE_RISING>; 3071 mboxes = <&ipcc IPCC_CLIENT_WPSS 3072 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3073 3074 label = "wpss"; 3075 qcom,remote-pid = <13>; 3076 }; 3077 }; 3078 3079 dc_noc: interconnect@90e0000 { 3080 reg = <0 0x090e0000 0 0x5080>; 3081 compatible = "qcom,sc7280-dc-noc"; 3082 #interconnect-cells = <2>; 3083 qcom,bcm-voters = <&apps_bcm_voter>; 3084 }; 3085 3086 gem_noc: interconnect@9100000 { 3087 reg = <0 0x9100000 0 0xe2200>; 3088 compatible = "qcom,sc7280-gem-noc"; 3089 #interconnect-cells = <2>; 3090 qcom,bcm-voters = <&apps_bcm_voter>; 3091 }; 3092 3093 system-cache-controller@9200000 { 3094 compatible = "qcom,sc7280-llcc"; 3095 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3096 reg-names = "llcc_base", "llcc_broadcast_base"; 3097 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3098 }; 3099 3100 nsp_noc: interconnect@a0c0000 { 3101 reg = <0 0x0a0c0000 0 0x10000>; 3102 compatible = "qcom,sc7280-nsp-noc"; 3103 #interconnect-cells = <2>; 3104 qcom,bcm-voters = <&apps_bcm_voter>; 3105 }; 3106 3107 usb_1: usb@a6f8800 { 3108 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3109 reg = <0 0x0a6f8800 0 0x400>; 3110 status = "disabled"; 3111 #address-cells = <2>; 3112 #size-cells = <2>; 3113 ranges; 3114 dma-ranges; 3115 3116 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3117 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3118 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3119 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3120 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3121 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3122 "sleep"; 3123 3124 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3125 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3126 assigned-clock-rates = <19200000>, <200000000>; 3127 3128 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3129 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3130 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3131 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3132 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3133 "dm_hs_phy_irq", "ss_phy_irq"; 3134 3135 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3136 3137 resets = <&gcc GCC_USB30_PRIM_BCR>; 3138 3139 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3140 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3141 interconnect-names = "usb-ddr", "apps-usb"; 3142 3143 usb_1_dwc3: usb@a600000 { 3144 compatible = "snps,dwc3"; 3145 reg = <0 0x0a600000 0 0xe000>; 3146 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3147 iommus = <&apps_smmu 0xe0 0x0>; 3148 snps,dis_u2_susphy_quirk; 3149 snps,dis_enblslpm_quirk; 3150 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3151 phy-names = "usb2-phy", "usb3-phy"; 3152 maximum-speed = "super-speed"; 3153 wakeup-source; 3154 }; 3155 }; 3156 3157 venus: video-codec@aa00000 { 3158 compatible = "qcom,sc7280-venus"; 3159 reg = <0 0x0aa00000 0 0xd0600>; 3160 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3161 3162 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3163 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3164 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3165 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3166 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3167 clock-names = "core", "bus", "iface", 3168 "vcodec_core", "vcodec_bus"; 3169 3170 power-domains = <&videocc MVSC_GDSC>, 3171 <&videocc MVS0_GDSC>, 3172 <&rpmhpd SC7280_CX>; 3173 power-domain-names = "venus", "vcodec0", "cx"; 3174 operating-points-v2 = <&venus_opp_table>; 3175 3176 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3177 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3178 interconnect-names = "cpu-cfg", "video-mem"; 3179 3180 iommus = <&apps_smmu 0x2180 0x20>, 3181 <&apps_smmu 0x2184 0x20>; 3182 memory-region = <&video_mem>; 3183 3184 video-decoder { 3185 compatible = "venus-decoder"; 3186 }; 3187 3188 video-encoder { 3189 compatible = "venus-encoder"; 3190 }; 3191 3192 video-firmware { 3193 iommus = <&apps_smmu 0x21a2 0x0>; 3194 }; 3195 3196 venus_opp_table: venus-opp-table { 3197 compatible = "operating-points-v2"; 3198 3199 opp-133330000 { 3200 opp-hz = /bits/ 64 <133330000>; 3201 required-opps = <&rpmhpd_opp_low_svs>; 3202 }; 3203 3204 opp-240000000 { 3205 opp-hz = /bits/ 64 <240000000>; 3206 required-opps = <&rpmhpd_opp_svs>; 3207 }; 3208 3209 opp-335000000 { 3210 opp-hz = /bits/ 64 <335000000>; 3211 required-opps = <&rpmhpd_opp_svs_l1>; 3212 }; 3213 3214 opp-424000000 { 3215 opp-hz = /bits/ 64 <424000000>; 3216 required-opps = <&rpmhpd_opp_nom>; 3217 }; 3218 3219 opp-460000048 { 3220 opp-hz = /bits/ 64 <460000048>; 3221 required-opps = <&rpmhpd_opp_turbo>; 3222 }; 3223 }; 3224 3225 }; 3226 3227 videocc: clock-controller@aaf0000 { 3228 compatible = "qcom,sc7280-videocc"; 3229 reg = <0 0xaaf0000 0 0x10000>; 3230 clocks = <&rpmhcc RPMH_CXO_CLK>, 3231 <&rpmhcc RPMH_CXO_CLK_A>; 3232 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3233 #clock-cells = <1>; 3234 #reset-cells = <1>; 3235 #power-domain-cells = <1>; 3236 }; 3237 3238 camcc: clock-controller@ad00000 { 3239 compatible = "qcom,sc7280-camcc"; 3240 reg = <0 0x0ad00000 0 0x10000>; 3241 clocks = <&rpmhcc RPMH_CXO_CLK>, 3242 <&rpmhcc RPMH_CXO_CLK_A>, 3243 <&sleep_clk>; 3244 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3245 #clock-cells = <1>; 3246 #reset-cells = <1>; 3247 #power-domain-cells = <1>; 3248 }; 3249 3250 dispcc: clock-controller@af00000 { 3251 compatible = "qcom,sc7280-dispcc"; 3252 reg = <0 0xaf00000 0 0x20000>; 3253 clocks = <&rpmhcc RPMH_CXO_CLK>, 3254 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3255 <&mdss_dsi_phy 0>, 3256 <&mdss_dsi_phy 1>, 3257 <&dp_phy 0>, 3258 <&dp_phy 1>, 3259 <&mdss_edp_phy 0>, 3260 <&mdss_edp_phy 1>; 3261 clock-names = "bi_tcxo", 3262 "gcc_disp_gpll0_clk", 3263 "dsi0_phy_pll_out_byteclk", 3264 "dsi0_phy_pll_out_dsiclk", 3265 "dp_phy_pll_link_clk", 3266 "dp_phy_pll_vco_div_clk", 3267 "edp_phy_pll_link_clk", 3268 "edp_phy_pll_vco_div_clk"; 3269 #clock-cells = <1>; 3270 #reset-cells = <1>; 3271 #power-domain-cells = <1>; 3272 }; 3273 3274 mdss: display-subsystem@ae00000 { 3275 compatible = "qcom,sc7280-mdss"; 3276 reg = <0 0x0ae00000 0 0x1000>; 3277 reg-names = "mdss"; 3278 3279 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3280 3281 clocks = <&gcc GCC_DISP_AHB_CLK>, 3282 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3283 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3284 clock-names = "iface", 3285 "ahb", 3286 "core"; 3287 3288 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3289 assigned-clock-rates = <300000000>; 3290 3291 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3292 interrupt-controller; 3293 #interrupt-cells = <1>; 3294 3295 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3296 interconnect-names = "mdp0-mem"; 3297 3298 iommus = <&apps_smmu 0x900 0x402>; 3299 3300 #address-cells = <2>; 3301 #size-cells = <2>; 3302 ranges; 3303 3304 status = "disabled"; 3305 3306 mdss_mdp: display-controller@ae01000 { 3307 compatible = "qcom,sc7280-dpu"; 3308 reg = <0 0x0ae01000 0 0x8f030>, 3309 <0 0x0aeb0000 0 0x2008>; 3310 reg-names = "mdp", "vbif"; 3311 3312 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3313 <&gcc GCC_DISP_SF_AXI_CLK>, 3314 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3315 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3316 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3317 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3318 clock-names = "bus", 3319 "nrt_bus", 3320 "iface", 3321 "lut", 3322 "core", 3323 "vsync"; 3324 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3325 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3326 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3327 assigned-clock-rates = <300000000>, 3328 <19200000>, 3329 <19200000>; 3330 operating-points-v2 = <&mdp_opp_table>; 3331 power-domains = <&rpmhpd SC7280_CX>; 3332 3333 interrupt-parent = <&mdss>; 3334 interrupts = <0>; 3335 3336 status = "disabled"; 3337 3338 ports { 3339 #address-cells = <1>; 3340 #size-cells = <0>; 3341 3342 port@0 { 3343 reg = <0>; 3344 dpu_intf1_out: endpoint { 3345 remote-endpoint = <&dsi0_in>; 3346 }; 3347 }; 3348 3349 port@1 { 3350 reg = <1>; 3351 dpu_intf5_out: endpoint { 3352 remote-endpoint = <&edp_in>; 3353 }; 3354 }; 3355 3356 port@2 { 3357 reg = <2>; 3358 dpu_intf0_out: endpoint { 3359 remote-endpoint = <&dp_in>; 3360 }; 3361 }; 3362 }; 3363 3364 mdp_opp_table: opp-table { 3365 compatible = "operating-points-v2"; 3366 3367 opp-200000000 { 3368 opp-hz = /bits/ 64 <200000000>; 3369 required-opps = <&rpmhpd_opp_low_svs>; 3370 }; 3371 3372 opp-300000000 { 3373 opp-hz = /bits/ 64 <300000000>; 3374 required-opps = <&rpmhpd_opp_svs>; 3375 }; 3376 3377 opp-380000000 { 3378 opp-hz = /bits/ 64 <380000000>; 3379 required-opps = <&rpmhpd_opp_svs_l1>; 3380 }; 3381 3382 opp-506666667 { 3383 opp-hz = /bits/ 64 <506666667>; 3384 required-opps = <&rpmhpd_opp_nom>; 3385 }; 3386 }; 3387 }; 3388 3389 mdss_dsi: dsi@ae94000 { 3390 compatible = "qcom,mdss-dsi-ctrl"; 3391 reg = <0 0x0ae94000 0 0x400>; 3392 reg-names = "dsi_ctrl"; 3393 3394 interrupt-parent = <&mdss>; 3395 interrupts = <4>; 3396 3397 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3398 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3399 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3400 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3401 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3402 <&gcc GCC_DISP_HF_AXI_CLK>; 3403 clock-names = "byte", 3404 "byte_intf", 3405 "pixel", 3406 "core", 3407 "iface", 3408 "bus"; 3409 3410 operating-points-v2 = <&dsi_opp_table>; 3411 power-domains = <&rpmhpd SC7280_CX>; 3412 3413 phys = <&mdss_dsi_phy>; 3414 phy-names = "dsi"; 3415 3416 #address-cells = <1>; 3417 #size-cells = <0>; 3418 3419 status = "disabled"; 3420 3421 ports { 3422 #address-cells = <1>; 3423 #size-cells = <0>; 3424 3425 port@0 { 3426 reg = <0>; 3427 dsi0_in: endpoint { 3428 remote-endpoint = <&dpu_intf1_out>; 3429 }; 3430 }; 3431 3432 port@1 { 3433 reg = <1>; 3434 dsi0_out: endpoint { 3435 }; 3436 }; 3437 }; 3438 3439 dsi_opp_table: opp-table { 3440 compatible = "operating-points-v2"; 3441 3442 opp-187500000 { 3443 opp-hz = /bits/ 64 <187500000>; 3444 required-opps = <&rpmhpd_opp_low_svs>; 3445 }; 3446 3447 opp-300000000 { 3448 opp-hz = /bits/ 64 <300000000>; 3449 required-opps = <&rpmhpd_opp_svs>; 3450 }; 3451 3452 opp-358000000 { 3453 opp-hz = /bits/ 64 <358000000>; 3454 required-opps = <&rpmhpd_opp_svs_l1>; 3455 }; 3456 }; 3457 }; 3458 3459 mdss_dsi_phy: phy@ae94400 { 3460 compatible = "qcom,sc7280-dsi-phy-7nm"; 3461 reg = <0 0x0ae94400 0 0x200>, 3462 <0 0x0ae94600 0 0x280>, 3463 <0 0x0ae94900 0 0x280>; 3464 reg-names = "dsi_phy", 3465 "dsi_phy_lane", 3466 "dsi_pll"; 3467 3468 #clock-cells = <1>; 3469 #phy-cells = <0>; 3470 3471 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3472 <&rpmhcc RPMH_CXO_CLK>; 3473 clock-names = "iface", "ref"; 3474 3475 status = "disabled"; 3476 }; 3477 3478 mdss_edp: edp@aea0000 { 3479 compatible = "qcom,sc7280-edp"; 3480 pinctrl-names = "default"; 3481 pinctrl-0 = <&edp_hot_plug_det>; 3482 3483 reg = <0 0xaea0000 0 0x200>, 3484 <0 0xaea0200 0 0x200>, 3485 <0 0xaea0400 0 0xc00>, 3486 <0 0xaea1000 0 0x400>; 3487 3488 interrupt-parent = <&mdss>; 3489 interrupts = <14>; 3490 3491 clocks = <&rpmhcc RPMH_CXO_CLK>, 3492 <&gcc GCC_EDP_CLKREF_EN>, 3493 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3494 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3495 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3496 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3497 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3498 clock-names = "core_xo", 3499 "core_ref", 3500 "core_iface", 3501 "core_aux", 3502 "ctrl_link", 3503 "ctrl_link_iface", 3504 "stream_pixel"; 3505 #clock-cells = <1>; 3506 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3507 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3508 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3509 3510 phys = <&mdss_edp_phy>; 3511 phy-names = "dp"; 3512 3513 operating-points-v2 = <&edp_opp_table>; 3514 power-domains = <&rpmhpd SC7280_CX>; 3515 3516 #address-cells = <1>; 3517 #size-cells = <0>; 3518 3519 status = "disabled"; 3520 3521 ports { 3522 #address-cells = <1>; 3523 #size-cells = <0>; 3524 3525 port@0 { 3526 reg = <0>; 3527 edp_in: endpoint { 3528 remote-endpoint = <&dpu_intf5_out>; 3529 }; 3530 }; 3531 3532 port@1 { 3533 reg = <1>; 3534 mdss_edp_out: endpoint { }; 3535 }; 3536 }; 3537 3538 edp_opp_table: opp-table { 3539 compatible = "operating-points-v2"; 3540 3541 opp-160000000 { 3542 opp-hz = /bits/ 64 <160000000>; 3543 required-opps = <&rpmhpd_opp_low_svs>; 3544 }; 3545 3546 opp-270000000 { 3547 opp-hz = /bits/ 64 <270000000>; 3548 required-opps = <&rpmhpd_opp_svs>; 3549 }; 3550 3551 opp-540000000 { 3552 opp-hz = /bits/ 64 <540000000>; 3553 required-opps = <&rpmhpd_opp_nom>; 3554 }; 3555 3556 opp-810000000 { 3557 opp-hz = /bits/ 64 <810000000>; 3558 required-opps = <&rpmhpd_opp_nom>; 3559 }; 3560 }; 3561 }; 3562 3563 mdss_edp_phy: phy@aec2a00 { 3564 compatible = "qcom,sc7280-edp-phy"; 3565 3566 reg = <0 0xaec2a00 0 0x19c>, 3567 <0 0xaec2200 0 0xa0>, 3568 <0 0xaec2600 0 0xa0>, 3569 <0 0xaec2000 0 0x1c0>; 3570 3571 clocks = <&rpmhcc RPMH_CXO_CLK>, 3572 <&gcc GCC_EDP_CLKREF_EN>; 3573 clock-names = "aux", 3574 "cfg_ahb"; 3575 3576 #clock-cells = <1>; 3577 #phy-cells = <0>; 3578 3579 status = "disabled"; 3580 }; 3581 3582 mdss_dp: displayport-controller@ae90000 { 3583 compatible = "qcom,sc7280-dp"; 3584 3585 reg = <0 0x0ae90000 0 0x1400>; 3586 3587 interrupt-parent = <&mdss>; 3588 interrupts = <12>; 3589 3590 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3591 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3592 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3593 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3594 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3595 clock-names = "core_iface", 3596 "core_aux", 3597 "ctrl_link", 3598 "ctrl_link_iface", 3599 "stream_pixel"; 3600 #clock-cells = <1>; 3601 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3602 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3603 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3604 phys = <&dp_phy>; 3605 phy-names = "dp"; 3606 3607 operating-points-v2 = <&dp_opp_table>; 3608 power-domains = <&rpmhpd SC7280_CX>; 3609 3610 #sound-dai-cells = <0>; 3611 3612 status = "disabled"; 3613 3614 ports { 3615 #address-cells = <1>; 3616 #size-cells = <0>; 3617 3618 port@0 { 3619 reg = <0>; 3620 dp_in: endpoint { 3621 remote-endpoint = <&dpu_intf0_out>; 3622 }; 3623 }; 3624 3625 port@1 { 3626 reg = <1>; 3627 dp_out: endpoint { }; 3628 }; 3629 }; 3630 3631 dp_opp_table: opp-table { 3632 compatible = "operating-points-v2"; 3633 3634 opp-160000000 { 3635 opp-hz = /bits/ 64 <160000000>; 3636 required-opps = <&rpmhpd_opp_low_svs>; 3637 }; 3638 3639 opp-270000000 { 3640 opp-hz = /bits/ 64 <270000000>; 3641 required-opps = <&rpmhpd_opp_svs>; 3642 }; 3643 3644 opp-540000000 { 3645 opp-hz = /bits/ 64 <540000000>; 3646 required-opps = <&rpmhpd_opp_svs_l1>; 3647 }; 3648 3649 opp-810000000 { 3650 opp-hz = /bits/ 64 <810000000>; 3651 required-opps = <&rpmhpd_opp_nom>; 3652 }; 3653 }; 3654 }; 3655 }; 3656 3657 pdc: interrupt-controller@b220000 { 3658 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3659 reg = <0 0x0b220000 0 0x30000>; 3660 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3661 <55 306 4>, <59 312 3>, <62 374 2>, 3662 <64 434 2>, <66 438 3>, <69 86 1>, 3663 <70 520 54>, <124 609 31>, <155 63 1>, 3664 <156 716 12>; 3665 #interrupt-cells = <2>; 3666 interrupt-parent = <&intc>; 3667 interrupt-controller; 3668 }; 3669 3670 pdc_reset: reset-controller@b5e0000 { 3671 compatible = "qcom,sc7280-pdc-global"; 3672 reg = <0 0x0b5e0000 0 0x20000>; 3673 #reset-cells = <1>; 3674 }; 3675 3676 tsens0: thermal-sensor@c263000 { 3677 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3678 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3679 <0 0x0c222000 0 0x1ff>; /* SROT */ 3680 #qcom,sensors = <15>; 3681 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3683 interrupt-names = "uplow","critical"; 3684 #thermal-sensor-cells = <1>; 3685 }; 3686 3687 tsens1: thermal-sensor@c265000 { 3688 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3689 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3690 <0 0x0c223000 0 0x1ff>; /* SROT */ 3691 #qcom,sensors = <12>; 3692 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3694 interrupt-names = "uplow","critical"; 3695 #thermal-sensor-cells = <1>; 3696 }; 3697 3698 aoss_reset: reset-controller@c2a0000 { 3699 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3700 reg = <0 0x0c2a0000 0 0x31000>; 3701 #reset-cells = <1>; 3702 }; 3703 3704 aoss_qmp: power-controller@c300000 { 3705 compatible = "qcom,sc7280-aoss-qmp"; 3706 reg = <0 0x0c300000 0 0x400>; 3707 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3708 IPCC_MPROC_SIGNAL_GLINK_QMP 3709 IRQ_TYPE_EDGE_RISING>; 3710 mboxes = <&ipcc IPCC_CLIENT_AOP 3711 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3712 3713 #clock-cells = <0>; 3714 }; 3715 3716 sram@c3f0000 { 3717 compatible = "qcom,rpmh-stats"; 3718 reg = <0 0x0c3f0000 0 0x400>; 3719 }; 3720 3721 spmi_bus: spmi@c440000 { 3722 compatible = "qcom,spmi-pmic-arb"; 3723 reg = <0 0x0c440000 0 0x1100>, 3724 <0 0x0c600000 0 0x2000000>, 3725 <0 0x0e600000 0 0x100000>, 3726 <0 0x0e700000 0 0xa0000>, 3727 <0 0x0c40a000 0 0x26000>; 3728 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3729 interrupt-names = "periph_irq"; 3730 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3731 qcom,ee = <0>; 3732 qcom,channel = <0>; 3733 #address-cells = <1>; 3734 #size-cells = <1>; 3735 interrupt-controller; 3736 #interrupt-cells = <4>; 3737 }; 3738 3739 tlmm: pinctrl@f100000 { 3740 compatible = "qcom,sc7280-pinctrl"; 3741 reg = <0 0x0f100000 0 0x300000>; 3742 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3743 gpio-controller; 3744 #gpio-cells = <2>; 3745 interrupt-controller; 3746 #interrupt-cells = <2>; 3747 gpio-ranges = <&tlmm 0 0 175>; 3748 wakeup-parent = <&pdc>; 3749 3750 dp_hot_plug_det: dp-hot-plug-det { 3751 pins = "gpio47"; 3752 function = "dp_hot"; 3753 }; 3754 3755 edp_hot_plug_det: edp-hot-plug-det { 3756 pins = "gpio60"; 3757 function = "edp_hot"; 3758 }; 3759 3760 pcie1_clkreq_n: pcie1-clkreq-n { 3761 pins = "gpio79"; 3762 function = "pcie1_clkreqn"; 3763 }; 3764 3765 qspi_clk: qspi-clk { 3766 pins = "gpio14"; 3767 function = "qspi_clk"; 3768 }; 3769 3770 qspi_cs0: qspi-cs0 { 3771 pins = "gpio15"; 3772 function = "qspi_cs"; 3773 }; 3774 3775 qspi_cs1: qspi-cs1 { 3776 pins = "gpio19"; 3777 function = "qspi_cs"; 3778 }; 3779 3780 qspi_data01: qspi-data01 { 3781 pins = "gpio12", "gpio13"; 3782 function = "qspi_data"; 3783 }; 3784 3785 qspi_data12: qspi-data12 { 3786 pins = "gpio16", "gpio17"; 3787 function = "qspi_data"; 3788 }; 3789 3790 qup_i2c0_data_clk: qup-i2c0-data-clk { 3791 pins = "gpio0", "gpio1"; 3792 function = "qup00"; 3793 }; 3794 3795 qup_i2c1_data_clk: qup-i2c1-data-clk { 3796 pins = "gpio4", "gpio5"; 3797 function = "qup01"; 3798 }; 3799 3800 qup_i2c2_data_clk: qup-i2c2-data-clk { 3801 pins = "gpio8", "gpio9"; 3802 function = "qup02"; 3803 }; 3804 3805 qup_i2c3_data_clk: qup-i2c3-data-clk { 3806 pins = "gpio12", "gpio13"; 3807 function = "qup03"; 3808 }; 3809 3810 qup_i2c4_data_clk: qup-i2c4-data-clk { 3811 pins = "gpio16", "gpio17"; 3812 function = "qup04"; 3813 }; 3814 3815 qup_i2c5_data_clk: qup-i2c5-data-clk { 3816 pins = "gpio20", "gpio21"; 3817 function = "qup05"; 3818 }; 3819 3820 qup_i2c6_data_clk: qup-i2c6-data-clk { 3821 pins = "gpio24", "gpio25"; 3822 function = "qup06"; 3823 }; 3824 3825 qup_i2c7_data_clk: qup-i2c7-data-clk { 3826 pins = "gpio28", "gpio29"; 3827 function = "qup07"; 3828 }; 3829 3830 qup_i2c8_data_clk: qup-i2c8-data-clk { 3831 pins = "gpio32", "gpio33"; 3832 function = "qup10"; 3833 }; 3834 3835 qup_i2c9_data_clk: qup-i2c9-data-clk { 3836 pins = "gpio36", "gpio37"; 3837 function = "qup11"; 3838 }; 3839 3840 qup_i2c10_data_clk: qup-i2c10-data-clk { 3841 pins = "gpio40", "gpio41"; 3842 function = "qup12"; 3843 }; 3844 3845 qup_i2c11_data_clk: qup-i2c11-data-clk { 3846 pins = "gpio44", "gpio45"; 3847 function = "qup13"; 3848 }; 3849 3850 qup_i2c12_data_clk: qup-i2c12-data-clk { 3851 pins = "gpio48", "gpio49"; 3852 function = "qup14"; 3853 }; 3854 3855 qup_i2c13_data_clk: qup-i2c13-data-clk { 3856 pins = "gpio52", "gpio53"; 3857 function = "qup15"; 3858 }; 3859 3860 qup_i2c14_data_clk: qup-i2c14-data-clk { 3861 pins = "gpio56", "gpio57"; 3862 function = "qup16"; 3863 }; 3864 3865 qup_i2c15_data_clk: qup-i2c15-data-clk { 3866 pins = "gpio60", "gpio61"; 3867 function = "qup17"; 3868 }; 3869 3870 qup_spi0_data_clk: qup-spi0-data-clk { 3871 pins = "gpio0", "gpio1", "gpio2"; 3872 function = "qup00"; 3873 }; 3874 3875 qup_spi0_cs: qup-spi0-cs { 3876 pins = "gpio3"; 3877 function = "qup00"; 3878 }; 3879 3880 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3881 pins = "gpio3"; 3882 function = "gpio"; 3883 }; 3884 3885 qup_spi1_data_clk: qup-spi1-data-clk { 3886 pins = "gpio4", "gpio5", "gpio6"; 3887 function = "qup01"; 3888 }; 3889 3890 qup_spi1_cs: qup-spi1-cs { 3891 pins = "gpio7"; 3892 function = "qup01"; 3893 }; 3894 3895 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3896 pins = "gpio7"; 3897 function = "gpio"; 3898 }; 3899 3900 qup_spi2_data_clk: qup-spi2-data-clk { 3901 pins = "gpio8", "gpio9", "gpio10"; 3902 function = "qup02"; 3903 }; 3904 3905 qup_spi2_cs: qup-spi2-cs { 3906 pins = "gpio11"; 3907 function = "qup02"; 3908 }; 3909 3910 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3911 pins = "gpio11"; 3912 function = "gpio"; 3913 }; 3914 3915 qup_spi3_data_clk: qup-spi3-data-clk { 3916 pins = "gpio12", "gpio13", "gpio14"; 3917 function = "qup03"; 3918 }; 3919 3920 qup_spi3_cs: qup-spi3-cs { 3921 pins = "gpio15"; 3922 function = "qup03"; 3923 }; 3924 3925 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3926 pins = "gpio15"; 3927 function = "gpio"; 3928 }; 3929 3930 qup_spi4_data_clk: qup-spi4-data-clk { 3931 pins = "gpio16", "gpio17", "gpio18"; 3932 function = "qup04"; 3933 }; 3934 3935 qup_spi4_cs: qup-spi4-cs { 3936 pins = "gpio19"; 3937 function = "qup04"; 3938 }; 3939 3940 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3941 pins = "gpio19"; 3942 function = "gpio"; 3943 }; 3944 3945 qup_spi5_data_clk: qup-spi5-data-clk { 3946 pins = "gpio20", "gpio21", "gpio22"; 3947 function = "qup05"; 3948 }; 3949 3950 qup_spi5_cs: qup-spi5-cs { 3951 pins = "gpio23"; 3952 function = "qup05"; 3953 }; 3954 3955 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3956 pins = "gpio23"; 3957 function = "gpio"; 3958 }; 3959 3960 qup_spi6_data_clk: qup-spi6-data-clk { 3961 pins = "gpio24", "gpio25", "gpio26"; 3962 function = "qup06"; 3963 }; 3964 3965 qup_spi6_cs: qup-spi6-cs { 3966 pins = "gpio27"; 3967 function = "qup06"; 3968 }; 3969 3970 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3971 pins = "gpio27"; 3972 function = "gpio"; 3973 }; 3974 3975 qup_spi7_data_clk: qup-spi7-data-clk { 3976 pins = "gpio28", "gpio29", "gpio30"; 3977 function = "qup07"; 3978 }; 3979 3980 qup_spi7_cs: qup-spi7-cs { 3981 pins = "gpio31"; 3982 function = "qup07"; 3983 }; 3984 3985 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3986 pins = "gpio31"; 3987 function = "gpio"; 3988 }; 3989 3990 qup_spi8_data_clk: qup-spi8-data-clk { 3991 pins = "gpio32", "gpio33", "gpio34"; 3992 function = "qup10"; 3993 }; 3994 3995 qup_spi8_cs: qup-spi8-cs { 3996 pins = "gpio35"; 3997 function = "qup10"; 3998 }; 3999 4000 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4001 pins = "gpio35"; 4002 function = "gpio"; 4003 }; 4004 4005 qup_spi9_data_clk: qup-spi9-data-clk { 4006 pins = "gpio36", "gpio37", "gpio38"; 4007 function = "qup11"; 4008 }; 4009 4010 qup_spi9_cs: qup-spi9-cs { 4011 pins = "gpio39"; 4012 function = "qup11"; 4013 }; 4014 4015 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4016 pins = "gpio39"; 4017 function = "gpio"; 4018 }; 4019 4020 qup_spi10_data_clk: qup-spi10-data-clk { 4021 pins = "gpio40", "gpio41", "gpio42"; 4022 function = "qup12"; 4023 }; 4024 4025 qup_spi10_cs: qup-spi10-cs { 4026 pins = "gpio43"; 4027 function = "qup12"; 4028 }; 4029 4030 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4031 pins = "gpio43"; 4032 function = "gpio"; 4033 }; 4034 4035 qup_spi11_data_clk: qup-spi11-data-clk { 4036 pins = "gpio44", "gpio45", "gpio46"; 4037 function = "qup13"; 4038 }; 4039 4040 qup_spi11_cs: qup-spi11-cs { 4041 pins = "gpio47"; 4042 function = "qup13"; 4043 }; 4044 4045 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4046 pins = "gpio47"; 4047 function = "gpio"; 4048 }; 4049 4050 qup_spi12_data_clk: qup-spi12-data-clk { 4051 pins = "gpio48", "gpio49", "gpio50"; 4052 function = "qup14"; 4053 }; 4054 4055 qup_spi12_cs: qup-spi12-cs { 4056 pins = "gpio51"; 4057 function = "qup14"; 4058 }; 4059 4060 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4061 pins = "gpio51"; 4062 function = "gpio"; 4063 }; 4064 4065 qup_spi13_data_clk: qup-spi13-data-clk { 4066 pins = "gpio52", "gpio53", "gpio54"; 4067 function = "qup15"; 4068 }; 4069 4070 qup_spi13_cs: qup-spi13-cs { 4071 pins = "gpio55"; 4072 function = "qup15"; 4073 }; 4074 4075 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4076 pins = "gpio55"; 4077 function = "gpio"; 4078 }; 4079 4080 qup_spi14_data_clk: qup-spi14-data-clk { 4081 pins = "gpio56", "gpio57", "gpio58"; 4082 function = "qup16"; 4083 }; 4084 4085 qup_spi14_cs: qup-spi14-cs { 4086 pins = "gpio59"; 4087 function = "qup16"; 4088 }; 4089 4090 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4091 pins = "gpio59"; 4092 function = "gpio"; 4093 }; 4094 4095 qup_spi15_data_clk: qup-spi15-data-clk { 4096 pins = "gpio60", "gpio61", "gpio62"; 4097 function = "qup17"; 4098 }; 4099 4100 qup_spi15_cs: qup-spi15-cs { 4101 pins = "gpio63"; 4102 function = "qup17"; 4103 }; 4104 4105 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4106 pins = "gpio63"; 4107 function = "gpio"; 4108 }; 4109 4110 qup_uart0_cts: qup-uart0-cts { 4111 pins = "gpio0"; 4112 function = "qup00"; 4113 }; 4114 4115 qup_uart0_rts: qup-uart0-rts { 4116 pins = "gpio1"; 4117 function = "qup00"; 4118 }; 4119 4120 qup_uart0_tx: qup-uart0-tx { 4121 pins = "gpio2"; 4122 function = "qup00"; 4123 }; 4124 4125 qup_uart0_rx: qup-uart0-rx { 4126 pins = "gpio3"; 4127 function = "qup00"; 4128 }; 4129 4130 qup_uart1_cts: qup-uart1-cts { 4131 pins = "gpio4"; 4132 function = "qup01"; 4133 }; 4134 4135 qup_uart1_rts: qup-uart1-rts { 4136 pins = "gpio5"; 4137 function = "qup01"; 4138 }; 4139 4140 qup_uart1_tx: qup-uart1-tx { 4141 pins = "gpio6"; 4142 function = "qup01"; 4143 }; 4144 4145 qup_uart1_rx: qup-uart1-rx { 4146 pins = "gpio7"; 4147 function = "qup01"; 4148 }; 4149 4150 qup_uart2_cts: qup-uart2-cts { 4151 pins = "gpio8"; 4152 function = "qup02"; 4153 }; 4154 4155 qup_uart2_rts: qup-uart2-rts { 4156 pins = "gpio9"; 4157 function = "qup02"; 4158 }; 4159 4160 qup_uart2_tx: qup-uart2-tx { 4161 pins = "gpio10"; 4162 function = "qup02"; 4163 }; 4164 4165 qup_uart2_rx: qup-uart2-rx { 4166 pins = "gpio11"; 4167 function = "qup02"; 4168 }; 4169 4170 qup_uart3_cts: qup-uart3-cts { 4171 pins = "gpio12"; 4172 function = "qup03"; 4173 }; 4174 4175 qup_uart3_rts: qup-uart3-rts { 4176 pins = "gpio13"; 4177 function = "qup03"; 4178 }; 4179 4180 qup_uart3_tx: qup-uart3-tx { 4181 pins = "gpio14"; 4182 function = "qup03"; 4183 }; 4184 4185 qup_uart3_rx: qup-uart3-rx { 4186 pins = "gpio15"; 4187 function = "qup03"; 4188 }; 4189 4190 qup_uart4_cts: qup-uart4-cts { 4191 pins = "gpio16"; 4192 function = "qup04"; 4193 }; 4194 4195 qup_uart4_rts: qup-uart4-rts { 4196 pins = "gpio17"; 4197 function = "qup04"; 4198 }; 4199 4200 qup_uart4_tx: qup-uart4-tx { 4201 pins = "gpio18"; 4202 function = "qup04"; 4203 }; 4204 4205 qup_uart4_rx: qup-uart4-rx { 4206 pins = "gpio19"; 4207 function = "qup04"; 4208 }; 4209 4210 qup_uart5_cts: qup-uart5-cts { 4211 pins = "gpio20"; 4212 function = "qup05"; 4213 }; 4214 4215 qup_uart5_rts: qup-uart5-rts { 4216 pins = "gpio21"; 4217 function = "qup05"; 4218 }; 4219 4220 qup_uart5_tx: qup-uart5-tx { 4221 pins = "gpio22"; 4222 function = "qup05"; 4223 }; 4224 4225 qup_uart5_rx: qup-uart5-rx { 4226 pins = "gpio23"; 4227 function = "qup05"; 4228 }; 4229 4230 qup_uart6_cts: qup-uart6-cts { 4231 pins = "gpio24"; 4232 function = "qup06"; 4233 }; 4234 4235 qup_uart6_rts: qup-uart6-rts { 4236 pins = "gpio25"; 4237 function = "qup06"; 4238 }; 4239 4240 qup_uart6_tx: qup-uart6-tx { 4241 pins = "gpio26"; 4242 function = "qup06"; 4243 }; 4244 4245 qup_uart6_rx: qup-uart6-rx { 4246 pins = "gpio27"; 4247 function = "qup06"; 4248 }; 4249 4250 qup_uart7_cts: qup-uart7-cts { 4251 pins = "gpio28"; 4252 function = "qup07"; 4253 }; 4254 4255 qup_uart7_rts: qup-uart7-rts { 4256 pins = "gpio29"; 4257 function = "qup07"; 4258 }; 4259 4260 qup_uart7_tx: qup-uart7-tx { 4261 pins = "gpio30"; 4262 function = "qup07"; 4263 }; 4264 4265 qup_uart7_rx: qup-uart7-rx { 4266 pins = "gpio31"; 4267 function = "qup07"; 4268 }; 4269 4270 qup_uart8_cts: qup-uart8-cts { 4271 pins = "gpio32"; 4272 function = "qup10"; 4273 }; 4274 4275 qup_uart8_rts: qup-uart8-rts { 4276 pins = "gpio33"; 4277 function = "qup10"; 4278 }; 4279 4280 qup_uart8_tx: qup-uart8-tx { 4281 pins = "gpio34"; 4282 function = "qup10"; 4283 }; 4284 4285 qup_uart8_rx: qup-uart8-rx { 4286 pins = "gpio35"; 4287 function = "qup10"; 4288 }; 4289 4290 qup_uart9_cts: qup-uart9-cts { 4291 pins = "gpio36"; 4292 function = "qup11"; 4293 }; 4294 4295 qup_uart9_rts: qup-uart9-rts { 4296 pins = "gpio37"; 4297 function = "qup11"; 4298 }; 4299 4300 qup_uart9_tx: qup-uart9-tx { 4301 pins = "gpio38"; 4302 function = "qup11"; 4303 }; 4304 4305 qup_uart9_rx: qup-uart9-rx { 4306 pins = "gpio39"; 4307 function = "qup11"; 4308 }; 4309 4310 qup_uart10_cts: qup-uart10-cts { 4311 pins = "gpio40"; 4312 function = "qup12"; 4313 }; 4314 4315 qup_uart10_rts: qup-uart10-rts { 4316 pins = "gpio41"; 4317 function = "qup12"; 4318 }; 4319 4320 qup_uart10_tx: qup-uart10-tx { 4321 pins = "gpio42"; 4322 function = "qup12"; 4323 }; 4324 4325 qup_uart10_rx: qup-uart10-rx { 4326 pins = "gpio43"; 4327 function = "qup12"; 4328 }; 4329 4330 qup_uart11_cts: qup-uart11-cts { 4331 pins = "gpio44"; 4332 function = "qup13"; 4333 }; 4334 4335 qup_uart11_rts: qup-uart11-rts { 4336 pins = "gpio45"; 4337 function = "qup13"; 4338 }; 4339 4340 qup_uart11_tx: qup-uart11-tx { 4341 pins = "gpio46"; 4342 function = "qup13"; 4343 }; 4344 4345 qup_uart11_rx: qup-uart11-rx { 4346 pins = "gpio47"; 4347 function = "qup13"; 4348 }; 4349 4350 qup_uart12_cts: qup-uart12-cts { 4351 pins = "gpio48"; 4352 function = "qup14"; 4353 }; 4354 4355 qup_uart12_rts: qup-uart12-rts { 4356 pins = "gpio49"; 4357 function = "qup14"; 4358 }; 4359 4360 qup_uart12_tx: qup-uart12-tx { 4361 pins = "gpio50"; 4362 function = "qup14"; 4363 }; 4364 4365 qup_uart12_rx: qup-uart12-rx { 4366 pins = "gpio51"; 4367 function = "qup14"; 4368 }; 4369 4370 qup_uart13_cts: qup-uart13-cts { 4371 pins = "gpio52"; 4372 function = "qup15"; 4373 }; 4374 4375 qup_uart13_rts: qup-uart13-rts { 4376 pins = "gpio53"; 4377 function = "qup15"; 4378 }; 4379 4380 qup_uart13_tx: qup-uart13-tx { 4381 pins = "gpio54"; 4382 function = "qup15"; 4383 }; 4384 4385 qup_uart13_rx: qup-uart13-rx { 4386 pins = "gpio55"; 4387 function = "qup15"; 4388 }; 4389 4390 qup_uart14_cts: qup-uart14-cts { 4391 pins = "gpio56"; 4392 function = "qup16"; 4393 }; 4394 4395 qup_uart14_rts: qup-uart14-rts { 4396 pins = "gpio57"; 4397 function = "qup16"; 4398 }; 4399 4400 qup_uart14_tx: qup-uart14-tx { 4401 pins = "gpio58"; 4402 function = "qup16"; 4403 }; 4404 4405 qup_uart14_rx: qup-uart14-rx { 4406 pins = "gpio59"; 4407 function = "qup16"; 4408 }; 4409 4410 qup_uart15_cts: qup-uart15-cts { 4411 pins = "gpio60"; 4412 function = "qup17"; 4413 }; 4414 4415 qup_uart15_rts: qup-uart15-rts { 4416 pins = "gpio61"; 4417 function = "qup17"; 4418 }; 4419 4420 qup_uart15_tx: qup-uart15-tx { 4421 pins = "gpio62"; 4422 function = "qup17"; 4423 }; 4424 4425 qup_uart15_rx: qup-uart15-rx { 4426 pins = "gpio63"; 4427 function = "qup17"; 4428 }; 4429 4430 sdc1_clk: sdc1-clk { 4431 pins = "sdc1_clk"; 4432 }; 4433 4434 sdc1_cmd: sdc1-cmd { 4435 pins = "sdc1_cmd"; 4436 }; 4437 4438 sdc1_data: sdc1-data { 4439 pins = "sdc1_data"; 4440 }; 4441 4442 sdc1_rclk: sdc1-rclk { 4443 pins = "sdc1_rclk"; 4444 }; 4445 4446 sdc1_clk_sleep: sdc1-clk-sleep { 4447 pins = "sdc1_clk"; 4448 drive-strength = <2>; 4449 bias-bus-hold; 4450 }; 4451 4452 sdc1_cmd_sleep: sdc1-cmd-sleep { 4453 pins = "sdc1_cmd"; 4454 drive-strength = <2>; 4455 bias-bus-hold; 4456 }; 4457 4458 sdc1_data_sleep: sdc1-data-sleep { 4459 pins = "sdc1_data"; 4460 drive-strength = <2>; 4461 bias-bus-hold; 4462 }; 4463 4464 sdc1_rclk_sleep: sdc1-rclk-sleep { 4465 pins = "sdc1_rclk"; 4466 drive-strength = <2>; 4467 bias-bus-hold; 4468 }; 4469 4470 sdc2_clk: sdc2-clk { 4471 pins = "sdc2_clk"; 4472 }; 4473 4474 sdc2_cmd: sdc2-cmd { 4475 pins = "sdc2_cmd"; 4476 }; 4477 4478 sdc2_data: sdc2-data { 4479 pins = "sdc2_data"; 4480 }; 4481 4482 sdc2_clk_sleep: sdc2-clk-sleep { 4483 pins = "sdc2_clk"; 4484 drive-strength = <2>; 4485 bias-bus-hold; 4486 }; 4487 4488 sdc2_cmd_sleep: sdc2-cmd-sleep { 4489 pins = "sdc2_cmd"; 4490 drive-strength = <2>; 4491 bias-bus-hold; 4492 }; 4493 4494 sdc2_data_sleep: sdc2-data-sleep { 4495 pins = "sdc2_data"; 4496 drive-strength = <2>; 4497 bias-bus-hold; 4498 }; 4499 }; 4500 4501 imem@146a5000 { 4502 compatible = "qcom,sc7280-imem", "syscon"; 4503 reg = <0 0x146a5000 0 0x6000>; 4504 4505 #address-cells = <1>; 4506 #size-cells = <1>; 4507 4508 ranges = <0 0 0x146a5000 0x6000>; 4509 4510 pil-reloc@594c { 4511 compatible = "qcom,pil-reloc-info"; 4512 reg = <0x594c 0xc8>; 4513 }; 4514 }; 4515 4516 apps_smmu: iommu@15000000 { 4517 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4518 reg = <0 0x15000000 0 0x100000>; 4519 #iommu-cells = <2>; 4520 #global-interrupts = <1>; 4521 dma-coherent; 4522 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4523 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4524 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4525 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4526 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4527 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4528 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4529 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4530 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4531 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4532 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4533 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4534 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4535 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4536 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4537 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4538 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4539 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4540 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4541 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4542 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4543 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4544 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4545 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4546 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4547 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4548 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4549 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4550 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4551 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4552 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4553 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4554 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4555 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4556 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4557 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4558 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4559 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4560 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4561 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4562 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4563 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4564 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4565 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4566 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4567 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4568 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4569 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4570 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4571 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4572 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4573 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4574 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4575 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4576 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4577 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4578 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4579 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4580 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4581 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4582 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4583 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4584 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4585 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4586 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4587 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4588 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4589 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4590 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4591 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4592 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4595 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4596 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4598 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4599 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4600 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4601 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4602 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4603 }; 4604 4605 intc: interrupt-controller@17a00000 { 4606 compatible = "arm,gic-v3"; 4607 #address-cells = <2>; 4608 #size-cells = <2>; 4609 ranges; 4610 #interrupt-cells = <3>; 4611 interrupt-controller; 4612 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4613 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4614 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4615 4616 gic-its@17a40000 { 4617 compatible = "arm,gic-v3-its"; 4618 msi-controller; 4619 #msi-cells = <1>; 4620 reg = <0 0x17a40000 0 0x20000>; 4621 status = "disabled"; 4622 }; 4623 }; 4624 4625 watchdog@17c10000 { 4626 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4627 reg = <0 0x17c10000 0 0x1000>; 4628 clocks = <&sleep_clk>; 4629 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4630 }; 4631 4632 timer@17c20000 { 4633 #address-cells = <2>; 4634 #size-cells = <2>; 4635 ranges; 4636 compatible = "arm,armv7-timer-mem"; 4637 reg = <0 0x17c20000 0 0x1000>; 4638 4639 frame@17c21000 { 4640 frame-number = <0>; 4641 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4642 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4643 reg = <0 0x17c21000 0 0x1000>, 4644 <0 0x17c22000 0 0x1000>; 4645 }; 4646 4647 frame@17c23000 { 4648 frame-number = <1>; 4649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4650 reg = <0 0x17c23000 0 0x1000>; 4651 status = "disabled"; 4652 }; 4653 4654 frame@17c25000 { 4655 frame-number = <2>; 4656 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4657 reg = <0 0x17c25000 0 0x1000>; 4658 status = "disabled"; 4659 }; 4660 4661 frame@17c27000 { 4662 frame-number = <3>; 4663 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4664 reg = <0 0x17c27000 0 0x1000>; 4665 status = "disabled"; 4666 }; 4667 4668 frame@17c29000 { 4669 frame-number = <4>; 4670 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4671 reg = <0 0x17c29000 0 0x1000>; 4672 status = "disabled"; 4673 }; 4674 4675 frame@17c2b000 { 4676 frame-number = <5>; 4677 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4678 reg = <0 0x17c2b000 0 0x1000>; 4679 status = "disabled"; 4680 }; 4681 4682 frame@17c2d000 { 4683 frame-number = <6>; 4684 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4685 reg = <0 0x17c2d000 0 0x1000>; 4686 status = "disabled"; 4687 }; 4688 }; 4689 4690 apps_rsc: rsc@18200000 { 4691 compatible = "qcom,rpmh-rsc"; 4692 reg = <0 0x18200000 0 0x10000>, 4693 <0 0x18210000 0 0x10000>, 4694 <0 0x18220000 0 0x10000>; 4695 reg-names = "drv-0", "drv-1", "drv-2"; 4696 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4697 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4698 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4699 qcom,tcs-offset = <0xd00>; 4700 qcom,drv-id = <2>; 4701 qcom,tcs-config = <ACTIVE_TCS 2>, 4702 <SLEEP_TCS 3>, 4703 <WAKE_TCS 3>, 4704 <CONTROL_TCS 1>; 4705 4706 apps_bcm_voter: bcm-voter { 4707 compatible = "qcom,bcm-voter"; 4708 }; 4709 4710 rpmhpd: power-controller { 4711 compatible = "qcom,sc7280-rpmhpd"; 4712 #power-domain-cells = <1>; 4713 operating-points-v2 = <&rpmhpd_opp_table>; 4714 4715 rpmhpd_opp_table: opp-table { 4716 compatible = "operating-points-v2"; 4717 4718 rpmhpd_opp_ret: opp1 { 4719 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4720 }; 4721 4722 rpmhpd_opp_low_svs: opp2 { 4723 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4724 }; 4725 4726 rpmhpd_opp_svs: opp3 { 4727 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4728 }; 4729 4730 rpmhpd_opp_svs_l1: opp4 { 4731 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4732 }; 4733 4734 rpmhpd_opp_svs_l2: opp5 { 4735 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4736 }; 4737 4738 rpmhpd_opp_nom: opp6 { 4739 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4740 }; 4741 4742 rpmhpd_opp_nom_l1: opp7 { 4743 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4744 }; 4745 4746 rpmhpd_opp_turbo: opp8 { 4747 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4748 }; 4749 4750 rpmhpd_opp_turbo_l1: opp9 { 4751 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4752 }; 4753 }; 4754 }; 4755 4756 rpmhcc: clock-controller { 4757 compatible = "qcom,sc7280-rpmh-clk"; 4758 clocks = <&xo_board>; 4759 clock-names = "xo"; 4760 #clock-cells = <1>; 4761 }; 4762 }; 4763 4764 epss_l3: interconnect@18590000 { 4765 compatible = "qcom,sc7280-epss-l3"; 4766 reg = <0 0x18590000 0 0x1000>; 4767 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4768 clock-names = "xo", "alternate"; 4769 #interconnect-cells = <1>; 4770 }; 4771 4772 cpufreq_hw: cpufreq@18591000 { 4773 compatible = "qcom,cpufreq-epss"; 4774 reg = <0 0x18591000 0 0x1000>, 4775 <0 0x18592000 0 0x1000>, 4776 <0 0x18593000 0 0x1000>; 4777 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4778 clock-names = "xo", "alternate"; 4779 #freq-domain-cells = <1>; 4780 }; 4781 }; 4782 4783 thermal_zones: thermal-zones { 4784 cpu0-thermal { 4785 polling-delay-passive = <250>; 4786 polling-delay = <0>; 4787 4788 thermal-sensors = <&tsens0 1>; 4789 4790 trips { 4791 cpu0_alert0: trip-point0 { 4792 temperature = <90000>; 4793 hysteresis = <2000>; 4794 type = "passive"; 4795 }; 4796 4797 cpu0_alert1: trip-point1 { 4798 temperature = <95000>; 4799 hysteresis = <2000>; 4800 type = "passive"; 4801 }; 4802 4803 cpu0_crit: cpu-crit { 4804 temperature = <110000>; 4805 hysteresis = <0>; 4806 type = "critical"; 4807 }; 4808 }; 4809 4810 cooling-maps { 4811 map0 { 4812 trip = <&cpu0_alert0>; 4813 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4817 }; 4818 map1 { 4819 trip = <&cpu0_alert1>; 4820 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4822 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4823 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4824 }; 4825 }; 4826 }; 4827 4828 cpu1-thermal { 4829 polling-delay-passive = <250>; 4830 polling-delay = <0>; 4831 4832 thermal-sensors = <&tsens0 2>; 4833 4834 trips { 4835 cpu1_alert0: trip-point0 { 4836 temperature = <90000>; 4837 hysteresis = <2000>; 4838 type = "passive"; 4839 }; 4840 4841 cpu1_alert1: trip-point1 { 4842 temperature = <95000>; 4843 hysteresis = <2000>; 4844 type = "passive"; 4845 }; 4846 4847 cpu1_crit: cpu-crit { 4848 temperature = <110000>; 4849 hysteresis = <0>; 4850 type = "critical"; 4851 }; 4852 }; 4853 4854 cooling-maps { 4855 map0 { 4856 trip = <&cpu1_alert0>; 4857 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4859 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4860 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4861 }; 4862 map1 { 4863 trip = <&cpu1_alert1>; 4864 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4865 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4866 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4867 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4868 }; 4869 }; 4870 }; 4871 4872 cpu2-thermal { 4873 polling-delay-passive = <250>; 4874 polling-delay = <0>; 4875 4876 thermal-sensors = <&tsens0 3>; 4877 4878 trips { 4879 cpu2_alert0: trip-point0 { 4880 temperature = <90000>; 4881 hysteresis = <2000>; 4882 type = "passive"; 4883 }; 4884 4885 cpu2_alert1: trip-point1 { 4886 temperature = <95000>; 4887 hysteresis = <2000>; 4888 type = "passive"; 4889 }; 4890 4891 cpu2_crit: cpu-crit { 4892 temperature = <110000>; 4893 hysteresis = <0>; 4894 type = "critical"; 4895 }; 4896 }; 4897 4898 cooling-maps { 4899 map0 { 4900 trip = <&cpu2_alert0>; 4901 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4902 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4903 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4904 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4905 }; 4906 map1 { 4907 trip = <&cpu2_alert1>; 4908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4909 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4910 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4911 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4912 }; 4913 }; 4914 }; 4915 4916 cpu3-thermal { 4917 polling-delay-passive = <250>; 4918 polling-delay = <0>; 4919 4920 thermal-sensors = <&tsens0 4>; 4921 4922 trips { 4923 cpu3_alert0: trip-point0 { 4924 temperature = <90000>; 4925 hysteresis = <2000>; 4926 type = "passive"; 4927 }; 4928 4929 cpu3_alert1: trip-point1 { 4930 temperature = <95000>; 4931 hysteresis = <2000>; 4932 type = "passive"; 4933 }; 4934 4935 cpu3_crit: cpu-crit { 4936 temperature = <110000>; 4937 hysteresis = <0>; 4938 type = "critical"; 4939 }; 4940 }; 4941 4942 cooling-maps { 4943 map0 { 4944 trip = <&cpu3_alert0>; 4945 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4946 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4947 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4948 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4949 }; 4950 map1 { 4951 trip = <&cpu3_alert1>; 4952 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4953 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4954 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4955 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4956 }; 4957 }; 4958 }; 4959 4960 cpu4-thermal { 4961 polling-delay-passive = <250>; 4962 polling-delay = <0>; 4963 4964 thermal-sensors = <&tsens0 7>; 4965 4966 trips { 4967 cpu4_alert0: trip-point0 { 4968 temperature = <90000>; 4969 hysteresis = <2000>; 4970 type = "passive"; 4971 }; 4972 4973 cpu4_alert1: trip-point1 { 4974 temperature = <95000>; 4975 hysteresis = <2000>; 4976 type = "passive"; 4977 }; 4978 4979 cpu4_crit: cpu-crit { 4980 temperature = <110000>; 4981 hysteresis = <0>; 4982 type = "critical"; 4983 }; 4984 }; 4985 4986 cooling-maps { 4987 map0 { 4988 trip = <&cpu4_alert0>; 4989 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4990 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4991 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4992 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4993 }; 4994 map1 { 4995 trip = <&cpu4_alert1>; 4996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4997 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4998 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5000 }; 5001 }; 5002 }; 5003 5004 cpu5-thermal { 5005 polling-delay-passive = <250>; 5006 polling-delay = <0>; 5007 5008 thermal-sensors = <&tsens0 8>; 5009 5010 trips { 5011 cpu5_alert0: trip-point0 { 5012 temperature = <90000>; 5013 hysteresis = <2000>; 5014 type = "passive"; 5015 }; 5016 5017 cpu5_alert1: trip-point1 { 5018 temperature = <95000>; 5019 hysteresis = <2000>; 5020 type = "passive"; 5021 }; 5022 5023 cpu5_crit: cpu-crit { 5024 temperature = <110000>; 5025 hysteresis = <0>; 5026 type = "critical"; 5027 }; 5028 }; 5029 5030 cooling-maps { 5031 map0 { 5032 trip = <&cpu5_alert0>; 5033 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5034 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5035 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5036 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5037 }; 5038 map1 { 5039 trip = <&cpu5_alert1>; 5040 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5041 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5042 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5043 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5044 }; 5045 }; 5046 }; 5047 5048 cpu6-thermal { 5049 polling-delay-passive = <250>; 5050 polling-delay = <0>; 5051 5052 thermal-sensors = <&tsens0 9>; 5053 5054 trips { 5055 cpu6_alert0: trip-point0 { 5056 temperature = <90000>; 5057 hysteresis = <2000>; 5058 type = "passive"; 5059 }; 5060 5061 cpu6_alert1: trip-point1 { 5062 temperature = <95000>; 5063 hysteresis = <2000>; 5064 type = "passive"; 5065 }; 5066 5067 cpu6_crit: cpu-crit { 5068 temperature = <110000>; 5069 hysteresis = <0>; 5070 type = "critical"; 5071 }; 5072 }; 5073 5074 cooling-maps { 5075 map0 { 5076 trip = <&cpu6_alert0>; 5077 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5078 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5079 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5080 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5081 }; 5082 map1 { 5083 trip = <&cpu6_alert1>; 5084 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5085 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5086 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5087 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5088 }; 5089 }; 5090 }; 5091 5092 cpu7-thermal { 5093 polling-delay-passive = <250>; 5094 polling-delay = <0>; 5095 5096 thermal-sensors = <&tsens0 10>; 5097 5098 trips { 5099 cpu7_alert0: trip-point0 { 5100 temperature = <90000>; 5101 hysteresis = <2000>; 5102 type = "passive"; 5103 }; 5104 5105 cpu7_alert1: trip-point1 { 5106 temperature = <95000>; 5107 hysteresis = <2000>; 5108 type = "passive"; 5109 }; 5110 5111 cpu7_crit: cpu-crit { 5112 temperature = <110000>; 5113 hysteresis = <0>; 5114 type = "critical"; 5115 }; 5116 }; 5117 5118 cooling-maps { 5119 map0 { 5120 trip = <&cpu7_alert0>; 5121 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5122 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5123 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5124 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5125 }; 5126 map1 { 5127 trip = <&cpu7_alert1>; 5128 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5129 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5130 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5131 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5132 }; 5133 }; 5134 }; 5135 5136 cpu8-thermal { 5137 polling-delay-passive = <250>; 5138 polling-delay = <0>; 5139 5140 thermal-sensors = <&tsens0 11>; 5141 5142 trips { 5143 cpu8_alert0: trip-point0 { 5144 temperature = <90000>; 5145 hysteresis = <2000>; 5146 type = "passive"; 5147 }; 5148 5149 cpu8_alert1: trip-point1 { 5150 temperature = <95000>; 5151 hysteresis = <2000>; 5152 type = "passive"; 5153 }; 5154 5155 cpu8_crit: cpu-crit { 5156 temperature = <110000>; 5157 hysteresis = <0>; 5158 type = "critical"; 5159 }; 5160 }; 5161 5162 cooling-maps { 5163 map0 { 5164 trip = <&cpu8_alert0>; 5165 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5166 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5167 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5168 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5169 }; 5170 map1 { 5171 trip = <&cpu8_alert1>; 5172 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5173 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5174 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5175 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5176 }; 5177 }; 5178 }; 5179 5180 cpu9-thermal { 5181 polling-delay-passive = <250>; 5182 polling-delay = <0>; 5183 5184 thermal-sensors = <&tsens0 12>; 5185 5186 trips { 5187 cpu9_alert0: trip-point0 { 5188 temperature = <90000>; 5189 hysteresis = <2000>; 5190 type = "passive"; 5191 }; 5192 5193 cpu9_alert1: trip-point1 { 5194 temperature = <95000>; 5195 hysteresis = <2000>; 5196 type = "passive"; 5197 }; 5198 5199 cpu9_crit: cpu-crit { 5200 temperature = <110000>; 5201 hysteresis = <0>; 5202 type = "critical"; 5203 }; 5204 }; 5205 5206 cooling-maps { 5207 map0 { 5208 trip = <&cpu9_alert0>; 5209 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5210 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5211 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5212 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5213 }; 5214 map1 { 5215 trip = <&cpu9_alert1>; 5216 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5217 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5218 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5219 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5220 }; 5221 }; 5222 }; 5223 5224 cpu10-thermal { 5225 polling-delay-passive = <250>; 5226 polling-delay = <0>; 5227 5228 thermal-sensors = <&tsens0 13>; 5229 5230 trips { 5231 cpu10_alert0: trip-point0 { 5232 temperature = <90000>; 5233 hysteresis = <2000>; 5234 type = "passive"; 5235 }; 5236 5237 cpu10_alert1: trip-point1 { 5238 temperature = <95000>; 5239 hysteresis = <2000>; 5240 type = "passive"; 5241 }; 5242 5243 cpu10_crit: cpu-crit { 5244 temperature = <110000>; 5245 hysteresis = <0>; 5246 type = "critical"; 5247 }; 5248 }; 5249 5250 cooling-maps { 5251 map0 { 5252 trip = <&cpu10_alert0>; 5253 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5254 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5255 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5256 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5257 }; 5258 map1 { 5259 trip = <&cpu10_alert1>; 5260 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5261 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5262 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5263 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5264 }; 5265 }; 5266 }; 5267 5268 cpu11-thermal { 5269 polling-delay-passive = <250>; 5270 polling-delay = <0>; 5271 5272 thermal-sensors = <&tsens0 14>; 5273 5274 trips { 5275 cpu11_alert0: trip-point0 { 5276 temperature = <90000>; 5277 hysteresis = <2000>; 5278 type = "passive"; 5279 }; 5280 5281 cpu11_alert1: trip-point1 { 5282 temperature = <95000>; 5283 hysteresis = <2000>; 5284 type = "passive"; 5285 }; 5286 5287 cpu11_crit: cpu-crit { 5288 temperature = <110000>; 5289 hysteresis = <0>; 5290 type = "critical"; 5291 }; 5292 }; 5293 5294 cooling-maps { 5295 map0 { 5296 trip = <&cpu11_alert0>; 5297 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5298 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5299 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5300 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5301 }; 5302 map1 { 5303 trip = <&cpu11_alert1>; 5304 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5305 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5306 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5307 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5308 }; 5309 }; 5310 }; 5311 5312 aoss0-thermal { 5313 polling-delay-passive = <0>; 5314 polling-delay = <0>; 5315 5316 thermal-sensors = <&tsens0 0>; 5317 5318 trips { 5319 aoss0_alert0: trip-point0 { 5320 temperature = <90000>; 5321 hysteresis = <2000>; 5322 type = "hot"; 5323 }; 5324 5325 aoss0_crit: aoss0-crit { 5326 temperature = <110000>; 5327 hysteresis = <0>; 5328 type = "critical"; 5329 }; 5330 }; 5331 }; 5332 5333 aoss1-thermal { 5334 polling-delay-passive = <0>; 5335 polling-delay = <0>; 5336 5337 thermal-sensors = <&tsens1 0>; 5338 5339 trips { 5340 aoss1_alert0: trip-point0 { 5341 temperature = <90000>; 5342 hysteresis = <2000>; 5343 type = "hot"; 5344 }; 5345 5346 aoss1_crit: aoss1-crit { 5347 temperature = <110000>; 5348 hysteresis = <0>; 5349 type = "critical"; 5350 }; 5351 }; 5352 }; 5353 5354 cpuss0-thermal { 5355 polling-delay-passive = <0>; 5356 polling-delay = <0>; 5357 5358 thermal-sensors = <&tsens0 5>; 5359 5360 trips { 5361 cpuss0_alert0: trip-point0 { 5362 temperature = <90000>; 5363 hysteresis = <2000>; 5364 type = "hot"; 5365 }; 5366 cpuss0_crit: cluster0-crit { 5367 temperature = <110000>; 5368 hysteresis = <0>; 5369 type = "critical"; 5370 }; 5371 }; 5372 }; 5373 5374 cpuss1-thermal { 5375 polling-delay-passive = <0>; 5376 polling-delay = <0>; 5377 5378 thermal-sensors = <&tsens0 6>; 5379 5380 trips { 5381 cpuss1_alert0: trip-point0 { 5382 temperature = <90000>; 5383 hysteresis = <2000>; 5384 type = "hot"; 5385 }; 5386 cpuss1_crit: cluster0-crit { 5387 temperature = <110000>; 5388 hysteresis = <0>; 5389 type = "critical"; 5390 }; 5391 }; 5392 }; 5393 5394 gpuss0-thermal { 5395 polling-delay-passive = <100>; 5396 polling-delay = <0>; 5397 5398 thermal-sensors = <&tsens1 1>; 5399 5400 trips { 5401 gpuss0_alert0: trip-point0 { 5402 temperature = <95000>; 5403 hysteresis = <2000>; 5404 type = "passive"; 5405 }; 5406 5407 gpuss0_crit: gpuss0-crit { 5408 temperature = <110000>; 5409 hysteresis = <0>; 5410 type = "critical"; 5411 }; 5412 }; 5413 5414 cooling-maps { 5415 map0 { 5416 trip = <&gpuss0_alert0>; 5417 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5418 }; 5419 }; 5420 }; 5421 5422 gpuss1-thermal { 5423 polling-delay-passive = <100>; 5424 polling-delay = <0>; 5425 5426 thermal-sensors = <&tsens1 2>; 5427 5428 trips { 5429 gpuss1_alert0: trip-point0 { 5430 temperature = <95000>; 5431 hysteresis = <2000>; 5432 type = "passive"; 5433 }; 5434 5435 gpuss1_crit: gpuss1-crit { 5436 temperature = <110000>; 5437 hysteresis = <0>; 5438 type = "critical"; 5439 }; 5440 }; 5441 5442 cooling-maps { 5443 map0 { 5444 trip = <&gpuss1_alert0>; 5445 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5446 }; 5447 }; 5448 }; 5449 5450 nspss0-thermal { 5451 polling-delay-passive = <0>; 5452 polling-delay = <0>; 5453 5454 thermal-sensors = <&tsens1 3>; 5455 5456 trips { 5457 nspss0_alert0: trip-point0 { 5458 temperature = <90000>; 5459 hysteresis = <2000>; 5460 type = "hot"; 5461 }; 5462 5463 nspss0_crit: nspss0-crit { 5464 temperature = <110000>; 5465 hysteresis = <0>; 5466 type = "critical"; 5467 }; 5468 }; 5469 }; 5470 5471 nspss1-thermal { 5472 polling-delay-passive = <0>; 5473 polling-delay = <0>; 5474 5475 thermal-sensors = <&tsens1 4>; 5476 5477 trips { 5478 nspss1_alert0: trip-point0 { 5479 temperature = <90000>; 5480 hysteresis = <2000>; 5481 type = "hot"; 5482 }; 5483 5484 nspss1_crit: nspss1-crit { 5485 temperature = <110000>; 5486 hysteresis = <0>; 5487 type = "critical"; 5488 }; 5489 }; 5490 }; 5491 5492 video-thermal { 5493 polling-delay-passive = <0>; 5494 polling-delay = <0>; 5495 5496 thermal-sensors = <&tsens1 5>; 5497 5498 trips { 5499 video_alert0: trip-point0 { 5500 temperature = <90000>; 5501 hysteresis = <2000>; 5502 type = "hot"; 5503 }; 5504 5505 video_crit: video-crit { 5506 temperature = <110000>; 5507 hysteresis = <0>; 5508 type = "critical"; 5509 }; 5510 }; 5511 }; 5512 5513 ddr-thermal { 5514 polling-delay-passive = <0>; 5515 polling-delay = <0>; 5516 5517 thermal-sensors = <&tsens1 6>; 5518 5519 trips { 5520 ddr_alert0: trip-point0 { 5521 temperature = <90000>; 5522 hysteresis = <2000>; 5523 type = "hot"; 5524 }; 5525 5526 ddr_crit: ddr-crit { 5527 temperature = <110000>; 5528 hysteresis = <0>; 5529 type = "critical"; 5530 }; 5531 }; 5532 }; 5533 5534 mdmss0-thermal { 5535 polling-delay-passive = <0>; 5536 polling-delay = <0>; 5537 5538 thermal-sensors = <&tsens1 7>; 5539 5540 trips { 5541 mdmss0_alert0: trip-point0 { 5542 temperature = <90000>; 5543 hysteresis = <2000>; 5544 type = "hot"; 5545 }; 5546 5547 mdmss0_crit: mdmss0-crit { 5548 temperature = <110000>; 5549 hysteresis = <0>; 5550 type = "critical"; 5551 }; 5552 }; 5553 }; 5554 5555 mdmss1-thermal { 5556 polling-delay-passive = <0>; 5557 polling-delay = <0>; 5558 5559 thermal-sensors = <&tsens1 8>; 5560 5561 trips { 5562 mdmss1_alert0: trip-point0 { 5563 temperature = <90000>; 5564 hysteresis = <2000>; 5565 type = "hot"; 5566 }; 5567 5568 mdmss1_crit: mdmss1-crit { 5569 temperature = <110000>; 5570 hysteresis = <0>; 5571 type = "critical"; 5572 }; 5573 }; 5574 }; 5575 5576 mdmss2-thermal { 5577 polling-delay-passive = <0>; 5578 polling-delay = <0>; 5579 5580 thermal-sensors = <&tsens1 9>; 5581 5582 trips { 5583 mdmss2_alert0: trip-point0 { 5584 temperature = <90000>; 5585 hysteresis = <2000>; 5586 type = "hot"; 5587 }; 5588 5589 mdmss2_crit: mdmss2-crit { 5590 temperature = <110000>; 5591 hysteresis = <0>; 5592 type = "critical"; 5593 }; 5594 }; 5595 }; 5596 5597 mdmss3-thermal { 5598 polling-delay-passive = <0>; 5599 polling-delay = <0>; 5600 5601 thermal-sensors = <&tsens1 10>; 5602 5603 trips { 5604 mdmss3_alert0: trip-point0 { 5605 temperature = <90000>; 5606 hysteresis = <2000>; 5607 type = "hot"; 5608 }; 5609 5610 mdmss3_crit: mdmss3-crit { 5611 temperature = <110000>; 5612 hysteresis = <0>; 5613 type = "critical"; 5614 }; 5615 }; 5616 }; 5617 5618 camera0-thermal { 5619 polling-delay-passive = <0>; 5620 polling-delay = <0>; 5621 5622 thermal-sensors = <&tsens1 11>; 5623 5624 trips { 5625 camera0_alert0: trip-point0 { 5626 temperature = <90000>; 5627 hysteresis = <2000>; 5628 type = "hot"; 5629 }; 5630 5631 camera0_crit: camera0-crit { 5632 temperature = <110000>; 5633 hysteresis = <0>; 5634 type = "critical"; 5635 }; 5636 }; 5637 }; 5638 }; 5639 5640 timer { 5641 compatible = "arm,armv8-timer"; 5642 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5643 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5644 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5645 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5646 }; 5647}; 5648