1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 aop_mem: memory@80800000 { 56 reg = <0x0 0x80800000 0x0 0x60000>; 57 no-map; 58 }; 59 60 aop_cmd_db_mem: memory@80860000 { 61 reg = <0x0 0x80860000 0x0 0x20000>; 62 compatible = "qcom,cmd-db"; 63 no-map; 64 }; 65 66 smem_mem: memory@80900000 { 67 reg = <0x0 0x80900000 0x0 0x200000>; 68 no-map; 69 }; 70 71 cpucp_mem: memory@80b00000 { 72 no-map; 73 reg = <0x0 0x80b00000 0x0 0x100000>; 74 }; 75 76 ipa_fw_mem: memory@8b700000 { 77 reg = <0 0x8b700000 0 0x10000>; 78 no-map; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <2>; 84 #size-cells = <0>; 85 86 CPU0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,kryo"; 89 reg = <0x0 0x0>; 90 enable-method = "psci"; 91 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 92 &LITTLE_CPU_SLEEP_1 93 &CLUSTER_SLEEP_0>; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_0: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 L3_0: l3-cache { 101 compatible = "cache"; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,kryo"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_100>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "arm,kryo"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_200>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_200: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x300>; 144 enable-method = "psci"; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 146 &LITTLE_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_300>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x400>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "arm,kryo"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 cpu-idle-states = <&BIG_CPU_SLEEP_0 180 &BIG_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,kryo"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 197 &BIG_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 cpu-idle-states = <&BIG_CPU_SLEEP_0 214 &BIG_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-power-down"; 267 arm,psci-suspend-param = <0x40000003>; 268 entry-latency-us = <549>; 269 exit-latency-us = <901>; 270 min-residency-us = <1774>; 271 local-timer-stop; 272 }; 273 274 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-down"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <702>; 279 exit-latency-us = <915>; 280 min-residency-us = <4001>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-power-down"; 287 arm,psci-suspend-param = <0x40000003>; 288 entry-latency-us = <523>; 289 exit-latency-us = <1244>; 290 min-residency-us = <2207>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "big-rail-power-down"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <526>; 299 exit-latency-us = <1854>; 300 min-residency-us = <5555>; 301 local-timer-stop; 302 }; 303 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "cluster-power-down"; 307 arm,psci-suspend-param = <0x40003444>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9926>; 311 local-timer-stop; 312 }; 313 }; 314 }; 315 316 memory@80000000 { 317 device_type = "memory"; 318 /* We expect the bootloader to fill in the size */ 319 reg = <0 0x80000000 0 0>; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-sc7280", "qcom,scm"; 325 }; 326 }; 327 328 clk_virt: interconnect { 329 compatible = "qcom,sc7280-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 smem { 335 compatible = "qcom,smem"; 336 memory-region = <&smem_mem>; 337 hwlocks = <&tcsr_mutex 3>; 338 }; 339 340 smp2p-adsp { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <443>, <429>; 343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P 345 IRQ_TYPE_EDGE_RISING>; 346 mboxes = <&ipcc IPCC_CLIENT_LPASS 347 IPCC_MPROC_SIGNAL_SMP2P>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <2>; 351 352 adsp_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 adsp_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 }; 363 364 smp2p-cdsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <94>, <432>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_CDSP 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <5>; 375 376 cdsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 cdsp_smp2p_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-mpss { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <435>, <428>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_MPSS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <1>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 ipa_smp2p_out: ipa-ap-to-modem { 412 qcom,entry-name = "ipa"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 ipa_smp2p_in: ipa-modem-to-ap { 417 qcom,entry-name = "ipa"; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smp2p-wpss { 424 compatible = "qcom,smp2p"; 425 qcom,smem = <617>, <616>; 426 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P 428 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&ipcc IPCC_CLIENT_WPSS 430 IPCC_MPROC_SIGNAL_SMP2P>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <13>; 434 435 wpss_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 wpss_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 }; 446 447 pmu { 448 compatible = "arm,armv8-pmuv3"; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 450 }; 451 452 psci { 453 compatible = "arm,psci-1.0"; 454 method = "smc"; 455 }; 456 457 qspi_opp_table: qspi-opp-table { 458 compatible = "operating-points-v2"; 459 460 opp-75000000 { 461 opp-hz = /bits/ 64 <75000000>; 462 required-opps = <&rpmhpd_opp_low_svs>; 463 }; 464 465 opp-150000000 { 466 opp-hz = /bits/ 64 <150000000>; 467 required-opps = <&rpmhpd_opp_svs>; 468 }; 469 470 opp-300000000 { 471 opp-hz = /bits/ 64 <300000000>; 472 required-opps = <&rpmhpd_opp_nom>; 473 }; 474 }; 475 476 qup_opp_table: qup-opp-table { 477 compatible = "operating-points-v2"; 478 479 opp-75000000 { 480 opp-hz = /bits/ 64 <75000000>; 481 required-opps = <&rpmhpd_opp_low_svs>; 482 }; 483 484 opp-100000000 { 485 opp-hz = /bits/ 64 <100000000>; 486 required-opps = <&rpmhpd_opp_svs>; 487 }; 488 489 opp-128000000 { 490 opp-hz = /bits/ 64 <128000000>; 491 required-opps = <&rpmhpd_opp_nom>; 492 }; 493 }; 494 495 soc: soc@0 { 496 #address-cells = <2>; 497 #size-cells = <2>; 498 ranges = <0 0 0 0 0x10 0>; 499 dma-ranges = <0 0 0 0 0x10 0>; 500 compatible = "simple-bus"; 501 502 gcc: clock-controller@100000 { 503 compatible = "qcom,gcc-sc7280"; 504 reg = <0 0x00100000 0 0x1f0000>; 505 clocks = <&rpmhcc RPMH_CXO_CLK>, 506 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 507 <0>, <0>, <0>, <0>, <0>, <0>; 508 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 509 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 510 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 511 "ufs_phy_tx_symbol_0_clk", 512 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 513 #clock-cells = <1>; 514 #reset-cells = <1>; 515 #power-domain-cells = <1>; 516 }; 517 518 ipcc: mailbox@408000 { 519 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 520 reg = <0 0x00408000 0 0x1000>; 521 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-controller; 523 #interrupt-cells = <3>; 524 #mbox-cells = <2>; 525 }; 526 527 qfprom: efuse@784000 { 528 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 529 reg = <0 0x00784000 0 0xa20>, 530 <0 0x00780000 0 0xa20>, 531 <0 0x00782000 0 0x120>, 532 <0 0x00786000 0 0x1fff>; 533 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 534 clock-names = "core"; 535 power-domains = <&rpmhpd SC7280_MX>; 536 #address-cells = <1>; 537 #size-cells = <1>; 538 }; 539 540 sdhc_1: sdhci@7c4000 { 541 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 542 status = "disabled"; 543 544 reg = <0 0x007c4000 0 0x1000>, 545 <0 0x007c5000 0 0x1000>; 546 reg-names = "hc", "cqhci"; 547 548 iommus = <&apps_smmu 0xc0 0x0>; 549 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "hc_irq", "pwr_irq"; 552 553 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 554 <&gcc GCC_SDCC1_AHB_CLK>, 555 <&rpmhcc RPMH_CXO_CLK>; 556 clock-names = "core", "iface", "xo"; 557 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 558 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 559 interconnect-names = "sdhc-ddr","cpu-sdhc"; 560 power-domains = <&rpmhpd SC7280_CX>; 561 operating-points-v2 = <&sdhc1_opp_table>; 562 563 bus-width = <8>; 564 supports-cqe; 565 566 qcom,dll-config = <0x0007642c>; 567 qcom,ddr-config = <0x80040868>; 568 569 mmc-ddr-1_8v; 570 mmc-hs200-1_8v; 571 mmc-hs400-1_8v; 572 mmc-hs400-enhanced-strobe; 573 574 sdhc1_opp_table: opp-table { 575 compatible = "operating-points-v2"; 576 577 opp-100000000 { 578 opp-hz = /bits/ 64 <100000000>; 579 required-opps = <&rpmhpd_opp_low_svs>; 580 opp-peak-kBps = <1800000 400000>; 581 opp-avg-kBps = <100000 0>; 582 }; 583 584 opp-384000000 { 585 opp-hz = /bits/ 64 <384000000>; 586 required-opps = <&rpmhpd_opp_nom>; 587 opp-peak-kBps = <5400000 1600000>; 588 opp-avg-kBps = <390000 0>; 589 }; 590 }; 591 592 }; 593 594 qupv3_id_0: geniqup@9c0000 { 595 compatible = "qcom,geni-se-qup"; 596 reg = <0 0x009c0000 0 0x2000>; 597 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 598 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 599 clock-names = "m-ahb", "s-ahb"; 600 #address-cells = <2>; 601 #size-cells = <2>; 602 ranges; 603 iommus = <&apps_smmu 0x123 0x0>; 604 status = "disabled"; 605 606 i2c0: i2c@980000 { 607 compatible = "qcom,geni-i2c"; 608 reg = <0 0x00980000 0 0x4000>; 609 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 610 clock-names = "se"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&qup_i2c0_data_clk>; 613 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 617 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 618 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 619 interconnect-names = "qup-core", "qup-config", 620 "qup-memory"; 621 status = "disabled"; 622 }; 623 624 spi0: spi@980000 { 625 compatible = "qcom,geni-spi"; 626 reg = <0 0x00980000 0 0x4000>; 627 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 628 clock-names = "se"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 631 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 power-domains = <&rpmhpd SC7280_CX>; 635 operating-points-v2 = <&qup_opp_table>; 636 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 638 interconnect-names = "qup-core", "qup-config"; 639 status = "disabled"; 640 }; 641 642 uart0: serial@980000 { 643 compatible = "qcom,geni-uart"; 644 reg = <0 0x00980000 0 0x4000>; 645 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 646 clock-names = "se"; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 649 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 650 power-domains = <&rpmhpd SC7280_CX>; 651 operating-points-v2 = <&qup_opp_table>; 652 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 654 interconnect-names = "qup-core", "qup-config"; 655 status = "disabled"; 656 }; 657 658 i2c1: i2c@984000 { 659 compatible = "qcom,geni-i2c"; 660 reg = <0 0x00984000 0 0x4000>; 661 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 662 clock-names = "se"; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&qup_i2c1_data_clk>; 665 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 669 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 670 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 671 interconnect-names = "qup-core", "qup-config", 672 "qup-memory"; 673 status = "disabled"; 674 }; 675 676 spi1: spi@984000 { 677 compatible = "qcom,geni-spi"; 678 reg = <0 0x00984000 0 0x4000>; 679 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 680 clock-names = "se"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 683 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 power-domains = <&rpmhpd SC7280_CX>; 687 operating-points-v2 = <&qup_opp_table>; 688 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 689 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 690 interconnect-names = "qup-core", "qup-config"; 691 status = "disabled"; 692 }; 693 694 uart1: serial@984000 { 695 compatible = "qcom,geni-uart"; 696 reg = <0 0x00984000 0 0x4000>; 697 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 698 clock-names = "se"; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 701 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 702 power-domains = <&rpmhpd SC7280_CX>; 703 operating-points-v2 = <&qup_opp_table>; 704 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 705 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 706 interconnect-names = "qup-core", "qup-config"; 707 status = "disabled"; 708 }; 709 710 i2c2: i2c@988000 { 711 compatible = "qcom,geni-i2c"; 712 reg = <0 0x00988000 0 0x4000>; 713 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 714 clock-names = "se"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&qup_i2c2_data_clk>; 717 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 721 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 722 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 723 interconnect-names = "qup-core", "qup-config", 724 "qup-memory"; 725 status = "disabled"; 726 }; 727 728 spi2: spi@988000 { 729 compatible = "qcom,geni-spi"; 730 reg = <0 0x00988000 0 0x4000>; 731 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 732 clock-names = "se"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 735 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 power-domains = <&rpmhpd SC7280_CX>; 739 operating-points-v2 = <&qup_opp_table>; 740 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 741 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 742 interconnect-names = "qup-core", "qup-config"; 743 status = "disabled"; 744 }; 745 746 uart2: serial@988000 { 747 compatible = "qcom,geni-uart"; 748 reg = <0 0x00988000 0 0x4000>; 749 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 750 clock-names = "se"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 753 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 754 power-domains = <&rpmhpd SC7280_CX>; 755 operating-points-v2 = <&qup_opp_table>; 756 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 758 interconnect-names = "qup-core", "qup-config"; 759 status = "disabled"; 760 }; 761 762 i2c3: i2c@98c000 { 763 compatible = "qcom,geni-i2c"; 764 reg = <0 0x0098c000 0 0x4000>; 765 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 766 clock-names = "se"; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&qup_i2c3_data_clk>; 769 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 773 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 774 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 775 interconnect-names = "qup-core", "qup-config", 776 "qup-memory"; 777 status = "disabled"; 778 }; 779 780 spi3: spi@98c000 { 781 compatible = "qcom,geni-spi"; 782 reg = <0 0x0098c000 0 0x4000>; 783 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 784 clock-names = "se"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 787 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 power-domains = <&rpmhpd SC7280_CX>; 791 operating-points-v2 = <&qup_opp_table>; 792 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 793 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 794 interconnect-names = "qup-core", "qup-config"; 795 status = "disabled"; 796 }; 797 798 uart3: serial@98c000 { 799 compatible = "qcom,geni-uart"; 800 reg = <0 0x0098c000 0 0x4000>; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 802 clock-names = "se"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 805 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 806 power-domains = <&rpmhpd SC7280_CX>; 807 operating-points-v2 = <&qup_opp_table>; 808 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 809 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 810 interconnect-names = "qup-core", "qup-config"; 811 status = "disabled"; 812 }; 813 814 i2c4: i2c@990000 { 815 compatible = "qcom,geni-i2c"; 816 reg = <0 0x00990000 0 0x4000>; 817 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 818 clock-names = "se"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&qup_i2c4_data_clk>; 821 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 825 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 826 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 827 interconnect-names = "qup-core", "qup-config", 828 "qup-memory"; 829 status = "disabled"; 830 }; 831 832 spi4: spi@990000 { 833 compatible = "qcom,geni-spi"; 834 reg = <0 0x00990000 0 0x4000>; 835 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 836 clock-names = "se"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 839 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 power-domains = <&rpmhpd SC7280_CX>; 843 operating-points-v2 = <&qup_opp_table>; 844 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 845 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 846 interconnect-names = "qup-core", "qup-config"; 847 status = "disabled"; 848 }; 849 850 uart4: serial@990000 { 851 compatible = "qcom,geni-uart"; 852 reg = <0 0x00990000 0 0x4000>; 853 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 854 clock-names = "se"; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 857 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 858 power-domains = <&rpmhpd SC7280_CX>; 859 operating-points-v2 = <&qup_opp_table>; 860 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 861 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 862 interconnect-names = "qup-core", "qup-config"; 863 status = "disabled"; 864 }; 865 866 i2c5: i2c@994000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x00994000 0 0x4000>; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 870 clock-names = "se"; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_i2c5_data_clk>; 873 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 878 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 879 interconnect-names = "qup-core", "qup-config", 880 "qup-memory"; 881 status = "disabled"; 882 }; 883 884 spi5: spi@994000 { 885 compatible = "qcom,geni-spi"; 886 reg = <0 0x00994000 0 0x4000>; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 888 clock-names = "se"; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 891 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 power-domains = <&rpmhpd SC7280_CX>; 895 operating-points-v2 = <&qup_opp_table>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 898 interconnect-names = "qup-core", "qup-config"; 899 status = "disabled"; 900 }; 901 902 uart5: serial@994000 { 903 compatible = "qcom,geni-debug-uart"; 904 reg = <0 0x00994000 0 0x4000>; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 906 clock-names = "se"; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&qup_uart5_default>; 909 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 910 status = "disabled"; 911 }; 912 913 i2c6: i2c@998000 { 914 compatible = "qcom,geni-i2c"; 915 reg = <0 0x00998000 0 0x4000>; 916 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 917 clock-names = "se"; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_i2c6_data_clk>; 920 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 924 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 925 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 926 interconnect-names = "qup-core", "qup-config", 927 "qup-memory"; 928 status = "disabled"; 929 }; 930 931 spi6: spi@998000 { 932 compatible = "qcom,geni-spi"; 933 reg = <0 0x00998000 0 0x4000>; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 935 clock-names = "se"; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 938 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 power-domains = <&rpmhpd SC7280_CX>; 942 operating-points-v2 = <&qup_opp_table>; 943 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 944 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 945 interconnect-names = "qup-core", "qup-config"; 946 status = "disabled"; 947 }; 948 949 uart6: serial@998000 { 950 compatible = "qcom,geni-uart"; 951 reg = <0 0x00998000 0 0x4000>; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 953 clock-names = "se"; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 956 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 957 power-domains = <&rpmhpd SC7280_CX>; 958 operating-points-v2 = <&qup_opp_table>; 959 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 960 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 961 interconnect-names = "qup-core", "qup-config"; 962 status = "disabled"; 963 }; 964 965 i2c7: i2c@99c000 { 966 compatible = "qcom,geni-i2c"; 967 reg = <0 0x0099c000 0 0x4000>; 968 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 969 clock-names = "se"; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&qup_i2c7_data_clk>; 972 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 976 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 977 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 978 interconnect-names = "qup-core", "qup-config", 979 "qup-memory"; 980 status = "disabled"; 981 }; 982 983 spi7: spi@99c000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0 0x0099c000 0 0x4000>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 987 clock-names = "se"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 990 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 power-domains = <&rpmhpd SC7280_CX>; 994 operating-points-v2 = <&qup_opp_table>; 995 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 996 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 997 interconnect-names = "qup-core", "qup-config"; 998 status = "disabled"; 999 }; 1000 1001 uart7: serial@99c000 { 1002 compatible = "qcom,geni-uart"; 1003 reg = <0 0x0099c000 0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1005 clock-names = "se"; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1008 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1009 power-domains = <&rpmhpd SC7280_CX>; 1010 operating-points-v2 = <&qup_opp_table>; 1011 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1012 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1013 interconnect-names = "qup-core", "qup-config"; 1014 status = "disabled"; 1015 }; 1016 }; 1017 1018 cnoc2: interconnect@1500000 { 1019 reg = <0 0x01500000 0 0x1000>; 1020 compatible = "qcom,sc7280-cnoc2"; 1021 #interconnect-cells = <2>; 1022 qcom,bcm-voters = <&apps_bcm_voter>; 1023 }; 1024 1025 cnoc3: interconnect@1502000 { 1026 reg = <0 0x01502000 0 0x1000>; 1027 compatible = "qcom,sc7280-cnoc3"; 1028 #interconnect-cells = <2>; 1029 qcom,bcm-voters = <&apps_bcm_voter>; 1030 }; 1031 1032 mc_virt: interconnect@1580000 { 1033 reg = <0 0x01580000 0 0x4>; 1034 compatible = "qcom,sc7280-mc-virt"; 1035 #interconnect-cells = <2>; 1036 qcom,bcm-voters = <&apps_bcm_voter>; 1037 }; 1038 1039 system_noc: interconnect@1680000 { 1040 reg = <0 0x01680000 0 0x15480>; 1041 compatible = "qcom,sc7280-system-noc"; 1042 #interconnect-cells = <2>; 1043 qcom,bcm-voters = <&apps_bcm_voter>; 1044 }; 1045 1046 aggre1_noc: interconnect@16e0000 { 1047 compatible = "qcom,sc7280-aggre1-noc"; 1048 reg = <0 0x016e0000 0 0x1c080>; 1049 #interconnect-cells = <2>; 1050 qcom,bcm-voters = <&apps_bcm_voter>; 1051 }; 1052 1053 aggre2_noc: interconnect@1700000 { 1054 reg = <0 0x01700000 0 0x2b080>; 1055 compatible = "qcom,sc7280-aggre2-noc"; 1056 #interconnect-cells = <2>; 1057 qcom,bcm-voters = <&apps_bcm_voter>; 1058 }; 1059 1060 mmss_noc: interconnect@1740000 { 1061 reg = <0 0x01740000 0 0x1e080>; 1062 compatible = "qcom,sc7280-mmss-noc"; 1063 #interconnect-cells = <2>; 1064 qcom,bcm-voters = <&apps_bcm_voter>; 1065 }; 1066 1067 ipa: ipa@1e40000 { 1068 compatible = "qcom,sc7280-ipa"; 1069 1070 iommus = <&apps_smmu 0x480 0x0>, 1071 <&apps_smmu 0x482 0x0>; 1072 reg = <0 0x1e40000 0 0x8000>, 1073 <0 0x1e50000 0 0x4ad0>, 1074 <0 0x1e04000 0 0x23000>; 1075 reg-names = "ipa-reg", 1076 "ipa-shared", 1077 "gsi"; 1078 1079 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1080 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1081 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1082 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1083 interrupt-names = "ipa", 1084 "gsi", 1085 "ipa-clock-query", 1086 "ipa-setup-ready"; 1087 1088 clocks = <&rpmhcc RPMH_IPA_CLK>; 1089 clock-names = "core"; 1090 1091 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1092 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1093 interconnect-names = "memory", 1094 "config"; 1095 1096 qcom,smem-states = <&ipa_smp2p_out 0>, 1097 <&ipa_smp2p_out 1>; 1098 qcom,smem-state-names = "ipa-clock-enabled-valid", 1099 "ipa-clock-enabled"; 1100 1101 status = "disabled"; 1102 }; 1103 1104 tcsr_mutex: hwlock@1f40000 { 1105 compatible = "qcom,tcsr-mutex", "syscon"; 1106 reg = <0 0x01f40000 0 0x40000>; 1107 #hwlock-cells = <1>; 1108 }; 1109 1110 lpasscc: lpasscc@3000000 { 1111 compatible = "qcom,sc7280-lpasscc"; 1112 reg = <0 0x03000000 0 0x40>, 1113 <0 0x03c04000 0 0x4>, 1114 <0 0x03389000 0 0x24>; 1115 reg-names = "qdsp6ss", "top_cc", "cc"; 1116 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1117 clock-names = "iface"; 1118 #clock-cells = <1>; 1119 }; 1120 1121 lpass_ag_noc: interconnect@3c40000 { 1122 reg = <0 0x03c40000 0 0xf080>; 1123 compatible = "qcom,sc7280-lpass-ag-noc"; 1124 #interconnect-cells = <2>; 1125 qcom,bcm-voters = <&apps_bcm_voter>; 1126 }; 1127 1128 gpu: gpu@3d00000 { 1129 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1130 #stream-id-cells = <16>; 1131 reg = <0 0x03d00000 0 0x40000>, 1132 <0 0x03d9e000 0 0x1000>, 1133 <0 0x03d61000 0 0x800>; 1134 reg-names = "kgsl_3d0_reg_memory", 1135 "cx_mem", 1136 "cx_dbgc"; 1137 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1138 iommus = <&adreno_smmu 0 0x401>; 1139 operating-points-v2 = <&gpu_opp_table>; 1140 qcom,gmu = <&gmu>; 1141 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1142 interconnect-names = "gfx-mem"; 1143 #cooling-cells = <2>; 1144 1145 gpu_opp_table: opp-table { 1146 compatible = "operating-points-v2"; 1147 1148 opp-315000000 { 1149 opp-hz = /bits/ 64 <315000000>; 1150 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1151 opp-peak-kBps = <1804000>; 1152 }; 1153 1154 opp-450000000 { 1155 opp-hz = /bits/ 64 <450000000>; 1156 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1157 opp-peak-kBps = <4068000>; 1158 }; 1159 1160 opp-550000000 { 1161 opp-hz = /bits/ 64 <550000000>; 1162 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1163 opp-peak-kBps = <6832000>; 1164 }; 1165 }; 1166 }; 1167 1168 gmu: gmu@3d69000 { 1169 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1170 reg = <0 0x03d6a000 0 0x34000>, 1171 <0 0x3de0000 0 0x10000>, 1172 <0 0x0b290000 0 0x10000>; 1173 reg-names = "gmu", "rscc", "gmu_pdc"; 1174 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1176 interrupt-names = "hfi", "gmu"; 1177 clocks = <&gpucc 5>, 1178 <&gpucc 8>, 1179 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1180 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1181 <&gpucc 2>, 1182 <&gpucc 15>, 1183 <&gpucc 11>; 1184 clock-names = "gmu", 1185 "cxo", 1186 "axi", 1187 "memnoc", 1188 "ahb", 1189 "hub", 1190 "smmu_vote"; 1191 power-domains = <&gpucc 0>, 1192 <&gpucc 1>; 1193 power-domain-names = "cx", 1194 "gx"; 1195 iommus = <&adreno_smmu 5 0x400>; 1196 operating-points-v2 = <&gmu_opp_table>; 1197 1198 gmu_opp_table: opp-table { 1199 compatible = "operating-points-v2"; 1200 1201 opp-200000000 { 1202 opp-hz = /bits/ 64 <200000000>; 1203 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1204 }; 1205 }; 1206 }; 1207 1208 gpucc: clock-controller@3d90000 { 1209 compatible = "qcom,sc7280-gpucc"; 1210 reg = <0 0x03d90000 0 0x9000>; 1211 clocks = <&rpmhcc RPMH_CXO_CLK>, 1212 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1213 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1214 clock-names = "bi_tcxo", 1215 "gcc_gpu_gpll0_clk_src", 1216 "gcc_gpu_gpll0_div_clk_src"; 1217 #clock-cells = <1>; 1218 #reset-cells = <1>; 1219 #power-domain-cells = <1>; 1220 }; 1221 1222 adreno_smmu: iommu@3da0000 { 1223 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1224 reg = <0 0x03da0000 0 0x20000>; 1225 #iommu-cells = <2>; 1226 #global-interrupts = <2>; 1227 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1239 1240 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1241 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1242 <&gpucc 2>, 1243 <&gpucc 11>, 1244 <&gpucc 5>, 1245 <&gpucc 15>, 1246 <&gpucc 13>; 1247 clock-names = "gcc_gpu_memnoc_gfx_clk", 1248 "gcc_gpu_snoc_dvm_gfx_clk", 1249 "gpu_cc_ahb_clk", 1250 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1251 "gpu_cc_cx_gmu_clk", 1252 "gpu_cc_hub_cx_int_clk", 1253 "gpu_cc_hub_aon_clk"; 1254 1255 power-domains = <&gpucc 0>; 1256 }; 1257 1258 stm@6002000 { 1259 compatible = "arm,coresight-stm", "arm,primecell"; 1260 reg = <0 0x06002000 0 0x1000>, 1261 <0 0x16280000 0 0x180000>; 1262 reg-names = "stm-base", "stm-stimulus-base"; 1263 1264 clocks = <&aoss_qmp>; 1265 clock-names = "apb_pclk"; 1266 1267 out-ports { 1268 port { 1269 stm_out: endpoint { 1270 remote-endpoint = <&funnel0_in7>; 1271 }; 1272 }; 1273 }; 1274 }; 1275 1276 funnel@6041000 { 1277 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1278 reg = <0 0x06041000 0 0x1000>; 1279 1280 clocks = <&aoss_qmp>; 1281 clock-names = "apb_pclk"; 1282 1283 out-ports { 1284 port { 1285 funnel0_out: endpoint { 1286 remote-endpoint = <&merge_funnel_in0>; 1287 }; 1288 }; 1289 }; 1290 1291 in-ports { 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 1295 port@7 { 1296 reg = <7>; 1297 funnel0_in7: endpoint { 1298 remote-endpoint = <&stm_out>; 1299 }; 1300 }; 1301 }; 1302 }; 1303 1304 funnel@6042000 { 1305 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1306 reg = <0 0x06042000 0 0x1000>; 1307 1308 clocks = <&aoss_qmp>; 1309 clock-names = "apb_pclk"; 1310 1311 out-ports { 1312 port { 1313 funnel1_out: endpoint { 1314 remote-endpoint = <&merge_funnel_in1>; 1315 }; 1316 }; 1317 }; 1318 1319 in-ports { 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 1323 port@4 { 1324 reg = <4>; 1325 funnel1_in4: endpoint { 1326 remote-endpoint = <&apss_merge_funnel_out>; 1327 }; 1328 }; 1329 }; 1330 }; 1331 1332 funnel@6045000 { 1333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1334 reg = <0 0x06045000 0 0x1000>; 1335 1336 clocks = <&aoss_qmp>; 1337 clock-names = "apb_pclk"; 1338 1339 out-ports { 1340 port { 1341 merge_funnel_out: endpoint { 1342 remote-endpoint = <&swao_funnel_in>; 1343 }; 1344 }; 1345 }; 1346 1347 in-ports { 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 1351 port@0 { 1352 reg = <0>; 1353 merge_funnel_in0: endpoint { 1354 remote-endpoint = <&funnel0_out>; 1355 }; 1356 }; 1357 1358 port@1 { 1359 reg = <1>; 1360 merge_funnel_in1: endpoint { 1361 remote-endpoint = <&funnel1_out>; 1362 }; 1363 }; 1364 }; 1365 }; 1366 1367 replicator@6046000 { 1368 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1369 reg = <0 0x06046000 0 0x1000>; 1370 1371 clocks = <&aoss_qmp>; 1372 clock-names = "apb_pclk"; 1373 1374 out-ports { 1375 port { 1376 replicator_out: endpoint { 1377 remote-endpoint = <&etr_in>; 1378 }; 1379 }; 1380 }; 1381 1382 in-ports { 1383 port { 1384 replicator_in: endpoint { 1385 remote-endpoint = <&swao_replicator_out>; 1386 }; 1387 }; 1388 }; 1389 }; 1390 1391 etr@6048000 { 1392 compatible = "arm,coresight-tmc", "arm,primecell"; 1393 reg = <0 0x06048000 0 0x1000>; 1394 iommus = <&apps_smmu 0x04c0 0>; 1395 1396 clocks = <&aoss_qmp>; 1397 clock-names = "apb_pclk"; 1398 arm,scatter-gather; 1399 1400 in-ports { 1401 port { 1402 etr_in: endpoint { 1403 remote-endpoint = <&replicator_out>; 1404 }; 1405 }; 1406 }; 1407 }; 1408 1409 funnel@6b04000 { 1410 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1411 reg = <0 0x06b04000 0 0x1000>; 1412 1413 clocks = <&aoss_qmp>; 1414 clock-names = "apb_pclk"; 1415 1416 out-ports { 1417 port { 1418 swao_funnel_out: endpoint { 1419 remote-endpoint = <&etf_in>; 1420 }; 1421 }; 1422 }; 1423 1424 in-ports { 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 1428 port@7 { 1429 reg = <7>; 1430 swao_funnel_in: endpoint { 1431 remote-endpoint = <&merge_funnel_out>; 1432 }; 1433 }; 1434 }; 1435 }; 1436 1437 etf@6b05000 { 1438 compatible = "arm,coresight-tmc", "arm,primecell"; 1439 reg = <0 0x06b05000 0 0x1000>; 1440 1441 clocks = <&aoss_qmp>; 1442 clock-names = "apb_pclk"; 1443 1444 out-ports { 1445 port { 1446 etf_out: endpoint { 1447 remote-endpoint = <&swao_replicator_in>; 1448 }; 1449 }; 1450 }; 1451 1452 in-ports { 1453 port { 1454 etf_in: endpoint { 1455 remote-endpoint = <&swao_funnel_out>; 1456 }; 1457 }; 1458 }; 1459 }; 1460 1461 replicator@6b06000 { 1462 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1463 reg = <0 0x06b06000 0 0x1000>; 1464 1465 clocks = <&aoss_qmp>; 1466 clock-names = "apb_pclk"; 1467 qcom,replicator-loses-context; 1468 1469 out-ports { 1470 port { 1471 swao_replicator_out: endpoint { 1472 remote-endpoint = <&replicator_in>; 1473 }; 1474 }; 1475 }; 1476 1477 in-ports { 1478 port { 1479 swao_replicator_in: endpoint { 1480 remote-endpoint = <&etf_out>; 1481 }; 1482 }; 1483 }; 1484 }; 1485 1486 etm@7040000 { 1487 compatible = "arm,coresight-etm4x", "arm,primecell"; 1488 reg = <0 0x07040000 0 0x1000>; 1489 1490 cpu = <&CPU0>; 1491 1492 clocks = <&aoss_qmp>; 1493 clock-names = "apb_pclk"; 1494 arm,coresight-loses-context-with-cpu; 1495 qcom,skip-power-up; 1496 1497 out-ports { 1498 port { 1499 etm0_out: endpoint { 1500 remote-endpoint = <&apss_funnel_in0>; 1501 }; 1502 }; 1503 }; 1504 }; 1505 1506 etm@7140000 { 1507 compatible = "arm,coresight-etm4x", "arm,primecell"; 1508 reg = <0 0x07140000 0 0x1000>; 1509 1510 cpu = <&CPU1>; 1511 1512 clocks = <&aoss_qmp>; 1513 clock-names = "apb_pclk"; 1514 arm,coresight-loses-context-with-cpu; 1515 qcom,skip-power-up; 1516 1517 out-ports { 1518 port { 1519 etm1_out: endpoint { 1520 remote-endpoint = <&apss_funnel_in1>; 1521 }; 1522 }; 1523 }; 1524 }; 1525 1526 etm@7240000 { 1527 compatible = "arm,coresight-etm4x", "arm,primecell"; 1528 reg = <0 0x07240000 0 0x1000>; 1529 1530 cpu = <&CPU2>; 1531 1532 clocks = <&aoss_qmp>; 1533 clock-names = "apb_pclk"; 1534 arm,coresight-loses-context-with-cpu; 1535 qcom,skip-power-up; 1536 1537 out-ports { 1538 port { 1539 etm2_out: endpoint { 1540 remote-endpoint = <&apss_funnel_in2>; 1541 }; 1542 }; 1543 }; 1544 }; 1545 1546 etm@7340000 { 1547 compatible = "arm,coresight-etm4x", "arm,primecell"; 1548 reg = <0 0x07340000 0 0x1000>; 1549 1550 cpu = <&CPU3>; 1551 1552 clocks = <&aoss_qmp>; 1553 clock-names = "apb_pclk"; 1554 arm,coresight-loses-context-with-cpu; 1555 qcom,skip-power-up; 1556 1557 out-ports { 1558 port { 1559 etm3_out: endpoint { 1560 remote-endpoint = <&apss_funnel_in3>; 1561 }; 1562 }; 1563 }; 1564 }; 1565 1566 etm@7440000 { 1567 compatible = "arm,coresight-etm4x", "arm,primecell"; 1568 reg = <0 0x07440000 0 0x1000>; 1569 1570 cpu = <&CPU4>; 1571 1572 clocks = <&aoss_qmp>; 1573 clock-names = "apb_pclk"; 1574 arm,coresight-loses-context-with-cpu; 1575 qcom,skip-power-up; 1576 1577 out-ports { 1578 port { 1579 etm4_out: endpoint { 1580 remote-endpoint = <&apss_funnel_in4>; 1581 }; 1582 }; 1583 }; 1584 }; 1585 1586 etm@7540000 { 1587 compatible = "arm,coresight-etm4x", "arm,primecell"; 1588 reg = <0 0x07540000 0 0x1000>; 1589 1590 cpu = <&CPU5>; 1591 1592 clocks = <&aoss_qmp>; 1593 clock-names = "apb_pclk"; 1594 arm,coresight-loses-context-with-cpu; 1595 qcom,skip-power-up; 1596 1597 out-ports { 1598 port { 1599 etm5_out: endpoint { 1600 remote-endpoint = <&apss_funnel_in5>; 1601 }; 1602 }; 1603 }; 1604 }; 1605 1606 etm@7640000 { 1607 compatible = "arm,coresight-etm4x", "arm,primecell"; 1608 reg = <0 0x07640000 0 0x1000>; 1609 1610 cpu = <&CPU6>; 1611 1612 clocks = <&aoss_qmp>; 1613 clock-names = "apb_pclk"; 1614 arm,coresight-loses-context-with-cpu; 1615 qcom,skip-power-up; 1616 1617 out-ports { 1618 port { 1619 etm6_out: endpoint { 1620 remote-endpoint = <&apss_funnel_in6>; 1621 }; 1622 }; 1623 }; 1624 }; 1625 1626 etm@7740000 { 1627 compatible = "arm,coresight-etm4x", "arm,primecell"; 1628 reg = <0 0x07740000 0 0x1000>; 1629 1630 cpu = <&CPU7>; 1631 1632 clocks = <&aoss_qmp>; 1633 clock-names = "apb_pclk"; 1634 arm,coresight-loses-context-with-cpu; 1635 qcom,skip-power-up; 1636 1637 out-ports { 1638 port { 1639 etm7_out: endpoint { 1640 remote-endpoint = <&apss_funnel_in7>; 1641 }; 1642 }; 1643 }; 1644 }; 1645 1646 funnel@7800000 { /* APSS Funnel */ 1647 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1648 reg = <0 0x07800000 0 0x1000>; 1649 1650 clocks = <&aoss_qmp>; 1651 clock-names = "apb_pclk"; 1652 1653 out-ports { 1654 port { 1655 apss_funnel_out: endpoint { 1656 remote-endpoint = <&apss_merge_funnel_in>; 1657 }; 1658 }; 1659 }; 1660 1661 in-ports { 1662 #address-cells = <1>; 1663 #size-cells = <0>; 1664 1665 port@0 { 1666 reg = <0>; 1667 apss_funnel_in0: endpoint { 1668 remote-endpoint = <&etm0_out>; 1669 }; 1670 }; 1671 1672 port@1 { 1673 reg = <1>; 1674 apss_funnel_in1: endpoint { 1675 remote-endpoint = <&etm1_out>; 1676 }; 1677 }; 1678 1679 port@2 { 1680 reg = <2>; 1681 apss_funnel_in2: endpoint { 1682 remote-endpoint = <&etm2_out>; 1683 }; 1684 }; 1685 1686 port@3 { 1687 reg = <3>; 1688 apss_funnel_in3: endpoint { 1689 remote-endpoint = <&etm3_out>; 1690 }; 1691 }; 1692 1693 port@4 { 1694 reg = <4>; 1695 apss_funnel_in4: endpoint { 1696 remote-endpoint = <&etm4_out>; 1697 }; 1698 }; 1699 1700 port@5 { 1701 reg = <5>; 1702 apss_funnel_in5: endpoint { 1703 remote-endpoint = <&etm5_out>; 1704 }; 1705 }; 1706 1707 port@6 { 1708 reg = <6>; 1709 apss_funnel_in6: endpoint { 1710 remote-endpoint = <&etm6_out>; 1711 }; 1712 }; 1713 1714 port@7 { 1715 reg = <7>; 1716 apss_funnel_in7: endpoint { 1717 remote-endpoint = <&etm7_out>; 1718 }; 1719 }; 1720 }; 1721 }; 1722 1723 funnel@7810000 { 1724 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1725 reg = <0 0x07810000 0 0x1000>; 1726 1727 clocks = <&aoss_qmp>; 1728 clock-names = "apb_pclk"; 1729 1730 out-ports { 1731 port { 1732 apss_merge_funnel_out: endpoint { 1733 remote-endpoint = <&funnel1_in4>; 1734 }; 1735 }; 1736 }; 1737 1738 in-ports { 1739 port { 1740 apss_merge_funnel_in: endpoint { 1741 remote-endpoint = <&apss_funnel_out>; 1742 }; 1743 }; 1744 }; 1745 }; 1746 1747 sdhc_2: sdhci@8804000 { 1748 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1749 status = "disabled"; 1750 1751 reg = <0 0x08804000 0 0x1000>; 1752 1753 iommus = <&apps_smmu 0x100 0x0>; 1754 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1756 interrupt-names = "hc_irq", "pwr_irq"; 1757 1758 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1759 <&gcc GCC_SDCC2_AHB_CLK>, 1760 <&rpmhcc RPMH_CXO_CLK>; 1761 clock-names = "core", "iface", "xo"; 1762 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1763 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1764 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1765 power-domains = <&rpmhpd SC7280_CX>; 1766 operating-points-v2 = <&sdhc2_opp_table>; 1767 1768 bus-width = <4>; 1769 1770 qcom,dll-config = <0x0007642c>; 1771 1772 sdhc2_opp_table: opp-table { 1773 compatible = "operating-points-v2"; 1774 1775 opp-100000000 { 1776 opp-hz = /bits/ 64 <100000000>; 1777 required-opps = <&rpmhpd_opp_low_svs>; 1778 opp-peak-kBps = <1800000 400000>; 1779 opp-avg-kBps = <100000 0>; 1780 }; 1781 1782 opp-202000000 { 1783 opp-hz = /bits/ 64 <202000000>; 1784 required-opps = <&rpmhpd_opp_nom>; 1785 opp-peak-kBps = <5400000 1600000>; 1786 opp-avg-kBps = <200000 0>; 1787 }; 1788 }; 1789 1790 }; 1791 1792 usb_1_hsphy: phy@88e3000 { 1793 compatible = "qcom,sc7280-usb-hs-phy", 1794 "qcom,usb-snps-hs-7nm-phy"; 1795 reg = <0 0x088e3000 0 0x400>; 1796 status = "disabled"; 1797 #phy-cells = <0>; 1798 1799 clocks = <&rpmhcc RPMH_CXO_CLK>; 1800 clock-names = "ref"; 1801 1802 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1803 }; 1804 1805 usb_2_hsphy: phy@88e4000 { 1806 compatible = "qcom,sc7280-usb-hs-phy", 1807 "qcom,usb-snps-hs-7nm-phy"; 1808 reg = <0 0x088e4000 0 0x400>; 1809 status = "disabled"; 1810 #phy-cells = <0>; 1811 1812 clocks = <&rpmhcc RPMH_CXO_CLK>; 1813 clock-names = "ref"; 1814 1815 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1816 }; 1817 1818 usb_1_qmpphy: phy-wrapper@88e9000 { 1819 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1820 "qcom,sm8250-qmp-usb3-dp-phy"; 1821 reg = <0 0x088e9000 0 0x200>, 1822 <0 0x088e8000 0 0x40>, 1823 <0 0x088ea000 0 0x200>; 1824 status = "disabled"; 1825 #address-cells = <2>; 1826 #size-cells = <2>; 1827 ranges; 1828 1829 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1830 <&rpmhcc RPMH_CXO_CLK>, 1831 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1832 clock-names = "aux", "ref_clk_src", "com_aux"; 1833 1834 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1835 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1836 reset-names = "phy", "common"; 1837 1838 usb_1_ssphy: usb3-phy@88e9200 { 1839 reg = <0 0x088e9200 0 0x200>, 1840 <0 0x088e9400 0 0x200>, 1841 <0 0x088e9c00 0 0x400>, 1842 <0 0x088e9600 0 0x200>, 1843 <0 0x088e9800 0 0x200>, 1844 <0 0x088e9a00 0 0x100>; 1845 #clock-cells = <0>; 1846 #phy-cells = <0>; 1847 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1848 clock-names = "pipe0"; 1849 clock-output-names = "usb3_phy_pipe_clk_src"; 1850 }; 1851 1852 dp_phy: dp-phy@88ea200 { 1853 reg = <0 0x088ea200 0 0x200>, 1854 <0 0x088ea400 0 0x200>, 1855 <0 0x088eaa00 0 0x200>, 1856 <0 0x088ea600 0 0x200>, 1857 <0 0x088ea800 0 0x200>; 1858 #phy-cells = <0>; 1859 #clock-cells = <1>; 1860 }; 1861 }; 1862 1863 usb_2: usb@8cf8800 { 1864 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1865 reg = <0 0x08cf8800 0 0x400>; 1866 status = "disabled"; 1867 #address-cells = <2>; 1868 #size-cells = <2>; 1869 ranges; 1870 dma-ranges; 1871 1872 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1873 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1874 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1875 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1876 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1877 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1878 "sleep"; 1879 1880 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1881 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1882 assigned-clock-rates = <19200000>, <200000000>; 1883 1884 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1885 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1886 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1887 interrupt-names = "hs_phy_irq", 1888 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1889 1890 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1891 1892 resets = <&gcc GCC_USB30_SEC_BCR>; 1893 1894 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1895 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1896 interconnect-names = "usb-ddr", "apps-usb"; 1897 1898 usb_2_dwc3: usb@8c00000 { 1899 compatible = "snps,dwc3"; 1900 reg = <0 0x08c00000 0 0xe000>; 1901 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1902 iommus = <&apps_smmu 0xa0 0x0>; 1903 snps,dis_u2_susphy_quirk; 1904 snps,dis_enblslpm_quirk; 1905 phys = <&usb_2_hsphy>; 1906 phy-names = "usb2-phy"; 1907 maximum-speed = "high-speed"; 1908 }; 1909 }; 1910 1911 qspi: spi@88dc000 { 1912 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 1913 reg = <0 0x088dc000 0 0x1000>; 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1917 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 1918 <&gcc GCC_QSPI_CORE_CLK>; 1919 clock-names = "iface", "core"; 1920 interconnects = <&gem_noc MASTER_APPSS_PROC 0 1921 &cnoc2 SLAVE_QSPI_0 0>; 1922 interconnect-names = "qspi-config"; 1923 power-domains = <&rpmhpd SC7280_CX>; 1924 operating-points-v2 = <&qspi_opp_table>; 1925 status = "disabled"; 1926 }; 1927 1928 dc_noc: interconnect@90e0000 { 1929 reg = <0 0x090e0000 0 0x5080>; 1930 compatible = "qcom,sc7280-dc-noc"; 1931 #interconnect-cells = <2>; 1932 qcom,bcm-voters = <&apps_bcm_voter>; 1933 }; 1934 1935 gem_noc: interconnect@9100000 { 1936 reg = <0 0x9100000 0 0xe2200>; 1937 compatible = "qcom,sc7280-gem-noc"; 1938 #interconnect-cells = <2>; 1939 qcom,bcm-voters = <&apps_bcm_voter>; 1940 }; 1941 1942 system-cache-controller@9200000 { 1943 compatible = "qcom,sc7280-llcc"; 1944 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1945 reg-names = "llcc_base", "llcc_broadcast_base"; 1946 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1947 }; 1948 1949 nsp_noc: interconnect@a0c0000 { 1950 reg = <0 0x0a0c0000 0 0x10000>; 1951 compatible = "qcom,sc7280-nsp-noc"; 1952 #interconnect-cells = <2>; 1953 qcom,bcm-voters = <&apps_bcm_voter>; 1954 }; 1955 1956 usb_1: usb@a6f8800 { 1957 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1958 reg = <0 0x0a6f8800 0 0x400>; 1959 status = "disabled"; 1960 #address-cells = <2>; 1961 #size-cells = <2>; 1962 ranges; 1963 dma-ranges; 1964 1965 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1966 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1967 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1968 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1969 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1970 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1971 "sleep"; 1972 1973 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1974 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1975 assigned-clock-rates = <19200000>, <200000000>; 1976 1977 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1978 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1979 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1980 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1981 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1982 "dm_hs_phy_irq", "ss_phy_irq"; 1983 1984 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1985 1986 resets = <&gcc GCC_USB30_PRIM_BCR>; 1987 1988 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1989 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1990 interconnect-names = "usb-ddr", "apps-usb"; 1991 1992 usb_1_dwc3: usb@a600000 { 1993 compatible = "snps,dwc3"; 1994 reg = <0 0x0a600000 0 0xe000>; 1995 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1996 iommus = <&apps_smmu 0xe0 0x0>; 1997 snps,dis_u2_susphy_quirk; 1998 snps,dis_enblslpm_quirk; 1999 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2000 phy-names = "usb2-phy", "usb3-phy"; 2001 maximum-speed = "super-speed"; 2002 }; 2003 }; 2004 2005 videocc: clock-controller@aaf0000 { 2006 compatible = "qcom,sc7280-videocc"; 2007 reg = <0 0xaaf0000 0 0x10000>; 2008 clocks = <&rpmhcc RPMH_CXO_CLK>, 2009 <&rpmhcc RPMH_CXO_CLK_A>; 2010 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2011 #clock-cells = <1>; 2012 #reset-cells = <1>; 2013 #power-domain-cells = <1>; 2014 }; 2015 2016 dispcc: clock-controller@af00000 { 2017 compatible = "qcom,sc7280-dispcc"; 2018 reg = <0 0xaf00000 0 0x20000>; 2019 clocks = <&rpmhcc RPMH_CXO_CLK>, 2020 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2021 <0>, <0>, <0>, <0>, <0>, <0>; 2022 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2023 "dsi0_phy_pll_out_byteclk", 2024 "dsi0_phy_pll_out_dsiclk", 2025 "dp_phy_pll_link_clk", 2026 "dp_phy_pll_vco_div_clk", 2027 "edp_phy_pll_link_clk", 2028 "edp_phy_pll_vco_div_clk"; 2029 #clock-cells = <1>; 2030 #reset-cells = <1>; 2031 #power-domain-cells = <1>; 2032 }; 2033 2034 pdc: interrupt-controller@b220000 { 2035 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2036 reg = <0 0x0b220000 0 0x30000>; 2037 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2038 <55 306 4>, <59 312 3>, <62 374 2>, 2039 <64 434 2>, <66 438 3>, <69 86 1>, 2040 <70 520 54>, <124 609 31>, <155 63 1>, 2041 <156 716 12>; 2042 #interrupt-cells = <2>; 2043 interrupt-parent = <&intc>; 2044 interrupt-controller; 2045 }; 2046 2047 pdc_reset: reset-controller@b5e0000 { 2048 compatible = "qcom,sc7280-pdc-global"; 2049 reg = <0 0x0b5e0000 0 0x20000>; 2050 #reset-cells = <1>; 2051 }; 2052 2053 tsens0: thermal-sensor@c263000 { 2054 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2055 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2056 <0 0x0c222000 0 0x1ff>; /* SROT */ 2057 #qcom,sensors = <15>; 2058 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2060 interrupt-names = "uplow","critical"; 2061 #thermal-sensor-cells = <1>; 2062 }; 2063 2064 tsens1: thermal-sensor@c265000 { 2065 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2066 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2067 <0 0x0c223000 0 0x1ff>; /* SROT */ 2068 #qcom,sensors = <12>; 2069 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2071 interrupt-names = "uplow","critical"; 2072 #thermal-sensor-cells = <1>; 2073 }; 2074 2075 aoss_reset: reset-controller@c2a0000 { 2076 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2077 reg = <0 0x0c2a0000 0 0x31000>; 2078 #reset-cells = <1>; 2079 }; 2080 2081 aoss_qmp: power-controller@c300000 { 2082 compatible = "qcom,sc7280-aoss-qmp"; 2083 reg = <0 0x0c300000 0 0x100000>; 2084 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2085 IPCC_MPROC_SIGNAL_GLINK_QMP 2086 IRQ_TYPE_EDGE_RISING>; 2087 mboxes = <&ipcc IPCC_CLIENT_AOP 2088 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2089 2090 #clock-cells = <0>; 2091 #power-domain-cells = <1>; 2092 }; 2093 2094 spmi_bus: spmi@c440000 { 2095 compatible = "qcom,spmi-pmic-arb"; 2096 reg = <0 0x0c440000 0 0x1100>, 2097 <0 0x0c600000 0 0x2000000>, 2098 <0 0x0e600000 0 0x100000>, 2099 <0 0x0e700000 0 0xa0000>, 2100 <0 0x0c40a000 0 0x26000>; 2101 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2102 interrupt-names = "periph_irq"; 2103 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2104 qcom,ee = <0>; 2105 qcom,channel = <0>; 2106 #address-cells = <1>; 2107 #size-cells = <1>; 2108 interrupt-controller; 2109 #interrupt-cells = <4>; 2110 }; 2111 2112 tlmm: pinctrl@f100000 { 2113 compatible = "qcom,sc7280-pinctrl"; 2114 reg = <0 0x0f100000 0 0x300000>; 2115 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2116 gpio-controller; 2117 #gpio-cells = <2>; 2118 interrupt-controller; 2119 #interrupt-cells = <2>; 2120 gpio-ranges = <&tlmm 0 0 175>; 2121 wakeup-parent = <&pdc>; 2122 2123 qspi_clk: qspi-clk { 2124 pins = "gpio14"; 2125 function = "qspi_clk"; 2126 }; 2127 2128 qspi_cs0: qspi-cs0 { 2129 pins = "gpio15"; 2130 function = "qspi_cs"; 2131 }; 2132 2133 qspi_cs1: qspi-cs1 { 2134 pins = "gpio19"; 2135 function = "qspi_cs"; 2136 }; 2137 2138 qspi_data01: qspi-data01 { 2139 pins = "gpio12", "gpio13"; 2140 function = "qspi_data"; 2141 }; 2142 2143 qspi_data12: qspi-data12 { 2144 pins = "gpio16", "gpio17"; 2145 function = "qspi_data"; 2146 }; 2147 2148 qup_i2c0_data_clk: qup-i2c0-data-clk { 2149 pins = "gpio0", "gpio1"; 2150 function = "qup00"; 2151 }; 2152 2153 qup_i2c1_data_clk: qup-i2c1-data-clk { 2154 pins = "gpio4", "gpio5"; 2155 function = "qup01"; 2156 }; 2157 2158 qup_i2c2_data_clk: qup-i2c2-data-clk { 2159 pins = "gpio8", "gpio9"; 2160 function = "qup02"; 2161 }; 2162 2163 qup_i2c3_data_clk: qup-i2c3-data-clk { 2164 pins = "gpio12", "gpio13"; 2165 function = "qup03"; 2166 }; 2167 2168 qup_i2c4_data_clk: qup-i2c4-data-clk { 2169 pins = "gpio16", "gpio17"; 2170 function = "qup04"; 2171 }; 2172 2173 qup_i2c5_data_clk: qup-i2c5-data-clk { 2174 pins = "gpio20", "gpio21"; 2175 function = "qup05"; 2176 }; 2177 2178 qup_i2c6_data_clk: qup-i2c6-data-clk { 2179 pins = "gpio24", "gpio25"; 2180 function = "qup06"; 2181 }; 2182 2183 qup_i2c7_data_clk: qup-i2c7-data-clk { 2184 pins = "gpio28", "gpio29"; 2185 function = "qup07"; 2186 }; 2187 2188 qup_spi0_data_clk: qup-spi0-data-clk { 2189 pins = "gpio0", "gpio1", "gpio2"; 2190 function = "qup00"; 2191 }; 2192 2193 qup_spi0_cs: qup-spi0-cs { 2194 pins = "gpio3"; 2195 function = "qup00"; 2196 }; 2197 2198 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2199 pins = "gpio3"; 2200 function = "gpio"; 2201 }; 2202 2203 qup_spi1_data_clk: qup-spi1-data-clk { 2204 pins = "gpio4", "gpio5", "gpio6"; 2205 function = "qup01"; 2206 }; 2207 2208 qup_spi1_cs: qup-spi1-cs { 2209 pins = "gpio7"; 2210 function = "qup01"; 2211 }; 2212 2213 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2214 pins = "gpio7"; 2215 function = "gpio"; 2216 }; 2217 2218 qup_spi2_data_clk: qup-spi2-data-clk { 2219 pins = "gpio8", "gpio9", "gpio10"; 2220 function = "qup02"; 2221 }; 2222 2223 qup_spi2_cs: qup-spi2-cs { 2224 pins = "gpio11"; 2225 function = "qup02"; 2226 }; 2227 2228 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2229 pins = "gpio11"; 2230 function = "gpio"; 2231 }; 2232 2233 qup_spi3_data_clk: qup-spi3-data-clk { 2234 pins = "gpio12", "gpio13", "gpio14"; 2235 function = "qup03"; 2236 }; 2237 2238 qup_spi3_cs: qup-spi3-cs { 2239 pins = "gpio15"; 2240 function = "qup03"; 2241 }; 2242 2243 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2244 pins = "gpio15"; 2245 function = "gpio"; 2246 }; 2247 2248 qup_spi4_data_clk: qup-spi4-data-clk { 2249 pins = "gpio16", "gpio17", "gpio18"; 2250 function = "qup04"; 2251 }; 2252 2253 qup_spi4_cs: qup-spi4-cs { 2254 pins = "gpio19"; 2255 function = "qup04"; 2256 }; 2257 2258 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2259 pins = "gpio19"; 2260 function = "gpio"; 2261 }; 2262 2263 qup_spi5_data_clk: qup-spi5-data-clk { 2264 pins = "gpio20", "gpio21", "gpio22"; 2265 function = "qup05"; 2266 }; 2267 2268 qup_spi5_cs: qup-spi5-cs { 2269 pins = "gpio23"; 2270 function = "qup05"; 2271 }; 2272 2273 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2274 pins = "gpio23"; 2275 function = "gpio"; 2276 }; 2277 2278 qup_spi6_data_clk: qup-spi6-data-clk { 2279 pins = "gpio24", "gpio25", "gpio26"; 2280 function = "qup06"; 2281 }; 2282 2283 qup_spi6_cs: qup-spi6-cs { 2284 pins = "gpio27"; 2285 function = "qup06"; 2286 }; 2287 2288 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2289 pins = "gpio27"; 2290 function = "gpio"; 2291 }; 2292 2293 qup_spi7_data_clk: qup-spi7-data-clk { 2294 pins = "gpio28", "gpio29", "gpio30"; 2295 function = "qup07"; 2296 }; 2297 2298 qup_spi7_cs: qup-spi7-cs { 2299 pins = "gpio31"; 2300 function = "qup07"; 2301 }; 2302 2303 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2304 pins = "gpio31"; 2305 function = "gpio"; 2306 }; 2307 2308 qup_uart0_cts: qup-uart0-cts { 2309 pins = "gpio0"; 2310 function = "qup00"; 2311 }; 2312 2313 qup_uart0_rts: qup-uart0-rts { 2314 pins = "gpio1"; 2315 function = "qup00"; 2316 }; 2317 2318 qup_uart0_tx: qup-uart0-tx { 2319 pins = "gpio2"; 2320 function = "qup00"; 2321 }; 2322 2323 qup_uart0_rx: qup-uart0-rx { 2324 pins = "gpio3"; 2325 function = "qup00"; 2326 }; 2327 2328 qup_uart1_cts: qup-uart1-cts { 2329 pins = "gpio4"; 2330 function = "qup01"; 2331 }; 2332 2333 qup_uart1_rts: qup-uart1-rts { 2334 pins = "gpio5"; 2335 function = "qup01"; 2336 }; 2337 2338 qup_uart1_tx: qup-uart1-tx { 2339 pins = "gpio6"; 2340 function = "qup01"; 2341 }; 2342 2343 qup_uart1_rx: qup-uart1-rx { 2344 pins = "gpio7"; 2345 function = "qup01"; 2346 }; 2347 2348 qup_uart2_cts: qup-uart2-cts { 2349 pins = "gpio8"; 2350 function = "qup02"; 2351 }; 2352 2353 qup_uart2_rts: qup-uart2-rts { 2354 pins = "gpio9"; 2355 function = "qup02"; 2356 }; 2357 2358 qup_uart2_tx: qup-uart2-tx { 2359 pins = "gpio10"; 2360 function = "qup02"; 2361 }; 2362 2363 qup_uart2_rx: qup-uart2-rx { 2364 pins = "gpio11"; 2365 function = "qup02"; 2366 }; 2367 2368 qup_uart3_cts: qup-uart3-cts { 2369 pins = "gpio12"; 2370 function = "qup03"; 2371 }; 2372 2373 qup_uart3_rts: qup-uart3-rts { 2374 pins = "gpio13"; 2375 function = "qup03"; 2376 }; 2377 2378 qup_uart3_tx: qup-uart3-tx { 2379 pins = "gpio14"; 2380 function = "qup03"; 2381 }; 2382 2383 qup_uart3_rx: qup-uart3-rx { 2384 pins = "gpio15"; 2385 function = "qup03"; 2386 }; 2387 2388 qup_uart4_cts: qup-uart4-cts { 2389 pins = "gpio16"; 2390 function = "qup04"; 2391 }; 2392 2393 qup_uart4_rts: qup-uart4-rts { 2394 pins = "gpio17"; 2395 function = "qup04"; 2396 }; 2397 2398 qup_uart4_tx: qup-uart4-tx { 2399 pins = "gpio18"; 2400 function = "qup04"; 2401 }; 2402 2403 qup_uart4_rx: qup-uart4-rx { 2404 pins = "gpio19"; 2405 function = "qup04"; 2406 }; 2407 2408 qup_uart5_default: qup-uart5-default { 2409 pins = "gpio46", "gpio47"; 2410 function = "qup13"; 2411 }; 2412 2413 qup_uart6_cts: qup-uart6-cts { 2414 pins = "gpio24"; 2415 function = "qup06"; 2416 }; 2417 2418 qup_uart6_rts: qup-uart6-rts { 2419 pins = "gpio25"; 2420 function = "qup06"; 2421 }; 2422 2423 qup_uart6_tx: qup-uart6-tx { 2424 pins = "gpio26"; 2425 function = "qup06"; 2426 }; 2427 2428 qup_uart6_rx: qup-uart6-rx { 2429 pins = "gpio27"; 2430 function = "qup06"; 2431 }; 2432 2433 qup_uart7_cts: qup-uart7-cts { 2434 pins = "gpio28"; 2435 function = "qup07"; 2436 }; 2437 2438 qup_uart7_rts: qup-uart7-rts { 2439 pins = "gpio29"; 2440 function = "qup07"; 2441 }; 2442 2443 qup_uart7_tx: qup-uart7-tx { 2444 pins = "gpio30"; 2445 function = "qup07"; 2446 }; 2447 2448 qup_uart7_rx: qup-uart7-rx { 2449 pins = "gpio31"; 2450 function = "qup07"; 2451 }; 2452 2453 sdc1_on: sdc1-on { 2454 clk { 2455 pins = "sdc1_clk"; 2456 }; 2457 2458 cmd { 2459 pins = "sdc1_cmd"; 2460 }; 2461 2462 data { 2463 pins = "sdc1_data"; 2464 }; 2465 2466 rclk { 2467 pins = "sdc1_rclk"; 2468 }; 2469 }; 2470 2471 sdc1_off: sdc1-off { 2472 clk { 2473 pins = "sdc1_clk"; 2474 drive-strength = <2>; 2475 bias-bus-hold; 2476 }; 2477 2478 cmd { 2479 pins = "sdc1_cmd"; 2480 drive-strength = <2>; 2481 bias-bus-hold; 2482 }; 2483 2484 data { 2485 pins = "sdc1_data"; 2486 drive-strength = <2>; 2487 bias-bus-hold; 2488 }; 2489 2490 rclk { 2491 pins = "sdc1_rclk"; 2492 bias-bus-hold; 2493 }; 2494 }; 2495 2496 sdc2_on: sdc2-on { 2497 clk { 2498 pins = "sdc2_clk"; 2499 }; 2500 2501 cmd { 2502 pins = "sdc2_cmd"; 2503 }; 2504 2505 data { 2506 pins = "sdc2_data"; 2507 }; 2508 }; 2509 2510 sdc2_off: sdc2-off { 2511 clk { 2512 pins = "sdc2_clk"; 2513 drive-strength = <2>; 2514 bias-bus-hold; 2515 }; 2516 2517 cmd { 2518 pins ="sdc2_cmd"; 2519 drive-strength = <2>; 2520 bias-bus-hold; 2521 }; 2522 2523 data { 2524 pins ="sdc2_data"; 2525 drive-strength = <2>; 2526 bias-bus-hold; 2527 }; 2528 }; 2529 }; 2530 2531 apps_smmu: iommu@15000000 { 2532 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 2533 reg = <0 0x15000000 0 0x100000>; 2534 #iommu-cells = <2>; 2535 #global-interrupts = <1>; 2536 dma-coherent; 2537 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2538 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2539 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2541 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2554 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2555 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2556 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2557 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2558 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2559 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2560 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2561 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2564 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2569 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2570 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2571 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2572 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2573 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2574 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2575 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2576 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2577 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2578 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2612 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2616 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 2618 }; 2619 2620 intc: interrupt-controller@17a00000 { 2621 compatible = "arm,gic-v3"; 2622 #address-cells = <2>; 2623 #size-cells = <2>; 2624 ranges; 2625 #interrupt-cells = <3>; 2626 interrupt-controller; 2627 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2628 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2629 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 2630 2631 gic-its@17a40000 { 2632 compatible = "arm,gic-v3-its"; 2633 msi-controller; 2634 #msi-cells = <1>; 2635 reg = <0 0x17a40000 0 0x20000>; 2636 status = "disabled"; 2637 }; 2638 }; 2639 2640 watchdog@17c10000 { 2641 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 2642 reg = <0 0x17c10000 0 0x1000>; 2643 clocks = <&sleep_clk>; 2644 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2645 }; 2646 2647 timer@17c20000 { 2648 #address-cells = <2>; 2649 #size-cells = <2>; 2650 ranges; 2651 compatible = "arm,armv7-timer-mem"; 2652 reg = <0 0x17c20000 0 0x1000>; 2653 2654 frame@17c21000 { 2655 frame-number = <0>; 2656 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2657 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2658 reg = <0 0x17c21000 0 0x1000>, 2659 <0 0x17c22000 0 0x1000>; 2660 }; 2661 2662 frame@17c23000 { 2663 frame-number = <1>; 2664 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2665 reg = <0 0x17c23000 0 0x1000>; 2666 status = "disabled"; 2667 }; 2668 2669 frame@17c25000 { 2670 frame-number = <2>; 2671 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2672 reg = <0 0x17c25000 0 0x1000>; 2673 status = "disabled"; 2674 }; 2675 2676 frame@17c27000 { 2677 frame-number = <3>; 2678 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2679 reg = <0 0x17c27000 0 0x1000>; 2680 status = "disabled"; 2681 }; 2682 2683 frame@17c29000 { 2684 frame-number = <4>; 2685 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2686 reg = <0 0x17c29000 0 0x1000>; 2687 status = "disabled"; 2688 }; 2689 2690 frame@17c2b000 { 2691 frame-number = <5>; 2692 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2693 reg = <0 0x17c2b000 0 0x1000>; 2694 status = "disabled"; 2695 }; 2696 2697 frame@17c2d000 { 2698 frame-number = <6>; 2699 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2700 reg = <0 0x17c2d000 0 0x1000>; 2701 status = "disabled"; 2702 }; 2703 }; 2704 2705 apps_rsc: rsc@18200000 { 2706 compatible = "qcom,rpmh-rsc"; 2707 reg = <0 0x18200000 0 0x10000>, 2708 <0 0x18210000 0 0x10000>, 2709 <0 0x18220000 0 0x10000>; 2710 reg-names = "drv-0", "drv-1", "drv-2"; 2711 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2714 qcom,tcs-offset = <0xd00>; 2715 qcom,drv-id = <2>; 2716 qcom,tcs-config = <ACTIVE_TCS 2>, 2717 <SLEEP_TCS 3>, 2718 <WAKE_TCS 3>, 2719 <CONTROL_TCS 1>; 2720 2721 apps_bcm_voter: bcm-voter { 2722 compatible = "qcom,bcm-voter"; 2723 }; 2724 2725 rpmhpd: power-controller { 2726 compatible = "qcom,sc7280-rpmhpd"; 2727 #power-domain-cells = <1>; 2728 operating-points-v2 = <&rpmhpd_opp_table>; 2729 2730 rpmhpd_opp_table: opp-table { 2731 compatible = "operating-points-v2"; 2732 2733 rpmhpd_opp_ret: opp1 { 2734 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2735 }; 2736 2737 rpmhpd_opp_low_svs: opp2 { 2738 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2739 }; 2740 2741 rpmhpd_opp_svs: opp3 { 2742 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2743 }; 2744 2745 rpmhpd_opp_svs_l1: opp4 { 2746 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2747 }; 2748 2749 rpmhpd_opp_svs_l2: opp5 { 2750 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2751 }; 2752 2753 rpmhpd_opp_nom: opp6 { 2754 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2755 }; 2756 2757 rpmhpd_opp_nom_l1: opp7 { 2758 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2759 }; 2760 2761 rpmhpd_opp_turbo: opp8 { 2762 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2763 }; 2764 2765 rpmhpd_opp_turbo_l1: opp9 { 2766 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2767 }; 2768 }; 2769 }; 2770 2771 rpmhcc: clock-controller { 2772 compatible = "qcom,sc7280-rpmh-clk"; 2773 clocks = <&xo_board>; 2774 clock-names = "xo"; 2775 #clock-cells = <1>; 2776 }; 2777 }; 2778 2779 cpufreq_hw: cpufreq@18591000 { 2780 compatible = "qcom,cpufreq-epss"; 2781 reg = <0 0x18591100 0 0x900>, 2782 <0 0x18592100 0 0x900>, 2783 <0 0x18593100 0 0x900>; 2784 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2785 clock-names = "xo", "alternate"; 2786 #freq-domain-cells = <1>; 2787 }; 2788 }; 2789 2790 thermal_zones: thermal-zones { 2791 cpu0-thermal { 2792 polling-delay-passive = <250>; 2793 polling-delay = <0>; 2794 2795 thermal-sensors = <&tsens0 1>; 2796 2797 trips { 2798 cpu0_alert0: trip-point0 { 2799 temperature = <90000>; 2800 hysteresis = <2000>; 2801 type = "passive"; 2802 }; 2803 2804 cpu0_alert1: trip-point1 { 2805 temperature = <95000>; 2806 hysteresis = <2000>; 2807 type = "passive"; 2808 }; 2809 2810 cpu0_crit: cpu-crit { 2811 temperature = <110000>; 2812 hysteresis = <0>; 2813 type = "critical"; 2814 }; 2815 }; 2816 2817 cooling-maps { 2818 map0 { 2819 trip = <&cpu0_alert0>; 2820 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2821 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2822 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2823 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2824 }; 2825 map1 { 2826 trip = <&cpu0_alert1>; 2827 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2828 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2829 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2830 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2831 }; 2832 }; 2833 }; 2834 2835 cpu1-thermal { 2836 polling-delay-passive = <250>; 2837 polling-delay = <0>; 2838 2839 thermal-sensors = <&tsens0 2>; 2840 2841 trips { 2842 cpu1_alert0: trip-point0 { 2843 temperature = <90000>; 2844 hysteresis = <2000>; 2845 type = "passive"; 2846 }; 2847 2848 cpu1_alert1: trip-point1 { 2849 temperature = <95000>; 2850 hysteresis = <2000>; 2851 type = "passive"; 2852 }; 2853 2854 cpu1_crit: cpu-crit { 2855 temperature = <110000>; 2856 hysteresis = <0>; 2857 type = "critical"; 2858 }; 2859 }; 2860 2861 cooling-maps { 2862 map0 { 2863 trip = <&cpu1_alert0>; 2864 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2865 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2866 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2867 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2868 }; 2869 map1 { 2870 trip = <&cpu1_alert1>; 2871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2875 }; 2876 }; 2877 }; 2878 2879 cpu2-thermal { 2880 polling-delay-passive = <250>; 2881 polling-delay = <0>; 2882 2883 thermal-sensors = <&tsens0 3>; 2884 2885 trips { 2886 cpu2_alert0: trip-point0 { 2887 temperature = <90000>; 2888 hysteresis = <2000>; 2889 type = "passive"; 2890 }; 2891 2892 cpu2_alert1: trip-point1 { 2893 temperature = <95000>; 2894 hysteresis = <2000>; 2895 type = "passive"; 2896 }; 2897 2898 cpu2_crit: cpu-crit { 2899 temperature = <110000>; 2900 hysteresis = <0>; 2901 type = "critical"; 2902 }; 2903 }; 2904 2905 cooling-maps { 2906 map0 { 2907 trip = <&cpu2_alert0>; 2908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2909 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2910 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2911 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2912 }; 2913 map1 { 2914 trip = <&cpu2_alert1>; 2915 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2916 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2917 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2918 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2919 }; 2920 }; 2921 }; 2922 2923 cpu3-thermal { 2924 polling-delay-passive = <250>; 2925 polling-delay = <0>; 2926 2927 thermal-sensors = <&tsens0 4>; 2928 2929 trips { 2930 cpu3_alert0: trip-point0 { 2931 temperature = <90000>; 2932 hysteresis = <2000>; 2933 type = "passive"; 2934 }; 2935 2936 cpu3_alert1: trip-point1 { 2937 temperature = <95000>; 2938 hysteresis = <2000>; 2939 type = "passive"; 2940 }; 2941 2942 cpu3_crit: cpu-crit { 2943 temperature = <110000>; 2944 hysteresis = <0>; 2945 type = "critical"; 2946 }; 2947 }; 2948 2949 cooling-maps { 2950 map0 { 2951 trip = <&cpu3_alert0>; 2952 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2953 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2954 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2955 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2956 }; 2957 map1 { 2958 trip = <&cpu3_alert1>; 2959 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2960 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2961 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2962 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2963 }; 2964 }; 2965 }; 2966 2967 cpu4-thermal { 2968 polling-delay-passive = <250>; 2969 polling-delay = <0>; 2970 2971 thermal-sensors = <&tsens0 7>; 2972 2973 trips { 2974 cpu4_alert0: trip-point0 { 2975 temperature = <90000>; 2976 hysteresis = <2000>; 2977 type = "passive"; 2978 }; 2979 2980 cpu4_alert1: trip-point1 { 2981 temperature = <95000>; 2982 hysteresis = <2000>; 2983 type = "passive"; 2984 }; 2985 2986 cpu4_crit: cpu-crit { 2987 temperature = <110000>; 2988 hysteresis = <0>; 2989 type = "critical"; 2990 }; 2991 }; 2992 2993 cooling-maps { 2994 map0 { 2995 trip = <&cpu4_alert0>; 2996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2997 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2998 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3000 }; 3001 map1 { 3002 trip = <&cpu4_alert1>; 3003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3007 }; 3008 }; 3009 }; 3010 3011 cpu5-thermal { 3012 polling-delay-passive = <250>; 3013 polling-delay = <0>; 3014 3015 thermal-sensors = <&tsens0 8>; 3016 3017 trips { 3018 cpu5_alert0: trip-point0 { 3019 temperature = <90000>; 3020 hysteresis = <2000>; 3021 type = "passive"; 3022 }; 3023 3024 cpu5_alert1: trip-point1 { 3025 temperature = <95000>; 3026 hysteresis = <2000>; 3027 type = "passive"; 3028 }; 3029 3030 cpu5_crit: cpu-crit { 3031 temperature = <110000>; 3032 hysteresis = <0>; 3033 type = "critical"; 3034 }; 3035 }; 3036 3037 cooling-maps { 3038 map0 { 3039 trip = <&cpu5_alert0>; 3040 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3041 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3042 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3043 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3044 }; 3045 map1 { 3046 trip = <&cpu5_alert1>; 3047 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3048 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3049 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3051 }; 3052 }; 3053 }; 3054 3055 cpu6-thermal { 3056 polling-delay-passive = <250>; 3057 polling-delay = <0>; 3058 3059 thermal-sensors = <&tsens0 9>; 3060 3061 trips { 3062 cpu6_alert0: trip-point0 { 3063 temperature = <90000>; 3064 hysteresis = <2000>; 3065 type = "passive"; 3066 }; 3067 3068 cpu6_alert1: trip-point1 { 3069 temperature = <95000>; 3070 hysteresis = <2000>; 3071 type = "passive"; 3072 }; 3073 3074 cpu6_crit: cpu-crit { 3075 temperature = <110000>; 3076 hysteresis = <0>; 3077 type = "critical"; 3078 }; 3079 }; 3080 3081 cooling-maps { 3082 map0 { 3083 trip = <&cpu6_alert0>; 3084 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3085 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3086 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3087 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3088 }; 3089 map1 { 3090 trip = <&cpu6_alert1>; 3091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3095 }; 3096 }; 3097 }; 3098 3099 cpu7-thermal { 3100 polling-delay-passive = <250>; 3101 polling-delay = <0>; 3102 3103 thermal-sensors = <&tsens0 10>; 3104 3105 trips { 3106 cpu7_alert0: trip-point0 { 3107 temperature = <90000>; 3108 hysteresis = <2000>; 3109 type = "passive"; 3110 }; 3111 3112 cpu7_alert1: trip-point1 { 3113 temperature = <95000>; 3114 hysteresis = <2000>; 3115 type = "passive"; 3116 }; 3117 3118 cpu7_crit: cpu-crit { 3119 temperature = <110000>; 3120 hysteresis = <0>; 3121 type = "critical"; 3122 }; 3123 }; 3124 3125 cooling-maps { 3126 map0 { 3127 trip = <&cpu7_alert0>; 3128 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3129 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3130 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3131 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3132 }; 3133 map1 { 3134 trip = <&cpu7_alert1>; 3135 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3136 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3137 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3139 }; 3140 }; 3141 }; 3142 3143 cpu8-thermal { 3144 polling-delay-passive = <250>; 3145 polling-delay = <0>; 3146 3147 thermal-sensors = <&tsens0 11>; 3148 3149 trips { 3150 cpu8_alert0: trip-point0 { 3151 temperature = <90000>; 3152 hysteresis = <2000>; 3153 type = "passive"; 3154 }; 3155 3156 cpu8_alert1: trip-point1 { 3157 temperature = <95000>; 3158 hysteresis = <2000>; 3159 type = "passive"; 3160 }; 3161 3162 cpu8_crit: cpu-crit { 3163 temperature = <110000>; 3164 hysteresis = <0>; 3165 type = "critical"; 3166 }; 3167 }; 3168 3169 cooling-maps { 3170 map0 { 3171 trip = <&cpu8_alert0>; 3172 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3173 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3174 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3175 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3176 }; 3177 map1 { 3178 trip = <&cpu8_alert1>; 3179 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3180 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3181 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3182 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3183 }; 3184 }; 3185 }; 3186 3187 cpu9-thermal { 3188 polling-delay-passive = <250>; 3189 polling-delay = <0>; 3190 3191 thermal-sensors = <&tsens0 12>; 3192 3193 trips { 3194 cpu9_alert0: trip-point0 { 3195 temperature = <90000>; 3196 hysteresis = <2000>; 3197 type = "passive"; 3198 }; 3199 3200 cpu9_alert1: trip-point1 { 3201 temperature = <95000>; 3202 hysteresis = <2000>; 3203 type = "passive"; 3204 }; 3205 3206 cpu9_crit: cpu-crit { 3207 temperature = <110000>; 3208 hysteresis = <0>; 3209 type = "critical"; 3210 }; 3211 }; 3212 3213 cooling-maps { 3214 map0 { 3215 trip = <&cpu9_alert0>; 3216 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3217 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3218 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3219 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3220 }; 3221 map1 { 3222 trip = <&cpu9_alert1>; 3223 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3224 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3225 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3226 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3227 }; 3228 }; 3229 }; 3230 3231 cpu10-thermal { 3232 polling-delay-passive = <250>; 3233 polling-delay = <0>; 3234 3235 thermal-sensors = <&tsens0 13>; 3236 3237 trips { 3238 cpu10_alert0: trip-point0 { 3239 temperature = <90000>; 3240 hysteresis = <2000>; 3241 type = "passive"; 3242 }; 3243 3244 cpu10_alert1: trip-point1 { 3245 temperature = <95000>; 3246 hysteresis = <2000>; 3247 type = "passive"; 3248 }; 3249 3250 cpu10_crit: cpu-crit { 3251 temperature = <110000>; 3252 hysteresis = <0>; 3253 type = "critical"; 3254 }; 3255 }; 3256 3257 cooling-maps { 3258 map0 { 3259 trip = <&cpu10_alert0>; 3260 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3261 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3262 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3263 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3264 }; 3265 map1 { 3266 trip = <&cpu10_alert1>; 3267 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3268 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3269 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3270 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3271 }; 3272 }; 3273 }; 3274 3275 cpu11-thermal { 3276 polling-delay-passive = <250>; 3277 polling-delay = <0>; 3278 3279 thermal-sensors = <&tsens0 14>; 3280 3281 trips { 3282 cpu11_alert0: trip-point0 { 3283 temperature = <90000>; 3284 hysteresis = <2000>; 3285 type = "passive"; 3286 }; 3287 3288 cpu11_alert1: trip-point1 { 3289 temperature = <95000>; 3290 hysteresis = <2000>; 3291 type = "passive"; 3292 }; 3293 3294 cpu11_crit: cpu-crit { 3295 temperature = <110000>; 3296 hysteresis = <0>; 3297 type = "critical"; 3298 }; 3299 }; 3300 3301 cooling-maps { 3302 map0 { 3303 trip = <&cpu11_alert0>; 3304 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3305 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3306 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3307 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3308 }; 3309 map1 { 3310 trip = <&cpu11_alert1>; 3311 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3312 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3313 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3314 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3315 }; 3316 }; 3317 }; 3318 3319 aoss0-thermal { 3320 polling-delay-passive = <0>; 3321 polling-delay = <0>; 3322 3323 thermal-sensors = <&tsens0 0>; 3324 3325 trips { 3326 aoss0_alert0: trip-point0 { 3327 temperature = <90000>; 3328 hysteresis = <2000>; 3329 type = "hot"; 3330 }; 3331 3332 aoss0_crit: aoss0-crit { 3333 temperature = <110000>; 3334 hysteresis = <0>; 3335 type = "critical"; 3336 }; 3337 }; 3338 }; 3339 3340 aoss1-thermal { 3341 polling-delay-passive = <0>; 3342 polling-delay = <0>; 3343 3344 thermal-sensors = <&tsens1 0>; 3345 3346 trips { 3347 aoss1_alert0: trip-point0 { 3348 temperature = <90000>; 3349 hysteresis = <2000>; 3350 type = "hot"; 3351 }; 3352 3353 aoss1_crit: aoss1-crit { 3354 temperature = <110000>; 3355 hysteresis = <0>; 3356 type = "critical"; 3357 }; 3358 }; 3359 }; 3360 3361 cpuss0-thermal { 3362 polling-delay-passive = <0>; 3363 polling-delay = <0>; 3364 3365 thermal-sensors = <&tsens0 5>; 3366 3367 trips { 3368 cpuss0_alert0: trip-point0 { 3369 temperature = <90000>; 3370 hysteresis = <2000>; 3371 type = "hot"; 3372 }; 3373 cpuss0_crit: cluster0-crit { 3374 temperature = <110000>; 3375 hysteresis = <0>; 3376 type = "critical"; 3377 }; 3378 }; 3379 }; 3380 3381 cpuss1-thermal { 3382 polling-delay-passive = <0>; 3383 polling-delay = <0>; 3384 3385 thermal-sensors = <&tsens0 6>; 3386 3387 trips { 3388 cpuss1_alert0: trip-point0 { 3389 temperature = <90000>; 3390 hysteresis = <2000>; 3391 type = "hot"; 3392 }; 3393 cpuss1_crit: cluster0-crit { 3394 temperature = <110000>; 3395 hysteresis = <0>; 3396 type = "critical"; 3397 }; 3398 }; 3399 }; 3400 3401 gpuss0-thermal { 3402 polling-delay-passive = <100>; 3403 polling-delay = <0>; 3404 3405 thermal-sensors = <&tsens1 1>; 3406 3407 trips { 3408 gpuss0_alert0: trip-point0 { 3409 temperature = <95000>; 3410 hysteresis = <2000>; 3411 type = "passive"; 3412 }; 3413 3414 gpuss0_crit: gpuss0-crit { 3415 temperature = <110000>; 3416 hysteresis = <0>; 3417 type = "critical"; 3418 }; 3419 }; 3420 3421 cooling-maps { 3422 map0 { 3423 trip = <&gpuss0_alert0>; 3424 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3425 }; 3426 }; 3427 }; 3428 3429 gpuss1-thermal { 3430 polling-delay-passive = <100>; 3431 polling-delay = <0>; 3432 3433 thermal-sensors = <&tsens1 2>; 3434 3435 trips { 3436 gpuss1_alert0: trip-point0 { 3437 temperature = <95000>; 3438 hysteresis = <2000>; 3439 type = "passive"; 3440 }; 3441 3442 gpuss1_crit: gpuss1-crit { 3443 temperature = <110000>; 3444 hysteresis = <0>; 3445 type = "critical"; 3446 }; 3447 }; 3448 3449 cooling-maps { 3450 map0 { 3451 trip = <&gpuss1_alert0>; 3452 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3453 }; 3454 }; 3455 }; 3456 3457 nspss0-thermal { 3458 polling-delay-passive = <0>; 3459 polling-delay = <0>; 3460 3461 thermal-sensors = <&tsens1 3>; 3462 3463 trips { 3464 nspss0_alert0: trip-point0 { 3465 temperature = <90000>; 3466 hysteresis = <2000>; 3467 type = "hot"; 3468 }; 3469 3470 nspss0_crit: nspss0-crit { 3471 temperature = <110000>; 3472 hysteresis = <0>; 3473 type = "critical"; 3474 }; 3475 }; 3476 }; 3477 3478 nspss1-thermal { 3479 polling-delay-passive = <0>; 3480 polling-delay = <0>; 3481 3482 thermal-sensors = <&tsens1 4>; 3483 3484 trips { 3485 nspss1_alert0: trip-point0 { 3486 temperature = <90000>; 3487 hysteresis = <2000>; 3488 type = "hot"; 3489 }; 3490 3491 nspss1_crit: nspss1-crit { 3492 temperature = <110000>; 3493 hysteresis = <0>; 3494 type = "critical"; 3495 }; 3496 }; 3497 }; 3498 3499 video-thermal { 3500 polling-delay-passive = <0>; 3501 polling-delay = <0>; 3502 3503 thermal-sensors = <&tsens1 5>; 3504 3505 trips { 3506 video_alert0: trip-point0 { 3507 temperature = <90000>; 3508 hysteresis = <2000>; 3509 type = "hot"; 3510 }; 3511 3512 video_crit: video-crit { 3513 temperature = <110000>; 3514 hysteresis = <0>; 3515 type = "critical"; 3516 }; 3517 }; 3518 }; 3519 3520 ddr-thermal { 3521 polling-delay-passive = <0>; 3522 polling-delay = <0>; 3523 3524 thermal-sensors = <&tsens1 6>; 3525 3526 trips { 3527 ddr_alert0: trip-point0 { 3528 temperature = <90000>; 3529 hysteresis = <2000>; 3530 type = "hot"; 3531 }; 3532 3533 ddr_crit: ddr-crit { 3534 temperature = <110000>; 3535 hysteresis = <0>; 3536 type = "critical"; 3537 }; 3538 }; 3539 }; 3540 3541 mdmss0-thermal { 3542 polling-delay-passive = <0>; 3543 polling-delay = <0>; 3544 3545 thermal-sensors = <&tsens1 7>; 3546 3547 trips { 3548 mdmss0_alert0: trip-point0 { 3549 temperature = <90000>; 3550 hysteresis = <2000>; 3551 type = "hot"; 3552 }; 3553 3554 mdmss0_crit: mdmss0-crit { 3555 temperature = <110000>; 3556 hysteresis = <0>; 3557 type = "critical"; 3558 }; 3559 }; 3560 }; 3561 3562 mdmss1-thermal { 3563 polling-delay-passive = <0>; 3564 polling-delay = <0>; 3565 3566 thermal-sensors = <&tsens1 8>; 3567 3568 trips { 3569 mdmss1_alert0: trip-point0 { 3570 temperature = <90000>; 3571 hysteresis = <2000>; 3572 type = "hot"; 3573 }; 3574 3575 mdmss1_crit: mdmss1-crit { 3576 temperature = <110000>; 3577 hysteresis = <0>; 3578 type = "critical"; 3579 }; 3580 }; 3581 }; 3582 3583 mdmss2-thermal { 3584 polling-delay-passive = <0>; 3585 polling-delay = <0>; 3586 3587 thermal-sensors = <&tsens1 9>; 3588 3589 trips { 3590 mdmss2_alert0: trip-point0 { 3591 temperature = <90000>; 3592 hysteresis = <2000>; 3593 type = "hot"; 3594 }; 3595 3596 mdmss2_crit: mdmss2-crit { 3597 temperature = <110000>; 3598 hysteresis = <0>; 3599 type = "critical"; 3600 }; 3601 }; 3602 }; 3603 3604 mdmss3-thermal { 3605 polling-delay-passive = <0>; 3606 polling-delay = <0>; 3607 3608 thermal-sensors = <&tsens1 10>; 3609 3610 trips { 3611 mdmss3_alert0: trip-point0 { 3612 temperature = <90000>; 3613 hysteresis = <2000>; 3614 type = "hot"; 3615 }; 3616 3617 mdmss3_crit: mdmss3-crit { 3618 temperature = <110000>; 3619 hysteresis = <0>; 3620 type = "critical"; 3621 }; 3622 }; 3623 }; 3624 3625 camera0-thermal { 3626 polling-delay-passive = <0>; 3627 polling-delay = <0>; 3628 3629 thermal-sensors = <&tsens1 11>; 3630 3631 trips { 3632 camera0_alert0: trip-point0 { 3633 temperature = <90000>; 3634 hysteresis = <2000>; 3635 type = "hot"; 3636 }; 3637 3638 camera0_crit: camera0-crit { 3639 temperature = <110000>; 3640 hysteresis = <0>; 3641 type = "critical"; 3642 }; 3643 }; 3644 }; 3645 }; 3646 3647 timer { 3648 compatible = "arm,armv8-timer"; 3649 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3650 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3651 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3652 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3653 }; 3654}; 3655