1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 next-level-cache = <&L3_0>; 186 L3_0: l3-cache { 187 compatible = "cache"; 188 cache-level = <3>; 189 }; 190 }; 191 }; 192 193 CPU1: cpu@100 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo"; 196 reg = <0x0 0x100>; 197 clocks = <&cpufreq_hw 0>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_100>; 203 operating-points-v2 = <&cpu0_opp_table>; 204 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 205 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 206 qcom,freq-domain = <&cpufreq_hw 0>; 207 #cooling-cells = <2>; 208 L2_100: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 next-level-cache = <&L3_0>; 212 }; 213 }; 214 215 CPU2: cpu@200 { 216 device_type = "cpu"; 217 compatible = "qcom,kryo"; 218 reg = <0x0 0x200>; 219 clocks = <&cpufreq_hw 0>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 next-level-cache = <&L2_200>; 225 operating-points-v2 = <&cpu0_opp_table>; 226 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 227 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 228 qcom,freq-domain = <&cpufreq_hw 0>; 229 #cooling-cells = <2>; 230 L2_200: l2-cache { 231 compatible = "cache"; 232 cache-level = <2>; 233 next-level-cache = <&L3_0>; 234 }; 235 }; 236 237 CPU3: cpu@300 { 238 device_type = "cpu"; 239 compatible = "qcom,kryo"; 240 reg = <0x0 0x300>; 241 clocks = <&cpufreq_hw 0>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 next-level-cache = <&L2_300>; 247 operating-points-v2 = <&cpu0_opp_table>; 248 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 249 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 250 qcom,freq-domain = <&cpufreq_hw 0>; 251 #cooling-cells = <2>; 252 L2_300: l2-cache { 253 compatible = "cache"; 254 cache-level = <2>; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU4: cpu@400 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo"; 262 reg = <0x0 0x400>; 263 clocks = <&cpufreq_hw 1>; 264 enable-method = "psci"; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 next-level-cache = <&L2_400>; 269 operating-points-v2 = <&cpu4_opp_table>; 270 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 271 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 272 qcom,freq-domain = <&cpufreq_hw 1>; 273 #cooling-cells = <2>; 274 L2_400: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU5: cpu@500 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo"; 284 reg = <0x0 0x500>; 285 clocks = <&cpufreq_hw 1>; 286 enable-method = "psci"; 287 cpu-idle-states = <&BIG_CPU_SLEEP_0 288 &BIG_CPU_SLEEP_1 289 &CLUSTER_SLEEP_0>; 290 next-level-cache = <&L2_500>; 291 operating-points-v2 = <&cpu4_opp_table>; 292 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 293 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 294 qcom,freq-domain = <&cpufreq_hw 1>; 295 #cooling-cells = <2>; 296 L2_500: l2-cache { 297 compatible = "cache"; 298 cache-level = <2>; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 CPU6: cpu@600 { 304 device_type = "cpu"; 305 compatible = "qcom,kryo"; 306 reg = <0x0 0x600>; 307 clocks = <&cpufreq_hw 1>; 308 enable-method = "psci"; 309 cpu-idle-states = <&BIG_CPU_SLEEP_0 310 &BIG_CPU_SLEEP_1 311 &CLUSTER_SLEEP_0>; 312 next-level-cache = <&L2_600>; 313 operating-points-v2 = <&cpu4_opp_table>; 314 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 315 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 316 qcom,freq-domain = <&cpufreq_hw 1>; 317 #cooling-cells = <2>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 cache-level = <2>; 321 next-level-cache = <&L3_0>; 322 }; 323 }; 324 325 CPU7: cpu@700 { 326 device_type = "cpu"; 327 compatible = "qcom,kryo"; 328 reg = <0x0 0x700>; 329 clocks = <&cpufreq_hw 2>; 330 enable-method = "psci"; 331 cpu-idle-states = <&BIG_CPU_SLEEP_0 332 &BIG_CPU_SLEEP_1 333 &CLUSTER_SLEEP_0>; 334 next-level-cache = <&L2_700>; 335 operating-points-v2 = <&cpu7_opp_table>; 336 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 337 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 338 qcom,freq-domain = <&cpufreq_hw 2>; 339 #cooling-cells = <2>; 340 L2_700: l2-cache { 341 compatible = "cache"; 342 cache-level = <2>; 343 next-level-cache = <&L3_0>; 344 }; 345 }; 346 347 cpu-map { 348 cluster0 { 349 core0 { 350 cpu = <&CPU0>; 351 }; 352 353 core1 { 354 cpu = <&CPU1>; 355 }; 356 357 core2 { 358 cpu = <&CPU2>; 359 }; 360 361 core3 { 362 cpu = <&CPU3>; 363 }; 364 365 core4 { 366 cpu = <&CPU4>; 367 }; 368 369 core5 { 370 cpu = <&CPU5>; 371 }; 372 373 core6 { 374 cpu = <&CPU6>; 375 }; 376 377 core7 { 378 cpu = <&CPU7>; 379 }; 380 }; 381 }; 382 383 idle-states { 384 entry-method = "psci"; 385 386 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 387 compatible = "arm,idle-state"; 388 idle-state-name = "little-power-down"; 389 arm,psci-suspend-param = <0x40000003>; 390 entry-latency-us = <549>; 391 exit-latency-us = <901>; 392 min-residency-us = <1774>; 393 local-timer-stop; 394 }; 395 396 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "little-rail-power-down"; 399 arm,psci-suspend-param = <0x40000004>; 400 entry-latency-us = <702>; 401 exit-latency-us = <915>; 402 min-residency-us = <4001>; 403 local-timer-stop; 404 }; 405 406 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "big-power-down"; 409 arm,psci-suspend-param = <0x40000003>; 410 entry-latency-us = <523>; 411 exit-latency-us = <1244>; 412 min-residency-us = <2207>; 413 local-timer-stop; 414 }; 415 416 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "big-rail-power-down"; 419 arm,psci-suspend-param = <0x40000004>; 420 entry-latency-us = <526>; 421 exit-latency-us = <1854>; 422 min-residency-us = <5555>; 423 local-timer-stop; 424 }; 425 426 CLUSTER_SLEEP_0: cluster-sleep-0 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "cluster-power-down"; 429 arm,psci-suspend-param = <0x40003444>; 430 entry-latency-us = <3263>; 431 exit-latency-us = <6562>; 432 min-residency-us = <9926>; 433 local-timer-stop; 434 }; 435 }; 436 }; 437 438 cpu0_opp_table: opp-table-cpu0 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 cpu0_opp_300mhz: opp-300000000 { 443 opp-hz = /bits/ 64 <300000000>; 444 opp-peak-kBps = <800000 9600000>; 445 }; 446 447 cpu0_opp_691mhz: opp-691200000 { 448 opp-hz = /bits/ 64 <691200000>; 449 opp-peak-kBps = <800000 17817600>; 450 }; 451 452 cpu0_opp_806mhz: opp-806400000 { 453 opp-hz = /bits/ 64 <806400000>; 454 opp-peak-kBps = <800000 20889600>; 455 }; 456 457 cpu0_opp_941mhz: opp-940800000 { 458 opp-hz = /bits/ 64 <940800000>; 459 opp-peak-kBps = <1804000 24576000>; 460 }; 461 462 cpu0_opp_1152mhz: opp-1152000000 { 463 opp-hz = /bits/ 64 <1152000000>; 464 opp-peak-kBps = <2188000 27033600>; 465 }; 466 467 cpu0_opp_1325mhz: opp-1324800000 { 468 opp-hz = /bits/ 64 <1324800000>; 469 opp-peak-kBps = <2188000 33792000>; 470 }; 471 472 cpu0_opp_1517mhz: opp-1516800000 { 473 opp-hz = /bits/ 64 <1516800000>; 474 opp-peak-kBps = <3072000 38092800>; 475 }; 476 477 cpu0_opp_1651mhz: opp-1651200000 { 478 opp-hz = /bits/ 64 <1651200000>; 479 opp-peak-kBps = <3072000 41779200>; 480 }; 481 482 cpu0_opp_1805mhz: opp-1804800000 { 483 opp-hz = /bits/ 64 <1804800000>; 484 opp-peak-kBps = <4068000 48537600>; 485 }; 486 487 cpu0_opp_1958mhz: opp-1958400000 { 488 opp-hz = /bits/ 64 <1958400000>; 489 opp-peak-kBps = <4068000 48537600>; 490 }; 491 492 cpu0_opp_2016mhz: opp-2016000000 { 493 opp-hz = /bits/ 64 <2016000000>; 494 opp-peak-kBps = <6220000 48537600>; 495 }; 496 }; 497 498 cpu4_opp_table: opp-table-cpu4 { 499 compatible = "operating-points-v2"; 500 opp-shared; 501 502 cpu4_opp_691mhz: opp-691200000 { 503 opp-hz = /bits/ 64 <691200000>; 504 opp-peak-kBps = <1804000 9600000>; 505 }; 506 507 cpu4_opp_941mhz: opp-940800000 { 508 opp-hz = /bits/ 64 <940800000>; 509 opp-peak-kBps = <2188000 17817600>; 510 }; 511 512 cpu4_opp_1229mhz: opp-1228800000 { 513 opp-hz = /bits/ 64 <1228800000>; 514 opp-peak-kBps = <4068000 24576000>; 515 }; 516 517 cpu4_opp_1344mhz: opp-1344000000 { 518 opp-hz = /bits/ 64 <1344000000>; 519 opp-peak-kBps = <4068000 24576000>; 520 }; 521 522 cpu4_opp_1517mhz: opp-1516800000 { 523 opp-hz = /bits/ 64 <1516800000>; 524 opp-peak-kBps = <4068000 24576000>; 525 }; 526 527 cpu4_opp_1651mhz: opp-1651200000 { 528 opp-hz = /bits/ 64 <1651200000>; 529 opp-peak-kBps = <6220000 38092800>; 530 }; 531 532 cpu4_opp_1901mhz: opp-1900800000 { 533 opp-hz = /bits/ 64 <1900800000>; 534 opp-peak-kBps = <6220000 44851200>; 535 }; 536 537 cpu4_opp_2054mhz: opp-2054400000 { 538 opp-hz = /bits/ 64 <2054400000>; 539 opp-peak-kBps = <6220000 44851200>; 540 }; 541 542 cpu4_opp_2112mhz: opp-2112000000 { 543 opp-hz = /bits/ 64 <2112000000>; 544 opp-peak-kBps = <6220000 44851200>; 545 }; 546 547 cpu4_opp_2131mhz: opp-2131200000 { 548 opp-hz = /bits/ 64 <2131200000>; 549 opp-peak-kBps = <6220000 44851200>; 550 }; 551 552 cpu4_opp_2208mhz: opp-2208000000 { 553 opp-hz = /bits/ 64 <2208000000>; 554 opp-peak-kBps = <6220000 44851200>; 555 }; 556 557 cpu4_opp_2400mhz: opp-2400000000 { 558 opp-hz = /bits/ 64 <2400000000>; 559 opp-peak-kBps = <8532000 48537600>; 560 }; 561 562 cpu4_opp_2611mhz: opp-2611200000 { 563 opp-hz = /bits/ 64 <2611200000>; 564 opp-peak-kBps = <8532000 48537600>; 565 }; 566 }; 567 568 cpu7_opp_table: opp-table-cpu7 { 569 compatible = "operating-points-v2"; 570 opp-shared; 571 572 cpu7_opp_806mhz: opp-806400000 { 573 opp-hz = /bits/ 64 <806400000>; 574 opp-peak-kBps = <1804000 9600000>; 575 }; 576 577 cpu7_opp_1056mhz: opp-1056000000 { 578 opp-hz = /bits/ 64 <1056000000>; 579 opp-peak-kBps = <2188000 17817600>; 580 }; 581 582 cpu7_opp_1325mhz: opp-1324800000 { 583 opp-hz = /bits/ 64 <1324800000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu7_opp_1517mhz: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu7_opp_1766mhz: opp-1766400000 { 593 opp-hz = /bits/ 64 <1766400000>; 594 opp-peak-kBps = <6220000 38092800>; 595 }; 596 597 cpu7_opp_1862mhz: opp-1862400000 { 598 opp-hz = /bits/ 64 <1862400000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu7_opp_2035mhz: opp-2035200000 { 603 opp-hz = /bits/ 64 <2035200000>; 604 opp-peak-kBps = <6220000 38092800>; 605 }; 606 607 cpu7_opp_2112mhz: opp-2112000000 { 608 opp-hz = /bits/ 64 <2112000000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu7_opp_2208mhz: opp-2208000000 { 613 opp-hz = /bits/ 64 <2208000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu7_opp_2381mhz: opp-2380800000 { 618 opp-hz = /bits/ 64 <2380800000>; 619 opp-peak-kBps = <6832000 44851200>; 620 }; 621 622 cpu7_opp_2400mhz: opp-2400000000 { 623 opp-hz = /bits/ 64 <2400000000>; 624 opp-peak-kBps = <8532000 48537600>; 625 }; 626 627 cpu7_opp_2515mhz: opp-2515200000 { 628 opp-hz = /bits/ 64 <2515200000>; 629 opp-peak-kBps = <8532000 48537600>; 630 }; 631 632 cpu7_opp_2707mhz: opp-2707200000 { 633 opp-hz = /bits/ 64 <2707200000>; 634 opp-peak-kBps = <8532000 48537600>; 635 }; 636 637 cpu7_opp_3014mhz: opp-3014400000 { 638 opp-hz = /bits/ 64 <3014400000>; 639 opp-peak-kBps = <8532000 48537600>; 640 }; 641 }; 642 643 memory@80000000 { 644 device_type = "memory"; 645 /* We expect the bootloader to fill in the size */ 646 reg = <0 0x80000000 0 0>; 647 }; 648 649 firmware { 650 scm { 651 compatible = "qcom,scm-sc7280", "qcom,scm"; 652 }; 653 }; 654 655 clk_virt: interconnect { 656 compatible = "qcom,sc7280-clk-virt"; 657 #interconnect-cells = <2>; 658 qcom,bcm-voters = <&apps_bcm_voter>; 659 }; 660 661 smem { 662 compatible = "qcom,smem"; 663 memory-region = <&smem_mem>; 664 hwlocks = <&tcsr_mutex 3>; 665 }; 666 667 smp2p-adsp { 668 compatible = "qcom,smp2p"; 669 qcom,smem = <443>, <429>; 670 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 671 IPCC_MPROC_SIGNAL_SMP2P 672 IRQ_TYPE_EDGE_RISING>; 673 mboxes = <&ipcc IPCC_CLIENT_LPASS 674 IPCC_MPROC_SIGNAL_SMP2P>; 675 676 qcom,local-pid = <0>; 677 qcom,remote-pid = <2>; 678 679 adsp_smp2p_out: master-kernel { 680 qcom,entry-name = "master-kernel"; 681 #qcom,smem-state-cells = <1>; 682 }; 683 684 adsp_smp2p_in: slave-kernel { 685 qcom,entry-name = "slave-kernel"; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 }; 689 }; 690 691 smp2p-cdsp { 692 compatible = "qcom,smp2p"; 693 qcom,smem = <94>, <432>; 694 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 695 IPCC_MPROC_SIGNAL_SMP2P 696 IRQ_TYPE_EDGE_RISING>; 697 mboxes = <&ipcc IPCC_CLIENT_CDSP 698 IPCC_MPROC_SIGNAL_SMP2P>; 699 700 qcom,local-pid = <0>; 701 qcom,remote-pid = <5>; 702 703 cdsp_smp2p_out: master-kernel { 704 qcom,entry-name = "master-kernel"; 705 #qcom,smem-state-cells = <1>; 706 }; 707 708 cdsp_smp2p_in: slave-kernel { 709 qcom,entry-name = "slave-kernel"; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 }; 713 }; 714 715 smp2p-mpss { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <435>, <428>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_MPSS 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <1>; 726 727 modem_smp2p_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 modem_smp2p_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 738 ipa_smp2p_out: ipa-ap-to-modem { 739 qcom,entry-name = "ipa"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 ipa_smp2p_in: ipa-modem-to-ap { 744 qcom,entry-name = "ipa"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-wpss { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <617>, <616>; 753 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 mboxes = <&ipcc IPCC_CLIENT_WPSS 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,local-pid = <0>; 760 qcom,remote-pid = <13>; 761 762 wpss_smp2p_out: master-kernel { 763 qcom,entry-name = "master-kernel"; 764 #qcom,smem-state-cells = <1>; 765 }; 766 767 wpss_smp2p_in: slave-kernel { 768 qcom,entry-name = "slave-kernel"; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 773 wlan_smp2p_out: wlan-ap-to-wpss { 774 qcom,entry-name = "wlan"; 775 #qcom,smem-state-cells = <1>; 776 }; 777 778 wlan_smp2p_in: wlan-wpss-to-ap { 779 qcom,entry-name = "wlan"; 780 interrupt-controller; 781 #interrupt-cells = <2>; 782 }; 783 }; 784 785 pmu { 786 compatible = "arm,armv8-pmuv3"; 787 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 788 }; 789 790 psci { 791 compatible = "arm,psci-1.0"; 792 method = "smc"; 793 }; 794 795 qspi_opp_table: opp-table-qspi { 796 compatible = "operating-points-v2"; 797 798 opp-75000000 { 799 opp-hz = /bits/ 64 <75000000>; 800 required-opps = <&rpmhpd_opp_low_svs>; 801 }; 802 803 opp-150000000 { 804 opp-hz = /bits/ 64 <150000000>; 805 required-opps = <&rpmhpd_opp_svs>; 806 }; 807 808 opp-200000000 { 809 opp-hz = /bits/ 64 <200000000>; 810 required-opps = <&rpmhpd_opp_svs_l1>; 811 }; 812 813 opp-300000000 { 814 opp-hz = /bits/ 64 <300000000>; 815 required-opps = <&rpmhpd_opp_nom>; 816 }; 817 }; 818 819 qup_opp_table: opp-table-qup { 820 compatible = "operating-points-v2"; 821 822 opp-75000000 { 823 opp-hz = /bits/ 64 <75000000>; 824 required-opps = <&rpmhpd_opp_low_svs>; 825 }; 826 827 opp-100000000 { 828 opp-hz = /bits/ 64 <100000000>; 829 required-opps = <&rpmhpd_opp_svs>; 830 }; 831 832 opp-128000000 { 833 opp-hz = /bits/ 64 <128000000>; 834 required-opps = <&rpmhpd_opp_nom>; 835 }; 836 }; 837 838 soc: soc@0 { 839 #address-cells = <2>; 840 #size-cells = <2>; 841 ranges = <0 0 0 0 0x10 0>; 842 dma-ranges = <0 0 0 0 0x10 0>; 843 compatible = "simple-bus"; 844 845 gcc: clock-controller@100000 { 846 compatible = "qcom,gcc-sc7280"; 847 reg = <0 0x00100000 0 0x1f0000>; 848 clocks = <&rpmhcc RPMH_CXO_CLK>, 849 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 850 <0>, <&pcie1_lane>, 851 <0>, <0>, <0>, <0>; 852 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 853 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 854 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 855 "ufs_phy_tx_symbol_0_clk", 856 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 857 #clock-cells = <1>; 858 #reset-cells = <1>; 859 #power-domain-cells = <1>; 860 power-domains = <&rpmhpd SC7280_CX>; 861 }; 862 863 ipcc: mailbox@408000 { 864 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 865 reg = <0 0x00408000 0 0x1000>; 866 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-controller; 868 #interrupt-cells = <3>; 869 #mbox-cells = <2>; 870 }; 871 872 qfprom: efuse@784000 { 873 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 874 reg = <0 0x00784000 0 0xa20>, 875 <0 0x00780000 0 0xa20>, 876 <0 0x00782000 0 0x120>, 877 <0 0x00786000 0 0x1fff>; 878 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 879 clock-names = "core"; 880 power-domains = <&rpmhpd SC7280_MX>; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 884 gpu_speed_bin: gpu_speed_bin@1e9 { 885 reg = <0x1e9 0x2>; 886 bits = <5 8>; 887 }; 888 }; 889 890 sdhc_1: mmc@7c4000 { 891 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 892 pinctrl-names = "default", "sleep"; 893 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 894 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 895 status = "disabled"; 896 897 reg = <0 0x007c4000 0 0x1000>, 898 <0 0x007c5000 0 0x1000>; 899 reg-names = "hc", "cqhci"; 900 901 iommus = <&apps_smmu 0xc0 0x0>; 902 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "hc_irq", "pwr_irq"; 905 906 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 907 <&gcc GCC_SDCC1_APPS_CLK>, 908 <&rpmhcc RPMH_CXO_CLK>; 909 clock-names = "iface", "core", "xo"; 910 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 912 interconnect-names = "sdhc-ddr","cpu-sdhc"; 913 power-domains = <&rpmhpd SC7280_CX>; 914 operating-points-v2 = <&sdhc1_opp_table>; 915 916 bus-width = <8>; 917 supports-cqe; 918 919 qcom,dll-config = <0x0007642c>; 920 qcom,ddr-config = <0x80040868>; 921 922 mmc-ddr-1_8v; 923 mmc-hs200-1_8v; 924 mmc-hs400-1_8v; 925 mmc-hs400-enhanced-strobe; 926 927 resets = <&gcc GCC_SDCC1_BCR>; 928 929 sdhc1_opp_table: opp-table { 930 compatible = "operating-points-v2"; 931 932 opp-100000000 { 933 opp-hz = /bits/ 64 <100000000>; 934 required-opps = <&rpmhpd_opp_low_svs>; 935 opp-peak-kBps = <1800000 400000>; 936 opp-avg-kBps = <100000 0>; 937 }; 938 939 opp-384000000 { 940 opp-hz = /bits/ 64 <384000000>; 941 required-opps = <&rpmhpd_opp_nom>; 942 opp-peak-kBps = <5400000 1600000>; 943 opp-avg-kBps = <390000 0>; 944 }; 945 }; 946 }; 947 948 gpi_dma0: dma-controller@900000 { 949 #dma-cells = <3>; 950 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 951 reg = <0 0x00900000 0 0x60000>; 952 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 964 dma-channels = <12>; 965 dma-channel-mask = <0x7f>; 966 iommus = <&apps_smmu 0x0136 0x0>; 967 status = "disabled"; 968 }; 969 970 qupv3_id_0: geniqup@9c0000 { 971 compatible = "qcom,geni-se-qup"; 972 reg = <0 0x009c0000 0 0x2000>; 973 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 974 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 975 clock-names = "m-ahb", "s-ahb"; 976 #address-cells = <2>; 977 #size-cells = <2>; 978 ranges; 979 iommus = <&apps_smmu 0x123 0x0>; 980 status = "disabled"; 981 982 i2c0: i2c@980000 { 983 compatible = "qcom,geni-i2c"; 984 reg = <0 0x00980000 0 0x4000>; 985 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 986 clock-names = "se"; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_i2c0_data_clk>; 989 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 994 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 995 interconnect-names = "qup-core", "qup-config", 996 "qup-memory"; 997 power-domains = <&rpmhpd SC7280_CX>; 998 required-opps = <&rpmhpd_opp_low_svs>; 999 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1000 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1001 dma-names = "tx", "rx"; 1002 status = "disabled"; 1003 }; 1004 1005 spi0: spi@980000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00980000 0 0x4000>; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1009 clock-names = "se"; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1012 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 power-domains = <&rpmhpd SC7280_CX>; 1016 operating-points-v2 = <&qup_opp_table>; 1017 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1019 interconnect-names = "qup-core", "qup-config"; 1020 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1021 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1022 dma-names = "tx", "rx"; 1023 status = "disabled"; 1024 }; 1025 1026 uart0: serial@980000 { 1027 compatible = "qcom,geni-uart"; 1028 reg = <0 0x00980000 0 0x4000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1030 clock-names = "se"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1033 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1034 power-domains = <&rpmhpd SC7280_CX>; 1035 operating-points-v2 = <&qup_opp_table>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1038 interconnect-names = "qup-core", "qup-config"; 1039 status = "disabled"; 1040 }; 1041 1042 i2c1: i2c@984000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00984000 0 0x4000>; 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1046 clock-names = "se"; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c1_data_clk>; 1049 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1053 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1054 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1055 interconnect-names = "qup-core", "qup-config", 1056 "qup-memory"; 1057 power-domains = <&rpmhpd SC7280_CX>; 1058 required-opps = <&rpmhpd_opp_low_svs>; 1059 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1060 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1061 dma-names = "tx", "rx"; 1062 status = "disabled"; 1063 }; 1064 1065 spi1: spi@984000 { 1066 compatible = "qcom,geni-spi"; 1067 reg = <0 0x00984000 0 0x4000>; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1069 clock-names = "se"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1072 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 power-domains = <&rpmhpd SC7280_CX>; 1076 operating-points-v2 = <&qup_opp_table>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1079 interconnect-names = "qup-core", "qup-config"; 1080 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1081 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1082 dma-names = "tx", "rx"; 1083 status = "disabled"; 1084 }; 1085 1086 uart1: serial@984000 { 1087 compatible = "qcom,geni-uart"; 1088 reg = <0 0x00984000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1093 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1094 power-domains = <&rpmhpd SC7280_CX>; 1095 operating-points-v2 = <&qup_opp_table>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1098 interconnect-names = "qup-core", "qup-config"; 1099 status = "disabled"; 1100 }; 1101 1102 i2c2: i2c@988000 { 1103 compatible = "qcom,geni-i2c"; 1104 reg = <0 0x00988000 0 0x4000>; 1105 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1106 clock-names = "se"; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&qup_i2c2_data_clk>; 1109 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1113 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1114 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1115 interconnect-names = "qup-core", "qup-config", 1116 "qup-memory"; 1117 power-domains = <&rpmhpd SC7280_CX>; 1118 required-opps = <&rpmhpd_opp_low_svs>; 1119 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1120 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1121 dma-names = "tx", "rx"; 1122 status = "disabled"; 1123 }; 1124 1125 spi2: spi@988000 { 1126 compatible = "qcom,geni-spi"; 1127 reg = <0 0x00988000 0 0x4000>; 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1129 clock-names = "se"; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1132 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 power-domains = <&rpmhpd SC7280_CX>; 1136 operating-points-v2 = <&qup_opp_table>; 1137 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1138 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1139 interconnect-names = "qup-core", "qup-config"; 1140 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1141 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1142 dma-names = "tx", "rx"; 1143 status = "disabled"; 1144 }; 1145 1146 uart2: serial@988000 { 1147 compatible = "qcom,geni-uart"; 1148 reg = <0 0x00988000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1153 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1154 power-domains = <&rpmhpd SC7280_CX>; 1155 operating-points-v2 = <&qup_opp_table>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1158 interconnect-names = "qup-core", "qup-config"; 1159 status = "disabled"; 1160 }; 1161 1162 i2c3: i2c@98c000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0 0x0098c000 0 0x4000>; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1166 clock-names = "se"; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&qup_i2c3_data_clk>; 1169 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1173 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1175 interconnect-names = "qup-core", "qup-config", 1176 "qup-memory"; 1177 power-domains = <&rpmhpd SC7280_CX>; 1178 required-opps = <&rpmhpd_opp_low_svs>; 1179 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1180 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1181 dma-names = "tx", "rx"; 1182 status = "disabled"; 1183 }; 1184 1185 spi3: spi@98c000 { 1186 compatible = "qcom,geni-spi"; 1187 reg = <0 0x0098c000 0 0x4000>; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1189 clock-names = "se"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1192 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 power-domains = <&rpmhpd SC7280_CX>; 1196 operating-points-v2 = <&qup_opp_table>; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1201 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1202 dma-names = "tx", "rx"; 1203 status = "disabled"; 1204 }; 1205 1206 uart3: serial@98c000 { 1207 compatible = "qcom,geni-uart"; 1208 reg = <0 0x0098c000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1213 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1214 power-domains = <&rpmhpd SC7280_CX>; 1215 operating-points-v2 = <&qup_opp_table>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1218 interconnect-names = "qup-core", "qup-config"; 1219 status = "disabled"; 1220 }; 1221 1222 i2c4: i2c@990000 { 1223 compatible = "qcom,geni-i2c"; 1224 reg = <0 0x00990000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1226 clock-names = "se"; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_i2c4_data_clk>; 1229 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1233 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1234 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1235 interconnect-names = "qup-core", "qup-config", 1236 "qup-memory"; 1237 power-domains = <&rpmhpd SC7280_CX>; 1238 required-opps = <&rpmhpd_opp_low_svs>; 1239 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1240 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1241 dma-names = "tx", "rx"; 1242 status = "disabled"; 1243 }; 1244 1245 spi4: spi@990000 { 1246 compatible = "qcom,geni-spi"; 1247 reg = <0 0x00990000 0 0x4000>; 1248 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1249 clock-names = "se"; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1252 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 power-domains = <&rpmhpd SC7280_CX>; 1256 operating-points-v2 = <&qup_opp_table>; 1257 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1258 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1259 interconnect-names = "qup-core", "qup-config"; 1260 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1261 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 uart4: serial@990000 { 1267 compatible = "qcom,geni-uart"; 1268 reg = <0 0x00990000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1273 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1274 power-domains = <&rpmhpd SC7280_CX>; 1275 operating-points-v2 = <&qup_opp_table>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1278 interconnect-names = "qup-core", "qup-config"; 1279 status = "disabled"; 1280 }; 1281 1282 i2c5: i2c@994000 { 1283 compatible = "qcom,geni-i2c"; 1284 reg = <0 0x00994000 0 0x4000>; 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1286 clock-names = "se"; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&qup_i2c5_data_clk>; 1289 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1293 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1294 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1295 interconnect-names = "qup-core", "qup-config", 1296 "qup-memory"; 1297 power-domains = <&rpmhpd SC7280_CX>; 1298 required-opps = <&rpmhpd_opp_low_svs>; 1299 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1300 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1301 dma-names = "tx", "rx"; 1302 status = "disabled"; 1303 }; 1304 1305 spi5: spi@994000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0 0x00994000 0 0x4000>; 1308 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1309 clock-names = "se"; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1312 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 power-domains = <&rpmhpd SC7280_CX>; 1316 operating-points-v2 = <&qup_opp_table>; 1317 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1318 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1319 interconnect-names = "qup-core", "qup-config"; 1320 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1321 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1322 dma-names = "tx", "rx"; 1323 status = "disabled"; 1324 }; 1325 1326 uart5: serial@994000 { 1327 compatible = "qcom,geni-uart"; 1328 reg = <0 0x00994000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1333 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1334 power-domains = <&rpmhpd SC7280_CX>; 1335 operating-points-v2 = <&qup_opp_table>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1338 interconnect-names = "qup-core", "qup-config"; 1339 status = "disabled"; 1340 }; 1341 1342 i2c6: i2c@998000 { 1343 compatible = "qcom,geni-i2c"; 1344 reg = <0 0x00998000 0 0x4000>; 1345 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1346 clock-names = "se"; 1347 pinctrl-names = "default"; 1348 pinctrl-0 = <&qup_i2c6_data_clk>; 1349 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1354 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", 1356 "qup-memory"; 1357 power-domains = <&rpmhpd SC7280_CX>; 1358 required-opps = <&rpmhpd_opp_low_svs>; 1359 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1360 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1361 dma-names = "tx", "rx"; 1362 status = "disabled"; 1363 }; 1364 1365 spi6: spi@998000 { 1366 compatible = "qcom,geni-spi"; 1367 reg = <0 0x00998000 0 0x4000>; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1369 clock-names = "se"; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1372 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 power-domains = <&rpmhpd SC7280_CX>; 1376 operating-points-v2 = <&qup_opp_table>; 1377 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1379 interconnect-names = "qup-core", "qup-config"; 1380 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1381 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1382 dma-names = "tx", "rx"; 1383 status = "disabled"; 1384 }; 1385 1386 uart6: serial@998000 { 1387 compatible = "qcom,geni-uart"; 1388 reg = <0 0x00998000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1393 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1394 power-domains = <&rpmhpd SC7280_CX>; 1395 operating-points-v2 = <&qup_opp_table>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1398 interconnect-names = "qup-core", "qup-config"; 1399 status = "disabled"; 1400 }; 1401 1402 i2c7: i2c@99c000 { 1403 compatible = "qcom,geni-i2c"; 1404 reg = <0 0x0099c000 0 0x4000>; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1406 clock-names = "se"; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_i2c7_data_clk>; 1409 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1413 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1414 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1415 interconnect-names = "qup-core", "qup-config", 1416 "qup-memory"; 1417 power-domains = <&rpmhpd SC7280_CX>; 1418 required-opps = <&rpmhpd_opp_low_svs>; 1419 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1420 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1421 dma-names = "tx", "rx"; 1422 status = "disabled"; 1423 }; 1424 1425 spi7: spi@99c000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x0099c000 0 0x4000>; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1429 clock-names = "se"; 1430 pinctrl-names = "default"; 1431 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1432 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 power-domains = <&rpmhpd SC7280_CX>; 1436 operating-points-v2 = <&qup_opp_table>; 1437 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1438 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1439 interconnect-names = "qup-core", "qup-config"; 1440 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1441 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1442 dma-names = "tx", "rx"; 1443 status = "disabled"; 1444 }; 1445 1446 uart7: serial@99c000 { 1447 compatible = "qcom,geni-uart"; 1448 reg = <0 0x0099c000 0 0x4000>; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1450 clock-names = "se"; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1453 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1454 power-domains = <&rpmhpd SC7280_CX>; 1455 operating-points-v2 = <&qup_opp_table>; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1457 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1458 interconnect-names = "qup-core", "qup-config"; 1459 status = "disabled"; 1460 }; 1461 }; 1462 1463 gpi_dma1: dma-controller@a00000 { 1464 #dma-cells = <3>; 1465 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1466 reg = <0 0x00a00000 0 0x60000>; 1467 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1479 dma-channels = <12>; 1480 dma-channel-mask = <0x1e>; 1481 iommus = <&apps_smmu 0x56 0x0>; 1482 status = "disabled"; 1483 }; 1484 1485 qupv3_id_1: geniqup@ac0000 { 1486 compatible = "qcom,geni-se-qup"; 1487 reg = <0 0x00ac0000 0 0x2000>; 1488 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1489 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1490 clock-names = "m-ahb", "s-ahb"; 1491 #address-cells = <2>; 1492 #size-cells = <2>; 1493 ranges; 1494 iommus = <&apps_smmu 0x43 0x0>; 1495 status = "disabled"; 1496 1497 i2c8: i2c@a80000 { 1498 compatible = "qcom,geni-i2c"; 1499 reg = <0 0x00a80000 0 0x4000>; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1501 clock-names = "se"; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_i2c8_data_clk>; 1504 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1508 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1509 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1510 interconnect-names = "qup-core", "qup-config", 1511 "qup-memory"; 1512 power-domains = <&rpmhpd SC7280_CX>; 1513 required-opps = <&rpmhpd_opp_low_svs>; 1514 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1515 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1516 dma-names = "tx", "rx"; 1517 status = "disabled"; 1518 }; 1519 1520 spi8: spi@a80000 { 1521 compatible = "qcom,geni-spi"; 1522 reg = <0 0x00a80000 0 0x4000>; 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1524 clock-names = "se"; 1525 pinctrl-names = "default"; 1526 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1527 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 power-domains = <&rpmhpd SC7280_CX>; 1531 operating-points-v2 = <&qup_opp_table>; 1532 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1533 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1534 interconnect-names = "qup-core", "qup-config"; 1535 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1536 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1537 dma-names = "tx", "rx"; 1538 status = "disabled"; 1539 }; 1540 1541 uart8: serial@a80000 { 1542 compatible = "qcom,geni-uart"; 1543 reg = <0 0x00a80000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1548 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1549 power-domains = <&rpmhpd SC7280_CX>; 1550 operating-points-v2 = <&qup_opp_table>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1552 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1553 interconnect-names = "qup-core", "qup-config"; 1554 status = "disabled"; 1555 }; 1556 1557 i2c9: i2c@a84000 { 1558 compatible = "qcom,geni-i2c"; 1559 reg = <0 0x00a84000 0 0x4000>; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1561 clock-names = "se"; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&qup_i2c9_data_clk>; 1564 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1568 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1569 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1570 interconnect-names = "qup-core", "qup-config", 1571 "qup-memory"; 1572 power-domains = <&rpmhpd SC7280_CX>; 1573 required-opps = <&rpmhpd_opp_low_svs>; 1574 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1575 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1576 dma-names = "tx", "rx"; 1577 status = "disabled"; 1578 }; 1579 1580 spi9: spi@a84000 { 1581 compatible = "qcom,geni-spi"; 1582 reg = <0 0x00a84000 0 0x4000>; 1583 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1584 clock-names = "se"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1587 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 power-domains = <&rpmhpd SC7280_CX>; 1591 operating-points-v2 = <&qup_opp_table>; 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1593 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1594 interconnect-names = "qup-core", "qup-config"; 1595 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1596 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1597 dma-names = "tx", "rx"; 1598 status = "disabled"; 1599 }; 1600 1601 uart9: serial@a84000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0 0x00a84000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1605 clock-names = "se"; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1608 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1609 power-domains = <&rpmhpd SC7280_CX>; 1610 operating-points-v2 = <&qup_opp_table>; 1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1612 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1613 interconnect-names = "qup-core", "qup-config"; 1614 status = "disabled"; 1615 }; 1616 1617 i2c10: i2c@a88000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0 0x00a88000 0 0x4000>; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 clock-names = "se"; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_i2c10_data_clk>; 1624 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1628 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1629 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1630 interconnect-names = "qup-core", "qup-config", 1631 "qup-memory"; 1632 power-domains = <&rpmhpd SC7280_CX>; 1633 required-opps = <&rpmhpd_opp_low_svs>; 1634 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1635 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1636 dma-names = "tx", "rx"; 1637 status = "disabled"; 1638 }; 1639 1640 spi10: spi@a88000 { 1641 compatible = "qcom,geni-spi"; 1642 reg = <0 0x00a88000 0 0x4000>; 1643 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1644 clock-names = "se"; 1645 pinctrl-names = "default"; 1646 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1647 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1648 #address-cells = <1>; 1649 #size-cells = <0>; 1650 power-domains = <&rpmhpd SC7280_CX>; 1651 operating-points-v2 = <&qup_opp_table>; 1652 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1654 interconnect-names = "qup-core", "qup-config"; 1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1656 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1657 dma-names = "tx", "rx"; 1658 status = "disabled"; 1659 }; 1660 1661 uart10: serial@a88000 { 1662 compatible = "qcom,geni-uart"; 1663 reg = <0 0x00a88000 0 0x4000>; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1665 clock-names = "se"; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1669 power-domains = <&rpmhpd SC7280_CX>; 1670 operating-points-v2 = <&qup_opp_table>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1673 interconnect-names = "qup-core", "qup-config"; 1674 status = "disabled"; 1675 }; 1676 1677 i2c11: i2c@a8c000 { 1678 compatible = "qcom,geni-i2c"; 1679 reg = <0 0x00a8c000 0 0x4000>; 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1681 clock-names = "se"; 1682 pinctrl-names = "default"; 1683 pinctrl-0 = <&qup_i2c11_data_clk>; 1684 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1688 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1689 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1690 interconnect-names = "qup-core", "qup-config", 1691 "qup-memory"; 1692 power-domains = <&rpmhpd SC7280_CX>; 1693 required-opps = <&rpmhpd_opp_low_svs>; 1694 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1695 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1696 dma-names = "tx", "rx"; 1697 status = "disabled"; 1698 }; 1699 1700 spi11: spi@a8c000 { 1701 compatible = "qcom,geni-spi"; 1702 reg = <0 0x00a8c000 0 0x4000>; 1703 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1704 clock-names = "se"; 1705 pinctrl-names = "default"; 1706 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1707 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 power-domains = <&rpmhpd SC7280_CX>; 1711 operating-points-v2 = <&qup_opp_table>; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1714 interconnect-names = "qup-core", "qup-config"; 1715 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1716 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1717 dma-names = "tx", "rx"; 1718 status = "disabled"; 1719 }; 1720 1721 uart11: serial@a8c000 { 1722 compatible = "qcom,geni-uart"; 1723 reg = <0 0x00a8c000 0 0x4000>; 1724 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1725 clock-names = "se"; 1726 pinctrl-names = "default"; 1727 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1728 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1729 power-domains = <&rpmhpd SC7280_CX>; 1730 operating-points-v2 = <&qup_opp_table>; 1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1732 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1733 interconnect-names = "qup-core", "qup-config"; 1734 status = "disabled"; 1735 }; 1736 1737 i2c12: i2c@a90000 { 1738 compatible = "qcom,geni-i2c"; 1739 reg = <0 0x00a90000 0 0x4000>; 1740 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1741 clock-names = "se"; 1742 pinctrl-names = "default"; 1743 pinctrl-0 = <&qup_i2c12_data_clk>; 1744 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1748 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1749 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1750 interconnect-names = "qup-core", "qup-config", 1751 "qup-memory"; 1752 power-domains = <&rpmhpd SC7280_CX>; 1753 required-opps = <&rpmhpd_opp_low_svs>; 1754 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1755 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1756 dma-names = "tx", "rx"; 1757 status = "disabled"; 1758 }; 1759 1760 spi12: spi@a90000 { 1761 compatible = "qcom,geni-spi"; 1762 reg = <0 0x00a90000 0 0x4000>; 1763 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1764 clock-names = "se"; 1765 pinctrl-names = "default"; 1766 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1767 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 power-domains = <&rpmhpd SC7280_CX>; 1771 operating-points-v2 = <&qup_opp_table>; 1772 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1773 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1774 interconnect-names = "qup-core", "qup-config"; 1775 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1776 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1777 dma-names = "tx", "rx"; 1778 status = "disabled"; 1779 }; 1780 1781 uart12: serial@a90000 { 1782 compatible = "qcom,geni-uart"; 1783 reg = <0 0x00a90000 0 0x4000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1785 clock-names = "se"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1788 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1789 power-domains = <&rpmhpd SC7280_CX>; 1790 operating-points-v2 = <&qup_opp_table>; 1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1792 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1793 interconnect-names = "qup-core", "qup-config"; 1794 status = "disabled"; 1795 }; 1796 1797 i2c13: i2c@a94000 { 1798 compatible = "qcom,geni-i2c"; 1799 reg = <0 0x00a94000 0 0x4000>; 1800 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1801 clock-names = "se"; 1802 pinctrl-names = "default"; 1803 pinctrl-0 = <&qup_i2c13_data_clk>; 1804 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1808 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1809 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1810 interconnect-names = "qup-core", "qup-config", 1811 "qup-memory"; 1812 power-domains = <&rpmhpd SC7280_CX>; 1813 required-opps = <&rpmhpd_opp_low_svs>; 1814 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1815 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1816 dma-names = "tx", "rx"; 1817 status = "disabled"; 1818 }; 1819 1820 spi13: spi@a94000 { 1821 compatible = "qcom,geni-spi"; 1822 reg = <0 0x00a94000 0 0x4000>; 1823 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1824 clock-names = "se"; 1825 pinctrl-names = "default"; 1826 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1827 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 power-domains = <&rpmhpd SC7280_CX>; 1831 operating-points-v2 = <&qup_opp_table>; 1832 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1833 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1834 interconnect-names = "qup-core", "qup-config"; 1835 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1836 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1837 dma-names = "tx", "rx"; 1838 status = "disabled"; 1839 }; 1840 1841 uart13: serial@a94000 { 1842 compatible = "qcom,geni-uart"; 1843 reg = <0 0x00a94000 0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1845 clock-names = "se"; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1848 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1849 power-domains = <&rpmhpd SC7280_CX>; 1850 operating-points-v2 = <&qup_opp_table>; 1851 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1852 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1853 interconnect-names = "qup-core", "qup-config"; 1854 status = "disabled"; 1855 }; 1856 1857 i2c14: i2c@a98000 { 1858 compatible = "qcom,geni-i2c"; 1859 reg = <0 0x00a98000 0 0x4000>; 1860 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1861 clock-names = "se"; 1862 pinctrl-names = "default"; 1863 pinctrl-0 = <&qup_i2c14_data_clk>; 1864 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1868 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1869 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1870 interconnect-names = "qup-core", "qup-config", 1871 "qup-memory"; 1872 power-domains = <&rpmhpd SC7280_CX>; 1873 required-opps = <&rpmhpd_opp_low_svs>; 1874 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1875 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1876 dma-names = "tx", "rx"; 1877 status = "disabled"; 1878 }; 1879 1880 spi14: spi@a98000 { 1881 compatible = "qcom,geni-spi"; 1882 reg = <0 0x00a98000 0 0x4000>; 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1884 clock-names = "se"; 1885 pinctrl-names = "default"; 1886 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1887 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 power-domains = <&rpmhpd SC7280_CX>; 1891 operating-points-v2 = <&qup_opp_table>; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1893 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1894 interconnect-names = "qup-core", "qup-config"; 1895 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1896 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1897 dma-names = "tx", "rx"; 1898 status = "disabled"; 1899 }; 1900 1901 uart14: serial@a98000 { 1902 compatible = "qcom,geni-uart"; 1903 reg = <0 0x00a98000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1908 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1909 power-domains = <&rpmhpd SC7280_CX>; 1910 operating-points-v2 = <&qup_opp_table>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1913 interconnect-names = "qup-core", "qup-config"; 1914 status = "disabled"; 1915 }; 1916 1917 i2c15: i2c@a9c000 { 1918 compatible = "qcom,geni-i2c"; 1919 reg = <0 0x00a9c000 0 0x4000>; 1920 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1921 clock-names = "se"; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&qup_i2c15_data_clk>; 1924 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1928 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1929 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1930 interconnect-names = "qup-core", "qup-config", 1931 "qup-memory"; 1932 power-domains = <&rpmhpd SC7280_CX>; 1933 required-opps = <&rpmhpd_opp_low_svs>; 1934 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1935 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1936 dma-names = "tx", "rx"; 1937 status = "disabled"; 1938 }; 1939 1940 spi15: spi@a9c000 { 1941 compatible = "qcom,geni-spi"; 1942 reg = <0 0x00a9c000 0 0x4000>; 1943 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1944 clock-names = "se"; 1945 pinctrl-names = "default"; 1946 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1947 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1948 #address-cells = <1>; 1949 #size-cells = <0>; 1950 power-domains = <&rpmhpd SC7280_CX>; 1951 operating-points-v2 = <&qup_opp_table>; 1952 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1953 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1954 interconnect-names = "qup-core", "qup-config"; 1955 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1956 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1957 dma-names = "tx", "rx"; 1958 status = "disabled"; 1959 }; 1960 1961 uart15: serial@a9c000 { 1962 compatible = "qcom,geni-uart"; 1963 reg = <0 0x00a9c000 0 0x4000>; 1964 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1965 clock-names = "se"; 1966 pinctrl-names = "default"; 1967 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1968 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1969 power-domains = <&rpmhpd SC7280_CX>; 1970 operating-points-v2 = <&qup_opp_table>; 1971 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1972 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1973 interconnect-names = "qup-core", "qup-config"; 1974 status = "disabled"; 1975 }; 1976 }; 1977 1978 cnoc2: interconnect@1500000 { 1979 reg = <0 0x01500000 0 0x1000>; 1980 compatible = "qcom,sc7280-cnoc2"; 1981 #interconnect-cells = <2>; 1982 qcom,bcm-voters = <&apps_bcm_voter>; 1983 }; 1984 1985 cnoc3: interconnect@1502000 { 1986 reg = <0 0x01502000 0 0x1000>; 1987 compatible = "qcom,sc7280-cnoc3"; 1988 #interconnect-cells = <2>; 1989 qcom,bcm-voters = <&apps_bcm_voter>; 1990 }; 1991 1992 mc_virt: interconnect@1580000 { 1993 reg = <0 0x01580000 0 0x4>; 1994 compatible = "qcom,sc7280-mc-virt"; 1995 #interconnect-cells = <2>; 1996 qcom,bcm-voters = <&apps_bcm_voter>; 1997 }; 1998 1999 system_noc: interconnect@1680000 { 2000 reg = <0 0x01680000 0 0x15480>; 2001 compatible = "qcom,sc7280-system-noc"; 2002 #interconnect-cells = <2>; 2003 qcom,bcm-voters = <&apps_bcm_voter>; 2004 }; 2005 2006 aggre1_noc: interconnect@16e0000 { 2007 compatible = "qcom,sc7280-aggre1-noc"; 2008 reg = <0 0x016e0000 0 0x1c080>; 2009 #interconnect-cells = <2>; 2010 qcom,bcm-voters = <&apps_bcm_voter>; 2011 }; 2012 2013 aggre2_noc: interconnect@1700000 { 2014 reg = <0 0x01700000 0 0x2b080>; 2015 compatible = "qcom,sc7280-aggre2-noc"; 2016 #interconnect-cells = <2>; 2017 qcom,bcm-voters = <&apps_bcm_voter>; 2018 }; 2019 2020 mmss_noc: interconnect@1740000 { 2021 reg = <0 0x01740000 0 0x1e080>; 2022 compatible = "qcom,sc7280-mmss-noc"; 2023 #interconnect-cells = <2>; 2024 qcom,bcm-voters = <&apps_bcm_voter>; 2025 }; 2026 2027 wifi: wifi@17a10040 { 2028 compatible = "qcom,wcn6750-wifi"; 2029 reg = <0 0x17a10040 0 0x0>; 2030 iommus = <&apps_smmu 0x1c00 0x1>; 2031 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2063 qcom,rproc = <&remoteproc_wpss>; 2064 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2065 status = "disabled"; 2066 qcom,smem-states = <&wlan_smp2p_out 0>; 2067 qcom,smem-state-names = "wlan-smp2p-out"; 2068 }; 2069 2070 pcie1: pci@1c08000 { 2071 compatible = "qcom,pcie-sc7280"; 2072 reg = <0 0x01c08000 0 0x3000>, 2073 <0 0x40000000 0 0xf1d>, 2074 <0 0x40000f20 0 0xa8>, 2075 <0 0x40001000 0 0x1000>, 2076 <0 0x40100000 0 0x100000>; 2077 2078 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2079 device_type = "pci"; 2080 linux,pci-domain = <1>; 2081 bus-range = <0x00 0xff>; 2082 num-lanes = <2>; 2083 2084 #address-cells = <3>; 2085 #size-cells = <2>; 2086 2087 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2088 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2089 2090 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2091 interrupt-names = "msi"; 2092 #interrupt-cells = <1>; 2093 interrupt-map-mask = <0 0 0 0x7>; 2094 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2095 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2096 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2097 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2098 2099 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2100 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2101 <&pcie1_lane>, 2102 <&rpmhcc RPMH_CXO_CLK>, 2103 <&gcc GCC_PCIE_1_AUX_CLK>, 2104 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2105 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2106 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2107 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2108 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2109 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2110 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2111 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2112 2113 clock-names = "pipe", 2114 "pipe_mux", 2115 "phy_pipe", 2116 "ref", 2117 "aux", 2118 "cfg", 2119 "bus_master", 2120 "bus_slave", 2121 "slave_q2a", 2122 "tbu", 2123 "ddrss_sf_tbu", 2124 "aggre0", 2125 "aggre1"; 2126 2127 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2128 assigned-clock-rates = <19200000>; 2129 2130 resets = <&gcc GCC_PCIE_1_BCR>; 2131 reset-names = "pci"; 2132 2133 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2134 2135 phys = <&pcie1_lane>; 2136 phy-names = "pciephy"; 2137 2138 pinctrl-names = "default"; 2139 pinctrl-0 = <&pcie1_clkreq_n>; 2140 2141 dma-coherent; 2142 2143 iommus = <&apps_smmu 0x1c80 0x1>; 2144 2145 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2146 <0x100 &apps_smmu 0x1c81 0x1>; 2147 2148 status = "disabled"; 2149 }; 2150 2151 pcie1_phy: phy@1c0e000 { 2152 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2153 reg = <0 0x01c0e000 0 0x1c0>; 2154 #address-cells = <2>; 2155 #size-cells = <2>; 2156 ranges; 2157 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2158 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2159 <&gcc GCC_PCIE_CLKREF_EN>, 2160 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2161 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2162 2163 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2164 reset-names = "phy"; 2165 2166 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2167 assigned-clock-rates = <100000000>; 2168 2169 status = "disabled"; 2170 2171 pcie1_lane: phy@1c0e200 { 2172 reg = <0 0x01c0e200 0 0x170>, 2173 <0 0x01c0e400 0 0x200>, 2174 <0 0x01c0ea00 0 0x1f0>, 2175 <0 0x01c0e600 0 0x170>, 2176 <0 0x01c0e800 0 0x200>, 2177 <0 0x01c0ee00 0 0xf4>; 2178 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2179 clock-names = "pipe0"; 2180 2181 #phy-cells = <0>; 2182 #clock-cells = <0>; 2183 clock-output-names = "pcie_1_pipe_clk"; 2184 }; 2185 }; 2186 2187 ipa: ipa@1e40000 { 2188 compatible = "qcom,sc7280-ipa"; 2189 2190 iommus = <&apps_smmu 0x480 0x0>, 2191 <&apps_smmu 0x482 0x0>; 2192 reg = <0 0x01e40000 0 0x8000>, 2193 <0 0x01e50000 0 0x4ad0>, 2194 <0 0x01e04000 0 0x23000>; 2195 reg-names = "ipa-reg", 2196 "ipa-shared", 2197 "gsi"; 2198 2199 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2200 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2201 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2202 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2203 interrupt-names = "ipa", 2204 "gsi", 2205 "ipa-clock-query", 2206 "ipa-setup-ready"; 2207 2208 clocks = <&rpmhcc RPMH_IPA_CLK>; 2209 clock-names = "core"; 2210 2211 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2212 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2213 interconnect-names = "memory", 2214 "config"; 2215 2216 qcom,qmp = <&aoss_qmp>; 2217 2218 qcom,smem-states = <&ipa_smp2p_out 0>, 2219 <&ipa_smp2p_out 1>; 2220 qcom,smem-state-names = "ipa-clock-enabled-valid", 2221 "ipa-clock-enabled"; 2222 2223 status = "disabled"; 2224 }; 2225 2226 tcsr_mutex: hwlock@1f40000 { 2227 compatible = "qcom,tcsr-mutex"; 2228 reg = <0 0x01f40000 0 0x20000>; 2229 #hwlock-cells = <1>; 2230 }; 2231 2232 tcsr_1: syscon@1f60000 { 2233 compatible = "qcom,sc7280-tcsr", "syscon"; 2234 reg = <0 0x01f60000 0 0x20000>; 2235 }; 2236 2237 tcsr_2: syscon@1fc0000 { 2238 compatible = "qcom,sc7280-tcsr", "syscon"; 2239 reg = <0 0x01fc0000 0 0x30000>; 2240 }; 2241 2242 lpasscc: lpasscc@3000000 { 2243 compatible = "qcom,sc7280-lpasscc"; 2244 reg = <0 0x03000000 0 0x40>, 2245 <0 0x03c04000 0 0x4>; 2246 reg-names = "qdsp6ss", "top_cc"; 2247 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2248 clock-names = "iface"; 2249 #clock-cells = <1>; 2250 }; 2251 2252 lpass_rx_macro: codec@3200000 { 2253 compatible = "qcom,sc7280-lpass-rx-macro"; 2254 reg = <0 0x03200000 0 0x1000>; 2255 2256 pinctrl-names = "default"; 2257 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2258 2259 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2260 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2261 <&lpass_va_macro>; 2262 clock-names = "mclk", "npl", "fsgen"; 2263 2264 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2265 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2266 power-domain-names = "macro", "dcodec"; 2267 2268 #clock-cells = <0>; 2269 #sound-dai-cells = <1>; 2270 2271 status = "disabled"; 2272 }; 2273 2274 swr0: soundwire@3210000 { 2275 compatible = "qcom,soundwire-v1.6.0"; 2276 reg = <0 0x03210000 0 0x2000>; 2277 2278 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&lpass_rx_macro>; 2280 clock-names = "iface"; 2281 2282 qcom,din-ports = <0>; 2283 qcom,dout-ports = <5>; 2284 2285 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2286 reset-names = "swr_audio_cgcr"; 2287 2288 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2289 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2290 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2291 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2292 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2293 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2294 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2295 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2296 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2297 2298 #sound-dai-cells = <1>; 2299 #address-cells = <2>; 2300 #size-cells = <0>; 2301 2302 status = "disabled"; 2303 }; 2304 2305 lpass_tx_macro: codec@3220000 { 2306 compatible = "qcom,sc7280-lpass-tx-macro"; 2307 reg = <0 0x03220000 0 0x1000>; 2308 2309 pinctrl-names = "default"; 2310 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2311 2312 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2313 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2314 <&lpass_va_macro>; 2315 clock-names = "mclk", "npl", "fsgen"; 2316 2317 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2318 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2319 power-domain-names = "macro", "dcodec"; 2320 2321 #clock-cells = <0>; 2322 #sound-dai-cells = <1>; 2323 2324 status = "disabled"; 2325 }; 2326 2327 swr1: soundwire@3230000 { 2328 compatible = "qcom,soundwire-v1.6.0"; 2329 reg = <0 0x03230000 0 0x2000>; 2330 2331 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2332 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2333 clocks = <&lpass_tx_macro>; 2334 clock-names = "iface"; 2335 2336 qcom,din-ports = <3>; 2337 qcom,dout-ports = <0>; 2338 2339 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2340 reset-names = "swr_audio_cgcr"; 2341 2342 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2343 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2344 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2345 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2346 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2347 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2348 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2349 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2350 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2351 2352 #sound-dai-cells = <1>; 2353 #address-cells = <2>; 2354 #size-cells = <0>; 2355 2356 status = "disabled"; 2357 }; 2358 2359 lpass_audiocc: clock-controller@3300000 { 2360 compatible = "qcom,sc7280-lpassaudiocc"; 2361 reg = <0 0x03300000 0 0x30000>, 2362 <0 0x032a9000 0 0x1000>; 2363 clocks = <&rpmhcc RPMH_CXO_CLK>, 2364 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2365 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2366 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2367 #clock-cells = <1>; 2368 #power-domain-cells = <1>; 2369 #reset-cells = <1>; 2370 }; 2371 2372 lpass_va_macro: codec@3370000 { 2373 compatible = "qcom,sc7280-lpass-va-macro"; 2374 reg = <0 0x03370000 0 0x1000>; 2375 2376 pinctrl-names = "default"; 2377 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2378 2379 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2380 clock-names = "mclk"; 2381 2382 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2383 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2384 power-domain-names = "macro", "dcodec"; 2385 2386 #clock-cells = <0>; 2387 #sound-dai-cells = <1>; 2388 2389 status = "disabled"; 2390 }; 2391 2392 lpass_aon: clock-controller@3380000 { 2393 compatible = "qcom,sc7280-lpassaoncc"; 2394 reg = <0 0x03380000 0 0x30000>; 2395 clocks = <&rpmhcc RPMH_CXO_CLK>, 2396 <&rpmhcc RPMH_CXO_CLK_A>, 2397 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2398 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2399 #clock-cells = <1>; 2400 #power-domain-cells = <1>; 2401 }; 2402 2403 lpass_core: clock-controller@3900000 { 2404 compatible = "qcom,sc7280-lpasscorecc"; 2405 reg = <0 0x03900000 0 0x50000>; 2406 clocks = <&rpmhcc RPMH_CXO_CLK>; 2407 clock-names = "bi_tcxo"; 2408 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2409 #clock-cells = <1>; 2410 #power-domain-cells = <1>; 2411 }; 2412 2413 lpass_cpu: audio@3987000 { 2414 compatible = "qcom,sc7280-lpass-cpu"; 2415 2416 reg = <0 0x03987000 0 0x68000>, 2417 <0 0x03b00000 0 0x29000>, 2418 <0 0x03260000 0 0xc000>, 2419 <0 0x03280000 0 0x29000>, 2420 <0 0x03340000 0 0x29000>, 2421 <0 0x0336c000 0 0x3000>; 2422 reg-names = "lpass-hdmiif", 2423 "lpass-lpaif", 2424 "lpass-rxtx-cdc-dma-lpm", 2425 "lpass-rxtx-lpaif", 2426 "lpass-va-lpaif", 2427 "lpass-va-cdc-dma-lpm"; 2428 2429 iommus = <&apps_smmu 0x1820 0>, 2430 <&apps_smmu 0x1821 0>, 2431 <&apps_smmu 0x1832 0>; 2432 2433 power-domains = <&rpmhpd SC7280_LCX>; 2434 power-domain-names = "lcx"; 2435 required-opps = <&rpmhpd_opp_nom>; 2436 2437 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2438 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2439 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2440 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2441 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2442 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2443 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2444 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2445 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2446 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2447 clock-names = "aon_cc_audio_hm_h", 2448 "audio_cc_ext_mclk0", 2449 "core_cc_sysnoc_mport_core", 2450 "core_cc_ext_if0_ibit", 2451 "core_cc_ext_if1_ibit", 2452 "audio_cc_codec_mem", 2453 "audio_cc_codec_mem0", 2454 "audio_cc_codec_mem1", 2455 "audio_cc_codec_mem2", 2456 "aon_cc_va_mem0"; 2457 2458 #sound-dai-cells = <1>; 2459 #address-cells = <1>; 2460 #size-cells = <0>; 2461 2462 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2466 interrupt-names = "lpass-irq-lpaif", 2467 "lpass-irq-hdmi", 2468 "lpass-irq-vaif", 2469 "lpass-irq-rxtxif"; 2470 2471 status = "disabled"; 2472 }; 2473 2474 lpass_hm: clock-controller@3c00000 { 2475 compatible = "qcom,sc7280-lpasshm"; 2476 reg = <0 0x03c00000 0 0x28>; 2477 clocks = <&rpmhcc RPMH_CXO_CLK>; 2478 clock-names = "bi_tcxo"; 2479 #clock-cells = <1>; 2480 #power-domain-cells = <1>; 2481 }; 2482 2483 lpass_ag_noc: interconnect@3c40000 { 2484 reg = <0 0x03c40000 0 0xf080>; 2485 compatible = "qcom,sc7280-lpass-ag-noc"; 2486 #interconnect-cells = <2>; 2487 qcom,bcm-voters = <&apps_bcm_voter>; 2488 }; 2489 2490 lpass_tlmm: pinctrl@33c0000 { 2491 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2492 reg = <0 0x033c0000 0x0 0x20000>, 2493 <0 0x03550000 0x0 0x10000>; 2494 qcom,adsp-bypass-mode; 2495 gpio-controller; 2496 #gpio-cells = <2>; 2497 gpio-ranges = <&lpass_tlmm 0 0 15>; 2498 2499 lpass_dmic01_clk: dmic01-clk-state { 2500 pins = "gpio6"; 2501 function = "dmic1_clk"; 2502 }; 2503 2504 lpass_dmic01_data: dmic01-data-state { 2505 pins = "gpio7"; 2506 function = "dmic1_data"; 2507 }; 2508 2509 lpass_dmic23_clk: dmic23-clk-state { 2510 pins = "gpio8"; 2511 function = "dmic2_clk"; 2512 }; 2513 2514 lpass_dmic23_data: dmic23-data-state { 2515 pins = "gpio9"; 2516 function = "dmic2_data"; 2517 }; 2518 2519 lpass_rx_swr_clk: rx-swr-clk-state { 2520 pins = "gpio3"; 2521 function = "swr_rx_clk"; 2522 }; 2523 2524 lpass_rx_swr_data: rx-swr-data-state { 2525 pins = "gpio4", "gpio5"; 2526 function = "swr_rx_data"; 2527 }; 2528 2529 lpass_tx_swr_clk: tx-swr-clk-state { 2530 pins = "gpio0"; 2531 function = "swr_tx_clk"; 2532 }; 2533 2534 lpass_tx_swr_data: tx-swr-data-state { 2535 pins = "gpio1", "gpio2", "gpio14"; 2536 function = "swr_tx_data"; 2537 }; 2538 }; 2539 2540 gpu: gpu@3d00000 { 2541 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2542 reg = <0 0x03d00000 0 0x40000>, 2543 <0 0x03d9e000 0 0x1000>, 2544 <0 0x03d61000 0 0x800>; 2545 reg-names = "kgsl_3d0_reg_memory", 2546 "cx_mem", 2547 "cx_dbgc"; 2548 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2549 iommus = <&adreno_smmu 0 0x401>; 2550 operating-points-v2 = <&gpu_opp_table>; 2551 qcom,gmu = <&gmu>; 2552 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2553 interconnect-names = "gfx-mem"; 2554 #cooling-cells = <2>; 2555 2556 nvmem-cells = <&gpu_speed_bin>; 2557 nvmem-cell-names = "speed_bin"; 2558 2559 gpu_opp_table: opp-table { 2560 compatible = "operating-points-v2"; 2561 2562 opp-315000000 { 2563 opp-hz = /bits/ 64 <315000000>; 2564 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2565 opp-peak-kBps = <1804000>; 2566 opp-supported-hw = <0x03>; 2567 }; 2568 2569 opp-450000000 { 2570 opp-hz = /bits/ 64 <450000000>; 2571 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2572 opp-peak-kBps = <4068000>; 2573 opp-supported-hw = <0x03>; 2574 }; 2575 2576 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2577 opp-550000000-0 { 2578 opp-hz = /bits/ 64 <550000000>; 2579 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2580 opp-peak-kBps = <8368000>; 2581 opp-supported-hw = <0x01>; 2582 }; 2583 2584 opp-550000000-1 { 2585 opp-hz = /bits/ 64 <550000000>; 2586 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2587 opp-peak-kBps = <6832000>; 2588 opp-supported-hw = <0x02>; 2589 }; 2590 2591 opp-608000000 { 2592 opp-hz = /bits/ 64 <608000000>; 2593 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2594 opp-peak-kBps = <8368000>; 2595 opp-supported-hw = <0x02>; 2596 }; 2597 2598 opp-700000000 { 2599 opp-hz = /bits/ 64 <700000000>; 2600 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2601 opp-peak-kBps = <8532000>; 2602 opp-supported-hw = <0x02>; 2603 }; 2604 2605 opp-812000000 { 2606 opp-hz = /bits/ 64 <812000000>; 2607 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2608 opp-peak-kBps = <8532000>; 2609 opp-supported-hw = <0x02>; 2610 }; 2611 2612 opp-840000000 { 2613 opp-hz = /bits/ 64 <840000000>; 2614 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2615 opp-peak-kBps = <8532000>; 2616 opp-supported-hw = <0x02>; 2617 }; 2618 2619 opp-900000000 { 2620 opp-hz = /bits/ 64 <900000000>; 2621 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2622 opp-peak-kBps = <8532000>; 2623 opp-supported-hw = <0x02>; 2624 }; 2625 }; 2626 }; 2627 2628 gmu: gmu@3d6a000 { 2629 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2630 reg = <0 0x03d6a000 0 0x34000>, 2631 <0 0x3de0000 0 0x10000>, 2632 <0 0x0b290000 0 0x10000>; 2633 reg-names = "gmu", "rscc", "gmu_pdc"; 2634 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2635 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2636 interrupt-names = "hfi", "gmu"; 2637 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2638 <&gpucc GPU_CC_CXO_CLK>, 2639 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2640 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2641 <&gpucc GPU_CC_AHB_CLK>, 2642 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2643 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2644 clock-names = "gmu", 2645 "cxo", 2646 "axi", 2647 "memnoc", 2648 "ahb", 2649 "hub", 2650 "smmu_vote"; 2651 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2652 <&gpucc GPU_CC_GX_GDSC>; 2653 power-domain-names = "cx", 2654 "gx"; 2655 iommus = <&adreno_smmu 5 0x400>; 2656 operating-points-v2 = <&gmu_opp_table>; 2657 2658 gmu_opp_table: opp-table { 2659 compatible = "operating-points-v2"; 2660 2661 opp-200000000 { 2662 opp-hz = /bits/ 64 <200000000>; 2663 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2664 }; 2665 }; 2666 }; 2667 2668 gpucc: clock-controller@3d90000 { 2669 compatible = "qcom,sc7280-gpucc"; 2670 reg = <0 0x03d90000 0 0x9000>; 2671 clocks = <&rpmhcc RPMH_CXO_CLK>, 2672 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2673 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2674 clock-names = "bi_tcxo", 2675 "gcc_gpu_gpll0_clk_src", 2676 "gcc_gpu_gpll0_div_clk_src"; 2677 #clock-cells = <1>; 2678 #reset-cells = <1>; 2679 #power-domain-cells = <1>; 2680 }; 2681 2682 dma@117f000 { 2683 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2684 reg = <0x0 0x0117f000 0x0 0x1000>, 2685 <0x0 0x01112000 0x0 0x6000>; 2686 }; 2687 2688 adreno_smmu: iommu@3da0000 { 2689 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2690 "qcom,smmu-500", "arm,mmu-500"; 2691 reg = <0 0x03da0000 0 0x20000>; 2692 #iommu-cells = <2>; 2693 #global-interrupts = <2>; 2694 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2706 2707 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2708 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2709 <&gpucc GPU_CC_AHB_CLK>, 2710 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2711 <&gpucc GPU_CC_CX_GMU_CLK>, 2712 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2713 <&gpucc GPU_CC_HUB_AON_CLK>; 2714 clock-names = "gcc_gpu_memnoc_gfx_clk", 2715 "gcc_gpu_snoc_dvm_gfx_clk", 2716 "gpu_cc_ahb_clk", 2717 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2718 "gpu_cc_cx_gmu_clk", 2719 "gpu_cc_hub_cx_int_clk", 2720 "gpu_cc_hub_aon_clk"; 2721 2722 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2723 }; 2724 2725 remoteproc_mpss: remoteproc@4080000 { 2726 compatible = "qcom,sc7280-mpss-pas"; 2727 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2728 reg-names = "qdsp6", "rmb"; 2729 2730 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2731 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2732 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2733 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2734 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2735 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2736 interrupt-names = "wdog", "fatal", "ready", "handover", 2737 "stop-ack", "shutdown-ack"; 2738 2739 clocks = <&rpmhcc RPMH_CXO_CLK>; 2740 clock-names = "xo"; 2741 2742 power-domains = <&rpmhpd SC7280_CX>, 2743 <&rpmhpd SC7280_MSS>; 2744 power-domain-names = "cx", "mss"; 2745 2746 memory-region = <&mpss_mem>; 2747 2748 qcom,qmp = <&aoss_qmp>; 2749 2750 qcom,smem-states = <&modem_smp2p_out 0>; 2751 qcom,smem-state-names = "stop"; 2752 2753 status = "disabled"; 2754 2755 glink-edge { 2756 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2757 IPCC_MPROC_SIGNAL_GLINK_QMP 2758 IRQ_TYPE_EDGE_RISING>; 2759 mboxes = <&ipcc IPCC_CLIENT_MPSS 2760 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2761 label = "modem"; 2762 qcom,remote-pid = <1>; 2763 }; 2764 }; 2765 2766 stm@6002000 { 2767 compatible = "arm,coresight-stm", "arm,primecell"; 2768 reg = <0 0x06002000 0 0x1000>, 2769 <0 0x16280000 0 0x180000>; 2770 reg-names = "stm-base", "stm-stimulus-base"; 2771 2772 clocks = <&aoss_qmp>; 2773 clock-names = "apb_pclk"; 2774 2775 out-ports { 2776 port { 2777 stm_out: endpoint { 2778 remote-endpoint = <&funnel0_in7>; 2779 }; 2780 }; 2781 }; 2782 }; 2783 2784 funnel@6041000 { 2785 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2786 reg = <0 0x06041000 0 0x1000>; 2787 2788 clocks = <&aoss_qmp>; 2789 clock-names = "apb_pclk"; 2790 2791 out-ports { 2792 port { 2793 funnel0_out: endpoint { 2794 remote-endpoint = <&merge_funnel_in0>; 2795 }; 2796 }; 2797 }; 2798 2799 in-ports { 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 2803 port@7 { 2804 reg = <7>; 2805 funnel0_in7: endpoint { 2806 remote-endpoint = <&stm_out>; 2807 }; 2808 }; 2809 }; 2810 }; 2811 2812 funnel@6042000 { 2813 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2814 reg = <0 0x06042000 0 0x1000>; 2815 2816 clocks = <&aoss_qmp>; 2817 clock-names = "apb_pclk"; 2818 2819 out-ports { 2820 port { 2821 funnel1_out: endpoint { 2822 remote-endpoint = <&merge_funnel_in1>; 2823 }; 2824 }; 2825 }; 2826 2827 in-ports { 2828 #address-cells = <1>; 2829 #size-cells = <0>; 2830 2831 port@4 { 2832 reg = <4>; 2833 funnel1_in4: endpoint { 2834 remote-endpoint = <&apss_merge_funnel_out>; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 funnel@6045000 { 2841 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2842 reg = <0 0x06045000 0 0x1000>; 2843 2844 clocks = <&aoss_qmp>; 2845 clock-names = "apb_pclk"; 2846 2847 out-ports { 2848 port { 2849 merge_funnel_out: endpoint { 2850 remote-endpoint = <&swao_funnel_in>; 2851 }; 2852 }; 2853 }; 2854 2855 in-ports { 2856 #address-cells = <1>; 2857 #size-cells = <0>; 2858 2859 port@0 { 2860 reg = <0>; 2861 merge_funnel_in0: endpoint { 2862 remote-endpoint = <&funnel0_out>; 2863 }; 2864 }; 2865 2866 port@1 { 2867 reg = <1>; 2868 merge_funnel_in1: endpoint { 2869 remote-endpoint = <&funnel1_out>; 2870 }; 2871 }; 2872 }; 2873 }; 2874 2875 replicator@6046000 { 2876 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2877 reg = <0 0x06046000 0 0x1000>; 2878 2879 clocks = <&aoss_qmp>; 2880 clock-names = "apb_pclk"; 2881 2882 out-ports { 2883 port { 2884 replicator_out: endpoint { 2885 remote-endpoint = <&etr_in>; 2886 }; 2887 }; 2888 }; 2889 2890 in-ports { 2891 port { 2892 replicator_in: endpoint { 2893 remote-endpoint = <&swao_replicator_out>; 2894 }; 2895 }; 2896 }; 2897 }; 2898 2899 etr@6048000 { 2900 compatible = "arm,coresight-tmc", "arm,primecell"; 2901 reg = <0 0x06048000 0 0x1000>; 2902 iommus = <&apps_smmu 0x04c0 0>; 2903 2904 clocks = <&aoss_qmp>; 2905 clock-names = "apb_pclk"; 2906 arm,scatter-gather; 2907 2908 in-ports { 2909 port { 2910 etr_in: endpoint { 2911 remote-endpoint = <&replicator_out>; 2912 }; 2913 }; 2914 }; 2915 }; 2916 2917 funnel@6b04000 { 2918 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2919 reg = <0 0x06b04000 0 0x1000>; 2920 2921 clocks = <&aoss_qmp>; 2922 clock-names = "apb_pclk"; 2923 2924 out-ports { 2925 port { 2926 swao_funnel_out: endpoint { 2927 remote-endpoint = <&etf_in>; 2928 }; 2929 }; 2930 }; 2931 2932 in-ports { 2933 #address-cells = <1>; 2934 #size-cells = <0>; 2935 2936 port@7 { 2937 reg = <7>; 2938 swao_funnel_in: endpoint { 2939 remote-endpoint = <&merge_funnel_out>; 2940 }; 2941 }; 2942 }; 2943 }; 2944 2945 etf@6b05000 { 2946 compatible = "arm,coresight-tmc", "arm,primecell"; 2947 reg = <0 0x06b05000 0 0x1000>; 2948 2949 clocks = <&aoss_qmp>; 2950 clock-names = "apb_pclk"; 2951 2952 out-ports { 2953 port { 2954 etf_out: endpoint { 2955 remote-endpoint = <&swao_replicator_in>; 2956 }; 2957 }; 2958 }; 2959 2960 in-ports { 2961 port { 2962 etf_in: endpoint { 2963 remote-endpoint = <&swao_funnel_out>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 replicator@6b06000 { 2970 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2971 reg = <0 0x06b06000 0 0x1000>; 2972 2973 clocks = <&aoss_qmp>; 2974 clock-names = "apb_pclk"; 2975 qcom,replicator-loses-context; 2976 2977 out-ports { 2978 port { 2979 swao_replicator_out: endpoint { 2980 remote-endpoint = <&replicator_in>; 2981 }; 2982 }; 2983 }; 2984 2985 in-ports { 2986 port { 2987 swao_replicator_in: endpoint { 2988 remote-endpoint = <&etf_out>; 2989 }; 2990 }; 2991 }; 2992 }; 2993 2994 etm@7040000 { 2995 compatible = "arm,coresight-etm4x", "arm,primecell"; 2996 reg = <0 0x07040000 0 0x1000>; 2997 2998 cpu = <&CPU0>; 2999 3000 clocks = <&aoss_qmp>; 3001 clock-names = "apb_pclk"; 3002 arm,coresight-loses-context-with-cpu; 3003 qcom,skip-power-up; 3004 3005 out-ports { 3006 port { 3007 etm0_out: endpoint { 3008 remote-endpoint = <&apss_funnel_in0>; 3009 }; 3010 }; 3011 }; 3012 }; 3013 3014 etm@7140000 { 3015 compatible = "arm,coresight-etm4x", "arm,primecell"; 3016 reg = <0 0x07140000 0 0x1000>; 3017 3018 cpu = <&CPU1>; 3019 3020 clocks = <&aoss_qmp>; 3021 clock-names = "apb_pclk"; 3022 arm,coresight-loses-context-with-cpu; 3023 qcom,skip-power-up; 3024 3025 out-ports { 3026 port { 3027 etm1_out: endpoint { 3028 remote-endpoint = <&apss_funnel_in1>; 3029 }; 3030 }; 3031 }; 3032 }; 3033 3034 etm@7240000 { 3035 compatible = "arm,coresight-etm4x", "arm,primecell"; 3036 reg = <0 0x07240000 0 0x1000>; 3037 3038 cpu = <&CPU2>; 3039 3040 clocks = <&aoss_qmp>; 3041 clock-names = "apb_pclk"; 3042 arm,coresight-loses-context-with-cpu; 3043 qcom,skip-power-up; 3044 3045 out-ports { 3046 port { 3047 etm2_out: endpoint { 3048 remote-endpoint = <&apss_funnel_in2>; 3049 }; 3050 }; 3051 }; 3052 }; 3053 3054 etm@7340000 { 3055 compatible = "arm,coresight-etm4x", "arm,primecell"; 3056 reg = <0 0x07340000 0 0x1000>; 3057 3058 cpu = <&CPU3>; 3059 3060 clocks = <&aoss_qmp>; 3061 clock-names = "apb_pclk"; 3062 arm,coresight-loses-context-with-cpu; 3063 qcom,skip-power-up; 3064 3065 out-ports { 3066 port { 3067 etm3_out: endpoint { 3068 remote-endpoint = <&apss_funnel_in3>; 3069 }; 3070 }; 3071 }; 3072 }; 3073 3074 etm@7440000 { 3075 compatible = "arm,coresight-etm4x", "arm,primecell"; 3076 reg = <0 0x07440000 0 0x1000>; 3077 3078 cpu = <&CPU4>; 3079 3080 clocks = <&aoss_qmp>; 3081 clock-names = "apb_pclk"; 3082 arm,coresight-loses-context-with-cpu; 3083 qcom,skip-power-up; 3084 3085 out-ports { 3086 port { 3087 etm4_out: endpoint { 3088 remote-endpoint = <&apss_funnel_in4>; 3089 }; 3090 }; 3091 }; 3092 }; 3093 3094 etm@7540000 { 3095 compatible = "arm,coresight-etm4x", "arm,primecell"; 3096 reg = <0 0x07540000 0 0x1000>; 3097 3098 cpu = <&CPU5>; 3099 3100 clocks = <&aoss_qmp>; 3101 clock-names = "apb_pclk"; 3102 arm,coresight-loses-context-with-cpu; 3103 qcom,skip-power-up; 3104 3105 out-ports { 3106 port { 3107 etm5_out: endpoint { 3108 remote-endpoint = <&apss_funnel_in5>; 3109 }; 3110 }; 3111 }; 3112 }; 3113 3114 etm@7640000 { 3115 compatible = "arm,coresight-etm4x", "arm,primecell"; 3116 reg = <0 0x07640000 0 0x1000>; 3117 3118 cpu = <&CPU6>; 3119 3120 clocks = <&aoss_qmp>; 3121 clock-names = "apb_pclk"; 3122 arm,coresight-loses-context-with-cpu; 3123 qcom,skip-power-up; 3124 3125 out-ports { 3126 port { 3127 etm6_out: endpoint { 3128 remote-endpoint = <&apss_funnel_in6>; 3129 }; 3130 }; 3131 }; 3132 }; 3133 3134 etm@7740000 { 3135 compatible = "arm,coresight-etm4x", "arm,primecell"; 3136 reg = <0 0x07740000 0 0x1000>; 3137 3138 cpu = <&CPU7>; 3139 3140 clocks = <&aoss_qmp>; 3141 clock-names = "apb_pclk"; 3142 arm,coresight-loses-context-with-cpu; 3143 qcom,skip-power-up; 3144 3145 out-ports { 3146 port { 3147 etm7_out: endpoint { 3148 remote-endpoint = <&apss_funnel_in7>; 3149 }; 3150 }; 3151 }; 3152 }; 3153 3154 funnel@7800000 { /* APSS Funnel */ 3155 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3156 reg = <0 0x07800000 0 0x1000>; 3157 3158 clocks = <&aoss_qmp>; 3159 clock-names = "apb_pclk"; 3160 3161 out-ports { 3162 port { 3163 apss_funnel_out: endpoint { 3164 remote-endpoint = <&apss_merge_funnel_in>; 3165 }; 3166 }; 3167 }; 3168 3169 in-ports { 3170 #address-cells = <1>; 3171 #size-cells = <0>; 3172 3173 port@0 { 3174 reg = <0>; 3175 apss_funnel_in0: endpoint { 3176 remote-endpoint = <&etm0_out>; 3177 }; 3178 }; 3179 3180 port@1 { 3181 reg = <1>; 3182 apss_funnel_in1: endpoint { 3183 remote-endpoint = <&etm1_out>; 3184 }; 3185 }; 3186 3187 port@2 { 3188 reg = <2>; 3189 apss_funnel_in2: endpoint { 3190 remote-endpoint = <&etm2_out>; 3191 }; 3192 }; 3193 3194 port@3 { 3195 reg = <3>; 3196 apss_funnel_in3: endpoint { 3197 remote-endpoint = <&etm3_out>; 3198 }; 3199 }; 3200 3201 port@4 { 3202 reg = <4>; 3203 apss_funnel_in4: endpoint { 3204 remote-endpoint = <&etm4_out>; 3205 }; 3206 }; 3207 3208 port@5 { 3209 reg = <5>; 3210 apss_funnel_in5: endpoint { 3211 remote-endpoint = <&etm5_out>; 3212 }; 3213 }; 3214 3215 port@6 { 3216 reg = <6>; 3217 apss_funnel_in6: endpoint { 3218 remote-endpoint = <&etm6_out>; 3219 }; 3220 }; 3221 3222 port@7 { 3223 reg = <7>; 3224 apss_funnel_in7: endpoint { 3225 remote-endpoint = <&etm7_out>; 3226 }; 3227 }; 3228 }; 3229 }; 3230 3231 funnel@7810000 { 3232 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3233 reg = <0 0x07810000 0 0x1000>; 3234 3235 clocks = <&aoss_qmp>; 3236 clock-names = "apb_pclk"; 3237 3238 out-ports { 3239 port { 3240 apss_merge_funnel_out: endpoint { 3241 remote-endpoint = <&funnel1_in4>; 3242 }; 3243 }; 3244 }; 3245 3246 in-ports { 3247 port { 3248 apss_merge_funnel_in: endpoint { 3249 remote-endpoint = <&apss_funnel_out>; 3250 }; 3251 }; 3252 }; 3253 }; 3254 3255 sdhc_2: mmc@8804000 { 3256 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3257 pinctrl-names = "default", "sleep"; 3258 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3259 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3260 status = "disabled"; 3261 3262 reg = <0 0x08804000 0 0x1000>; 3263 3264 iommus = <&apps_smmu 0x100 0x0>; 3265 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3267 interrupt-names = "hc_irq", "pwr_irq"; 3268 3269 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3270 <&gcc GCC_SDCC2_APPS_CLK>, 3271 <&rpmhcc RPMH_CXO_CLK>; 3272 clock-names = "iface", "core", "xo"; 3273 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3274 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3275 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3276 power-domains = <&rpmhpd SC7280_CX>; 3277 operating-points-v2 = <&sdhc2_opp_table>; 3278 3279 bus-width = <4>; 3280 3281 qcom,dll-config = <0x0007642c>; 3282 3283 resets = <&gcc GCC_SDCC2_BCR>; 3284 3285 sdhc2_opp_table: opp-table { 3286 compatible = "operating-points-v2"; 3287 3288 opp-100000000 { 3289 opp-hz = /bits/ 64 <100000000>; 3290 required-opps = <&rpmhpd_opp_low_svs>; 3291 opp-peak-kBps = <1800000 400000>; 3292 opp-avg-kBps = <100000 0>; 3293 }; 3294 3295 opp-202000000 { 3296 opp-hz = /bits/ 64 <202000000>; 3297 required-opps = <&rpmhpd_opp_nom>; 3298 opp-peak-kBps = <5400000 1600000>; 3299 opp-avg-kBps = <200000 0>; 3300 }; 3301 }; 3302 }; 3303 3304 usb_1_hsphy: phy@88e3000 { 3305 compatible = "qcom,sc7280-usb-hs-phy", 3306 "qcom,usb-snps-hs-7nm-phy"; 3307 reg = <0 0x088e3000 0 0x400>; 3308 status = "disabled"; 3309 #phy-cells = <0>; 3310 3311 clocks = <&rpmhcc RPMH_CXO_CLK>; 3312 clock-names = "ref"; 3313 3314 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3315 }; 3316 3317 usb_2_hsphy: phy@88e4000 { 3318 compatible = "qcom,sc7280-usb-hs-phy", 3319 "qcom,usb-snps-hs-7nm-phy"; 3320 reg = <0 0x088e4000 0 0x400>; 3321 status = "disabled"; 3322 #phy-cells = <0>; 3323 3324 clocks = <&rpmhcc RPMH_CXO_CLK>; 3325 clock-names = "ref"; 3326 3327 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3328 }; 3329 3330 usb_1_qmpphy: phy-wrapper@88e9000 { 3331 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3332 "qcom,sm8250-qmp-usb3-dp-phy"; 3333 reg = <0 0x088e9000 0 0x200>, 3334 <0 0x088e8000 0 0x40>, 3335 <0 0x088ea000 0 0x200>; 3336 status = "disabled"; 3337 #address-cells = <2>; 3338 #size-cells = <2>; 3339 ranges; 3340 3341 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3342 <&rpmhcc RPMH_CXO_CLK>, 3343 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3344 clock-names = "aux", "ref_clk_src", "com_aux"; 3345 3346 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3347 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3348 reset-names = "phy", "common"; 3349 3350 usb_1_ssphy: usb3-phy@88e9200 { 3351 reg = <0 0x088e9200 0 0x200>, 3352 <0 0x088e9400 0 0x200>, 3353 <0 0x088e9c00 0 0x400>, 3354 <0 0x088e9600 0 0x200>, 3355 <0 0x088e9800 0 0x200>, 3356 <0 0x088e9a00 0 0x100>; 3357 #clock-cells = <0>; 3358 #phy-cells = <0>; 3359 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3360 clock-names = "pipe0"; 3361 clock-output-names = "usb3_phy_pipe_clk_src"; 3362 }; 3363 3364 dp_phy: dp-phy@88ea200 { 3365 reg = <0 0x088ea200 0 0x200>, 3366 <0 0x088ea400 0 0x200>, 3367 <0 0x088eaa00 0 0x200>, 3368 <0 0x088ea600 0 0x200>, 3369 <0 0x088ea800 0 0x200>; 3370 #phy-cells = <0>; 3371 #clock-cells = <1>; 3372 }; 3373 }; 3374 3375 usb_2: usb@8cf8800 { 3376 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3377 reg = <0 0x08cf8800 0 0x400>; 3378 status = "disabled"; 3379 #address-cells = <2>; 3380 #size-cells = <2>; 3381 ranges; 3382 dma-ranges; 3383 3384 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3385 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3386 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3387 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3388 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3389 clock-names = "cfg_noc", 3390 "core", 3391 "iface", 3392 "sleep", 3393 "mock_utmi"; 3394 3395 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3396 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3397 assigned-clock-rates = <19200000>, <200000000>; 3398 3399 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3400 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3401 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3402 interrupt-names = "hs_phy_irq", 3403 "dp_hs_phy_irq", 3404 "dm_hs_phy_irq"; 3405 3406 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3407 required-opps = <&rpmhpd_opp_nom>; 3408 3409 resets = <&gcc GCC_USB30_SEC_BCR>; 3410 3411 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3413 interconnect-names = "usb-ddr", "apps-usb"; 3414 3415 usb_2_dwc3: usb@8c00000 { 3416 compatible = "snps,dwc3"; 3417 reg = <0 0x08c00000 0 0xe000>; 3418 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3419 iommus = <&apps_smmu 0xa0 0x0>; 3420 snps,dis_u2_susphy_quirk; 3421 snps,dis_enblslpm_quirk; 3422 phys = <&usb_2_hsphy>; 3423 phy-names = "usb2-phy"; 3424 maximum-speed = "high-speed"; 3425 usb-role-switch; 3426 port { 3427 usb2_role_switch: endpoint { 3428 remote-endpoint = <&eud_ep>; 3429 }; 3430 }; 3431 }; 3432 }; 3433 3434 qspi: spi@88dc000 { 3435 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3436 reg = <0 0x088dc000 0 0x1000>; 3437 #address-cells = <1>; 3438 #size-cells = <0>; 3439 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3440 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3441 <&gcc GCC_QSPI_CORE_CLK>; 3442 clock-names = "iface", "core"; 3443 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3444 &cnoc2 SLAVE_QSPI_0 0>; 3445 interconnect-names = "qspi-config"; 3446 power-domains = <&rpmhpd SC7280_CX>; 3447 operating-points-v2 = <&qspi_opp_table>; 3448 status = "disabled"; 3449 }; 3450 3451 remoteproc_wpss: remoteproc@8a00000 { 3452 compatible = "qcom,sc7280-wpss-pil"; 3453 reg = <0 0x08a00000 0 0x10000>; 3454 3455 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3456 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3457 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3458 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3459 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3460 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3461 interrupt-names = "wdog", "fatal", "ready", "handover", 3462 "stop-ack", "shutdown-ack"; 3463 3464 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3465 <&gcc GCC_WPSS_AHB_CLK>, 3466 <&gcc GCC_WPSS_RSCP_CLK>, 3467 <&rpmhcc RPMH_CXO_CLK>; 3468 clock-names = "ahb_bdg", "ahb", 3469 "rscp", "xo"; 3470 3471 power-domains = <&rpmhpd SC7280_CX>, 3472 <&rpmhpd SC7280_MX>; 3473 power-domain-names = "cx", "mx"; 3474 3475 memory-region = <&wpss_mem>; 3476 3477 qcom,qmp = <&aoss_qmp>; 3478 3479 qcom,smem-states = <&wpss_smp2p_out 0>; 3480 qcom,smem-state-names = "stop"; 3481 3482 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3483 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3484 reset-names = "restart", "pdc_sync"; 3485 3486 qcom,halt-regs = <&tcsr_1 0x17000>; 3487 3488 status = "disabled"; 3489 3490 glink-edge { 3491 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3492 IPCC_MPROC_SIGNAL_GLINK_QMP 3493 IRQ_TYPE_EDGE_RISING>; 3494 mboxes = <&ipcc IPCC_CLIENT_WPSS 3495 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3496 3497 label = "wpss"; 3498 qcom,remote-pid = <13>; 3499 }; 3500 }; 3501 3502 pmu@9091000 { 3503 compatible = "qcom,sc7280-llcc-bwmon"; 3504 reg = <0 0x09091000 0 0x1000>; 3505 3506 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3507 3508 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3509 3510 operating-points-v2 = <&llcc_bwmon_opp_table>; 3511 3512 llcc_bwmon_opp_table: opp-table { 3513 compatible = "operating-points-v2"; 3514 3515 opp-0 { 3516 opp-peak-kBps = <800000>; 3517 }; 3518 opp-1 { 3519 opp-peak-kBps = <1804000>; 3520 }; 3521 opp-2 { 3522 opp-peak-kBps = <2188000>; 3523 }; 3524 opp-3 { 3525 opp-peak-kBps = <3072000>; 3526 }; 3527 opp-4 { 3528 opp-peak-kBps = <4068000>; 3529 }; 3530 opp-5 { 3531 opp-peak-kBps = <6220000>; 3532 }; 3533 opp-6 { 3534 opp-peak-kBps = <6832000>; 3535 }; 3536 opp-7 { 3537 opp-peak-kBps = <8532000>; 3538 }; 3539 }; 3540 }; 3541 3542 pmu@90b6400 { 3543 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3544 reg = <0 0x090b6400 0 0x600>; 3545 3546 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3547 3548 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3549 operating-points-v2 = <&cpu_bwmon_opp_table>; 3550 3551 cpu_bwmon_opp_table: opp-table { 3552 compatible = "operating-points-v2"; 3553 3554 opp-0 { 3555 opp-peak-kBps = <2400000>; 3556 }; 3557 opp-1 { 3558 opp-peak-kBps = <4800000>; 3559 }; 3560 opp-2 { 3561 opp-peak-kBps = <7456000>; 3562 }; 3563 opp-3 { 3564 opp-peak-kBps = <9600000>; 3565 }; 3566 opp-4 { 3567 opp-peak-kBps = <12896000>; 3568 }; 3569 opp-5 { 3570 opp-peak-kBps = <14928000>; 3571 }; 3572 opp-6 { 3573 opp-peak-kBps = <17056000>; 3574 }; 3575 }; 3576 }; 3577 3578 dc_noc: interconnect@90e0000 { 3579 reg = <0 0x090e0000 0 0x5080>; 3580 compatible = "qcom,sc7280-dc-noc"; 3581 #interconnect-cells = <2>; 3582 qcom,bcm-voters = <&apps_bcm_voter>; 3583 }; 3584 3585 gem_noc: interconnect@9100000 { 3586 reg = <0 0x09100000 0 0xe2200>; 3587 compatible = "qcom,sc7280-gem-noc"; 3588 #interconnect-cells = <2>; 3589 qcom,bcm-voters = <&apps_bcm_voter>; 3590 }; 3591 3592 system-cache-controller@9200000 { 3593 compatible = "qcom,sc7280-llcc"; 3594 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3595 <0 0x09600000 0 0x58000>; 3596 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3597 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3598 }; 3599 3600 eud: eud@88e0000 { 3601 compatible = "qcom,sc7280-eud","qcom,eud"; 3602 reg = <0 0x088e0000 0 0x2000>, 3603 <0 0x088e2000 0 0x1000>; 3604 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3605 ports { 3606 #address-cells = <1>; 3607 #size-cells = <0>; 3608 3609 port@0 { 3610 reg = <0>; 3611 eud_ep: endpoint { 3612 remote-endpoint = <&usb2_role_switch>; 3613 }; 3614 }; 3615 port@1 { 3616 reg = <1>; 3617 eud_con: endpoint { 3618 remote-endpoint = <&con_eud>; 3619 }; 3620 }; 3621 }; 3622 }; 3623 3624 eud_typec: connector { 3625 compatible = "usb-c-connector"; 3626 ports { 3627 #address-cells = <1>; 3628 #size-cells = <0>; 3629 3630 port@0 { 3631 reg = <0>; 3632 con_eud: endpoint { 3633 remote-endpoint = <&eud_con>; 3634 }; 3635 }; 3636 }; 3637 }; 3638 3639 nsp_noc: interconnect@a0c0000 { 3640 reg = <0 0x0a0c0000 0 0x10000>; 3641 compatible = "qcom,sc7280-nsp-noc"; 3642 #interconnect-cells = <2>; 3643 qcom,bcm-voters = <&apps_bcm_voter>; 3644 }; 3645 3646 usb_1: usb@a6f8800 { 3647 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3648 reg = <0 0x0a6f8800 0 0x400>; 3649 status = "disabled"; 3650 #address-cells = <2>; 3651 #size-cells = <2>; 3652 ranges; 3653 dma-ranges; 3654 3655 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3656 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3657 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3658 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3659 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3660 clock-names = "cfg_noc", 3661 "core", 3662 "iface", 3663 "sleep", 3664 "mock_utmi"; 3665 3666 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3667 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3668 assigned-clock-rates = <19200000>, <200000000>; 3669 3670 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3671 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3672 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3673 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3674 interrupt-names = "hs_phy_irq", 3675 "dp_hs_phy_irq", 3676 "dm_hs_phy_irq", 3677 "ss_phy_irq"; 3678 3679 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3680 required-opps = <&rpmhpd_opp_nom>; 3681 3682 resets = <&gcc GCC_USB30_PRIM_BCR>; 3683 3684 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3685 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3686 interconnect-names = "usb-ddr", "apps-usb"; 3687 3688 wakeup-source; 3689 3690 usb_1_dwc3: usb@a600000 { 3691 compatible = "snps,dwc3"; 3692 reg = <0 0x0a600000 0 0xe000>; 3693 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3694 iommus = <&apps_smmu 0xe0 0x0>; 3695 snps,dis_u2_susphy_quirk; 3696 snps,dis_enblslpm_quirk; 3697 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3698 phy-names = "usb2-phy", "usb3-phy"; 3699 maximum-speed = "super-speed"; 3700 }; 3701 }; 3702 3703 venus: video-codec@aa00000 { 3704 compatible = "qcom,sc7280-venus"; 3705 reg = <0 0x0aa00000 0 0xd0600>; 3706 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3707 3708 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3709 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3710 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3711 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3712 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3713 clock-names = "core", "bus", "iface", 3714 "vcodec_core", "vcodec_bus"; 3715 3716 power-domains = <&videocc MVSC_GDSC>, 3717 <&videocc MVS0_GDSC>, 3718 <&rpmhpd SC7280_CX>; 3719 power-domain-names = "venus", "vcodec0", "cx"; 3720 operating-points-v2 = <&venus_opp_table>; 3721 3722 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3723 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3724 interconnect-names = "cpu-cfg", "video-mem"; 3725 3726 iommus = <&apps_smmu 0x2180 0x20>, 3727 <&apps_smmu 0x2184 0x20>; 3728 memory-region = <&video_mem>; 3729 3730 video-decoder { 3731 compatible = "venus-decoder"; 3732 }; 3733 3734 video-encoder { 3735 compatible = "venus-encoder"; 3736 }; 3737 3738 video-firmware { 3739 iommus = <&apps_smmu 0x21a2 0x0>; 3740 }; 3741 3742 venus_opp_table: opp-table { 3743 compatible = "operating-points-v2"; 3744 3745 opp-133330000 { 3746 opp-hz = /bits/ 64 <133330000>; 3747 required-opps = <&rpmhpd_opp_low_svs>; 3748 }; 3749 3750 opp-240000000 { 3751 opp-hz = /bits/ 64 <240000000>; 3752 required-opps = <&rpmhpd_opp_svs>; 3753 }; 3754 3755 opp-335000000 { 3756 opp-hz = /bits/ 64 <335000000>; 3757 required-opps = <&rpmhpd_opp_svs_l1>; 3758 }; 3759 3760 opp-424000000 { 3761 opp-hz = /bits/ 64 <424000000>; 3762 required-opps = <&rpmhpd_opp_nom>; 3763 }; 3764 3765 opp-460000048 { 3766 opp-hz = /bits/ 64 <460000048>; 3767 required-opps = <&rpmhpd_opp_turbo>; 3768 }; 3769 }; 3770 }; 3771 3772 videocc: clock-controller@aaf0000 { 3773 compatible = "qcom,sc7280-videocc"; 3774 reg = <0 0x0aaf0000 0 0x10000>; 3775 clocks = <&rpmhcc RPMH_CXO_CLK>, 3776 <&rpmhcc RPMH_CXO_CLK_A>; 3777 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3778 #clock-cells = <1>; 3779 #reset-cells = <1>; 3780 #power-domain-cells = <1>; 3781 }; 3782 3783 camcc: clock-controller@ad00000 { 3784 compatible = "qcom,sc7280-camcc"; 3785 reg = <0 0x0ad00000 0 0x10000>; 3786 clocks = <&rpmhcc RPMH_CXO_CLK>, 3787 <&rpmhcc RPMH_CXO_CLK_A>, 3788 <&sleep_clk>; 3789 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3790 #clock-cells = <1>; 3791 #reset-cells = <1>; 3792 #power-domain-cells = <1>; 3793 }; 3794 3795 dispcc: clock-controller@af00000 { 3796 compatible = "qcom,sc7280-dispcc"; 3797 reg = <0 0x0af00000 0 0x20000>; 3798 clocks = <&rpmhcc RPMH_CXO_CLK>, 3799 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3800 <&mdss_dsi_phy 0>, 3801 <&mdss_dsi_phy 1>, 3802 <&dp_phy 0>, 3803 <&dp_phy 1>, 3804 <&mdss_edp_phy 0>, 3805 <&mdss_edp_phy 1>; 3806 clock-names = "bi_tcxo", 3807 "gcc_disp_gpll0_clk", 3808 "dsi0_phy_pll_out_byteclk", 3809 "dsi0_phy_pll_out_dsiclk", 3810 "dp_phy_pll_link_clk", 3811 "dp_phy_pll_vco_div_clk", 3812 "edp_phy_pll_link_clk", 3813 "edp_phy_pll_vco_div_clk"; 3814 #clock-cells = <1>; 3815 #reset-cells = <1>; 3816 #power-domain-cells = <1>; 3817 }; 3818 3819 mdss: display-subsystem@ae00000 { 3820 compatible = "qcom,sc7280-mdss"; 3821 reg = <0 0x0ae00000 0 0x1000>; 3822 reg-names = "mdss"; 3823 3824 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3825 3826 clocks = <&gcc GCC_DISP_AHB_CLK>, 3827 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3828 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3829 clock-names = "iface", 3830 "ahb", 3831 "core"; 3832 3833 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3834 interrupt-controller; 3835 #interrupt-cells = <1>; 3836 3837 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3838 interconnect-names = "mdp0-mem"; 3839 3840 iommus = <&apps_smmu 0x900 0x402>; 3841 3842 #address-cells = <2>; 3843 #size-cells = <2>; 3844 ranges; 3845 3846 status = "disabled"; 3847 3848 mdss_mdp: display-controller@ae01000 { 3849 compatible = "qcom,sc7280-dpu"; 3850 reg = <0 0x0ae01000 0 0x8f030>, 3851 <0 0x0aeb0000 0 0x2008>; 3852 reg-names = "mdp", "vbif"; 3853 3854 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3855 <&gcc GCC_DISP_SF_AXI_CLK>, 3856 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3857 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3858 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3859 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3860 clock-names = "bus", 3861 "nrt_bus", 3862 "iface", 3863 "lut", 3864 "core", 3865 "vsync"; 3866 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3867 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3868 assigned-clock-rates = <19200000>, 3869 <19200000>; 3870 operating-points-v2 = <&mdp_opp_table>; 3871 power-domains = <&rpmhpd SC7280_CX>; 3872 3873 interrupt-parent = <&mdss>; 3874 interrupts = <0>; 3875 3876 status = "disabled"; 3877 3878 ports { 3879 #address-cells = <1>; 3880 #size-cells = <0>; 3881 3882 port@0 { 3883 reg = <0>; 3884 dpu_intf1_out: endpoint { 3885 remote-endpoint = <&dsi0_in>; 3886 }; 3887 }; 3888 3889 port@1 { 3890 reg = <1>; 3891 dpu_intf5_out: endpoint { 3892 remote-endpoint = <&edp_in>; 3893 }; 3894 }; 3895 3896 port@2 { 3897 reg = <2>; 3898 dpu_intf0_out: endpoint { 3899 remote-endpoint = <&dp_in>; 3900 }; 3901 }; 3902 }; 3903 3904 mdp_opp_table: opp-table { 3905 compatible = "operating-points-v2"; 3906 3907 opp-200000000 { 3908 opp-hz = /bits/ 64 <200000000>; 3909 required-opps = <&rpmhpd_opp_low_svs>; 3910 }; 3911 3912 opp-300000000 { 3913 opp-hz = /bits/ 64 <300000000>; 3914 required-opps = <&rpmhpd_opp_svs>; 3915 }; 3916 3917 opp-380000000 { 3918 opp-hz = /bits/ 64 <380000000>; 3919 required-opps = <&rpmhpd_opp_svs_l1>; 3920 }; 3921 3922 opp-506666667 { 3923 opp-hz = /bits/ 64 <506666667>; 3924 required-opps = <&rpmhpd_opp_nom>; 3925 }; 3926 }; 3927 }; 3928 3929 mdss_dsi: dsi@ae94000 { 3930 compatible = "qcom,sc7280-dsi-ctrl", 3931 "qcom,mdss-dsi-ctrl"; 3932 reg = <0 0x0ae94000 0 0x400>; 3933 reg-names = "dsi_ctrl"; 3934 3935 interrupt-parent = <&mdss>; 3936 interrupts = <4>; 3937 3938 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3939 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3940 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3941 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3942 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3943 <&gcc GCC_DISP_HF_AXI_CLK>; 3944 clock-names = "byte", 3945 "byte_intf", 3946 "pixel", 3947 "core", 3948 "iface", 3949 "bus"; 3950 3951 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3952 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3953 3954 operating-points-v2 = <&dsi_opp_table>; 3955 power-domains = <&rpmhpd SC7280_CX>; 3956 3957 phys = <&mdss_dsi_phy>; 3958 3959 #address-cells = <1>; 3960 #size-cells = <0>; 3961 3962 status = "disabled"; 3963 3964 ports { 3965 #address-cells = <1>; 3966 #size-cells = <0>; 3967 3968 port@0 { 3969 reg = <0>; 3970 dsi0_in: endpoint { 3971 remote-endpoint = <&dpu_intf1_out>; 3972 }; 3973 }; 3974 3975 port@1 { 3976 reg = <1>; 3977 dsi0_out: endpoint { 3978 }; 3979 }; 3980 }; 3981 3982 dsi_opp_table: opp-table { 3983 compatible = "operating-points-v2"; 3984 3985 opp-187500000 { 3986 opp-hz = /bits/ 64 <187500000>; 3987 required-opps = <&rpmhpd_opp_low_svs>; 3988 }; 3989 3990 opp-300000000 { 3991 opp-hz = /bits/ 64 <300000000>; 3992 required-opps = <&rpmhpd_opp_svs>; 3993 }; 3994 3995 opp-358000000 { 3996 opp-hz = /bits/ 64 <358000000>; 3997 required-opps = <&rpmhpd_opp_svs_l1>; 3998 }; 3999 }; 4000 }; 4001 4002 mdss_dsi_phy: phy@ae94400 { 4003 compatible = "qcom,sc7280-dsi-phy-7nm"; 4004 reg = <0 0x0ae94400 0 0x200>, 4005 <0 0x0ae94600 0 0x280>, 4006 <0 0x0ae94900 0 0x280>; 4007 reg-names = "dsi_phy", 4008 "dsi_phy_lane", 4009 "dsi_pll"; 4010 4011 #clock-cells = <1>; 4012 #phy-cells = <0>; 4013 4014 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4015 <&rpmhcc RPMH_CXO_CLK>; 4016 clock-names = "iface", "ref"; 4017 4018 status = "disabled"; 4019 }; 4020 4021 mdss_edp: edp@aea0000 { 4022 compatible = "qcom,sc7280-edp"; 4023 pinctrl-names = "default"; 4024 pinctrl-0 = <&edp_hot_plug_det>; 4025 4026 reg = <0 0x0aea0000 0 0x200>, 4027 <0 0x0aea0200 0 0x200>, 4028 <0 0x0aea0400 0 0xc00>, 4029 <0 0x0aea1000 0 0x400>; 4030 4031 interrupt-parent = <&mdss>; 4032 interrupts = <14>; 4033 4034 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4035 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4036 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4037 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4038 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4039 clock-names = "core_iface", 4040 "core_aux", 4041 "ctrl_link", 4042 "ctrl_link_iface", 4043 "stream_pixel"; 4044 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4045 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4046 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4047 4048 phys = <&mdss_edp_phy>; 4049 phy-names = "dp"; 4050 4051 operating-points-v2 = <&edp_opp_table>; 4052 power-domains = <&rpmhpd SC7280_CX>; 4053 4054 status = "disabled"; 4055 4056 ports { 4057 #address-cells = <1>; 4058 #size-cells = <0>; 4059 4060 port@0 { 4061 reg = <0>; 4062 edp_in: endpoint { 4063 remote-endpoint = <&dpu_intf5_out>; 4064 }; 4065 }; 4066 4067 port@1 { 4068 reg = <1>; 4069 mdss_edp_out: endpoint { }; 4070 }; 4071 }; 4072 4073 edp_opp_table: opp-table { 4074 compatible = "operating-points-v2"; 4075 4076 opp-160000000 { 4077 opp-hz = /bits/ 64 <160000000>; 4078 required-opps = <&rpmhpd_opp_low_svs>; 4079 }; 4080 4081 opp-270000000 { 4082 opp-hz = /bits/ 64 <270000000>; 4083 required-opps = <&rpmhpd_opp_svs>; 4084 }; 4085 4086 opp-540000000 { 4087 opp-hz = /bits/ 64 <540000000>; 4088 required-opps = <&rpmhpd_opp_nom>; 4089 }; 4090 4091 opp-810000000 { 4092 opp-hz = /bits/ 64 <810000000>; 4093 required-opps = <&rpmhpd_opp_nom>; 4094 }; 4095 }; 4096 }; 4097 4098 mdss_edp_phy: phy@aec2a00 { 4099 compatible = "qcom,sc7280-edp-phy"; 4100 4101 reg = <0 0x0aec2a00 0 0x19c>, 4102 <0 0x0aec2200 0 0xa0>, 4103 <0 0x0aec2600 0 0xa0>, 4104 <0 0x0aec2000 0 0x1c0>; 4105 4106 clocks = <&rpmhcc RPMH_CXO_CLK>, 4107 <&gcc GCC_EDP_CLKREF_EN>; 4108 clock-names = "aux", 4109 "cfg_ahb"; 4110 4111 #clock-cells = <1>; 4112 #phy-cells = <0>; 4113 4114 status = "disabled"; 4115 }; 4116 4117 mdss_dp: displayport-controller@ae90000 { 4118 compatible = "qcom,sc7280-dp"; 4119 4120 reg = <0 0x0ae90000 0 0x200>, 4121 <0 0x0ae90200 0 0x200>, 4122 <0 0x0ae90400 0 0xc00>, 4123 <0 0x0ae91000 0 0x400>, 4124 <0 0x0ae91400 0 0x400>; 4125 4126 interrupt-parent = <&mdss>; 4127 interrupts = <12>; 4128 4129 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4130 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4131 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4132 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4133 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4134 clock-names = "core_iface", 4135 "core_aux", 4136 "ctrl_link", 4137 "ctrl_link_iface", 4138 "stream_pixel"; 4139 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4140 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4141 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4142 phys = <&dp_phy>; 4143 phy-names = "dp"; 4144 4145 operating-points-v2 = <&dp_opp_table>; 4146 power-domains = <&rpmhpd SC7280_CX>; 4147 4148 #sound-dai-cells = <0>; 4149 4150 status = "disabled"; 4151 4152 ports { 4153 #address-cells = <1>; 4154 #size-cells = <0>; 4155 4156 port@0 { 4157 reg = <0>; 4158 dp_in: endpoint { 4159 remote-endpoint = <&dpu_intf0_out>; 4160 }; 4161 }; 4162 4163 port@1 { 4164 reg = <1>; 4165 mdss_dp_out: endpoint { }; 4166 }; 4167 }; 4168 4169 dp_opp_table: opp-table { 4170 compatible = "operating-points-v2"; 4171 4172 opp-160000000 { 4173 opp-hz = /bits/ 64 <160000000>; 4174 required-opps = <&rpmhpd_opp_low_svs>; 4175 }; 4176 4177 opp-270000000 { 4178 opp-hz = /bits/ 64 <270000000>; 4179 required-opps = <&rpmhpd_opp_svs>; 4180 }; 4181 4182 opp-540000000 { 4183 opp-hz = /bits/ 64 <540000000>; 4184 required-opps = <&rpmhpd_opp_svs_l1>; 4185 }; 4186 4187 opp-810000000 { 4188 opp-hz = /bits/ 64 <810000000>; 4189 required-opps = <&rpmhpd_opp_nom>; 4190 }; 4191 }; 4192 }; 4193 }; 4194 4195 pdc: interrupt-controller@b220000 { 4196 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4197 reg = <0 0x0b220000 0 0x30000>; 4198 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4199 <55 306 4>, <59 312 3>, <62 374 2>, 4200 <64 434 2>, <66 438 3>, <69 86 1>, 4201 <70 520 54>, <124 609 31>, <155 63 1>, 4202 <156 716 12>; 4203 #interrupt-cells = <2>; 4204 interrupt-parent = <&intc>; 4205 interrupt-controller; 4206 }; 4207 4208 pdc_reset: reset-controller@b5e0000 { 4209 compatible = "qcom,sc7280-pdc-global"; 4210 reg = <0 0x0b5e0000 0 0x20000>; 4211 #reset-cells = <1>; 4212 }; 4213 4214 tsens0: thermal-sensor@c263000 { 4215 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4216 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4217 <0 0x0c222000 0 0x1ff>; /* SROT */ 4218 #qcom,sensors = <15>; 4219 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4221 interrupt-names = "uplow","critical"; 4222 #thermal-sensor-cells = <1>; 4223 }; 4224 4225 tsens1: thermal-sensor@c265000 { 4226 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4227 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4228 <0 0x0c223000 0 0x1ff>; /* SROT */ 4229 #qcom,sensors = <12>; 4230 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4232 interrupt-names = "uplow","critical"; 4233 #thermal-sensor-cells = <1>; 4234 }; 4235 4236 aoss_reset: reset-controller@c2a0000 { 4237 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4238 reg = <0 0x0c2a0000 0 0x31000>; 4239 #reset-cells = <1>; 4240 }; 4241 4242 aoss_qmp: power-management@c300000 { 4243 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4244 reg = <0 0x0c300000 0 0x400>; 4245 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4246 IPCC_MPROC_SIGNAL_GLINK_QMP 4247 IRQ_TYPE_EDGE_RISING>; 4248 mboxes = <&ipcc IPCC_CLIENT_AOP 4249 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4250 4251 #clock-cells = <0>; 4252 }; 4253 4254 sram@c3f0000 { 4255 compatible = "qcom,rpmh-stats"; 4256 reg = <0 0x0c3f0000 0 0x400>; 4257 }; 4258 4259 spmi_bus: spmi@c440000 { 4260 compatible = "qcom,spmi-pmic-arb"; 4261 reg = <0 0x0c440000 0 0x1100>, 4262 <0 0x0c600000 0 0x2000000>, 4263 <0 0x0e600000 0 0x100000>, 4264 <0 0x0e700000 0 0xa0000>, 4265 <0 0x0c40a000 0 0x26000>; 4266 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4267 interrupt-names = "periph_irq"; 4268 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4269 qcom,ee = <0>; 4270 qcom,channel = <0>; 4271 #address-cells = <2>; 4272 #size-cells = <0>; 4273 interrupt-controller; 4274 #interrupt-cells = <4>; 4275 }; 4276 4277 tlmm: pinctrl@f100000 { 4278 compatible = "qcom,sc7280-pinctrl"; 4279 reg = <0 0x0f100000 0 0x300000>; 4280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4281 gpio-controller; 4282 #gpio-cells = <2>; 4283 interrupt-controller; 4284 #interrupt-cells = <2>; 4285 gpio-ranges = <&tlmm 0 0 175>; 4286 wakeup-parent = <&pdc>; 4287 4288 dp_hot_plug_det: dp-hot-plug-det-state { 4289 pins = "gpio47"; 4290 function = "dp_hot"; 4291 }; 4292 4293 edp_hot_plug_det: edp-hot-plug-det-state { 4294 pins = "gpio60"; 4295 function = "edp_hot"; 4296 }; 4297 4298 mi2s0_data0: mi2s0-data0-state { 4299 pins = "gpio98"; 4300 function = "mi2s0_data0"; 4301 }; 4302 4303 mi2s0_data1: mi2s0-data1-state { 4304 pins = "gpio99"; 4305 function = "mi2s0_data1"; 4306 }; 4307 4308 mi2s0_mclk: mi2s0-mclk-state { 4309 pins = "gpio96"; 4310 function = "pri_mi2s"; 4311 }; 4312 4313 mi2s0_sclk: mi2s0-sclk-state { 4314 pins = "gpio97"; 4315 function = "mi2s0_sck"; 4316 }; 4317 4318 mi2s0_ws: mi2s0-ws-state { 4319 pins = "gpio100"; 4320 function = "mi2s0_ws"; 4321 }; 4322 4323 mi2s1_data0: mi2s1-data0-state { 4324 pins = "gpio107"; 4325 function = "mi2s1_data0"; 4326 }; 4327 4328 mi2s1_sclk: mi2s1-sclk-state { 4329 pins = "gpio106"; 4330 function = "mi2s1_sck"; 4331 }; 4332 4333 mi2s1_ws: mi2s1-ws-state { 4334 pins = "gpio108"; 4335 function = "mi2s1_ws"; 4336 }; 4337 4338 pcie1_clkreq_n: pcie1-clkreq-n-state { 4339 pins = "gpio79"; 4340 function = "pcie1_clkreqn"; 4341 }; 4342 4343 qspi_clk: qspi-clk-state { 4344 pins = "gpio14"; 4345 function = "qspi_clk"; 4346 }; 4347 4348 qspi_cs0: qspi-cs0-state { 4349 pins = "gpio15"; 4350 function = "qspi_cs"; 4351 }; 4352 4353 qspi_cs1: qspi-cs1-state { 4354 pins = "gpio19"; 4355 function = "qspi_cs"; 4356 }; 4357 4358 qspi_data01: qspi-data01-state { 4359 pins = "gpio12", "gpio13"; 4360 function = "qspi_data"; 4361 }; 4362 4363 qspi_data12: qspi-data12-state { 4364 pins = "gpio16", "gpio17"; 4365 function = "qspi_data"; 4366 }; 4367 4368 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4369 pins = "gpio0", "gpio1"; 4370 function = "qup00"; 4371 }; 4372 4373 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4374 pins = "gpio4", "gpio5"; 4375 function = "qup01"; 4376 }; 4377 4378 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4379 pins = "gpio8", "gpio9"; 4380 function = "qup02"; 4381 }; 4382 4383 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4384 pins = "gpio12", "gpio13"; 4385 function = "qup03"; 4386 }; 4387 4388 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4389 pins = "gpio16", "gpio17"; 4390 function = "qup04"; 4391 }; 4392 4393 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4394 pins = "gpio20", "gpio21"; 4395 function = "qup05"; 4396 }; 4397 4398 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4399 pins = "gpio24", "gpio25"; 4400 function = "qup06"; 4401 }; 4402 4403 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4404 pins = "gpio28", "gpio29"; 4405 function = "qup07"; 4406 }; 4407 4408 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4409 pins = "gpio32", "gpio33"; 4410 function = "qup10"; 4411 }; 4412 4413 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4414 pins = "gpio36", "gpio37"; 4415 function = "qup11"; 4416 }; 4417 4418 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4419 pins = "gpio40", "gpio41"; 4420 function = "qup12"; 4421 }; 4422 4423 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4424 pins = "gpio44", "gpio45"; 4425 function = "qup13"; 4426 }; 4427 4428 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4429 pins = "gpio48", "gpio49"; 4430 function = "qup14"; 4431 }; 4432 4433 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4434 pins = "gpio52", "gpio53"; 4435 function = "qup15"; 4436 }; 4437 4438 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4439 pins = "gpio56", "gpio57"; 4440 function = "qup16"; 4441 }; 4442 4443 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4444 pins = "gpio60", "gpio61"; 4445 function = "qup17"; 4446 }; 4447 4448 qup_spi0_data_clk: qup-spi0-data-clk-state { 4449 pins = "gpio0", "gpio1", "gpio2"; 4450 function = "qup00"; 4451 }; 4452 4453 qup_spi0_cs: qup-spi0-cs-state { 4454 pins = "gpio3"; 4455 function = "qup00"; 4456 }; 4457 4458 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4459 pins = "gpio3"; 4460 function = "gpio"; 4461 }; 4462 4463 qup_spi1_data_clk: qup-spi1-data-clk-state { 4464 pins = "gpio4", "gpio5", "gpio6"; 4465 function = "qup01"; 4466 }; 4467 4468 qup_spi1_cs: qup-spi1-cs-state { 4469 pins = "gpio7"; 4470 function = "qup01"; 4471 }; 4472 4473 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4474 pins = "gpio7"; 4475 function = "gpio"; 4476 }; 4477 4478 qup_spi2_data_clk: qup-spi2-data-clk-state { 4479 pins = "gpio8", "gpio9", "gpio10"; 4480 function = "qup02"; 4481 }; 4482 4483 qup_spi2_cs: qup-spi2-cs-state { 4484 pins = "gpio11"; 4485 function = "qup02"; 4486 }; 4487 4488 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4489 pins = "gpio11"; 4490 function = "gpio"; 4491 }; 4492 4493 qup_spi3_data_clk: qup-spi3-data-clk-state { 4494 pins = "gpio12", "gpio13", "gpio14"; 4495 function = "qup03"; 4496 }; 4497 4498 qup_spi3_cs: qup-spi3-cs-state { 4499 pins = "gpio15"; 4500 function = "qup03"; 4501 }; 4502 4503 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4504 pins = "gpio15"; 4505 function = "gpio"; 4506 }; 4507 4508 qup_spi4_data_clk: qup-spi4-data-clk-state { 4509 pins = "gpio16", "gpio17", "gpio18"; 4510 function = "qup04"; 4511 }; 4512 4513 qup_spi4_cs: qup-spi4-cs-state { 4514 pins = "gpio19"; 4515 function = "qup04"; 4516 }; 4517 4518 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4519 pins = "gpio19"; 4520 function = "gpio"; 4521 }; 4522 4523 qup_spi5_data_clk: qup-spi5-data-clk-state { 4524 pins = "gpio20", "gpio21", "gpio22"; 4525 function = "qup05"; 4526 }; 4527 4528 qup_spi5_cs: qup-spi5-cs-state { 4529 pins = "gpio23"; 4530 function = "qup05"; 4531 }; 4532 4533 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4534 pins = "gpio23"; 4535 function = "gpio"; 4536 }; 4537 4538 qup_spi6_data_clk: qup-spi6-data-clk-state { 4539 pins = "gpio24", "gpio25", "gpio26"; 4540 function = "qup06"; 4541 }; 4542 4543 qup_spi6_cs: qup-spi6-cs-state { 4544 pins = "gpio27"; 4545 function = "qup06"; 4546 }; 4547 4548 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4549 pins = "gpio27"; 4550 function = "gpio"; 4551 }; 4552 4553 qup_spi7_data_clk: qup-spi7-data-clk-state { 4554 pins = "gpio28", "gpio29", "gpio30"; 4555 function = "qup07"; 4556 }; 4557 4558 qup_spi7_cs: qup-spi7-cs-state { 4559 pins = "gpio31"; 4560 function = "qup07"; 4561 }; 4562 4563 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4564 pins = "gpio31"; 4565 function = "gpio"; 4566 }; 4567 4568 qup_spi8_data_clk: qup-spi8-data-clk-state { 4569 pins = "gpio32", "gpio33", "gpio34"; 4570 function = "qup10"; 4571 }; 4572 4573 qup_spi8_cs: qup-spi8-cs-state { 4574 pins = "gpio35"; 4575 function = "qup10"; 4576 }; 4577 4578 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4579 pins = "gpio35"; 4580 function = "gpio"; 4581 }; 4582 4583 qup_spi9_data_clk: qup-spi9-data-clk-state { 4584 pins = "gpio36", "gpio37", "gpio38"; 4585 function = "qup11"; 4586 }; 4587 4588 qup_spi9_cs: qup-spi9-cs-state { 4589 pins = "gpio39"; 4590 function = "qup11"; 4591 }; 4592 4593 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4594 pins = "gpio39"; 4595 function = "gpio"; 4596 }; 4597 4598 qup_spi10_data_clk: qup-spi10-data-clk-state { 4599 pins = "gpio40", "gpio41", "gpio42"; 4600 function = "qup12"; 4601 }; 4602 4603 qup_spi10_cs: qup-spi10-cs-state { 4604 pins = "gpio43"; 4605 function = "qup12"; 4606 }; 4607 4608 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4609 pins = "gpio43"; 4610 function = "gpio"; 4611 }; 4612 4613 qup_spi11_data_clk: qup-spi11-data-clk-state { 4614 pins = "gpio44", "gpio45", "gpio46"; 4615 function = "qup13"; 4616 }; 4617 4618 qup_spi11_cs: qup-spi11-cs-state { 4619 pins = "gpio47"; 4620 function = "qup13"; 4621 }; 4622 4623 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4624 pins = "gpio47"; 4625 function = "gpio"; 4626 }; 4627 4628 qup_spi12_data_clk: qup-spi12-data-clk-state { 4629 pins = "gpio48", "gpio49", "gpio50"; 4630 function = "qup14"; 4631 }; 4632 4633 qup_spi12_cs: qup-spi12-cs-state { 4634 pins = "gpio51"; 4635 function = "qup14"; 4636 }; 4637 4638 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4639 pins = "gpio51"; 4640 function = "gpio"; 4641 }; 4642 4643 qup_spi13_data_clk: qup-spi13-data-clk-state { 4644 pins = "gpio52", "gpio53", "gpio54"; 4645 function = "qup15"; 4646 }; 4647 4648 qup_spi13_cs: qup-spi13-cs-state { 4649 pins = "gpio55"; 4650 function = "qup15"; 4651 }; 4652 4653 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4654 pins = "gpio55"; 4655 function = "gpio"; 4656 }; 4657 4658 qup_spi14_data_clk: qup-spi14-data-clk-state { 4659 pins = "gpio56", "gpio57", "gpio58"; 4660 function = "qup16"; 4661 }; 4662 4663 qup_spi14_cs: qup-spi14-cs-state { 4664 pins = "gpio59"; 4665 function = "qup16"; 4666 }; 4667 4668 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4669 pins = "gpio59"; 4670 function = "gpio"; 4671 }; 4672 4673 qup_spi15_data_clk: qup-spi15-data-clk-state { 4674 pins = "gpio60", "gpio61", "gpio62"; 4675 function = "qup17"; 4676 }; 4677 4678 qup_spi15_cs: qup-spi15-cs-state { 4679 pins = "gpio63"; 4680 function = "qup17"; 4681 }; 4682 4683 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4684 pins = "gpio63"; 4685 function = "gpio"; 4686 }; 4687 4688 qup_uart0_cts: qup-uart0-cts-state { 4689 pins = "gpio0"; 4690 function = "qup00"; 4691 }; 4692 4693 qup_uart0_rts: qup-uart0-rts-state { 4694 pins = "gpio1"; 4695 function = "qup00"; 4696 }; 4697 4698 qup_uart0_tx: qup-uart0-tx-state { 4699 pins = "gpio2"; 4700 function = "qup00"; 4701 }; 4702 4703 qup_uart0_rx: qup-uart0-rx-state { 4704 pins = "gpio3"; 4705 function = "qup00"; 4706 }; 4707 4708 qup_uart1_cts: qup-uart1-cts-state { 4709 pins = "gpio4"; 4710 function = "qup01"; 4711 }; 4712 4713 qup_uart1_rts: qup-uart1-rts-state { 4714 pins = "gpio5"; 4715 function = "qup01"; 4716 }; 4717 4718 qup_uart1_tx: qup-uart1-tx-state { 4719 pins = "gpio6"; 4720 function = "qup01"; 4721 }; 4722 4723 qup_uart1_rx: qup-uart1-rx-state { 4724 pins = "gpio7"; 4725 function = "qup01"; 4726 }; 4727 4728 qup_uart2_cts: qup-uart2-cts-state { 4729 pins = "gpio8"; 4730 function = "qup02"; 4731 }; 4732 4733 qup_uart2_rts: qup-uart2-rts-state { 4734 pins = "gpio9"; 4735 function = "qup02"; 4736 }; 4737 4738 qup_uart2_tx: qup-uart2-tx-state { 4739 pins = "gpio10"; 4740 function = "qup02"; 4741 }; 4742 4743 qup_uart2_rx: qup-uart2-rx-state { 4744 pins = "gpio11"; 4745 function = "qup02"; 4746 }; 4747 4748 qup_uart3_cts: qup-uart3-cts-state { 4749 pins = "gpio12"; 4750 function = "qup03"; 4751 }; 4752 4753 qup_uart3_rts: qup-uart3-rts-state { 4754 pins = "gpio13"; 4755 function = "qup03"; 4756 }; 4757 4758 qup_uart3_tx: qup-uart3-tx-state { 4759 pins = "gpio14"; 4760 function = "qup03"; 4761 }; 4762 4763 qup_uart3_rx: qup-uart3-rx-state { 4764 pins = "gpio15"; 4765 function = "qup03"; 4766 }; 4767 4768 qup_uart4_cts: qup-uart4-cts-state { 4769 pins = "gpio16"; 4770 function = "qup04"; 4771 }; 4772 4773 qup_uart4_rts: qup-uart4-rts-state { 4774 pins = "gpio17"; 4775 function = "qup04"; 4776 }; 4777 4778 qup_uart4_tx: qup-uart4-tx-state { 4779 pins = "gpio18"; 4780 function = "qup04"; 4781 }; 4782 4783 qup_uart4_rx: qup-uart4-rx-state { 4784 pins = "gpio19"; 4785 function = "qup04"; 4786 }; 4787 4788 qup_uart5_cts: qup-uart5-cts-state { 4789 pins = "gpio20"; 4790 function = "qup05"; 4791 }; 4792 4793 qup_uart5_rts: qup-uart5-rts-state { 4794 pins = "gpio21"; 4795 function = "qup05"; 4796 }; 4797 4798 qup_uart5_tx: qup-uart5-tx-state { 4799 pins = "gpio22"; 4800 function = "qup05"; 4801 }; 4802 4803 qup_uart5_rx: qup-uart5-rx-state { 4804 pins = "gpio23"; 4805 function = "qup05"; 4806 }; 4807 4808 qup_uart6_cts: qup-uart6-cts-state { 4809 pins = "gpio24"; 4810 function = "qup06"; 4811 }; 4812 4813 qup_uart6_rts: qup-uart6-rts-state { 4814 pins = "gpio25"; 4815 function = "qup06"; 4816 }; 4817 4818 qup_uart6_tx: qup-uart6-tx-state { 4819 pins = "gpio26"; 4820 function = "qup06"; 4821 }; 4822 4823 qup_uart6_rx: qup-uart6-rx-state { 4824 pins = "gpio27"; 4825 function = "qup06"; 4826 }; 4827 4828 qup_uart7_cts: qup-uart7-cts-state { 4829 pins = "gpio28"; 4830 function = "qup07"; 4831 }; 4832 4833 qup_uart7_rts: qup-uart7-rts-state { 4834 pins = "gpio29"; 4835 function = "qup07"; 4836 }; 4837 4838 qup_uart7_tx: qup-uart7-tx-state { 4839 pins = "gpio30"; 4840 function = "qup07"; 4841 }; 4842 4843 qup_uart7_rx: qup-uart7-rx-state { 4844 pins = "gpio31"; 4845 function = "qup07"; 4846 }; 4847 4848 qup_uart8_cts: qup-uart8-cts-state { 4849 pins = "gpio32"; 4850 function = "qup10"; 4851 }; 4852 4853 qup_uart8_rts: qup-uart8-rts-state { 4854 pins = "gpio33"; 4855 function = "qup10"; 4856 }; 4857 4858 qup_uart8_tx: qup-uart8-tx-state { 4859 pins = "gpio34"; 4860 function = "qup10"; 4861 }; 4862 4863 qup_uart8_rx: qup-uart8-rx-state { 4864 pins = "gpio35"; 4865 function = "qup10"; 4866 }; 4867 4868 qup_uart9_cts: qup-uart9-cts-state { 4869 pins = "gpio36"; 4870 function = "qup11"; 4871 }; 4872 4873 qup_uart9_rts: qup-uart9-rts-state { 4874 pins = "gpio37"; 4875 function = "qup11"; 4876 }; 4877 4878 qup_uart9_tx: qup-uart9-tx-state { 4879 pins = "gpio38"; 4880 function = "qup11"; 4881 }; 4882 4883 qup_uart9_rx: qup-uart9-rx-state { 4884 pins = "gpio39"; 4885 function = "qup11"; 4886 }; 4887 4888 qup_uart10_cts: qup-uart10-cts-state { 4889 pins = "gpio40"; 4890 function = "qup12"; 4891 }; 4892 4893 qup_uart10_rts: qup-uart10-rts-state { 4894 pins = "gpio41"; 4895 function = "qup12"; 4896 }; 4897 4898 qup_uart10_tx: qup-uart10-tx-state { 4899 pins = "gpio42"; 4900 function = "qup12"; 4901 }; 4902 4903 qup_uart10_rx: qup-uart10-rx-state { 4904 pins = "gpio43"; 4905 function = "qup12"; 4906 }; 4907 4908 qup_uart11_cts: qup-uart11-cts-state { 4909 pins = "gpio44"; 4910 function = "qup13"; 4911 }; 4912 4913 qup_uart11_rts: qup-uart11-rts-state { 4914 pins = "gpio45"; 4915 function = "qup13"; 4916 }; 4917 4918 qup_uart11_tx: qup-uart11-tx-state { 4919 pins = "gpio46"; 4920 function = "qup13"; 4921 }; 4922 4923 qup_uart11_rx: qup-uart11-rx-state { 4924 pins = "gpio47"; 4925 function = "qup13"; 4926 }; 4927 4928 qup_uart12_cts: qup-uart12-cts-state { 4929 pins = "gpio48"; 4930 function = "qup14"; 4931 }; 4932 4933 qup_uart12_rts: qup-uart12-rts-state { 4934 pins = "gpio49"; 4935 function = "qup14"; 4936 }; 4937 4938 qup_uart12_tx: qup-uart12-tx-state { 4939 pins = "gpio50"; 4940 function = "qup14"; 4941 }; 4942 4943 qup_uart12_rx: qup-uart12-rx-state { 4944 pins = "gpio51"; 4945 function = "qup14"; 4946 }; 4947 4948 qup_uart13_cts: qup-uart13-cts-state { 4949 pins = "gpio52"; 4950 function = "qup15"; 4951 }; 4952 4953 qup_uart13_rts: qup-uart13-rts-state { 4954 pins = "gpio53"; 4955 function = "qup15"; 4956 }; 4957 4958 qup_uart13_tx: qup-uart13-tx-state { 4959 pins = "gpio54"; 4960 function = "qup15"; 4961 }; 4962 4963 qup_uart13_rx: qup-uart13-rx-state { 4964 pins = "gpio55"; 4965 function = "qup15"; 4966 }; 4967 4968 qup_uart14_cts: qup-uart14-cts-state { 4969 pins = "gpio56"; 4970 function = "qup16"; 4971 }; 4972 4973 qup_uart14_rts: qup-uart14-rts-state { 4974 pins = "gpio57"; 4975 function = "qup16"; 4976 }; 4977 4978 qup_uart14_tx: qup-uart14-tx-state { 4979 pins = "gpio58"; 4980 function = "qup16"; 4981 }; 4982 4983 qup_uart14_rx: qup-uart14-rx-state { 4984 pins = "gpio59"; 4985 function = "qup16"; 4986 }; 4987 4988 qup_uart15_cts: qup-uart15-cts-state { 4989 pins = "gpio60"; 4990 function = "qup17"; 4991 }; 4992 4993 qup_uart15_rts: qup-uart15-rts-state { 4994 pins = "gpio61"; 4995 function = "qup17"; 4996 }; 4997 4998 qup_uart15_tx: qup-uart15-tx-state { 4999 pins = "gpio62"; 5000 function = "qup17"; 5001 }; 5002 5003 qup_uart15_rx: qup-uart15-rx-state { 5004 pins = "gpio63"; 5005 function = "qup17"; 5006 }; 5007 5008 sdc1_clk: sdc1-clk-state { 5009 pins = "sdc1_clk"; 5010 }; 5011 5012 sdc1_cmd: sdc1-cmd-state { 5013 pins = "sdc1_cmd"; 5014 }; 5015 5016 sdc1_data: sdc1-data-state { 5017 pins = "sdc1_data"; 5018 }; 5019 5020 sdc1_rclk: sdc1-rclk-state { 5021 pins = "sdc1_rclk"; 5022 }; 5023 5024 sdc1_clk_sleep: sdc1-clk-sleep-state { 5025 pins = "sdc1_clk"; 5026 drive-strength = <2>; 5027 bias-bus-hold; 5028 }; 5029 5030 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5031 pins = "sdc1_cmd"; 5032 drive-strength = <2>; 5033 bias-bus-hold; 5034 }; 5035 5036 sdc1_data_sleep: sdc1-data-sleep-state { 5037 pins = "sdc1_data"; 5038 drive-strength = <2>; 5039 bias-bus-hold; 5040 }; 5041 5042 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5043 pins = "sdc1_rclk"; 5044 drive-strength = <2>; 5045 bias-bus-hold; 5046 }; 5047 5048 sdc2_clk: sdc2-clk-state { 5049 pins = "sdc2_clk"; 5050 }; 5051 5052 sdc2_cmd: sdc2-cmd-state { 5053 pins = "sdc2_cmd"; 5054 }; 5055 5056 sdc2_data: sdc2-data-state { 5057 pins = "sdc2_data"; 5058 }; 5059 5060 sdc2_clk_sleep: sdc2-clk-sleep-state { 5061 pins = "sdc2_clk"; 5062 drive-strength = <2>; 5063 bias-bus-hold; 5064 }; 5065 5066 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5067 pins = "sdc2_cmd"; 5068 drive-strength = <2>; 5069 bias-bus-hold; 5070 }; 5071 5072 sdc2_data_sleep: sdc2-data-sleep-state { 5073 pins = "sdc2_data"; 5074 drive-strength = <2>; 5075 bias-bus-hold; 5076 }; 5077 }; 5078 5079 sram@146a5000 { 5080 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5081 reg = <0 0x146a5000 0 0x6000>; 5082 5083 #address-cells = <1>; 5084 #size-cells = <1>; 5085 5086 ranges = <0 0 0x146a5000 0x6000>; 5087 5088 pil-reloc@594c { 5089 compatible = "qcom,pil-reloc-info"; 5090 reg = <0x594c 0xc8>; 5091 }; 5092 }; 5093 5094 apps_smmu: iommu@15000000 { 5095 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5096 reg = <0 0x15000000 0 0x100000>; 5097 #iommu-cells = <2>; 5098 #global-interrupts = <1>; 5099 dma-coherent; 5100 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5181 }; 5182 5183 intc: interrupt-controller@17a00000 { 5184 compatible = "arm,gic-v3"; 5185 #address-cells = <2>; 5186 #size-cells = <2>; 5187 ranges; 5188 #interrupt-cells = <3>; 5189 interrupt-controller; 5190 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5191 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5192 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5193 5194 gic-its@17a40000 { 5195 compatible = "arm,gic-v3-its"; 5196 msi-controller; 5197 #msi-cells = <1>; 5198 reg = <0 0x17a40000 0 0x20000>; 5199 status = "disabled"; 5200 }; 5201 }; 5202 5203 watchdog@17c10000 { 5204 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5205 reg = <0 0x17c10000 0 0x1000>; 5206 clocks = <&sleep_clk>; 5207 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5208 }; 5209 5210 timer@17c20000 { 5211 #address-cells = <1>; 5212 #size-cells = <1>; 5213 ranges = <0 0 0 0x20000000>; 5214 compatible = "arm,armv7-timer-mem"; 5215 reg = <0 0x17c20000 0 0x1000>; 5216 5217 frame@17c21000 { 5218 frame-number = <0>; 5219 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5220 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5221 reg = <0x17c21000 0x1000>, 5222 <0x17c22000 0x1000>; 5223 }; 5224 5225 frame@17c23000 { 5226 frame-number = <1>; 5227 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5228 reg = <0x17c23000 0x1000>; 5229 status = "disabled"; 5230 }; 5231 5232 frame@17c25000 { 5233 frame-number = <2>; 5234 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5235 reg = <0x17c25000 0x1000>; 5236 status = "disabled"; 5237 }; 5238 5239 frame@17c27000 { 5240 frame-number = <3>; 5241 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5242 reg = <0x17c27000 0x1000>; 5243 status = "disabled"; 5244 }; 5245 5246 frame@17c29000 { 5247 frame-number = <4>; 5248 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5249 reg = <0x17c29000 0x1000>; 5250 status = "disabled"; 5251 }; 5252 5253 frame@17c2b000 { 5254 frame-number = <5>; 5255 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5256 reg = <0x17c2b000 0x1000>; 5257 status = "disabled"; 5258 }; 5259 5260 frame@17c2d000 { 5261 frame-number = <6>; 5262 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5263 reg = <0x17c2d000 0x1000>; 5264 status = "disabled"; 5265 }; 5266 }; 5267 5268 apps_rsc: rsc@18200000 { 5269 compatible = "qcom,rpmh-rsc"; 5270 reg = <0 0x18200000 0 0x10000>, 5271 <0 0x18210000 0 0x10000>, 5272 <0 0x18220000 0 0x10000>; 5273 reg-names = "drv-0", "drv-1", "drv-2"; 5274 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5275 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5276 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5277 qcom,tcs-offset = <0xd00>; 5278 qcom,drv-id = <2>; 5279 qcom,tcs-config = <ACTIVE_TCS 2>, 5280 <SLEEP_TCS 3>, 5281 <WAKE_TCS 3>, 5282 <CONTROL_TCS 1>; 5283 5284 apps_bcm_voter: bcm-voter { 5285 compatible = "qcom,bcm-voter"; 5286 }; 5287 5288 rpmhpd: power-controller { 5289 compatible = "qcom,sc7280-rpmhpd"; 5290 #power-domain-cells = <1>; 5291 operating-points-v2 = <&rpmhpd_opp_table>; 5292 5293 rpmhpd_opp_table: opp-table { 5294 compatible = "operating-points-v2"; 5295 5296 rpmhpd_opp_ret: opp1 { 5297 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5298 }; 5299 5300 rpmhpd_opp_low_svs: opp2 { 5301 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5302 }; 5303 5304 rpmhpd_opp_svs: opp3 { 5305 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5306 }; 5307 5308 rpmhpd_opp_svs_l1: opp4 { 5309 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5310 }; 5311 5312 rpmhpd_opp_svs_l2: opp5 { 5313 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5314 }; 5315 5316 rpmhpd_opp_nom: opp6 { 5317 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5318 }; 5319 5320 rpmhpd_opp_nom_l1: opp7 { 5321 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5322 }; 5323 5324 rpmhpd_opp_turbo: opp8 { 5325 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5326 }; 5327 5328 rpmhpd_opp_turbo_l1: opp9 { 5329 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5330 }; 5331 }; 5332 }; 5333 5334 rpmhcc: clock-controller { 5335 compatible = "qcom,sc7280-rpmh-clk"; 5336 clocks = <&xo_board>; 5337 clock-names = "xo"; 5338 #clock-cells = <1>; 5339 }; 5340 }; 5341 5342 epss_l3: interconnect@18590000 { 5343 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5344 reg = <0 0x18590000 0 0x1000>; 5345 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5346 clock-names = "xo", "alternate"; 5347 #interconnect-cells = <1>; 5348 }; 5349 5350 cpufreq_hw: cpufreq@18591000 { 5351 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5352 reg = <0 0x18591000 0 0x1000>, 5353 <0 0x18592000 0 0x1000>, 5354 <0 0x18593000 0 0x1000>; 5355 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5356 clock-names = "xo", "alternate"; 5357 #freq-domain-cells = <1>; 5358 #clock-cells = <1>; 5359 }; 5360 }; 5361 5362 thermal_zones: thermal-zones { 5363 cpu0-thermal { 5364 polling-delay-passive = <250>; 5365 polling-delay = <0>; 5366 5367 thermal-sensors = <&tsens0 1>; 5368 5369 trips { 5370 cpu0_alert0: trip-point0 { 5371 temperature = <90000>; 5372 hysteresis = <2000>; 5373 type = "passive"; 5374 }; 5375 5376 cpu0_alert1: trip-point1 { 5377 temperature = <95000>; 5378 hysteresis = <2000>; 5379 type = "passive"; 5380 }; 5381 5382 cpu0_crit: cpu-crit { 5383 temperature = <110000>; 5384 hysteresis = <0>; 5385 type = "critical"; 5386 }; 5387 }; 5388 5389 cooling-maps { 5390 map0 { 5391 trip = <&cpu0_alert0>; 5392 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5393 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5394 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5395 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5396 }; 5397 map1 { 5398 trip = <&cpu0_alert1>; 5399 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5400 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5401 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5402 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5403 }; 5404 }; 5405 }; 5406 5407 cpu1-thermal { 5408 polling-delay-passive = <250>; 5409 polling-delay = <0>; 5410 5411 thermal-sensors = <&tsens0 2>; 5412 5413 trips { 5414 cpu1_alert0: trip-point0 { 5415 temperature = <90000>; 5416 hysteresis = <2000>; 5417 type = "passive"; 5418 }; 5419 5420 cpu1_alert1: trip-point1 { 5421 temperature = <95000>; 5422 hysteresis = <2000>; 5423 type = "passive"; 5424 }; 5425 5426 cpu1_crit: cpu-crit { 5427 temperature = <110000>; 5428 hysteresis = <0>; 5429 type = "critical"; 5430 }; 5431 }; 5432 5433 cooling-maps { 5434 map0 { 5435 trip = <&cpu1_alert0>; 5436 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5437 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5438 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5439 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5440 }; 5441 map1 { 5442 trip = <&cpu1_alert1>; 5443 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5444 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5445 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5446 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5447 }; 5448 }; 5449 }; 5450 5451 cpu2-thermal { 5452 polling-delay-passive = <250>; 5453 polling-delay = <0>; 5454 5455 thermal-sensors = <&tsens0 3>; 5456 5457 trips { 5458 cpu2_alert0: trip-point0 { 5459 temperature = <90000>; 5460 hysteresis = <2000>; 5461 type = "passive"; 5462 }; 5463 5464 cpu2_alert1: trip-point1 { 5465 temperature = <95000>; 5466 hysteresis = <2000>; 5467 type = "passive"; 5468 }; 5469 5470 cpu2_crit: cpu-crit { 5471 temperature = <110000>; 5472 hysteresis = <0>; 5473 type = "critical"; 5474 }; 5475 }; 5476 5477 cooling-maps { 5478 map0 { 5479 trip = <&cpu2_alert0>; 5480 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5481 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5482 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5483 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5484 }; 5485 map1 { 5486 trip = <&cpu2_alert1>; 5487 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5488 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5489 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5490 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5491 }; 5492 }; 5493 }; 5494 5495 cpu3-thermal { 5496 polling-delay-passive = <250>; 5497 polling-delay = <0>; 5498 5499 thermal-sensors = <&tsens0 4>; 5500 5501 trips { 5502 cpu3_alert0: trip-point0 { 5503 temperature = <90000>; 5504 hysteresis = <2000>; 5505 type = "passive"; 5506 }; 5507 5508 cpu3_alert1: trip-point1 { 5509 temperature = <95000>; 5510 hysteresis = <2000>; 5511 type = "passive"; 5512 }; 5513 5514 cpu3_crit: cpu-crit { 5515 temperature = <110000>; 5516 hysteresis = <0>; 5517 type = "critical"; 5518 }; 5519 }; 5520 5521 cooling-maps { 5522 map0 { 5523 trip = <&cpu3_alert0>; 5524 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5525 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5526 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5527 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5528 }; 5529 map1 { 5530 trip = <&cpu3_alert1>; 5531 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5532 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5533 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5534 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5535 }; 5536 }; 5537 }; 5538 5539 cpu4-thermal { 5540 polling-delay-passive = <250>; 5541 polling-delay = <0>; 5542 5543 thermal-sensors = <&tsens0 7>; 5544 5545 trips { 5546 cpu4_alert0: trip-point0 { 5547 temperature = <90000>; 5548 hysteresis = <2000>; 5549 type = "passive"; 5550 }; 5551 5552 cpu4_alert1: trip-point1 { 5553 temperature = <95000>; 5554 hysteresis = <2000>; 5555 type = "passive"; 5556 }; 5557 5558 cpu4_crit: cpu-crit { 5559 temperature = <110000>; 5560 hysteresis = <0>; 5561 type = "critical"; 5562 }; 5563 }; 5564 5565 cooling-maps { 5566 map0 { 5567 trip = <&cpu4_alert0>; 5568 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5569 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5570 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5571 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5572 }; 5573 map1 { 5574 trip = <&cpu4_alert1>; 5575 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5576 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5577 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5578 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5579 }; 5580 }; 5581 }; 5582 5583 cpu5-thermal { 5584 polling-delay-passive = <250>; 5585 polling-delay = <0>; 5586 5587 thermal-sensors = <&tsens0 8>; 5588 5589 trips { 5590 cpu5_alert0: trip-point0 { 5591 temperature = <90000>; 5592 hysteresis = <2000>; 5593 type = "passive"; 5594 }; 5595 5596 cpu5_alert1: trip-point1 { 5597 temperature = <95000>; 5598 hysteresis = <2000>; 5599 type = "passive"; 5600 }; 5601 5602 cpu5_crit: cpu-crit { 5603 temperature = <110000>; 5604 hysteresis = <0>; 5605 type = "critical"; 5606 }; 5607 }; 5608 5609 cooling-maps { 5610 map0 { 5611 trip = <&cpu5_alert0>; 5612 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5613 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5614 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5615 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5616 }; 5617 map1 { 5618 trip = <&cpu5_alert1>; 5619 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5620 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5621 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5622 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5623 }; 5624 }; 5625 }; 5626 5627 cpu6-thermal { 5628 polling-delay-passive = <250>; 5629 polling-delay = <0>; 5630 5631 thermal-sensors = <&tsens0 9>; 5632 5633 trips { 5634 cpu6_alert0: trip-point0 { 5635 temperature = <90000>; 5636 hysteresis = <2000>; 5637 type = "passive"; 5638 }; 5639 5640 cpu6_alert1: trip-point1 { 5641 temperature = <95000>; 5642 hysteresis = <2000>; 5643 type = "passive"; 5644 }; 5645 5646 cpu6_crit: cpu-crit { 5647 temperature = <110000>; 5648 hysteresis = <0>; 5649 type = "critical"; 5650 }; 5651 }; 5652 5653 cooling-maps { 5654 map0 { 5655 trip = <&cpu6_alert0>; 5656 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5657 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5658 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5659 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5660 }; 5661 map1 { 5662 trip = <&cpu6_alert1>; 5663 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5664 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5665 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5666 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5667 }; 5668 }; 5669 }; 5670 5671 cpu7-thermal { 5672 polling-delay-passive = <250>; 5673 polling-delay = <0>; 5674 5675 thermal-sensors = <&tsens0 10>; 5676 5677 trips { 5678 cpu7_alert0: trip-point0 { 5679 temperature = <90000>; 5680 hysteresis = <2000>; 5681 type = "passive"; 5682 }; 5683 5684 cpu7_alert1: trip-point1 { 5685 temperature = <95000>; 5686 hysteresis = <2000>; 5687 type = "passive"; 5688 }; 5689 5690 cpu7_crit: cpu-crit { 5691 temperature = <110000>; 5692 hysteresis = <0>; 5693 type = "critical"; 5694 }; 5695 }; 5696 5697 cooling-maps { 5698 map0 { 5699 trip = <&cpu7_alert0>; 5700 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5701 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5702 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5703 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5704 }; 5705 map1 { 5706 trip = <&cpu7_alert1>; 5707 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5708 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5709 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5710 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5711 }; 5712 }; 5713 }; 5714 5715 cpu8-thermal { 5716 polling-delay-passive = <250>; 5717 polling-delay = <0>; 5718 5719 thermal-sensors = <&tsens0 11>; 5720 5721 trips { 5722 cpu8_alert0: trip-point0 { 5723 temperature = <90000>; 5724 hysteresis = <2000>; 5725 type = "passive"; 5726 }; 5727 5728 cpu8_alert1: trip-point1 { 5729 temperature = <95000>; 5730 hysteresis = <2000>; 5731 type = "passive"; 5732 }; 5733 5734 cpu8_crit: cpu-crit { 5735 temperature = <110000>; 5736 hysteresis = <0>; 5737 type = "critical"; 5738 }; 5739 }; 5740 5741 cooling-maps { 5742 map0 { 5743 trip = <&cpu8_alert0>; 5744 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5745 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5746 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5747 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5748 }; 5749 map1 { 5750 trip = <&cpu8_alert1>; 5751 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5752 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5753 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5754 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5755 }; 5756 }; 5757 }; 5758 5759 cpu9-thermal { 5760 polling-delay-passive = <250>; 5761 polling-delay = <0>; 5762 5763 thermal-sensors = <&tsens0 12>; 5764 5765 trips { 5766 cpu9_alert0: trip-point0 { 5767 temperature = <90000>; 5768 hysteresis = <2000>; 5769 type = "passive"; 5770 }; 5771 5772 cpu9_alert1: trip-point1 { 5773 temperature = <95000>; 5774 hysteresis = <2000>; 5775 type = "passive"; 5776 }; 5777 5778 cpu9_crit: cpu-crit { 5779 temperature = <110000>; 5780 hysteresis = <0>; 5781 type = "critical"; 5782 }; 5783 }; 5784 5785 cooling-maps { 5786 map0 { 5787 trip = <&cpu9_alert0>; 5788 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5789 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5790 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5791 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5792 }; 5793 map1 { 5794 trip = <&cpu9_alert1>; 5795 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5796 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5797 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5798 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5799 }; 5800 }; 5801 }; 5802 5803 cpu10-thermal { 5804 polling-delay-passive = <250>; 5805 polling-delay = <0>; 5806 5807 thermal-sensors = <&tsens0 13>; 5808 5809 trips { 5810 cpu10_alert0: trip-point0 { 5811 temperature = <90000>; 5812 hysteresis = <2000>; 5813 type = "passive"; 5814 }; 5815 5816 cpu10_alert1: trip-point1 { 5817 temperature = <95000>; 5818 hysteresis = <2000>; 5819 type = "passive"; 5820 }; 5821 5822 cpu10_crit: cpu-crit { 5823 temperature = <110000>; 5824 hysteresis = <0>; 5825 type = "critical"; 5826 }; 5827 }; 5828 5829 cooling-maps { 5830 map0 { 5831 trip = <&cpu10_alert0>; 5832 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5833 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5834 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5835 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5836 }; 5837 map1 { 5838 trip = <&cpu10_alert1>; 5839 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5840 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5841 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5842 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5843 }; 5844 }; 5845 }; 5846 5847 cpu11-thermal { 5848 polling-delay-passive = <250>; 5849 polling-delay = <0>; 5850 5851 thermal-sensors = <&tsens0 14>; 5852 5853 trips { 5854 cpu11_alert0: trip-point0 { 5855 temperature = <90000>; 5856 hysteresis = <2000>; 5857 type = "passive"; 5858 }; 5859 5860 cpu11_alert1: trip-point1 { 5861 temperature = <95000>; 5862 hysteresis = <2000>; 5863 type = "passive"; 5864 }; 5865 5866 cpu11_crit: cpu-crit { 5867 temperature = <110000>; 5868 hysteresis = <0>; 5869 type = "critical"; 5870 }; 5871 }; 5872 5873 cooling-maps { 5874 map0 { 5875 trip = <&cpu11_alert0>; 5876 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5877 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5878 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5879 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5880 }; 5881 map1 { 5882 trip = <&cpu11_alert1>; 5883 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5884 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5885 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5886 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5887 }; 5888 }; 5889 }; 5890 5891 aoss0-thermal { 5892 polling-delay-passive = <0>; 5893 polling-delay = <0>; 5894 5895 thermal-sensors = <&tsens0 0>; 5896 5897 trips { 5898 aoss0_alert0: trip-point0 { 5899 temperature = <90000>; 5900 hysteresis = <2000>; 5901 type = "hot"; 5902 }; 5903 5904 aoss0_crit: aoss0-crit { 5905 temperature = <110000>; 5906 hysteresis = <0>; 5907 type = "critical"; 5908 }; 5909 }; 5910 }; 5911 5912 aoss1-thermal { 5913 polling-delay-passive = <0>; 5914 polling-delay = <0>; 5915 5916 thermal-sensors = <&tsens1 0>; 5917 5918 trips { 5919 aoss1_alert0: trip-point0 { 5920 temperature = <90000>; 5921 hysteresis = <2000>; 5922 type = "hot"; 5923 }; 5924 5925 aoss1_crit: aoss1-crit { 5926 temperature = <110000>; 5927 hysteresis = <0>; 5928 type = "critical"; 5929 }; 5930 }; 5931 }; 5932 5933 cpuss0-thermal { 5934 polling-delay-passive = <0>; 5935 polling-delay = <0>; 5936 5937 thermal-sensors = <&tsens0 5>; 5938 5939 trips { 5940 cpuss0_alert0: trip-point0 { 5941 temperature = <90000>; 5942 hysteresis = <2000>; 5943 type = "hot"; 5944 }; 5945 cpuss0_crit: cluster0-crit { 5946 temperature = <110000>; 5947 hysteresis = <0>; 5948 type = "critical"; 5949 }; 5950 }; 5951 }; 5952 5953 cpuss1-thermal { 5954 polling-delay-passive = <0>; 5955 polling-delay = <0>; 5956 5957 thermal-sensors = <&tsens0 6>; 5958 5959 trips { 5960 cpuss1_alert0: trip-point0 { 5961 temperature = <90000>; 5962 hysteresis = <2000>; 5963 type = "hot"; 5964 }; 5965 cpuss1_crit: cluster0-crit { 5966 temperature = <110000>; 5967 hysteresis = <0>; 5968 type = "critical"; 5969 }; 5970 }; 5971 }; 5972 5973 gpuss0-thermal { 5974 polling-delay-passive = <100>; 5975 polling-delay = <0>; 5976 5977 thermal-sensors = <&tsens1 1>; 5978 5979 trips { 5980 gpuss0_alert0: trip-point0 { 5981 temperature = <95000>; 5982 hysteresis = <2000>; 5983 type = "passive"; 5984 }; 5985 5986 gpuss0_crit: gpuss0-crit { 5987 temperature = <110000>; 5988 hysteresis = <0>; 5989 type = "critical"; 5990 }; 5991 }; 5992 5993 cooling-maps { 5994 map0 { 5995 trip = <&gpuss0_alert0>; 5996 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5997 }; 5998 }; 5999 }; 6000 6001 gpuss1-thermal { 6002 polling-delay-passive = <100>; 6003 polling-delay = <0>; 6004 6005 thermal-sensors = <&tsens1 2>; 6006 6007 trips { 6008 gpuss1_alert0: trip-point0 { 6009 temperature = <95000>; 6010 hysteresis = <2000>; 6011 type = "passive"; 6012 }; 6013 6014 gpuss1_crit: gpuss1-crit { 6015 temperature = <110000>; 6016 hysteresis = <0>; 6017 type = "critical"; 6018 }; 6019 }; 6020 6021 cooling-maps { 6022 map0 { 6023 trip = <&gpuss1_alert0>; 6024 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6025 }; 6026 }; 6027 }; 6028 6029 nspss0-thermal { 6030 polling-delay-passive = <0>; 6031 polling-delay = <0>; 6032 6033 thermal-sensors = <&tsens1 3>; 6034 6035 trips { 6036 nspss0_alert0: trip-point0 { 6037 temperature = <90000>; 6038 hysteresis = <2000>; 6039 type = "hot"; 6040 }; 6041 6042 nspss0_crit: nspss0-crit { 6043 temperature = <110000>; 6044 hysteresis = <0>; 6045 type = "critical"; 6046 }; 6047 }; 6048 }; 6049 6050 nspss1-thermal { 6051 polling-delay-passive = <0>; 6052 polling-delay = <0>; 6053 6054 thermal-sensors = <&tsens1 4>; 6055 6056 trips { 6057 nspss1_alert0: trip-point0 { 6058 temperature = <90000>; 6059 hysteresis = <2000>; 6060 type = "hot"; 6061 }; 6062 6063 nspss1_crit: nspss1-crit { 6064 temperature = <110000>; 6065 hysteresis = <0>; 6066 type = "critical"; 6067 }; 6068 }; 6069 }; 6070 6071 video-thermal { 6072 polling-delay-passive = <0>; 6073 polling-delay = <0>; 6074 6075 thermal-sensors = <&tsens1 5>; 6076 6077 trips { 6078 video_alert0: trip-point0 { 6079 temperature = <90000>; 6080 hysteresis = <2000>; 6081 type = "hot"; 6082 }; 6083 6084 video_crit: video-crit { 6085 temperature = <110000>; 6086 hysteresis = <0>; 6087 type = "critical"; 6088 }; 6089 }; 6090 }; 6091 6092 ddr-thermal { 6093 polling-delay-passive = <0>; 6094 polling-delay = <0>; 6095 6096 thermal-sensors = <&tsens1 6>; 6097 6098 trips { 6099 ddr_alert0: trip-point0 { 6100 temperature = <90000>; 6101 hysteresis = <2000>; 6102 type = "hot"; 6103 }; 6104 6105 ddr_crit: ddr-crit { 6106 temperature = <110000>; 6107 hysteresis = <0>; 6108 type = "critical"; 6109 }; 6110 }; 6111 }; 6112 6113 mdmss0-thermal { 6114 polling-delay-passive = <0>; 6115 polling-delay = <0>; 6116 6117 thermal-sensors = <&tsens1 7>; 6118 6119 trips { 6120 mdmss0_alert0: trip-point0 { 6121 temperature = <90000>; 6122 hysteresis = <2000>; 6123 type = "hot"; 6124 }; 6125 6126 mdmss0_crit: mdmss0-crit { 6127 temperature = <110000>; 6128 hysteresis = <0>; 6129 type = "critical"; 6130 }; 6131 }; 6132 }; 6133 6134 mdmss1-thermal { 6135 polling-delay-passive = <0>; 6136 polling-delay = <0>; 6137 6138 thermal-sensors = <&tsens1 8>; 6139 6140 trips { 6141 mdmss1_alert0: trip-point0 { 6142 temperature = <90000>; 6143 hysteresis = <2000>; 6144 type = "hot"; 6145 }; 6146 6147 mdmss1_crit: mdmss1-crit { 6148 temperature = <110000>; 6149 hysteresis = <0>; 6150 type = "critical"; 6151 }; 6152 }; 6153 }; 6154 6155 mdmss2-thermal { 6156 polling-delay-passive = <0>; 6157 polling-delay = <0>; 6158 6159 thermal-sensors = <&tsens1 9>; 6160 6161 trips { 6162 mdmss2_alert0: trip-point0 { 6163 temperature = <90000>; 6164 hysteresis = <2000>; 6165 type = "hot"; 6166 }; 6167 6168 mdmss2_crit: mdmss2-crit { 6169 temperature = <110000>; 6170 hysteresis = <0>; 6171 type = "critical"; 6172 }; 6173 }; 6174 }; 6175 6176 mdmss3-thermal { 6177 polling-delay-passive = <0>; 6178 polling-delay = <0>; 6179 6180 thermal-sensors = <&tsens1 10>; 6181 6182 trips { 6183 mdmss3_alert0: trip-point0 { 6184 temperature = <90000>; 6185 hysteresis = <2000>; 6186 type = "hot"; 6187 }; 6188 6189 mdmss3_crit: mdmss3-crit { 6190 temperature = <110000>; 6191 hysteresis = <0>; 6192 type = "critical"; 6193 }; 6194 }; 6195 }; 6196 6197 camera0-thermal { 6198 polling-delay-passive = <0>; 6199 polling-delay = <0>; 6200 6201 thermal-sensors = <&tsens1 11>; 6202 6203 trips { 6204 camera0_alert0: trip-point0 { 6205 temperature = <90000>; 6206 hysteresis = <2000>; 6207 type = "hot"; 6208 }; 6209 6210 camera0_crit: camera0-crit { 6211 temperature = <110000>; 6212 hysteresis = <0>; 6213 type = "critical"; 6214 }; 6215 }; 6216 }; 6217 }; 6218 6219 timer { 6220 compatible = "arm,armv8-timer"; 6221 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6222 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6223 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6224 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6225 }; 6226}; 6227