1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 aop_mem: memory@80800000 { 56 reg = <0x0 0x80800000 0x0 0x60000>; 57 no-map; 58 }; 59 60 aop_cmd_db_mem: memory@80860000 { 61 reg = <0x0 0x80860000 0x0 0x20000>; 62 compatible = "qcom,cmd-db"; 63 no-map; 64 }; 65 66 smem_mem: memory@80900000 { 67 reg = <0x0 0x80900000 0x0 0x200000>; 68 no-map; 69 }; 70 71 cpucp_mem: memory@80b00000 { 72 no-map; 73 reg = <0x0 0x80b00000 0x0 0x100000>; 74 }; 75 76 ipa_fw_mem: memory@8b700000 { 77 reg = <0 0x8b700000 0 0x10000>; 78 no-map; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <2>; 84 #size-cells = <0>; 85 86 CPU0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,kryo"; 89 reg = <0x0 0x0>; 90 enable-method = "psci"; 91 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 92 &LITTLE_CPU_SLEEP_1 93 &CLUSTER_SLEEP_0>; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_0: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 L3_0: l3-cache { 101 compatible = "cache"; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,kryo"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_100>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "arm,kryo"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_200>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_200: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x300>; 144 enable-method = "psci"; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 146 &LITTLE_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_300>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x400>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "arm,kryo"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 cpu-idle-states = <&BIG_CPU_SLEEP_0 180 &BIG_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,kryo"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 197 &BIG_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 cpu-idle-states = <&BIG_CPU_SLEEP_0 214 &BIG_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-power-down"; 267 arm,psci-suspend-param = <0x40000003>; 268 entry-latency-us = <549>; 269 exit-latency-us = <901>; 270 min-residency-us = <1774>; 271 local-timer-stop; 272 }; 273 274 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-down"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <702>; 279 exit-latency-us = <915>; 280 min-residency-us = <4001>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-power-down"; 287 arm,psci-suspend-param = <0x40000003>; 288 entry-latency-us = <523>; 289 exit-latency-us = <1244>; 290 min-residency-us = <2207>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "big-rail-power-down"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <526>; 299 exit-latency-us = <1854>; 300 min-residency-us = <5555>; 301 local-timer-stop; 302 }; 303 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "cluster-power-down"; 307 arm,psci-suspend-param = <0x40003444>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9926>; 311 local-timer-stop; 312 }; 313 }; 314 }; 315 316 memory@80000000 { 317 device_type = "memory"; 318 /* We expect the bootloader to fill in the size */ 319 reg = <0 0x80000000 0 0>; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-sc7280", "qcom,scm"; 325 }; 326 }; 327 328 clk_virt: interconnect { 329 compatible = "qcom,sc7280-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 smem { 335 compatible = "qcom,smem"; 336 memory-region = <&smem_mem>; 337 hwlocks = <&tcsr_mutex 3>; 338 }; 339 340 smp2p-adsp { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <443>, <429>; 343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P 345 IRQ_TYPE_EDGE_RISING>; 346 mboxes = <&ipcc IPCC_CLIENT_LPASS 347 IPCC_MPROC_SIGNAL_SMP2P>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <2>; 351 352 adsp_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 adsp_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 }; 363 364 smp2p-cdsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <94>, <432>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_CDSP 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <5>; 375 376 cdsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 cdsp_smp2p_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-mpss { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <435>, <428>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_MPSS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <1>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 ipa_smp2p_out: ipa-ap-to-modem { 412 qcom,entry-name = "ipa"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 ipa_smp2p_in: ipa-modem-to-ap { 417 qcom,entry-name = "ipa"; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smp2p-wpss { 424 compatible = "qcom,smp2p"; 425 qcom,smem = <617>, <616>; 426 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P 428 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&ipcc IPCC_CLIENT_WPSS 430 IPCC_MPROC_SIGNAL_SMP2P>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <13>; 434 435 wpss_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 wpss_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 }; 446 447 pmu { 448 compatible = "arm,armv8-pmuv3"; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 450 }; 451 452 psci { 453 compatible = "arm,psci-1.0"; 454 method = "smc"; 455 }; 456 457 soc: soc@0 { 458 #address-cells = <2>; 459 #size-cells = <2>; 460 ranges = <0 0 0 0 0x10 0>; 461 dma-ranges = <0 0 0 0 0x10 0>; 462 compatible = "simple-bus"; 463 464 gcc: clock-controller@100000 { 465 compatible = "qcom,gcc-sc7280"; 466 reg = <0 0x00100000 0 0x1f0000>; 467 clocks = <&rpmhcc RPMH_CXO_CLK>, 468 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 469 <0>, <0>, <0>, <0>, <0>, <0>; 470 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 471 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 472 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 473 "ufs_phy_tx_symbol_0_clk", 474 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 475 #clock-cells = <1>; 476 #reset-cells = <1>; 477 #power-domain-cells = <1>; 478 }; 479 480 ipcc: mailbox@408000 { 481 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 482 reg = <0 0x00408000 0 0x1000>; 483 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-controller; 485 #interrupt-cells = <3>; 486 #mbox-cells = <2>; 487 }; 488 489 qfprom: efuse@784000 { 490 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 491 reg = <0 0x00784000 0 0xa20>, 492 <0 0x00780000 0 0xa20>, 493 <0 0x00782000 0 0x120>, 494 <0 0x00786000 0 0x1fff>; 495 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 496 clock-names = "core"; 497 power-domains = <&rpmhpd SC7280_MX>; 498 #address-cells = <1>; 499 #size-cells = <1>; 500 }; 501 502 sdhc_1: sdhci@7c4000 { 503 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 504 status = "disabled"; 505 506 reg = <0 0x007c4000 0 0x1000>, 507 <0 0x007c5000 0 0x1000>; 508 reg-names = "hc", "cqhci"; 509 510 iommus = <&apps_smmu 0xc0 0x0>; 511 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "hc_irq", "pwr_irq"; 514 515 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 516 <&gcc GCC_SDCC1_AHB_CLK>, 517 <&rpmhcc RPMH_CXO_CLK>; 518 clock-names = "core", "iface", "xo"; 519 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 521 interconnect-names = "sdhc-ddr","cpu-sdhc"; 522 power-domains = <&rpmhpd SC7280_CX>; 523 operating-points-v2 = <&sdhc1_opp_table>; 524 525 bus-width = <8>; 526 supports-cqe; 527 528 qcom,dll-config = <0x0007642c>; 529 qcom,ddr-config = <0x80040868>; 530 531 mmc-ddr-1_8v; 532 mmc-hs200-1_8v; 533 mmc-hs400-1_8v; 534 mmc-hs400-enhanced-strobe; 535 536 sdhc1_opp_table: opp-table { 537 compatible = "operating-points-v2"; 538 539 opp-100000000 { 540 opp-hz = /bits/ 64 <100000000>; 541 required-opps = <&rpmhpd_opp_low_svs>; 542 opp-peak-kBps = <1800000 400000>; 543 opp-avg-kBps = <100000 0>; 544 }; 545 546 opp-384000000 { 547 opp-hz = /bits/ 64 <384000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 opp-peak-kBps = <5400000 1600000>; 550 opp-avg-kBps = <390000 0>; 551 }; 552 }; 553 554 }; 555 556 qupv3_id_0: geniqup@9c0000 { 557 compatible = "qcom,geni-se-qup"; 558 reg = <0 0x009c0000 0 0x2000>; 559 clock-names = "m-ahb", "s-ahb"; 560 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 561 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 562 #address-cells = <2>; 563 #size-cells = <2>; 564 ranges; 565 status = "disabled"; 566 567 uart5: serial@994000 { 568 compatible = "qcom,geni-debug-uart"; 569 reg = <0 0x00994000 0 0x4000>; 570 clock-names = "se"; 571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&qup_uart5_default>; 574 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 575 status = "disabled"; 576 }; 577 }; 578 579 cnoc2: interconnect@1500000 { 580 reg = <0 0x01500000 0 0x1000>; 581 compatible = "qcom,sc7280-cnoc2"; 582 #interconnect-cells = <2>; 583 qcom,bcm-voters = <&apps_bcm_voter>; 584 }; 585 586 cnoc3: interconnect@1502000 { 587 reg = <0 0x01502000 0 0x1000>; 588 compatible = "qcom,sc7280-cnoc3"; 589 #interconnect-cells = <2>; 590 qcom,bcm-voters = <&apps_bcm_voter>; 591 }; 592 593 mc_virt: interconnect@1580000 { 594 reg = <0 0x01580000 0 0x4>; 595 compatible = "qcom,sc7280-mc-virt"; 596 #interconnect-cells = <2>; 597 qcom,bcm-voters = <&apps_bcm_voter>; 598 }; 599 600 system_noc: interconnect@1680000 { 601 reg = <0 0x01680000 0 0x15480>; 602 compatible = "qcom,sc7280-system-noc"; 603 #interconnect-cells = <2>; 604 qcom,bcm-voters = <&apps_bcm_voter>; 605 }; 606 607 aggre1_noc: interconnect@16e0000 { 608 compatible = "qcom,sc7280-aggre1-noc"; 609 reg = <0 0x016e0000 0 0x1c080>; 610 #interconnect-cells = <2>; 611 qcom,bcm-voters = <&apps_bcm_voter>; 612 }; 613 614 aggre2_noc: interconnect@1700000 { 615 reg = <0 0x01700000 0 0x2b080>; 616 compatible = "qcom,sc7280-aggre2-noc"; 617 #interconnect-cells = <2>; 618 qcom,bcm-voters = <&apps_bcm_voter>; 619 }; 620 621 mmss_noc: interconnect@1740000 { 622 reg = <0 0x01740000 0 0x1e080>; 623 compatible = "qcom,sc7280-mmss-noc"; 624 #interconnect-cells = <2>; 625 qcom,bcm-voters = <&apps_bcm_voter>; 626 }; 627 628 ipa: ipa@1e40000 { 629 compatible = "qcom,sc7280-ipa"; 630 631 iommus = <&apps_smmu 0x480 0x0>, 632 <&apps_smmu 0x482 0x0>; 633 reg = <0 0x1e40000 0 0x8000>, 634 <0 0x1e50000 0 0x4ad0>, 635 <0 0x1e04000 0 0x23000>; 636 reg-names = "ipa-reg", 637 "ipa-shared", 638 "gsi"; 639 640 interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, 641 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 642 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 643 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 644 interrupt-names = "ipa", 645 "gsi", 646 "ipa-clock-query", 647 "ipa-setup-ready"; 648 649 clocks = <&rpmhcc RPMH_IPA_CLK>; 650 clock-names = "core"; 651 652 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 654 interconnect-names = "memory", 655 "config"; 656 657 qcom,smem-states = <&ipa_smp2p_out 0>, 658 <&ipa_smp2p_out 1>; 659 qcom,smem-state-names = "ipa-clock-enabled-valid", 660 "ipa-clock-enabled"; 661 662 status = "disabled"; 663 }; 664 665 tcsr_mutex: hwlock@1f40000 { 666 compatible = "qcom,tcsr-mutex", "syscon"; 667 reg = <0 0x01f40000 0 0x40000>; 668 #hwlock-cells = <1>; 669 }; 670 671 lpasscc: lpasscc@3000000 { 672 compatible = "qcom,sc7280-lpasscc"; 673 reg = <0 0x03000000 0 0x40>, 674 <0 0x03c04000 0 0x4>, 675 <0 0x03389000 0 0x24>; 676 reg-names = "qdsp6ss", "top_cc", "cc"; 677 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 678 clock-names = "iface"; 679 #clock-cells = <1>; 680 }; 681 682 lpass_ag_noc: interconnect@3c40000 { 683 reg = <0 0x03c40000 0 0xf080>; 684 compatible = "qcom,sc7280-lpass-ag-noc"; 685 #interconnect-cells = <2>; 686 qcom,bcm-voters = <&apps_bcm_voter>; 687 }; 688 689 gpu: gpu@3d00000 { 690 compatible = "qcom,adreno-635.0", "qcom,adreno"; 691 #stream-id-cells = <16>; 692 reg = <0 0x03d00000 0 0x40000>, 693 <0 0x03d9e000 0 0x1000>, 694 <0 0x03d61000 0 0x800>; 695 reg-names = "kgsl_3d0_reg_memory", 696 "cx_mem", 697 "cx_dbgc"; 698 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 699 iommus = <&adreno_smmu 0 0x401>; 700 operating-points-v2 = <&gpu_opp_table>; 701 qcom,gmu = <&gmu>; 702 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 703 interconnect-names = "gfx-mem"; 704 #cooling-cells = <2>; 705 706 gpu_opp_table: opp-table { 707 compatible = "operating-points-v2"; 708 709 opp-315000000 { 710 opp-hz = /bits/ 64 <315000000>; 711 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 712 opp-peak-kBps = <1804000>; 713 }; 714 715 opp-450000000 { 716 opp-hz = /bits/ 64 <450000000>; 717 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 718 opp-peak-kBps = <4068000>; 719 }; 720 721 opp-550000000 { 722 opp-hz = /bits/ 64 <550000000>; 723 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 724 opp-peak-kBps = <6832000>; 725 }; 726 }; 727 }; 728 729 gmu: gmu@3d69000 { 730 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 731 reg = <0 0x03d6a000 0 0x34000>, 732 <0 0x3de0000 0 0x10000>, 733 <0 0x0b290000 0 0x10000>; 734 reg-names = "gmu", "rscc", "gmu_pdc"; 735 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 737 interrupt-names = "hfi", "gmu"; 738 clocks = <&gpucc 5>, 739 <&gpucc 8>, 740 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 741 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 742 <&gpucc 2>, 743 <&gpucc 15>, 744 <&gpucc 11>; 745 clock-names = "gmu", 746 "cxo", 747 "axi", 748 "memnoc", 749 "ahb", 750 "hub", 751 "smmu_vote"; 752 power-domains = <&gpucc 0>, 753 <&gpucc 1>; 754 power-domain-names = "cx", 755 "gx"; 756 iommus = <&adreno_smmu 5 0x400>; 757 operating-points-v2 = <&gmu_opp_table>; 758 759 gmu_opp_table: opp-table { 760 compatible = "operating-points-v2"; 761 762 opp-200000000 { 763 opp-hz = /bits/ 64 <200000000>; 764 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 765 }; 766 }; 767 }; 768 769 gpucc: clock-controller@3d90000 { 770 compatible = "qcom,sc7280-gpucc"; 771 reg = <0 0x03d90000 0 0x9000>; 772 clocks = <&rpmhcc RPMH_CXO_CLK>, 773 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 774 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 775 clock-names = "bi_tcxo", 776 "gcc_gpu_gpll0_clk_src", 777 "gcc_gpu_gpll0_div_clk_src"; 778 #clock-cells = <1>; 779 #reset-cells = <1>; 780 #power-domain-cells = <1>; 781 }; 782 783 adreno_smmu: iommu@3da0000 { 784 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 785 reg = <0 0x03da0000 0 0x20000>; 786 #iommu-cells = <2>; 787 #global-interrupts = <2>; 788 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 800 801 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 802 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 803 <&gpucc 2>, 804 <&gpucc 11>, 805 <&gpucc 5>, 806 <&gpucc 15>, 807 <&gpucc 13>; 808 clock-names = "gcc_gpu_memnoc_gfx_clk", 809 "gcc_gpu_snoc_dvm_gfx_clk", 810 "gpu_cc_ahb_clk", 811 "gpu_cc_hlos1_vote_gpu_smmu_clk", 812 "gpu_cc_cx_gmu_clk", 813 "gpu_cc_hub_cx_int_clk", 814 "gpu_cc_hub_aon_clk"; 815 816 power-domains = <&gpucc 0>; 817 }; 818 819 stm@6002000 { 820 compatible = "arm,coresight-stm", "arm,primecell"; 821 reg = <0 0x06002000 0 0x1000>, 822 <0 0x16280000 0 0x180000>; 823 reg-names = "stm-base", "stm-stimulus-base"; 824 825 clocks = <&aoss_qmp>; 826 clock-names = "apb_pclk"; 827 828 out-ports { 829 port { 830 stm_out: endpoint { 831 remote-endpoint = <&funnel0_in7>; 832 }; 833 }; 834 }; 835 }; 836 837 funnel@6041000 { 838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 839 reg = <0 0x06041000 0 0x1000>; 840 841 clocks = <&aoss_qmp>; 842 clock-names = "apb_pclk"; 843 844 out-ports { 845 port { 846 funnel0_out: endpoint { 847 remote-endpoint = <&merge_funnel_in0>; 848 }; 849 }; 850 }; 851 852 in-ports { 853 #address-cells = <1>; 854 #size-cells = <0>; 855 856 port@7 { 857 reg = <7>; 858 funnel0_in7: endpoint { 859 remote-endpoint = <&stm_out>; 860 }; 861 }; 862 }; 863 }; 864 865 funnel@6042000 { 866 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 867 reg = <0 0x06042000 0 0x1000>; 868 869 clocks = <&aoss_qmp>; 870 clock-names = "apb_pclk"; 871 872 out-ports { 873 port { 874 funnel1_out: endpoint { 875 remote-endpoint = <&merge_funnel_in1>; 876 }; 877 }; 878 }; 879 880 in-ports { 881 #address-cells = <1>; 882 #size-cells = <0>; 883 884 port@4 { 885 reg = <4>; 886 funnel1_in4: endpoint { 887 remote-endpoint = <&apss_merge_funnel_out>; 888 }; 889 }; 890 }; 891 }; 892 893 funnel@6045000 { 894 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 895 reg = <0 0x06045000 0 0x1000>; 896 897 clocks = <&aoss_qmp>; 898 clock-names = "apb_pclk"; 899 900 out-ports { 901 port { 902 merge_funnel_out: endpoint { 903 remote-endpoint = <&swao_funnel_in>; 904 }; 905 }; 906 }; 907 908 in-ports { 909 #address-cells = <1>; 910 #size-cells = <0>; 911 912 port@0 { 913 reg = <0>; 914 merge_funnel_in0: endpoint { 915 remote-endpoint = <&funnel0_out>; 916 }; 917 }; 918 919 port@1 { 920 reg = <1>; 921 merge_funnel_in1: endpoint { 922 remote-endpoint = <&funnel1_out>; 923 }; 924 }; 925 }; 926 }; 927 928 replicator@6046000 { 929 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 930 reg = <0 0x06046000 0 0x1000>; 931 932 clocks = <&aoss_qmp>; 933 clock-names = "apb_pclk"; 934 935 out-ports { 936 port { 937 replicator_out: endpoint { 938 remote-endpoint = <&etr_in>; 939 }; 940 }; 941 }; 942 943 in-ports { 944 port { 945 replicator_in: endpoint { 946 remote-endpoint = <&swao_replicator_out>; 947 }; 948 }; 949 }; 950 }; 951 952 etr@6048000 { 953 compatible = "arm,coresight-tmc", "arm,primecell"; 954 reg = <0 0x06048000 0 0x1000>; 955 iommus = <&apps_smmu 0x04c0 0>; 956 957 clocks = <&aoss_qmp>; 958 clock-names = "apb_pclk"; 959 arm,scatter-gather; 960 961 in-ports { 962 port { 963 etr_in: endpoint { 964 remote-endpoint = <&replicator_out>; 965 }; 966 }; 967 }; 968 }; 969 970 funnel@6b04000 { 971 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 972 reg = <0 0x06b04000 0 0x1000>; 973 974 clocks = <&aoss_qmp>; 975 clock-names = "apb_pclk"; 976 977 out-ports { 978 port { 979 swao_funnel_out: endpoint { 980 remote-endpoint = <&etf_in>; 981 }; 982 }; 983 }; 984 985 in-ports { 986 #address-cells = <1>; 987 #size-cells = <0>; 988 989 port@7 { 990 reg = <7>; 991 swao_funnel_in: endpoint { 992 remote-endpoint = <&merge_funnel_out>; 993 }; 994 }; 995 }; 996 }; 997 998 etf@6b05000 { 999 compatible = "arm,coresight-tmc", "arm,primecell"; 1000 reg = <0 0x06b05000 0 0x1000>; 1001 1002 clocks = <&aoss_qmp>; 1003 clock-names = "apb_pclk"; 1004 1005 out-ports { 1006 port { 1007 etf_out: endpoint { 1008 remote-endpoint = <&swao_replicator_in>; 1009 }; 1010 }; 1011 }; 1012 1013 in-ports { 1014 port { 1015 etf_in: endpoint { 1016 remote-endpoint = <&swao_funnel_out>; 1017 }; 1018 }; 1019 }; 1020 }; 1021 1022 replicator@6b06000 { 1023 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1024 reg = <0 0x06b06000 0 0x1000>; 1025 1026 clocks = <&aoss_qmp>; 1027 clock-names = "apb_pclk"; 1028 qcom,replicator-loses-context; 1029 1030 out-ports { 1031 port { 1032 swao_replicator_out: endpoint { 1033 remote-endpoint = <&replicator_in>; 1034 }; 1035 }; 1036 }; 1037 1038 in-ports { 1039 port { 1040 swao_replicator_in: endpoint { 1041 remote-endpoint = <&etf_out>; 1042 }; 1043 }; 1044 }; 1045 }; 1046 1047 etm@7040000 { 1048 compatible = "arm,coresight-etm4x", "arm,primecell"; 1049 reg = <0 0x07040000 0 0x1000>; 1050 1051 cpu = <&CPU0>; 1052 1053 clocks = <&aoss_qmp>; 1054 clock-names = "apb_pclk"; 1055 arm,coresight-loses-context-with-cpu; 1056 qcom,skip-power-up; 1057 1058 out-ports { 1059 port { 1060 etm0_out: endpoint { 1061 remote-endpoint = <&apss_funnel_in0>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 etm@7140000 { 1068 compatible = "arm,coresight-etm4x", "arm,primecell"; 1069 reg = <0 0x07140000 0 0x1000>; 1070 1071 cpu = <&CPU1>; 1072 1073 clocks = <&aoss_qmp>; 1074 clock-names = "apb_pclk"; 1075 arm,coresight-loses-context-with-cpu; 1076 qcom,skip-power-up; 1077 1078 out-ports { 1079 port { 1080 etm1_out: endpoint { 1081 remote-endpoint = <&apss_funnel_in1>; 1082 }; 1083 }; 1084 }; 1085 }; 1086 1087 etm@7240000 { 1088 compatible = "arm,coresight-etm4x", "arm,primecell"; 1089 reg = <0 0x07240000 0 0x1000>; 1090 1091 cpu = <&CPU2>; 1092 1093 clocks = <&aoss_qmp>; 1094 clock-names = "apb_pclk"; 1095 arm,coresight-loses-context-with-cpu; 1096 qcom,skip-power-up; 1097 1098 out-ports { 1099 port { 1100 etm2_out: endpoint { 1101 remote-endpoint = <&apss_funnel_in2>; 1102 }; 1103 }; 1104 }; 1105 }; 1106 1107 etm@7340000 { 1108 compatible = "arm,coresight-etm4x", "arm,primecell"; 1109 reg = <0 0x07340000 0 0x1000>; 1110 1111 cpu = <&CPU3>; 1112 1113 clocks = <&aoss_qmp>; 1114 clock-names = "apb_pclk"; 1115 arm,coresight-loses-context-with-cpu; 1116 qcom,skip-power-up; 1117 1118 out-ports { 1119 port { 1120 etm3_out: endpoint { 1121 remote-endpoint = <&apss_funnel_in3>; 1122 }; 1123 }; 1124 }; 1125 }; 1126 1127 etm@7440000 { 1128 compatible = "arm,coresight-etm4x", "arm,primecell"; 1129 reg = <0 0x07440000 0 0x1000>; 1130 1131 cpu = <&CPU4>; 1132 1133 clocks = <&aoss_qmp>; 1134 clock-names = "apb_pclk"; 1135 arm,coresight-loses-context-with-cpu; 1136 qcom,skip-power-up; 1137 1138 out-ports { 1139 port { 1140 etm4_out: endpoint { 1141 remote-endpoint = <&apss_funnel_in4>; 1142 }; 1143 }; 1144 }; 1145 }; 1146 1147 etm@7540000 { 1148 compatible = "arm,coresight-etm4x", "arm,primecell"; 1149 reg = <0 0x07540000 0 0x1000>; 1150 1151 cpu = <&CPU5>; 1152 1153 clocks = <&aoss_qmp>; 1154 clock-names = "apb_pclk"; 1155 arm,coresight-loses-context-with-cpu; 1156 qcom,skip-power-up; 1157 1158 out-ports { 1159 port { 1160 etm5_out: endpoint { 1161 remote-endpoint = <&apss_funnel_in5>; 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 etm@7640000 { 1168 compatible = "arm,coresight-etm4x", "arm,primecell"; 1169 reg = <0 0x07640000 0 0x1000>; 1170 1171 cpu = <&CPU6>; 1172 1173 clocks = <&aoss_qmp>; 1174 clock-names = "apb_pclk"; 1175 arm,coresight-loses-context-with-cpu; 1176 qcom,skip-power-up; 1177 1178 out-ports { 1179 port { 1180 etm6_out: endpoint { 1181 remote-endpoint = <&apss_funnel_in6>; 1182 }; 1183 }; 1184 }; 1185 }; 1186 1187 etm@7740000 { 1188 compatible = "arm,coresight-etm4x", "arm,primecell"; 1189 reg = <0 0x07740000 0 0x1000>; 1190 1191 cpu = <&CPU7>; 1192 1193 clocks = <&aoss_qmp>; 1194 clock-names = "apb_pclk"; 1195 arm,coresight-loses-context-with-cpu; 1196 qcom,skip-power-up; 1197 1198 out-ports { 1199 port { 1200 etm7_out: endpoint { 1201 remote-endpoint = <&apss_funnel_in7>; 1202 }; 1203 }; 1204 }; 1205 }; 1206 1207 funnel@7800000 { /* APSS Funnel */ 1208 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1209 reg = <0 0x07800000 0 0x1000>; 1210 1211 clocks = <&aoss_qmp>; 1212 clock-names = "apb_pclk"; 1213 1214 out-ports { 1215 port { 1216 apss_funnel_out: endpoint { 1217 remote-endpoint = <&apss_merge_funnel_in>; 1218 }; 1219 }; 1220 }; 1221 1222 in-ports { 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 1226 port@0 { 1227 reg = <0>; 1228 apss_funnel_in0: endpoint { 1229 remote-endpoint = <&etm0_out>; 1230 }; 1231 }; 1232 1233 port@1 { 1234 reg = <1>; 1235 apss_funnel_in1: endpoint { 1236 remote-endpoint = <&etm1_out>; 1237 }; 1238 }; 1239 1240 port@2 { 1241 reg = <2>; 1242 apss_funnel_in2: endpoint { 1243 remote-endpoint = <&etm2_out>; 1244 }; 1245 }; 1246 1247 port@3 { 1248 reg = <3>; 1249 apss_funnel_in3: endpoint { 1250 remote-endpoint = <&etm3_out>; 1251 }; 1252 }; 1253 1254 port@4 { 1255 reg = <4>; 1256 apss_funnel_in4: endpoint { 1257 remote-endpoint = <&etm4_out>; 1258 }; 1259 }; 1260 1261 port@5 { 1262 reg = <5>; 1263 apss_funnel_in5: endpoint { 1264 remote-endpoint = <&etm5_out>; 1265 }; 1266 }; 1267 1268 port@6 { 1269 reg = <6>; 1270 apss_funnel_in6: endpoint { 1271 remote-endpoint = <&etm6_out>; 1272 }; 1273 }; 1274 1275 port@7 { 1276 reg = <7>; 1277 apss_funnel_in7: endpoint { 1278 remote-endpoint = <&etm7_out>; 1279 }; 1280 }; 1281 }; 1282 }; 1283 1284 funnel@7810000 { 1285 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1286 reg = <0 0x07810000 0 0x1000>; 1287 1288 clocks = <&aoss_qmp>; 1289 clock-names = "apb_pclk"; 1290 1291 out-ports { 1292 port { 1293 apss_merge_funnel_out: endpoint { 1294 remote-endpoint = <&funnel1_in4>; 1295 }; 1296 }; 1297 }; 1298 1299 in-ports { 1300 port { 1301 apss_merge_funnel_in: endpoint { 1302 remote-endpoint = <&apss_funnel_out>; 1303 }; 1304 }; 1305 }; 1306 }; 1307 1308 sdhc_2: sdhci@8804000 { 1309 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1310 status = "disabled"; 1311 1312 reg = <0 0x08804000 0 0x1000>; 1313 1314 iommus = <&apps_smmu 0x100 0x0>; 1315 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1317 interrupt-names = "hc_irq", "pwr_irq"; 1318 1319 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1320 <&gcc GCC_SDCC2_AHB_CLK>, 1321 <&rpmhcc RPMH_CXO_CLK>; 1322 clock-names = "core", "iface", "xo"; 1323 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1325 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1326 power-domains = <&rpmhpd SC7280_CX>; 1327 operating-points-v2 = <&sdhc2_opp_table>; 1328 1329 bus-width = <4>; 1330 1331 qcom,dll-config = <0x0007642c>; 1332 1333 sdhc2_opp_table: opp-table { 1334 compatible = "operating-points-v2"; 1335 1336 opp-100000000 { 1337 opp-hz = /bits/ 64 <100000000>; 1338 required-opps = <&rpmhpd_opp_low_svs>; 1339 opp-peak-kBps = <1800000 400000>; 1340 opp-avg-kBps = <100000 0>; 1341 }; 1342 1343 opp-202000000 { 1344 opp-hz = /bits/ 64 <202000000>; 1345 required-opps = <&rpmhpd_opp_nom>; 1346 opp-peak-kBps = <5400000 1600000>; 1347 opp-avg-kBps = <200000 0>; 1348 }; 1349 }; 1350 1351 }; 1352 1353 usb_1_hsphy: phy@88e3000 { 1354 compatible = "qcom,sc7280-usb-hs-phy", 1355 "qcom,usb-snps-hs-7nm-phy"; 1356 reg = <0 0x088e3000 0 0x400>; 1357 status = "disabled"; 1358 #phy-cells = <0>; 1359 1360 clocks = <&rpmhcc RPMH_CXO_CLK>; 1361 clock-names = "ref"; 1362 1363 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1364 }; 1365 1366 usb_2_hsphy: phy@88e4000 { 1367 compatible = "qcom,sc7280-usb-hs-phy", 1368 "qcom,usb-snps-hs-7nm-phy"; 1369 reg = <0 0x088e4000 0 0x400>; 1370 status = "disabled"; 1371 #phy-cells = <0>; 1372 1373 clocks = <&rpmhcc RPMH_CXO_CLK>; 1374 clock-names = "ref"; 1375 1376 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1377 }; 1378 1379 usb_1_qmpphy: phy-wrapper@88e9000 { 1380 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1381 "qcom,sm8250-qmp-usb3-dp-phy"; 1382 reg = <0 0x088e9000 0 0x200>, 1383 <0 0x088e8000 0 0x40>, 1384 <0 0x088ea000 0 0x200>; 1385 status = "disabled"; 1386 #address-cells = <2>; 1387 #size-cells = <2>; 1388 ranges; 1389 1390 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1391 <&rpmhcc RPMH_CXO_CLK>, 1392 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1393 clock-names = "aux", "ref_clk_src", "com_aux"; 1394 1395 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1396 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1397 reset-names = "phy", "common"; 1398 1399 usb_1_ssphy: usb3-phy@88e9200 { 1400 reg = <0 0x088e9200 0 0x200>, 1401 <0 0x088e9400 0 0x200>, 1402 <0 0x088e9c00 0 0x400>, 1403 <0 0x088e9600 0 0x200>, 1404 <0 0x088e9800 0 0x200>, 1405 <0 0x088e9a00 0 0x100>; 1406 #clock-cells = <0>; 1407 #phy-cells = <0>; 1408 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1409 clock-names = "pipe0"; 1410 clock-output-names = "usb3_phy_pipe_clk_src"; 1411 }; 1412 1413 dp_phy: dp-phy@88ea200 { 1414 reg = <0 0x088ea200 0 0x200>, 1415 <0 0x088ea400 0 0x200>, 1416 <0 0x088eaa00 0 0x200>, 1417 <0 0x088ea600 0 0x200>, 1418 <0 0x088ea800 0 0x200>; 1419 #phy-cells = <0>; 1420 #clock-cells = <1>; 1421 }; 1422 }; 1423 1424 usb_2: usb@8cf8800 { 1425 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1426 reg = <0 0x08cf8800 0 0x400>; 1427 status = "disabled"; 1428 #address-cells = <2>; 1429 #size-cells = <2>; 1430 ranges; 1431 dma-ranges; 1432 1433 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1434 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1435 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1436 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1437 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1438 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1439 "sleep"; 1440 1441 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1442 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1443 assigned-clock-rates = <19200000>, <200000000>; 1444 1445 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1446 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1447 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1448 interrupt-names = "hs_phy_irq", 1449 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1450 1451 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1452 1453 resets = <&gcc GCC_USB30_SEC_BCR>; 1454 1455 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1456 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1457 interconnect-names = "usb-ddr", "apps-usb"; 1458 1459 usb_2_dwc3: usb@8c00000 { 1460 compatible = "snps,dwc3"; 1461 reg = <0 0x08c00000 0 0xe000>; 1462 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1463 iommus = <&apps_smmu 0xa0 0x0>; 1464 snps,dis_u2_susphy_quirk; 1465 snps,dis_enblslpm_quirk; 1466 phys = <&usb_2_hsphy>; 1467 phy-names = "usb2-phy"; 1468 maximum-speed = "high-speed"; 1469 }; 1470 }; 1471 1472 dc_noc: interconnect@90e0000 { 1473 reg = <0 0x090e0000 0 0x5080>; 1474 compatible = "qcom,sc7280-dc-noc"; 1475 #interconnect-cells = <2>; 1476 qcom,bcm-voters = <&apps_bcm_voter>; 1477 }; 1478 1479 gem_noc: interconnect@9100000 { 1480 reg = <0 0x9100000 0 0xe2200>; 1481 compatible = "qcom,sc7280-gem-noc"; 1482 #interconnect-cells = <2>; 1483 qcom,bcm-voters = <&apps_bcm_voter>; 1484 }; 1485 1486 system-cache-controller@9200000 { 1487 compatible = "qcom,sc7280-llcc"; 1488 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1489 reg-names = "llcc_base", "llcc_broadcast_base"; 1490 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1491 }; 1492 1493 nsp_noc: interconnect@a0c0000 { 1494 reg = <0 0x0a0c0000 0 0x10000>; 1495 compatible = "qcom,sc7280-nsp-noc"; 1496 #interconnect-cells = <2>; 1497 qcom,bcm-voters = <&apps_bcm_voter>; 1498 }; 1499 1500 usb_1: usb@a6f8800 { 1501 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1502 reg = <0 0x0a6f8800 0 0x400>; 1503 status = "disabled"; 1504 #address-cells = <2>; 1505 #size-cells = <2>; 1506 ranges; 1507 dma-ranges; 1508 1509 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1510 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1511 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1512 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1513 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1514 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1515 "sleep"; 1516 1517 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1518 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1519 assigned-clock-rates = <19200000>, <200000000>; 1520 1521 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1522 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1523 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1524 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1525 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1526 "dm_hs_phy_irq", "ss_phy_irq"; 1527 1528 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1529 1530 resets = <&gcc GCC_USB30_PRIM_BCR>; 1531 1532 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1533 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1534 interconnect-names = "usb-ddr", "apps-usb"; 1535 1536 usb_1_dwc3: usb@a600000 { 1537 compatible = "snps,dwc3"; 1538 reg = <0 0x0a600000 0 0xe000>; 1539 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1540 iommus = <&apps_smmu 0xe0 0x0>; 1541 snps,dis_u2_susphy_quirk; 1542 snps,dis_enblslpm_quirk; 1543 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1544 phy-names = "usb2-phy", "usb3-phy"; 1545 maximum-speed = "super-speed"; 1546 }; 1547 }; 1548 1549 videocc: clock-controller@aaf0000 { 1550 compatible = "qcom,sc7280-videocc"; 1551 reg = <0 0xaaf0000 0 0x10000>; 1552 clocks = <&rpmhcc RPMH_CXO_CLK>, 1553 <&rpmhcc RPMH_CXO_CLK_A>; 1554 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1555 #clock-cells = <1>; 1556 #reset-cells = <1>; 1557 #power-domain-cells = <1>; 1558 }; 1559 1560 dispcc: clock-controller@af00000 { 1561 compatible = "qcom,sc7280-dispcc"; 1562 reg = <0 0xaf00000 0 0x20000>; 1563 clocks = <&rpmhcc RPMH_CXO_CLK>, 1564 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1565 <0>, <0>, <0>, <0>, <0>, <0>; 1566 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1567 "dsi0_phy_pll_out_byteclk", 1568 "dsi0_phy_pll_out_dsiclk", 1569 "dp_phy_pll_link_clk", 1570 "dp_phy_pll_vco_div_clk", 1571 "edp_phy_pll_link_clk", 1572 "edp_phy_pll_vco_div_clk"; 1573 #clock-cells = <1>; 1574 #reset-cells = <1>; 1575 #power-domain-cells = <1>; 1576 }; 1577 1578 pdc: interrupt-controller@b220000 { 1579 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1580 reg = <0 0x0b220000 0 0x30000>; 1581 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1582 <55 306 4>, <59 312 3>, <62 374 2>, 1583 <64 434 2>, <66 438 3>, <69 86 1>, 1584 <70 520 54>, <124 609 31>, <155 63 1>, 1585 <156 716 12>; 1586 #interrupt-cells = <2>; 1587 interrupt-parent = <&intc>; 1588 interrupt-controller; 1589 }; 1590 1591 pdc_reset: reset-controller@b5e0000 { 1592 compatible = "qcom,sc7280-pdc-global"; 1593 reg = <0 0x0b5e0000 0 0x20000>; 1594 #reset-cells = <1>; 1595 }; 1596 1597 tsens0: thermal-sensor@c263000 { 1598 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1599 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1600 <0 0x0c222000 0 0x1ff>; /* SROT */ 1601 #qcom,sensors = <15>; 1602 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1604 interrupt-names = "uplow","critical"; 1605 #thermal-sensor-cells = <1>; 1606 }; 1607 1608 tsens1: thermal-sensor@c265000 { 1609 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1610 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1611 <0 0x0c223000 0 0x1ff>; /* SROT */ 1612 #qcom,sensors = <12>; 1613 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1615 interrupt-names = "uplow","critical"; 1616 #thermal-sensor-cells = <1>; 1617 }; 1618 1619 aoss_reset: reset-controller@c2a0000 { 1620 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1621 reg = <0 0x0c2a0000 0 0x31000>; 1622 #reset-cells = <1>; 1623 }; 1624 1625 aoss_qmp: power-controller@c300000 { 1626 compatible = "qcom,sc7280-aoss-qmp"; 1627 reg = <0 0x0c300000 0 0x100000>; 1628 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1629 IPCC_MPROC_SIGNAL_GLINK_QMP 1630 IRQ_TYPE_EDGE_RISING>; 1631 mboxes = <&ipcc IPCC_CLIENT_AOP 1632 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1633 1634 #clock-cells = <0>; 1635 #power-domain-cells = <1>; 1636 }; 1637 1638 spmi_bus: spmi@c440000 { 1639 compatible = "qcom,spmi-pmic-arb"; 1640 reg = <0 0x0c440000 0 0x1100>, 1641 <0 0x0c600000 0 0x2000000>, 1642 <0 0x0e600000 0 0x100000>, 1643 <0 0x0e700000 0 0xa0000>, 1644 <0 0x0c40a000 0 0x26000>; 1645 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1646 interrupt-names = "periph_irq"; 1647 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1648 qcom,ee = <0>; 1649 qcom,channel = <0>; 1650 #address-cells = <1>; 1651 #size-cells = <1>; 1652 interrupt-controller; 1653 #interrupt-cells = <4>; 1654 }; 1655 1656 tlmm: pinctrl@f100000 { 1657 compatible = "qcom,sc7280-pinctrl"; 1658 reg = <0 0x0f100000 0 0x300000>; 1659 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1660 gpio-controller; 1661 #gpio-cells = <2>; 1662 interrupt-controller; 1663 #interrupt-cells = <2>; 1664 gpio-ranges = <&tlmm 0 0 175>; 1665 wakeup-parent = <&pdc>; 1666 1667 qup_uart5_default: qup-uart5-default { 1668 pins = "gpio46", "gpio47"; 1669 function = "qup13"; 1670 }; 1671 1672 sdc1_on: sdc1-on { 1673 clk { 1674 pins = "sdc1_clk"; 1675 }; 1676 1677 cmd { 1678 pins = "sdc1_cmd"; 1679 }; 1680 1681 data { 1682 pins = "sdc1_data"; 1683 }; 1684 1685 rclk { 1686 pins = "sdc1_rclk"; 1687 }; 1688 }; 1689 1690 sdc1_off: sdc1-off { 1691 clk { 1692 pins = "sdc1_clk"; 1693 drive-strength = <2>; 1694 bias-bus-hold; 1695 }; 1696 1697 cmd { 1698 pins = "sdc1_cmd"; 1699 drive-strength = <2>; 1700 bias-bus-hold; 1701 }; 1702 1703 data { 1704 pins = "sdc1_data"; 1705 drive-strength = <2>; 1706 bias-bus-hold; 1707 }; 1708 1709 rclk { 1710 pins = "sdc1_rclk"; 1711 bias-bus-hold; 1712 }; 1713 }; 1714 1715 sdc2_on: sdc2-on { 1716 clk { 1717 pins = "sdc2_clk"; 1718 }; 1719 1720 cmd { 1721 pins = "sdc2_cmd"; 1722 }; 1723 1724 data { 1725 pins = "sdc2_data"; 1726 }; 1727 }; 1728 1729 sdc2_off: sdc2-off { 1730 clk { 1731 pins = "sdc2_clk"; 1732 drive-strength = <2>; 1733 bias-bus-hold; 1734 }; 1735 1736 cmd { 1737 pins ="sdc2_cmd"; 1738 drive-strength = <2>; 1739 bias-bus-hold; 1740 }; 1741 1742 data { 1743 pins ="sdc2_data"; 1744 drive-strength = <2>; 1745 bias-bus-hold; 1746 }; 1747 }; 1748 }; 1749 1750 apps_smmu: iommu@15000000 { 1751 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1752 reg = <0 0x15000000 0 0x100000>; 1753 #iommu-cells = <2>; 1754 #global-interrupts = <1>; 1755 dma-coherent; 1756 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1837 }; 1838 1839 intc: interrupt-controller@17a00000 { 1840 compatible = "arm,gic-v3"; 1841 #address-cells = <2>; 1842 #size-cells = <2>; 1843 ranges; 1844 #interrupt-cells = <3>; 1845 interrupt-controller; 1846 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1847 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1848 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1849 1850 gic-its@17a40000 { 1851 compatible = "arm,gic-v3-its"; 1852 msi-controller; 1853 #msi-cells = <1>; 1854 reg = <0 0x17a40000 0 0x20000>; 1855 status = "disabled"; 1856 }; 1857 }; 1858 1859 watchdog@17c10000 { 1860 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1861 reg = <0 0x17c10000 0 0x1000>; 1862 clocks = <&sleep_clk>; 1863 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1864 }; 1865 1866 timer@17c20000 { 1867 #address-cells = <2>; 1868 #size-cells = <2>; 1869 ranges; 1870 compatible = "arm,armv7-timer-mem"; 1871 reg = <0 0x17c20000 0 0x1000>; 1872 1873 frame@17c21000 { 1874 frame-number = <0>; 1875 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1877 reg = <0 0x17c21000 0 0x1000>, 1878 <0 0x17c22000 0 0x1000>; 1879 }; 1880 1881 frame@17c23000 { 1882 frame-number = <1>; 1883 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1884 reg = <0 0x17c23000 0 0x1000>; 1885 status = "disabled"; 1886 }; 1887 1888 frame@17c25000 { 1889 frame-number = <2>; 1890 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1891 reg = <0 0x17c25000 0 0x1000>; 1892 status = "disabled"; 1893 }; 1894 1895 frame@17c27000 { 1896 frame-number = <3>; 1897 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1898 reg = <0 0x17c27000 0 0x1000>; 1899 status = "disabled"; 1900 }; 1901 1902 frame@17c29000 { 1903 frame-number = <4>; 1904 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1905 reg = <0 0x17c29000 0 0x1000>; 1906 status = "disabled"; 1907 }; 1908 1909 frame@17c2b000 { 1910 frame-number = <5>; 1911 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1912 reg = <0 0x17c2b000 0 0x1000>; 1913 status = "disabled"; 1914 }; 1915 1916 frame@17c2d000 { 1917 frame-number = <6>; 1918 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1919 reg = <0 0x17c2d000 0 0x1000>; 1920 status = "disabled"; 1921 }; 1922 }; 1923 1924 apps_rsc: rsc@18200000 { 1925 compatible = "qcom,rpmh-rsc"; 1926 reg = <0 0x18200000 0 0x10000>, 1927 <0 0x18210000 0 0x10000>, 1928 <0 0x18220000 0 0x10000>; 1929 reg-names = "drv-0", "drv-1", "drv-2"; 1930 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1933 qcom,tcs-offset = <0xd00>; 1934 qcom,drv-id = <2>; 1935 qcom,tcs-config = <ACTIVE_TCS 2>, 1936 <SLEEP_TCS 3>, 1937 <WAKE_TCS 3>, 1938 <CONTROL_TCS 1>; 1939 1940 apps_bcm_voter: bcm-voter { 1941 compatible = "qcom,bcm-voter"; 1942 }; 1943 1944 rpmhpd: power-controller { 1945 compatible = "qcom,sc7280-rpmhpd"; 1946 #power-domain-cells = <1>; 1947 operating-points-v2 = <&rpmhpd_opp_table>; 1948 1949 rpmhpd_opp_table: opp-table { 1950 compatible = "operating-points-v2"; 1951 1952 rpmhpd_opp_ret: opp1 { 1953 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1954 }; 1955 1956 rpmhpd_opp_low_svs: opp2 { 1957 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1958 }; 1959 1960 rpmhpd_opp_svs: opp3 { 1961 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1962 }; 1963 1964 rpmhpd_opp_svs_l1: opp4 { 1965 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1966 }; 1967 1968 rpmhpd_opp_svs_l2: opp5 { 1969 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1970 }; 1971 1972 rpmhpd_opp_nom: opp6 { 1973 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1974 }; 1975 1976 rpmhpd_opp_nom_l1: opp7 { 1977 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1978 }; 1979 1980 rpmhpd_opp_turbo: opp8 { 1981 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1982 }; 1983 1984 rpmhpd_opp_turbo_l1: opp9 { 1985 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1986 }; 1987 }; 1988 }; 1989 1990 rpmhcc: clock-controller { 1991 compatible = "qcom,sc7280-rpmh-clk"; 1992 clocks = <&xo_board>; 1993 clock-names = "xo"; 1994 #clock-cells = <1>; 1995 }; 1996 }; 1997 1998 cpufreq_hw: cpufreq@18591000 { 1999 compatible = "qcom,cpufreq-epss"; 2000 reg = <0 0x18591100 0 0x900>, 2001 <0 0x18592100 0 0x900>, 2002 <0 0x18593100 0 0x900>; 2003 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2004 clock-names = "xo", "alternate"; 2005 #freq-domain-cells = <1>; 2006 }; 2007 }; 2008 2009 thermal_zones: thermal-zones { 2010 cpu0-thermal { 2011 polling-delay-passive = <250>; 2012 polling-delay = <0>; 2013 2014 thermal-sensors = <&tsens0 1>; 2015 2016 trips { 2017 cpu0_alert0: trip-point0 { 2018 temperature = <90000>; 2019 hysteresis = <2000>; 2020 type = "passive"; 2021 }; 2022 2023 cpu0_alert1: trip-point1 { 2024 temperature = <95000>; 2025 hysteresis = <2000>; 2026 type = "passive"; 2027 }; 2028 2029 cpu0_crit: cpu-crit { 2030 temperature = <110000>; 2031 hysteresis = <0>; 2032 type = "critical"; 2033 }; 2034 }; 2035 2036 cooling-maps { 2037 map0 { 2038 trip = <&cpu0_alert0>; 2039 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2040 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2041 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2042 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2043 }; 2044 map1 { 2045 trip = <&cpu0_alert1>; 2046 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2047 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2048 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2049 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2050 }; 2051 }; 2052 }; 2053 2054 cpu1-thermal { 2055 polling-delay-passive = <250>; 2056 polling-delay = <0>; 2057 2058 thermal-sensors = <&tsens0 2>; 2059 2060 trips { 2061 cpu1_alert0: trip-point0 { 2062 temperature = <90000>; 2063 hysteresis = <2000>; 2064 type = "passive"; 2065 }; 2066 2067 cpu1_alert1: trip-point1 { 2068 temperature = <95000>; 2069 hysteresis = <2000>; 2070 type = "passive"; 2071 }; 2072 2073 cpu1_crit: cpu-crit { 2074 temperature = <110000>; 2075 hysteresis = <0>; 2076 type = "critical"; 2077 }; 2078 }; 2079 2080 cooling-maps { 2081 map0 { 2082 trip = <&cpu1_alert0>; 2083 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2084 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2085 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2086 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2087 }; 2088 map1 { 2089 trip = <&cpu1_alert1>; 2090 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2091 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2092 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2093 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2094 }; 2095 }; 2096 }; 2097 2098 cpu2-thermal { 2099 polling-delay-passive = <250>; 2100 polling-delay = <0>; 2101 2102 thermal-sensors = <&tsens0 3>; 2103 2104 trips { 2105 cpu2_alert0: trip-point0 { 2106 temperature = <90000>; 2107 hysteresis = <2000>; 2108 type = "passive"; 2109 }; 2110 2111 cpu2_alert1: trip-point1 { 2112 temperature = <95000>; 2113 hysteresis = <2000>; 2114 type = "passive"; 2115 }; 2116 2117 cpu2_crit: cpu-crit { 2118 temperature = <110000>; 2119 hysteresis = <0>; 2120 type = "critical"; 2121 }; 2122 }; 2123 2124 cooling-maps { 2125 map0 { 2126 trip = <&cpu2_alert0>; 2127 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2128 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2129 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2130 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2131 }; 2132 map1 { 2133 trip = <&cpu2_alert1>; 2134 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2135 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2136 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2137 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2138 }; 2139 }; 2140 }; 2141 2142 cpu3-thermal { 2143 polling-delay-passive = <250>; 2144 polling-delay = <0>; 2145 2146 thermal-sensors = <&tsens0 4>; 2147 2148 trips { 2149 cpu3_alert0: trip-point0 { 2150 temperature = <90000>; 2151 hysteresis = <2000>; 2152 type = "passive"; 2153 }; 2154 2155 cpu3_alert1: trip-point1 { 2156 temperature = <95000>; 2157 hysteresis = <2000>; 2158 type = "passive"; 2159 }; 2160 2161 cpu3_crit: cpu-crit { 2162 temperature = <110000>; 2163 hysteresis = <0>; 2164 type = "critical"; 2165 }; 2166 }; 2167 2168 cooling-maps { 2169 map0 { 2170 trip = <&cpu3_alert0>; 2171 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2172 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2173 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2174 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2175 }; 2176 map1 { 2177 trip = <&cpu3_alert1>; 2178 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2179 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2180 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2181 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2182 }; 2183 }; 2184 }; 2185 2186 cpu4-thermal { 2187 polling-delay-passive = <250>; 2188 polling-delay = <0>; 2189 2190 thermal-sensors = <&tsens0 7>; 2191 2192 trips { 2193 cpu4_alert0: trip-point0 { 2194 temperature = <90000>; 2195 hysteresis = <2000>; 2196 type = "passive"; 2197 }; 2198 2199 cpu4_alert1: trip-point1 { 2200 temperature = <95000>; 2201 hysteresis = <2000>; 2202 type = "passive"; 2203 }; 2204 2205 cpu4_crit: cpu-crit { 2206 temperature = <110000>; 2207 hysteresis = <0>; 2208 type = "critical"; 2209 }; 2210 }; 2211 2212 cooling-maps { 2213 map0 { 2214 trip = <&cpu4_alert0>; 2215 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2216 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2217 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2218 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2219 }; 2220 map1 { 2221 trip = <&cpu4_alert1>; 2222 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2223 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2224 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2225 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2226 }; 2227 }; 2228 }; 2229 2230 cpu5-thermal { 2231 polling-delay-passive = <250>; 2232 polling-delay = <0>; 2233 2234 thermal-sensors = <&tsens0 8>; 2235 2236 trips { 2237 cpu5_alert0: trip-point0 { 2238 temperature = <90000>; 2239 hysteresis = <2000>; 2240 type = "passive"; 2241 }; 2242 2243 cpu5_alert1: trip-point1 { 2244 temperature = <95000>; 2245 hysteresis = <2000>; 2246 type = "passive"; 2247 }; 2248 2249 cpu5_crit: cpu-crit { 2250 temperature = <110000>; 2251 hysteresis = <0>; 2252 type = "critical"; 2253 }; 2254 }; 2255 2256 cooling-maps { 2257 map0 { 2258 trip = <&cpu5_alert0>; 2259 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2260 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2261 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2262 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2263 }; 2264 map1 { 2265 trip = <&cpu5_alert1>; 2266 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2267 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2268 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2269 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2270 }; 2271 }; 2272 }; 2273 2274 cpu6-thermal { 2275 polling-delay-passive = <250>; 2276 polling-delay = <0>; 2277 2278 thermal-sensors = <&tsens0 9>; 2279 2280 trips { 2281 cpu6_alert0: trip-point0 { 2282 temperature = <90000>; 2283 hysteresis = <2000>; 2284 type = "passive"; 2285 }; 2286 2287 cpu6_alert1: trip-point1 { 2288 temperature = <95000>; 2289 hysteresis = <2000>; 2290 type = "passive"; 2291 }; 2292 2293 cpu6_crit: cpu-crit { 2294 temperature = <110000>; 2295 hysteresis = <0>; 2296 type = "critical"; 2297 }; 2298 }; 2299 2300 cooling-maps { 2301 map0 { 2302 trip = <&cpu6_alert0>; 2303 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2304 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2305 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2306 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2307 }; 2308 map1 { 2309 trip = <&cpu6_alert1>; 2310 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2311 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2312 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2313 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2314 }; 2315 }; 2316 }; 2317 2318 cpu7-thermal { 2319 polling-delay-passive = <250>; 2320 polling-delay = <0>; 2321 2322 thermal-sensors = <&tsens0 10>; 2323 2324 trips { 2325 cpu7_alert0: trip-point0 { 2326 temperature = <90000>; 2327 hysteresis = <2000>; 2328 type = "passive"; 2329 }; 2330 2331 cpu7_alert1: trip-point1 { 2332 temperature = <95000>; 2333 hysteresis = <2000>; 2334 type = "passive"; 2335 }; 2336 2337 cpu7_crit: cpu-crit { 2338 temperature = <110000>; 2339 hysteresis = <0>; 2340 type = "critical"; 2341 }; 2342 }; 2343 2344 cooling-maps { 2345 map0 { 2346 trip = <&cpu7_alert0>; 2347 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2348 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2349 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2350 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2351 }; 2352 map1 { 2353 trip = <&cpu7_alert1>; 2354 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2355 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2356 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2357 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2358 }; 2359 }; 2360 }; 2361 2362 cpu8-thermal { 2363 polling-delay-passive = <250>; 2364 polling-delay = <0>; 2365 2366 thermal-sensors = <&tsens0 11>; 2367 2368 trips { 2369 cpu8_alert0: trip-point0 { 2370 temperature = <90000>; 2371 hysteresis = <2000>; 2372 type = "passive"; 2373 }; 2374 2375 cpu8_alert1: trip-point1 { 2376 temperature = <95000>; 2377 hysteresis = <2000>; 2378 type = "passive"; 2379 }; 2380 2381 cpu8_crit: cpu-crit { 2382 temperature = <110000>; 2383 hysteresis = <0>; 2384 type = "critical"; 2385 }; 2386 }; 2387 2388 cooling-maps { 2389 map0 { 2390 trip = <&cpu8_alert0>; 2391 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2392 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2393 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2394 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2395 }; 2396 map1 { 2397 trip = <&cpu8_alert1>; 2398 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2399 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2400 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2401 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2402 }; 2403 }; 2404 }; 2405 2406 cpu9-thermal { 2407 polling-delay-passive = <250>; 2408 polling-delay = <0>; 2409 2410 thermal-sensors = <&tsens0 12>; 2411 2412 trips { 2413 cpu9_alert0: trip-point0 { 2414 temperature = <90000>; 2415 hysteresis = <2000>; 2416 type = "passive"; 2417 }; 2418 2419 cpu9_alert1: trip-point1 { 2420 temperature = <95000>; 2421 hysteresis = <2000>; 2422 type = "passive"; 2423 }; 2424 2425 cpu9_crit: cpu-crit { 2426 temperature = <110000>; 2427 hysteresis = <0>; 2428 type = "critical"; 2429 }; 2430 }; 2431 2432 cooling-maps { 2433 map0 { 2434 trip = <&cpu9_alert0>; 2435 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2436 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2437 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2438 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2439 }; 2440 map1 { 2441 trip = <&cpu9_alert1>; 2442 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2443 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2444 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2445 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2446 }; 2447 }; 2448 }; 2449 2450 cpu10-thermal { 2451 polling-delay-passive = <250>; 2452 polling-delay = <0>; 2453 2454 thermal-sensors = <&tsens0 13>; 2455 2456 trips { 2457 cpu10_alert0: trip-point0 { 2458 temperature = <90000>; 2459 hysteresis = <2000>; 2460 type = "passive"; 2461 }; 2462 2463 cpu10_alert1: trip-point1 { 2464 temperature = <95000>; 2465 hysteresis = <2000>; 2466 type = "passive"; 2467 }; 2468 2469 cpu10_crit: cpu-crit { 2470 temperature = <110000>; 2471 hysteresis = <0>; 2472 type = "critical"; 2473 }; 2474 }; 2475 2476 cooling-maps { 2477 map0 { 2478 trip = <&cpu10_alert0>; 2479 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2480 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2481 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2482 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2483 }; 2484 map1 { 2485 trip = <&cpu10_alert1>; 2486 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2487 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2488 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2489 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2490 }; 2491 }; 2492 }; 2493 2494 cpu11-thermal { 2495 polling-delay-passive = <250>; 2496 polling-delay = <0>; 2497 2498 thermal-sensors = <&tsens0 14>; 2499 2500 trips { 2501 cpu11_alert0: trip-point0 { 2502 temperature = <90000>; 2503 hysteresis = <2000>; 2504 type = "passive"; 2505 }; 2506 2507 cpu11_alert1: trip-point1 { 2508 temperature = <95000>; 2509 hysteresis = <2000>; 2510 type = "passive"; 2511 }; 2512 2513 cpu11_crit: cpu-crit { 2514 temperature = <110000>; 2515 hysteresis = <0>; 2516 type = "critical"; 2517 }; 2518 }; 2519 2520 cooling-maps { 2521 map0 { 2522 trip = <&cpu11_alert0>; 2523 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2524 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2525 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2526 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2527 }; 2528 map1 { 2529 trip = <&cpu11_alert1>; 2530 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2531 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2532 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2533 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2534 }; 2535 }; 2536 }; 2537 2538 aoss0-thermal { 2539 polling-delay-passive = <0>; 2540 polling-delay = <0>; 2541 2542 thermal-sensors = <&tsens0 0>; 2543 2544 trips { 2545 aoss0_alert0: trip-point0 { 2546 temperature = <90000>; 2547 hysteresis = <2000>; 2548 type = "hot"; 2549 }; 2550 2551 aoss0_crit: aoss0-crit { 2552 temperature = <110000>; 2553 hysteresis = <0>; 2554 type = "critical"; 2555 }; 2556 }; 2557 }; 2558 2559 aoss1-thermal { 2560 polling-delay-passive = <0>; 2561 polling-delay = <0>; 2562 2563 thermal-sensors = <&tsens1 0>; 2564 2565 trips { 2566 aoss1_alert0: trip-point0 { 2567 temperature = <90000>; 2568 hysteresis = <2000>; 2569 type = "hot"; 2570 }; 2571 2572 aoss1_crit: aoss1-crit { 2573 temperature = <110000>; 2574 hysteresis = <0>; 2575 type = "critical"; 2576 }; 2577 }; 2578 }; 2579 2580 cpuss0-thermal { 2581 polling-delay-passive = <0>; 2582 polling-delay = <0>; 2583 2584 thermal-sensors = <&tsens0 5>; 2585 2586 trips { 2587 cpuss0_alert0: trip-point0 { 2588 temperature = <90000>; 2589 hysteresis = <2000>; 2590 type = "hot"; 2591 }; 2592 cpuss0_crit: cluster0-crit { 2593 temperature = <110000>; 2594 hysteresis = <0>; 2595 type = "critical"; 2596 }; 2597 }; 2598 }; 2599 2600 cpuss1-thermal { 2601 polling-delay-passive = <0>; 2602 polling-delay = <0>; 2603 2604 thermal-sensors = <&tsens0 6>; 2605 2606 trips { 2607 cpuss1_alert0: trip-point0 { 2608 temperature = <90000>; 2609 hysteresis = <2000>; 2610 type = "hot"; 2611 }; 2612 cpuss1_crit: cluster0-crit { 2613 temperature = <110000>; 2614 hysteresis = <0>; 2615 type = "critical"; 2616 }; 2617 }; 2618 }; 2619 2620 gpuss0-thermal { 2621 polling-delay-passive = <100>; 2622 polling-delay = <0>; 2623 2624 thermal-sensors = <&tsens1 1>; 2625 2626 trips { 2627 gpuss0_alert0: trip-point0 { 2628 temperature = <95000>; 2629 hysteresis = <2000>; 2630 type = "passive"; 2631 }; 2632 2633 gpuss0_crit: gpuss0-crit { 2634 temperature = <110000>; 2635 hysteresis = <0>; 2636 type = "critical"; 2637 }; 2638 }; 2639 2640 cooling-maps { 2641 map0 { 2642 trip = <&gpuss0_alert0>; 2643 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2644 }; 2645 }; 2646 }; 2647 2648 gpuss1-thermal { 2649 polling-delay-passive = <100>; 2650 polling-delay = <0>; 2651 2652 thermal-sensors = <&tsens1 2>; 2653 2654 trips { 2655 gpuss1_alert0: trip-point0 { 2656 temperature = <95000>; 2657 hysteresis = <2000>; 2658 type = "passive"; 2659 }; 2660 2661 gpuss1_crit: gpuss1-crit { 2662 temperature = <110000>; 2663 hysteresis = <0>; 2664 type = "critical"; 2665 }; 2666 }; 2667 2668 cooling-maps { 2669 map0 { 2670 trip = <&gpuss1_alert0>; 2671 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2672 }; 2673 }; 2674 }; 2675 2676 nspss0-thermal { 2677 polling-delay-passive = <0>; 2678 polling-delay = <0>; 2679 2680 thermal-sensors = <&tsens1 3>; 2681 2682 trips { 2683 nspss0_alert0: trip-point0 { 2684 temperature = <90000>; 2685 hysteresis = <2000>; 2686 type = "hot"; 2687 }; 2688 2689 nspss0_crit: nspss0-crit { 2690 temperature = <110000>; 2691 hysteresis = <0>; 2692 type = "critical"; 2693 }; 2694 }; 2695 }; 2696 2697 nspss1-thermal { 2698 polling-delay-passive = <0>; 2699 polling-delay = <0>; 2700 2701 thermal-sensors = <&tsens1 4>; 2702 2703 trips { 2704 nspss1_alert0: trip-point0 { 2705 temperature = <90000>; 2706 hysteresis = <2000>; 2707 type = "hot"; 2708 }; 2709 2710 nspss1_crit: nspss1-crit { 2711 temperature = <110000>; 2712 hysteresis = <0>; 2713 type = "critical"; 2714 }; 2715 }; 2716 }; 2717 2718 video-thermal { 2719 polling-delay-passive = <0>; 2720 polling-delay = <0>; 2721 2722 thermal-sensors = <&tsens1 5>; 2723 2724 trips { 2725 video_alert0: trip-point0 { 2726 temperature = <90000>; 2727 hysteresis = <2000>; 2728 type = "hot"; 2729 }; 2730 2731 video_crit: video-crit { 2732 temperature = <110000>; 2733 hysteresis = <0>; 2734 type = "critical"; 2735 }; 2736 }; 2737 }; 2738 2739 ddr-thermal { 2740 polling-delay-passive = <0>; 2741 polling-delay = <0>; 2742 2743 thermal-sensors = <&tsens1 6>; 2744 2745 trips { 2746 ddr_alert0: trip-point0 { 2747 temperature = <90000>; 2748 hysteresis = <2000>; 2749 type = "hot"; 2750 }; 2751 2752 ddr_crit: ddr-crit { 2753 temperature = <110000>; 2754 hysteresis = <0>; 2755 type = "critical"; 2756 }; 2757 }; 2758 }; 2759 2760 mdmss0-thermal { 2761 polling-delay-passive = <0>; 2762 polling-delay = <0>; 2763 2764 thermal-sensors = <&tsens1 7>; 2765 2766 trips { 2767 mdmss0_alert0: trip-point0 { 2768 temperature = <90000>; 2769 hysteresis = <2000>; 2770 type = "hot"; 2771 }; 2772 2773 mdmss0_crit: mdmss0-crit { 2774 temperature = <110000>; 2775 hysteresis = <0>; 2776 type = "critical"; 2777 }; 2778 }; 2779 }; 2780 2781 mdmss1-thermal { 2782 polling-delay-passive = <0>; 2783 polling-delay = <0>; 2784 2785 thermal-sensors = <&tsens1 8>; 2786 2787 trips { 2788 mdmss1_alert0: trip-point0 { 2789 temperature = <90000>; 2790 hysteresis = <2000>; 2791 type = "hot"; 2792 }; 2793 2794 mdmss1_crit: mdmss1-crit { 2795 temperature = <110000>; 2796 hysteresis = <0>; 2797 type = "critical"; 2798 }; 2799 }; 2800 }; 2801 2802 mdmss2-thermal { 2803 polling-delay-passive = <0>; 2804 polling-delay = <0>; 2805 2806 thermal-sensors = <&tsens1 9>; 2807 2808 trips { 2809 mdmss2_alert0: trip-point0 { 2810 temperature = <90000>; 2811 hysteresis = <2000>; 2812 type = "hot"; 2813 }; 2814 2815 mdmss2_crit: mdmss2-crit { 2816 temperature = <110000>; 2817 hysteresis = <0>; 2818 type = "critical"; 2819 }; 2820 }; 2821 }; 2822 2823 mdmss3-thermal { 2824 polling-delay-passive = <0>; 2825 polling-delay = <0>; 2826 2827 thermal-sensors = <&tsens1 10>; 2828 2829 trips { 2830 mdmss3_alert0: trip-point0 { 2831 temperature = <90000>; 2832 hysteresis = <2000>; 2833 type = "hot"; 2834 }; 2835 2836 mdmss3_crit: mdmss3-crit { 2837 temperature = <110000>; 2838 hysteresis = <0>; 2839 type = "critical"; 2840 }; 2841 }; 2842 }; 2843 2844 camera0-thermal { 2845 polling-delay-passive = <0>; 2846 polling-delay = <0>; 2847 2848 thermal-sensors = <&tsens1 11>; 2849 2850 trips { 2851 camera0_alert0: trip-point0 { 2852 temperature = <90000>; 2853 hysteresis = <2000>; 2854 type = "hot"; 2855 }; 2856 2857 camera0_crit: camera0-crit { 2858 temperature = <110000>; 2859 hysteresis = <0>; 2860 type = "critical"; 2861 }; 2862 }; 2863 }; 2864 }; 2865 2866 timer { 2867 compatible = "arm,armv8-timer"; 2868 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2869 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2870 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2871 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2872 }; 2873}; 2874