1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 pmu { 758 compatible = "arm,armv8-pmuv3"; 759 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 760 }; 761 762 psci { 763 compatible = "arm,psci-1.0"; 764 method = "smc"; 765 }; 766 767 qspi_opp_table: opp-table-qspi { 768 compatible = "operating-points-v2"; 769 770 opp-75000000 { 771 opp-hz = /bits/ 64 <75000000>; 772 required-opps = <&rpmhpd_opp_low_svs>; 773 }; 774 775 opp-150000000 { 776 opp-hz = /bits/ 64 <150000000>; 777 required-opps = <&rpmhpd_opp_svs>; 778 }; 779 780 opp-200000000 { 781 opp-hz = /bits/ 64 <200000000>; 782 required-opps = <&rpmhpd_opp_svs_l1>; 783 }; 784 785 opp-300000000 { 786 opp-hz = /bits/ 64 <300000000>; 787 required-opps = <&rpmhpd_opp_nom>; 788 }; 789 }; 790 791 qup_opp_table: opp-table-qup { 792 compatible = "operating-points-v2"; 793 794 opp-75000000 { 795 opp-hz = /bits/ 64 <75000000>; 796 required-opps = <&rpmhpd_opp_low_svs>; 797 }; 798 799 opp-100000000 { 800 opp-hz = /bits/ 64 <100000000>; 801 required-opps = <&rpmhpd_opp_svs>; 802 }; 803 804 opp-128000000 { 805 opp-hz = /bits/ 64 <128000000>; 806 required-opps = <&rpmhpd_opp_nom>; 807 }; 808 }; 809 810 soc: soc@0 { 811 #address-cells = <2>; 812 #size-cells = <2>; 813 ranges = <0 0 0 0 0x10 0>; 814 dma-ranges = <0 0 0 0 0x10 0>; 815 compatible = "simple-bus"; 816 817 gcc: clock-controller@100000 { 818 compatible = "qcom,gcc-sc7280"; 819 reg = <0 0x00100000 0 0x1f0000>; 820 clocks = <&rpmhcc RPMH_CXO_CLK>, 821 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 822 <0>, <&pcie1_lane>, 823 <0>, <0>, <0>, <0>; 824 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 825 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 826 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 827 "ufs_phy_tx_symbol_0_clk", 828 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 }; 833 834 ipcc: mailbox@408000 { 835 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 836 reg = <0 0x00408000 0 0x1000>; 837 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-controller; 839 #interrupt-cells = <3>; 840 #mbox-cells = <2>; 841 }; 842 843 qfprom: efuse@784000 { 844 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 845 reg = <0 0x00784000 0 0xa20>, 846 <0 0x00780000 0 0xa20>, 847 <0 0x00782000 0 0x120>, 848 <0 0x00786000 0 0x1fff>; 849 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 850 clock-names = "core"; 851 power-domains = <&rpmhpd SC7280_MX>; 852 #address-cells = <1>; 853 #size-cells = <1>; 854 855 gpu_speed_bin: gpu_speed_bin@1e9 { 856 reg = <0x1e9 0x2>; 857 bits = <5 8>; 858 }; 859 }; 860 861 sdhc_1: mmc@7c4000 { 862 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 863 pinctrl-names = "default", "sleep"; 864 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 865 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 866 status = "disabled"; 867 868 reg = <0 0x007c4000 0 0x1000>, 869 <0 0x007c5000 0 0x1000>; 870 reg-names = "hc", "cqhci"; 871 872 iommus = <&apps_smmu 0xc0 0x0>; 873 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "hc_irq", "pwr_irq"; 876 877 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 878 <&gcc GCC_SDCC1_APPS_CLK>, 879 <&rpmhcc RPMH_CXO_CLK>; 880 clock-names = "iface", "core", "xo"; 881 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 882 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 883 interconnect-names = "sdhc-ddr","cpu-sdhc"; 884 power-domains = <&rpmhpd SC7280_CX>; 885 operating-points-v2 = <&sdhc1_opp_table>; 886 887 bus-width = <8>; 888 supports-cqe; 889 890 qcom,dll-config = <0x0007642c>; 891 qcom,ddr-config = <0x80040868>; 892 893 mmc-ddr-1_8v; 894 mmc-hs200-1_8v; 895 mmc-hs400-1_8v; 896 mmc-hs400-enhanced-strobe; 897 898 resets = <&gcc GCC_SDCC1_BCR>; 899 900 sdhc1_opp_table: opp-table { 901 compatible = "operating-points-v2"; 902 903 opp-100000000 { 904 opp-hz = /bits/ 64 <100000000>; 905 required-opps = <&rpmhpd_opp_low_svs>; 906 opp-peak-kBps = <1800000 400000>; 907 opp-avg-kBps = <100000 0>; 908 }; 909 910 opp-384000000 { 911 opp-hz = /bits/ 64 <384000000>; 912 required-opps = <&rpmhpd_opp_nom>; 913 opp-peak-kBps = <5400000 1600000>; 914 opp-avg-kBps = <390000 0>; 915 }; 916 }; 917 918 }; 919 920 gpi_dma0: dma-controller@900000 { 921 #dma-cells = <3>; 922 compatible = "qcom,sc7280-gpi-dma"; 923 reg = <0 0x00900000 0 0x60000>; 924 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 936 dma-channels = <12>; 937 dma-channel-mask = <0x7f>; 938 iommus = <&apps_smmu 0x0136 0x0>; 939 status = "disabled"; 940 }; 941 942 qupv3_id_0: geniqup@9c0000 { 943 compatible = "qcom,geni-se-qup"; 944 reg = <0 0x009c0000 0 0x2000>; 945 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 946 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 947 clock-names = "m-ahb", "s-ahb"; 948 #address-cells = <2>; 949 #size-cells = <2>; 950 ranges; 951 iommus = <&apps_smmu 0x123 0x0>; 952 status = "disabled"; 953 954 i2c0: i2c@980000 { 955 compatible = "qcom,geni-i2c"; 956 reg = <0 0x00980000 0 0x4000>; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 958 clock-names = "se"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_i2c0_data_clk>; 961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 966 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 967 interconnect-names = "qup-core", "qup-config", 968 "qup-memory"; 969 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 970 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 971 dma-names = "tx", "rx"; 972 status = "disabled"; 973 }; 974 975 spi0: spi@980000 { 976 compatible = "qcom,geni-spi"; 977 reg = <0 0x00980000 0 0x4000>; 978 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 979 clock-names = "se"; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 982 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 power-domains = <&rpmhpd SC7280_CX>; 986 operating-points-v2 = <&qup_opp_table>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 989 interconnect-names = "qup-core", "qup-config"; 990 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 991 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 992 dma-names = "tx", "rx"; 993 status = "disabled"; 994 }; 995 996 uart0: serial@980000 { 997 compatible = "qcom,geni-uart"; 998 reg = <0 0x00980000 0 0x4000>; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1000 clock-names = "se"; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1003 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1004 power-domains = <&rpmhpd SC7280_CX>; 1005 operating-points-v2 = <&qup_opp_table>; 1006 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1007 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1008 interconnect-names = "qup-core", "qup-config"; 1009 status = "disabled"; 1010 }; 1011 1012 i2c1: i2c@984000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x00984000 0 0x4000>; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1016 clock-names = "se"; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_i2c1_data_clk>; 1019 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1023 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1024 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1025 interconnect-names = "qup-core", "qup-config", 1026 "qup-memory"; 1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 status = "disabled"; 1031 }; 1032 1033 spi1: spi@984000 { 1034 compatible = "qcom,geni-spi"; 1035 reg = <0 0x00984000 0 0x4000>; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1037 clock-names = "se"; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1040 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 power-domains = <&rpmhpd SC7280_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1049 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 status = "disabled"; 1052 }; 1053 1054 uart1: serial@984000 { 1055 compatible = "qcom,geni-uart"; 1056 reg = <0 0x00984000 0 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1058 clock-names = "se"; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1061 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1062 power-domains = <&rpmhpd SC7280_CX>; 1063 operating-points-v2 = <&qup_opp_table>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1066 interconnect-names = "qup-core", "qup-config"; 1067 status = "disabled"; 1068 }; 1069 1070 i2c2: i2c@988000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0 0x00988000 0 0x4000>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1074 clock-names = "se"; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_i2c2_data_clk>; 1077 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1082 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1083 interconnect-names = "qup-core", "qup-config", 1084 "qup-memory"; 1085 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1086 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1087 dma-names = "tx", "rx"; 1088 status = "disabled"; 1089 }; 1090 1091 spi2: spi@988000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0 0x00988000 0 0x4000>; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1095 clock-names = "se"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1098 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 power-domains = <&rpmhpd SC7280_CX>; 1102 operating-points-v2 = <&qup_opp_table>; 1103 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1104 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1105 interconnect-names = "qup-core", "qup-config"; 1106 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1107 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1108 dma-names = "tx", "rx"; 1109 status = "disabled"; 1110 }; 1111 1112 uart2: serial@988000 { 1113 compatible = "qcom,geni-uart"; 1114 reg = <0 0x00988000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1116 clock-names = "se"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1119 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1120 power-domains = <&rpmhpd SC7280_CX>; 1121 operating-points-v2 = <&qup_opp_table>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1124 interconnect-names = "qup-core", "qup-config"; 1125 status = "disabled"; 1126 }; 1127 1128 i2c3: i2c@98c000 { 1129 compatible = "qcom,geni-i2c"; 1130 reg = <0 0x0098c000 0 0x4000>; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1132 clock-names = "se"; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_i2c3_data_clk>; 1135 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1139 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1140 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1141 interconnect-names = "qup-core", "qup-config", 1142 "qup-memory"; 1143 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1144 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1145 dma-names = "tx", "rx"; 1146 status = "disabled"; 1147 }; 1148 1149 spi3: spi@98c000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0 0x0098c000 0 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1153 clock-names = "se"; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1156 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 power-domains = <&rpmhpd SC7280_CX>; 1160 operating-points-v2 = <&qup_opp_table>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1162 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1165 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1166 dma-names = "tx", "rx"; 1167 status = "disabled"; 1168 }; 1169 1170 uart3: serial@98c000 { 1171 compatible = "qcom,geni-uart"; 1172 reg = <0 0x0098c000 0 0x4000>; 1173 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1174 clock-names = "se"; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1177 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1178 power-domains = <&rpmhpd SC7280_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1181 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1182 interconnect-names = "qup-core", "qup-config"; 1183 status = "disabled"; 1184 }; 1185 1186 i2c4: i2c@990000 { 1187 compatible = "qcom,geni-i2c"; 1188 reg = <0 0x00990000 0 0x4000>; 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1190 clock-names = "se"; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_i2c4_data_clk>; 1193 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1197 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1198 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1199 interconnect-names = "qup-core", "qup-config", 1200 "qup-memory"; 1201 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1202 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1203 dma-names = "tx", "rx"; 1204 status = "disabled"; 1205 }; 1206 1207 spi4: spi@990000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x00990000 0 0x4000>; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1211 clock-names = "se"; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1214 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 power-domains = <&rpmhpd SC7280_CX>; 1218 operating-points-v2 = <&qup_opp_table>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1223 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1224 dma-names = "tx", "rx"; 1225 status = "disabled"; 1226 }; 1227 1228 uart4: serial@990000 { 1229 compatible = "qcom,geni-uart"; 1230 reg = <0 0x00990000 0 0x4000>; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1232 clock-names = "se"; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1235 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1236 power-domains = <&rpmhpd SC7280_CX>; 1237 operating-points-v2 = <&qup_opp_table>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1239 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1240 interconnect-names = "qup-core", "qup-config"; 1241 status = "disabled"; 1242 }; 1243 1244 i2c5: i2c@994000 { 1245 compatible = "qcom,geni-i2c"; 1246 reg = <0 0x00994000 0 0x4000>; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1248 clock-names = "se"; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_i2c5_data_clk>; 1251 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1255 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1256 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1257 interconnect-names = "qup-core", "qup-config", 1258 "qup-memory"; 1259 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1260 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1261 dma-names = "tx", "rx"; 1262 status = "disabled"; 1263 }; 1264 1265 spi5: spi@994000 { 1266 compatible = "qcom,geni-spi"; 1267 reg = <0 0x00994000 0 0x4000>; 1268 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1269 clock-names = "se"; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1272 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 power-domains = <&rpmhpd SC7280_CX>; 1276 operating-points-v2 = <&qup_opp_table>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1279 interconnect-names = "qup-core", "qup-config"; 1280 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1281 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1282 dma-names = "tx", "rx"; 1283 status = "disabled"; 1284 }; 1285 1286 uart5: serial@994000 { 1287 compatible = "qcom,geni-uart"; 1288 reg = <0 0x00994000 0 0x4000>; 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1290 clock-names = "se"; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1293 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1294 power-domains = <&rpmhpd SC7280_CX>; 1295 operating-points-v2 = <&qup_opp_table>; 1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1297 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1298 interconnect-names = "qup-core", "qup-config"; 1299 status = "disabled"; 1300 }; 1301 1302 i2c6: i2c@998000 { 1303 compatible = "qcom,geni-i2c"; 1304 reg = <0 0x00998000 0 0x4000>; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1306 clock-names = "se"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_i2c6_data_clk>; 1309 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1313 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1314 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1315 interconnect-names = "qup-core", "qup-config", 1316 "qup-memory"; 1317 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1318 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1319 dma-names = "tx", "rx"; 1320 status = "disabled"; 1321 }; 1322 1323 spi6: spi@998000 { 1324 compatible = "qcom,geni-spi"; 1325 reg = <0 0x00998000 0 0x4000>; 1326 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1327 clock-names = "se"; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1330 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 power-domains = <&rpmhpd SC7280_CX>; 1334 operating-points-v2 = <&qup_opp_table>; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1336 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1337 interconnect-names = "qup-core", "qup-config"; 1338 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1339 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1340 dma-names = "tx", "rx"; 1341 status = "disabled"; 1342 }; 1343 1344 uart6: serial@998000 { 1345 compatible = "qcom,geni-uart"; 1346 reg = <0 0x00998000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1348 clock-names = "se"; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1351 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1352 power-domains = <&rpmhpd SC7280_CX>; 1353 operating-points-v2 = <&qup_opp_table>; 1354 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1355 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1356 interconnect-names = "qup-core", "qup-config"; 1357 status = "disabled"; 1358 }; 1359 1360 i2c7: i2c@99c000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x0099c000 0 0x4000>; 1363 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1364 clock-names = "se"; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c7_data_clk>; 1367 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1372 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", 1374 "qup-memory"; 1375 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1376 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1377 dma-names = "tx", "rx"; 1378 status = "disabled"; 1379 }; 1380 1381 spi7: spi@99c000 { 1382 compatible = "qcom,geni-spi"; 1383 reg = <0 0x0099c000 0 0x4000>; 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1385 clock-names = "se"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1388 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 power-domains = <&rpmhpd SC7280_CX>; 1392 operating-points-v2 = <&qup_opp_table>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1394 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1395 interconnect-names = "qup-core", "qup-config"; 1396 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1397 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1398 dma-names = "tx", "rx"; 1399 status = "disabled"; 1400 }; 1401 1402 uart7: serial@99c000 { 1403 compatible = "qcom,geni-uart"; 1404 reg = <0 0x0099c000 0 0x4000>; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1406 clock-names = "se"; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1409 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd SC7280_CX>; 1411 operating-points-v2 = <&qup_opp_table>; 1412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1413 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1414 interconnect-names = "qup-core", "qup-config"; 1415 status = "disabled"; 1416 }; 1417 }; 1418 1419 gpi_dma1: dma-controller@a00000 { 1420 #dma-cells = <3>; 1421 compatible = "qcom,sc7280-gpi-dma"; 1422 reg = <0 0x00a00000 0 0x60000>; 1423 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1435 dma-channels = <12>; 1436 dma-channel-mask = <0x1e>; 1437 iommus = <&apps_smmu 0x56 0x0>; 1438 status = "disabled"; 1439 }; 1440 1441 qupv3_id_1: geniqup@ac0000 { 1442 compatible = "qcom,geni-se-qup"; 1443 reg = <0 0x00ac0000 0 0x2000>; 1444 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1445 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1446 clock-names = "m-ahb", "s-ahb"; 1447 #address-cells = <2>; 1448 #size-cells = <2>; 1449 ranges; 1450 iommus = <&apps_smmu 0x43 0x0>; 1451 status = "disabled"; 1452 1453 i2c8: i2c@a80000 { 1454 compatible = "qcom,geni-i2c"; 1455 reg = <0 0x00a80000 0 0x4000>; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1457 clock-names = "se"; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_i2c8_data_clk>; 1460 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1465 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1466 interconnect-names = "qup-core", "qup-config", 1467 "qup-memory"; 1468 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1469 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1470 dma-names = "tx", "rx"; 1471 status = "disabled"; 1472 }; 1473 1474 spi8: spi@a80000 { 1475 compatible = "qcom,geni-spi"; 1476 reg = <0 0x00a80000 0 0x4000>; 1477 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1478 clock-names = "se"; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1481 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 power-domains = <&rpmhpd SC7280_CX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1488 interconnect-names = "qup-core", "qup-config"; 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1490 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1491 dma-names = "tx", "rx"; 1492 status = "disabled"; 1493 }; 1494 1495 uart8: serial@a80000 { 1496 compatible = "qcom,geni-uart"; 1497 reg = <0 0x00a80000 0 0x4000>; 1498 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1499 clock-names = "se"; 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1502 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1503 power-domains = <&rpmhpd SC7280_CX>; 1504 operating-points-v2 = <&qup_opp_table>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 status = "disabled"; 1509 }; 1510 1511 i2c9: i2c@a84000 { 1512 compatible = "qcom,geni-i2c"; 1513 reg = <0 0x00a84000 0 0x4000>; 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1515 clock-names = "se"; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&qup_i2c9_data_clk>; 1518 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1523 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1524 interconnect-names = "qup-core", "qup-config", 1525 "qup-memory"; 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi9: spi@a84000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0 0x00a84000 0 0x4000>; 1535 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1536 clock-names = "se"; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1539 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 power-domains = <&rpmhpd SC7280_CX>; 1543 operating-points-v2 = <&qup_opp_table>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1546 interconnect-names = "qup-core", "qup-config"; 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 status = "disabled"; 1551 }; 1552 1553 uart9: serial@a84000 { 1554 compatible = "qcom,geni-uart"; 1555 reg = <0 0x00a84000 0 0x4000>; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1557 clock-names = "se"; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1560 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1561 power-domains = <&rpmhpd SC7280_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1565 interconnect-names = "qup-core", "qup-config"; 1566 status = "disabled"; 1567 }; 1568 1569 i2c10: i2c@a88000 { 1570 compatible = "qcom,geni-i2c"; 1571 reg = <0 0x00a88000 0 0x4000>; 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1573 clock-names = "se"; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_i2c10_data_clk>; 1576 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1580 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1581 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1582 interconnect-names = "qup-core", "qup-config", 1583 "qup-memory"; 1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1585 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1586 dma-names = "tx", "rx"; 1587 status = "disabled"; 1588 }; 1589 1590 spi10: spi@a88000 { 1591 compatible = "qcom,geni-spi"; 1592 reg = <0 0x00a88000 0 0x4000>; 1593 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1594 clock-names = "se"; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1597 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 power-domains = <&rpmhpd SC7280_CX>; 1601 operating-points-v2 = <&qup_opp_table>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1604 interconnect-names = "qup-core", "qup-config"; 1605 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 status = "disabled"; 1609 }; 1610 1611 uart10: serial@a88000 { 1612 compatible = "qcom,geni-uart"; 1613 reg = <0 0x00a88000 0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1615 clock-names = "se"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1618 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1619 power-domains = <&rpmhpd SC7280_CX>; 1620 operating-points-v2 = <&qup_opp_table>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1623 interconnect-names = "qup-core", "qup-config"; 1624 status = "disabled"; 1625 }; 1626 1627 i2c11: i2c@a8c000 { 1628 compatible = "qcom,geni-i2c"; 1629 reg = <0 0x00a8c000 0 0x4000>; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1631 clock-names = "se"; 1632 pinctrl-names = "default"; 1633 pinctrl-0 = <&qup_i2c11_data_clk>; 1634 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1639 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1640 interconnect-names = "qup-core", "qup-config", 1641 "qup-memory"; 1642 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1643 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1644 dma-names = "tx", "rx"; 1645 status = "disabled"; 1646 }; 1647 1648 spi11: spi@a8c000 { 1649 compatible = "qcom,geni-spi"; 1650 reg = <0 0x00a8c000 0 0x4000>; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1652 clock-names = "se"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1655 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 power-domains = <&rpmhpd SC7280_CX>; 1659 operating-points-v2 = <&qup_opp_table>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1662 interconnect-names = "qup-core", "qup-config"; 1663 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1664 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1665 dma-names = "tx", "rx"; 1666 status = "disabled"; 1667 }; 1668 1669 uart11: serial@a8c000 { 1670 compatible = "qcom,geni-uart"; 1671 reg = <0 0x00a8c000 0 0x4000>; 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1673 clock-names = "se"; 1674 pinctrl-names = "default"; 1675 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1676 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1677 power-domains = <&rpmhpd SC7280_CX>; 1678 operating-points-v2 = <&qup_opp_table>; 1679 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1680 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1681 interconnect-names = "qup-core", "qup-config"; 1682 status = "disabled"; 1683 }; 1684 1685 i2c12: i2c@a90000 { 1686 compatible = "qcom,geni-i2c"; 1687 reg = <0 0x00a90000 0 0x4000>; 1688 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1689 clock-names = "se"; 1690 pinctrl-names = "default"; 1691 pinctrl-0 = <&qup_i2c12_data_clk>; 1692 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1696 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1697 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1698 interconnect-names = "qup-core", "qup-config", 1699 "qup-memory"; 1700 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1701 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1702 dma-names = "tx", "rx"; 1703 status = "disabled"; 1704 }; 1705 1706 spi12: spi@a90000 { 1707 compatible = "qcom,geni-spi"; 1708 reg = <0 0x00a90000 0 0x4000>; 1709 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1710 clock-names = "se"; 1711 pinctrl-names = "default"; 1712 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1713 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 power-domains = <&rpmhpd SC7280_CX>; 1717 operating-points-v2 = <&qup_opp_table>; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1720 interconnect-names = "qup-core", "qup-config"; 1721 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1722 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1723 dma-names = "tx", "rx"; 1724 status = "disabled"; 1725 }; 1726 1727 uart12: serial@a90000 { 1728 compatible = "qcom,geni-uart"; 1729 reg = <0 0x00a90000 0 0x4000>; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1731 clock-names = "se"; 1732 pinctrl-names = "default"; 1733 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1734 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1735 power-domains = <&rpmhpd SC7280_CX>; 1736 operating-points-v2 = <&qup_opp_table>; 1737 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1738 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1739 interconnect-names = "qup-core", "qup-config"; 1740 status = "disabled"; 1741 }; 1742 1743 i2c13: i2c@a94000 { 1744 compatible = "qcom,geni-i2c"; 1745 reg = <0 0x00a94000 0 0x4000>; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1747 clock-names = "se"; 1748 pinctrl-names = "default"; 1749 pinctrl-0 = <&qup_i2c13_data_clk>; 1750 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1755 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1756 interconnect-names = "qup-core", "qup-config", 1757 "qup-memory"; 1758 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1759 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1760 dma-names = "tx", "rx"; 1761 status = "disabled"; 1762 }; 1763 1764 spi13: spi@a94000 { 1765 compatible = "qcom,geni-spi"; 1766 reg = <0 0x00a94000 0 0x4000>; 1767 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1768 clock-names = "se"; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1771 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 power-domains = <&rpmhpd SC7280_CX>; 1775 operating-points-v2 = <&qup_opp_table>; 1776 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1777 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1778 interconnect-names = "qup-core", "qup-config"; 1779 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1780 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1781 dma-names = "tx", "rx"; 1782 status = "disabled"; 1783 }; 1784 1785 uart13: serial@a94000 { 1786 compatible = "qcom,geni-uart"; 1787 reg = <0 0x00a94000 0 0x4000>; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1789 clock-names = "se"; 1790 pinctrl-names = "default"; 1791 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1792 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1793 power-domains = <&rpmhpd SC7280_CX>; 1794 operating-points-v2 = <&qup_opp_table>; 1795 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1796 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1797 interconnect-names = "qup-core", "qup-config"; 1798 status = "disabled"; 1799 }; 1800 1801 i2c14: i2c@a98000 { 1802 compatible = "qcom,geni-i2c"; 1803 reg = <0 0x00a98000 0 0x4000>; 1804 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1805 clock-names = "se"; 1806 pinctrl-names = "default"; 1807 pinctrl-0 = <&qup_i2c14_data_clk>; 1808 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1812 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1813 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1814 interconnect-names = "qup-core", "qup-config", 1815 "qup-memory"; 1816 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1817 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1818 dma-names = "tx", "rx"; 1819 status = "disabled"; 1820 }; 1821 1822 spi14: spi@a98000 { 1823 compatible = "qcom,geni-spi"; 1824 reg = <0 0x00a98000 0 0x4000>; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1826 clock-names = "se"; 1827 pinctrl-names = "default"; 1828 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1829 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 power-domains = <&rpmhpd SC7280_CX>; 1833 operating-points-v2 = <&qup_opp_table>; 1834 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1835 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1836 interconnect-names = "qup-core", "qup-config"; 1837 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1838 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1839 dma-names = "tx", "rx"; 1840 status = "disabled"; 1841 }; 1842 1843 uart14: serial@a98000 { 1844 compatible = "qcom,geni-uart"; 1845 reg = <0 0x00a98000 0 0x4000>; 1846 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1847 clock-names = "se"; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1850 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1851 power-domains = <&rpmhpd SC7280_CX>; 1852 operating-points-v2 = <&qup_opp_table>; 1853 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1854 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1855 interconnect-names = "qup-core", "qup-config"; 1856 status = "disabled"; 1857 }; 1858 1859 i2c15: i2c@a9c000 { 1860 compatible = "qcom,geni-i2c"; 1861 reg = <0 0x00a9c000 0 0x4000>; 1862 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1863 clock-names = "se"; 1864 pinctrl-names = "default"; 1865 pinctrl-0 = <&qup_i2c15_data_clk>; 1866 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1870 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1871 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1872 interconnect-names = "qup-core", "qup-config", 1873 "qup-memory"; 1874 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1875 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1876 dma-names = "tx", "rx"; 1877 status = "disabled"; 1878 }; 1879 1880 spi15: spi@a9c000 { 1881 compatible = "qcom,geni-spi"; 1882 reg = <0 0x00a9c000 0 0x4000>; 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1884 clock-names = "se"; 1885 pinctrl-names = "default"; 1886 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1887 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 power-domains = <&rpmhpd SC7280_CX>; 1891 operating-points-v2 = <&qup_opp_table>; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1893 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1894 interconnect-names = "qup-core", "qup-config"; 1895 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1896 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1897 dma-names = "tx", "rx"; 1898 status = "disabled"; 1899 }; 1900 1901 uart15: serial@a9c000 { 1902 compatible = "qcom,geni-uart"; 1903 reg = <0 0x00a9c000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1908 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1909 power-domains = <&rpmhpd SC7280_CX>; 1910 operating-points-v2 = <&qup_opp_table>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1913 interconnect-names = "qup-core", "qup-config"; 1914 status = "disabled"; 1915 }; 1916 }; 1917 1918 cnoc2: interconnect@1500000 { 1919 reg = <0 0x01500000 0 0x1000>; 1920 compatible = "qcom,sc7280-cnoc2"; 1921 #interconnect-cells = <2>; 1922 qcom,bcm-voters = <&apps_bcm_voter>; 1923 }; 1924 1925 cnoc3: interconnect@1502000 { 1926 reg = <0 0x01502000 0 0x1000>; 1927 compatible = "qcom,sc7280-cnoc3"; 1928 #interconnect-cells = <2>; 1929 qcom,bcm-voters = <&apps_bcm_voter>; 1930 }; 1931 1932 mc_virt: interconnect@1580000 { 1933 reg = <0 0x01580000 0 0x4>; 1934 compatible = "qcom,sc7280-mc-virt"; 1935 #interconnect-cells = <2>; 1936 qcom,bcm-voters = <&apps_bcm_voter>; 1937 }; 1938 1939 system_noc: interconnect@1680000 { 1940 reg = <0 0x01680000 0 0x15480>; 1941 compatible = "qcom,sc7280-system-noc"; 1942 #interconnect-cells = <2>; 1943 qcom,bcm-voters = <&apps_bcm_voter>; 1944 }; 1945 1946 aggre1_noc: interconnect@16e0000 { 1947 compatible = "qcom,sc7280-aggre1-noc"; 1948 reg = <0 0x016e0000 0 0x1c080>; 1949 #interconnect-cells = <2>; 1950 qcom,bcm-voters = <&apps_bcm_voter>; 1951 }; 1952 1953 aggre2_noc: interconnect@1700000 { 1954 reg = <0 0x01700000 0 0x2b080>; 1955 compatible = "qcom,sc7280-aggre2-noc"; 1956 #interconnect-cells = <2>; 1957 qcom,bcm-voters = <&apps_bcm_voter>; 1958 }; 1959 1960 mmss_noc: interconnect@1740000 { 1961 reg = <0 0x01740000 0 0x1e080>; 1962 compatible = "qcom,sc7280-mmss-noc"; 1963 #interconnect-cells = <2>; 1964 qcom,bcm-voters = <&apps_bcm_voter>; 1965 }; 1966 1967 wifi: wifi@17a10040 { 1968 compatible = "qcom,wcn6750-wifi"; 1969 reg = <0 0x17a10040 0 0x0>; 1970 iommus = <&apps_smmu 0x1c00 0x1>; 1971 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1979 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1980 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1981 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1982 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1983 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1984 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1985 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1986 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1987 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1988 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1989 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1990 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1991 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1992 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1993 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1994 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1995 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1996 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1997 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1998 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2002 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2003 qcom,rproc = <&remoteproc_wpss>; 2004 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2005 status = "disabled"; 2006 }; 2007 2008 pcie1: pci@1c08000 { 2009 compatible = "qcom,pcie-sc7280"; 2010 reg = <0 0x01c08000 0 0x3000>, 2011 <0 0x40000000 0 0xf1d>, 2012 <0 0x40000f20 0 0xa8>, 2013 <0 0x40001000 0 0x1000>, 2014 <0 0x40100000 0 0x100000>; 2015 2016 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2017 device_type = "pci"; 2018 linux,pci-domain = <1>; 2019 bus-range = <0x00 0xff>; 2020 num-lanes = <2>; 2021 2022 #address-cells = <3>; 2023 #size-cells = <2>; 2024 2025 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2026 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2027 2028 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2029 interrupt-names = "msi"; 2030 #interrupt-cells = <1>; 2031 interrupt-map-mask = <0 0 0 0x7>; 2032 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2033 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2034 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2035 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2036 2037 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2038 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2039 <&pcie1_lane>, 2040 <&rpmhcc RPMH_CXO_CLK>, 2041 <&gcc GCC_PCIE_1_AUX_CLK>, 2042 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2043 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2044 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2045 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2046 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2047 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 2048 2049 clock-names = "pipe", 2050 "pipe_mux", 2051 "phy_pipe", 2052 "ref", 2053 "aux", 2054 "cfg", 2055 "bus_master", 2056 "bus_slave", 2057 "slave_q2a", 2058 "tbu", 2059 "ddrss_sf_tbu"; 2060 2061 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2062 assigned-clock-rates = <19200000>; 2063 2064 resets = <&gcc GCC_PCIE_1_BCR>; 2065 reset-names = "pci"; 2066 2067 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2068 2069 phys = <&pcie1_lane>; 2070 phy-names = "pciephy"; 2071 2072 pinctrl-names = "default"; 2073 pinctrl-0 = <&pcie1_clkreq_n>; 2074 2075 iommus = <&apps_smmu 0x1c80 0x1>; 2076 2077 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2078 <0x100 &apps_smmu 0x1c81 0x1>; 2079 2080 status = "disabled"; 2081 }; 2082 2083 pcie1_phy: phy@1c0e000 { 2084 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2085 reg = <0 0x01c0e000 0 0x1c0>; 2086 #address-cells = <2>; 2087 #size-cells = <2>; 2088 ranges; 2089 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2090 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2091 <&gcc GCC_PCIE_CLKREF_EN>, 2092 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2093 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2094 2095 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2096 reset-names = "phy"; 2097 2098 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2099 assigned-clock-rates = <100000000>; 2100 2101 status = "disabled"; 2102 2103 pcie1_lane: phy@1c0e200 { 2104 reg = <0 0x01c0e200 0 0x170>, 2105 <0 0x01c0e400 0 0x200>, 2106 <0 0x01c0ea00 0 0x1f0>, 2107 <0 0x01c0e600 0 0x170>, 2108 <0 0x01c0e800 0 0x200>, 2109 <0 0x01c0ee00 0 0xf4>; 2110 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2111 clock-names = "pipe0"; 2112 2113 #phy-cells = <0>; 2114 #clock-cells = <0>; 2115 clock-output-names = "pcie_1_pipe_clk"; 2116 }; 2117 }; 2118 2119 ipa: ipa@1e40000 { 2120 compatible = "qcom,sc7280-ipa"; 2121 2122 iommus = <&apps_smmu 0x480 0x0>, 2123 <&apps_smmu 0x482 0x0>; 2124 reg = <0 0x1e40000 0 0x8000>, 2125 <0 0x1e50000 0 0x4ad0>, 2126 <0 0x1e04000 0 0x23000>; 2127 reg-names = "ipa-reg", 2128 "ipa-shared", 2129 "gsi"; 2130 2131 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2132 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2133 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2134 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2135 interrupt-names = "ipa", 2136 "gsi", 2137 "ipa-clock-query", 2138 "ipa-setup-ready"; 2139 2140 clocks = <&rpmhcc RPMH_IPA_CLK>; 2141 clock-names = "core"; 2142 2143 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2144 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2145 interconnect-names = "memory", 2146 "config"; 2147 2148 qcom,qmp = <&aoss_qmp>; 2149 2150 qcom,smem-states = <&ipa_smp2p_out 0>, 2151 <&ipa_smp2p_out 1>; 2152 qcom,smem-state-names = "ipa-clock-enabled-valid", 2153 "ipa-clock-enabled"; 2154 2155 status = "disabled"; 2156 }; 2157 2158 tcsr_mutex: hwlock@1f40000 { 2159 compatible = "qcom,tcsr-mutex"; 2160 reg = <0 0x01f40000 0 0x20000>; 2161 #hwlock-cells = <1>; 2162 }; 2163 2164 tcsr_1: syscon@1f60000 { 2165 compatible = "qcom,sc7280-tcsr", "syscon"; 2166 reg = <0 0x01f60000 0 0x20000>; 2167 }; 2168 2169 tcsr_2: syscon@1fc0000 { 2170 compatible = "qcom,sc7280-tcsr", "syscon"; 2171 reg = <0 0x01fc0000 0 0x30000>; 2172 }; 2173 2174 lpasscc: lpasscc@3000000 { 2175 compatible = "qcom,sc7280-lpasscc"; 2176 reg = <0 0x03000000 0 0x40>, 2177 <0 0x03c04000 0 0x4>; 2178 reg-names = "qdsp6ss", "top_cc"; 2179 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2180 clock-names = "iface"; 2181 #clock-cells = <1>; 2182 }; 2183 2184 lpass_rx_macro: codec@3200000 { 2185 compatible = "qcom,sc7280-lpass-rx-macro"; 2186 reg = <0 0x03200000 0 0x1000>; 2187 2188 pinctrl-names = "default"; 2189 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2190 2191 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2192 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2193 <&lpass_va_macro>; 2194 clock-names = "mclk", "npl", "fsgen"; 2195 2196 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2197 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2198 power-domain-names = "macro", "dcodec"; 2199 2200 #clock-cells = <0>; 2201 #sound-dai-cells = <1>; 2202 2203 status = "disabled"; 2204 }; 2205 2206 swr0: soundwire@3210000 { 2207 compatible = "qcom,soundwire-v1.6.0"; 2208 reg = <0 0x03210000 0 0x2000>; 2209 2210 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2211 clocks = <&lpass_rx_macro>; 2212 clock-names = "iface"; 2213 2214 qcom,din-ports = <0>; 2215 qcom,dout-ports = <5>; 2216 2217 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2218 reset-names = "swr_audio_cgcr"; 2219 2220 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2221 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2222 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2223 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2224 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2225 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2226 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2227 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2228 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2229 2230 #sound-dai-cells = <1>; 2231 #address-cells = <2>; 2232 #size-cells = <0>; 2233 2234 status = "disabled"; 2235 }; 2236 2237 lpass_tx_macro: codec@3220000 { 2238 compatible = "qcom,sc7280-lpass-tx-macro"; 2239 reg = <0 0x03220000 0 0x1000>; 2240 2241 pinctrl-names = "default"; 2242 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2243 2244 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2245 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2246 <&lpass_va_macro>; 2247 clock-names = "mclk", "npl", "fsgen"; 2248 2249 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2250 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2251 power-domain-names = "macro", "dcodec"; 2252 2253 #clock-cells = <0>; 2254 #sound-dai-cells = <1>; 2255 2256 status = "disabled"; 2257 }; 2258 2259 swr1: soundwire@3230000 { 2260 compatible = "qcom,soundwire-v1.6.0"; 2261 reg = <0 0x03230000 0 0x2000>; 2262 2263 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2264 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&lpass_tx_macro>; 2266 clock-names = "iface"; 2267 2268 qcom,din-ports = <3>; 2269 qcom,dout-ports = <0>; 2270 2271 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2272 reset-names = "swr_audio_cgcr"; 2273 2274 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2275 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2276 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2277 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2278 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2279 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2280 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2281 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2282 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2283 qcom,port-offset = <1>; 2284 2285 #sound-dai-cells = <1>; 2286 #address-cells = <2>; 2287 #size-cells = <0>; 2288 2289 status = "disabled"; 2290 }; 2291 2292 lpass_audiocc: clock-controller@3300000 { 2293 compatible = "qcom,sc7280-lpassaudiocc"; 2294 reg = <0 0x03300000 0 0x30000>; 2295 clocks = <&rpmhcc RPMH_CXO_CLK>, 2296 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2297 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2298 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2299 #clock-cells = <1>; 2300 #power-domain-cells = <1>; 2301 #reset-cells = <1>; 2302 }; 2303 2304 lpass_va_macro: codec@3370000 { 2305 compatible = "qcom,sc7280-lpass-va-macro"; 2306 reg = <0 0x03370000 0 0x1000>; 2307 2308 pinctrl-names = "default"; 2309 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2310 2311 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2312 clock-names = "mclk"; 2313 2314 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2315 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2316 power-domain-names = "macro", "dcodec"; 2317 2318 #clock-cells = <0>; 2319 #sound-dai-cells = <1>; 2320 2321 status = "disabled"; 2322 }; 2323 2324 lpass_aon: clock-controller@3380000 { 2325 compatible = "qcom,sc7280-lpassaoncc"; 2326 reg = <0 0x03380000 0 0x30000>; 2327 clocks = <&rpmhcc RPMH_CXO_CLK>, 2328 <&rpmhcc RPMH_CXO_CLK_A>, 2329 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2330 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2331 #clock-cells = <1>; 2332 #power-domain-cells = <1>; 2333 }; 2334 2335 lpass_core: clock-controller@3900000 { 2336 compatible = "qcom,sc7280-lpasscorecc"; 2337 reg = <0 0x03900000 0 0x50000>; 2338 clocks = <&rpmhcc RPMH_CXO_CLK>; 2339 clock-names = "bi_tcxo"; 2340 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2341 #clock-cells = <1>; 2342 #power-domain-cells = <1>; 2343 }; 2344 2345 lpass_cpu: audio@3987000 { 2346 compatible = "qcom,sc7280-lpass-cpu"; 2347 2348 reg = <0 0x03987000 0 0x68000>, 2349 <0 0x03b00000 0 0x29000>, 2350 <0 0x03260000 0 0xc000>, 2351 <0 0x03280000 0 0x29000>, 2352 <0 0x03340000 0 0x29000>, 2353 <0 0x0336c000 0 0x3000>; 2354 reg-names = "lpass-hdmiif", 2355 "lpass-lpaif", 2356 "lpass-rxtx-cdc-dma-lpm", 2357 "lpass-rxtx-lpaif", 2358 "lpass-va-lpaif", 2359 "lpass-va-cdc-dma-lpm"; 2360 2361 iommus = <&apps_smmu 0x1820 0>, 2362 <&apps_smmu 0x1821 0>, 2363 <&apps_smmu 0x1832 0>; 2364 2365 power-domains = <&rpmhpd SC7280_LCX>; 2366 power-domain-names = "lcx"; 2367 required-opps = <&rpmhpd_opp_nom>; 2368 2369 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2370 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2371 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2372 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2373 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2374 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2375 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2376 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2377 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2378 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2379 clock-names = "aon_cc_audio_hm_h", 2380 "audio_cc_ext_mclk0", 2381 "core_cc_sysnoc_mport_core", 2382 "core_cc_ext_if0_ibit", 2383 "core_cc_ext_if1_ibit", 2384 "audio_cc_codec_mem", 2385 "audio_cc_codec_mem0", 2386 "audio_cc_codec_mem1", 2387 "audio_cc_codec_mem2", 2388 "aon_cc_va_mem0"; 2389 2390 #sound-dai-cells = <1>; 2391 #address-cells = <1>; 2392 #size-cells = <0>; 2393 2394 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2398 interrupt-names = "lpass-irq-lpaif", 2399 "lpass-irq-hdmi", 2400 "lpass-irq-vaif", 2401 "lpass-irq-rxtxif"; 2402 2403 status = "disabled"; 2404 }; 2405 2406 lpass_hm: clock-controller@3c00000 { 2407 compatible = "qcom,sc7280-lpasshm"; 2408 reg = <0 0x3c00000 0 0x28>; 2409 clocks = <&rpmhcc RPMH_CXO_CLK>; 2410 clock-names = "bi_tcxo"; 2411 #clock-cells = <1>; 2412 #power-domain-cells = <1>; 2413 }; 2414 2415 lpass_ag_noc: interconnect@3c40000 { 2416 reg = <0 0x03c40000 0 0xf080>; 2417 compatible = "qcom,sc7280-lpass-ag-noc"; 2418 #interconnect-cells = <2>; 2419 qcom,bcm-voters = <&apps_bcm_voter>; 2420 }; 2421 2422 lpass_tlmm: pinctrl@33c0000 { 2423 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2424 reg = <0 0x033c0000 0x0 0x20000>, 2425 <0 0x03550000 0x0 0x10000>; 2426 qcom,adsp-bypass-mode; 2427 gpio-controller; 2428 #gpio-cells = <2>; 2429 gpio-ranges = <&lpass_tlmm 0 0 15>; 2430 2431 #clock-cells = <1>; 2432 2433 lpass_dmic01_clk: dmic01-clk { 2434 pins = "gpio6"; 2435 function = "dmic1_clk"; 2436 }; 2437 2438 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2439 pins = "gpio6"; 2440 function = "dmic1_clk"; 2441 }; 2442 2443 lpass_dmic01_data: dmic01-data { 2444 pins = "gpio7"; 2445 function = "dmic1_data"; 2446 }; 2447 2448 lpass_dmic01_data_sleep: dmic01-data-sleep { 2449 pins = "gpio7"; 2450 function = "dmic1_data"; 2451 }; 2452 2453 lpass_dmic23_clk: dmic23-clk { 2454 pins = "gpio8"; 2455 function = "dmic2_clk"; 2456 }; 2457 2458 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2459 pins = "gpio8"; 2460 function = "dmic2_clk"; 2461 }; 2462 2463 lpass_dmic23_data: dmic23-data { 2464 pins = "gpio9"; 2465 function = "dmic2_data"; 2466 }; 2467 2468 lpass_dmic23_data_sleep: dmic23-data-sleep { 2469 pins = "gpio9"; 2470 function = "dmic2_data"; 2471 }; 2472 2473 lpass_rx_swr_clk: rx-swr-clk { 2474 pins = "gpio3"; 2475 function = "swr_rx_clk"; 2476 }; 2477 2478 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2479 pins = "gpio3"; 2480 function = "swr_rx_clk"; 2481 }; 2482 2483 lpass_rx_swr_data: rx-swr-data { 2484 pins = "gpio4", "gpio5"; 2485 function = "swr_rx_data"; 2486 }; 2487 2488 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2489 pins = "gpio4", "gpio5"; 2490 function = "swr_rx_data"; 2491 }; 2492 2493 lpass_tx_swr_clk: tx-swr-clk { 2494 pins = "gpio0"; 2495 function = "swr_tx_clk"; 2496 }; 2497 2498 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2499 pins = "gpio0"; 2500 function = "swr_tx_clk"; 2501 }; 2502 2503 lpass_tx_swr_data: tx-swr-data { 2504 pins = "gpio1", "gpio2", "gpio14"; 2505 function = "swr_tx_data"; 2506 }; 2507 2508 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2509 pins = "gpio1", "gpio2", "gpio14"; 2510 function = "swr_tx_data"; 2511 }; 2512 }; 2513 2514 gpu: gpu@3d00000 { 2515 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2516 reg = <0 0x03d00000 0 0x40000>, 2517 <0 0x03d9e000 0 0x1000>, 2518 <0 0x03d61000 0 0x800>; 2519 reg-names = "kgsl_3d0_reg_memory", 2520 "cx_mem", 2521 "cx_dbgc"; 2522 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2523 iommus = <&adreno_smmu 0 0x401>; 2524 operating-points-v2 = <&gpu_opp_table>; 2525 qcom,gmu = <&gmu>; 2526 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2527 interconnect-names = "gfx-mem"; 2528 #cooling-cells = <2>; 2529 2530 nvmem-cells = <&gpu_speed_bin>; 2531 nvmem-cell-names = "speed_bin"; 2532 2533 gpu_opp_table: opp-table { 2534 compatible = "operating-points-v2"; 2535 2536 opp-315000000 { 2537 opp-hz = /bits/ 64 <315000000>; 2538 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2539 opp-peak-kBps = <1804000>; 2540 opp-supported-hw = <0x03>; 2541 }; 2542 2543 opp-450000000 { 2544 opp-hz = /bits/ 64 <450000000>; 2545 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2546 opp-peak-kBps = <4068000>; 2547 opp-supported-hw = <0x03>; 2548 }; 2549 2550 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2551 opp-550000000-0 { 2552 opp-hz = /bits/ 64 <550000000>; 2553 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2554 opp-peak-kBps = <8368000>; 2555 opp-supported-hw = <0x01>; 2556 }; 2557 2558 opp-550000000-1 { 2559 opp-hz = /bits/ 64 <550000000>; 2560 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2561 opp-peak-kBps = <6832000>; 2562 opp-supported-hw = <0x02>; 2563 }; 2564 2565 opp-608000000 { 2566 opp-hz = /bits/ 64 <608000000>; 2567 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2568 opp-peak-kBps = <8368000>; 2569 opp-supported-hw = <0x02>; 2570 }; 2571 2572 opp-700000000 { 2573 opp-hz = /bits/ 64 <700000000>; 2574 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2575 opp-peak-kBps = <8532000>; 2576 opp-supported-hw = <0x02>; 2577 }; 2578 2579 opp-812000000 { 2580 opp-hz = /bits/ 64 <812000000>; 2581 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2582 opp-peak-kBps = <8532000>; 2583 opp-supported-hw = <0x02>; 2584 }; 2585 2586 opp-840000000 { 2587 opp-hz = /bits/ 64 <840000000>; 2588 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2589 opp-peak-kBps = <8532000>; 2590 opp-supported-hw = <0x02>; 2591 }; 2592 2593 opp-900000000 { 2594 opp-hz = /bits/ 64 <900000000>; 2595 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2596 opp-peak-kBps = <8532000>; 2597 opp-supported-hw = <0x02>; 2598 }; 2599 }; 2600 }; 2601 2602 gmu: gmu@3d6a000 { 2603 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2604 reg = <0 0x03d6a000 0 0x34000>, 2605 <0 0x3de0000 0 0x10000>, 2606 <0 0x0b290000 0 0x10000>; 2607 reg-names = "gmu", "rscc", "gmu_pdc"; 2608 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2610 interrupt-names = "hfi", "gmu"; 2611 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2612 <&gpucc GPU_CC_CXO_CLK>, 2613 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2614 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2615 <&gpucc GPU_CC_AHB_CLK>, 2616 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2617 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2618 clock-names = "gmu", 2619 "cxo", 2620 "axi", 2621 "memnoc", 2622 "ahb", 2623 "hub", 2624 "smmu_vote"; 2625 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2626 <&gpucc GPU_CC_GX_GDSC>; 2627 power-domain-names = "cx", 2628 "gx"; 2629 iommus = <&adreno_smmu 5 0x400>; 2630 operating-points-v2 = <&gmu_opp_table>; 2631 2632 gmu_opp_table: opp-table { 2633 compatible = "operating-points-v2"; 2634 2635 opp-200000000 { 2636 opp-hz = /bits/ 64 <200000000>; 2637 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2638 }; 2639 }; 2640 }; 2641 2642 gpucc: clock-controller@3d90000 { 2643 compatible = "qcom,sc7280-gpucc"; 2644 reg = <0 0x03d90000 0 0x9000>; 2645 clocks = <&rpmhcc RPMH_CXO_CLK>, 2646 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2647 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2648 clock-names = "bi_tcxo", 2649 "gcc_gpu_gpll0_clk_src", 2650 "gcc_gpu_gpll0_div_clk_src"; 2651 #clock-cells = <1>; 2652 #reset-cells = <1>; 2653 #power-domain-cells = <1>; 2654 }; 2655 2656 adreno_smmu: iommu@3da0000 { 2657 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2658 reg = <0 0x03da0000 0 0x20000>; 2659 #iommu-cells = <2>; 2660 #global-interrupts = <2>; 2661 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2662 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2664 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2665 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2673 2674 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2675 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2676 <&gpucc GPU_CC_AHB_CLK>, 2677 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2678 <&gpucc GPU_CC_CX_GMU_CLK>, 2679 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2680 <&gpucc GPU_CC_HUB_AON_CLK>; 2681 clock-names = "gcc_gpu_memnoc_gfx_clk", 2682 "gcc_gpu_snoc_dvm_gfx_clk", 2683 "gpu_cc_ahb_clk", 2684 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2685 "gpu_cc_cx_gmu_clk", 2686 "gpu_cc_hub_cx_int_clk", 2687 "gpu_cc_hub_aon_clk"; 2688 2689 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2690 }; 2691 2692 remoteproc_mpss: remoteproc@4080000 { 2693 compatible = "qcom,sc7280-mpss-pas"; 2694 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2695 reg-names = "qdsp6", "rmb"; 2696 2697 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2698 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2699 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2700 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2701 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2702 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2703 interrupt-names = "wdog", "fatal", "ready", "handover", 2704 "stop-ack", "shutdown-ack"; 2705 2706 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2707 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2708 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2709 <&rpmhcc RPMH_PKA_CLK>, 2710 <&rpmhcc RPMH_CXO_CLK>; 2711 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2712 2713 power-domains = <&rpmhpd SC7280_CX>, 2714 <&rpmhpd SC7280_MSS>; 2715 power-domain-names = "cx", "mss"; 2716 2717 memory-region = <&mpss_mem>; 2718 2719 qcom,qmp = <&aoss_qmp>; 2720 2721 qcom,smem-states = <&modem_smp2p_out 0>; 2722 qcom,smem-state-names = "stop"; 2723 2724 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2725 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2726 reset-names = "mss_restart", "pdc_reset"; 2727 2728 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2729 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2730 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2731 2732 status = "disabled"; 2733 2734 glink-edge { 2735 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2736 IPCC_MPROC_SIGNAL_GLINK_QMP 2737 IRQ_TYPE_EDGE_RISING>; 2738 mboxes = <&ipcc IPCC_CLIENT_MPSS 2739 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2740 label = "modem"; 2741 qcom,remote-pid = <1>; 2742 }; 2743 }; 2744 2745 stm@6002000 { 2746 compatible = "arm,coresight-stm", "arm,primecell"; 2747 reg = <0 0x06002000 0 0x1000>, 2748 <0 0x16280000 0 0x180000>; 2749 reg-names = "stm-base", "stm-stimulus-base"; 2750 2751 clocks = <&aoss_qmp>; 2752 clock-names = "apb_pclk"; 2753 2754 out-ports { 2755 port { 2756 stm_out: endpoint { 2757 remote-endpoint = <&funnel0_in7>; 2758 }; 2759 }; 2760 }; 2761 }; 2762 2763 funnel@6041000 { 2764 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2765 reg = <0 0x06041000 0 0x1000>; 2766 2767 clocks = <&aoss_qmp>; 2768 clock-names = "apb_pclk"; 2769 2770 out-ports { 2771 port { 2772 funnel0_out: endpoint { 2773 remote-endpoint = <&merge_funnel_in0>; 2774 }; 2775 }; 2776 }; 2777 2778 in-ports { 2779 #address-cells = <1>; 2780 #size-cells = <0>; 2781 2782 port@7 { 2783 reg = <7>; 2784 funnel0_in7: endpoint { 2785 remote-endpoint = <&stm_out>; 2786 }; 2787 }; 2788 }; 2789 }; 2790 2791 funnel@6042000 { 2792 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2793 reg = <0 0x06042000 0 0x1000>; 2794 2795 clocks = <&aoss_qmp>; 2796 clock-names = "apb_pclk"; 2797 2798 out-ports { 2799 port { 2800 funnel1_out: endpoint { 2801 remote-endpoint = <&merge_funnel_in1>; 2802 }; 2803 }; 2804 }; 2805 2806 in-ports { 2807 #address-cells = <1>; 2808 #size-cells = <0>; 2809 2810 port@4 { 2811 reg = <4>; 2812 funnel1_in4: endpoint { 2813 remote-endpoint = <&apss_merge_funnel_out>; 2814 }; 2815 }; 2816 }; 2817 }; 2818 2819 funnel@6045000 { 2820 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2821 reg = <0 0x06045000 0 0x1000>; 2822 2823 clocks = <&aoss_qmp>; 2824 clock-names = "apb_pclk"; 2825 2826 out-ports { 2827 port { 2828 merge_funnel_out: endpoint { 2829 remote-endpoint = <&swao_funnel_in>; 2830 }; 2831 }; 2832 }; 2833 2834 in-ports { 2835 #address-cells = <1>; 2836 #size-cells = <0>; 2837 2838 port@0 { 2839 reg = <0>; 2840 merge_funnel_in0: endpoint { 2841 remote-endpoint = <&funnel0_out>; 2842 }; 2843 }; 2844 2845 port@1 { 2846 reg = <1>; 2847 merge_funnel_in1: endpoint { 2848 remote-endpoint = <&funnel1_out>; 2849 }; 2850 }; 2851 }; 2852 }; 2853 2854 replicator@6046000 { 2855 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2856 reg = <0 0x06046000 0 0x1000>; 2857 2858 clocks = <&aoss_qmp>; 2859 clock-names = "apb_pclk"; 2860 2861 out-ports { 2862 port { 2863 replicator_out: endpoint { 2864 remote-endpoint = <&etr_in>; 2865 }; 2866 }; 2867 }; 2868 2869 in-ports { 2870 port { 2871 replicator_in: endpoint { 2872 remote-endpoint = <&swao_replicator_out>; 2873 }; 2874 }; 2875 }; 2876 }; 2877 2878 etr@6048000 { 2879 compatible = "arm,coresight-tmc", "arm,primecell"; 2880 reg = <0 0x06048000 0 0x1000>; 2881 iommus = <&apps_smmu 0x04c0 0>; 2882 2883 clocks = <&aoss_qmp>; 2884 clock-names = "apb_pclk"; 2885 arm,scatter-gather; 2886 2887 in-ports { 2888 port { 2889 etr_in: endpoint { 2890 remote-endpoint = <&replicator_out>; 2891 }; 2892 }; 2893 }; 2894 }; 2895 2896 funnel@6b04000 { 2897 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2898 reg = <0 0x06b04000 0 0x1000>; 2899 2900 clocks = <&aoss_qmp>; 2901 clock-names = "apb_pclk"; 2902 2903 out-ports { 2904 port { 2905 swao_funnel_out: endpoint { 2906 remote-endpoint = <&etf_in>; 2907 }; 2908 }; 2909 }; 2910 2911 in-ports { 2912 #address-cells = <1>; 2913 #size-cells = <0>; 2914 2915 port@7 { 2916 reg = <7>; 2917 swao_funnel_in: endpoint { 2918 remote-endpoint = <&merge_funnel_out>; 2919 }; 2920 }; 2921 }; 2922 }; 2923 2924 etf@6b05000 { 2925 compatible = "arm,coresight-tmc", "arm,primecell"; 2926 reg = <0 0x06b05000 0 0x1000>; 2927 2928 clocks = <&aoss_qmp>; 2929 clock-names = "apb_pclk"; 2930 2931 out-ports { 2932 port { 2933 etf_out: endpoint { 2934 remote-endpoint = <&swao_replicator_in>; 2935 }; 2936 }; 2937 }; 2938 2939 in-ports { 2940 port { 2941 etf_in: endpoint { 2942 remote-endpoint = <&swao_funnel_out>; 2943 }; 2944 }; 2945 }; 2946 }; 2947 2948 replicator@6b06000 { 2949 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2950 reg = <0 0x06b06000 0 0x1000>; 2951 2952 clocks = <&aoss_qmp>; 2953 clock-names = "apb_pclk"; 2954 qcom,replicator-loses-context; 2955 2956 out-ports { 2957 port { 2958 swao_replicator_out: endpoint { 2959 remote-endpoint = <&replicator_in>; 2960 }; 2961 }; 2962 }; 2963 2964 in-ports { 2965 port { 2966 swao_replicator_in: endpoint { 2967 remote-endpoint = <&etf_out>; 2968 }; 2969 }; 2970 }; 2971 }; 2972 2973 etm@7040000 { 2974 compatible = "arm,coresight-etm4x", "arm,primecell"; 2975 reg = <0 0x07040000 0 0x1000>; 2976 2977 cpu = <&CPU0>; 2978 2979 clocks = <&aoss_qmp>; 2980 clock-names = "apb_pclk"; 2981 arm,coresight-loses-context-with-cpu; 2982 qcom,skip-power-up; 2983 2984 out-ports { 2985 port { 2986 etm0_out: endpoint { 2987 remote-endpoint = <&apss_funnel_in0>; 2988 }; 2989 }; 2990 }; 2991 }; 2992 2993 etm@7140000 { 2994 compatible = "arm,coresight-etm4x", "arm,primecell"; 2995 reg = <0 0x07140000 0 0x1000>; 2996 2997 cpu = <&CPU1>; 2998 2999 clocks = <&aoss_qmp>; 3000 clock-names = "apb_pclk"; 3001 arm,coresight-loses-context-with-cpu; 3002 qcom,skip-power-up; 3003 3004 out-ports { 3005 port { 3006 etm1_out: endpoint { 3007 remote-endpoint = <&apss_funnel_in1>; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 etm@7240000 { 3014 compatible = "arm,coresight-etm4x", "arm,primecell"; 3015 reg = <0 0x07240000 0 0x1000>; 3016 3017 cpu = <&CPU2>; 3018 3019 clocks = <&aoss_qmp>; 3020 clock-names = "apb_pclk"; 3021 arm,coresight-loses-context-with-cpu; 3022 qcom,skip-power-up; 3023 3024 out-ports { 3025 port { 3026 etm2_out: endpoint { 3027 remote-endpoint = <&apss_funnel_in2>; 3028 }; 3029 }; 3030 }; 3031 }; 3032 3033 etm@7340000 { 3034 compatible = "arm,coresight-etm4x", "arm,primecell"; 3035 reg = <0 0x07340000 0 0x1000>; 3036 3037 cpu = <&CPU3>; 3038 3039 clocks = <&aoss_qmp>; 3040 clock-names = "apb_pclk"; 3041 arm,coresight-loses-context-with-cpu; 3042 qcom,skip-power-up; 3043 3044 out-ports { 3045 port { 3046 etm3_out: endpoint { 3047 remote-endpoint = <&apss_funnel_in3>; 3048 }; 3049 }; 3050 }; 3051 }; 3052 3053 etm@7440000 { 3054 compatible = "arm,coresight-etm4x", "arm,primecell"; 3055 reg = <0 0x07440000 0 0x1000>; 3056 3057 cpu = <&CPU4>; 3058 3059 clocks = <&aoss_qmp>; 3060 clock-names = "apb_pclk"; 3061 arm,coresight-loses-context-with-cpu; 3062 qcom,skip-power-up; 3063 3064 out-ports { 3065 port { 3066 etm4_out: endpoint { 3067 remote-endpoint = <&apss_funnel_in4>; 3068 }; 3069 }; 3070 }; 3071 }; 3072 3073 etm@7540000 { 3074 compatible = "arm,coresight-etm4x", "arm,primecell"; 3075 reg = <0 0x07540000 0 0x1000>; 3076 3077 cpu = <&CPU5>; 3078 3079 clocks = <&aoss_qmp>; 3080 clock-names = "apb_pclk"; 3081 arm,coresight-loses-context-with-cpu; 3082 qcom,skip-power-up; 3083 3084 out-ports { 3085 port { 3086 etm5_out: endpoint { 3087 remote-endpoint = <&apss_funnel_in5>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 etm@7640000 { 3094 compatible = "arm,coresight-etm4x", "arm,primecell"; 3095 reg = <0 0x07640000 0 0x1000>; 3096 3097 cpu = <&CPU6>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 arm,coresight-loses-context-with-cpu; 3102 qcom,skip-power-up; 3103 3104 out-ports { 3105 port { 3106 etm6_out: endpoint { 3107 remote-endpoint = <&apss_funnel_in6>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 etm@7740000 { 3114 compatible = "arm,coresight-etm4x", "arm,primecell"; 3115 reg = <0 0x07740000 0 0x1000>; 3116 3117 cpu = <&CPU7>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 arm,coresight-loses-context-with-cpu; 3122 qcom,skip-power-up; 3123 3124 out-ports { 3125 port { 3126 etm7_out: endpoint { 3127 remote-endpoint = <&apss_funnel_in7>; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 funnel@7800000 { /* APSS Funnel */ 3134 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3135 reg = <0 0x07800000 0 0x1000>; 3136 3137 clocks = <&aoss_qmp>; 3138 clock-names = "apb_pclk"; 3139 3140 out-ports { 3141 port { 3142 apss_funnel_out: endpoint { 3143 remote-endpoint = <&apss_merge_funnel_in>; 3144 }; 3145 }; 3146 }; 3147 3148 in-ports { 3149 #address-cells = <1>; 3150 #size-cells = <0>; 3151 3152 port@0 { 3153 reg = <0>; 3154 apss_funnel_in0: endpoint { 3155 remote-endpoint = <&etm0_out>; 3156 }; 3157 }; 3158 3159 port@1 { 3160 reg = <1>; 3161 apss_funnel_in1: endpoint { 3162 remote-endpoint = <&etm1_out>; 3163 }; 3164 }; 3165 3166 port@2 { 3167 reg = <2>; 3168 apss_funnel_in2: endpoint { 3169 remote-endpoint = <&etm2_out>; 3170 }; 3171 }; 3172 3173 port@3 { 3174 reg = <3>; 3175 apss_funnel_in3: endpoint { 3176 remote-endpoint = <&etm3_out>; 3177 }; 3178 }; 3179 3180 port@4 { 3181 reg = <4>; 3182 apss_funnel_in4: endpoint { 3183 remote-endpoint = <&etm4_out>; 3184 }; 3185 }; 3186 3187 port@5 { 3188 reg = <5>; 3189 apss_funnel_in5: endpoint { 3190 remote-endpoint = <&etm5_out>; 3191 }; 3192 }; 3193 3194 port@6 { 3195 reg = <6>; 3196 apss_funnel_in6: endpoint { 3197 remote-endpoint = <&etm6_out>; 3198 }; 3199 }; 3200 3201 port@7 { 3202 reg = <7>; 3203 apss_funnel_in7: endpoint { 3204 remote-endpoint = <&etm7_out>; 3205 }; 3206 }; 3207 }; 3208 }; 3209 3210 funnel@7810000 { 3211 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3212 reg = <0 0x07810000 0 0x1000>; 3213 3214 clocks = <&aoss_qmp>; 3215 clock-names = "apb_pclk"; 3216 3217 out-ports { 3218 port { 3219 apss_merge_funnel_out: endpoint { 3220 remote-endpoint = <&funnel1_in4>; 3221 }; 3222 }; 3223 }; 3224 3225 in-ports { 3226 port { 3227 apss_merge_funnel_in: endpoint { 3228 remote-endpoint = <&apss_funnel_out>; 3229 }; 3230 }; 3231 }; 3232 }; 3233 3234 sdhc_2: mmc@8804000 { 3235 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3236 pinctrl-names = "default", "sleep"; 3237 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3238 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3239 status = "disabled"; 3240 3241 reg = <0 0x08804000 0 0x1000>; 3242 3243 iommus = <&apps_smmu 0x100 0x0>; 3244 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3246 interrupt-names = "hc_irq", "pwr_irq"; 3247 3248 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3249 <&gcc GCC_SDCC2_APPS_CLK>, 3250 <&rpmhcc RPMH_CXO_CLK>; 3251 clock-names = "iface", "core", "xo"; 3252 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3253 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3254 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3255 power-domains = <&rpmhpd SC7280_CX>; 3256 operating-points-v2 = <&sdhc2_opp_table>; 3257 3258 bus-width = <4>; 3259 3260 qcom,dll-config = <0x0007642c>; 3261 3262 resets = <&gcc GCC_SDCC2_BCR>; 3263 3264 sdhc2_opp_table: opp-table { 3265 compatible = "operating-points-v2"; 3266 3267 opp-100000000 { 3268 opp-hz = /bits/ 64 <100000000>; 3269 required-opps = <&rpmhpd_opp_low_svs>; 3270 opp-peak-kBps = <1800000 400000>; 3271 opp-avg-kBps = <100000 0>; 3272 }; 3273 3274 opp-202000000 { 3275 opp-hz = /bits/ 64 <202000000>; 3276 required-opps = <&rpmhpd_opp_nom>; 3277 opp-peak-kBps = <5400000 1600000>; 3278 opp-avg-kBps = <200000 0>; 3279 }; 3280 }; 3281 3282 }; 3283 3284 usb_1_hsphy: phy@88e3000 { 3285 compatible = "qcom,sc7280-usb-hs-phy", 3286 "qcom,usb-snps-hs-7nm-phy"; 3287 reg = <0 0x088e3000 0 0x400>; 3288 status = "disabled"; 3289 #phy-cells = <0>; 3290 3291 clocks = <&rpmhcc RPMH_CXO_CLK>; 3292 clock-names = "ref"; 3293 3294 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3295 }; 3296 3297 usb_2_hsphy: phy@88e4000 { 3298 compatible = "qcom,sc7280-usb-hs-phy", 3299 "qcom,usb-snps-hs-7nm-phy"; 3300 reg = <0 0x088e4000 0 0x400>; 3301 status = "disabled"; 3302 #phy-cells = <0>; 3303 3304 clocks = <&rpmhcc RPMH_CXO_CLK>; 3305 clock-names = "ref"; 3306 3307 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3308 }; 3309 3310 usb_1_qmpphy: phy-wrapper@88e9000 { 3311 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3312 "qcom,sm8250-qmp-usb3-dp-phy"; 3313 reg = <0 0x088e9000 0 0x200>, 3314 <0 0x088e8000 0 0x40>, 3315 <0 0x088ea000 0 0x200>; 3316 status = "disabled"; 3317 #address-cells = <2>; 3318 #size-cells = <2>; 3319 ranges; 3320 3321 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3322 <&rpmhcc RPMH_CXO_CLK>, 3323 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3324 clock-names = "aux", "ref_clk_src", "com_aux"; 3325 3326 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3327 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3328 reset-names = "phy", "common"; 3329 3330 usb_1_ssphy: usb3-phy@88e9200 { 3331 reg = <0 0x088e9200 0 0x200>, 3332 <0 0x088e9400 0 0x200>, 3333 <0 0x088e9c00 0 0x400>, 3334 <0 0x088e9600 0 0x200>, 3335 <0 0x088e9800 0 0x200>, 3336 <0 0x088e9a00 0 0x100>; 3337 #clock-cells = <0>; 3338 #phy-cells = <0>; 3339 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3340 clock-names = "pipe0"; 3341 clock-output-names = "usb3_phy_pipe_clk_src"; 3342 }; 3343 3344 dp_phy: dp-phy@88ea200 { 3345 reg = <0 0x088ea200 0 0x200>, 3346 <0 0x088ea400 0 0x200>, 3347 <0 0x088eaa00 0 0x200>, 3348 <0 0x088ea600 0 0x200>, 3349 <0 0x088ea800 0 0x200>; 3350 #phy-cells = <0>; 3351 #clock-cells = <1>; 3352 }; 3353 }; 3354 3355 usb_2: usb@8cf8800 { 3356 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3357 reg = <0 0x08cf8800 0 0x400>; 3358 status = "disabled"; 3359 #address-cells = <2>; 3360 #size-cells = <2>; 3361 ranges; 3362 dma-ranges; 3363 3364 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3365 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3366 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3367 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3368 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3369 clock-names = "cfg_noc", 3370 "core", 3371 "iface", 3372 "sleep", 3373 "mock_utmi"; 3374 3375 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3376 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3377 assigned-clock-rates = <19200000>, <200000000>; 3378 3379 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3380 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3381 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3382 interrupt-names = "hs_phy_irq", 3383 "dp_hs_phy_irq", 3384 "dm_hs_phy_irq"; 3385 3386 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3387 3388 resets = <&gcc GCC_USB30_SEC_BCR>; 3389 3390 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3391 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3392 interconnect-names = "usb-ddr", "apps-usb"; 3393 3394 usb_2_dwc3: usb@8c00000 { 3395 compatible = "snps,dwc3"; 3396 reg = <0 0x08c00000 0 0xe000>; 3397 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3398 iommus = <&apps_smmu 0xa0 0x0>; 3399 snps,dis_u2_susphy_quirk; 3400 snps,dis_enblslpm_quirk; 3401 phys = <&usb_2_hsphy>; 3402 phy-names = "usb2-phy"; 3403 maximum-speed = "high-speed"; 3404 usb-role-switch; 3405 port { 3406 usb2_role_switch: endpoint { 3407 remote-endpoint = <&eud_ep>; 3408 }; 3409 }; 3410 }; 3411 }; 3412 3413 qspi: spi@88dc000 { 3414 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3415 reg = <0 0x088dc000 0 0x1000>; 3416 #address-cells = <1>; 3417 #size-cells = <0>; 3418 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3419 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3420 <&gcc GCC_QSPI_CORE_CLK>; 3421 clock-names = "iface", "core"; 3422 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3423 &cnoc2 SLAVE_QSPI_0 0>; 3424 interconnect-names = "qspi-config"; 3425 power-domains = <&rpmhpd SC7280_CX>; 3426 operating-points-v2 = <&qspi_opp_table>; 3427 status = "disabled"; 3428 }; 3429 3430 remoteproc_wpss: remoteproc@8a00000 { 3431 compatible = "qcom,sc7280-wpss-pil"; 3432 reg = <0 0x08a00000 0 0x10000>; 3433 3434 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3435 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3436 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3437 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3438 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3439 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3440 interrupt-names = "wdog", "fatal", "ready", "handover", 3441 "stop-ack", "shutdown-ack"; 3442 3443 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3444 <&gcc GCC_WPSS_AHB_CLK>, 3445 <&gcc GCC_WPSS_RSCP_CLK>, 3446 <&rpmhcc RPMH_CXO_CLK>; 3447 clock-names = "ahb_bdg", "ahb", 3448 "rscp", "xo"; 3449 3450 power-domains = <&rpmhpd SC7280_CX>, 3451 <&rpmhpd SC7280_MX>; 3452 power-domain-names = "cx", "mx"; 3453 3454 memory-region = <&wpss_mem>; 3455 3456 qcom,qmp = <&aoss_qmp>; 3457 3458 qcom,smem-states = <&wpss_smp2p_out 0>; 3459 qcom,smem-state-names = "stop"; 3460 3461 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3462 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3463 reset-names = "restart", "pdc_sync"; 3464 3465 qcom,halt-regs = <&tcsr_1 0x17000>; 3466 3467 status = "disabled"; 3468 3469 glink-edge { 3470 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3471 IPCC_MPROC_SIGNAL_GLINK_QMP 3472 IRQ_TYPE_EDGE_RISING>; 3473 mboxes = <&ipcc IPCC_CLIENT_WPSS 3474 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3475 3476 label = "wpss"; 3477 qcom,remote-pid = <13>; 3478 }; 3479 }; 3480 3481 pmu@9091000 { 3482 compatible = "qcom,sc7280-llcc-bwmon"; 3483 reg = <0 0x9091000 0 0x1000>; 3484 3485 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3486 3487 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3488 3489 operating-points-v2 = <&llcc_bwmon_opp_table>; 3490 3491 llcc_bwmon_opp_table: opp-table { 3492 compatible = "operating-points-v2"; 3493 3494 opp-0 { 3495 opp-peak-kBps = <800000>; 3496 }; 3497 opp-1 { 3498 opp-peak-kBps = <1804000>; 3499 }; 3500 opp-2 { 3501 opp-peak-kBps = <2188000>; 3502 }; 3503 opp-3 { 3504 opp-peak-kBps = <3072000>; 3505 }; 3506 opp-4 { 3507 opp-peak-kBps = <4068000>; 3508 }; 3509 opp-5 { 3510 opp-peak-kBps = <6220000>; 3511 }; 3512 opp-6 { 3513 opp-peak-kBps = <6832000>; 3514 }; 3515 opp-7 { 3516 opp-peak-kBps = <8532000>; 3517 }; 3518 }; 3519 }; 3520 3521 pmu@90b6400 { 3522 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3523 reg = <0 0x090b6400 0 0x600>; 3524 3525 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3526 3527 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3528 operating-points-v2 = <&cpu_bwmon_opp_table>; 3529 3530 cpu_bwmon_opp_table: opp-table { 3531 compatible = "operating-points-v2"; 3532 3533 opp-0 { 3534 opp-peak-kBps = <2400000>; 3535 }; 3536 opp-1 { 3537 opp-peak-kBps = <4800000>; 3538 }; 3539 opp-2 { 3540 opp-peak-kBps = <7456000>; 3541 }; 3542 opp-3 { 3543 opp-peak-kBps = <9600000>; 3544 }; 3545 opp-4 { 3546 opp-peak-kBps = <12896000>; 3547 }; 3548 opp-5 { 3549 opp-peak-kBps = <14928000>; 3550 }; 3551 opp-6 { 3552 opp-peak-kBps = <17056000>; 3553 }; 3554 }; 3555 }; 3556 3557 dc_noc: interconnect@90e0000 { 3558 reg = <0 0x090e0000 0 0x5080>; 3559 compatible = "qcom,sc7280-dc-noc"; 3560 #interconnect-cells = <2>; 3561 qcom,bcm-voters = <&apps_bcm_voter>; 3562 }; 3563 3564 gem_noc: interconnect@9100000 { 3565 reg = <0 0x9100000 0 0xe2200>; 3566 compatible = "qcom,sc7280-gem-noc"; 3567 #interconnect-cells = <2>; 3568 qcom,bcm-voters = <&apps_bcm_voter>; 3569 }; 3570 3571 system-cache-controller@9200000 { 3572 compatible = "qcom,sc7280-llcc"; 3573 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3574 reg-names = "llcc_base", "llcc_broadcast_base"; 3575 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3576 }; 3577 3578 eud: eud@88e0000 { 3579 compatible = "qcom,sc7280-eud","qcom,eud"; 3580 reg = <0 0x88e0000 0 0x2000>, 3581 <0 0x88e2000 0 0x1000>; 3582 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3583 ports { 3584 port@0 { 3585 eud_ep: endpoint { 3586 remote-endpoint = <&usb2_role_switch>; 3587 }; 3588 }; 3589 port@1 { 3590 eud_con: endpoint { 3591 remote-endpoint = <&con_eud>; 3592 }; 3593 }; 3594 }; 3595 }; 3596 3597 eud_typec: connector { 3598 compatible = "usb-c-connector"; 3599 ports { 3600 port@0 { 3601 con_eud: endpoint { 3602 remote-endpoint = <&eud_con>; 3603 }; 3604 }; 3605 }; 3606 }; 3607 3608 nsp_noc: interconnect@a0c0000 { 3609 reg = <0 0x0a0c0000 0 0x10000>; 3610 compatible = "qcom,sc7280-nsp-noc"; 3611 #interconnect-cells = <2>; 3612 qcom,bcm-voters = <&apps_bcm_voter>; 3613 }; 3614 3615 usb_1: usb@a6f8800 { 3616 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3617 reg = <0 0x0a6f8800 0 0x400>; 3618 status = "disabled"; 3619 #address-cells = <2>; 3620 #size-cells = <2>; 3621 ranges; 3622 dma-ranges; 3623 3624 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3625 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3626 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3627 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3628 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3629 clock-names = "cfg_noc", 3630 "core", 3631 "iface", 3632 "sleep", 3633 "mock_utmi"; 3634 3635 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3636 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3637 assigned-clock-rates = <19200000>, <200000000>; 3638 3639 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3640 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3641 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3642 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3643 interrupt-names = "hs_phy_irq", 3644 "dp_hs_phy_irq", 3645 "dm_hs_phy_irq", 3646 "ss_phy_irq"; 3647 3648 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3649 3650 resets = <&gcc GCC_USB30_PRIM_BCR>; 3651 3652 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3654 interconnect-names = "usb-ddr", "apps-usb"; 3655 3656 usb_1_dwc3: usb@a600000 { 3657 compatible = "snps,dwc3"; 3658 reg = <0 0x0a600000 0 0xe000>; 3659 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3660 iommus = <&apps_smmu 0xe0 0x0>; 3661 snps,dis_u2_susphy_quirk; 3662 snps,dis_enblslpm_quirk; 3663 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3664 phy-names = "usb2-phy", "usb3-phy"; 3665 maximum-speed = "super-speed"; 3666 wakeup-source; 3667 }; 3668 }; 3669 3670 venus: video-codec@aa00000 { 3671 compatible = "qcom,sc7280-venus"; 3672 reg = <0 0x0aa00000 0 0xd0600>; 3673 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3674 3675 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3676 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3677 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3678 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3679 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3680 clock-names = "core", "bus", "iface", 3681 "vcodec_core", "vcodec_bus"; 3682 3683 power-domains = <&videocc MVSC_GDSC>, 3684 <&videocc MVS0_GDSC>, 3685 <&rpmhpd SC7280_CX>; 3686 power-domain-names = "venus", "vcodec0", "cx"; 3687 operating-points-v2 = <&venus_opp_table>; 3688 3689 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3690 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3691 interconnect-names = "cpu-cfg", "video-mem"; 3692 3693 iommus = <&apps_smmu 0x2180 0x20>, 3694 <&apps_smmu 0x2184 0x20>; 3695 memory-region = <&video_mem>; 3696 3697 video-decoder { 3698 compatible = "venus-decoder"; 3699 }; 3700 3701 video-encoder { 3702 compatible = "venus-encoder"; 3703 }; 3704 3705 video-firmware { 3706 iommus = <&apps_smmu 0x21a2 0x0>; 3707 }; 3708 3709 venus_opp_table: opp-table { 3710 compatible = "operating-points-v2"; 3711 3712 opp-133330000 { 3713 opp-hz = /bits/ 64 <133330000>; 3714 required-opps = <&rpmhpd_opp_low_svs>; 3715 }; 3716 3717 opp-240000000 { 3718 opp-hz = /bits/ 64 <240000000>; 3719 required-opps = <&rpmhpd_opp_svs>; 3720 }; 3721 3722 opp-335000000 { 3723 opp-hz = /bits/ 64 <335000000>; 3724 required-opps = <&rpmhpd_opp_svs_l1>; 3725 }; 3726 3727 opp-424000000 { 3728 opp-hz = /bits/ 64 <424000000>; 3729 required-opps = <&rpmhpd_opp_nom>; 3730 }; 3731 3732 opp-460000048 { 3733 opp-hz = /bits/ 64 <460000048>; 3734 required-opps = <&rpmhpd_opp_turbo>; 3735 }; 3736 }; 3737 3738 }; 3739 3740 videocc: clock-controller@aaf0000 { 3741 compatible = "qcom,sc7280-videocc"; 3742 reg = <0 0xaaf0000 0 0x10000>; 3743 clocks = <&rpmhcc RPMH_CXO_CLK>, 3744 <&rpmhcc RPMH_CXO_CLK_A>; 3745 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3746 #clock-cells = <1>; 3747 #reset-cells = <1>; 3748 #power-domain-cells = <1>; 3749 }; 3750 3751 camcc: clock-controller@ad00000 { 3752 compatible = "qcom,sc7280-camcc"; 3753 reg = <0 0x0ad00000 0 0x10000>; 3754 clocks = <&rpmhcc RPMH_CXO_CLK>, 3755 <&rpmhcc RPMH_CXO_CLK_A>, 3756 <&sleep_clk>; 3757 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3758 #clock-cells = <1>; 3759 #reset-cells = <1>; 3760 #power-domain-cells = <1>; 3761 }; 3762 3763 dispcc: clock-controller@af00000 { 3764 compatible = "qcom,sc7280-dispcc"; 3765 reg = <0 0xaf00000 0 0x20000>; 3766 clocks = <&rpmhcc RPMH_CXO_CLK>, 3767 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3768 <&mdss_dsi_phy 0>, 3769 <&mdss_dsi_phy 1>, 3770 <&dp_phy 0>, 3771 <&dp_phy 1>, 3772 <&mdss_edp_phy 0>, 3773 <&mdss_edp_phy 1>; 3774 clock-names = "bi_tcxo", 3775 "gcc_disp_gpll0_clk", 3776 "dsi0_phy_pll_out_byteclk", 3777 "dsi0_phy_pll_out_dsiclk", 3778 "dp_phy_pll_link_clk", 3779 "dp_phy_pll_vco_div_clk", 3780 "edp_phy_pll_link_clk", 3781 "edp_phy_pll_vco_div_clk"; 3782 #clock-cells = <1>; 3783 #reset-cells = <1>; 3784 #power-domain-cells = <1>; 3785 }; 3786 3787 mdss: display-subsystem@ae00000 { 3788 compatible = "qcom,sc7280-mdss"; 3789 reg = <0 0x0ae00000 0 0x1000>; 3790 reg-names = "mdss"; 3791 3792 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3793 3794 clocks = <&gcc GCC_DISP_AHB_CLK>, 3795 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3796 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3797 clock-names = "iface", 3798 "ahb", 3799 "core"; 3800 3801 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3802 interrupt-controller; 3803 #interrupt-cells = <1>; 3804 3805 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3806 interconnect-names = "mdp0-mem"; 3807 3808 iommus = <&apps_smmu 0x900 0x402>; 3809 3810 #address-cells = <2>; 3811 #size-cells = <2>; 3812 ranges; 3813 3814 status = "disabled"; 3815 3816 mdss_mdp: display-controller@ae01000 { 3817 compatible = "qcom,sc7280-dpu"; 3818 reg = <0 0x0ae01000 0 0x8f030>, 3819 <0 0x0aeb0000 0 0x2008>; 3820 reg-names = "mdp", "vbif"; 3821 3822 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3823 <&gcc GCC_DISP_SF_AXI_CLK>, 3824 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3825 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3826 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3827 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3828 clock-names = "bus", 3829 "nrt_bus", 3830 "iface", 3831 "lut", 3832 "core", 3833 "vsync"; 3834 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3835 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3836 assigned-clock-rates = <19200000>, 3837 <19200000>; 3838 operating-points-v2 = <&mdp_opp_table>; 3839 power-domains = <&rpmhpd SC7280_CX>; 3840 3841 interrupt-parent = <&mdss>; 3842 interrupts = <0>; 3843 3844 status = "disabled"; 3845 3846 ports { 3847 #address-cells = <1>; 3848 #size-cells = <0>; 3849 3850 port@0 { 3851 reg = <0>; 3852 dpu_intf1_out: endpoint { 3853 remote-endpoint = <&dsi0_in>; 3854 }; 3855 }; 3856 3857 port@1 { 3858 reg = <1>; 3859 dpu_intf5_out: endpoint { 3860 remote-endpoint = <&edp_in>; 3861 }; 3862 }; 3863 3864 port@2 { 3865 reg = <2>; 3866 dpu_intf0_out: endpoint { 3867 remote-endpoint = <&dp_in>; 3868 }; 3869 }; 3870 }; 3871 3872 mdp_opp_table: opp-table { 3873 compatible = "operating-points-v2"; 3874 3875 opp-200000000 { 3876 opp-hz = /bits/ 64 <200000000>; 3877 required-opps = <&rpmhpd_opp_low_svs>; 3878 }; 3879 3880 opp-300000000 { 3881 opp-hz = /bits/ 64 <300000000>; 3882 required-opps = <&rpmhpd_opp_svs>; 3883 }; 3884 3885 opp-380000000 { 3886 opp-hz = /bits/ 64 <380000000>; 3887 required-opps = <&rpmhpd_opp_svs_l1>; 3888 }; 3889 3890 opp-506666667 { 3891 opp-hz = /bits/ 64 <506666667>; 3892 required-opps = <&rpmhpd_opp_nom>; 3893 }; 3894 }; 3895 }; 3896 3897 mdss_dsi: dsi@ae94000 { 3898 compatible = "qcom,mdss-dsi-ctrl"; 3899 reg = <0 0x0ae94000 0 0x400>; 3900 reg-names = "dsi_ctrl"; 3901 3902 interrupt-parent = <&mdss>; 3903 interrupts = <4>; 3904 3905 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3906 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3907 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3908 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3909 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3910 <&gcc GCC_DISP_HF_AXI_CLK>; 3911 clock-names = "byte", 3912 "byte_intf", 3913 "pixel", 3914 "core", 3915 "iface", 3916 "bus"; 3917 3918 operating-points-v2 = <&dsi_opp_table>; 3919 power-domains = <&rpmhpd SC7280_CX>; 3920 3921 phys = <&mdss_dsi_phy>; 3922 phy-names = "dsi"; 3923 3924 #address-cells = <1>; 3925 #size-cells = <0>; 3926 3927 status = "disabled"; 3928 3929 ports { 3930 #address-cells = <1>; 3931 #size-cells = <0>; 3932 3933 port@0 { 3934 reg = <0>; 3935 dsi0_in: endpoint { 3936 remote-endpoint = <&dpu_intf1_out>; 3937 }; 3938 }; 3939 3940 port@1 { 3941 reg = <1>; 3942 dsi0_out: endpoint { 3943 }; 3944 }; 3945 }; 3946 3947 dsi_opp_table: opp-table { 3948 compatible = "operating-points-v2"; 3949 3950 opp-187500000 { 3951 opp-hz = /bits/ 64 <187500000>; 3952 required-opps = <&rpmhpd_opp_low_svs>; 3953 }; 3954 3955 opp-300000000 { 3956 opp-hz = /bits/ 64 <300000000>; 3957 required-opps = <&rpmhpd_opp_svs>; 3958 }; 3959 3960 opp-358000000 { 3961 opp-hz = /bits/ 64 <358000000>; 3962 required-opps = <&rpmhpd_opp_svs_l1>; 3963 }; 3964 }; 3965 }; 3966 3967 mdss_dsi_phy: phy@ae94400 { 3968 compatible = "qcom,sc7280-dsi-phy-7nm"; 3969 reg = <0 0x0ae94400 0 0x200>, 3970 <0 0x0ae94600 0 0x280>, 3971 <0 0x0ae94900 0 0x280>; 3972 reg-names = "dsi_phy", 3973 "dsi_phy_lane", 3974 "dsi_pll"; 3975 3976 #clock-cells = <1>; 3977 #phy-cells = <0>; 3978 3979 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3980 <&rpmhcc RPMH_CXO_CLK>; 3981 clock-names = "iface", "ref"; 3982 3983 status = "disabled"; 3984 }; 3985 3986 mdss_edp: edp@aea0000 { 3987 compatible = "qcom,sc7280-edp"; 3988 pinctrl-names = "default"; 3989 pinctrl-0 = <&edp_hot_plug_det>; 3990 3991 reg = <0 0xaea0000 0 0x200>, 3992 <0 0xaea0200 0 0x200>, 3993 <0 0xaea0400 0 0xc00>, 3994 <0 0xaea1000 0 0x400>; 3995 3996 interrupt-parent = <&mdss>; 3997 interrupts = <14>; 3998 3999 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4000 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4001 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4002 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4003 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4004 clock-names = "core_iface", 4005 "core_aux", 4006 "ctrl_link", 4007 "ctrl_link_iface", 4008 "stream_pixel"; 4009 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4010 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4011 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4012 4013 phys = <&mdss_edp_phy>; 4014 phy-names = "dp"; 4015 4016 operating-points-v2 = <&edp_opp_table>; 4017 power-domains = <&rpmhpd SC7280_CX>; 4018 4019 status = "disabled"; 4020 4021 ports { 4022 #address-cells = <1>; 4023 #size-cells = <0>; 4024 4025 port@0 { 4026 reg = <0>; 4027 edp_in: endpoint { 4028 remote-endpoint = <&dpu_intf5_out>; 4029 }; 4030 }; 4031 4032 port@1 { 4033 reg = <1>; 4034 mdss_edp_out: endpoint { }; 4035 }; 4036 }; 4037 4038 edp_opp_table: opp-table { 4039 compatible = "operating-points-v2"; 4040 4041 opp-160000000 { 4042 opp-hz = /bits/ 64 <160000000>; 4043 required-opps = <&rpmhpd_opp_low_svs>; 4044 }; 4045 4046 opp-270000000 { 4047 opp-hz = /bits/ 64 <270000000>; 4048 required-opps = <&rpmhpd_opp_svs>; 4049 }; 4050 4051 opp-540000000 { 4052 opp-hz = /bits/ 64 <540000000>; 4053 required-opps = <&rpmhpd_opp_nom>; 4054 }; 4055 4056 opp-810000000 { 4057 opp-hz = /bits/ 64 <810000000>; 4058 required-opps = <&rpmhpd_opp_nom>; 4059 }; 4060 }; 4061 }; 4062 4063 mdss_edp_phy: phy@aec2a00 { 4064 compatible = "qcom,sc7280-edp-phy"; 4065 4066 reg = <0 0xaec2a00 0 0x19c>, 4067 <0 0xaec2200 0 0xa0>, 4068 <0 0xaec2600 0 0xa0>, 4069 <0 0xaec2000 0 0x1c0>; 4070 4071 clocks = <&rpmhcc RPMH_CXO_CLK>, 4072 <&gcc GCC_EDP_CLKREF_EN>; 4073 clock-names = "aux", 4074 "cfg_ahb"; 4075 4076 #clock-cells = <1>; 4077 #phy-cells = <0>; 4078 4079 status = "disabled"; 4080 }; 4081 4082 mdss_dp: displayport-controller@ae90000 { 4083 compatible = "qcom,sc7280-dp"; 4084 4085 reg = <0 0xae90000 0 0x200>, 4086 <0 0xae90200 0 0x200>, 4087 <0 0xae90400 0 0xc00>, 4088 <0 0xae91000 0 0x400>, 4089 <0 0xae91400 0 0x400>; 4090 4091 interrupt-parent = <&mdss>; 4092 interrupts = <12>; 4093 4094 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4095 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4096 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4097 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4098 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4099 clock-names = "core_iface", 4100 "core_aux", 4101 "ctrl_link", 4102 "ctrl_link_iface", 4103 "stream_pixel"; 4104 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4105 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4106 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4107 phys = <&dp_phy>; 4108 phy-names = "dp"; 4109 4110 operating-points-v2 = <&dp_opp_table>; 4111 power-domains = <&rpmhpd SC7280_CX>; 4112 4113 #sound-dai-cells = <0>; 4114 4115 status = "disabled"; 4116 4117 ports { 4118 #address-cells = <1>; 4119 #size-cells = <0>; 4120 4121 port@0 { 4122 reg = <0>; 4123 dp_in: endpoint { 4124 remote-endpoint = <&dpu_intf0_out>; 4125 }; 4126 }; 4127 4128 port@1 { 4129 reg = <1>; 4130 dp_out: endpoint { }; 4131 }; 4132 }; 4133 4134 dp_opp_table: opp-table { 4135 compatible = "operating-points-v2"; 4136 4137 opp-160000000 { 4138 opp-hz = /bits/ 64 <160000000>; 4139 required-opps = <&rpmhpd_opp_low_svs>; 4140 }; 4141 4142 opp-270000000 { 4143 opp-hz = /bits/ 64 <270000000>; 4144 required-opps = <&rpmhpd_opp_svs>; 4145 }; 4146 4147 opp-540000000 { 4148 opp-hz = /bits/ 64 <540000000>; 4149 required-opps = <&rpmhpd_opp_svs_l1>; 4150 }; 4151 4152 opp-810000000 { 4153 opp-hz = /bits/ 64 <810000000>; 4154 required-opps = <&rpmhpd_opp_nom>; 4155 }; 4156 }; 4157 }; 4158 }; 4159 4160 pdc: interrupt-controller@b220000 { 4161 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4162 reg = <0 0x0b220000 0 0x30000>; 4163 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4164 <55 306 4>, <59 312 3>, <62 374 2>, 4165 <64 434 2>, <66 438 3>, <69 86 1>, 4166 <70 520 54>, <124 609 31>, <155 63 1>, 4167 <156 716 12>; 4168 #interrupt-cells = <2>; 4169 interrupt-parent = <&intc>; 4170 interrupt-controller; 4171 }; 4172 4173 pdc_reset: reset-controller@b5e0000 { 4174 compatible = "qcom,sc7280-pdc-global"; 4175 reg = <0 0x0b5e0000 0 0x20000>; 4176 #reset-cells = <1>; 4177 }; 4178 4179 tsens0: thermal-sensor@c263000 { 4180 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4181 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4182 <0 0x0c222000 0 0x1ff>; /* SROT */ 4183 #qcom,sensors = <15>; 4184 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4186 interrupt-names = "uplow","critical"; 4187 #thermal-sensor-cells = <1>; 4188 }; 4189 4190 tsens1: thermal-sensor@c265000 { 4191 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4192 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4193 <0 0x0c223000 0 0x1ff>; /* SROT */ 4194 #qcom,sensors = <12>; 4195 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4197 interrupt-names = "uplow","critical"; 4198 #thermal-sensor-cells = <1>; 4199 }; 4200 4201 aoss_reset: reset-controller@c2a0000 { 4202 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4203 reg = <0 0x0c2a0000 0 0x31000>; 4204 #reset-cells = <1>; 4205 }; 4206 4207 aoss_qmp: power-controller@c300000 { 4208 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4209 reg = <0 0x0c300000 0 0x400>; 4210 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4211 IPCC_MPROC_SIGNAL_GLINK_QMP 4212 IRQ_TYPE_EDGE_RISING>; 4213 mboxes = <&ipcc IPCC_CLIENT_AOP 4214 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4215 4216 #clock-cells = <0>; 4217 }; 4218 4219 sram@c3f0000 { 4220 compatible = "qcom,rpmh-stats"; 4221 reg = <0 0x0c3f0000 0 0x400>; 4222 }; 4223 4224 spmi_bus: spmi@c440000 { 4225 compatible = "qcom,spmi-pmic-arb"; 4226 reg = <0 0x0c440000 0 0x1100>, 4227 <0 0x0c600000 0 0x2000000>, 4228 <0 0x0e600000 0 0x100000>, 4229 <0 0x0e700000 0 0xa0000>, 4230 <0 0x0c40a000 0 0x26000>; 4231 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4232 interrupt-names = "periph_irq"; 4233 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4234 qcom,ee = <0>; 4235 qcom,channel = <0>; 4236 #address-cells = <1>; 4237 #size-cells = <1>; 4238 interrupt-controller; 4239 #interrupt-cells = <4>; 4240 }; 4241 4242 tlmm: pinctrl@f100000 { 4243 compatible = "qcom,sc7280-pinctrl"; 4244 reg = <0 0x0f100000 0 0x300000>; 4245 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4246 gpio-controller; 4247 #gpio-cells = <2>; 4248 interrupt-controller; 4249 #interrupt-cells = <2>; 4250 gpio-ranges = <&tlmm 0 0 175>; 4251 wakeup-parent = <&pdc>; 4252 4253 dp_hot_plug_det: dp-hot-plug-det { 4254 pins = "gpio47"; 4255 function = "dp_hot"; 4256 }; 4257 4258 edp_hot_plug_det: edp-hot-plug-det { 4259 pins = "gpio60"; 4260 function = "edp_hot"; 4261 }; 4262 4263 mi2s0_data0: mi2s0-data0 { 4264 pins = "gpio98"; 4265 function = "mi2s0_data0"; 4266 }; 4267 4268 mi2s0_data1: mi2s0-data1 { 4269 pins = "gpio99"; 4270 function = "mi2s0_data1"; 4271 }; 4272 4273 mi2s0_mclk: mi2s0-mclk { 4274 pins = "gpio96"; 4275 function = "pri_mi2s"; 4276 }; 4277 4278 mi2s0_sclk: mi2s0-sclk { 4279 pins = "gpio97"; 4280 function = "mi2s0_sck"; 4281 }; 4282 4283 mi2s0_ws: mi2s0-ws { 4284 pins = "gpio100"; 4285 function = "mi2s0_ws"; 4286 }; 4287 4288 mi2s1_data0: mi2s1-data0 { 4289 pins = "gpio107"; 4290 function = "mi2s1_data0"; 4291 }; 4292 4293 mi2s1_sclk: mi2s1-sclk { 4294 pins = "gpio106"; 4295 function = "mi2s1_sck"; 4296 }; 4297 4298 mi2s1_ws: mi2s1-ws { 4299 pins = "gpio108"; 4300 function = "mi2s1_ws"; 4301 }; 4302 4303 pcie1_clkreq_n: pcie1-clkreq-n { 4304 pins = "gpio79"; 4305 function = "pcie1_clkreqn"; 4306 }; 4307 4308 qspi_clk: qspi-clk { 4309 pins = "gpio14"; 4310 function = "qspi_clk"; 4311 }; 4312 4313 qspi_cs0: qspi-cs0 { 4314 pins = "gpio15"; 4315 function = "qspi_cs"; 4316 }; 4317 4318 qspi_cs1: qspi-cs1 { 4319 pins = "gpio19"; 4320 function = "qspi_cs"; 4321 }; 4322 4323 qspi_data01: qspi-data01 { 4324 pins = "gpio12", "gpio13"; 4325 function = "qspi_data"; 4326 }; 4327 4328 qspi_data12: qspi-data12 { 4329 pins = "gpio16", "gpio17"; 4330 function = "qspi_data"; 4331 }; 4332 4333 qup_i2c0_data_clk: qup-i2c0-data-clk { 4334 pins = "gpio0", "gpio1"; 4335 function = "qup00"; 4336 }; 4337 4338 qup_i2c1_data_clk: qup-i2c1-data-clk { 4339 pins = "gpio4", "gpio5"; 4340 function = "qup01"; 4341 }; 4342 4343 qup_i2c2_data_clk: qup-i2c2-data-clk { 4344 pins = "gpio8", "gpio9"; 4345 function = "qup02"; 4346 }; 4347 4348 qup_i2c3_data_clk: qup-i2c3-data-clk { 4349 pins = "gpio12", "gpio13"; 4350 function = "qup03"; 4351 }; 4352 4353 qup_i2c4_data_clk: qup-i2c4-data-clk { 4354 pins = "gpio16", "gpio17"; 4355 function = "qup04"; 4356 }; 4357 4358 qup_i2c5_data_clk: qup-i2c5-data-clk { 4359 pins = "gpio20", "gpio21"; 4360 function = "qup05"; 4361 }; 4362 4363 qup_i2c6_data_clk: qup-i2c6-data-clk { 4364 pins = "gpio24", "gpio25"; 4365 function = "qup06"; 4366 }; 4367 4368 qup_i2c7_data_clk: qup-i2c7-data-clk { 4369 pins = "gpio28", "gpio29"; 4370 function = "qup07"; 4371 }; 4372 4373 qup_i2c8_data_clk: qup-i2c8-data-clk { 4374 pins = "gpio32", "gpio33"; 4375 function = "qup10"; 4376 }; 4377 4378 qup_i2c9_data_clk: qup-i2c9-data-clk { 4379 pins = "gpio36", "gpio37"; 4380 function = "qup11"; 4381 }; 4382 4383 qup_i2c10_data_clk: qup-i2c10-data-clk { 4384 pins = "gpio40", "gpio41"; 4385 function = "qup12"; 4386 }; 4387 4388 qup_i2c11_data_clk: qup-i2c11-data-clk { 4389 pins = "gpio44", "gpio45"; 4390 function = "qup13"; 4391 }; 4392 4393 qup_i2c12_data_clk: qup-i2c12-data-clk { 4394 pins = "gpio48", "gpio49"; 4395 function = "qup14"; 4396 }; 4397 4398 qup_i2c13_data_clk: qup-i2c13-data-clk { 4399 pins = "gpio52", "gpio53"; 4400 function = "qup15"; 4401 }; 4402 4403 qup_i2c14_data_clk: qup-i2c14-data-clk { 4404 pins = "gpio56", "gpio57"; 4405 function = "qup16"; 4406 }; 4407 4408 qup_i2c15_data_clk: qup-i2c15-data-clk { 4409 pins = "gpio60", "gpio61"; 4410 function = "qup17"; 4411 }; 4412 4413 qup_spi0_data_clk: qup-spi0-data-clk { 4414 pins = "gpio0", "gpio1", "gpio2"; 4415 function = "qup00"; 4416 }; 4417 4418 qup_spi0_cs: qup-spi0-cs { 4419 pins = "gpio3"; 4420 function = "qup00"; 4421 }; 4422 4423 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 4424 pins = "gpio3"; 4425 function = "gpio"; 4426 }; 4427 4428 qup_spi1_data_clk: qup-spi1-data-clk { 4429 pins = "gpio4", "gpio5", "gpio6"; 4430 function = "qup01"; 4431 }; 4432 4433 qup_spi1_cs: qup-spi1-cs { 4434 pins = "gpio7"; 4435 function = "qup01"; 4436 }; 4437 4438 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 4439 pins = "gpio7"; 4440 function = "gpio"; 4441 }; 4442 4443 qup_spi2_data_clk: qup-spi2-data-clk { 4444 pins = "gpio8", "gpio9", "gpio10"; 4445 function = "qup02"; 4446 }; 4447 4448 qup_spi2_cs: qup-spi2-cs { 4449 pins = "gpio11"; 4450 function = "qup02"; 4451 }; 4452 4453 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 4454 pins = "gpio11"; 4455 function = "gpio"; 4456 }; 4457 4458 qup_spi3_data_clk: qup-spi3-data-clk { 4459 pins = "gpio12", "gpio13", "gpio14"; 4460 function = "qup03"; 4461 }; 4462 4463 qup_spi3_cs: qup-spi3-cs { 4464 pins = "gpio15"; 4465 function = "qup03"; 4466 }; 4467 4468 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 4469 pins = "gpio15"; 4470 function = "gpio"; 4471 }; 4472 4473 qup_spi4_data_clk: qup-spi4-data-clk { 4474 pins = "gpio16", "gpio17", "gpio18"; 4475 function = "qup04"; 4476 }; 4477 4478 qup_spi4_cs: qup-spi4-cs { 4479 pins = "gpio19"; 4480 function = "qup04"; 4481 }; 4482 4483 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 4484 pins = "gpio19"; 4485 function = "gpio"; 4486 }; 4487 4488 qup_spi5_data_clk: qup-spi5-data-clk { 4489 pins = "gpio20", "gpio21", "gpio22"; 4490 function = "qup05"; 4491 }; 4492 4493 qup_spi5_cs: qup-spi5-cs { 4494 pins = "gpio23"; 4495 function = "qup05"; 4496 }; 4497 4498 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 4499 pins = "gpio23"; 4500 function = "gpio"; 4501 }; 4502 4503 qup_spi6_data_clk: qup-spi6-data-clk { 4504 pins = "gpio24", "gpio25", "gpio26"; 4505 function = "qup06"; 4506 }; 4507 4508 qup_spi6_cs: qup-spi6-cs { 4509 pins = "gpio27"; 4510 function = "qup06"; 4511 }; 4512 4513 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 4514 pins = "gpio27"; 4515 function = "gpio"; 4516 }; 4517 4518 qup_spi7_data_clk: qup-spi7-data-clk { 4519 pins = "gpio28", "gpio29", "gpio30"; 4520 function = "qup07"; 4521 }; 4522 4523 qup_spi7_cs: qup-spi7-cs { 4524 pins = "gpio31"; 4525 function = "qup07"; 4526 }; 4527 4528 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 4529 pins = "gpio31"; 4530 function = "gpio"; 4531 }; 4532 4533 qup_spi8_data_clk: qup-spi8-data-clk { 4534 pins = "gpio32", "gpio33", "gpio34"; 4535 function = "qup10"; 4536 }; 4537 4538 qup_spi8_cs: qup-spi8-cs { 4539 pins = "gpio35"; 4540 function = "qup10"; 4541 }; 4542 4543 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4544 pins = "gpio35"; 4545 function = "gpio"; 4546 }; 4547 4548 qup_spi9_data_clk: qup-spi9-data-clk { 4549 pins = "gpio36", "gpio37", "gpio38"; 4550 function = "qup11"; 4551 }; 4552 4553 qup_spi9_cs: qup-spi9-cs { 4554 pins = "gpio39"; 4555 function = "qup11"; 4556 }; 4557 4558 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4559 pins = "gpio39"; 4560 function = "gpio"; 4561 }; 4562 4563 qup_spi10_data_clk: qup-spi10-data-clk { 4564 pins = "gpio40", "gpio41", "gpio42"; 4565 function = "qup12"; 4566 }; 4567 4568 qup_spi10_cs: qup-spi10-cs { 4569 pins = "gpio43"; 4570 function = "qup12"; 4571 }; 4572 4573 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4574 pins = "gpio43"; 4575 function = "gpio"; 4576 }; 4577 4578 qup_spi11_data_clk: qup-spi11-data-clk { 4579 pins = "gpio44", "gpio45", "gpio46"; 4580 function = "qup13"; 4581 }; 4582 4583 qup_spi11_cs: qup-spi11-cs { 4584 pins = "gpio47"; 4585 function = "qup13"; 4586 }; 4587 4588 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4589 pins = "gpio47"; 4590 function = "gpio"; 4591 }; 4592 4593 qup_spi12_data_clk: qup-spi12-data-clk { 4594 pins = "gpio48", "gpio49", "gpio50"; 4595 function = "qup14"; 4596 }; 4597 4598 qup_spi12_cs: qup-spi12-cs { 4599 pins = "gpio51"; 4600 function = "qup14"; 4601 }; 4602 4603 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4604 pins = "gpio51"; 4605 function = "gpio"; 4606 }; 4607 4608 qup_spi13_data_clk: qup-spi13-data-clk { 4609 pins = "gpio52", "gpio53", "gpio54"; 4610 function = "qup15"; 4611 }; 4612 4613 qup_spi13_cs: qup-spi13-cs { 4614 pins = "gpio55"; 4615 function = "qup15"; 4616 }; 4617 4618 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4619 pins = "gpio55"; 4620 function = "gpio"; 4621 }; 4622 4623 qup_spi14_data_clk: qup-spi14-data-clk { 4624 pins = "gpio56", "gpio57", "gpio58"; 4625 function = "qup16"; 4626 }; 4627 4628 qup_spi14_cs: qup-spi14-cs { 4629 pins = "gpio59"; 4630 function = "qup16"; 4631 }; 4632 4633 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4634 pins = "gpio59"; 4635 function = "gpio"; 4636 }; 4637 4638 qup_spi15_data_clk: qup-spi15-data-clk { 4639 pins = "gpio60", "gpio61", "gpio62"; 4640 function = "qup17"; 4641 }; 4642 4643 qup_spi15_cs: qup-spi15-cs { 4644 pins = "gpio63"; 4645 function = "qup17"; 4646 }; 4647 4648 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4649 pins = "gpio63"; 4650 function = "gpio"; 4651 }; 4652 4653 qup_uart0_cts: qup-uart0-cts { 4654 pins = "gpio0"; 4655 function = "qup00"; 4656 }; 4657 4658 qup_uart0_rts: qup-uart0-rts { 4659 pins = "gpio1"; 4660 function = "qup00"; 4661 }; 4662 4663 qup_uart0_tx: qup-uart0-tx { 4664 pins = "gpio2"; 4665 function = "qup00"; 4666 }; 4667 4668 qup_uart0_rx: qup-uart0-rx { 4669 pins = "gpio3"; 4670 function = "qup00"; 4671 }; 4672 4673 qup_uart1_cts: qup-uart1-cts { 4674 pins = "gpio4"; 4675 function = "qup01"; 4676 }; 4677 4678 qup_uart1_rts: qup-uart1-rts { 4679 pins = "gpio5"; 4680 function = "qup01"; 4681 }; 4682 4683 qup_uart1_tx: qup-uart1-tx { 4684 pins = "gpio6"; 4685 function = "qup01"; 4686 }; 4687 4688 qup_uart1_rx: qup-uart1-rx { 4689 pins = "gpio7"; 4690 function = "qup01"; 4691 }; 4692 4693 qup_uart2_cts: qup-uart2-cts { 4694 pins = "gpio8"; 4695 function = "qup02"; 4696 }; 4697 4698 qup_uart2_rts: qup-uart2-rts { 4699 pins = "gpio9"; 4700 function = "qup02"; 4701 }; 4702 4703 qup_uart2_tx: qup-uart2-tx { 4704 pins = "gpio10"; 4705 function = "qup02"; 4706 }; 4707 4708 qup_uart2_rx: qup-uart2-rx { 4709 pins = "gpio11"; 4710 function = "qup02"; 4711 }; 4712 4713 qup_uart3_cts: qup-uart3-cts { 4714 pins = "gpio12"; 4715 function = "qup03"; 4716 }; 4717 4718 qup_uart3_rts: qup-uart3-rts { 4719 pins = "gpio13"; 4720 function = "qup03"; 4721 }; 4722 4723 qup_uart3_tx: qup-uart3-tx { 4724 pins = "gpio14"; 4725 function = "qup03"; 4726 }; 4727 4728 qup_uart3_rx: qup-uart3-rx { 4729 pins = "gpio15"; 4730 function = "qup03"; 4731 }; 4732 4733 qup_uart4_cts: qup-uart4-cts { 4734 pins = "gpio16"; 4735 function = "qup04"; 4736 }; 4737 4738 qup_uart4_rts: qup-uart4-rts { 4739 pins = "gpio17"; 4740 function = "qup04"; 4741 }; 4742 4743 qup_uart4_tx: qup-uart4-tx { 4744 pins = "gpio18"; 4745 function = "qup04"; 4746 }; 4747 4748 qup_uart4_rx: qup-uart4-rx { 4749 pins = "gpio19"; 4750 function = "qup04"; 4751 }; 4752 4753 qup_uart5_cts: qup-uart5-cts { 4754 pins = "gpio20"; 4755 function = "qup05"; 4756 }; 4757 4758 qup_uart5_rts: qup-uart5-rts { 4759 pins = "gpio21"; 4760 function = "qup05"; 4761 }; 4762 4763 qup_uart5_tx: qup-uart5-tx { 4764 pins = "gpio22"; 4765 function = "qup05"; 4766 }; 4767 4768 qup_uart5_rx: qup-uart5-rx { 4769 pins = "gpio23"; 4770 function = "qup05"; 4771 }; 4772 4773 qup_uart6_cts: qup-uart6-cts { 4774 pins = "gpio24"; 4775 function = "qup06"; 4776 }; 4777 4778 qup_uart6_rts: qup-uart6-rts { 4779 pins = "gpio25"; 4780 function = "qup06"; 4781 }; 4782 4783 qup_uart6_tx: qup-uart6-tx { 4784 pins = "gpio26"; 4785 function = "qup06"; 4786 }; 4787 4788 qup_uart6_rx: qup-uart6-rx { 4789 pins = "gpio27"; 4790 function = "qup06"; 4791 }; 4792 4793 qup_uart7_cts: qup-uart7-cts { 4794 pins = "gpio28"; 4795 function = "qup07"; 4796 }; 4797 4798 qup_uart7_rts: qup-uart7-rts { 4799 pins = "gpio29"; 4800 function = "qup07"; 4801 }; 4802 4803 qup_uart7_tx: qup-uart7-tx { 4804 pins = "gpio30"; 4805 function = "qup07"; 4806 }; 4807 4808 qup_uart7_rx: qup-uart7-rx { 4809 pins = "gpio31"; 4810 function = "qup07"; 4811 }; 4812 4813 qup_uart8_cts: qup-uart8-cts { 4814 pins = "gpio32"; 4815 function = "qup10"; 4816 }; 4817 4818 qup_uart8_rts: qup-uart8-rts { 4819 pins = "gpio33"; 4820 function = "qup10"; 4821 }; 4822 4823 qup_uart8_tx: qup-uart8-tx { 4824 pins = "gpio34"; 4825 function = "qup10"; 4826 }; 4827 4828 qup_uart8_rx: qup-uart8-rx { 4829 pins = "gpio35"; 4830 function = "qup10"; 4831 }; 4832 4833 qup_uart9_cts: qup-uart9-cts { 4834 pins = "gpio36"; 4835 function = "qup11"; 4836 }; 4837 4838 qup_uart9_rts: qup-uart9-rts { 4839 pins = "gpio37"; 4840 function = "qup11"; 4841 }; 4842 4843 qup_uart9_tx: qup-uart9-tx { 4844 pins = "gpio38"; 4845 function = "qup11"; 4846 }; 4847 4848 qup_uart9_rx: qup-uart9-rx { 4849 pins = "gpio39"; 4850 function = "qup11"; 4851 }; 4852 4853 qup_uart10_cts: qup-uart10-cts { 4854 pins = "gpio40"; 4855 function = "qup12"; 4856 }; 4857 4858 qup_uart10_rts: qup-uart10-rts { 4859 pins = "gpio41"; 4860 function = "qup12"; 4861 }; 4862 4863 qup_uart10_tx: qup-uart10-tx { 4864 pins = "gpio42"; 4865 function = "qup12"; 4866 }; 4867 4868 qup_uart10_rx: qup-uart10-rx { 4869 pins = "gpio43"; 4870 function = "qup12"; 4871 }; 4872 4873 qup_uart11_cts: qup-uart11-cts { 4874 pins = "gpio44"; 4875 function = "qup13"; 4876 }; 4877 4878 qup_uart11_rts: qup-uart11-rts { 4879 pins = "gpio45"; 4880 function = "qup13"; 4881 }; 4882 4883 qup_uart11_tx: qup-uart11-tx { 4884 pins = "gpio46"; 4885 function = "qup13"; 4886 }; 4887 4888 qup_uart11_rx: qup-uart11-rx { 4889 pins = "gpio47"; 4890 function = "qup13"; 4891 }; 4892 4893 qup_uart12_cts: qup-uart12-cts { 4894 pins = "gpio48"; 4895 function = "qup14"; 4896 }; 4897 4898 qup_uart12_rts: qup-uart12-rts { 4899 pins = "gpio49"; 4900 function = "qup14"; 4901 }; 4902 4903 qup_uart12_tx: qup-uart12-tx { 4904 pins = "gpio50"; 4905 function = "qup14"; 4906 }; 4907 4908 qup_uart12_rx: qup-uart12-rx { 4909 pins = "gpio51"; 4910 function = "qup14"; 4911 }; 4912 4913 qup_uart13_cts: qup-uart13-cts { 4914 pins = "gpio52"; 4915 function = "qup15"; 4916 }; 4917 4918 qup_uart13_rts: qup-uart13-rts { 4919 pins = "gpio53"; 4920 function = "qup15"; 4921 }; 4922 4923 qup_uart13_tx: qup-uart13-tx { 4924 pins = "gpio54"; 4925 function = "qup15"; 4926 }; 4927 4928 qup_uart13_rx: qup-uart13-rx { 4929 pins = "gpio55"; 4930 function = "qup15"; 4931 }; 4932 4933 qup_uart14_cts: qup-uart14-cts { 4934 pins = "gpio56"; 4935 function = "qup16"; 4936 }; 4937 4938 qup_uart14_rts: qup-uart14-rts { 4939 pins = "gpio57"; 4940 function = "qup16"; 4941 }; 4942 4943 qup_uart14_tx: qup-uart14-tx { 4944 pins = "gpio58"; 4945 function = "qup16"; 4946 }; 4947 4948 qup_uart14_rx: qup-uart14-rx { 4949 pins = "gpio59"; 4950 function = "qup16"; 4951 }; 4952 4953 qup_uart15_cts: qup-uart15-cts { 4954 pins = "gpio60"; 4955 function = "qup17"; 4956 }; 4957 4958 qup_uart15_rts: qup-uart15-rts { 4959 pins = "gpio61"; 4960 function = "qup17"; 4961 }; 4962 4963 qup_uart15_tx: qup-uart15-tx { 4964 pins = "gpio62"; 4965 function = "qup17"; 4966 }; 4967 4968 qup_uart15_rx: qup-uart15-rx { 4969 pins = "gpio63"; 4970 function = "qup17"; 4971 }; 4972 4973 sdc1_clk: sdc1-clk { 4974 pins = "sdc1_clk"; 4975 }; 4976 4977 sdc1_cmd: sdc1-cmd { 4978 pins = "sdc1_cmd"; 4979 }; 4980 4981 sdc1_data: sdc1-data { 4982 pins = "sdc1_data"; 4983 }; 4984 4985 sdc1_rclk: sdc1-rclk { 4986 pins = "sdc1_rclk"; 4987 }; 4988 4989 sdc1_clk_sleep: sdc1-clk-sleep { 4990 pins = "sdc1_clk"; 4991 drive-strength = <2>; 4992 bias-bus-hold; 4993 }; 4994 4995 sdc1_cmd_sleep: sdc1-cmd-sleep { 4996 pins = "sdc1_cmd"; 4997 drive-strength = <2>; 4998 bias-bus-hold; 4999 }; 5000 5001 sdc1_data_sleep: sdc1-data-sleep { 5002 pins = "sdc1_data"; 5003 drive-strength = <2>; 5004 bias-bus-hold; 5005 }; 5006 5007 sdc1_rclk_sleep: sdc1-rclk-sleep { 5008 pins = "sdc1_rclk"; 5009 drive-strength = <2>; 5010 bias-bus-hold; 5011 }; 5012 5013 sdc2_clk: sdc2-clk { 5014 pins = "sdc2_clk"; 5015 }; 5016 5017 sdc2_cmd: sdc2-cmd { 5018 pins = "sdc2_cmd"; 5019 }; 5020 5021 sdc2_data: sdc2-data { 5022 pins = "sdc2_data"; 5023 }; 5024 5025 sdc2_clk_sleep: sdc2-clk-sleep { 5026 pins = "sdc2_clk"; 5027 drive-strength = <2>; 5028 bias-bus-hold; 5029 }; 5030 5031 sdc2_cmd_sleep: sdc2-cmd-sleep { 5032 pins = "sdc2_cmd"; 5033 drive-strength = <2>; 5034 bias-bus-hold; 5035 }; 5036 5037 sdc2_data_sleep: sdc2-data-sleep { 5038 pins = "sdc2_data"; 5039 drive-strength = <2>; 5040 bias-bus-hold; 5041 }; 5042 }; 5043 5044 sram@146a5000 { 5045 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5046 reg = <0 0x146a5000 0 0x6000>; 5047 5048 #address-cells = <1>; 5049 #size-cells = <1>; 5050 5051 ranges = <0 0 0x146a5000 0x6000>; 5052 5053 pil-reloc@594c { 5054 compatible = "qcom,pil-reloc-info"; 5055 reg = <0x594c 0xc8>; 5056 }; 5057 }; 5058 5059 apps_smmu: iommu@15000000 { 5060 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5061 reg = <0 0x15000000 0 0x100000>; 5062 #iommu-cells = <2>; 5063 #global-interrupts = <1>; 5064 dma-coherent; 5065 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5146 }; 5147 5148 intc: interrupt-controller@17a00000 { 5149 compatible = "arm,gic-v3"; 5150 #address-cells = <2>; 5151 #size-cells = <2>; 5152 ranges; 5153 #interrupt-cells = <3>; 5154 interrupt-controller; 5155 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5156 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5157 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5158 5159 gic-its@17a40000 { 5160 compatible = "arm,gic-v3-its"; 5161 msi-controller; 5162 #msi-cells = <1>; 5163 reg = <0 0x17a40000 0 0x20000>; 5164 status = "disabled"; 5165 }; 5166 }; 5167 5168 watchdog@17c10000 { 5169 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5170 reg = <0 0x17c10000 0 0x1000>; 5171 clocks = <&sleep_clk>; 5172 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5173 }; 5174 5175 timer@17c20000 { 5176 #address-cells = <1>; 5177 #size-cells = <1>; 5178 ranges = <0 0 0 0x20000000>; 5179 compatible = "arm,armv7-timer-mem"; 5180 reg = <0 0x17c20000 0 0x1000>; 5181 5182 frame@17c21000 { 5183 frame-number = <0>; 5184 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5186 reg = <0x17c21000 0x1000>, 5187 <0x17c22000 0x1000>; 5188 }; 5189 5190 frame@17c23000 { 5191 frame-number = <1>; 5192 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5193 reg = <0x17c23000 0x1000>; 5194 status = "disabled"; 5195 }; 5196 5197 frame@17c25000 { 5198 frame-number = <2>; 5199 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5200 reg = <0x17c25000 0x1000>; 5201 status = "disabled"; 5202 }; 5203 5204 frame@17c27000 { 5205 frame-number = <3>; 5206 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5207 reg = <0x17c27000 0x1000>; 5208 status = "disabled"; 5209 }; 5210 5211 frame@17c29000 { 5212 frame-number = <4>; 5213 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5214 reg = <0x17c29000 0x1000>; 5215 status = "disabled"; 5216 }; 5217 5218 frame@17c2b000 { 5219 frame-number = <5>; 5220 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5221 reg = <0x17c2b000 0x1000>; 5222 status = "disabled"; 5223 }; 5224 5225 frame@17c2d000 { 5226 frame-number = <6>; 5227 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5228 reg = <0x17c2d000 0x1000>; 5229 status = "disabled"; 5230 }; 5231 }; 5232 5233 apps_rsc: rsc@18200000 { 5234 compatible = "qcom,rpmh-rsc"; 5235 reg = <0 0x18200000 0 0x10000>, 5236 <0 0x18210000 0 0x10000>, 5237 <0 0x18220000 0 0x10000>; 5238 reg-names = "drv-0", "drv-1", "drv-2"; 5239 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5240 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5241 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5242 qcom,tcs-offset = <0xd00>; 5243 qcom,drv-id = <2>; 5244 qcom,tcs-config = <ACTIVE_TCS 2>, 5245 <SLEEP_TCS 3>, 5246 <WAKE_TCS 3>, 5247 <CONTROL_TCS 1>; 5248 5249 apps_bcm_voter: bcm-voter { 5250 compatible = "qcom,bcm-voter"; 5251 }; 5252 5253 rpmhpd: power-controller { 5254 compatible = "qcom,sc7280-rpmhpd"; 5255 #power-domain-cells = <1>; 5256 operating-points-v2 = <&rpmhpd_opp_table>; 5257 5258 rpmhpd_opp_table: opp-table { 5259 compatible = "operating-points-v2"; 5260 5261 rpmhpd_opp_ret: opp1 { 5262 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5263 }; 5264 5265 rpmhpd_opp_low_svs: opp2 { 5266 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5267 }; 5268 5269 rpmhpd_opp_svs: opp3 { 5270 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5271 }; 5272 5273 rpmhpd_opp_svs_l1: opp4 { 5274 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5275 }; 5276 5277 rpmhpd_opp_svs_l2: opp5 { 5278 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5279 }; 5280 5281 rpmhpd_opp_nom: opp6 { 5282 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5283 }; 5284 5285 rpmhpd_opp_nom_l1: opp7 { 5286 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5287 }; 5288 5289 rpmhpd_opp_turbo: opp8 { 5290 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5291 }; 5292 5293 rpmhpd_opp_turbo_l1: opp9 { 5294 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5295 }; 5296 }; 5297 }; 5298 5299 rpmhcc: clock-controller { 5300 compatible = "qcom,sc7280-rpmh-clk"; 5301 clocks = <&xo_board>; 5302 clock-names = "xo"; 5303 #clock-cells = <1>; 5304 }; 5305 }; 5306 5307 epss_l3: interconnect@18590000 { 5308 compatible = "qcom,sc7280-epss-l3"; 5309 reg = <0 0x18590000 0 0x1000>; 5310 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5311 clock-names = "xo", "alternate"; 5312 #interconnect-cells = <1>; 5313 }; 5314 5315 cpufreq_hw: cpufreq@18591000 { 5316 compatible = "qcom,cpufreq-epss"; 5317 reg = <0 0x18591000 0 0x1000>, 5318 <0 0x18592000 0 0x1000>, 5319 <0 0x18593000 0 0x1000>; 5320 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5321 clock-names = "xo", "alternate"; 5322 #freq-domain-cells = <1>; 5323 }; 5324 }; 5325 5326 thermal_zones: thermal-zones { 5327 cpu0-thermal { 5328 polling-delay-passive = <250>; 5329 polling-delay = <0>; 5330 5331 thermal-sensors = <&tsens0 1>; 5332 5333 trips { 5334 cpu0_alert0: trip-point0 { 5335 temperature = <90000>; 5336 hysteresis = <2000>; 5337 type = "passive"; 5338 }; 5339 5340 cpu0_alert1: trip-point1 { 5341 temperature = <95000>; 5342 hysteresis = <2000>; 5343 type = "passive"; 5344 }; 5345 5346 cpu0_crit: cpu-crit { 5347 temperature = <110000>; 5348 hysteresis = <0>; 5349 type = "critical"; 5350 }; 5351 }; 5352 5353 cooling-maps { 5354 map0 { 5355 trip = <&cpu0_alert0>; 5356 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5357 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5358 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5359 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5360 }; 5361 map1 { 5362 trip = <&cpu0_alert1>; 5363 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5364 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5365 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5366 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5367 }; 5368 }; 5369 }; 5370 5371 cpu1-thermal { 5372 polling-delay-passive = <250>; 5373 polling-delay = <0>; 5374 5375 thermal-sensors = <&tsens0 2>; 5376 5377 trips { 5378 cpu1_alert0: trip-point0 { 5379 temperature = <90000>; 5380 hysteresis = <2000>; 5381 type = "passive"; 5382 }; 5383 5384 cpu1_alert1: trip-point1 { 5385 temperature = <95000>; 5386 hysteresis = <2000>; 5387 type = "passive"; 5388 }; 5389 5390 cpu1_crit: cpu-crit { 5391 temperature = <110000>; 5392 hysteresis = <0>; 5393 type = "critical"; 5394 }; 5395 }; 5396 5397 cooling-maps { 5398 map0 { 5399 trip = <&cpu1_alert0>; 5400 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5401 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5402 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5403 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5404 }; 5405 map1 { 5406 trip = <&cpu1_alert1>; 5407 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5408 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5409 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5411 }; 5412 }; 5413 }; 5414 5415 cpu2-thermal { 5416 polling-delay-passive = <250>; 5417 polling-delay = <0>; 5418 5419 thermal-sensors = <&tsens0 3>; 5420 5421 trips { 5422 cpu2_alert0: trip-point0 { 5423 temperature = <90000>; 5424 hysteresis = <2000>; 5425 type = "passive"; 5426 }; 5427 5428 cpu2_alert1: trip-point1 { 5429 temperature = <95000>; 5430 hysteresis = <2000>; 5431 type = "passive"; 5432 }; 5433 5434 cpu2_crit: cpu-crit { 5435 temperature = <110000>; 5436 hysteresis = <0>; 5437 type = "critical"; 5438 }; 5439 }; 5440 5441 cooling-maps { 5442 map0 { 5443 trip = <&cpu2_alert0>; 5444 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5445 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5446 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5447 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5448 }; 5449 map1 { 5450 trip = <&cpu2_alert1>; 5451 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5452 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5453 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5455 }; 5456 }; 5457 }; 5458 5459 cpu3-thermal { 5460 polling-delay-passive = <250>; 5461 polling-delay = <0>; 5462 5463 thermal-sensors = <&tsens0 4>; 5464 5465 trips { 5466 cpu3_alert0: trip-point0 { 5467 temperature = <90000>; 5468 hysteresis = <2000>; 5469 type = "passive"; 5470 }; 5471 5472 cpu3_alert1: trip-point1 { 5473 temperature = <95000>; 5474 hysteresis = <2000>; 5475 type = "passive"; 5476 }; 5477 5478 cpu3_crit: cpu-crit { 5479 temperature = <110000>; 5480 hysteresis = <0>; 5481 type = "critical"; 5482 }; 5483 }; 5484 5485 cooling-maps { 5486 map0 { 5487 trip = <&cpu3_alert0>; 5488 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5489 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5490 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5491 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5492 }; 5493 map1 { 5494 trip = <&cpu3_alert1>; 5495 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5496 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5497 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5499 }; 5500 }; 5501 }; 5502 5503 cpu4-thermal { 5504 polling-delay-passive = <250>; 5505 polling-delay = <0>; 5506 5507 thermal-sensors = <&tsens0 7>; 5508 5509 trips { 5510 cpu4_alert0: trip-point0 { 5511 temperature = <90000>; 5512 hysteresis = <2000>; 5513 type = "passive"; 5514 }; 5515 5516 cpu4_alert1: trip-point1 { 5517 temperature = <95000>; 5518 hysteresis = <2000>; 5519 type = "passive"; 5520 }; 5521 5522 cpu4_crit: cpu-crit { 5523 temperature = <110000>; 5524 hysteresis = <0>; 5525 type = "critical"; 5526 }; 5527 }; 5528 5529 cooling-maps { 5530 map0 { 5531 trip = <&cpu4_alert0>; 5532 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5533 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5534 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5536 }; 5537 map1 { 5538 trip = <&cpu4_alert1>; 5539 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5540 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5541 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5543 }; 5544 }; 5545 }; 5546 5547 cpu5-thermal { 5548 polling-delay-passive = <250>; 5549 polling-delay = <0>; 5550 5551 thermal-sensors = <&tsens0 8>; 5552 5553 trips { 5554 cpu5_alert0: trip-point0 { 5555 temperature = <90000>; 5556 hysteresis = <2000>; 5557 type = "passive"; 5558 }; 5559 5560 cpu5_alert1: trip-point1 { 5561 temperature = <95000>; 5562 hysteresis = <2000>; 5563 type = "passive"; 5564 }; 5565 5566 cpu5_crit: cpu-crit { 5567 temperature = <110000>; 5568 hysteresis = <0>; 5569 type = "critical"; 5570 }; 5571 }; 5572 5573 cooling-maps { 5574 map0 { 5575 trip = <&cpu5_alert0>; 5576 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5577 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5578 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5580 }; 5581 map1 { 5582 trip = <&cpu5_alert1>; 5583 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5584 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5585 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5587 }; 5588 }; 5589 }; 5590 5591 cpu6-thermal { 5592 polling-delay-passive = <250>; 5593 polling-delay = <0>; 5594 5595 thermal-sensors = <&tsens0 9>; 5596 5597 trips { 5598 cpu6_alert0: trip-point0 { 5599 temperature = <90000>; 5600 hysteresis = <2000>; 5601 type = "passive"; 5602 }; 5603 5604 cpu6_alert1: trip-point1 { 5605 temperature = <95000>; 5606 hysteresis = <2000>; 5607 type = "passive"; 5608 }; 5609 5610 cpu6_crit: cpu-crit { 5611 temperature = <110000>; 5612 hysteresis = <0>; 5613 type = "critical"; 5614 }; 5615 }; 5616 5617 cooling-maps { 5618 map0 { 5619 trip = <&cpu6_alert0>; 5620 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5621 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5622 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5623 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5624 }; 5625 map1 { 5626 trip = <&cpu6_alert1>; 5627 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5628 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5629 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5631 }; 5632 }; 5633 }; 5634 5635 cpu7-thermal { 5636 polling-delay-passive = <250>; 5637 polling-delay = <0>; 5638 5639 thermal-sensors = <&tsens0 10>; 5640 5641 trips { 5642 cpu7_alert0: trip-point0 { 5643 temperature = <90000>; 5644 hysteresis = <2000>; 5645 type = "passive"; 5646 }; 5647 5648 cpu7_alert1: trip-point1 { 5649 temperature = <95000>; 5650 hysteresis = <2000>; 5651 type = "passive"; 5652 }; 5653 5654 cpu7_crit: cpu-crit { 5655 temperature = <110000>; 5656 hysteresis = <0>; 5657 type = "critical"; 5658 }; 5659 }; 5660 5661 cooling-maps { 5662 map0 { 5663 trip = <&cpu7_alert0>; 5664 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5665 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5666 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5667 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5668 }; 5669 map1 { 5670 trip = <&cpu7_alert1>; 5671 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5672 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5673 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5675 }; 5676 }; 5677 }; 5678 5679 cpu8-thermal { 5680 polling-delay-passive = <250>; 5681 polling-delay = <0>; 5682 5683 thermal-sensors = <&tsens0 11>; 5684 5685 trips { 5686 cpu8_alert0: trip-point0 { 5687 temperature = <90000>; 5688 hysteresis = <2000>; 5689 type = "passive"; 5690 }; 5691 5692 cpu8_alert1: trip-point1 { 5693 temperature = <95000>; 5694 hysteresis = <2000>; 5695 type = "passive"; 5696 }; 5697 5698 cpu8_crit: cpu-crit { 5699 temperature = <110000>; 5700 hysteresis = <0>; 5701 type = "critical"; 5702 }; 5703 }; 5704 5705 cooling-maps { 5706 map0 { 5707 trip = <&cpu8_alert0>; 5708 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5710 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5712 }; 5713 map1 { 5714 trip = <&cpu8_alert1>; 5715 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5716 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5717 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5719 }; 5720 }; 5721 }; 5722 5723 cpu9-thermal { 5724 polling-delay-passive = <250>; 5725 polling-delay = <0>; 5726 5727 thermal-sensors = <&tsens0 12>; 5728 5729 trips { 5730 cpu9_alert0: trip-point0 { 5731 temperature = <90000>; 5732 hysteresis = <2000>; 5733 type = "passive"; 5734 }; 5735 5736 cpu9_alert1: trip-point1 { 5737 temperature = <95000>; 5738 hysteresis = <2000>; 5739 type = "passive"; 5740 }; 5741 5742 cpu9_crit: cpu-crit { 5743 temperature = <110000>; 5744 hysteresis = <0>; 5745 type = "critical"; 5746 }; 5747 }; 5748 5749 cooling-maps { 5750 map0 { 5751 trip = <&cpu9_alert0>; 5752 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5754 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5756 }; 5757 map1 { 5758 trip = <&cpu9_alert1>; 5759 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5760 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5761 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5763 }; 5764 }; 5765 }; 5766 5767 cpu10-thermal { 5768 polling-delay-passive = <250>; 5769 polling-delay = <0>; 5770 5771 thermal-sensors = <&tsens0 13>; 5772 5773 trips { 5774 cpu10_alert0: trip-point0 { 5775 temperature = <90000>; 5776 hysteresis = <2000>; 5777 type = "passive"; 5778 }; 5779 5780 cpu10_alert1: trip-point1 { 5781 temperature = <95000>; 5782 hysteresis = <2000>; 5783 type = "passive"; 5784 }; 5785 5786 cpu10_crit: cpu-crit { 5787 temperature = <110000>; 5788 hysteresis = <0>; 5789 type = "critical"; 5790 }; 5791 }; 5792 5793 cooling-maps { 5794 map0 { 5795 trip = <&cpu10_alert0>; 5796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5800 }; 5801 map1 { 5802 trip = <&cpu10_alert1>; 5803 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5804 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5805 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5807 }; 5808 }; 5809 }; 5810 5811 cpu11-thermal { 5812 polling-delay-passive = <250>; 5813 polling-delay = <0>; 5814 5815 thermal-sensors = <&tsens0 14>; 5816 5817 trips { 5818 cpu11_alert0: trip-point0 { 5819 temperature = <90000>; 5820 hysteresis = <2000>; 5821 type = "passive"; 5822 }; 5823 5824 cpu11_alert1: trip-point1 { 5825 temperature = <95000>; 5826 hysteresis = <2000>; 5827 type = "passive"; 5828 }; 5829 5830 cpu11_crit: cpu-crit { 5831 temperature = <110000>; 5832 hysteresis = <0>; 5833 type = "critical"; 5834 }; 5835 }; 5836 5837 cooling-maps { 5838 map0 { 5839 trip = <&cpu11_alert0>; 5840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5841 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5842 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5844 }; 5845 map1 { 5846 trip = <&cpu11_alert1>; 5847 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5848 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5849 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5851 }; 5852 }; 5853 }; 5854 5855 aoss0-thermal { 5856 polling-delay-passive = <0>; 5857 polling-delay = <0>; 5858 5859 thermal-sensors = <&tsens0 0>; 5860 5861 trips { 5862 aoss0_alert0: trip-point0 { 5863 temperature = <90000>; 5864 hysteresis = <2000>; 5865 type = "hot"; 5866 }; 5867 5868 aoss0_crit: aoss0-crit { 5869 temperature = <110000>; 5870 hysteresis = <0>; 5871 type = "critical"; 5872 }; 5873 }; 5874 }; 5875 5876 aoss1-thermal { 5877 polling-delay-passive = <0>; 5878 polling-delay = <0>; 5879 5880 thermal-sensors = <&tsens1 0>; 5881 5882 trips { 5883 aoss1_alert0: trip-point0 { 5884 temperature = <90000>; 5885 hysteresis = <2000>; 5886 type = "hot"; 5887 }; 5888 5889 aoss1_crit: aoss1-crit { 5890 temperature = <110000>; 5891 hysteresis = <0>; 5892 type = "critical"; 5893 }; 5894 }; 5895 }; 5896 5897 cpuss0-thermal { 5898 polling-delay-passive = <0>; 5899 polling-delay = <0>; 5900 5901 thermal-sensors = <&tsens0 5>; 5902 5903 trips { 5904 cpuss0_alert0: trip-point0 { 5905 temperature = <90000>; 5906 hysteresis = <2000>; 5907 type = "hot"; 5908 }; 5909 cpuss0_crit: cluster0-crit { 5910 temperature = <110000>; 5911 hysteresis = <0>; 5912 type = "critical"; 5913 }; 5914 }; 5915 }; 5916 5917 cpuss1-thermal { 5918 polling-delay-passive = <0>; 5919 polling-delay = <0>; 5920 5921 thermal-sensors = <&tsens0 6>; 5922 5923 trips { 5924 cpuss1_alert0: trip-point0 { 5925 temperature = <90000>; 5926 hysteresis = <2000>; 5927 type = "hot"; 5928 }; 5929 cpuss1_crit: cluster0-crit { 5930 temperature = <110000>; 5931 hysteresis = <0>; 5932 type = "critical"; 5933 }; 5934 }; 5935 }; 5936 5937 gpuss0-thermal { 5938 polling-delay-passive = <100>; 5939 polling-delay = <0>; 5940 5941 thermal-sensors = <&tsens1 1>; 5942 5943 trips { 5944 gpuss0_alert0: trip-point0 { 5945 temperature = <95000>; 5946 hysteresis = <2000>; 5947 type = "passive"; 5948 }; 5949 5950 gpuss0_crit: gpuss0-crit { 5951 temperature = <110000>; 5952 hysteresis = <0>; 5953 type = "critical"; 5954 }; 5955 }; 5956 5957 cooling-maps { 5958 map0 { 5959 trip = <&gpuss0_alert0>; 5960 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5961 }; 5962 }; 5963 }; 5964 5965 gpuss1-thermal { 5966 polling-delay-passive = <100>; 5967 polling-delay = <0>; 5968 5969 thermal-sensors = <&tsens1 2>; 5970 5971 trips { 5972 gpuss1_alert0: trip-point0 { 5973 temperature = <95000>; 5974 hysteresis = <2000>; 5975 type = "passive"; 5976 }; 5977 5978 gpuss1_crit: gpuss1-crit { 5979 temperature = <110000>; 5980 hysteresis = <0>; 5981 type = "critical"; 5982 }; 5983 }; 5984 5985 cooling-maps { 5986 map0 { 5987 trip = <&gpuss1_alert0>; 5988 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5989 }; 5990 }; 5991 }; 5992 5993 nspss0-thermal { 5994 polling-delay-passive = <0>; 5995 polling-delay = <0>; 5996 5997 thermal-sensors = <&tsens1 3>; 5998 5999 trips { 6000 nspss0_alert0: trip-point0 { 6001 temperature = <90000>; 6002 hysteresis = <2000>; 6003 type = "hot"; 6004 }; 6005 6006 nspss0_crit: nspss0-crit { 6007 temperature = <110000>; 6008 hysteresis = <0>; 6009 type = "critical"; 6010 }; 6011 }; 6012 }; 6013 6014 nspss1-thermal { 6015 polling-delay-passive = <0>; 6016 polling-delay = <0>; 6017 6018 thermal-sensors = <&tsens1 4>; 6019 6020 trips { 6021 nspss1_alert0: trip-point0 { 6022 temperature = <90000>; 6023 hysteresis = <2000>; 6024 type = "hot"; 6025 }; 6026 6027 nspss1_crit: nspss1-crit { 6028 temperature = <110000>; 6029 hysteresis = <0>; 6030 type = "critical"; 6031 }; 6032 }; 6033 }; 6034 6035 video-thermal { 6036 polling-delay-passive = <0>; 6037 polling-delay = <0>; 6038 6039 thermal-sensors = <&tsens1 5>; 6040 6041 trips { 6042 video_alert0: trip-point0 { 6043 temperature = <90000>; 6044 hysteresis = <2000>; 6045 type = "hot"; 6046 }; 6047 6048 video_crit: video-crit { 6049 temperature = <110000>; 6050 hysteresis = <0>; 6051 type = "critical"; 6052 }; 6053 }; 6054 }; 6055 6056 ddr-thermal { 6057 polling-delay-passive = <0>; 6058 polling-delay = <0>; 6059 6060 thermal-sensors = <&tsens1 6>; 6061 6062 trips { 6063 ddr_alert0: trip-point0 { 6064 temperature = <90000>; 6065 hysteresis = <2000>; 6066 type = "hot"; 6067 }; 6068 6069 ddr_crit: ddr-crit { 6070 temperature = <110000>; 6071 hysteresis = <0>; 6072 type = "critical"; 6073 }; 6074 }; 6075 }; 6076 6077 mdmss0-thermal { 6078 polling-delay-passive = <0>; 6079 polling-delay = <0>; 6080 6081 thermal-sensors = <&tsens1 7>; 6082 6083 trips { 6084 mdmss0_alert0: trip-point0 { 6085 temperature = <90000>; 6086 hysteresis = <2000>; 6087 type = "hot"; 6088 }; 6089 6090 mdmss0_crit: mdmss0-crit { 6091 temperature = <110000>; 6092 hysteresis = <0>; 6093 type = "critical"; 6094 }; 6095 }; 6096 }; 6097 6098 mdmss1-thermal { 6099 polling-delay-passive = <0>; 6100 polling-delay = <0>; 6101 6102 thermal-sensors = <&tsens1 8>; 6103 6104 trips { 6105 mdmss1_alert0: trip-point0 { 6106 temperature = <90000>; 6107 hysteresis = <2000>; 6108 type = "hot"; 6109 }; 6110 6111 mdmss1_crit: mdmss1-crit { 6112 temperature = <110000>; 6113 hysteresis = <0>; 6114 type = "critical"; 6115 }; 6116 }; 6117 }; 6118 6119 mdmss2-thermal { 6120 polling-delay-passive = <0>; 6121 polling-delay = <0>; 6122 6123 thermal-sensors = <&tsens1 9>; 6124 6125 trips { 6126 mdmss2_alert0: trip-point0 { 6127 temperature = <90000>; 6128 hysteresis = <2000>; 6129 type = "hot"; 6130 }; 6131 6132 mdmss2_crit: mdmss2-crit { 6133 temperature = <110000>; 6134 hysteresis = <0>; 6135 type = "critical"; 6136 }; 6137 }; 6138 }; 6139 6140 mdmss3-thermal { 6141 polling-delay-passive = <0>; 6142 polling-delay = <0>; 6143 6144 thermal-sensors = <&tsens1 10>; 6145 6146 trips { 6147 mdmss3_alert0: trip-point0 { 6148 temperature = <90000>; 6149 hysteresis = <2000>; 6150 type = "hot"; 6151 }; 6152 6153 mdmss3_crit: mdmss3-crit { 6154 temperature = <110000>; 6155 hysteresis = <0>; 6156 type = "critical"; 6157 }; 6158 }; 6159 }; 6160 6161 camera0-thermal { 6162 polling-delay-passive = <0>; 6163 polling-delay = <0>; 6164 6165 thermal-sensors = <&tsens1 11>; 6166 6167 trips { 6168 camera0_alert0: trip-point0 { 6169 temperature = <90000>; 6170 hysteresis = <2000>; 6171 type = "hot"; 6172 }; 6173 6174 camera0_crit: camera0-crit { 6175 temperature = <110000>; 6176 hysteresis = <0>; 6177 type = "critical"; 6178 }; 6179 }; 6180 }; 6181 }; 6182 6183 timer { 6184 compatible = "arm,armv8-timer"; 6185 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6186 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6187 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6188 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6189 }; 6190}; 6191