1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 aliases { 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 i2c12 = &i2c12; 49 i2c13 = &i2c13; 50 i2c14 = &i2c14; 51 i2c15 = &i2c15; 52 mmc1 = &sdhc_1; 53 mmc2 = &sdhc_2; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 }; 71 72 clocks { 73 xo_board: xo-board { 74 compatible = "fixed-clock"; 75 clock-frequency = <76800000>; 76 #clock-cells = <0>; 77 }; 78 79 sleep_clk: sleep-clk { 80 compatible = "fixed-clock"; 81 clock-frequency = <32000>; 82 #clock-cells = <0>; 83 }; 84 }; 85 86 reserved-memory { 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 wlan_ce_mem: memory@4cd000 { 92 no-map; 93 reg = <0x0 0x004cd000 0x0 0x1000>; 94 }; 95 96 hyp_mem: memory@80000000 { 97 reg = <0x0 0x80000000 0x0 0x600000>; 98 no-map; 99 }; 100 101 xbl_mem: memory@80600000 { 102 reg = <0x0 0x80600000 0x0 0x200000>; 103 no-map; 104 }; 105 106 aop_mem: memory@80800000 { 107 reg = <0x0 0x80800000 0x0 0x60000>; 108 no-map; 109 }; 110 111 aop_cmd_db_mem: memory@80860000 { 112 reg = <0x0 0x80860000 0x0 0x20000>; 113 compatible = "qcom,cmd-db"; 114 no-map; 115 }; 116 117 reserved_xbl_uefi_log: memory@80880000 { 118 reg = <0x0 0x80884000 0x0 0x10000>; 119 no-map; 120 }; 121 122 sec_apps_mem: memory@808ff000 { 123 reg = <0x0 0x808ff000 0x0 0x1000>; 124 no-map; 125 }; 126 127 smem_mem: memory@80900000 { 128 reg = <0x0 0x80900000 0x0 0x200000>; 129 no-map; 130 }; 131 132 cpucp_mem: memory@80b00000 { 133 no-map; 134 reg = <0x0 0x80b00000 0x0 0x100000>; 135 }; 136 137 wlan_fw_mem: memory@80c00000 { 138 reg = <0x0 0x80c00000 0x0 0xc00000>; 139 no-map; 140 }; 141 142 video_mem: memory@8b200000 { 143 reg = <0x0 0x8b200000 0x0 0x500000>; 144 no-map; 145 }; 146 147 ipa_fw_mem: memory@8b700000 { 148 reg = <0 0x8b700000 0 0x10000>; 149 no-map; 150 }; 151 152 rmtfs_mem: memory@9c900000 { 153 compatible = "qcom,rmtfs-mem"; 154 reg = <0x0 0x9c900000 0x0 0x280000>; 155 no-map; 156 157 qcom,client-id = <1>; 158 qcom,vmid = <15>; 159 }; 160 }; 161 162 cpus { 163 #address-cells = <2>; 164 #size-cells = <0>; 165 166 CPU0: cpu@0 { 167 device_type = "cpu"; 168 compatible = "arm,kryo"; 169 reg = <0x0 0x0>; 170 enable-method = "psci"; 171 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 172 &LITTLE_CPU_SLEEP_1 173 &CLUSTER_SLEEP_0>; 174 next-level-cache = <&L2_0>; 175 operating-points-v2 = <&cpu0_opp_table>; 176 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 177 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 178 qcom,freq-domain = <&cpufreq_hw 0>; 179 #cooling-cells = <2>; 180 L2_0: l2-cache { 181 compatible = "cache"; 182 next-level-cache = <&L3_0>; 183 L3_0: l3-cache { 184 compatible = "cache"; 185 }; 186 }; 187 }; 188 189 CPU1: cpu@100 { 190 device_type = "cpu"; 191 compatible = "arm,kryo"; 192 reg = <0x0 0x100>; 193 enable-method = "psci"; 194 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 195 &LITTLE_CPU_SLEEP_1 196 &CLUSTER_SLEEP_0>; 197 next-level-cache = <&L2_100>; 198 operating-points-v2 = <&cpu0_opp_table>; 199 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 200 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 #cooling-cells = <2>; 203 L2_100: l2-cache { 204 compatible = "cache"; 205 next-level-cache = <&L3_0>; 206 }; 207 }; 208 209 CPU2: cpu@200 { 210 device_type = "cpu"; 211 compatible = "arm,kryo"; 212 reg = <0x0 0x200>; 213 enable-method = "psci"; 214 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 215 &LITTLE_CPU_SLEEP_1 216 &CLUSTER_SLEEP_0>; 217 next-level-cache = <&L2_200>; 218 operating-points-v2 = <&cpu0_opp_table>; 219 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 220 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 #cooling-cells = <2>; 223 L2_200: l2-cache { 224 compatible = "cache"; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU3: cpu@300 { 230 device_type = "cpu"; 231 compatible = "arm,kryo"; 232 reg = <0x0 0x300>; 233 enable-method = "psci"; 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 235 &LITTLE_CPU_SLEEP_1 236 &CLUSTER_SLEEP_0>; 237 next-level-cache = <&L2_300>; 238 operating-points-v2 = <&cpu0_opp_table>; 239 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 240 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 qcom,freq-domain = <&cpufreq_hw 0>; 242 #cooling-cells = <2>; 243 L2_300: l2-cache { 244 compatible = "cache"; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 CPU4: cpu@400 { 250 device_type = "cpu"; 251 compatible = "arm,kryo"; 252 reg = <0x0 0x400>; 253 enable-method = "psci"; 254 cpu-idle-states = <&BIG_CPU_SLEEP_0 255 &BIG_CPU_SLEEP_1 256 &CLUSTER_SLEEP_0>; 257 next-level-cache = <&L2_400>; 258 operating-points-v2 = <&cpu4_opp_table>; 259 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 260 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 261 qcom,freq-domain = <&cpufreq_hw 1>; 262 #cooling-cells = <2>; 263 L2_400: l2-cache { 264 compatible = "cache"; 265 next-level-cache = <&L3_0>; 266 }; 267 }; 268 269 CPU5: cpu@500 { 270 device_type = "cpu"; 271 compatible = "arm,kryo"; 272 reg = <0x0 0x500>; 273 enable-method = "psci"; 274 cpu-idle-states = <&BIG_CPU_SLEEP_0 275 &BIG_CPU_SLEEP_1 276 &CLUSTER_SLEEP_0>; 277 next-level-cache = <&L2_500>; 278 operating-points-v2 = <&cpu4_opp_table>; 279 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 280 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 281 qcom,freq-domain = <&cpufreq_hw 1>; 282 #cooling-cells = <2>; 283 L2_500: l2-cache { 284 compatible = "cache"; 285 next-level-cache = <&L3_0>; 286 }; 287 }; 288 289 CPU6: cpu@600 { 290 device_type = "cpu"; 291 compatible = "arm,kryo"; 292 reg = <0x0 0x600>; 293 enable-method = "psci"; 294 cpu-idle-states = <&BIG_CPU_SLEEP_0 295 &BIG_CPU_SLEEP_1 296 &CLUSTER_SLEEP_0>; 297 next-level-cache = <&L2_600>; 298 operating-points-v2 = <&cpu4_opp_table>; 299 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 300 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 301 qcom,freq-domain = <&cpufreq_hw 1>; 302 #cooling-cells = <2>; 303 L2_600: l2-cache { 304 compatible = "cache"; 305 next-level-cache = <&L3_0>; 306 }; 307 }; 308 309 CPU7: cpu@700 { 310 device_type = "cpu"; 311 compatible = "arm,kryo"; 312 reg = <0x0 0x700>; 313 enable-method = "psci"; 314 cpu-idle-states = <&BIG_CPU_SLEEP_0 315 &BIG_CPU_SLEEP_1 316 &CLUSTER_SLEEP_0>; 317 next-level-cache = <&L2_700>; 318 operating-points-v2 = <&cpu7_opp_table>; 319 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 320 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 321 qcom,freq-domain = <&cpufreq_hw 2>; 322 #cooling-cells = <2>; 323 L2_700: l2-cache { 324 compatible = "cache"; 325 next-level-cache = <&L3_0>; 326 }; 327 }; 328 329 cpu-map { 330 cluster0 { 331 core0 { 332 cpu = <&CPU0>; 333 }; 334 335 core1 { 336 cpu = <&CPU1>; 337 }; 338 339 core2 { 340 cpu = <&CPU2>; 341 }; 342 343 core3 { 344 cpu = <&CPU3>; 345 }; 346 347 core4 { 348 cpu = <&CPU4>; 349 }; 350 351 core5 { 352 cpu = <&CPU5>; 353 }; 354 355 core6 { 356 cpu = <&CPU6>; 357 }; 358 359 core7 { 360 cpu = <&CPU7>; 361 }; 362 }; 363 }; 364 365 idle-states { 366 entry-method = "psci"; 367 368 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 369 compatible = "arm,idle-state"; 370 idle-state-name = "little-power-down"; 371 arm,psci-suspend-param = <0x40000003>; 372 entry-latency-us = <549>; 373 exit-latency-us = <901>; 374 min-residency-us = <1774>; 375 local-timer-stop; 376 }; 377 378 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 379 compatible = "arm,idle-state"; 380 idle-state-name = "little-rail-power-down"; 381 arm,psci-suspend-param = <0x40000004>; 382 entry-latency-us = <702>; 383 exit-latency-us = <915>; 384 min-residency-us = <4001>; 385 local-timer-stop; 386 }; 387 388 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 389 compatible = "arm,idle-state"; 390 idle-state-name = "big-power-down"; 391 arm,psci-suspend-param = <0x40000003>; 392 entry-latency-us = <523>; 393 exit-latency-us = <1244>; 394 min-residency-us = <2207>; 395 local-timer-stop; 396 }; 397 398 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 399 compatible = "arm,idle-state"; 400 idle-state-name = "big-rail-power-down"; 401 arm,psci-suspend-param = <0x40000004>; 402 entry-latency-us = <526>; 403 exit-latency-us = <1854>; 404 min-residency-us = <5555>; 405 local-timer-stop; 406 }; 407 408 CLUSTER_SLEEP_0: cluster-sleep-0 { 409 compatible = "arm,idle-state"; 410 idle-state-name = "cluster-power-down"; 411 arm,psci-suspend-param = <0x40003444>; 412 entry-latency-us = <3263>; 413 exit-latency-us = <6562>; 414 min-residency-us = <9926>; 415 local-timer-stop; 416 }; 417 }; 418 }; 419 420 cpu0_opp_table: opp-table-cpu0 { 421 compatible = "operating-points-v2"; 422 opp-shared; 423 424 cpu0_opp_300mhz: opp-300000000 { 425 opp-hz = /bits/ 64 <300000000>; 426 opp-peak-kBps = <800000 9600000>; 427 }; 428 429 cpu0_opp_691mhz: opp-691200000 { 430 opp-hz = /bits/ 64 <691200000>; 431 opp-peak-kBps = <800000 17817600>; 432 }; 433 434 cpu0_opp_806mhz: opp-806400000 { 435 opp-hz = /bits/ 64 <806400000>; 436 opp-peak-kBps = <800000 20889600>; 437 }; 438 439 cpu0_opp_941mhz: opp-940800000 { 440 opp-hz = /bits/ 64 <940800000>; 441 opp-peak-kBps = <1804000 24576000>; 442 }; 443 444 cpu0_opp_1152mhz: opp-1152000000 { 445 opp-hz = /bits/ 64 <1152000000>; 446 opp-peak-kBps = <2188000 27033600>; 447 }; 448 449 cpu0_opp_1325mhz: opp-1324800000 { 450 opp-hz = /bits/ 64 <1324800000>; 451 opp-peak-kBps = <2188000 33792000>; 452 }; 453 454 cpu0_opp_1517mhz: opp-1516800000 { 455 opp-hz = /bits/ 64 <1516800000>; 456 opp-peak-kBps = <3072000 38092800>; 457 }; 458 459 cpu0_opp_1651mhz: opp-1651200000 { 460 opp-hz = /bits/ 64 <1651200000>; 461 opp-peak-kBps = <3072000 41779200>; 462 }; 463 464 cpu0_opp_1805mhz: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <4068000 48537600>; 467 }; 468 469 cpu0_opp_1958mhz: opp-1958400000 { 470 opp-hz = /bits/ 64 <1958400000>; 471 opp-peak-kBps = <4068000 48537600>; 472 }; 473 474 cpu0_opp_2016mhz: opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <6220000 48537600>; 477 }; 478 }; 479 480 cpu4_opp_table: opp-table-cpu4 { 481 compatible = "operating-points-v2"; 482 opp-shared; 483 484 cpu4_opp_691mhz: opp-691200000 { 485 opp-hz = /bits/ 64 <691200000>; 486 opp-peak-kBps = <1804000 9600000>; 487 }; 488 489 cpu4_opp_941mhz: opp-940800000 { 490 opp-hz = /bits/ 64 <940800000>; 491 opp-peak-kBps = <2188000 17817600>; 492 }; 493 494 cpu4_opp_1229mhz: opp-1228800000 { 495 opp-hz = /bits/ 64 <1228800000>; 496 opp-peak-kBps = <4068000 24576000>; 497 }; 498 499 cpu4_opp_1344mhz: opp-1344000000 { 500 opp-hz = /bits/ 64 <1344000000>; 501 opp-peak-kBps = <4068000 24576000>; 502 }; 503 504 cpu4_opp_1517mhz: opp-1516800000 { 505 opp-hz = /bits/ 64 <1516800000>; 506 opp-peak-kBps = <4068000 24576000>; 507 }; 508 509 cpu4_opp_1651mhz: opp-1651200000 { 510 opp-hz = /bits/ 64 <1651200000>; 511 opp-peak-kBps = <6220000 38092800>; 512 }; 513 514 cpu4_opp_1901mhz: opp-1900800000 { 515 opp-hz = /bits/ 64 <1900800000>; 516 opp-peak-kBps = <6220000 44851200>; 517 }; 518 519 cpu4_opp_2054mhz: opp-2054400000 { 520 opp-hz = /bits/ 64 <2054400000>; 521 opp-peak-kBps = <6220000 44851200>; 522 }; 523 524 cpu4_opp_2112mhz: opp-2112000000 { 525 opp-hz = /bits/ 64 <2112000000>; 526 opp-peak-kBps = <6220000 44851200>; 527 }; 528 529 cpu4_opp_2131mhz: opp-2131200000 { 530 opp-hz = /bits/ 64 <2131200000>; 531 opp-peak-kBps = <6220000 44851200>; 532 }; 533 534 cpu4_opp_2208mhz: opp-2208000000 { 535 opp-hz = /bits/ 64 <2208000000>; 536 opp-peak-kBps = <6220000 44851200>; 537 }; 538 539 cpu4_opp_2400mhz: opp-2400000000 { 540 opp-hz = /bits/ 64 <2400000000>; 541 opp-peak-kBps = <8532000 48537600>; 542 }; 543 544 cpu4_opp_2611mhz: opp-2611200000 { 545 opp-hz = /bits/ 64 <2611200000>; 546 opp-peak-kBps = <8532000 48537600>; 547 }; 548 }; 549 550 cpu7_opp_table: opp-table-cpu7 { 551 compatible = "operating-points-v2"; 552 opp-shared; 553 554 cpu7_opp_806mhz: opp-806400000 { 555 opp-hz = /bits/ 64 <806400000>; 556 opp-peak-kBps = <1804000 9600000>; 557 }; 558 559 cpu7_opp_1056mhz: opp-1056000000 { 560 opp-hz = /bits/ 64 <1056000000>; 561 opp-peak-kBps = <2188000 17817600>; 562 }; 563 564 cpu7_opp_1325mhz: opp-1324800000 { 565 opp-hz = /bits/ 64 <1324800000>; 566 opp-peak-kBps = <4068000 24576000>; 567 }; 568 569 cpu7_opp_1517mhz: opp-1516800000 { 570 opp-hz = /bits/ 64 <1516800000>; 571 opp-peak-kBps = <4068000 24576000>; 572 }; 573 574 cpu7_opp_1766mhz: opp-1766400000 { 575 opp-hz = /bits/ 64 <1766400000>; 576 opp-peak-kBps = <6220000 38092800>; 577 }; 578 579 cpu7_opp_1862mhz: opp-1862400000 { 580 opp-hz = /bits/ 64 <1862400000>; 581 opp-peak-kBps = <6220000 38092800>; 582 }; 583 584 cpu7_opp_2035mhz: opp-2035200000 { 585 opp-hz = /bits/ 64 <2035200000>; 586 opp-peak-kBps = <6220000 38092800>; 587 }; 588 589 cpu7_opp_2112mhz: opp-2112000000 { 590 opp-hz = /bits/ 64 <2112000000>; 591 opp-peak-kBps = <6220000 44851200>; 592 }; 593 594 cpu7_opp_2208mhz: opp-2208000000 { 595 opp-hz = /bits/ 64 <2208000000>; 596 opp-peak-kBps = <6220000 44851200>; 597 }; 598 599 cpu7_opp_2381mhz: opp-2380800000 { 600 opp-hz = /bits/ 64 <2380800000>; 601 opp-peak-kBps = <6832000 44851200>; 602 }; 603 604 cpu7_opp_2400mhz: opp-2400000000 { 605 opp-hz = /bits/ 64 <2400000000>; 606 opp-peak-kBps = <8532000 48537600>; 607 }; 608 609 cpu7_opp_2515mhz: opp-2515200000 { 610 opp-hz = /bits/ 64 <2515200000>; 611 opp-peak-kBps = <8532000 48537600>; 612 }; 613 614 cpu7_opp_2707mhz: opp-2707200000 { 615 opp-hz = /bits/ 64 <2707200000>; 616 opp-peak-kBps = <8532000 48537600>; 617 }; 618 619 cpu7_opp_3014mhz: opp-3014400000 { 620 opp-hz = /bits/ 64 <3014400000>; 621 opp-peak-kBps = <8532000 48537600>; 622 }; 623 }; 624 625 memory@80000000 { 626 device_type = "memory"; 627 /* We expect the bootloader to fill in the size */ 628 reg = <0 0x80000000 0 0>; 629 }; 630 631 firmware { 632 scm { 633 compatible = "qcom,scm-sc7280", "qcom,scm"; 634 }; 635 }; 636 637 clk_virt: interconnect { 638 compatible = "qcom,sc7280-clk-virt"; 639 #interconnect-cells = <2>; 640 qcom,bcm-voters = <&apps_bcm_voter>; 641 }; 642 643 smem { 644 compatible = "qcom,smem"; 645 memory-region = <&smem_mem>; 646 hwlocks = <&tcsr_mutex 3>; 647 }; 648 649 smp2p-adsp { 650 compatible = "qcom,smp2p"; 651 qcom,smem = <443>, <429>; 652 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 653 IPCC_MPROC_SIGNAL_SMP2P 654 IRQ_TYPE_EDGE_RISING>; 655 mboxes = <&ipcc IPCC_CLIENT_LPASS 656 IPCC_MPROC_SIGNAL_SMP2P>; 657 658 qcom,local-pid = <0>; 659 qcom,remote-pid = <2>; 660 661 adsp_smp2p_out: master-kernel { 662 qcom,entry-name = "master-kernel"; 663 #qcom,smem-state-cells = <1>; 664 }; 665 666 adsp_smp2p_in: slave-kernel { 667 qcom,entry-name = "slave-kernel"; 668 interrupt-controller; 669 #interrupt-cells = <2>; 670 }; 671 }; 672 673 smp2p-cdsp { 674 compatible = "qcom,smp2p"; 675 qcom,smem = <94>, <432>; 676 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 677 IPCC_MPROC_SIGNAL_SMP2P 678 IRQ_TYPE_EDGE_RISING>; 679 mboxes = <&ipcc IPCC_CLIENT_CDSP 680 IPCC_MPROC_SIGNAL_SMP2P>; 681 682 qcom,local-pid = <0>; 683 qcom,remote-pid = <5>; 684 685 cdsp_smp2p_out: master-kernel { 686 qcom,entry-name = "master-kernel"; 687 #qcom,smem-state-cells = <1>; 688 }; 689 690 cdsp_smp2p_in: slave-kernel { 691 qcom,entry-name = "slave-kernel"; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 }; 695 }; 696 697 smp2p-mpss { 698 compatible = "qcom,smp2p"; 699 qcom,smem = <435>, <428>; 700 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 701 IPCC_MPROC_SIGNAL_SMP2P 702 IRQ_TYPE_EDGE_RISING>; 703 mboxes = <&ipcc IPCC_CLIENT_MPSS 704 IPCC_MPROC_SIGNAL_SMP2P>; 705 706 qcom,local-pid = <0>; 707 qcom,remote-pid = <1>; 708 709 modem_smp2p_out: master-kernel { 710 qcom,entry-name = "master-kernel"; 711 #qcom,smem-state-cells = <1>; 712 }; 713 714 modem_smp2p_in: slave-kernel { 715 qcom,entry-name = "slave-kernel"; 716 interrupt-controller; 717 #interrupt-cells = <2>; 718 }; 719 720 ipa_smp2p_out: ipa-ap-to-modem { 721 qcom,entry-name = "ipa"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 ipa_smp2p_in: ipa-modem-to-ap { 726 qcom,entry-name = "ipa"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 }; 731 732 smp2p-wpss { 733 compatible = "qcom,smp2p"; 734 qcom,smem = <617>, <616>; 735 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 736 IPCC_MPROC_SIGNAL_SMP2P 737 IRQ_TYPE_EDGE_RISING>; 738 mboxes = <&ipcc IPCC_CLIENT_WPSS 739 IPCC_MPROC_SIGNAL_SMP2P>; 740 741 qcom,local-pid = <0>; 742 qcom,remote-pid = <13>; 743 744 wpss_smp2p_out: master-kernel { 745 qcom,entry-name = "master-kernel"; 746 #qcom,smem-state-cells = <1>; 747 }; 748 749 wpss_smp2p_in: slave-kernel { 750 qcom,entry-name = "slave-kernel"; 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 }; 754 }; 755 756 pmu { 757 compatible = "arm,armv8-pmuv3"; 758 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 759 }; 760 761 psci { 762 compatible = "arm,psci-1.0"; 763 method = "smc"; 764 }; 765 766 qspi_opp_table: opp-table-qspi { 767 compatible = "operating-points-v2"; 768 769 opp-75000000 { 770 opp-hz = /bits/ 64 <75000000>; 771 required-opps = <&rpmhpd_opp_low_svs>; 772 }; 773 774 opp-150000000 { 775 opp-hz = /bits/ 64 <150000000>; 776 required-opps = <&rpmhpd_opp_svs>; 777 }; 778 779 opp-200000000 { 780 opp-hz = /bits/ 64 <200000000>; 781 required-opps = <&rpmhpd_opp_svs_l1>; 782 }; 783 784 opp-300000000 { 785 opp-hz = /bits/ 64 <300000000>; 786 required-opps = <&rpmhpd_opp_nom>; 787 }; 788 }; 789 790 qup_opp_table: opp-table-qup { 791 compatible = "operating-points-v2"; 792 793 opp-75000000 { 794 opp-hz = /bits/ 64 <75000000>; 795 required-opps = <&rpmhpd_opp_low_svs>; 796 }; 797 798 opp-100000000 { 799 opp-hz = /bits/ 64 <100000000>; 800 required-opps = <&rpmhpd_opp_svs>; 801 }; 802 803 opp-128000000 { 804 opp-hz = /bits/ 64 <128000000>; 805 required-opps = <&rpmhpd_opp_nom>; 806 }; 807 }; 808 809 soc: soc@0 { 810 #address-cells = <2>; 811 #size-cells = <2>; 812 ranges = <0 0 0 0 0x10 0>; 813 dma-ranges = <0 0 0 0 0x10 0>; 814 compatible = "simple-bus"; 815 816 gcc: clock-controller@100000 { 817 compatible = "qcom,gcc-sc7280"; 818 reg = <0 0x00100000 0 0x1f0000>; 819 clocks = <&rpmhcc RPMH_CXO_CLK>, 820 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 821 <0>, <&pcie1_lane>, 822 <0>, <0>, <0>, <0>; 823 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 824 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 825 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 826 "ufs_phy_tx_symbol_0_clk", 827 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 828 #clock-cells = <1>; 829 #reset-cells = <1>; 830 #power-domain-cells = <1>; 831 }; 832 833 ipcc: mailbox@408000 { 834 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 835 reg = <0 0x00408000 0 0x1000>; 836 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 837 interrupt-controller; 838 #interrupt-cells = <3>; 839 #mbox-cells = <2>; 840 }; 841 842 qfprom: efuse@784000 { 843 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 844 reg = <0 0x00784000 0 0xa20>, 845 <0 0x00780000 0 0xa20>, 846 <0 0x00782000 0 0x120>, 847 <0 0x00786000 0 0x1fff>; 848 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 849 clock-names = "core"; 850 power-domains = <&rpmhpd SC7280_MX>; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 854 gpu_speed_bin: gpu_speed_bin@1e9 { 855 reg = <0x1e9 0x2>; 856 bits = <5 8>; 857 }; 858 }; 859 860 sdhc_1: mmc@7c4000 { 861 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 862 pinctrl-names = "default", "sleep"; 863 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 864 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 865 status = "disabled"; 866 867 reg = <0 0x007c4000 0 0x1000>, 868 <0 0x007c5000 0 0x1000>; 869 reg-names = "hc", "cqhci"; 870 871 iommus = <&apps_smmu 0xc0 0x0>; 872 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "hc_irq", "pwr_irq"; 875 876 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 877 <&gcc GCC_SDCC1_APPS_CLK>, 878 <&rpmhcc RPMH_CXO_CLK>; 879 clock-names = "iface", "core", "xo"; 880 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 881 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 882 interconnect-names = "sdhc-ddr","cpu-sdhc"; 883 power-domains = <&rpmhpd SC7280_CX>; 884 operating-points-v2 = <&sdhc1_opp_table>; 885 886 bus-width = <8>; 887 supports-cqe; 888 889 qcom,dll-config = <0x0007642c>; 890 qcom,ddr-config = <0x80040868>; 891 892 mmc-ddr-1_8v; 893 mmc-hs200-1_8v; 894 mmc-hs400-1_8v; 895 mmc-hs400-enhanced-strobe; 896 897 resets = <&gcc GCC_SDCC1_BCR>; 898 899 sdhc1_opp_table: opp-table { 900 compatible = "operating-points-v2"; 901 902 opp-100000000 { 903 opp-hz = /bits/ 64 <100000000>; 904 required-opps = <&rpmhpd_opp_low_svs>; 905 opp-peak-kBps = <1800000 400000>; 906 opp-avg-kBps = <100000 0>; 907 }; 908 909 opp-384000000 { 910 opp-hz = /bits/ 64 <384000000>; 911 required-opps = <&rpmhpd_opp_nom>; 912 opp-peak-kBps = <5400000 1600000>; 913 opp-avg-kBps = <390000 0>; 914 }; 915 }; 916 917 }; 918 919 gpi_dma0: dma-controller@900000 { 920 #dma-cells = <3>; 921 compatible = "qcom,sc7280-gpi-dma"; 922 reg = <0 0x00900000 0 0x60000>; 923 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 935 dma-channels = <12>; 936 dma-channel-mask = <0x7f>; 937 iommus = <&apps_smmu 0x0136 0x0>; 938 status = "disabled"; 939 }; 940 941 qupv3_id_0: geniqup@9c0000 { 942 compatible = "qcom,geni-se-qup"; 943 reg = <0 0x009c0000 0 0x2000>; 944 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 945 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 946 clock-names = "m-ahb", "s-ahb"; 947 #address-cells = <2>; 948 #size-cells = <2>; 949 ranges; 950 iommus = <&apps_smmu 0x123 0x0>; 951 status = "disabled"; 952 953 i2c0: i2c@980000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0 0x00980000 0 0x4000>; 956 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 957 clock-names = "se"; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c0_data_clk>; 960 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 964 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 965 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", 967 "qup-memory"; 968 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 969 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 970 dma-names = "tx", "rx"; 971 status = "disabled"; 972 }; 973 974 spi0: spi@980000 { 975 compatible = "qcom,geni-spi"; 976 reg = <0 0x00980000 0 0x4000>; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 978 clock-names = "se"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 981 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 power-domains = <&rpmhpd SC7280_CX>; 985 operating-points-v2 = <&qup_opp_table>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 988 interconnect-names = "qup-core", "qup-config"; 989 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 990 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 991 dma-names = "tx", "rx"; 992 status = "disabled"; 993 }; 994 995 uart0: serial@980000 { 996 compatible = "qcom,geni-uart"; 997 reg = <0 0x00980000 0 0x4000>; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 999 clock-names = "se"; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1002 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1003 power-domains = <&rpmhpd SC7280_CX>; 1004 operating-points-v2 = <&qup_opp_table>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1007 interconnect-names = "qup-core", "qup-config"; 1008 status = "disabled"; 1009 }; 1010 1011 i2c1: i2c@984000 { 1012 compatible = "qcom,geni-i2c"; 1013 reg = <0 0x00984000 0 0x4000>; 1014 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1015 clock-names = "se"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_i2c1_data_clk>; 1018 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1022 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1023 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1024 interconnect-names = "qup-core", "qup-config", 1025 "qup-memory"; 1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1027 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1028 dma-names = "tx", "rx"; 1029 status = "disabled"; 1030 }; 1031 1032 spi1: spi@984000 { 1033 compatible = "qcom,geni-spi"; 1034 reg = <0 0x00984000 0 0x4000>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1036 clock-names = "se"; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1039 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 power-domains = <&rpmhpd SC7280_CX>; 1043 operating-points-v2 = <&qup_opp_table>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1046 interconnect-names = "qup-core", "qup-config"; 1047 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1048 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1049 dma-names = "tx", "rx"; 1050 status = "disabled"; 1051 }; 1052 1053 uart1: serial@984000 { 1054 compatible = "qcom,geni-uart"; 1055 reg = <0 0x00984000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1060 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&rpmhpd SC7280_CX>; 1062 operating-points-v2 = <&qup_opp_table>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 status = "disabled"; 1067 }; 1068 1069 i2c2: i2c@988000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0 0x00988000 0 0x4000>; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1073 clock-names = "se"; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_i2c2_data_clk>; 1076 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1081 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1082 interconnect-names = "qup-core", "qup-config", 1083 "qup-memory"; 1084 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1085 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1086 dma-names = "tx", "rx"; 1087 status = "disabled"; 1088 }; 1089 1090 spi2: spi@988000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x00988000 0 0x4000>; 1093 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1094 clock-names = "se"; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1097 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 power-domains = <&rpmhpd SC7280_CX>; 1101 operating-points-v2 = <&qup_opp_table>; 1102 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1103 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1104 interconnect-names = "qup-core", "qup-config"; 1105 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1106 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1107 dma-names = "tx", "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 uart2: serial@988000 { 1112 compatible = "qcom,geni-uart"; 1113 reg = <0 0x00988000 0 0x4000>; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1115 clock-names = "se"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1118 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1119 power-domains = <&rpmhpd SC7280_CX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 status = "disabled"; 1125 }; 1126 1127 i2c3: i2c@98c000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x0098c000 0 0x4000>; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1131 clock-names = "se"; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c3_data_clk>; 1134 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1138 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1139 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1140 interconnect-names = "qup-core", "qup-config", 1141 "qup-memory"; 1142 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1143 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1144 dma-names = "tx", "rx"; 1145 status = "disabled"; 1146 }; 1147 1148 spi3: spi@98c000 { 1149 compatible = "qcom,geni-spi"; 1150 reg = <0 0x0098c000 0 0x4000>; 1151 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1152 clock-names = "se"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1155 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 power-domains = <&rpmhpd SC7280_CX>; 1159 operating-points-v2 = <&qup_opp_table>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1161 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1162 interconnect-names = "qup-core", "qup-config"; 1163 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1164 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1165 dma-names = "tx", "rx"; 1166 status = "disabled"; 1167 }; 1168 1169 uart3: serial@98c000 { 1170 compatible = "qcom,geni-uart"; 1171 reg = <0 0x0098c000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1176 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC7280_CX>; 1178 operating-points-v2 = <&qup_opp_table>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1181 interconnect-names = "qup-core", "qup-config"; 1182 status = "disabled"; 1183 }; 1184 1185 i2c4: i2c@990000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x00990000 0 0x4000>; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1189 clock-names = "se"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_i2c4_data_clk>; 1192 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1196 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1197 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1198 interconnect-names = "qup-core", "qup-config", 1199 "qup-memory"; 1200 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 status = "disabled"; 1204 }; 1205 1206 spi4: spi@990000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0 0x00990000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1213 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 power-domains = <&rpmhpd SC7280_CX>; 1217 operating-points-v2 = <&qup_opp_table>; 1218 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1219 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1220 interconnect-names = "qup-core", "qup-config"; 1221 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1222 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1223 dma-names = "tx", "rx"; 1224 status = "disabled"; 1225 }; 1226 1227 uart4: serial@990000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00990000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1234 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC7280_CX>; 1236 operating-points-v2 = <&qup_opp_table>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c5: i2c@994000 { 1244 compatible = "qcom,geni-i2c"; 1245 reg = <0 0x00994000 0 0x4000>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1247 clock-names = "se"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_i2c5_data_clk>; 1250 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1256 interconnect-names = "qup-core", "qup-config", 1257 "qup-memory"; 1258 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1259 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1260 dma-names = "tx", "rx"; 1261 status = "disabled"; 1262 }; 1263 1264 spi5: spi@994000 { 1265 compatible = "qcom,geni-spi"; 1266 reg = <0 0x00994000 0 0x4000>; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1268 clock-names = "se"; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1271 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 power-domains = <&rpmhpd SC7280_CX>; 1275 operating-points-v2 = <&qup_opp_table>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1278 interconnect-names = "qup-core", "qup-config"; 1279 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1280 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1281 dma-names = "tx", "rx"; 1282 status = "disabled"; 1283 }; 1284 1285 uart5: serial@994000 { 1286 compatible = "qcom,geni-uart"; 1287 reg = <0 0x00994000 0 0x4000>; 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1289 clock-names = "se"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1292 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd SC7280_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1296 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1297 interconnect-names = "qup-core", "qup-config"; 1298 status = "disabled"; 1299 }; 1300 1301 i2c6: i2c@998000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0 0x00998000 0 0x4000>; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1305 clock-names = "se"; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_i2c6_data_clk>; 1308 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1312 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1313 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1314 interconnect-names = "qup-core", "qup-config", 1315 "qup-memory"; 1316 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1317 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1318 dma-names = "tx", "rx"; 1319 status = "disabled"; 1320 }; 1321 1322 spi6: spi@998000 { 1323 compatible = "qcom,geni-spi"; 1324 reg = <0 0x00998000 0 0x4000>; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1326 clock-names = "se"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1329 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 power-domains = <&rpmhpd SC7280_CX>; 1333 operating-points-v2 = <&qup_opp_table>; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1335 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1336 interconnect-names = "qup-core", "qup-config"; 1337 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1338 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1339 dma-names = "tx", "rx"; 1340 status = "disabled"; 1341 }; 1342 1343 uart6: serial@998000 { 1344 compatible = "qcom,geni-uart"; 1345 reg = <0 0x00998000 0 0x4000>; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1347 clock-names = "se"; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1350 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1351 power-domains = <&rpmhpd SC7280_CX>; 1352 operating-points-v2 = <&qup_opp_table>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1355 interconnect-names = "qup-core", "qup-config"; 1356 status = "disabled"; 1357 }; 1358 1359 i2c7: i2c@99c000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x0099c000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1363 clock-names = "se"; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&qup_i2c7_data_clk>; 1366 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1370 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1371 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1372 interconnect-names = "qup-core", "qup-config", 1373 "qup-memory"; 1374 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1375 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1376 dma-names = "tx", "rx"; 1377 status = "disabled"; 1378 }; 1379 1380 spi7: spi@99c000 { 1381 compatible = "qcom,geni-spi"; 1382 reg = <0 0x0099c000 0 0x4000>; 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1384 clock-names = "se"; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1387 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 power-domains = <&rpmhpd SC7280_CX>; 1391 operating-points-v2 = <&qup_opp_table>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1396 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1397 dma-names = "tx", "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 uart7: serial@99c000 { 1402 compatible = "qcom,geni-uart"; 1403 reg = <0 0x0099c000 0 0x4000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1405 clock-names = "se"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC7280_CX>; 1410 operating-points-v2 = <&qup_opp_table>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1413 interconnect-names = "qup-core", "qup-config"; 1414 status = "disabled"; 1415 }; 1416 }; 1417 1418 gpi_dma1: dma-controller@a00000 { 1419 #dma-cells = <3>; 1420 compatible = "qcom,sc7280-gpi-dma"; 1421 reg = <0 0x00a00000 0 0x60000>; 1422 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1434 dma-channels = <12>; 1435 dma-channel-mask = <0x1e>; 1436 iommus = <&apps_smmu 0x56 0x0>; 1437 status = "disabled"; 1438 }; 1439 1440 qupv3_id_1: geniqup@ac0000 { 1441 compatible = "qcom,geni-se-qup"; 1442 reg = <0 0x00ac0000 0 0x2000>; 1443 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1444 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1445 clock-names = "m-ahb", "s-ahb"; 1446 #address-cells = <2>; 1447 #size-cells = <2>; 1448 ranges; 1449 iommus = <&apps_smmu 0x43 0x0>; 1450 status = "disabled"; 1451 1452 i2c8: i2c@a80000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00a80000 0 0x4000>; 1455 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1456 clock-names = "se"; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_i2c8_data_clk>; 1459 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1463 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1464 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1465 interconnect-names = "qup-core", "qup-config", 1466 "qup-memory"; 1467 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1468 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1469 dma-names = "tx", "rx"; 1470 status = "disabled"; 1471 }; 1472 1473 spi8: spi@a80000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0x00a80000 0 0x4000>; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1477 clock-names = "se"; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1480 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 power-domains = <&rpmhpd SC7280_CX>; 1484 operating-points-v2 = <&qup_opp_table>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1487 interconnect-names = "qup-core", "qup-config"; 1488 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1489 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1490 dma-names = "tx", "rx"; 1491 status = "disabled"; 1492 }; 1493 1494 uart8: serial@a80000 { 1495 compatible = "qcom,geni-uart"; 1496 reg = <0 0x00a80000 0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1498 clock-names = "se"; 1499 pinctrl-names = "default"; 1500 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1501 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1502 power-domains = <&rpmhpd SC7280_CX>; 1503 operating-points-v2 = <&qup_opp_table>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1506 interconnect-names = "qup-core", "qup-config"; 1507 status = "disabled"; 1508 }; 1509 1510 i2c9: i2c@a84000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0 0x00a84000 0 0x4000>; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1514 clock-names = "se"; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&qup_i2c9_data_clk>; 1517 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1523 interconnect-names = "qup-core", "qup-config", 1524 "qup-memory"; 1525 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1526 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1527 dma-names = "tx", "rx"; 1528 status = "disabled"; 1529 }; 1530 1531 spi9: spi@a84000 { 1532 compatible = "qcom,geni-spi"; 1533 reg = <0 0x00a84000 0 0x4000>; 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1535 clock-names = "se"; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1538 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 power-domains = <&rpmhpd SC7280_CX>; 1542 operating-points-v2 = <&qup_opp_table>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1545 interconnect-names = "qup-core", "qup-config"; 1546 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1547 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1548 dma-names = "tx", "rx"; 1549 status = "disabled"; 1550 }; 1551 1552 uart9: serial@a84000 { 1553 compatible = "qcom,geni-uart"; 1554 reg = <0 0x00a84000 0 0x4000>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1556 clock-names = "se"; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1559 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1560 power-domains = <&rpmhpd SC7280_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1564 interconnect-names = "qup-core", "qup-config"; 1565 status = "disabled"; 1566 }; 1567 1568 i2c10: i2c@a88000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00a88000 0 0x4000>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1572 clock-names = "se"; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c10_data_clk>; 1575 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1579 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1580 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", 1582 "qup-memory"; 1583 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 status = "disabled"; 1587 }; 1588 1589 spi10: spi@a88000 { 1590 compatible = "qcom,geni-spi"; 1591 reg = <0 0x00a88000 0 0x4000>; 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1593 clock-names = "se"; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1596 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 power-domains = <&rpmhpd SC7280_CX>; 1600 operating-points-v2 = <&qup_opp_table>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1603 interconnect-names = "qup-core", "qup-config"; 1604 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1605 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1606 dma-names = "tx", "rx"; 1607 status = "disabled"; 1608 }; 1609 1610 uart10: serial@a88000 { 1611 compatible = "qcom,geni-uart"; 1612 reg = <0 0x00a88000 0 0x4000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1614 clock-names = "se"; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1617 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1618 power-domains = <&rpmhpd SC7280_CX>; 1619 operating-points-v2 = <&qup_opp_table>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1622 interconnect-names = "qup-core", "qup-config"; 1623 status = "disabled"; 1624 }; 1625 1626 i2c11: i2c@a8c000 { 1627 compatible = "qcom,geni-i2c"; 1628 reg = <0 0x00a8c000 0 0x4000>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1630 clock-names = "se"; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_i2c11_data_clk>; 1633 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1638 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1639 interconnect-names = "qup-core", "qup-config", 1640 "qup-memory"; 1641 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1642 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1643 dma-names = "tx", "rx"; 1644 status = "disabled"; 1645 }; 1646 1647 spi11: spi@a8c000 { 1648 compatible = "qcom,geni-spi"; 1649 reg = <0 0x00a8c000 0 0x4000>; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1651 clock-names = "se"; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 power-domains = <&rpmhpd SC7280_CX>; 1658 operating-points-v2 = <&qup_opp_table>; 1659 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1660 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1661 interconnect-names = "qup-core", "qup-config"; 1662 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1663 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1664 dma-names = "tx", "rx"; 1665 status = "disabled"; 1666 }; 1667 1668 uart11: serial@a8c000 { 1669 compatible = "qcom,geni-uart"; 1670 reg = <0 0x00a8c000 0 0x4000>; 1671 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1672 clock-names = "se"; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1675 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1676 power-domains = <&rpmhpd SC7280_CX>; 1677 operating-points-v2 = <&qup_opp_table>; 1678 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1679 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1680 interconnect-names = "qup-core", "qup-config"; 1681 status = "disabled"; 1682 }; 1683 1684 i2c12: i2c@a90000 { 1685 compatible = "qcom,geni-i2c"; 1686 reg = <0 0x00a90000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_i2c12_data_clk>; 1691 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1695 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1696 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1697 interconnect-names = "qup-core", "qup-config", 1698 "qup-memory"; 1699 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1700 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 spi12: spi@a90000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a90000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1712 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 power-domains = <&rpmhpd SC7280_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1721 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1722 dma-names = "tx", "rx"; 1723 status = "disabled"; 1724 }; 1725 1726 uart12: serial@a90000 { 1727 compatible = "qcom,geni-uart"; 1728 reg = <0 0x00a90000 0 0x4000>; 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1730 clock-names = "se"; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SC7280_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1737 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1738 interconnect-names = "qup-core", "qup-config"; 1739 status = "disabled"; 1740 }; 1741 1742 i2c13: i2c@a94000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0 0x00a94000 0 0x4000>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1746 clock-names = "se"; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c13_data_clk>; 1749 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", 1756 "qup-memory"; 1757 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1759 dma-names = "tx", "rx"; 1760 status = "disabled"; 1761 }; 1762 1763 spi13: spi@a94000 { 1764 compatible = "qcom,geni-spi"; 1765 reg = <0 0x00a94000 0 0x4000>; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1767 clock-names = "se"; 1768 pinctrl-names = "default"; 1769 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1770 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1779 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1780 dma-names = "tx", "rx"; 1781 status = "disabled"; 1782 }; 1783 1784 uart13: serial@a94000 { 1785 compatible = "qcom,geni-uart"; 1786 reg = <0 0x00a94000 0 0x4000>; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1788 clock-names = "se"; 1789 pinctrl-names = "default"; 1790 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1791 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1792 power-domains = <&rpmhpd SC7280_CX>; 1793 operating-points-v2 = <&qup_opp_table>; 1794 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1795 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1796 interconnect-names = "qup-core", "qup-config"; 1797 status = "disabled"; 1798 }; 1799 1800 i2c14: i2c@a98000 { 1801 compatible = "qcom,geni-i2c"; 1802 reg = <0 0x00a98000 0 0x4000>; 1803 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1804 clock-names = "se"; 1805 pinctrl-names = "default"; 1806 pinctrl-0 = <&qup_i2c14_data_clk>; 1807 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1811 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1813 interconnect-names = "qup-core", "qup-config", 1814 "qup-memory"; 1815 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1816 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1817 dma-names = "tx", "rx"; 1818 status = "disabled"; 1819 }; 1820 1821 spi14: spi@a98000 { 1822 compatible = "qcom,geni-spi"; 1823 reg = <0 0x00a98000 0 0x4000>; 1824 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1825 clock-names = "se"; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1828 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 power-domains = <&rpmhpd SC7280_CX>; 1832 operating-points-v2 = <&qup_opp_table>; 1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1835 interconnect-names = "qup-core", "qup-config"; 1836 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1837 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1838 dma-names = "tx", "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 uart14: serial@a98000 { 1843 compatible = "qcom,geni-uart"; 1844 reg = <0 0x00a98000 0 0x4000>; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 clock-names = "se"; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1849 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1850 power-domains = <&rpmhpd SC7280_CX>; 1851 operating-points-v2 = <&qup_opp_table>; 1852 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1853 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1854 interconnect-names = "qup-core", "qup-config"; 1855 status = "disabled"; 1856 }; 1857 1858 i2c15: i2c@a9c000 { 1859 compatible = "qcom,geni-i2c"; 1860 reg = <0 0x00a9c000 0 0x4000>; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1862 clock-names = "se"; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&qup_i2c15_data_clk>; 1865 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1869 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1870 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "qup-core", "qup-config", 1872 "qup-memory"; 1873 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1874 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1875 dma-names = "tx", "rx"; 1876 status = "disabled"; 1877 }; 1878 1879 spi15: spi@a9c000 { 1880 compatible = "qcom,geni-spi"; 1881 reg = <0 0x00a9c000 0 0x4000>; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1883 clock-names = "se"; 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1886 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 power-domains = <&rpmhpd SC7280_CX>; 1890 operating-points-v2 = <&qup_opp_table>; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1892 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1893 interconnect-names = "qup-core", "qup-config"; 1894 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1895 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 uart15: serial@a9c000 { 1901 compatible = "qcom,geni-uart"; 1902 reg = <0 0x00a9c000 0 0x4000>; 1903 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1904 clock-names = "se"; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1907 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1908 power-domains = <&rpmhpd SC7280_CX>; 1909 operating-points-v2 = <&qup_opp_table>; 1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 status = "disabled"; 1914 }; 1915 }; 1916 1917 cnoc2: interconnect@1500000 { 1918 reg = <0 0x01500000 0 0x1000>; 1919 compatible = "qcom,sc7280-cnoc2"; 1920 #interconnect-cells = <2>; 1921 qcom,bcm-voters = <&apps_bcm_voter>; 1922 }; 1923 1924 cnoc3: interconnect@1502000 { 1925 reg = <0 0x01502000 0 0x1000>; 1926 compatible = "qcom,sc7280-cnoc3"; 1927 #interconnect-cells = <2>; 1928 qcom,bcm-voters = <&apps_bcm_voter>; 1929 }; 1930 1931 mc_virt: interconnect@1580000 { 1932 reg = <0 0x01580000 0 0x4>; 1933 compatible = "qcom,sc7280-mc-virt"; 1934 #interconnect-cells = <2>; 1935 qcom,bcm-voters = <&apps_bcm_voter>; 1936 }; 1937 1938 system_noc: interconnect@1680000 { 1939 reg = <0 0x01680000 0 0x15480>; 1940 compatible = "qcom,sc7280-system-noc"; 1941 #interconnect-cells = <2>; 1942 qcom,bcm-voters = <&apps_bcm_voter>; 1943 }; 1944 1945 aggre1_noc: interconnect@16e0000 { 1946 compatible = "qcom,sc7280-aggre1-noc"; 1947 reg = <0 0x016e0000 0 0x1c080>; 1948 #interconnect-cells = <2>; 1949 qcom,bcm-voters = <&apps_bcm_voter>; 1950 }; 1951 1952 aggre2_noc: interconnect@1700000 { 1953 reg = <0 0x01700000 0 0x2b080>; 1954 compatible = "qcom,sc7280-aggre2-noc"; 1955 #interconnect-cells = <2>; 1956 qcom,bcm-voters = <&apps_bcm_voter>; 1957 }; 1958 1959 mmss_noc: interconnect@1740000 { 1960 reg = <0 0x01740000 0 0x1e080>; 1961 compatible = "qcom,sc7280-mmss-noc"; 1962 #interconnect-cells = <2>; 1963 qcom,bcm-voters = <&apps_bcm_voter>; 1964 }; 1965 1966 wifi: wifi@17a10040 { 1967 compatible = "qcom,wcn6750-wifi"; 1968 reg = <0 0x17a10040 0 0x0>; 1969 iommus = <&apps_smmu 0x1c00 0x1>; 1970 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1971 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1979 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1980 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1981 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1982 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1983 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1984 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1985 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1986 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1987 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1988 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1989 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1990 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1991 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1992 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1993 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1994 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1995 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1996 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1997 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1998 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2002 qcom,rproc = <&remoteproc_wpss>; 2003 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2004 status = "disabled"; 2005 }; 2006 2007 pcie1: pci@1c08000 { 2008 compatible = "qcom,pcie-sc7280"; 2009 reg = <0 0x01c08000 0 0x3000>, 2010 <0 0x40000000 0 0xf1d>, 2011 <0 0x40000f20 0 0xa8>, 2012 <0 0x40001000 0 0x1000>, 2013 <0 0x40100000 0 0x100000>; 2014 2015 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2016 device_type = "pci"; 2017 linux,pci-domain = <1>; 2018 bus-range = <0x00 0xff>; 2019 num-lanes = <2>; 2020 2021 #address-cells = <3>; 2022 #size-cells = <2>; 2023 2024 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2025 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2026 2027 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2028 interrupt-names = "msi"; 2029 #interrupt-cells = <1>; 2030 interrupt-map-mask = <0 0 0 0x7>; 2031 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2032 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2033 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2034 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2035 2036 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2037 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2038 <&pcie1_lane>, 2039 <&rpmhcc RPMH_CXO_CLK>, 2040 <&gcc GCC_PCIE_1_AUX_CLK>, 2041 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2042 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2043 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2044 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2045 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2046 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 2047 2048 clock-names = "pipe", 2049 "pipe_mux", 2050 "phy_pipe", 2051 "ref", 2052 "aux", 2053 "cfg", 2054 "bus_master", 2055 "bus_slave", 2056 "slave_q2a", 2057 "tbu", 2058 "ddrss_sf_tbu"; 2059 2060 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2061 assigned-clock-rates = <19200000>; 2062 2063 resets = <&gcc GCC_PCIE_1_BCR>; 2064 reset-names = "pci"; 2065 2066 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2067 2068 phys = <&pcie1_lane>; 2069 phy-names = "pciephy"; 2070 2071 pinctrl-names = "default"; 2072 pinctrl-0 = <&pcie1_clkreq_n>; 2073 2074 iommus = <&apps_smmu 0x1c80 0x1>; 2075 2076 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2077 <0x100 &apps_smmu 0x1c81 0x1>; 2078 2079 status = "disabled"; 2080 }; 2081 2082 pcie1_phy: phy@1c0e000 { 2083 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2084 reg = <0 0x01c0e000 0 0x1c0>; 2085 #address-cells = <2>; 2086 #size-cells = <2>; 2087 ranges; 2088 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2089 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2090 <&gcc GCC_PCIE_CLKREF_EN>, 2091 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2092 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2093 2094 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2095 reset-names = "phy"; 2096 2097 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2098 assigned-clock-rates = <100000000>; 2099 2100 status = "disabled"; 2101 2102 pcie1_lane: phy@1c0e200 { 2103 reg = <0 0x01c0e200 0 0x170>, 2104 <0 0x01c0e400 0 0x200>, 2105 <0 0x01c0ea00 0 0x1f0>, 2106 <0 0x01c0e600 0 0x170>, 2107 <0 0x01c0e800 0 0x200>, 2108 <0 0x01c0ee00 0 0xf4>; 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2110 clock-names = "pipe0"; 2111 2112 #phy-cells = <0>; 2113 #clock-cells = <0>; 2114 clock-output-names = "pcie_1_pipe_clk"; 2115 }; 2116 }; 2117 2118 ipa: ipa@1e40000 { 2119 compatible = "qcom,sc7280-ipa"; 2120 2121 iommus = <&apps_smmu 0x480 0x0>, 2122 <&apps_smmu 0x482 0x0>; 2123 reg = <0 0x1e40000 0 0x8000>, 2124 <0 0x1e50000 0 0x4ad0>, 2125 <0 0x1e04000 0 0x23000>; 2126 reg-names = "ipa-reg", 2127 "ipa-shared", 2128 "gsi"; 2129 2130 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2131 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2132 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2133 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2134 interrupt-names = "ipa", 2135 "gsi", 2136 "ipa-clock-query", 2137 "ipa-setup-ready"; 2138 2139 clocks = <&rpmhcc RPMH_IPA_CLK>; 2140 clock-names = "core"; 2141 2142 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2144 interconnect-names = "memory", 2145 "config"; 2146 2147 qcom,qmp = <&aoss_qmp>; 2148 2149 qcom,smem-states = <&ipa_smp2p_out 0>, 2150 <&ipa_smp2p_out 1>; 2151 qcom,smem-state-names = "ipa-clock-enabled-valid", 2152 "ipa-clock-enabled"; 2153 2154 status = "disabled"; 2155 }; 2156 2157 tcsr_mutex: hwlock@1f40000 { 2158 compatible = "qcom,tcsr-mutex"; 2159 reg = <0 0x01f40000 0 0x20000>; 2160 #hwlock-cells = <1>; 2161 }; 2162 2163 tcsr_1: sycon@1f60000 { 2164 compatible = "qcom,sc7280-tcsr", "syscon"; 2165 reg = <0 0x01f60000 0 0x20000>; 2166 }; 2167 2168 tcsr_2: syscon@1fc0000 { 2169 compatible = "qcom,sc7280-tcsr", "syscon"; 2170 reg = <0 0x01fc0000 0 0x30000>; 2171 }; 2172 2173 lpasscc: lpasscc@3000000 { 2174 compatible = "qcom,sc7280-lpasscc"; 2175 reg = <0 0x03000000 0 0x40>, 2176 <0 0x03c04000 0 0x4>; 2177 reg-names = "qdsp6ss", "top_cc"; 2178 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2179 clock-names = "iface"; 2180 #clock-cells = <1>; 2181 }; 2182 2183 lpass_audiocc: clock-controller@3300000 { 2184 compatible = "qcom,sc7280-lpassaudiocc"; 2185 reg = <0 0x03300000 0 0x30000>; 2186 clocks = <&rpmhcc RPMH_CXO_CLK>, 2187 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2188 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2189 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2190 #clock-cells = <1>; 2191 #power-domain-cells = <1>; 2192 #reset-cells = <1>; 2193 }; 2194 2195 lpass_aon: clock-controller@3380000 { 2196 compatible = "qcom,sc7280-lpassaoncc"; 2197 reg = <0 0x03380000 0 0x30000>; 2198 clocks = <&rpmhcc RPMH_CXO_CLK>, 2199 <&rpmhcc RPMH_CXO_CLK_A>, 2200 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2201 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2202 #clock-cells = <1>; 2203 #power-domain-cells = <1>; 2204 }; 2205 2206 lpass_core: clock-controller@3900000 { 2207 compatible = "qcom,sc7280-lpasscorecc"; 2208 reg = <0 0x03900000 0 0x50000>; 2209 clocks = <&rpmhcc RPMH_CXO_CLK>; 2210 clock-names = "bi_tcxo"; 2211 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2212 #clock-cells = <1>; 2213 #power-domain-cells = <1>; 2214 }; 2215 2216 lpass_hm: clock-controller@3c00000 { 2217 compatible = "qcom,sc7280-lpasshm"; 2218 reg = <0 0x3c00000 0 0x28>; 2219 clocks = <&rpmhcc RPMH_CXO_CLK>; 2220 clock-names = "bi_tcxo"; 2221 #clock-cells = <1>; 2222 #power-domain-cells = <1>; 2223 }; 2224 2225 lpass_ag_noc: interconnect@3c40000 { 2226 reg = <0 0x03c40000 0 0xf080>; 2227 compatible = "qcom,sc7280-lpass-ag-noc"; 2228 #interconnect-cells = <2>; 2229 qcom,bcm-voters = <&apps_bcm_voter>; 2230 }; 2231 2232 lpass_tlmm: pinctrl@33c0000 { 2233 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2234 reg = <0 0x033c0000 0x0 0x20000>, 2235 <0 0x03550000 0x0 0x10000>; 2236 qcom,adsp-bypass-mode; 2237 gpio-controller; 2238 #gpio-cells = <2>; 2239 gpio-ranges = <&lpass_tlmm 0 0 15>; 2240 2241 #clock-cells = <1>; 2242 2243 lpass_dmic01_clk: dmic01-clk { 2244 pins = "gpio6"; 2245 function = "dmic1_clk"; 2246 }; 2247 2248 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2249 pins = "gpio6"; 2250 function = "dmic1_clk"; 2251 }; 2252 2253 lpass_dmic01_data: dmic01-data { 2254 pins = "gpio7"; 2255 function = "dmic1_data"; 2256 }; 2257 2258 lpass_dmic01_data_sleep: dmic01-data-sleep { 2259 pins = "gpio7"; 2260 function = "dmic1_data"; 2261 }; 2262 2263 lpass_dmic23_clk: dmic23-clk { 2264 pins = "gpio8"; 2265 function = "dmic2_clk"; 2266 }; 2267 2268 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2269 pins = "gpio8"; 2270 function = "dmic2_clk"; 2271 }; 2272 2273 lpass_dmic23_data: dmic23-data { 2274 pins = "gpio9"; 2275 function = "dmic2_data"; 2276 }; 2277 2278 lpass_dmic23_data_sleep: dmic23-data-sleep { 2279 pins = "gpio9"; 2280 function = "dmic2_data"; 2281 }; 2282 2283 lpass_rx_swr_clk: rx-swr-clk { 2284 pins = "gpio3"; 2285 function = "swr_rx_clk"; 2286 }; 2287 2288 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2289 pins = "gpio3"; 2290 function = "swr_rx_clk"; 2291 }; 2292 2293 lpass_rx_swr_data: rx-swr-data { 2294 pins = "gpio4", "gpio5"; 2295 function = "swr_rx_data"; 2296 }; 2297 2298 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2299 pins = "gpio4", "gpio5"; 2300 function = "swr_rx_data"; 2301 }; 2302 2303 lpass_tx_swr_clk: tx-swr-clk { 2304 pins = "gpio0"; 2305 function = "swr_tx_clk"; 2306 }; 2307 2308 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2309 pins = "gpio0"; 2310 function = "swr_tx_clk"; 2311 }; 2312 2313 lpass_tx_swr_data: tx-swr-data { 2314 pins = "gpio1", "gpio2", "gpio14"; 2315 function = "swr_tx_data"; 2316 }; 2317 2318 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2319 pins = "gpio1", "gpio2", "gpio14"; 2320 function = "swr_tx_data"; 2321 }; 2322 }; 2323 2324 gpu: gpu@3d00000 { 2325 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2326 reg = <0 0x03d00000 0 0x40000>, 2327 <0 0x03d9e000 0 0x1000>, 2328 <0 0x03d61000 0 0x800>; 2329 reg-names = "kgsl_3d0_reg_memory", 2330 "cx_mem", 2331 "cx_dbgc"; 2332 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2333 iommus = <&adreno_smmu 0 0x401>; 2334 operating-points-v2 = <&gpu_opp_table>; 2335 qcom,gmu = <&gmu>; 2336 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2337 interconnect-names = "gfx-mem"; 2338 #cooling-cells = <2>; 2339 2340 nvmem-cells = <&gpu_speed_bin>; 2341 nvmem-cell-names = "speed_bin"; 2342 2343 gpu_opp_table: opp-table { 2344 compatible = "operating-points-v2"; 2345 2346 opp-315000000 { 2347 opp-hz = /bits/ 64 <315000000>; 2348 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2349 opp-peak-kBps = <1804000>; 2350 opp-supported-hw = <0x03>; 2351 }; 2352 2353 opp-450000000 { 2354 opp-hz = /bits/ 64 <450000000>; 2355 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2356 opp-peak-kBps = <4068000>; 2357 opp-supported-hw = <0x03>; 2358 }; 2359 2360 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2361 opp-550000000-0 { 2362 opp-hz = /bits/ 64 <550000000>; 2363 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2364 opp-peak-kBps = <8368000>; 2365 opp-supported-hw = <0x01>; 2366 }; 2367 2368 opp-550000000-1 { 2369 opp-hz = /bits/ 64 <550000000>; 2370 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2371 opp-peak-kBps = <6832000>; 2372 opp-supported-hw = <0x02>; 2373 }; 2374 2375 opp-608000000 { 2376 opp-hz = /bits/ 64 <608000000>; 2377 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2378 opp-peak-kBps = <8368000>; 2379 opp-supported-hw = <0x02>; 2380 }; 2381 2382 opp-700000000 { 2383 opp-hz = /bits/ 64 <700000000>; 2384 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2385 opp-peak-kBps = <8532000>; 2386 opp-supported-hw = <0x02>; 2387 }; 2388 2389 opp-812000000 { 2390 opp-hz = /bits/ 64 <812000000>; 2391 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2392 opp-peak-kBps = <8532000>; 2393 opp-supported-hw = <0x02>; 2394 }; 2395 2396 opp-840000000 { 2397 opp-hz = /bits/ 64 <840000000>; 2398 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2399 opp-peak-kBps = <8532000>; 2400 opp-supported-hw = <0x02>; 2401 }; 2402 2403 opp-900000000 { 2404 opp-hz = /bits/ 64 <900000000>; 2405 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2406 opp-peak-kBps = <8532000>; 2407 opp-supported-hw = <0x02>; 2408 }; 2409 }; 2410 }; 2411 2412 gmu: gmu@3d6a000 { 2413 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2414 reg = <0 0x03d6a000 0 0x34000>, 2415 <0 0x3de0000 0 0x10000>, 2416 <0 0x0b290000 0 0x10000>; 2417 reg-names = "gmu", "rscc", "gmu_pdc"; 2418 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2419 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2420 interrupt-names = "hfi", "gmu"; 2421 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2422 <&gpucc GPU_CC_CXO_CLK>, 2423 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2424 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2425 <&gpucc GPU_CC_AHB_CLK>, 2426 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2427 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2428 clock-names = "gmu", 2429 "cxo", 2430 "axi", 2431 "memnoc", 2432 "ahb", 2433 "hub", 2434 "smmu_vote"; 2435 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2436 <&gpucc GPU_CC_GX_GDSC>; 2437 power-domain-names = "cx", 2438 "gx"; 2439 iommus = <&adreno_smmu 5 0x400>; 2440 operating-points-v2 = <&gmu_opp_table>; 2441 2442 gmu_opp_table: opp-table { 2443 compatible = "operating-points-v2"; 2444 2445 opp-200000000 { 2446 opp-hz = /bits/ 64 <200000000>; 2447 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2448 }; 2449 }; 2450 }; 2451 2452 gpucc: clock-controller@3d90000 { 2453 compatible = "qcom,sc7280-gpucc"; 2454 reg = <0 0x03d90000 0 0x9000>; 2455 clocks = <&rpmhcc RPMH_CXO_CLK>, 2456 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2457 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2458 clock-names = "bi_tcxo", 2459 "gcc_gpu_gpll0_clk_src", 2460 "gcc_gpu_gpll0_div_clk_src"; 2461 #clock-cells = <1>; 2462 #reset-cells = <1>; 2463 #power-domain-cells = <1>; 2464 }; 2465 2466 adreno_smmu: iommu@3da0000 { 2467 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2468 reg = <0 0x03da0000 0 0x20000>; 2469 #iommu-cells = <2>; 2470 #global-interrupts = <2>; 2471 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2483 2484 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2485 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2486 <&gpucc GPU_CC_AHB_CLK>, 2487 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2488 <&gpucc GPU_CC_CX_GMU_CLK>, 2489 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2490 <&gpucc GPU_CC_HUB_AON_CLK>; 2491 clock-names = "gcc_gpu_memnoc_gfx_clk", 2492 "gcc_gpu_snoc_dvm_gfx_clk", 2493 "gpu_cc_ahb_clk", 2494 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2495 "gpu_cc_cx_gmu_clk", 2496 "gpu_cc_hub_cx_int_clk", 2497 "gpu_cc_hub_aon_clk"; 2498 2499 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2500 }; 2501 2502 remoteproc_mpss: remoteproc@4080000 { 2503 compatible = "qcom,sc7280-mpss-pas"; 2504 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2505 reg-names = "qdsp6", "rmb"; 2506 2507 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2508 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2509 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2510 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2511 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2512 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2513 interrupt-names = "wdog", "fatal", "ready", "handover", 2514 "stop-ack", "shutdown-ack"; 2515 2516 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2517 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2518 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2519 <&rpmhcc RPMH_PKA_CLK>, 2520 <&rpmhcc RPMH_CXO_CLK>; 2521 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2522 2523 power-domains = <&rpmhpd SC7280_CX>, 2524 <&rpmhpd SC7280_MSS>; 2525 power-domain-names = "cx", "mss"; 2526 2527 memory-region = <&mpss_mem>; 2528 2529 qcom,qmp = <&aoss_qmp>; 2530 2531 qcom,smem-states = <&modem_smp2p_out 0>; 2532 qcom,smem-state-names = "stop"; 2533 2534 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2535 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2536 reset-names = "mss_restart", "pdc_reset"; 2537 2538 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2539 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2540 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2541 2542 status = "disabled"; 2543 2544 glink-edge { 2545 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2546 IPCC_MPROC_SIGNAL_GLINK_QMP 2547 IRQ_TYPE_EDGE_RISING>; 2548 mboxes = <&ipcc IPCC_CLIENT_MPSS 2549 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2550 label = "modem"; 2551 qcom,remote-pid = <1>; 2552 }; 2553 }; 2554 2555 stm@6002000 { 2556 compatible = "arm,coresight-stm", "arm,primecell"; 2557 reg = <0 0x06002000 0 0x1000>, 2558 <0 0x16280000 0 0x180000>; 2559 reg-names = "stm-base", "stm-stimulus-base"; 2560 2561 clocks = <&aoss_qmp>; 2562 clock-names = "apb_pclk"; 2563 2564 out-ports { 2565 port { 2566 stm_out: endpoint { 2567 remote-endpoint = <&funnel0_in7>; 2568 }; 2569 }; 2570 }; 2571 }; 2572 2573 funnel@6041000 { 2574 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2575 reg = <0 0x06041000 0 0x1000>; 2576 2577 clocks = <&aoss_qmp>; 2578 clock-names = "apb_pclk"; 2579 2580 out-ports { 2581 port { 2582 funnel0_out: endpoint { 2583 remote-endpoint = <&merge_funnel_in0>; 2584 }; 2585 }; 2586 }; 2587 2588 in-ports { 2589 #address-cells = <1>; 2590 #size-cells = <0>; 2591 2592 port@7 { 2593 reg = <7>; 2594 funnel0_in7: endpoint { 2595 remote-endpoint = <&stm_out>; 2596 }; 2597 }; 2598 }; 2599 }; 2600 2601 funnel@6042000 { 2602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2603 reg = <0 0x06042000 0 0x1000>; 2604 2605 clocks = <&aoss_qmp>; 2606 clock-names = "apb_pclk"; 2607 2608 out-ports { 2609 port { 2610 funnel1_out: endpoint { 2611 remote-endpoint = <&merge_funnel_in1>; 2612 }; 2613 }; 2614 }; 2615 2616 in-ports { 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 2620 port@4 { 2621 reg = <4>; 2622 funnel1_in4: endpoint { 2623 remote-endpoint = <&apss_merge_funnel_out>; 2624 }; 2625 }; 2626 }; 2627 }; 2628 2629 funnel@6045000 { 2630 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2631 reg = <0 0x06045000 0 0x1000>; 2632 2633 clocks = <&aoss_qmp>; 2634 clock-names = "apb_pclk"; 2635 2636 out-ports { 2637 port { 2638 merge_funnel_out: endpoint { 2639 remote-endpoint = <&swao_funnel_in>; 2640 }; 2641 }; 2642 }; 2643 2644 in-ports { 2645 #address-cells = <1>; 2646 #size-cells = <0>; 2647 2648 port@0 { 2649 reg = <0>; 2650 merge_funnel_in0: endpoint { 2651 remote-endpoint = <&funnel0_out>; 2652 }; 2653 }; 2654 2655 port@1 { 2656 reg = <1>; 2657 merge_funnel_in1: endpoint { 2658 remote-endpoint = <&funnel1_out>; 2659 }; 2660 }; 2661 }; 2662 }; 2663 2664 replicator@6046000 { 2665 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2666 reg = <0 0x06046000 0 0x1000>; 2667 2668 clocks = <&aoss_qmp>; 2669 clock-names = "apb_pclk"; 2670 2671 out-ports { 2672 port { 2673 replicator_out: endpoint { 2674 remote-endpoint = <&etr_in>; 2675 }; 2676 }; 2677 }; 2678 2679 in-ports { 2680 port { 2681 replicator_in: endpoint { 2682 remote-endpoint = <&swao_replicator_out>; 2683 }; 2684 }; 2685 }; 2686 }; 2687 2688 etr@6048000 { 2689 compatible = "arm,coresight-tmc", "arm,primecell"; 2690 reg = <0 0x06048000 0 0x1000>; 2691 iommus = <&apps_smmu 0x04c0 0>; 2692 2693 clocks = <&aoss_qmp>; 2694 clock-names = "apb_pclk"; 2695 arm,scatter-gather; 2696 2697 in-ports { 2698 port { 2699 etr_in: endpoint { 2700 remote-endpoint = <&replicator_out>; 2701 }; 2702 }; 2703 }; 2704 }; 2705 2706 funnel@6b04000 { 2707 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2708 reg = <0 0x06b04000 0 0x1000>; 2709 2710 clocks = <&aoss_qmp>; 2711 clock-names = "apb_pclk"; 2712 2713 out-ports { 2714 port { 2715 swao_funnel_out: endpoint { 2716 remote-endpoint = <&etf_in>; 2717 }; 2718 }; 2719 }; 2720 2721 in-ports { 2722 #address-cells = <1>; 2723 #size-cells = <0>; 2724 2725 port@7 { 2726 reg = <7>; 2727 swao_funnel_in: endpoint { 2728 remote-endpoint = <&merge_funnel_out>; 2729 }; 2730 }; 2731 }; 2732 }; 2733 2734 etf@6b05000 { 2735 compatible = "arm,coresight-tmc", "arm,primecell"; 2736 reg = <0 0x06b05000 0 0x1000>; 2737 2738 clocks = <&aoss_qmp>; 2739 clock-names = "apb_pclk"; 2740 2741 out-ports { 2742 port { 2743 etf_out: endpoint { 2744 remote-endpoint = <&swao_replicator_in>; 2745 }; 2746 }; 2747 }; 2748 2749 in-ports { 2750 port { 2751 etf_in: endpoint { 2752 remote-endpoint = <&swao_funnel_out>; 2753 }; 2754 }; 2755 }; 2756 }; 2757 2758 replicator@6b06000 { 2759 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2760 reg = <0 0x06b06000 0 0x1000>; 2761 2762 clocks = <&aoss_qmp>; 2763 clock-names = "apb_pclk"; 2764 qcom,replicator-loses-context; 2765 2766 out-ports { 2767 port { 2768 swao_replicator_out: endpoint { 2769 remote-endpoint = <&replicator_in>; 2770 }; 2771 }; 2772 }; 2773 2774 in-ports { 2775 port { 2776 swao_replicator_in: endpoint { 2777 remote-endpoint = <&etf_out>; 2778 }; 2779 }; 2780 }; 2781 }; 2782 2783 etm@7040000 { 2784 compatible = "arm,coresight-etm4x", "arm,primecell"; 2785 reg = <0 0x07040000 0 0x1000>; 2786 2787 cpu = <&CPU0>; 2788 2789 clocks = <&aoss_qmp>; 2790 clock-names = "apb_pclk"; 2791 arm,coresight-loses-context-with-cpu; 2792 qcom,skip-power-up; 2793 2794 out-ports { 2795 port { 2796 etm0_out: endpoint { 2797 remote-endpoint = <&apss_funnel_in0>; 2798 }; 2799 }; 2800 }; 2801 }; 2802 2803 etm@7140000 { 2804 compatible = "arm,coresight-etm4x", "arm,primecell"; 2805 reg = <0 0x07140000 0 0x1000>; 2806 2807 cpu = <&CPU1>; 2808 2809 clocks = <&aoss_qmp>; 2810 clock-names = "apb_pclk"; 2811 arm,coresight-loses-context-with-cpu; 2812 qcom,skip-power-up; 2813 2814 out-ports { 2815 port { 2816 etm1_out: endpoint { 2817 remote-endpoint = <&apss_funnel_in1>; 2818 }; 2819 }; 2820 }; 2821 }; 2822 2823 etm@7240000 { 2824 compatible = "arm,coresight-etm4x", "arm,primecell"; 2825 reg = <0 0x07240000 0 0x1000>; 2826 2827 cpu = <&CPU2>; 2828 2829 clocks = <&aoss_qmp>; 2830 clock-names = "apb_pclk"; 2831 arm,coresight-loses-context-with-cpu; 2832 qcom,skip-power-up; 2833 2834 out-ports { 2835 port { 2836 etm2_out: endpoint { 2837 remote-endpoint = <&apss_funnel_in2>; 2838 }; 2839 }; 2840 }; 2841 }; 2842 2843 etm@7340000 { 2844 compatible = "arm,coresight-etm4x", "arm,primecell"; 2845 reg = <0 0x07340000 0 0x1000>; 2846 2847 cpu = <&CPU3>; 2848 2849 clocks = <&aoss_qmp>; 2850 clock-names = "apb_pclk"; 2851 arm,coresight-loses-context-with-cpu; 2852 qcom,skip-power-up; 2853 2854 out-ports { 2855 port { 2856 etm3_out: endpoint { 2857 remote-endpoint = <&apss_funnel_in3>; 2858 }; 2859 }; 2860 }; 2861 }; 2862 2863 etm@7440000 { 2864 compatible = "arm,coresight-etm4x", "arm,primecell"; 2865 reg = <0 0x07440000 0 0x1000>; 2866 2867 cpu = <&CPU4>; 2868 2869 clocks = <&aoss_qmp>; 2870 clock-names = "apb_pclk"; 2871 arm,coresight-loses-context-with-cpu; 2872 qcom,skip-power-up; 2873 2874 out-ports { 2875 port { 2876 etm4_out: endpoint { 2877 remote-endpoint = <&apss_funnel_in4>; 2878 }; 2879 }; 2880 }; 2881 }; 2882 2883 etm@7540000 { 2884 compatible = "arm,coresight-etm4x", "arm,primecell"; 2885 reg = <0 0x07540000 0 0x1000>; 2886 2887 cpu = <&CPU5>; 2888 2889 clocks = <&aoss_qmp>; 2890 clock-names = "apb_pclk"; 2891 arm,coresight-loses-context-with-cpu; 2892 qcom,skip-power-up; 2893 2894 out-ports { 2895 port { 2896 etm5_out: endpoint { 2897 remote-endpoint = <&apss_funnel_in5>; 2898 }; 2899 }; 2900 }; 2901 }; 2902 2903 etm@7640000 { 2904 compatible = "arm,coresight-etm4x", "arm,primecell"; 2905 reg = <0 0x07640000 0 0x1000>; 2906 2907 cpu = <&CPU6>; 2908 2909 clocks = <&aoss_qmp>; 2910 clock-names = "apb_pclk"; 2911 arm,coresight-loses-context-with-cpu; 2912 qcom,skip-power-up; 2913 2914 out-ports { 2915 port { 2916 etm6_out: endpoint { 2917 remote-endpoint = <&apss_funnel_in6>; 2918 }; 2919 }; 2920 }; 2921 }; 2922 2923 etm@7740000 { 2924 compatible = "arm,coresight-etm4x", "arm,primecell"; 2925 reg = <0 0x07740000 0 0x1000>; 2926 2927 cpu = <&CPU7>; 2928 2929 clocks = <&aoss_qmp>; 2930 clock-names = "apb_pclk"; 2931 arm,coresight-loses-context-with-cpu; 2932 qcom,skip-power-up; 2933 2934 out-ports { 2935 port { 2936 etm7_out: endpoint { 2937 remote-endpoint = <&apss_funnel_in7>; 2938 }; 2939 }; 2940 }; 2941 }; 2942 2943 funnel@7800000 { /* APSS Funnel */ 2944 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2945 reg = <0 0x07800000 0 0x1000>; 2946 2947 clocks = <&aoss_qmp>; 2948 clock-names = "apb_pclk"; 2949 2950 out-ports { 2951 port { 2952 apss_funnel_out: endpoint { 2953 remote-endpoint = <&apss_merge_funnel_in>; 2954 }; 2955 }; 2956 }; 2957 2958 in-ports { 2959 #address-cells = <1>; 2960 #size-cells = <0>; 2961 2962 port@0 { 2963 reg = <0>; 2964 apss_funnel_in0: endpoint { 2965 remote-endpoint = <&etm0_out>; 2966 }; 2967 }; 2968 2969 port@1 { 2970 reg = <1>; 2971 apss_funnel_in1: endpoint { 2972 remote-endpoint = <&etm1_out>; 2973 }; 2974 }; 2975 2976 port@2 { 2977 reg = <2>; 2978 apss_funnel_in2: endpoint { 2979 remote-endpoint = <&etm2_out>; 2980 }; 2981 }; 2982 2983 port@3 { 2984 reg = <3>; 2985 apss_funnel_in3: endpoint { 2986 remote-endpoint = <&etm3_out>; 2987 }; 2988 }; 2989 2990 port@4 { 2991 reg = <4>; 2992 apss_funnel_in4: endpoint { 2993 remote-endpoint = <&etm4_out>; 2994 }; 2995 }; 2996 2997 port@5 { 2998 reg = <5>; 2999 apss_funnel_in5: endpoint { 3000 remote-endpoint = <&etm5_out>; 3001 }; 3002 }; 3003 3004 port@6 { 3005 reg = <6>; 3006 apss_funnel_in6: endpoint { 3007 remote-endpoint = <&etm6_out>; 3008 }; 3009 }; 3010 3011 port@7 { 3012 reg = <7>; 3013 apss_funnel_in7: endpoint { 3014 remote-endpoint = <&etm7_out>; 3015 }; 3016 }; 3017 }; 3018 }; 3019 3020 funnel@7810000 { 3021 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3022 reg = <0 0x07810000 0 0x1000>; 3023 3024 clocks = <&aoss_qmp>; 3025 clock-names = "apb_pclk"; 3026 3027 out-ports { 3028 port { 3029 apss_merge_funnel_out: endpoint { 3030 remote-endpoint = <&funnel1_in4>; 3031 }; 3032 }; 3033 }; 3034 3035 in-ports { 3036 port { 3037 apss_merge_funnel_in: endpoint { 3038 remote-endpoint = <&apss_funnel_out>; 3039 }; 3040 }; 3041 }; 3042 }; 3043 3044 sdhc_2: mmc@8804000 { 3045 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3046 pinctrl-names = "default", "sleep"; 3047 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3048 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3049 status = "disabled"; 3050 3051 reg = <0 0x08804000 0 0x1000>; 3052 3053 iommus = <&apps_smmu 0x100 0x0>; 3054 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3056 interrupt-names = "hc_irq", "pwr_irq"; 3057 3058 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3059 <&gcc GCC_SDCC2_APPS_CLK>, 3060 <&rpmhcc RPMH_CXO_CLK>; 3061 clock-names = "iface", "core", "xo"; 3062 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3063 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3064 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3065 power-domains = <&rpmhpd SC7280_CX>; 3066 operating-points-v2 = <&sdhc2_opp_table>; 3067 3068 bus-width = <4>; 3069 3070 qcom,dll-config = <0x0007642c>; 3071 3072 resets = <&gcc GCC_SDCC2_BCR>; 3073 3074 sdhc2_opp_table: opp-table { 3075 compatible = "operating-points-v2"; 3076 3077 opp-100000000 { 3078 opp-hz = /bits/ 64 <100000000>; 3079 required-opps = <&rpmhpd_opp_low_svs>; 3080 opp-peak-kBps = <1800000 400000>; 3081 opp-avg-kBps = <100000 0>; 3082 }; 3083 3084 opp-202000000 { 3085 opp-hz = /bits/ 64 <202000000>; 3086 required-opps = <&rpmhpd_opp_nom>; 3087 opp-peak-kBps = <5400000 1600000>; 3088 opp-avg-kBps = <200000 0>; 3089 }; 3090 }; 3091 3092 }; 3093 3094 usb_1_hsphy: phy@88e3000 { 3095 compatible = "qcom,sc7280-usb-hs-phy", 3096 "qcom,usb-snps-hs-7nm-phy"; 3097 reg = <0 0x088e3000 0 0x400>; 3098 status = "disabled"; 3099 #phy-cells = <0>; 3100 3101 clocks = <&rpmhcc RPMH_CXO_CLK>; 3102 clock-names = "ref"; 3103 3104 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3105 }; 3106 3107 usb_2_hsphy: phy@88e4000 { 3108 compatible = "qcom,sc7280-usb-hs-phy", 3109 "qcom,usb-snps-hs-7nm-phy"; 3110 reg = <0 0x088e4000 0 0x400>; 3111 status = "disabled"; 3112 #phy-cells = <0>; 3113 3114 clocks = <&rpmhcc RPMH_CXO_CLK>; 3115 clock-names = "ref"; 3116 3117 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3118 }; 3119 3120 usb_1_qmpphy: phy-wrapper@88e9000 { 3121 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3122 "qcom,sm8250-qmp-usb3-dp-phy"; 3123 reg = <0 0x088e9000 0 0x200>, 3124 <0 0x088e8000 0 0x40>, 3125 <0 0x088ea000 0 0x200>; 3126 status = "disabled"; 3127 #address-cells = <2>; 3128 #size-cells = <2>; 3129 ranges; 3130 3131 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3132 <&rpmhcc RPMH_CXO_CLK>, 3133 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3134 clock-names = "aux", "ref_clk_src", "com_aux"; 3135 3136 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3137 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3138 reset-names = "phy", "common"; 3139 3140 usb_1_ssphy: usb3-phy@88e9200 { 3141 reg = <0 0x088e9200 0 0x200>, 3142 <0 0x088e9400 0 0x200>, 3143 <0 0x088e9c00 0 0x400>, 3144 <0 0x088e9600 0 0x200>, 3145 <0 0x088e9800 0 0x200>, 3146 <0 0x088e9a00 0 0x100>; 3147 #clock-cells = <0>; 3148 #phy-cells = <0>; 3149 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3150 clock-names = "pipe0"; 3151 clock-output-names = "usb3_phy_pipe_clk_src"; 3152 }; 3153 3154 dp_phy: dp-phy@88ea200 { 3155 reg = <0 0x088ea200 0 0x200>, 3156 <0 0x088ea400 0 0x200>, 3157 <0 0x088eaa00 0 0x200>, 3158 <0 0x088ea600 0 0x200>, 3159 <0 0x088ea800 0 0x200>; 3160 #phy-cells = <0>; 3161 #clock-cells = <1>; 3162 }; 3163 }; 3164 3165 usb_2: usb@8cf8800 { 3166 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3167 reg = <0 0x08cf8800 0 0x400>; 3168 status = "disabled"; 3169 #address-cells = <2>; 3170 #size-cells = <2>; 3171 ranges; 3172 dma-ranges; 3173 3174 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3175 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3176 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3177 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3178 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3179 clock-names = "cfg_noc", 3180 "core", 3181 "iface", 3182 "sleep", 3183 "mock_utmi"; 3184 3185 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3186 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3187 assigned-clock-rates = <19200000>, <200000000>; 3188 3189 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3190 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3191 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3192 interrupt-names = "hs_phy_irq", 3193 "dp_hs_phy_irq", 3194 "dm_hs_phy_irq"; 3195 3196 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3197 3198 resets = <&gcc GCC_USB30_SEC_BCR>; 3199 3200 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3202 interconnect-names = "usb-ddr", "apps-usb"; 3203 3204 usb_2_dwc3: usb@8c00000 { 3205 compatible = "snps,dwc3"; 3206 reg = <0 0x08c00000 0 0xe000>; 3207 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3208 iommus = <&apps_smmu 0xa0 0x0>; 3209 snps,dis_u2_susphy_quirk; 3210 snps,dis_enblslpm_quirk; 3211 phys = <&usb_2_hsphy>; 3212 phy-names = "usb2-phy"; 3213 maximum-speed = "high-speed"; 3214 usb-role-switch; 3215 port { 3216 usb2_role_switch: endpoint { 3217 remote-endpoint = <&eud_ep>; 3218 }; 3219 }; 3220 }; 3221 }; 3222 3223 qspi: spi@88dc000 { 3224 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3225 reg = <0 0x088dc000 0 0x1000>; 3226 #address-cells = <1>; 3227 #size-cells = <0>; 3228 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3229 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3230 <&gcc GCC_QSPI_CORE_CLK>; 3231 clock-names = "iface", "core"; 3232 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3233 &cnoc2 SLAVE_QSPI_0 0>; 3234 interconnect-names = "qspi-config"; 3235 power-domains = <&rpmhpd SC7280_CX>; 3236 operating-points-v2 = <&qspi_opp_table>; 3237 status = "disabled"; 3238 }; 3239 3240 remoteproc_wpss: remoteproc@8a00000 { 3241 compatible = "qcom,sc7280-wpss-pil"; 3242 reg = <0 0x08a00000 0 0x10000>; 3243 3244 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3245 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3246 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3247 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3248 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3249 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3250 interrupt-names = "wdog", "fatal", "ready", "handover", 3251 "stop-ack", "shutdown-ack"; 3252 3253 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3254 <&gcc GCC_WPSS_AHB_CLK>, 3255 <&gcc GCC_WPSS_RSCP_CLK>, 3256 <&rpmhcc RPMH_CXO_CLK>; 3257 clock-names = "ahb_bdg", "ahb", 3258 "rscp", "xo"; 3259 3260 power-domains = <&rpmhpd SC7280_CX>, 3261 <&rpmhpd SC7280_MX>; 3262 power-domain-names = "cx", "mx"; 3263 3264 memory-region = <&wpss_mem>; 3265 3266 qcom,qmp = <&aoss_qmp>; 3267 3268 qcom,smem-states = <&wpss_smp2p_out 0>; 3269 qcom,smem-state-names = "stop"; 3270 3271 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3272 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3273 reset-names = "restart", "pdc_sync"; 3274 3275 qcom,halt-regs = <&tcsr_1 0x17000>; 3276 3277 status = "disabled"; 3278 3279 glink-edge { 3280 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3281 IPCC_MPROC_SIGNAL_GLINK_QMP 3282 IRQ_TYPE_EDGE_RISING>; 3283 mboxes = <&ipcc IPCC_CLIENT_WPSS 3284 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3285 3286 label = "wpss"; 3287 qcom,remote-pid = <13>; 3288 }; 3289 }; 3290 3291 dc_noc: interconnect@90e0000 { 3292 reg = <0 0x090e0000 0 0x5080>; 3293 compatible = "qcom,sc7280-dc-noc"; 3294 #interconnect-cells = <2>; 3295 qcom,bcm-voters = <&apps_bcm_voter>; 3296 }; 3297 3298 gem_noc: interconnect@9100000 { 3299 reg = <0 0x9100000 0 0xe2200>; 3300 compatible = "qcom,sc7280-gem-noc"; 3301 #interconnect-cells = <2>; 3302 qcom,bcm-voters = <&apps_bcm_voter>; 3303 }; 3304 3305 system-cache-controller@9200000 { 3306 compatible = "qcom,sc7280-llcc"; 3307 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3308 reg-names = "llcc_base", "llcc_broadcast_base"; 3309 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3310 }; 3311 3312 eud: eud@88e0000 { 3313 compatible = "qcom,sc7280-eud","qcom,eud"; 3314 reg = <0 0x88e0000 0 0x2000>, 3315 <0 0x88e2000 0 0x1000>; 3316 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3317 ports { 3318 port@0 { 3319 eud_ep: endpoint { 3320 remote-endpoint = <&usb2_role_switch>; 3321 }; 3322 }; 3323 port@1 { 3324 eud_con: endpoint { 3325 remote-endpoint = <&con_eud>; 3326 }; 3327 }; 3328 }; 3329 }; 3330 3331 eud_typec: connector { 3332 compatible = "usb-c-connector"; 3333 ports { 3334 port@0 { 3335 con_eud: endpoint { 3336 remote-endpoint = <&eud_con>; 3337 }; 3338 }; 3339 }; 3340 }; 3341 3342 nsp_noc: interconnect@a0c0000 { 3343 reg = <0 0x0a0c0000 0 0x10000>; 3344 compatible = "qcom,sc7280-nsp-noc"; 3345 #interconnect-cells = <2>; 3346 qcom,bcm-voters = <&apps_bcm_voter>; 3347 }; 3348 3349 usb_1: usb@a6f8800 { 3350 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3351 reg = <0 0x0a6f8800 0 0x400>; 3352 status = "disabled"; 3353 #address-cells = <2>; 3354 #size-cells = <2>; 3355 ranges; 3356 dma-ranges; 3357 3358 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3359 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3360 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3361 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3362 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3363 clock-names = "cfg_noc", 3364 "core", 3365 "iface", 3366 "sleep", 3367 "mock_utmi"; 3368 3369 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3370 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3371 assigned-clock-rates = <19200000>, <200000000>; 3372 3373 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3374 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3375 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3376 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3377 interrupt-names = "hs_phy_irq", 3378 "dp_hs_phy_irq", 3379 "dm_hs_phy_irq", 3380 "ss_phy_irq"; 3381 3382 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3383 3384 resets = <&gcc GCC_USB30_PRIM_BCR>; 3385 3386 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3387 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3388 interconnect-names = "usb-ddr", "apps-usb"; 3389 3390 usb_1_dwc3: usb@a600000 { 3391 compatible = "snps,dwc3"; 3392 reg = <0 0x0a600000 0 0xe000>; 3393 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3394 iommus = <&apps_smmu 0xe0 0x0>; 3395 snps,dis_u2_susphy_quirk; 3396 snps,dis_enblslpm_quirk; 3397 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3398 phy-names = "usb2-phy", "usb3-phy"; 3399 maximum-speed = "super-speed"; 3400 wakeup-source; 3401 }; 3402 }; 3403 3404 venus: video-codec@aa00000 { 3405 compatible = "qcom,sc7280-venus"; 3406 reg = <0 0x0aa00000 0 0xd0600>; 3407 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3408 3409 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3410 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3411 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3412 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3413 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3414 clock-names = "core", "bus", "iface", 3415 "vcodec_core", "vcodec_bus"; 3416 3417 power-domains = <&videocc MVSC_GDSC>, 3418 <&videocc MVS0_GDSC>, 3419 <&rpmhpd SC7280_CX>; 3420 power-domain-names = "venus", "vcodec0", "cx"; 3421 operating-points-v2 = <&venus_opp_table>; 3422 3423 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3424 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3425 interconnect-names = "cpu-cfg", "video-mem"; 3426 3427 iommus = <&apps_smmu 0x2180 0x20>, 3428 <&apps_smmu 0x2184 0x20>; 3429 memory-region = <&video_mem>; 3430 3431 video-decoder { 3432 compatible = "venus-decoder"; 3433 }; 3434 3435 video-encoder { 3436 compatible = "venus-encoder"; 3437 }; 3438 3439 video-firmware { 3440 iommus = <&apps_smmu 0x21a2 0x0>; 3441 }; 3442 3443 venus_opp_table: opp-table { 3444 compatible = "operating-points-v2"; 3445 3446 opp-133330000 { 3447 opp-hz = /bits/ 64 <133330000>; 3448 required-opps = <&rpmhpd_opp_low_svs>; 3449 }; 3450 3451 opp-240000000 { 3452 opp-hz = /bits/ 64 <240000000>; 3453 required-opps = <&rpmhpd_opp_svs>; 3454 }; 3455 3456 opp-335000000 { 3457 opp-hz = /bits/ 64 <335000000>; 3458 required-opps = <&rpmhpd_opp_svs_l1>; 3459 }; 3460 3461 opp-424000000 { 3462 opp-hz = /bits/ 64 <424000000>; 3463 required-opps = <&rpmhpd_opp_nom>; 3464 }; 3465 3466 opp-460000048 { 3467 opp-hz = /bits/ 64 <460000048>; 3468 required-opps = <&rpmhpd_opp_turbo>; 3469 }; 3470 }; 3471 3472 }; 3473 3474 videocc: clock-controller@aaf0000 { 3475 compatible = "qcom,sc7280-videocc"; 3476 reg = <0 0xaaf0000 0 0x10000>; 3477 clocks = <&rpmhcc RPMH_CXO_CLK>, 3478 <&rpmhcc RPMH_CXO_CLK_A>; 3479 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3480 #clock-cells = <1>; 3481 #reset-cells = <1>; 3482 #power-domain-cells = <1>; 3483 }; 3484 3485 camcc: clock-controller@ad00000 { 3486 compatible = "qcom,sc7280-camcc"; 3487 reg = <0 0x0ad00000 0 0x10000>; 3488 clocks = <&rpmhcc RPMH_CXO_CLK>, 3489 <&rpmhcc RPMH_CXO_CLK_A>, 3490 <&sleep_clk>; 3491 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3492 #clock-cells = <1>; 3493 #reset-cells = <1>; 3494 #power-domain-cells = <1>; 3495 }; 3496 3497 dispcc: clock-controller@af00000 { 3498 compatible = "qcom,sc7280-dispcc"; 3499 reg = <0 0xaf00000 0 0x20000>; 3500 clocks = <&rpmhcc RPMH_CXO_CLK>, 3501 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3502 <&mdss_dsi_phy 0>, 3503 <&mdss_dsi_phy 1>, 3504 <&dp_phy 0>, 3505 <&dp_phy 1>, 3506 <&mdss_edp_phy 0>, 3507 <&mdss_edp_phy 1>; 3508 clock-names = "bi_tcxo", 3509 "gcc_disp_gpll0_clk", 3510 "dsi0_phy_pll_out_byteclk", 3511 "dsi0_phy_pll_out_dsiclk", 3512 "dp_phy_pll_link_clk", 3513 "dp_phy_pll_vco_div_clk", 3514 "edp_phy_pll_link_clk", 3515 "edp_phy_pll_vco_div_clk"; 3516 #clock-cells = <1>; 3517 #reset-cells = <1>; 3518 #power-domain-cells = <1>; 3519 }; 3520 3521 mdss: display-subsystem@ae00000 { 3522 compatible = "qcom,sc7280-mdss"; 3523 reg = <0 0x0ae00000 0 0x1000>; 3524 reg-names = "mdss"; 3525 3526 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3527 3528 clocks = <&gcc GCC_DISP_AHB_CLK>, 3529 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3530 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3531 clock-names = "iface", 3532 "ahb", 3533 "core"; 3534 3535 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3536 interrupt-controller; 3537 #interrupt-cells = <1>; 3538 3539 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3540 interconnect-names = "mdp0-mem"; 3541 3542 iommus = <&apps_smmu 0x900 0x402>; 3543 3544 #address-cells = <2>; 3545 #size-cells = <2>; 3546 ranges; 3547 3548 status = "disabled"; 3549 3550 mdss_mdp: display-controller@ae01000 { 3551 compatible = "qcom,sc7280-dpu"; 3552 reg = <0 0x0ae01000 0 0x8f030>, 3553 <0 0x0aeb0000 0 0x2008>; 3554 reg-names = "mdp", "vbif"; 3555 3556 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3557 <&gcc GCC_DISP_SF_AXI_CLK>, 3558 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3559 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3560 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3561 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3562 clock-names = "bus", 3563 "nrt_bus", 3564 "iface", 3565 "lut", 3566 "core", 3567 "vsync"; 3568 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3569 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3570 assigned-clock-rates = <19200000>, 3571 <19200000>; 3572 operating-points-v2 = <&mdp_opp_table>; 3573 power-domains = <&rpmhpd SC7280_CX>; 3574 3575 interrupt-parent = <&mdss>; 3576 interrupts = <0>; 3577 3578 status = "disabled"; 3579 3580 ports { 3581 #address-cells = <1>; 3582 #size-cells = <0>; 3583 3584 port@0 { 3585 reg = <0>; 3586 dpu_intf1_out: endpoint { 3587 remote-endpoint = <&dsi0_in>; 3588 }; 3589 }; 3590 3591 port@1 { 3592 reg = <1>; 3593 dpu_intf5_out: endpoint { 3594 remote-endpoint = <&edp_in>; 3595 }; 3596 }; 3597 3598 port@2 { 3599 reg = <2>; 3600 dpu_intf0_out: endpoint { 3601 remote-endpoint = <&dp_in>; 3602 }; 3603 }; 3604 }; 3605 3606 mdp_opp_table: opp-table { 3607 compatible = "operating-points-v2"; 3608 3609 opp-200000000 { 3610 opp-hz = /bits/ 64 <200000000>; 3611 required-opps = <&rpmhpd_opp_low_svs>; 3612 }; 3613 3614 opp-300000000 { 3615 opp-hz = /bits/ 64 <300000000>; 3616 required-opps = <&rpmhpd_opp_svs>; 3617 }; 3618 3619 opp-380000000 { 3620 opp-hz = /bits/ 64 <380000000>; 3621 required-opps = <&rpmhpd_opp_svs_l1>; 3622 }; 3623 3624 opp-506666667 { 3625 opp-hz = /bits/ 64 <506666667>; 3626 required-opps = <&rpmhpd_opp_nom>; 3627 }; 3628 }; 3629 }; 3630 3631 mdss_dsi: dsi@ae94000 { 3632 compatible = "qcom,mdss-dsi-ctrl"; 3633 reg = <0 0x0ae94000 0 0x400>; 3634 reg-names = "dsi_ctrl"; 3635 3636 interrupt-parent = <&mdss>; 3637 interrupts = <4>; 3638 3639 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3640 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3641 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3642 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3643 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3644 <&gcc GCC_DISP_HF_AXI_CLK>; 3645 clock-names = "byte", 3646 "byte_intf", 3647 "pixel", 3648 "core", 3649 "iface", 3650 "bus"; 3651 3652 operating-points-v2 = <&dsi_opp_table>; 3653 power-domains = <&rpmhpd SC7280_CX>; 3654 3655 phys = <&mdss_dsi_phy>; 3656 phy-names = "dsi"; 3657 3658 #address-cells = <1>; 3659 #size-cells = <0>; 3660 3661 status = "disabled"; 3662 3663 ports { 3664 #address-cells = <1>; 3665 #size-cells = <0>; 3666 3667 port@0 { 3668 reg = <0>; 3669 dsi0_in: endpoint { 3670 remote-endpoint = <&dpu_intf1_out>; 3671 }; 3672 }; 3673 3674 port@1 { 3675 reg = <1>; 3676 dsi0_out: endpoint { 3677 }; 3678 }; 3679 }; 3680 3681 dsi_opp_table: opp-table { 3682 compatible = "operating-points-v2"; 3683 3684 opp-187500000 { 3685 opp-hz = /bits/ 64 <187500000>; 3686 required-opps = <&rpmhpd_opp_low_svs>; 3687 }; 3688 3689 opp-300000000 { 3690 opp-hz = /bits/ 64 <300000000>; 3691 required-opps = <&rpmhpd_opp_svs>; 3692 }; 3693 3694 opp-358000000 { 3695 opp-hz = /bits/ 64 <358000000>; 3696 required-opps = <&rpmhpd_opp_svs_l1>; 3697 }; 3698 }; 3699 }; 3700 3701 mdss_dsi_phy: phy@ae94400 { 3702 compatible = "qcom,sc7280-dsi-phy-7nm"; 3703 reg = <0 0x0ae94400 0 0x200>, 3704 <0 0x0ae94600 0 0x280>, 3705 <0 0x0ae94900 0 0x280>; 3706 reg-names = "dsi_phy", 3707 "dsi_phy_lane", 3708 "dsi_pll"; 3709 3710 #clock-cells = <1>; 3711 #phy-cells = <0>; 3712 3713 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3714 <&rpmhcc RPMH_CXO_CLK>; 3715 clock-names = "iface", "ref"; 3716 3717 status = "disabled"; 3718 }; 3719 3720 mdss_edp: edp@aea0000 { 3721 compatible = "qcom,sc7280-edp"; 3722 pinctrl-names = "default"; 3723 pinctrl-0 = <&edp_hot_plug_det>; 3724 3725 reg = <0 0xaea0000 0 0x200>, 3726 <0 0xaea0200 0 0x200>, 3727 <0 0xaea0400 0 0xc00>, 3728 <0 0xaea1000 0 0x400>; 3729 3730 interrupt-parent = <&mdss>; 3731 interrupts = <14>; 3732 3733 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3734 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3735 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3736 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3737 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3738 clock-names = "core_iface", 3739 "core_aux", 3740 "ctrl_link", 3741 "ctrl_link_iface", 3742 "stream_pixel"; 3743 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3744 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3745 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3746 3747 phys = <&mdss_edp_phy>; 3748 phy-names = "dp"; 3749 3750 operating-points-v2 = <&edp_opp_table>; 3751 power-domains = <&rpmhpd SC7280_CX>; 3752 3753 status = "disabled"; 3754 3755 ports { 3756 #address-cells = <1>; 3757 #size-cells = <0>; 3758 3759 port@0 { 3760 reg = <0>; 3761 edp_in: endpoint { 3762 remote-endpoint = <&dpu_intf5_out>; 3763 }; 3764 }; 3765 3766 port@1 { 3767 reg = <1>; 3768 mdss_edp_out: endpoint { }; 3769 }; 3770 }; 3771 3772 edp_opp_table: opp-table { 3773 compatible = "operating-points-v2"; 3774 3775 opp-160000000 { 3776 opp-hz = /bits/ 64 <160000000>; 3777 required-opps = <&rpmhpd_opp_low_svs>; 3778 }; 3779 3780 opp-270000000 { 3781 opp-hz = /bits/ 64 <270000000>; 3782 required-opps = <&rpmhpd_opp_svs>; 3783 }; 3784 3785 opp-540000000 { 3786 opp-hz = /bits/ 64 <540000000>; 3787 required-opps = <&rpmhpd_opp_nom>; 3788 }; 3789 3790 opp-810000000 { 3791 opp-hz = /bits/ 64 <810000000>; 3792 required-opps = <&rpmhpd_opp_nom>; 3793 }; 3794 }; 3795 }; 3796 3797 mdss_edp_phy: phy@aec2a00 { 3798 compatible = "qcom,sc7280-edp-phy"; 3799 3800 reg = <0 0xaec2a00 0 0x19c>, 3801 <0 0xaec2200 0 0xa0>, 3802 <0 0xaec2600 0 0xa0>, 3803 <0 0xaec2000 0 0x1c0>; 3804 3805 clocks = <&rpmhcc RPMH_CXO_CLK>, 3806 <&gcc GCC_EDP_CLKREF_EN>; 3807 clock-names = "aux", 3808 "cfg_ahb"; 3809 3810 #clock-cells = <1>; 3811 #phy-cells = <0>; 3812 3813 status = "disabled"; 3814 }; 3815 3816 mdss_dp: displayport-controller@ae90000 { 3817 compatible = "qcom,sc7280-dp"; 3818 3819 reg = <0 0xae90000 0 0x200>, 3820 <0 0xae90200 0 0x200>, 3821 <0 0xae90400 0 0xc00>, 3822 <0 0xae91000 0 0x400>, 3823 <0 0xae91400 0 0x400>; 3824 3825 interrupt-parent = <&mdss>; 3826 interrupts = <12>; 3827 3828 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3829 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3830 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3831 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3832 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3833 clock-names = "core_iface", 3834 "core_aux", 3835 "ctrl_link", 3836 "ctrl_link_iface", 3837 "stream_pixel"; 3838 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3839 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3840 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3841 phys = <&dp_phy>; 3842 phy-names = "dp"; 3843 3844 operating-points-v2 = <&dp_opp_table>; 3845 power-domains = <&rpmhpd SC7280_CX>; 3846 3847 #sound-dai-cells = <0>; 3848 3849 status = "disabled"; 3850 3851 ports { 3852 #address-cells = <1>; 3853 #size-cells = <0>; 3854 3855 port@0 { 3856 reg = <0>; 3857 dp_in: endpoint { 3858 remote-endpoint = <&dpu_intf0_out>; 3859 }; 3860 }; 3861 3862 port@1 { 3863 reg = <1>; 3864 dp_out: endpoint { }; 3865 }; 3866 }; 3867 3868 dp_opp_table: opp-table { 3869 compatible = "operating-points-v2"; 3870 3871 opp-160000000 { 3872 opp-hz = /bits/ 64 <160000000>; 3873 required-opps = <&rpmhpd_opp_low_svs>; 3874 }; 3875 3876 opp-270000000 { 3877 opp-hz = /bits/ 64 <270000000>; 3878 required-opps = <&rpmhpd_opp_svs>; 3879 }; 3880 3881 opp-540000000 { 3882 opp-hz = /bits/ 64 <540000000>; 3883 required-opps = <&rpmhpd_opp_svs_l1>; 3884 }; 3885 3886 opp-810000000 { 3887 opp-hz = /bits/ 64 <810000000>; 3888 required-opps = <&rpmhpd_opp_nom>; 3889 }; 3890 }; 3891 }; 3892 }; 3893 3894 pdc: interrupt-controller@b220000 { 3895 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3896 reg = <0 0x0b220000 0 0x30000>; 3897 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3898 <55 306 4>, <59 312 3>, <62 374 2>, 3899 <64 434 2>, <66 438 3>, <69 86 1>, 3900 <70 520 54>, <124 609 31>, <155 63 1>, 3901 <156 716 12>; 3902 #interrupt-cells = <2>; 3903 interrupt-parent = <&intc>; 3904 interrupt-controller; 3905 }; 3906 3907 pdc_reset: reset-controller@b5e0000 { 3908 compatible = "qcom,sc7280-pdc-global"; 3909 reg = <0 0x0b5e0000 0 0x20000>; 3910 #reset-cells = <1>; 3911 }; 3912 3913 tsens0: thermal-sensor@c263000 { 3914 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3915 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3916 <0 0x0c222000 0 0x1ff>; /* SROT */ 3917 #qcom,sensors = <15>; 3918 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3920 interrupt-names = "uplow","critical"; 3921 #thermal-sensor-cells = <1>; 3922 }; 3923 3924 tsens1: thermal-sensor@c265000 { 3925 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3926 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3927 <0 0x0c223000 0 0x1ff>; /* SROT */ 3928 #qcom,sensors = <12>; 3929 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3931 interrupt-names = "uplow","critical"; 3932 #thermal-sensor-cells = <1>; 3933 }; 3934 3935 aoss_reset: reset-controller@c2a0000 { 3936 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3937 reg = <0 0x0c2a0000 0 0x31000>; 3938 #reset-cells = <1>; 3939 }; 3940 3941 aoss_qmp: power-controller@c300000 { 3942 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 3943 reg = <0 0x0c300000 0 0x400>; 3944 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3945 IPCC_MPROC_SIGNAL_GLINK_QMP 3946 IRQ_TYPE_EDGE_RISING>; 3947 mboxes = <&ipcc IPCC_CLIENT_AOP 3948 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3949 3950 #clock-cells = <0>; 3951 }; 3952 3953 sram@c3f0000 { 3954 compatible = "qcom,rpmh-stats"; 3955 reg = <0 0x0c3f0000 0 0x400>; 3956 }; 3957 3958 spmi_bus: spmi@c440000 { 3959 compatible = "qcom,spmi-pmic-arb"; 3960 reg = <0 0x0c440000 0 0x1100>, 3961 <0 0x0c600000 0 0x2000000>, 3962 <0 0x0e600000 0 0x100000>, 3963 <0 0x0e700000 0 0xa0000>, 3964 <0 0x0c40a000 0 0x26000>; 3965 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3966 interrupt-names = "periph_irq"; 3967 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3968 qcom,ee = <0>; 3969 qcom,channel = <0>; 3970 #address-cells = <1>; 3971 #size-cells = <1>; 3972 interrupt-controller; 3973 #interrupt-cells = <4>; 3974 }; 3975 3976 tlmm: pinctrl@f100000 { 3977 compatible = "qcom,sc7280-pinctrl"; 3978 reg = <0 0x0f100000 0 0x300000>; 3979 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3980 gpio-controller; 3981 #gpio-cells = <2>; 3982 interrupt-controller; 3983 #interrupt-cells = <2>; 3984 gpio-ranges = <&tlmm 0 0 175>; 3985 wakeup-parent = <&pdc>; 3986 3987 dp_hot_plug_det: dp-hot-plug-det { 3988 pins = "gpio47"; 3989 function = "dp_hot"; 3990 }; 3991 3992 edp_hot_plug_det: edp-hot-plug-det { 3993 pins = "gpio60"; 3994 function = "edp_hot"; 3995 }; 3996 3997 mi2s0_data0: mi2s0-data0 { 3998 pins = "gpio98"; 3999 function = "mi2s0_data0"; 4000 }; 4001 4002 mi2s0_data1: mi2s0-data1 { 4003 pins = "gpio99"; 4004 function = "mi2s0_data1"; 4005 }; 4006 4007 mi2s0_mclk: mi2s0-mclk { 4008 pins = "gpio96"; 4009 function = "pri_mi2s"; 4010 }; 4011 4012 mi2s0_sclk: mi2s0-sclk { 4013 pins = "gpio97"; 4014 function = "mi2s0_sck"; 4015 }; 4016 4017 mi2s0_ws: mi2s0-ws { 4018 pins = "gpio100"; 4019 function = "mi2s0_ws"; 4020 }; 4021 4022 mi2s1_data0: mi2s1-data0 { 4023 pins = "gpio107"; 4024 function = "mi2s1_data0"; 4025 }; 4026 4027 mi2s1_sclk: mi2s1-sclk { 4028 pins = "gpio106"; 4029 function = "mi2s1_sck"; 4030 }; 4031 4032 mi2s1_ws: mi2s1-ws { 4033 pins = "gpio108"; 4034 function = "mi2s1_ws"; 4035 }; 4036 4037 pcie1_clkreq_n: pcie1-clkreq-n { 4038 pins = "gpio79"; 4039 function = "pcie1_clkreqn"; 4040 }; 4041 4042 qspi_clk: qspi-clk { 4043 pins = "gpio14"; 4044 function = "qspi_clk"; 4045 }; 4046 4047 qspi_cs0: qspi-cs0 { 4048 pins = "gpio15"; 4049 function = "qspi_cs"; 4050 }; 4051 4052 qspi_cs1: qspi-cs1 { 4053 pins = "gpio19"; 4054 function = "qspi_cs"; 4055 }; 4056 4057 qspi_data01: qspi-data01 { 4058 pins = "gpio12", "gpio13"; 4059 function = "qspi_data"; 4060 }; 4061 4062 qspi_data12: qspi-data12 { 4063 pins = "gpio16", "gpio17"; 4064 function = "qspi_data"; 4065 }; 4066 4067 qup_i2c0_data_clk: qup-i2c0-data-clk { 4068 pins = "gpio0", "gpio1"; 4069 function = "qup00"; 4070 }; 4071 4072 qup_i2c1_data_clk: qup-i2c1-data-clk { 4073 pins = "gpio4", "gpio5"; 4074 function = "qup01"; 4075 }; 4076 4077 qup_i2c2_data_clk: qup-i2c2-data-clk { 4078 pins = "gpio8", "gpio9"; 4079 function = "qup02"; 4080 }; 4081 4082 qup_i2c3_data_clk: qup-i2c3-data-clk { 4083 pins = "gpio12", "gpio13"; 4084 function = "qup03"; 4085 }; 4086 4087 qup_i2c4_data_clk: qup-i2c4-data-clk { 4088 pins = "gpio16", "gpio17"; 4089 function = "qup04"; 4090 }; 4091 4092 qup_i2c5_data_clk: qup-i2c5-data-clk { 4093 pins = "gpio20", "gpio21"; 4094 function = "qup05"; 4095 }; 4096 4097 qup_i2c6_data_clk: qup-i2c6-data-clk { 4098 pins = "gpio24", "gpio25"; 4099 function = "qup06"; 4100 }; 4101 4102 qup_i2c7_data_clk: qup-i2c7-data-clk { 4103 pins = "gpio28", "gpio29"; 4104 function = "qup07"; 4105 }; 4106 4107 qup_i2c8_data_clk: qup-i2c8-data-clk { 4108 pins = "gpio32", "gpio33"; 4109 function = "qup10"; 4110 }; 4111 4112 qup_i2c9_data_clk: qup-i2c9-data-clk { 4113 pins = "gpio36", "gpio37"; 4114 function = "qup11"; 4115 }; 4116 4117 qup_i2c10_data_clk: qup-i2c10-data-clk { 4118 pins = "gpio40", "gpio41"; 4119 function = "qup12"; 4120 }; 4121 4122 qup_i2c11_data_clk: qup-i2c11-data-clk { 4123 pins = "gpio44", "gpio45"; 4124 function = "qup13"; 4125 }; 4126 4127 qup_i2c12_data_clk: qup-i2c12-data-clk { 4128 pins = "gpio48", "gpio49"; 4129 function = "qup14"; 4130 }; 4131 4132 qup_i2c13_data_clk: qup-i2c13-data-clk { 4133 pins = "gpio52", "gpio53"; 4134 function = "qup15"; 4135 }; 4136 4137 qup_i2c14_data_clk: qup-i2c14-data-clk { 4138 pins = "gpio56", "gpio57"; 4139 function = "qup16"; 4140 }; 4141 4142 qup_i2c15_data_clk: qup-i2c15-data-clk { 4143 pins = "gpio60", "gpio61"; 4144 function = "qup17"; 4145 }; 4146 4147 qup_spi0_data_clk: qup-spi0-data-clk { 4148 pins = "gpio0", "gpio1", "gpio2"; 4149 function = "qup00"; 4150 }; 4151 4152 qup_spi0_cs: qup-spi0-cs { 4153 pins = "gpio3"; 4154 function = "qup00"; 4155 }; 4156 4157 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 4158 pins = "gpio3"; 4159 function = "gpio"; 4160 }; 4161 4162 qup_spi1_data_clk: qup-spi1-data-clk { 4163 pins = "gpio4", "gpio5", "gpio6"; 4164 function = "qup01"; 4165 }; 4166 4167 qup_spi1_cs: qup-spi1-cs { 4168 pins = "gpio7"; 4169 function = "qup01"; 4170 }; 4171 4172 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 4173 pins = "gpio7"; 4174 function = "gpio"; 4175 }; 4176 4177 qup_spi2_data_clk: qup-spi2-data-clk { 4178 pins = "gpio8", "gpio9", "gpio10"; 4179 function = "qup02"; 4180 }; 4181 4182 qup_spi2_cs: qup-spi2-cs { 4183 pins = "gpio11"; 4184 function = "qup02"; 4185 }; 4186 4187 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 4188 pins = "gpio11"; 4189 function = "gpio"; 4190 }; 4191 4192 qup_spi3_data_clk: qup-spi3-data-clk { 4193 pins = "gpio12", "gpio13", "gpio14"; 4194 function = "qup03"; 4195 }; 4196 4197 qup_spi3_cs: qup-spi3-cs { 4198 pins = "gpio15"; 4199 function = "qup03"; 4200 }; 4201 4202 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 4203 pins = "gpio15"; 4204 function = "gpio"; 4205 }; 4206 4207 qup_spi4_data_clk: qup-spi4-data-clk { 4208 pins = "gpio16", "gpio17", "gpio18"; 4209 function = "qup04"; 4210 }; 4211 4212 qup_spi4_cs: qup-spi4-cs { 4213 pins = "gpio19"; 4214 function = "qup04"; 4215 }; 4216 4217 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 4218 pins = "gpio19"; 4219 function = "gpio"; 4220 }; 4221 4222 qup_spi5_data_clk: qup-spi5-data-clk { 4223 pins = "gpio20", "gpio21", "gpio22"; 4224 function = "qup05"; 4225 }; 4226 4227 qup_spi5_cs: qup-spi5-cs { 4228 pins = "gpio23"; 4229 function = "qup05"; 4230 }; 4231 4232 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 4233 pins = "gpio23"; 4234 function = "gpio"; 4235 }; 4236 4237 qup_spi6_data_clk: qup-spi6-data-clk { 4238 pins = "gpio24", "gpio25", "gpio26"; 4239 function = "qup06"; 4240 }; 4241 4242 qup_spi6_cs: qup-spi6-cs { 4243 pins = "gpio27"; 4244 function = "qup06"; 4245 }; 4246 4247 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 4248 pins = "gpio27"; 4249 function = "gpio"; 4250 }; 4251 4252 qup_spi7_data_clk: qup-spi7-data-clk { 4253 pins = "gpio28", "gpio29", "gpio30"; 4254 function = "qup07"; 4255 }; 4256 4257 qup_spi7_cs: qup-spi7-cs { 4258 pins = "gpio31"; 4259 function = "qup07"; 4260 }; 4261 4262 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 4263 pins = "gpio31"; 4264 function = "gpio"; 4265 }; 4266 4267 qup_spi8_data_clk: qup-spi8-data-clk { 4268 pins = "gpio32", "gpio33", "gpio34"; 4269 function = "qup10"; 4270 }; 4271 4272 qup_spi8_cs: qup-spi8-cs { 4273 pins = "gpio35"; 4274 function = "qup10"; 4275 }; 4276 4277 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 4278 pins = "gpio35"; 4279 function = "gpio"; 4280 }; 4281 4282 qup_spi9_data_clk: qup-spi9-data-clk { 4283 pins = "gpio36", "gpio37", "gpio38"; 4284 function = "qup11"; 4285 }; 4286 4287 qup_spi9_cs: qup-spi9-cs { 4288 pins = "gpio39"; 4289 function = "qup11"; 4290 }; 4291 4292 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 4293 pins = "gpio39"; 4294 function = "gpio"; 4295 }; 4296 4297 qup_spi10_data_clk: qup-spi10-data-clk { 4298 pins = "gpio40", "gpio41", "gpio42"; 4299 function = "qup12"; 4300 }; 4301 4302 qup_spi10_cs: qup-spi10-cs { 4303 pins = "gpio43"; 4304 function = "qup12"; 4305 }; 4306 4307 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 4308 pins = "gpio43"; 4309 function = "gpio"; 4310 }; 4311 4312 qup_spi11_data_clk: qup-spi11-data-clk { 4313 pins = "gpio44", "gpio45", "gpio46"; 4314 function = "qup13"; 4315 }; 4316 4317 qup_spi11_cs: qup-spi11-cs { 4318 pins = "gpio47"; 4319 function = "qup13"; 4320 }; 4321 4322 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 4323 pins = "gpio47"; 4324 function = "gpio"; 4325 }; 4326 4327 qup_spi12_data_clk: qup-spi12-data-clk { 4328 pins = "gpio48", "gpio49", "gpio50"; 4329 function = "qup14"; 4330 }; 4331 4332 qup_spi12_cs: qup-spi12-cs { 4333 pins = "gpio51"; 4334 function = "qup14"; 4335 }; 4336 4337 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4338 pins = "gpio51"; 4339 function = "gpio"; 4340 }; 4341 4342 qup_spi13_data_clk: qup-spi13-data-clk { 4343 pins = "gpio52", "gpio53", "gpio54"; 4344 function = "qup15"; 4345 }; 4346 4347 qup_spi13_cs: qup-spi13-cs { 4348 pins = "gpio55"; 4349 function = "qup15"; 4350 }; 4351 4352 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4353 pins = "gpio55"; 4354 function = "gpio"; 4355 }; 4356 4357 qup_spi14_data_clk: qup-spi14-data-clk { 4358 pins = "gpio56", "gpio57", "gpio58"; 4359 function = "qup16"; 4360 }; 4361 4362 qup_spi14_cs: qup-spi14-cs { 4363 pins = "gpio59"; 4364 function = "qup16"; 4365 }; 4366 4367 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4368 pins = "gpio59"; 4369 function = "gpio"; 4370 }; 4371 4372 qup_spi15_data_clk: qup-spi15-data-clk { 4373 pins = "gpio60", "gpio61", "gpio62"; 4374 function = "qup17"; 4375 }; 4376 4377 qup_spi15_cs: qup-spi15-cs { 4378 pins = "gpio63"; 4379 function = "qup17"; 4380 }; 4381 4382 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4383 pins = "gpio63"; 4384 function = "gpio"; 4385 }; 4386 4387 qup_uart0_cts: qup-uart0-cts { 4388 pins = "gpio0"; 4389 function = "qup00"; 4390 }; 4391 4392 qup_uart0_rts: qup-uart0-rts { 4393 pins = "gpio1"; 4394 function = "qup00"; 4395 }; 4396 4397 qup_uart0_tx: qup-uart0-tx { 4398 pins = "gpio2"; 4399 function = "qup00"; 4400 }; 4401 4402 qup_uart0_rx: qup-uart0-rx { 4403 pins = "gpio3"; 4404 function = "qup00"; 4405 }; 4406 4407 qup_uart1_cts: qup-uart1-cts { 4408 pins = "gpio4"; 4409 function = "qup01"; 4410 }; 4411 4412 qup_uart1_rts: qup-uart1-rts { 4413 pins = "gpio5"; 4414 function = "qup01"; 4415 }; 4416 4417 qup_uart1_tx: qup-uart1-tx { 4418 pins = "gpio6"; 4419 function = "qup01"; 4420 }; 4421 4422 qup_uart1_rx: qup-uart1-rx { 4423 pins = "gpio7"; 4424 function = "qup01"; 4425 }; 4426 4427 qup_uart2_cts: qup-uart2-cts { 4428 pins = "gpio8"; 4429 function = "qup02"; 4430 }; 4431 4432 qup_uart2_rts: qup-uart2-rts { 4433 pins = "gpio9"; 4434 function = "qup02"; 4435 }; 4436 4437 qup_uart2_tx: qup-uart2-tx { 4438 pins = "gpio10"; 4439 function = "qup02"; 4440 }; 4441 4442 qup_uart2_rx: qup-uart2-rx { 4443 pins = "gpio11"; 4444 function = "qup02"; 4445 }; 4446 4447 qup_uart3_cts: qup-uart3-cts { 4448 pins = "gpio12"; 4449 function = "qup03"; 4450 }; 4451 4452 qup_uart3_rts: qup-uart3-rts { 4453 pins = "gpio13"; 4454 function = "qup03"; 4455 }; 4456 4457 qup_uart3_tx: qup-uart3-tx { 4458 pins = "gpio14"; 4459 function = "qup03"; 4460 }; 4461 4462 qup_uart3_rx: qup-uart3-rx { 4463 pins = "gpio15"; 4464 function = "qup03"; 4465 }; 4466 4467 qup_uart4_cts: qup-uart4-cts { 4468 pins = "gpio16"; 4469 function = "qup04"; 4470 }; 4471 4472 qup_uart4_rts: qup-uart4-rts { 4473 pins = "gpio17"; 4474 function = "qup04"; 4475 }; 4476 4477 qup_uart4_tx: qup-uart4-tx { 4478 pins = "gpio18"; 4479 function = "qup04"; 4480 }; 4481 4482 qup_uart4_rx: qup-uart4-rx { 4483 pins = "gpio19"; 4484 function = "qup04"; 4485 }; 4486 4487 qup_uart5_cts: qup-uart5-cts { 4488 pins = "gpio20"; 4489 function = "qup05"; 4490 }; 4491 4492 qup_uart5_rts: qup-uart5-rts { 4493 pins = "gpio21"; 4494 function = "qup05"; 4495 }; 4496 4497 qup_uart5_tx: qup-uart5-tx { 4498 pins = "gpio22"; 4499 function = "qup05"; 4500 }; 4501 4502 qup_uart5_rx: qup-uart5-rx { 4503 pins = "gpio23"; 4504 function = "qup05"; 4505 }; 4506 4507 qup_uart6_cts: qup-uart6-cts { 4508 pins = "gpio24"; 4509 function = "qup06"; 4510 }; 4511 4512 qup_uart6_rts: qup-uart6-rts { 4513 pins = "gpio25"; 4514 function = "qup06"; 4515 }; 4516 4517 qup_uart6_tx: qup-uart6-tx { 4518 pins = "gpio26"; 4519 function = "qup06"; 4520 }; 4521 4522 qup_uart6_rx: qup-uart6-rx { 4523 pins = "gpio27"; 4524 function = "qup06"; 4525 }; 4526 4527 qup_uart7_cts: qup-uart7-cts { 4528 pins = "gpio28"; 4529 function = "qup07"; 4530 }; 4531 4532 qup_uart7_rts: qup-uart7-rts { 4533 pins = "gpio29"; 4534 function = "qup07"; 4535 }; 4536 4537 qup_uart7_tx: qup-uart7-tx { 4538 pins = "gpio30"; 4539 function = "qup07"; 4540 }; 4541 4542 qup_uart7_rx: qup-uart7-rx { 4543 pins = "gpio31"; 4544 function = "qup07"; 4545 }; 4546 4547 qup_uart8_cts: qup-uart8-cts { 4548 pins = "gpio32"; 4549 function = "qup10"; 4550 }; 4551 4552 qup_uart8_rts: qup-uart8-rts { 4553 pins = "gpio33"; 4554 function = "qup10"; 4555 }; 4556 4557 qup_uart8_tx: qup-uart8-tx { 4558 pins = "gpio34"; 4559 function = "qup10"; 4560 }; 4561 4562 qup_uart8_rx: qup-uart8-rx { 4563 pins = "gpio35"; 4564 function = "qup10"; 4565 }; 4566 4567 qup_uart9_cts: qup-uart9-cts { 4568 pins = "gpio36"; 4569 function = "qup11"; 4570 }; 4571 4572 qup_uart9_rts: qup-uart9-rts { 4573 pins = "gpio37"; 4574 function = "qup11"; 4575 }; 4576 4577 qup_uart9_tx: qup-uart9-tx { 4578 pins = "gpio38"; 4579 function = "qup11"; 4580 }; 4581 4582 qup_uart9_rx: qup-uart9-rx { 4583 pins = "gpio39"; 4584 function = "qup11"; 4585 }; 4586 4587 qup_uart10_cts: qup-uart10-cts { 4588 pins = "gpio40"; 4589 function = "qup12"; 4590 }; 4591 4592 qup_uart10_rts: qup-uart10-rts { 4593 pins = "gpio41"; 4594 function = "qup12"; 4595 }; 4596 4597 qup_uart10_tx: qup-uart10-tx { 4598 pins = "gpio42"; 4599 function = "qup12"; 4600 }; 4601 4602 qup_uart10_rx: qup-uart10-rx { 4603 pins = "gpio43"; 4604 function = "qup12"; 4605 }; 4606 4607 qup_uart11_cts: qup-uart11-cts { 4608 pins = "gpio44"; 4609 function = "qup13"; 4610 }; 4611 4612 qup_uart11_rts: qup-uart11-rts { 4613 pins = "gpio45"; 4614 function = "qup13"; 4615 }; 4616 4617 qup_uart11_tx: qup-uart11-tx { 4618 pins = "gpio46"; 4619 function = "qup13"; 4620 }; 4621 4622 qup_uart11_rx: qup-uart11-rx { 4623 pins = "gpio47"; 4624 function = "qup13"; 4625 }; 4626 4627 qup_uart12_cts: qup-uart12-cts { 4628 pins = "gpio48"; 4629 function = "qup14"; 4630 }; 4631 4632 qup_uart12_rts: qup-uart12-rts { 4633 pins = "gpio49"; 4634 function = "qup14"; 4635 }; 4636 4637 qup_uart12_tx: qup-uart12-tx { 4638 pins = "gpio50"; 4639 function = "qup14"; 4640 }; 4641 4642 qup_uart12_rx: qup-uart12-rx { 4643 pins = "gpio51"; 4644 function = "qup14"; 4645 }; 4646 4647 qup_uart13_cts: qup-uart13-cts { 4648 pins = "gpio52"; 4649 function = "qup15"; 4650 }; 4651 4652 qup_uart13_rts: qup-uart13-rts { 4653 pins = "gpio53"; 4654 function = "qup15"; 4655 }; 4656 4657 qup_uart13_tx: qup-uart13-tx { 4658 pins = "gpio54"; 4659 function = "qup15"; 4660 }; 4661 4662 qup_uart13_rx: qup-uart13-rx { 4663 pins = "gpio55"; 4664 function = "qup15"; 4665 }; 4666 4667 qup_uart14_cts: qup-uart14-cts { 4668 pins = "gpio56"; 4669 function = "qup16"; 4670 }; 4671 4672 qup_uart14_rts: qup-uart14-rts { 4673 pins = "gpio57"; 4674 function = "qup16"; 4675 }; 4676 4677 qup_uart14_tx: qup-uart14-tx { 4678 pins = "gpio58"; 4679 function = "qup16"; 4680 }; 4681 4682 qup_uart14_rx: qup-uart14-rx { 4683 pins = "gpio59"; 4684 function = "qup16"; 4685 }; 4686 4687 qup_uart15_cts: qup-uart15-cts { 4688 pins = "gpio60"; 4689 function = "qup17"; 4690 }; 4691 4692 qup_uart15_rts: qup-uart15-rts { 4693 pins = "gpio61"; 4694 function = "qup17"; 4695 }; 4696 4697 qup_uart15_tx: qup-uart15-tx { 4698 pins = "gpio62"; 4699 function = "qup17"; 4700 }; 4701 4702 qup_uart15_rx: qup-uart15-rx { 4703 pins = "gpio63"; 4704 function = "qup17"; 4705 }; 4706 4707 sdc1_clk: sdc1-clk { 4708 pins = "sdc1_clk"; 4709 }; 4710 4711 sdc1_cmd: sdc1-cmd { 4712 pins = "sdc1_cmd"; 4713 }; 4714 4715 sdc1_data: sdc1-data { 4716 pins = "sdc1_data"; 4717 }; 4718 4719 sdc1_rclk: sdc1-rclk { 4720 pins = "sdc1_rclk"; 4721 }; 4722 4723 sdc1_clk_sleep: sdc1-clk-sleep { 4724 pins = "sdc1_clk"; 4725 drive-strength = <2>; 4726 bias-bus-hold; 4727 }; 4728 4729 sdc1_cmd_sleep: sdc1-cmd-sleep { 4730 pins = "sdc1_cmd"; 4731 drive-strength = <2>; 4732 bias-bus-hold; 4733 }; 4734 4735 sdc1_data_sleep: sdc1-data-sleep { 4736 pins = "sdc1_data"; 4737 drive-strength = <2>; 4738 bias-bus-hold; 4739 }; 4740 4741 sdc1_rclk_sleep: sdc1-rclk-sleep { 4742 pins = "sdc1_rclk"; 4743 drive-strength = <2>; 4744 bias-bus-hold; 4745 }; 4746 4747 sdc2_clk: sdc2-clk { 4748 pins = "sdc2_clk"; 4749 }; 4750 4751 sdc2_cmd: sdc2-cmd { 4752 pins = "sdc2_cmd"; 4753 }; 4754 4755 sdc2_data: sdc2-data { 4756 pins = "sdc2_data"; 4757 }; 4758 4759 sdc2_clk_sleep: sdc2-clk-sleep { 4760 pins = "sdc2_clk"; 4761 drive-strength = <2>; 4762 bias-bus-hold; 4763 }; 4764 4765 sdc2_cmd_sleep: sdc2-cmd-sleep { 4766 pins = "sdc2_cmd"; 4767 drive-strength = <2>; 4768 bias-bus-hold; 4769 }; 4770 4771 sdc2_data_sleep: sdc2-data-sleep { 4772 pins = "sdc2_data"; 4773 drive-strength = <2>; 4774 bias-bus-hold; 4775 }; 4776 }; 4777 4778 sram@146a5000 { 4779 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 4780 reg = <0 0x146a5000 0 0x6000>; 4781 4782 #address-cells = <1>; 4783 #size-cells = <1>; 4784 4785 ranges = <0 0 0x146a5000 0x6000>; 4786 4787 pil-reloc@594c { 4788 compatible = "qcom,pil-reloc-info"; 4789 reg = <0x594c 0xc8>; 4790 }; 4791 }; 4792 4793 apps_smmu: iommu@15000000 { 4794 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4795 reg = <0 0x15000000 0 0x100000>; 4796 #iommu-cells = <2>; 4797 #global-interrupts = <1>; 4798 dma-coherent; 4799 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4800 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4801 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4802 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4803 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4804 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4805 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4806 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4807 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4808 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4809 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4810 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4811 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4812 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4813 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4814 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4815 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4816 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4817 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4818 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4819 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4820 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4821 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4822 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4823 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4824 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4825 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4826 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4827 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4828 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4829 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4830 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4831 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4832 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4833 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4834 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4835 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4836 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4837 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4838 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4839 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4840 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4841 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4842 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4843 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4844 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4845 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4846 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4847 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4848 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4849 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4850 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4851 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4852 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4853 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4854 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4855 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4856 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4857 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4858 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4859 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4860 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4861 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4862 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4863 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4864 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4865 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4866 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4868 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4869 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4870 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4871 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4872 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4873 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4874 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4875 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4876 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4877 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4878 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4879 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4880 }; 4881 4882 intc: interrupt-controller@17a00000 { 4883 compatible = "arm,gic-v3"; 4884 #address-cells = <2>; 4885 #size-cells = <2>; 4886 ranges; 4887 #interrupt-cells = <3>; 4888 interrupt-controller; 4889 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4890 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4891 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4892 4893 gic-its@17a40000 { 4894 compatible = "arm,gic-v3-its"; 4895 msi-controller; 4896 #msi-cells = <1>; 4897 reg = <0 0x17a40000 0 0x20000>; 4898 status = "disabled"; 4899 }; 4900 }; 4901 4902 watchdog@17c10000 { 4903 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4904 reg = <0 0x17c10000 0 0x1000>; 4905 clocks = <&sleep_clk>; 4906 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4907 }; 4908 4909 timer@17c20000 { 4910 #address-cells = <1>; 4911 #size-cells = <1>; 4912 ranges = <0 0 0 0x20000000>; 4913 compatible = "arm,armv7-timer-mem"; 4914 reg = <0 0x17c20000 0 0x1000>; 4915 4916 frame@17c21000 { 4917 frame-number = <0>; 4918 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4920 reg = <0x17c21000 0x1000>, 4921 <0x17c22000 0x1000>; 4922 }; 4923 4924 frame@17c23000 { 4925 frame-number = <1>; 4926 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4927 reg = <0x17c23000 0x1000>; 4928 status = "disabled"; 4929 }; 4930 4931 frame@17c25000 { 4932 frame-number = <2>; 4933 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4934 reg = <0x17c25000 0x1000>; 4935 status = "disabled"; 4936 }; 4937 4938 frame@17c27000 { 4939 frame-number = <3>; 4940 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4941 reg = <0x17c27000 0x1000>; 4942 status = "disabled"; 4943 }; 4944 4945 frame@17c29000 { 4946 frame-number = <4>; 4947 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4948 reg = <0x17c29000 0x1000>; 4949 status = "disabled"; 4950 }; 4951 4952 frame@17c2b000 { 4953 frame-number = <5>; 4954 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4955 reg = <0x17c2b000 0x1000>; 4956 status = "disabled"; 4957 }; 4958 4959 frame@17c2d000 { 4960 frame-number = <6>; 4961 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4962 reg = <0x17c2d000 0x1000>; 4963 status = "disabled"; 4964 }; 4965 }; 4966 4967 apps_rsc: rsc@18200000 { 4968 compatible = "qcom,rpmh-rsc"; 4969 reg = <0 0x18200000 0 0x10000>, 4970 <0 0x18210000 0 0x10000>, 4971 <0 0x18220000 0 0x10000>; 4972 reg-names = "drv-0", "drv-1", "drv-2"; 4973 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4976 qcom,tcs-offset = <0xd00>; 4977 qcom,drv-id = <2>; 4978 qcom,tcs-config = <ACTIVE_TCS 2>, 4979 <SLEEP_TCS 3>, 4980 <WAKE_TCS 3>, 4981 <CONTROL_TCS 1>; 4982 4983 apps_bcm_voter: bcm-voter { 4984 compatible = "qcom,bcm-voter"; 4985 }; 4986 4987 rpmhpd: power-controller { 4988 compatible = "qcom,sc7280-rpmhpd"; 4989 #power-domain-cells = <1>; 4990 operating-points-v2 = <&rpmhpd_opp_table>; 4991 4992 rpmhpd_opp_table: opp-table { 4993 compatible = "operating-points-v2"; 4994 4995 rpmhpd_opp_ret: opp1 { 4996 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4997 }; 4998 4999 rpmhpd_opp_low_svs: opp2 { 5000 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5001 }; 5002 5003 rpmhpd_opp_svs: opp3 { 5004 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5005 }; 5006 5007 rpmhpd_opp_svs_l1: opp4 { 5008 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5009 }; 5010 5011 rpmhpd_opp_svs_l2: opp5 { 5012 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5013 }; 5014 5015 rpmhpd_opp_nom: opp6 { 5016 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5017 }; 5018 5019 rpmhpd_opp_nom_l1: opp7 { 5020 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5021 }; 5022 5023 rpmhpd_opp_turbo: opp8 { 5024 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5025 }; 5026 5027 rpmhpd_opp_turbo_l1: opp9 { 5028 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5029 }; 5030 }; 5031 }; 5032 5033 rpmhcc: clock-controller { 5034 compatible = "qcom,sc7280-rpmh-clk"; 5035 clocks = <&xo_board>; 5036 clock-names = "xo"; 5037 #clock-cells = <1>; 5038 }; 5039 }; 5040 5041 epss_l3: interconnect@18590000 { 5042 compatible = "qcom,sc7280-epss-l3"; 5043 reg = <0 0x18590000 0 0x1000>; 5044 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5045 clock-names = "xo", "alternate"; 5046 #interconnect-cells = <1>; 5047 }; 5048 5049 cpufreq_hw: cpufreq@18591000 { 5050 compatible = "qcom,cpufreq-epss"; 5051 reg = <0 0x18591000 0 0x1000>, 5052 <0 0x18592000 0 0x1000>, 5053 <0 0x18593000 0 0x1000>; 5054 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5055 clock-names = "xo", "alternate"; 5056 #freq-domain-cells = <1>; 5057 }; 5058 }; 5059 5060 thermal_zones: thermal-zones { 5061 cpu0-thermal { 5062 polling-delay-passive = <250>; 5063 polling-delay = <0>; 5064 5065 thermal-sensors = <&tsens0 1>; 5066 5067 trips { 5068 cpu0_alert0: trip-point0 { 5069 temperature = <90000>; 5070 hysteresis = <2000>; 5071 type = "passive"; 5072 }; 5073 5074 cpu0_alert1: trip-point1 { 5075 temperature = <95000>; 5076 hysteresis = <2000>; 5077 type = "passive"; 5078 }; 5079 5080 cpu0_crit: cpu-crit { 5081 temperature = <110000>; 5082 hysteresis = <0>; 5083 type = "critical"; 5084 }; 5085 }; 5086 5087 cooling-maps { 5088 map0 { 5089 trip = <&cpu0_alert0>; 5090 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5091 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5092 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5093 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5094 }; 5095 map1 { 5096 trip = <&cpu0_alert1>; 5097 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5098 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5099 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5100 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5101 }; 5102 }; 5103 }; 5104 5105 cpu1-thermal { 5106 polling-delay-passive = <250>; 5107 polling-delay = <0>; 5108 5109 thermal-sensors = <&tsens0 2>; 5110 5111 trips { 5112 cpu1_alert0: trip-point0 { 5113 temperature = <90000>; 5114 hysteresis = <2000>; 5115 type = "passive"; 5116 }; 5117 5118 cpu1_alert1: trip-point1 { 5119 temperature = <95000>; 5120 hysteresis = <2000>; 5121 type = "passive"; 5122 }; 5123 5124 cpu1_crit: cpu-crit { 5125 temperature = <110000>; 5126 hysteresis = <0>; 5127 type = "critical"; 5128 }; 5129 }; 5130 5131 cooling-maps { 5132 map0 { 5133 trip = <&cpu1_alert0>; 5134 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5135 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5136 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5137 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5138 }; 5139 map1 { 5140 trip = <&cpu1_alert1>; 5141 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5142 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5143 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5144 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5145 }; 5146 }; 5147 }; 5148 5149 cpu2-thermal { 5150 polling-delay-passive = <250>; 5151 polling-delay = <0>; 5152 5153 thermal-sensors = <&tsens0 3>; 5154 5155 trips { 5156 cpu2_alert0: trip-point0 { 5157 temperature = <90000>; 5158 hysteresis = <2000>; 5159 type = "passive"; 5160 }; 5161 5162 cpu2_alert1: trip-point1 { 5163 temperature = <95000>; 5164 hysteresis = <2000>; 5165 type = "passive"; 5166 }; 5167 5168 cpu2_crit: cpu-crit { 5169 temperature = <110000>; 5170 hysteresis = <0>; 5171 type = "critical"; 5172 }; 5173 }; 5174 5175 cooling-maps { 5176 map0 { 5177 trip = <&cpu2_alert0>; 5178 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5179 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5180 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5181 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5182 }; 5183 map1 { 5184 trip = <&cpu2_alert1>; 5185 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5186 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5187 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5188 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5189 }; 5190 }; 5191 }; 5192 5193 cpu3-thermal { 5194 polling-delay-passive = <250>; 5195 polling-delay = <0>; 5196 5197 thermal-sensors = <&tsens0 4>; 5198 5199 trips { 5200 cpu3_alert0: trip-point0 { 5201 temperature = <90000>; 5202 hysteresis = <2000>; 5203 type = "passive"; 5204 }; 5205 5206 cpu3_alert1: trip-point1 { 5207 temperature = <95000>; 5208 hysteresis = <2000>; 5209 type = "passive"; 5210 }; 5211 5212 cpu3_crit: cpu-crit { 5213 temperature = <110000>; 5214 hysteresis = <0>; 5215 type = "critical"; 5216 }; 5217 }; 5218 5219 cooling-maps { 5220 map0 { 5221 trip = <&cpu3_alert0>; 5222 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5223 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5224 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5225 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5226 }; 5227 map1 { 5228 trip = <&cpu3_alert1>; 5229 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5230 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5231 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5232 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5233 }; 5234 }; 5235 }; 5236 5237 cpu4-thermal { 5238 polling-delay-passive = <250>; 5239 polling-delay = <0>; 5240 5241 thermal-sensors = <&tsens0 7>; 5242 5243 trips { 5244 cpu4_alert0: trip-point0 { 5245 temperature = <90000>; 5246 hysteresis = <2000>; 5247 type = "passive"; 5248 }; 5249 5250 cpu4_alert1: trip-point1 { 5251 temperature = <95000>; 5252 hysteresis = <2000>; 5253 type = "passive"; 5254 }; 5255 5256 cpu4_crit: cpu-crit { 5257 temperature = <110000>; 5258 hysteresis = <0>; 5259 type = "critical"; 5260 }; 5261 }; 5262 5263 cooling-maps { 5264 map0 { 5265 trip = <&cpu4_alert0>; 5266 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5267 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5268 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5269 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5270 }; 5271 map1 { 5272 trip = <&cpu4_alert1>; 5273 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5274 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5275 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5276 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5277 }; 5278 }; 5279 }; 5280 5281 cpu5-thermal { 5282 polling-delay-passive = <250>; 5283 polling-delay = <0>; 5284 5285 thermal-sensors = <&tsens0 8>; 5286 5287 trips { 5288 cpu5_alert0: trip-point0 { 5289 temperature = <90000>; 5290 hysteresis = <2000>; 5291 type = "passive"; 5292 }; 5293 5294 cpu5_alert1: trip-point1 { 5295 temperature = <95000>; 5296 hysteresis = <2000>; 5297 type = "passive"; 5298 }; 5299 5300 cpu5_crit: cpu-crit { 5301 temperature = <110000>; 5302 hysteresis = <0>; 5303 type = "critical"; 5304 }; 5305 }; 5306 5307 cooling-maps { 5308 map0 { 5309 trip = <&cpu5_alert0>; 5310 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5311 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5312 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5313 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5314 }; 5315 map1 { 5316 trip = <&cpu5_alert1>; 5317 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5318 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5319 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5320 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5321 }; 5322 }; 5323 }; 5324 5325 cpu6-thermal { 5326 polling-delay-passive = <250>; 5327 polling-delay = <0>; 5328 5329 thermal-sensors = <&tsens0 9>; 5330 5331 trips { 5332 cpu6_alert0: trip-point0 { 5333 temperature = <90000>; 5334 hysteresis = <2000>; 5335 type = "passive"; 5336 }; 5337 5338 cpu6_alert1: trip-point1 { 5339 temperature = <95000>; 5340 hysteresis = <2000>; 5341 type = "passive"; 5342 }; 5343 5344 cpu6_crit: cpu-crit { 5345 temperature = <110000>; 5346 hysteresis = <0>; 5347 type = "critical"; 5348 }; 5349 }; 5350 5351 cooling-maps { 5352 map0 { 5353 trip = <&cpu6_alert0>; 5354 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5355 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5356 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5357 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5358 }; 5359 map1 { 5360 trip = <&cpu6_alert1>; 5361 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5362 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5363 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5364 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5365 }; 5366 }; 5367 }; 5368 5369 cpu7-thermal { 5370 polling-delay-passive = <250>; 5371 polling-delay = <0>; 5372 5373 thermal-sensors = <&tsens0 10>; 5374 5375 trips { 5376 cpu7_alert0: trip-point0 { 5377 temperature = <90000>; 5378 hysteresis = <2000>; 5379 type = "passive"; 5380 }; 5381 5382 cpu7_alert1: trip-point1 { 5383 temperature = <95000>; 5384 hysteresis = <2000>; 5385 type = "passive"; 5386 }; 5387 5388 cpu7_crit: cpu-crit { 5389 temperature = <110000>; 5390 hysteresis = <0>; 5391 type = "critical"; 5392 }; 5393 }; 5394 5395 cooling-maps { 5396 map0 { 5397 trip = <&cpu7_alert0>; 5398 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5399 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5400 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5401 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5402 }; 5403 map1 { 5404 trip = <&cpu7_alert1>; 5405 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5407 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5408 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5409 }; 5410 }; 5411 }; 5412 5413 cpu8-thermal { 5414 polling-delay-passive = <250>; 5415 polling-delay = <0>; 5416 5417 thermal-sensors = <&tsens0 11>; 5418 5419 trips { 5420 cpu8_alert0: trip-point0 { 5421 temperature = <90000>; 5422 hysteresis = <2000>; 5423 type = "passive"; 5424 }; 5425 5426 cpu8_alert1: trip-point1 { 5427 temperature = <95000>; 5428 hysteresis = <2000>; 5429 type = "passive"; 5430 }; 5431 5432 cpu8_crit: cpu-crit { 5433 temperature = <110000>; 5434 hysteresis = <0>; 5435 type = "critical"; 5436 }; 5437 }; 5438 5439 cooling-maps { 5440 map0 { 5441 trip = <&cpu8_alert0>; 5442 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5443 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5444 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5445 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5446 }; 5447 map1 { 5448 trip = <&cpu8_alert1>; 5449 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5451 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5452 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5453 }; 5454 }; 5455 }; 5456 5457 cpu9-thermal { 5458 polling-delay-passive = <250>; 5459 polling-delay = <0>; 5460 5461 thermal-sensors = <&tsens0 12>; 5462 5463 trips { 5464 cpu9_alert0: trip-point0 { 5465 temperature = <90000>; 5466 hysteresis = <2000>; 5467 type = "passive"; 5468 }; 5469 5470 cpu9_alert1: trip-point1 { 5471 temperature = <95000>; 5472 hysteresis = <2000>; 5473 type = "passive"; 5474 }; 5475 5476 cpu9_crit: cpu-crit { 5477 temperature = <110000>; 5478 hysteresis = <0>; 5479 type = "critical"; 5480 }; 5481 }; 5482 5483 cooling-maps { 5484 map0 { 5485 trip = <&cpu9_alert0>; 5486 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5487 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5488 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5489 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5490 }; 5491 map1 { 5492 trip = <&cpu9_alert1>; 5493 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5495 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5496 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5497 }; 5498 }; 5499 }; 5500 5501 cpu10-thermal { 5502 polling-delay-passive = <250>; 5503 polling-delay = <0>; 5504 5505 thermal-sensors = <&tsens0 13>; 5506 5507 trips { 5508 cpu10_alert0: trip-point0 { 5509 temperature = <90000>; 5510 hysteresis = <2000>; 5511 type = "passive"; 5512 }; 5513 5514 cpu10_alert1: trip-point1 { 5515 temperature = <95000>; 5516 hysteresis = <2000>; 5517 type = "passive"; 5518 }; 5519 5520 cpu10_crit: cpu-crit { 5521 temperature = <110000>; 5522 hysteresis = <0>; 5523 type = "critical"; 5524 }; 5525 }; 5526 5527 cooling-maps { 5528 map0 { 5529 trip = <&cpu10_alert0>; 5530 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5531 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5532 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5533 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5534 }; 5535 map1 { 5536 trip = <&cpu10_alert1>; 5537 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5539 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5540 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5541 }; 5542 }; 5543 }; 5544 5545 cpu11-thermal { 5546 polling-delay-passive = <250>; 5547 polling-delay = <0>; 5548 5549 thermal-sensors = <&tsens0 14>; 5550 5551 trips { 5552 cpu11_alert0: trip-point0 { 5553 temperature = <90000>; 5554 hysteresis = <2000>; 5555 type = "passive"; 5556 }; 5557 5558 cpu11_alert1: trip-point1 { 5559 temperature = <95000>; 5560 hysteresis = <2000>; 5561 type = "passive"; 5562 }; 5563 5564 cpu11_crit: cpu-crit { 5565 temperature = <110000>; 5566 hysteresis = <0>; 5567 type = "critical"; 5568 }; 5569 }; 5570 5571 cooling-maps { 5572 map0 { 5573 trip = <&cpu11_alert0>; 5574 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5575 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5576 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5577 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5578 }; 5579 map1 { 5580 trip = <&cpu11_alert1>; 5581 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5583 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5584 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5585 }; 5586 }; 5587 }; 5588 5589 aoss0-thermal { 5590 polling-delay-passive = <0>; 5591 polling-delay = <0>; 5592 5593 thermal-sensors = <&tsens0 0>; 5594 5595 trips { 5596 aoss0_alert0: trip-point0 { 5597 temperature = <90000>; 5598 hysteresis = <2000>; 5599 type = "hot"; 5600 }; 5601 5602 aoss0_crit: aoss0-crit { 5603 temperature = <110000>; 5604 hysteresis = <0>; 5605 type = "critical"; 5606 }; 5607 }; 5608 }; 5609 5610 aoss1-thermal { 5611 polling-delay-passive = <0>; 5612 polling-delay = <0>; 5613 5614 thermal-sensors = <&tsens1 0>; 5615 5616 trips { 5617 aoss1_alert0: trip-point0 { 5618 temperature = <90000>; 5619 hysteresis = <2000>; 5620 type = "hot"; 5621 }; 5622 5623 aoss1_crit: aoss1-crit { 5624 temperature = <110000>; 5625 hysteresis = <0>; 5626 type = "critical"; 5627 }; 5628 }; 5629 }; 5630 5631 cpuss0-thermal { 5632 polling-delay-passive = <0>; 5633 polling-delay = <0>; 5634 5635 thermal-sensors = <&tsens0 5>; 5636 5637 trips { 5638 cpuss0_alert0: trip-point0 { 5639 temperature = <90000>; 5640 hysteresis = <2000>; 5641 type = "hot"; 5642 }; 5643 cpuss0_crit: cluster0-crit { 5644 temperature = <110000>; 5645 hysteresis = <0>; 5646 type = "critical"; 5647 }; 5648 }; 5649 }; 5650 5651 cpuss1-thermal { 5652 polling-delay-passive = <0>; 5653 polling-delay = <0>; 5654 5655 thermal-sensors = <&tsens0 6>; 5656 5657 trips { 5658 cpuss1_alert0: trip-point0 { 5659 temperature = <90000>; 5660 hysteresis = <2000>; 5661 type = "hot"; 5662 }; 5663 cpuss1_crit: cluster0-crit { 5664 temperature = <110000>; 5665 hysteresis = <0>; 5666 type = "critical"; 5667 }; 5668 }; 5669 }; 5670 5671 gpuss0-thermal { 5672 polling-delay-passive = <100>; 5673 polling-delay = <0>; 5674 5675 thermal-sensors = <&tsens1 1>; 5676 5677 trips { 5678 gpuss0_alert0: trip-point0 { 5679 temperature = <95000>; 5680 hysteresis = <2000>; 5681 type = "passive"; 5682 }; 5683 5684 gpuss0_crit: gpuss0-crit { 5685 temperature = <110000>; 5686 hysteresis = <0>; 5687 type = "critical"; 5688 }; 5689 }; 5690 5691 cooling-maps { 5692 map0 { 5693 trip = <&gpuss0_alert0>; 5694 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5695 }; 5696 }; 5697 }; 5698 5699 gpuss1-thermal { 5700 polling-delay-passive = <100>; 5701 polling-delay = <0>; 5702 5703 thermal-sensors = <&tsens1 2>; 5704 5705 trips { 5706 gpuss1_alert0: trip-point0 { 5707 temperature = <95000>; 5708 hysteresis = <2000>; 5709 type = "passive"; 5710 }; 5711 5712 gpuss1_crit: gpuss1-crit { 5713 temperature = <110000>; 5714 hysteresis = <0>; 5715 type = "critical"; 5716 }; 5717 }; 5718 5719 cooling-maps { 5720 map0 { 5721 trip = <&gpuss1_alert0>; 5722 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5723 }; 5724 }; 5725 }; 5726 5727 nspss0-thermal { 5728 polling-delay-passive = <0>; 5729 polling-delay = <0>; 5730 5731 thermal-sensors = <&tsens1 3>; 5732 5733 trips { 5734 nspss0_alert0: trip-point0 { 5735 temperature = <90000>; 5736 hysteresis = <2000>; 5737 type = "hot"; 5738 }; 5739 5740 nspss0_crit: nspss0-crit { 5741 temperature = <110000>; 5742 hysteresis = <0>; 5743 type = "critical"; 5744 }; 5745 }; 5746 }; 5747 5748 nspss1-thermal { 5749 polling-delay-passive = <0>; 5750 polling-delay = <0>; 5751 5752 thermal-sensors = <&tsens1 4>; 5753 5754 trips { 5755 nspss1_alert0: trip-point0 { 5756 temperature = <90000>; 5757 hysteresis = <2000>; 5758 type = "hot"; 5759 }; 5760 5761 nspss1_crit: nspss1-crit { 5762 temperature = <110000>; 5763 hysteresis = <0>; 5764 type = "critical"; 5765 }; 5766 }; 5767 }; 5768 5769 video-thermal { 5770 polling-delay-passive = <0>; 5771 polling-delay = <0>; 5772 5773 thermal-sensors = <&tsens1 5>; 5774 5775 trips { 5776 video_alert0: trip-point0 { 5777 temperature = <90000>; 5778 hysteresis = <2000>; 5779 type = "hot"; 5780 }; 5781 5782 video_crit: video-crit { 5783 temperature = <110000>; 5784 hysteresis = <0>; 5785 type = "critical"; 5786 }; 5787 }; 5788 }; 5789 5790 ddr-thermal { 5791 polling-delay-passive = <0>; 5792 polling-delay = <0>; 5793 5794 thermal-sensors = <&tsens1 6>; 5795 5796 trips { 5797 ddr_alert0: trip-point0 { 5798 temperature = <90000>; 5799 hysteresis = <2000>; 5800 type = "hot"; 5801 }; 5802 5803 ddr_crit: ddr-crit { 5804 temperature = <110000>; 5805 hysteresis = <0>; 5806 type = "critical"; 5807 }; 5808 }; 5809 }; 5810 5811 mdmss0-thermal { 5812 polling-delay-passive = <0>; 5813 polling-delay = <0>; 5814 5815 thermal-sensors = <&tsens1 7>; 5816 5817 trips { 5818 mdmss0_alert0: trip-point0 { 5819 temperature = <90000>; 5820 hysteresis = <2000>; 5821 type = "hot"; 5822 }; 5823 5824 mdmss0_crit: mdmss0-crit { 5825 temperature = <110000>; 5826 hysteresis = <0>; 5827 type = "critical"; 5828 }; 5829 }; 5830 }; 5831 5832 mdmss1-thermal { 5833 polling-delay-passive = <0>; 5834 polling-delay = <0>; 5835 5836 thermal-sensors = <&tsens1 8>; 5837 5838 trips { 5839 mdmss1_alert0: trip-point0 { 5840 temperature = <90000>; 5841 hysteresis = <2000>; 5842 type = "hot"; 5843 }; 5844 5845 mdmss1_crit: mdmss1-crit { 5846 temperature = <110000>; 5847 hysteresis = <0>; 5848 type = "critical"; 5849 }; 5850 }; 5851 }; 5852 5853 mdmss2-thermal { 5854 polling-delay-passive = <0>; 5855 polling-delay = <0>; 5856 5857 thermal-sensors = <&tsens1 9>; 5858 5859 trips { 5860 mdmss2_alert0: trip-point0 { 5861 temperature = <90000>; 5862 hysteresis = <2000>; 5863 type = "hot"; 5864 }; 5865 5866 mdmss2_crit: mdmss2-crit { 5867 temperature = <110000>; 5868 hysteresis = <0>; 5869 type = "critical"; 5870 }; 5871 }; 5872 }; 5873 5874 mdmss3-thermal { 5875 polling-delay-passive = <0>; 5876 polling-delay = <0>; 5877 5878 thermal-sensors = <&tsens1 10>; 5879 5880 trips { 5881 mdmss3_alert0: trip-point0 { 5882 temperature = <90000>; 5883 hysteresis = <2000>; 5884 type = "hot"; 5885 }; 5886 5887 mdmss3_crit: mdmss3-crit { 5888 temperature = <110000>; 5889 hysteresis = <0>; 5890 type = "critical"; 5891 }; 5892 }; 5893 }; 5894 5895 camera0-thermal { 5896 polling-delay-passive = <0>; 5897 polling-delay = <0>; 5898 5899 thermal-sensors = <&tsens1 11>; 5900 5901 trips { 5902 camera0_alert0: trip-point0 { 5903 temperature = <90000>; 5904 hysteresis = <2000>; 5905 type = "hot"; 5906 }; 5907 5908 camera0_crit: camera0-crit { 5909 temperature = <110000>; 5910 hysteresis = <0>; 5911 type = "critical"; 5912 }; 5913 }; 5914 }; 5915 }; 5916 5917 timer { 5918 compatible = "arm,armv8-timer"; 5919 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5920 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5921 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5922 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5923 }; 5924}; 5925