1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 clock-frequency = <76800000>; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 clock-frequency = <32000>; 31 #clock-cells = <0>; 32 }; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 aop_cmd_db_mem: memory@80860000 { 41 reg = <0x0 0x80860000 0x0 0x20000>; 42 compatible = "qcom,cmd-db"; 43 no-map; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 CPU0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,kryo"; 54 reg = <0x0 0x0>; 55 enable-method = "psci"; 56 next-level-cache = <&L2_0>; 57 L2_0: l2-cache { 58 compatible = "cache"; 59 next-level-cache = <&L3_0>; 60 L3_0: l3-cache { 61 compatible = "cache"; 62 }; 63 }; 64 }; 65 66 CPU1: cpu@100 { 67 device_type = "cpu"; 68 compatible = "arm,kryo"; 69 reg = <0x0 0x100>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_100>; 72 L2_100: l2-cache { 73 compatible = "cache"; 74 next-level-cache = <&L3_0>; 75 }; 76 }; 77 78 CPU2: cpu@200 { 79 device_type = "cpu"; 80 compatible = "arm,kryo"; 81 reg = <0x0 0x200>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_200>; 84 L2_200: l2-cache { 85 compatible = "cache"; 86 next-level-cache = <&L3_0>; 87 }; 88 }; 89 90 CPU3: cpu@300 { 91 device_type = "cpu"; 92 compatible = "arm,kryo"; 93 reg = <0x0 0x300>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_300>; 96 L2_300: l2-cache { 97 compatible = "cache"; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU4: cpu@400 { 103 device_type = "cpu"; 104 compatible = "arm,kryo"; 105 reg = <0x0 0x400>; 106 enable-method = "psci"; 107 next-level-cache = <&L2_400>; 108 L2_400: l2-cache { 109 compatible = "cache"; 110 next-level-cache = <&L3_0>; 111 }; 112 }; 113 114 CPU5: cpu@500 { 115 device_type = "cpu"; 116 compatible = "arm,kryo"; 117 reg = <0x0 0x500>; 118 enable-method = "psci"; 119 next-level-cache = <&L2_500>; 120 L2_500: l2-cache { 121 compatible = "cache"; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU6: cpu@600 { 127 device_type = "cpu"; 128 compatible = "arm,kryo"; 129 reg = <0x0 0x600>; 130 enable-method = "psci"; 131 next-level-cache = <&L2_600>; 132 L2_600: l2-cache { 133 compatible = "cache"; 134 next-level-cache = <&L3_0>; 135 }; 136 }; 137 138 CPU7: cpu@700 { 139 device_type = "cpu"; 140 compatible = "arm,kryo"; 141 reg = <0x0 0x700>; 142 enable-method = "psci"; 143 next-level-cache = <&L2_700>; 144 L2_700: l2-cache { 145 compatible = "cache"; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 }; 150 151 memory@80000000 { 152 device_type = "memory"; 153 /* We expect the bootloader to fill in the size */ 154 reg = <0 0x80000000 0 0>; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-sc7280", "qcom,scm"; 160 }; 161 }; 162 163 pmu { 164 compatible = "arm,armv8-pmuv3"; 165 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 166 }; 167 168 psci { 169 compatible = "arm,psci-1.0"; 170 method = "smc"; 171 }; 172 173 soc: soc@0 { 174 #address-cells = <2>; 175 #size-cells = <2>; 176 ranges = <0 0 0 0 0x10 0>; 177 dma-ranges = <0 0 0 0 0x10 0>; 178 compatible = "simple-bus"; 179 180 gcc: clock-controller@100000 { 181 compatible = "qcom,gcc-sc7280"; 182 reg = <0 0x00100000 0 0x1f0000>; 183 clocks = <&rpmhcc RPMH_CXO_CLK>, 184 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 185 <0>, <0>, <0>, <0>, <0>, <0>; 186 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 187 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 188 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 189 "ufs_phy_tx_symbol_0_clk", 190 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 191 #clock-cells = <1>; 192 #reset-cells = <1>; 193 #power-domain-cells = <1>; 194 }; 195 196 qupv3_id_0: geniqup@9c0000 { 197 compatible = "qcom,geni-se-qup"; 198 reg = <0 0x009c0000 0 0x2000>; 199 clock-names = "m-ahb", "s-ahb"; 200 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 201 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 status = "disabled"; 206 207 uart5: serial@994000 { 208 compatible = "qcom,geni-debug-uart"; 209 reg = <0 0x00994000 0 0x4000>; 210 clock-names = "se"; 211 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&qup_uart5_default>; 214 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 215 status = "disabled"; 216 }; 217 }; 218 219 pdc: interrupt-controller@b220000 { 220 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 221 reg = <0 0x0b220000 0 0x30000>; 222 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 223 <55 306 4>, <59 312 3>, <62 374 2>, 224 <64 434 2>, <66 438 3>, <69 86 1>, 225 <70 520 54>, <124 609 31>, <155 63 1>, 226 <156 716 12>; 227 #interrupt-cells = <2>; 228 interrupt-parent = <&intc>; 229 interrupt-controller; 230 }; 231 232 tlmm: pinctrl@f100000 { 233 compatible = "qcom,sc7280-pinctrl"; 234 reg = <0 0x0f100000 0 0x300000>; 235 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 gpio-ranges = <&tlmm 0 0 175>; 241 wakeup-parent = <&pdc>; 242 243 qup_uart5_default: qup-uart5-default { 244 pins = "gpio46", "gpio47"; 245 function = "qup13"; 246 }; 247 }; 248 249 intc: interrupt-controller@17a00000 { 250 compatible = "arm,gic-v3"; 251 #address-cells = <2>; 252 #size-cells = <2>; 253 ranges; 254 #interrupt-cells = <3>; 255 interrupt-controller; 256 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 257 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 258 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 259 260 gic-its@17a40000 { 261 compatible = "arm,gic-v3-its"; 262 msi-controller; 263 #msi-cells = <1>; 264 reg = <0 0x17a40000 0 0x20000>; 265 status = "disabled"; 266 }; 267 }; 268 269 timer@17c20000 { 270 #address-cells = <2>; 271 #size-cells = <2>; 272 ranges; 273 compatible = "arm,armv7-timer-mem"; 274 reg = <0 0x17c20000 0 0x1000>; 275 276 frame@17c21000 { 277 frame-number = <0>; 278 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 280 reg = <0 0x17c21000 0 0x1000>, 281 <0 0x17c22000 0 0x1000>; 282 }; 283 284 frame@17c23000 { 285 frame-number = <1>; 286 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 287 reg = <0 0x17c23000 0 0x1000>; 288 status = "disabled"; 289 }; 290 291 frame@17c25000 { 292 frame-number = <2>; 293 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 294 reg = <0 0x17c25000 0 0x1000>; 295 status = "disabled"; 296 }; 297 298 frame@17c27000 { 299 frame-number = <3>; 300 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 301 reg = <0 0x17c27000 0 0x1000>; 302 status = "disabled"; 303 }; 304 305 frame@17c29000 { 306 frame-number = <4>; 307 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 308 reg = <0 0x17c29000 0 0x1000>; 309 status = "disabled"; 310 }; 311 312 frame@17c2b000 { 313 frame-number = <5>; 314 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 315 reg = <0 0x17c2b000 0 0x1000>; 316 status = "disabled"; 317 }; 318 319 frame@17c2d000 { 320 frame-number = <6>; 321 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 322 reg = <0 0x17c2d000 0 0x1000>; 323 status = "disabled"; 324 }; 325 }; 326 327 apps_rsc: rsc@18200000 { 328 compatible = "qcom,rpmh-rsc"; 329 reg = <0 0x18200000 0 0x10000>, 330 <0 0x18210000 0 0x10000>, 331 <0 0x18220000 0 0x10000>; 332 reg-names = "drv-0", "drv-1", "drv-2"; 333 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 336 qcom,tcs-offset = <0xd00>; 337 qcom,drv-id = <2>; 338 qcom,tcs-config = <ACTIVE_TCS 2>, 339 <SLEEP_TCS 3>, 340 <WAKE_TCS 3>, 341 <CONTROL_TCS 1>; 342 343 rpmhcc: clock-controller { 344 compatible = "qcom,sc7280-rpmh-clk"; 345 clocks = <&xo_board>; 346 clock-names = "xo"; 347 #clock-cells = <1>; 348 }; 349 }; 350 }; 351 352 timer { 353 compatible = "arm,armv8-timer"; 354 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 355 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 356 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 357 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 358 }; 359}; 360