1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 pmu { 758 compatible = "arm,armv8-pmuv3"; 759 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 760 }; 761 762 psci { 763 compatible = "arm,psci-1.0"; 764 method = "smc"; 765 }; 766 767 qspi_opp_table: opp-table-qspi { 768 compatible = "operating-points-v2"; 769 770 opp-75000000 { 771 opp-hz = /bits/ 64 <75000000>; 772 required-opps = <&rpmhpd_opp_low_svs>; 773 }; 774 775 opp-150000000 { 776 opp-hz = /bits/ 64 <150000000>; 777 required-opps = <&rpmhpd_opp_svs>; 778 }; 779 780 opp-200000000 { 781 opp-hz = /bits/ 64 <200000000>; 782 required-opps = <&rpmhpd_opp_svs_l1>; 783 }; 784 785 opp-300000000 { 786 opp-hz = /bits/ 64 <300000000>; 787 required-opps = <&rpmhpd_opp_nom>; 788 }; 789 }; 790 791 qup_opp_table: opp-table-qup { 792 compatible = "operating-points-v2"; 793 794 opp-75000000 { 795 opp-hz = /bits/ 64 <75000000>; 796 required-opps = <&rpmhpd_opp_low_svs>; 797 }; 798 799 opp-100000000 { 800 opp-hz = /bits/ 64 <100000000>; 801 required-opps = <&rpmhpd_opp_svs>; 802 }; 803 804 opp-128000000 { 805 opp-hz = /bits/ 64 <128000000>; 806 required-opps = <&rpmhpd_opp_nom>; 807 }; 808 }; 809 810 soc: soc@0 { 811 #address-cells = <2>; 812 #size-cells = <2>; 813 ranges = <0 0 0 0 0x10 0>; 814 dma-ranges = <0 0 0 0 0x10 0>; 815 compatible = "simple-bus"; 816 817 gcc: clock-controller@100000 { 818 compatible = "qcom,gcc-sc7280"; 819 reg = <0 0x00100000 0 0x1f0000>; 820 clocks = <&rpmhcc RPMH_CXO_CLK>, 821 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 822 <0>, <&pcie1_lane>, 823 <0>, <0>, <0>, <0>; 824 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 825 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 826 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 827 "ufs_phy_tx_symbol_0_clk", 828 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 }; 833 834 ipcc: mailbox@408000 { 835 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 836 reg = <0 0x00408000 0 0x1000>; 837 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-controller; 839 #interrupt-cells = <3>; 840 #mbox-cells = <2>; 841 }; 842 843 qfprom: efuse@784000 { 844 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 845 reg = <0 0x00784000 0 0xa20>, 846 <0 0x00780000 0 0xa20>, 847 <0 0x00782000 0 0x120>, 848 <0 0x00786000 0 0x1fff>; 849 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 850 clock-names = "core"; 851 power-domains = <&rpmhpd SC7280_MX>; 852 #address-cells = <1>; 853 #size-cells = <1>; 854 855 gpu_speed_bin: gpu_speed_bin@1e9 { 856 reg = <0x1e9 0x2>; 857 bits = <5 8>; 858 }; 859 }; 860 861 sdhc_1: mmc@7c4000 { 862 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 863 pinctrl-names = "default", "sleep"; 864 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 865 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 866 status = "disabled"; 867 868 reg = <0 0x007c4000 0 0x1000>, 869 <0 0x007c5000 0 0x1000>; 870 reg-names = "hc", "cqhci"; 871 872 iommus = <&apps_smmu 0xc0 0x0>; 873 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "hc_irq", "pwr_irq"; 876 877 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 878 <&gcc GCC_SDCC1_APPS_CLK>, 879 <&rpmhcc RPMH_CXO_CLK>; 880 clock-names = "iface", "core", "xo"; 881 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 882 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 883 interconnect-names = "sdhc-ddr","cpu-sdhc"; 884 power-domains = <&rpmhpd SC7280_CX>; 885 operating-points-v2 = <&sdhc1_opp_table>; 886 887 bus-width = <8>; 888 supports-cqe; 889 890 qcom,dll-config = <0x0007642c>; 891 qcom,ddr-config = <0x80040868>; 892 893 mmc-ddr-1_8v; 894 mmc-hs200-1_8v; 895 mmc-hs400-1_8v; 896 mmc-hs400-enhanced-strobe; 897 898 resets = <&gcc GCC_SDCC1_BCR>; 899 900 sdhc1_opp_table: opp-table { 901 compatible = "operating-points-v2"; 902 903 opp-100000000 { 904 opp-hz = /bits/ 64 <100000000>; 905 required-opps = <&rpmhpd_opp_low_svs>; 906 opp-peak-kBps = <1800000 400000>; 907 opp-avg-kBps = <100000 0>; 908 }; 909 910 opp-384000000 { 911 opp-hz = /bits/ 64 <384000000>; 912 required-opps = <&rpmhpd_opp_nom>; 913 opp-peak-kBps = <5400000 1600000>; 914 opp-avg-kBps = <390000 0>; 915 }; 916 }; 917 918 }; 919 920 gpi_dma0: dma-controller@900000 { 921 #dma-cells = <3>; 922 compatible = "qcom,sc7280-gpi-dma"; 923 reg = <0 0x00900000 0 0x60000>; 924 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 936 dma-channels = <12>; 937 dma-channel-mask = <0x7f>; 938 iommus = <&apps_smmu 0x0136 0x0>; 939 status = "disabled"; 940 }; 941 942 qupv3_id_0: geniqup@9c0000 { 943 compatible = "qcom,geni-se-qup"; 944 reg = <0 0x009c0000 0 0x2000>; 945 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 946 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 947 clock-names = "m-ahb", "s-ahb"; 948 #address-cells = <2>; 949 #size-cells = <2>; 950 ranges; 951 iommus = <&apps_smmu 0x123 0x0>; 952 status = "disabled"; 953 954 i2c0: i2c@980000 { 955 compatible = "qcom,geni-i2c"; 956 reg = <0 0x00980000 0 0x4000>; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 958 clock-names = "se"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_i2c0_data_clk>; 961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 966 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 967 interconnect-names = "qup-core", "qup-config", 968 "qup-memory"; 969 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 970 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 971 dma-names = "tx", "rx"; 972 status = "disabled"; 973 }; 974 975 spi0: spi@980000 { 976 compatible = "qcom,geni-spi"; 977 reg = <0 0x00980000 0 0x4000>; 978 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 979 clock-names = "se"; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 982 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 power-domains = <&rpmhpd SC7280_CX>; 986 operating-points-v2 = <&qup_opp_table>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 989 interconnect-names = "qup-core", "qup-config"; 990 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 991 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 992 dma-names = "tx", "rx"; 993 status = "disabled"; 994 }; 995 996 uart0: serial@980000 { 997 compatible = "qcom,geni-uart"; 998 reg = <0 0x00980000 0 0x4000>; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1000 clock-names = "se"; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1003 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1004 power-domains = <&rpmhpd SC7280_CX>; 1005 operating-points-v2 = <&qup_opp_table>; 1006 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1007 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1008 interconnect-names = "qup-core", "qup-config"; 1009 status = "disabled"; 1010 }; 1011 1012 i2c1: i2c@984000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x00984000 0 0x4000>; 1015 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1016 clock-names = "se"; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_i2c1_data_clk>; 1019 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1023 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1024 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1025 interconnect-names = "qup-core", "qup-config", 1026 "qup-memory"; 1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 status = "disabled"; 1031 }; 1032 1033 spi1: spi@984000 { 1034 compatible = "qcom,geni-spi"; 1035 reg = <0 0x00984000 0 0x4000>; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1037 clock-names = "se"; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1040 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 power-domains = <&rpmhpd SC7280_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1049 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1050 dma-names = "tx", "rx"; 1051 status = "disabled"; 1052 }; 1053 1054 uart1: serial@984000 { 1055 compatible = "qcom,geni-uart"; 1056 reg = <0 0x00984000 0 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1058 clock-names = "se"; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1061 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1062 power-domains = <&rpmhpd SC7280_CX>; 1063 operating-points-v2 = <&qup_opp_table>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1066 interconnect-names = "qup-core", "qup-config"; 1067 status = "disabled"; 1068 }; 1069 1070 i2c2: i2c@988000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0 0x00988000 0 0x4000>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1074 clock-names = "se"; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_i2c2_data_clk>; 1077 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1082 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1083 interconnect-names = "qup-core", "qup-config", 1084 "qup-memory"; 1085 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1086 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1087 dma-names = "tx", "rx"; 1088 status = "disabled"; 1089 }; 1090 1091 spi2: spi@988000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0 0x00988000 0 0x4000>; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1095 clock-names = "se"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1098 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 power-domains = <&rpmhpd SC7280_CX>; 1102 operating-points-v2 = <&qup_opp_table>; 1103 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1104 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1105 interconnect-names = "qup-core", "qup-config"; 1106 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1107 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1108 dma-names = "tx", "rx"; 1109 status = "disabled"; 1110 }; 1111 1112 uart2: serial@988000 { 1113 compatible = "qcom,geni-uart"; 1114 reg = <0 0x00988000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1116 clock-names = "se"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1119 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1120 power-domains = <&rpmhpd SC7280_CX>; 1121 operating-points-v2 = <&qup_opp_table>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1124 interconnect-names = "qup-core", "qup-config"; 1125 status = "disabled"; 1126 }; 1127 1128 i2c3: i2c@98c000 { 1129 compatible = "qcom,geni-i2c"; 1130 reg = <0 0x0098c000 0 0x4000>; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1132 clock-names = "se"; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_i2c3_data_clk>; 1135 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1139 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1140 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1141 interconnect-names = "qup-core", "qup-config", 1142 "qup-memory"; 1143 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1144 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1145 dma-names = "tx", "rx"; 1146 status = "disabled"; 1147 }; 1148 1149 spi3: spi@98c000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0 0x0098c000 0 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1153 clock-names = "se"; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1156 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 power-domains = <&rpmhpd SC7280_CX>; 1160 operating-points-v2 = <&qup_opp_table>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1162 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1165 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1166 dma-names = "tx", "rx"; 1167 status = "disabled"; 1168 }; 1169 1170 uart3: serial@98c000 { 1171 compatible = "qcom,geni-uart"; 1172 reg = <0 0x0098c000 0 0x4000>; 1173 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1174 clock-names = "se"; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1177 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1178 power-domains = <&rpmhpd SC7280_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1181 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1182 interconnect-names = "qup-core", "qup-config"; 1183 status = "disabled"; 1184 }; 1185 1186 i2c4: i2c@990000 { 1187 compatible = "qcom,geni-i2c"; 1188 reg = <0 0x00990000 0 0x4000>; 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1190 clock-names = "se"; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_i2c4_data_clk>; 1193 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1197 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1198 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1199 interconnect-names = "qup-core", "qup-config", 1200 "qup-memory"; 1201 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1202 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1203 dma-names = "tx", "rx"; 1204 status = "disabled"; 1205 }; 1206 1207 spi4: spi@990000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x00990000 0 0x4000>; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1211 clock-names = "se"; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1214 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 power-domains = <&rpmhpd SC7280_CX>; 1218 operating-points-v2 = <&qup_opp_table>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1223 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1224 dma-names = "tx", "rx"; 1225 status = "disabled"; 1226 }; 1227 1228 uart4: serial@990000 { 1229 compatible = "qcom,geni-uart"; 1230 reg = <0 0x00990000 0 0x4000>; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1232 clock-names = "se"; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1235 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1236 power-domains = <&rpmhpd SC7280_CX>; 1237 operating-points-v2 = <&qup_opp_table>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1239 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1240 interconnect-names = "qup-core", "qup-config"; 1241 status = "disabled"; 1242 }; 1243 1244 i2c5: i2c@994000 { 1245 compatible = "qcom,geni-i2c"; 1246 reg = <0 0x00994000 0 0x4000>; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1248 clock-names = "se"; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_i2c5_data_clk>; 1251 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1255 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1256 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1257 interconnect-names = "qup-core", "qup-config", 1258 "qup-memory"; 1259 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1260 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1261 dma-names = "tx", "rx"; 1262 status = "disabled"; 1263 }; 1264 1265 spi5: spi@994000 { 1266 compatible = "qcom,geni-spi"; 1267 reg = <0 0x00994000 0 0x4000>; 1268 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1269 clock-names = "se"; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1272 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 power-domains = <&rpmhpd SC7280_CX>; 1276 operating-points-v2 = <&qup_opp_table>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1278 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1279 interconnect-names = "qup-core", "qup-config"; 1280 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1281 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1282 dma-names = "tx", "rx"; 1283 status = "disabled"; 1284 }; 1285 1286 uart5: serial@994000 { 1287 compatible = "qcom,geni-uart"; 1288 reg = <0 0x00994000 0 0x4000>; 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1290 clock-names = "se"; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1293 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1294 power-domains = <&rpmhpd SC7280_CX>; 1295 operating-points-v2 = <&qup_opp_table>; 1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1297 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1298 interconnect-names = "qup-core", "qup-config"; 1299 status = "disabled"; 1300 }; 1301 1302 i2c6: i2c@998000 { 1303 compatible = "qcom,geni-i2c"; 1304 reg = <0 0x00998000 0 0x4000>; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1306 clock-names = "se"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_i2c6_data_clk>; 1309 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1313 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1314 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1315 interconnect-names = "qup-core", "qup-config", 1316 "qup-memory"; 1317 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1318 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1319 dma-names = "tx", "rx"; 1320 status = "disabled"; 1321 }; 1322 1323 spi6: spi@998000 { 1324 compatible = "qcom,geni-spi"; 1325 reg = <0 0x00998000 0 0x4000>; 1326 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1327 clock-names = "se"; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1330 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 power-domains = <&rpmhpd SC7280_CX>; 1334 operating-points-v2 = <&qup_opp_table>; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1336 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1337 interconnect-names = "qup-core", "qup-config"; 1338 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1339 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1340 dma-names = "tx", "rx"; 1341 status = "disabled"; 1342 }; 1343 1344 uart6: serial@998000 { 1345 compatible = "qcom,geni-uart"; 1346 reg = <0 0x00998000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1348 clock-names = "se"; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1351 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1352 power-domains = <&rpmhpd SC7280_CX>; 1353 operating-points-v2 = <&qup_opp_table>; 1354 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1355 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1356 interconnect-names = "qup-core", "qup-config"; 1357 status = "disabled"; 1358 }; 1359 1360 i2c7: i2c@99c000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x0099c000 0 0x4000>; 1363 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1364 clock-names = "se"; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c7_data_clk>; 1367 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1372 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", 1374 "qup-memory"; 1375 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1376 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1377 dma-names = "tx", "rx"; 1378 status = "disabled"; 1379 }; 1380 1381 spi7: spi@99c000 { 1382 compatible = "qcom,geni-spi"; 1383 reg = <0 0x0099c000 0 0x4000>; 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1385 clock-names = "se"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1388 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 power-domains = <&rpmhpd SC7280_CX>; 1392 operating-points-v2 = <&qup_opp_table>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1394 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1395 interconnect-names = "qup-core", "qup-config"; 1396 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1397 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1398 dma-names = "tx", "rx"; 1399 status = "disabled"; 1400 }; 1401 1402 uart7: serial@99c000 { 1403 compatible = "qcom,geni-uart"; 1404 reg = <0 0x0099c000 0 0x4000>; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1406 clock-names = "se"; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1409 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd SC7280_CX>; 1411 operating-points-v2 = <&qup_opp_table>; 1412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1413 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1414 interconnect-names = "qup-core", "qup-config"; 1415 status = "disabled"; 1416 }; 1417 }; 1418 1419 gpi_dma1: dma-controller@a00000 { 1420 #dma-cells = <3>; 1421 compatible = "qcom,sc7280-gpi-dma"; 1422 reg = <0 0x00a00000 0 0x60000>; 1423 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1435 dma-channels = <12>; 1436 dma-channel-mask = <0x1e>; 1437 iommus = <&apps_smmu 0x56 0x0>; 1438 status = "disabled"; 1439 }; 1440 1441 qupv3_id_1: geniqup@ac0000 { 1442 compatible = "qcom,geni-se-qup"; 1443 reg = <0 0x00ac0000 0 0x2000>; 1444 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1445 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1446 clock-names = "m-ahb", "s-ahb"; 1447 #address-cells = <2>; 1448 #size-cells = <2>; 1449 ranges; 1450 iommus = <&apps_smmu 0x43 0x0>; 1451 status = "disabled"; 1452 1453 i2c8: i2c@a80000 { 1454 compatible = "qcom,geni-i2c"; 1455 reg = <0 0x00a80000 0 0x4000>; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1457 clock-names = "se"; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_i2c8_data_clk>; 1460 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1465 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1466 interconnect-names = "qup-core", "qup-config", 1467 "qup-memory"; 1468 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1469 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1470 dma-names = "tx", "rx"; 1471 status = "disabled"; 1472 }; 1473 1474 spi8: spi@a80000 { 1475 compatible = "qcom,geni-spi"; 1476 reg = <0 0x00a80000 0 0x4000>; 1477 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1478 clock-names = "se"; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1481 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 power-domains = <&rpmhpd SC7280_CX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1488 interconnect-names = "qup-core", "qup-config"; 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1490 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1491 dma-names = "tx", "rx"; 1492 status = "disabled"; 1493 }; 1494 1495 uart8: serial@a80000 { 1496 compatible = "qcom,geni-uart"; 1497 reg = <0 0x00a80000 0 0x4000>; 1498 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1499 clock-names = "se"; 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1502 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1503 power-domains = <&rpmhpd SC7280_CX>; 1504 operating-points-v2 = <&qup_opp_table>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 status = "disabled"; 1509 }; 1510 1511 i2c9: i2c@a84000 { 1512 compatible = "qcom,geni-i2c"; 1513 reg = <0 0x00a84000 0 0x4000>; 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1515 clock-names = "se"; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&qup_i2c9_data_clk>; 1518 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1523 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1524 interconnect-names = "qup-core", "qup-config", 1525 "qup-memory"; 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1528 dma-names = "tx", "rx"; 1529 status = "disabled"; 1530 }; 1531 1532 spi9: spi@a84000 { 1533 compatible = "qcom,geni-spi"; 1534 reg = <0 0x00a84000 0 0x4000>; 1535 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1536 clock-names = "se"; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1539 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 power-domains = <&rpmhpd SC7280_CX>; 1543 operating-points-v2 = <&qup_opp_table>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1546 interconnect-names = "qup-core", "qup-config"; 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 status = "disabled"; 1551 }; 1552 1553 uart9: serial@a84000 { 1554 compatible = "qcom,geni-uart"; 1555 reg = <0 0x00a84000 0 0x4000>; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1557 clock-names = "se"; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1560 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1561 power-domains = <&rpmhpd SC7280_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1565 interconnect-names = "qup-core", "qup-config"; 1566 status = "disabled"; 1567 }; 1568 1569 i2c10: i2c@a88000 { 1570 compatible = "qcom,geni-i2c"; 1571 reg = <0 0x00a88000 0 0x4000>; 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1573 clock-names = "se"; 1574 pinctrl-names = "default"; 1575 pinctrl-0 = <&qup_i2c10_data_clk>; 1576 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1580 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1581 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1582 interconnect-names = "qup-core", "qup-config", 1583 "qup-memory"; 1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1585 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1586 dma-names = "tx", "rx"; 1587 status = "disabled"; 1588 }; 1589 1590 spi10: spi@a88000 { 1591 compatible = "qcom,geni-spi"; 1592 reg = <0 0x00a88000 0 0x4000>; 1593 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1594 clock-names = "se"; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1597 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 power-domains = <&rpmhpd SC7280_CX>; 1601 operating-points-v2 = <&qup_opp_table>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1604 interconnect-names = "qup-core", "qup-config"; 1605 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 status = "disabled"; 1609 }; 1610 1611 uart10: serial@a88000 { 1612 compatible = "qcom,geni-uart"; 1613 reg = <0 0x00a88000 0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1615 clock-names = "se"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1618 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1619 power-domains = <&rpmhpd SC7280_CX>; 1620 operating-points-v2 = <&qup_opp_table>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1623 interconnect-names = "qup-core", "qup-config"; 1624 status = "disabled"; 1625 }; 1626 1627 i2c11: i2c@a8c000 { 1628 compatible = "qcom,geni-i2c"; 1629 reg = <0 0x00a8c000 0 0x4000>; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1631 clock-names = "se"; 1632 pinctrl-names = "default"; 1633 pinctrl-0 = <&qup_i2c11_data_clk>; 1634 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1639 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1640 interconnect-names = "qup-core", "qup-config", 1641 "qup-memory"; 1642 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1643 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1644 dma-names = "tx", "rx"; 1645 status = "disabled"; 1646 }; 1647 1648 spi11: spi@a8c000 { 1649 compatible = "qcom,geni-spi"; 1650 reg = <0 0x00a8c000 0 0x4000>; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1652 clock-names = "se"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1655 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 power-domains = <&rpmhpd SC7280_CX>; 1659 operating-points-v2 = <&qup_opp_table>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1662 interconnect-names = "qup-core", "qup-config"; 1663 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1664 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1665 dma-names = "tx", "rx"; 1666 status = "disabled"; 1667 }; 1668 1669 uart11: serial@a8c000 { 1670 compatible = "qcom,geni-uart"; 1671 reg = <0 0x00a8c000 0 0x4000>; 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1673 clock-names = "se"; 1674 pinctrl-names = "default"; 1675 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1676 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1677 power-domains = <&rpmhpd SC7280_CX>; 1678 operating-points-v2 = <&qup_opp_table>; 1679 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1680 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1681 interconnect-names = "qup-core", "qup-config"; 1682 status = "disabled"; 1683 }; 1684 1685 i2c12: i2c@a90000 { 1686 compatible = "qcom,geni-i2c"; 1687 reg = <0 0x00a90000 0 0x4000>; 1688 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1689 clock-names = "se"; 1690 pinctrl-names = "default"; 1691 pinctrl-0 = <&qup_i2c12_data_clk>; 1692 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1696 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1697 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1698 interconnect-names = "qup-core", "qup-config", 1699 "qup-memory"; 1700 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1701 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1702 dma-names = "tx", "rx"; 1703 status = "disabled"; 1704 }; 1705 1706 spi12: spi@a90000 { 1707 compatible = "qcom,geni-spi"; 1708 reg = <0 0x00a90000 0 0x4000>; 1709 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1710 clock-names = "se"; 1711 pinctrl-names = "default"; 1712 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1713 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 power-domains = <&rpmhpd SC7280_CX>; 1717 operating-points-v2 = <&qup_opp_table>; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1720 interconnect-names = "qup-core", "qup-config"; 1721 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1722 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1723 dma-names = "tx", "rx"; 1724 status = "disabled"; 1725 }; 1726 1727 uart12: serial@a90000 { 1728 compatible = "qcom,geni-uart"; 1729 reg = <0 0x00a90000 0 0x4000>; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1731 clock-names = "se"; 1732 pinctrl-names = "default"; 1733 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1734 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1735 power-domains = <&rpmhpd SC7280_CX>; 1736 operating-points-v2 = <&qup_opp_table>; 1737 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1738 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1739 interconnect-names = "qup-core", "qup-config"; 1740 status = "disabled"; 1741 }; 1742 1743 i2c13: i2c@a94000 { 1744 compatible = "qcom,geni-i2c"; 1745 reg = <0 0x00a94000 0 0x4000>; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1747 clock-names = "se"; 1748 pinctrl-names = "default"; 1749 pinctrl-0 = <&qup_i2c13_data_clk>; 1750 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1755 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1756 interconnect-names = "qup-core", "qup-config", 1757 "qup-memory"; 1758 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1759 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1760 dma-names = "tx", "rx"; 1761 status = "disabled"; 1762 }; 1763 1764 spi13: spi@a94000 { 1765 compatible = "qcom,geni-spi"; 1766 reg = <0 0x00a94000 0 0x4000>; 1767 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1768 clock-names = "se"; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1771 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 power-domains = <&rpmhpd SC7280_CX>; 1775 operating-points-v2 = <&qup_opp_table>; 1776 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1777 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1778 interconnect-names = "qup-core", "qup-config"; 1779 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1780 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1781 dma-names = "tx", "rx"; 1782 status = "disabled"; 1783 }; 1784 1785 uart13: serial@a94000 { 1786 compatible = "qcom,geni-uart"; 1787 reg = <0 0x00a94000 0 0x4000>; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1789 clock-names = "se"; 1790 pinctrl-names = "default"; 1791 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1792 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1793 power-domains = <&rpmhpd SC7280_CX>; 1794 operating-points-v2 = <&qup_opp_table>; 1795 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1796 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1797 interconnect-names = "qup-core", "qup-config"; 1798 status = "disabled"; 1799 }; 1800 1801 i2c14: i2c@a98000 { 1802 compatible = "qcom,geni-i2c"; 1803 reg = <0 0x00a98000 0 0x4000>; 1804 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1805 clock-names = "se"; 1806 pinctrl-names = "default"; 1807 pinctrl-0 = <&qup_i2c14_data_clk>; 1808 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1812 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1813 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1814 interconnect-names = "qup-core", "qup-config", 1815 "qup-memory"; 1816 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1817 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1818 dma-names = "tx", "rx"; 1819 status = "disabled"; 1820 }; 1821 1822 spi14: spi@a98000 { 1823 compatible = "qcom,geni-spi"; 1824 reg = <0 0x00a98000 0 0x4000>; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1826 clock-names = "se"; 1827 pinctrl-names = "default"; 1828 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1829 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 power-domains = <&rpmhpd SC7280_CX>; 1833 operating-points-v2 = <&qup_opp_table>; 1834 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1835 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1836 interconnect-names = "qup-core", "qup-config"; 1837 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1838 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1839 dma-names = "tx", "rx"; 1840 status = "disabled"; 1841 }; 1842 1843 uart14: serial@a98000 { 1844 compatible = "qcom,geni-uart"; 1845 reg = <0 0x00a98000 0 0x4000>; 1846 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1847 clock-names = "se"; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1850 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1851 power-domains = <&rpmhpd SC7280_CX>; 1852 operating-points-v2 = <&qup_opp_table>; 1853 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1854 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1855 interconnect-names = "qup-core", "qup-config"; 1856 status = "disabled"; 1857 }; 1858 1859 i2c15: i2c@a9c000 { 1860 compatible = "qcom,geni-i2c"; 1861 reg = <0 0x00a9c000 0 0x4000>; 1862 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1863 clock-names = "se"; 1864 pinctrl-names = "default"; 1865 pinctrl-0 = <&qup_i2c15_data_clk>; 1866 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1870 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1871 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1872 interconnect-names = "qup-core", "qup-config", 1873 "qup-memory"; 1874 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1875 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1876 dma-names = "tx", "rx"; 1877 status = "disabled"; 1878 }; 1879 1880 spi15: spi@a9c000 { 1881 compatible = "qcom,geni-spi"; 1882 reg = <0 0x00a9c000 0 0x4000>; 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1884 clock-names = "se"; 1885 pinctrl-names = "default"; 1886 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1887 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 power-domains = <&rpmhpd SC7280_CX>; 1891 operating-points-v2 = <&qup_opp_table>; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1893 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1894 interconnect-names = "qup-core", "qup-config"; 1895 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1896 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1897 dma-names = "tx", "rx"; 1898 status = "disabled"; 1899 }; 1900 1901 uart15: serial@a9c000 { 1902 compatible = "qcom,geni-uart"; 1903 reg = <0 0x00a9c000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1908 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1909 power-domains = <&rpmhpd SC7280_CX>; 1910 operating-points-v2 = <&qup_opp_table>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1913 interconnect-names = "qup-core", "qup-config"; 1914 status = "disabled"; 1915 }; 1916 }; 1917 1918 cnoc2: interconnect@1500000 { 1919 reg = <0 0x01500000 0 0x1000>; 1920 compatible = "qcom,sc7280-cnoc2"; 1921 #interconnect-cells = <2>; 1922 qcom,bcm-voters = <&apps_bcm_voter>; 1923 }; 1924 1925 cnoc3: interconnect@1502000 { 1926 reg = <0 0x01502000 0 0x1000>; 1927 compatible = "qcom,sc7280-cnoc3"; 1928 #interconnect-cells = <2>; 1929 qcom,bcm-voters = <&apps_bcm_voter>; 1930 }; 1931 1932 mc_virt: interconnect@1580000 { 1933 reg = <0 0x01580000 0 0x4>; 1934 compatible = "qcom,sc7280-mc-virt"; 1935 #interconnect-cells = <2>; 1936 qcom,bcm-voters = <&apps_bcm_voter>; 1937 }; 1938 1939 system_noc: interconnect@1680000 { 1940 reg = <0 0x01680000 0 0x15480>; 1941 compatible = "qcom,sc7280-system-noc"; 1942 #interconnect-cells = <2>; 1943 qcom,bcm-voters = <&apps_bcm_voter>; 1944 }; 1945 1946 aggre1_noc: interconnect@16e0000 { 1947 compatible = "qcom,sc7280-aggre1-noc"; 1948 reg = <0 0x016e0000 0 0x1c080>; 1949 #interconnect-cells = <2>; 1950 qcom,bcm-voters = <&apps_bcm_voter>; 1951 }; 1952 1953 aggre2_noc: interconnect@1700000 { 1954 reg = <0 0x01700000 0 0x2b080>; 1955 compatible = "qcom,sc7280-aggre2-noc"; 1956 #interconnect-cells = <2>; 1957 qcom,bcm-voters = <&apps_bcm_voter>; 1958 }; 1959 1960 mmss_noc: interconnect@1740000 { 1961 reg = <0 0x01740000 0 0x1e080>; 1962 compatible = "qcom,sc7280-mmss-noc"; 1963 #interconnect-cells = <2>; 1964 qcom,bcm-voters = <&apps_bcm_voter>; 1965 }; 1966 1967 wifi: wifi@17a10040 { 1968 compatible = "qcom,wcn6750-wifi"; 1969 reg = <0 0x17a10040 0 0x0>; 1970 iommus = <&apps_smmu 0x1c00 0x1>; 1971 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1979 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1980 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1981 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1982 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1983 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1984 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1985 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1986 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1987 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1988 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1989 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1990 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1991 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1992 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1993 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1994 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1995 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1996 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1997 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1998 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2002 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2003 qcom,rproc = <&remoteproc_wpss>; 2004 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2005 status = "disabled"; 2006 }; 2007 2008 pcie1: pci@1c08000 { 2009 compatible = "qcom,pcie-sc7280"; 2010 reg = <0 0x01c08000 0 0x3000>, 2011 <0 0x40000000 0 0xf1d>, 2012 <0 0x40000f20 0 0xa8>, 2013 <0 0x40001000 0 0x1000>, 2014 <0 0x40100000 0 0x100000>; 2015 2016 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2017 device_type = "pci"; 2018 linux,pci-domain = <1>; 2019 bus-range = <0x00 0xff>; 2020 num-lanes = <2>; 2021 2022 #address-cells = <3>; 2023 #size-cells = <2>; 2024 2025 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2026 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2027 2028 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2029 interrupt-names = "msi"; 2030 #interrupt-cells = <1>; 2031 interrupt-map-mask = <0 0 0 0x7>; 2032 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2033 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2034 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2035 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2036 2037 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2038 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2039 <&pcie1_lane>, 2040 <&rpmhcc RPMH_CXO_CLK>, 2041 <&gcc GCC_PCIE_1_AUX_CLK>, 2042 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2043 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2044 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2045 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2046 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2047 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2048 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2049 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2050 2051 clock-names = "pipe", 2052 "pipe_mux", 2053 "phy_pipe", 2054 "ref", 2055 "aux", 2056 "cfg", 2057 "bus_master", 2058 "bus_slave", 2059 "slave_q2a", 2060 "tbu", 2061 "ddrss_sf_tbu", 2062 "aggre0", 2063 "aggre1"; 2064 2065 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2066 assigned-clock-rates = <19200000>; 2067 2068 resets = <&gcc GCC_PCIE_1_BCR>; 2069 reset-names = "pci"; 2070 2071 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2072 2073 phys = <&pcie1_lane>; 2074 phy-names = "pciephy"; 2075 2076 pinctrl-names = "default"; 2077 pinctrl-0 = <&pcie1_clkreq_n>; 2078 2079 iommus = <&apps_smmu 0x1c80 0x1>; 2080 2081 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2082 <0x100 &apps_smmu 0x1c81 0x1>; 2083 2084 status = "disabled"; 2085 }; 2086 2087 pcie1_phy: phy@1c0e000 { 2088 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2089 reg = <0 0x01c0e000 0 0x1c0>; 2090 #address-cells = <2>; 2091 #size-cells = <2>; 2092 ranges; 2093 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2094 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2095 <&gcc GCC_PCIE_CLKREF_EN>, 2096 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2097 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2098 2099 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2100 reset-names = "phy"; 2101 2102 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2103 assigned-clock-rates = <100000000>; 2104 2105 status = "disabled"; 2106 2107 pcie1_lane: phy@1c0e200 { 2108 reg = <0 0x01c0e200 0 0x170>, 2109 <0 0x01c0e400 0 0x200>, 2110 <0 0x01c0ea00 0 0x1f0>, 2111 <0 0x01c0e600 0 0x170>, 2112 <0 0x01c0e800 0 0x200>, 2113 <0 0x01c0ee00 0 0xf4>; 2114 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2115 clock-names = "pipe0"; 2116 2117 #phy-cells = <0>; 2118 #clock-cells = <0>; 2119 clock-output-names = "pcie_1_pipe_clk"; 2120 }; 2121 }; 2122 2123 ipa: ipa@1e40000 { 2124 compatible = "qcom,sc7280-ipa"; 2125 2126 iommus = <&apps_smmu 0x480 0x0>, 2127 <&apps_smmu 0x482 0x0>; 2128 reg = <0 0x1e40000 0 0x8000>, 2129 <0 0x1e50000 0 0x4ad0>, 2130 <0 0x1e04000 0 0x23000>; 2131 reg-names = "ipa-reg", 2132 "ipa-shared", 2133 "gsi"; 2134 2135 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2136 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2137 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2138 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2139 interrupt-names = "ipa", 2140 "gsi", 2141 "ipa-clock-query", 2142 "ipa-setup-ready"; 2143 2144 clocks = <&rpmhcc RPMH_IPA_CLK>; 2145 clock-names = "core"; 2146 2147 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2148 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2149 interconnect-names = "memory", 2150 "config"; 2151 2152 qcom,qmp = <&aoss_qmp>; 2153 2154 qcom,smem-states = <&ipa_smp2p_out 0>, 2155 <&ipa_smp2p_out 1>; 2156 qcom,smem-state-names = "ipa-clock-enabled-valid", 2157 "ipa-clock-enabled"; 2158 2159 status = "disabled"; 2160 }; 2161 2162 tcsr_mutex: hwlock@1f40000 { 2163 compatible = "qcom,tcsr-mutex"; 2164 reg = <0 0x01f40000 0 0x20000>; 2165 #hwlock-cells = <1>; 2166 }; 2167 2168 tcsr_1: syscon@1f60000 { 2169 compatible = "qcom,sc7280-tcsr", "syscon"; 2170 reg = <0 0x01f60000 0 0x20000>; 2171 }; 2172 2173 tcsr_2: syscon@1fc0000 { 2174 compatible = "qcom,sc7280-tcsr", "syscon"; 2175 reg = <0 0x01fc0000 0 0x30000>; 2176 }; 2177 2178 lpasscc: lpasscc@3000000 { 2179 compatible = "qcom,sc7280-lpasscc"; 2180 reg = <0 0x03000000 0 0x40>, 2181 <0 0x03c04000 0 0x4>; 2182 reg-names = "qdsp6ss", "top_cc"; 2183 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2184 clock-names = "iface"; 2185 #clock-cells = <1>; 2186 }; 2187 2188 lpass_rx_macro: codec@3200000 { 2189 compatible = "qcom,sc7280-lpass-rx-macro"; 2190 reg = <0 0x03200000 0 0x1000>; 2191 2192 pinctrl-names = "default"; 2193 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2194 2195 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2196 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2197 <&lpass_va_macro>; 2198 clock-names = "mclk", "npl", "fsgen"; 2199 2200 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2201 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2202 power-domain-names = "macro", "dcodec"; 2203 2204 #clock-cells = <0>; 2205 #sound-dai-cells = <1>; 2206 2207 status = "disabled"; 2208 }; 2209 2210 swr0: soundwire@3210000 { 2211 compatible = "qcom,soundwire-v1.6.0"; 2212 reg = <0 0x03210000 0 0x2000>; 2213 2214 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2215 clocks = <&lpass_rx_macro>; 2216 clock-names = "iface"; 2217 2218 qcom,din-ports = <0>; 2219 qcom,dout-ports = <5>; 2220 2221 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2222 reset-names = "swr_audio_cgcr"; 2223 2224 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2225 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2226 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2227 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2228 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2229 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2230 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2231 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2232 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2233 2234 #sound-dai-cells = <1>; 2235 #address-cells = <2>; 2236 #size-cells = <0>; 2237 2238 status = "disabled"; 2239 }; 2240 2241 lpass_tx_macro: codec@3220000 { 2242 compatible = "qcom,sc7280-lpass-tx-macro"; 2243 reg = <0 0x03220000 0 0x1000>; 2244 2245 pinctrl-names = "default"; 2246 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2247 2248 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2249 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2250 <&lpass_va_macro>; 2251 clock-names = "mclk", "npl", "fsgen"; 2252 2253 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2254 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2255 power-domain-names = "macro", "dcodec"; 2256 2257 #clock-cells = <0>; 2258 #sound-dai-cells = <1>; 2259 2260 status = "disabled"; 2261 }; 2262 2263 swr1: soundwire@3230000 { 2264 compatible = "qcom,soundwire-v1.6.0"; 2265 reg = <0 0x03230000 0 0x2000>; 2266 2267 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2268 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2269 clocks = <&lpass_tx_macro>; 2270 clock-names = "iface"; 2271 2272 qcom,din-ports = <3>; 2273 qcom,dout-ports = <0>; 2274 2275 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2276 reset-names = "swr_audio_cgcr"; 2277 2278 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2279 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2280 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2281 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2282 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2283 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2284 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2285 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2286 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2287 qcom,port-offset = <1>; 2288 2289 #sound-dai-cells = <1>; 2290 #address-cells = <2>; 2291 #size-cells = <0>; 2292 2293 status = "disabled"; 2294 }; 2295 2296 lpass_audiocc: clock-controller@3300000 { 2297 compatible = "qcom,sc7280-lpassaudiocc"; 2298 reg = <0 0x03300000 0 0x30000>; 2299 clocks = <&rpmhcc RPMH_CXO_CLK>, 2300 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2301 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2302 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2303 #clock-cells = <1>; 2304 #power-domain-cells = <1>; 2305 #reset-cells = <1>; 2306 }; 2307 2308 lpass_va_macro: codec@3370000 { 2309 compatible = "qcom,sc7280-lpass-va-macro"; 2310 reg = <0 0x03370000 0 0x1000>; 2311 2312 pinctrl-names = "default"; 2313 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2314 2315 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2316 clock-names = "mclk"; 2317 2318 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2319 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2320 power-domain-names = "macro", "dcodec"; 2321 2322 #clock-cells = <0>; 2323 #sound-dai-cells = <1>; 2324 2325 status = "disabled"; 2326 }; 2327 2328 lpass_aon: clock-controller@3380000 { 2329 compatible = "qcom,sc7280-lpassaoncc"; 2330 reg = <0 0x03380000 0 0x30000>; 2331 clocks = <&rpmhcc RPMH_CXO_CLK>, 2332 <&rpmhcc RPMH_CXO_CLK_A>, 2333 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2334 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2335 #clock-cells = <1>; 2336 #power-domain-cells = <1>; 2337 }; 2338 2339 lpass_core: clock-controller@3900000 { 2340 compatible = "qcom,sc7280-lpasscorecc"; 2341 reg = <0 0x03900000 0 0x50000>; 2342 clocks = <&rpmhcc RPMH_CXO_CLK>; 2343 clock-names = "bi_tcxo"; 2344 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2345 #clock-cells = <1>; 2346 #power-domain-cells = <1>; 2347 }; 2348 2349 lpass_cpu: audio@3987000 { 2350 compatible = "qcom,sc7280-lpass-cpu"; 2351 2352 reg = <0 0x03987000 0 0x68000>, 2353 <0 0x03b00000 0 0x29000>, 2354 <0 0x03260000 0 0xc000>, 2355 <0 0x03280000 0 0x29000>, 2356 <0 0x03340000 0 0x29000>, 2357 <0 0x0336c000 0 0x3000>; 2358 reg-names = "lpass-hdmiif", 2359 "lpass-lpaif", 2360 "lpass-rxtx-cdc-dma-lpm", 2361 "lpass-rxtx-lpaif", 2362 "lpass-va-lpaif", 2363 "lpass-va-cdc-dma-lpm"; 2364 2365 iommus = <&apps_smmu 0x1820 0>, 2366 <&apps_smmu 0x1821 0>, 2367 <&apps_smmu 0x1832 0>; 2368 2369 power-domains = <&rpmhpd SC7280_LCX>; 2370 power-domain-names = "lcx"; 2371 required-opps = <&rpmhpd_opp_nom>; 2372 2373 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2374 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2375 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2376 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2377 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2378 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2379 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2380 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2381 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2382 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2383 clock-names = "aon_cc_audio_hm_h", 2384 "audio_cc_ext_mclk0", 2385 "core_cc_sysnoc_mport_core", 2386 "core_cc_ext_if0_ibit", 2387 "core_cc_ext_if1_ibit", 2388 "audio_cc_codec_mem", 2389 "audio_cc_codec_mem0", 2390 "audio_cc_codec_mem1", 2391 "audio_cc_codec_mem2", 2392 "aon_cc_va_mem0"; 2393 2394 #sound-dai-cells = <1>; 2395 #address-cells = <1>; 2396 #size-cells = <0>; 2397 2398 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2402 interrupt-names = "lpass-irq-lpaif", 2403 "lpass-irq-hdmi", 2404 "lpass-irq-vaif", 2405 "lpass-irq-rxtxif"; 2406 2407 status = "disabled"; 2408 }; 2409 2410 lpass_hm: clock-controller@3c00000 { 2411 compatible = "qcom,sc7280-lpasshm"; 2412 reg = <0 0x3c00000 0 0x28>; 2413 clocks = <&rpmhcc RPMH_CXO_CLK>; 2414 clock-names = "bi_tcxo"; 2415 #clock-cells = <1>; 2416 #power-domain-cells = <1>; 2417 }; 2418 2419 lpass_ag_noc: interconnect@3c40000 { 2420 reg = <0 0x03c40000 0 0xf080>; 2421 compatible = "qcom,sc7280-lpass-ag-noc"; 2422 #interconnect-cells = <2>; 2423 qcom,bcm-voters = <&apps_bcm_voter>; 2424 }; 2425 2426 lpass_tlmm: pinctrl@33c0000 { 2427 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2428 reg = <0 0x033c0000 0x0 0x20000>, 2429 <0 0x03550000 0x0 0x10000>; 2430 qcom,adsp-bypass-mode; 2431 gpio-controller; 2432 #gpio-cells = <2>; 2433 gpio-ranges = <&lpass_tlmm 0 0 15>; 2434 2435 #clock-cells = <1>; 2436 2437 lpass_dmic01_clk: dmic01-clk { 2438 pins = "gpio6"; 2439 function = "dmic1_clk"; 2440 }; 2441 2442 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2443 pins = "gpio6"; 2444 function = "dmic1_clk"; 2445 }; 2446 2447 lpass_dmic01_data: dmic01-data { 2448 pins = "gpio7"; 2449 function = "dmic1_data"; 2450 }; 2451 2452 lpass_dmic01_data_sleep: dmic01-data-sleep { 2453 pins = "gpio7"; 2454 function = "dmic1_data"; 2455 }; 2456 2457 lpass_dmic23_clk: dmic23-clk { 2458 pins = "gpio8"; 2459 function = "dmic2_clk"; 2460 }; 2461 2462 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2463 pins = "gpio8"; 2464 function = "dmic2_clk"; 2465 }; 2466 2467 lpass_dmic23_data: dmic23-data { 2468 pins = "gpio9"; 2469 function = "dmic2_data"; 2470 }; 2471 2472 lpass_dmic23_data_sleep: dmic23-data-sleep { 2473 pins = "gpio9"; 2474 function = "dmic2_data"; 2475 }; 2476 2477 lpass_rx_swr_clk: rx-swr-clk { 2478 pins = "gpio3"; 2479 function = "swr_rx_clk"; 2480 }; 2481 2482 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2483 pins = "gpio3"; 2484 function = "swr_rx_clk"; 2485 }; 2486 2487 lpass_rx_swr_data: rx-swr-data { 2488 pins = "gpio4", "gpio5"; 2489 function = "swr_rx_data"; 2490 }; 2491 2492 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2493 pins = "gpio4", "gpio5"; 2494 function = "swr_rx_data"; 2495 }; 2496 2497 lpass_tx_swr_clk: tx-swr-clk { 2498 pins = "gpio0"; 2499 function = "swr_tx_clk"; 2500 }; 2501 2502 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2503 pins = "gpio0"; 2504 function = "swr_tx_clk"; 2505 }; 2506 2507 lpass_tx_swr_data: tx-swr-data { 2508 pins = "gpio1", "gpio2", "gpio14"; 2509 function = "swr_tx_data"; 2510 }; 2511 2512 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2513 pins = "gpio1", "gpio2", "gpio14"; 2514 function = "swr_tx_data"; 2515 }; 2516 }; 2517 2518 gpu: gpu@3d00000 { 2519 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2520 reg = <0 0x03d00000 0 0x40000>, 2521 <0 0x03d9e000 0 0x1000>, 2522 <0 0x03d61000 0 0x800>; 2523 reg-names = "kgsl_3d0_reg_memory", 2524 "cx_mem", 2525 "cx_dbgc"; 2526 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2527 iommus = <&adreno_smmu 0 0x401>; 2528 operating-points-v2 = <&gpu_opp_table>; 2529 qcom,gmu = <&gmu>; 2530 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2531 interconnect-names = "gfx-mem"; 2532 #cooling-cells = <2>; 2533 2534 nvmem-cells = <&gpu_speed_bin>; 2535 nvmem-cell-names = "speed_bin"; 2536 2537 gpu_opp_table: opp-table { 2538 compatible = "operating-points-v2"; 2539 2540 opp-315000000 { 2541 opp-hz = /bits/ 64 <315000000>; 2542 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2543 opp-peak-kBps = <1804000>; 2544 opp-supported-hw = <0x03>; 2545 }; 2546 2547 opp-450000000 { 2548 opp-hz = /bits/ 64 <450000000>; 2549 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2550 opp-peak-kBps = <4068000>; 2551 opp-supported-hw = <0x03>; 2552 }; 2553 2554 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2555 opp-550000000-0 { 2556 opp-hz = /bits/ 64 <550000000>; 2557 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2558 opp-peak-kBps = <8368000>; 2559 opp-supported-hw = <0x01>; 2560 }; 2561 2562 opp-550000000-1 { 2563 opp-hz = /bits/ 64 <550000000>; 2564 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2565 opp-peak-kBps = <6832000>; 2566 opp-supported-hw = <0x02>; 2567 }; 2568 2569 opp-608000000 { 2570 opp-hz = /bits/ 64 <608000000>; 2571 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2572 opp-peak-kBps = <8368000>; 2573 opp-supported-hw = <0x02>; 2574 }; 2575 2576 opp-700000000 { 2577 opp-hz = /bits/ 64 <700000000>; 2578 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2579 opp-peak-kBps = <8532000>; 2580 opp-supported-hw = <0x02>; 2581 }; 2582 2583 opp-812000000 { 2584 opp-hz = /bits/ 64 <812000000>; 2585 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2586 opp-peak-kBps = <8532000>; 2587 opp-supported-hw = <0x02>; 2588 }; 2589 2590 opp-840000000 { 2591 opp-hz = /bits/ 64 <840000000>; 2592 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2593 opp-peak-kBps = <8532000>; 2594 opp-supported-hw = <0x02>; 2595 }; 2596 2597 opp-900000000 { 2598 opp-hz = /bits/ 64 <900000000>; 2599 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2600 opp-peak-kBps = <8532000>; 2601 opp-supported-hw = <0x02>; 2602 }; 2603 }; 2604 }; 2605 2606 gmu: gmu@3d6a000 { 2607 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2608 reg = <0 0x03d6a000 0 0x34000>, 2609 <0 0x3de0000 0 0x10000>, 2610 <0 0x0b290000 0 0x10000>; 2611 reg-names = "gmu", "rscc", "gmu_pdc"; 2612 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2614 interrupt-names = "hfi", "gmu"; 2615 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2616 <&gpucc GPU_CC_CXO_CLK>, 2617 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2618 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2619 <&gpucc GPU_CC_AHB_CLK>, 2620 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2621 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2622 clock-names = "gmu", 2623 "cxo", 2624 "axi", 2625 "memnoc", 2626 "ahb", 2627 "hub", 2628 "smmu_vote"; 2629 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2630 <&gpucc GPU_CC_GX_GDSC>; 2631 power-domain-names = "cx", 2632 "gx"; 2633 iommus = <&adreno_smmu 5 0x400>; 2634 operating-points-v2 = <&gmu_opp_table>; 2635 2636 gmu_opp_table: opp-table { 2637 compatible = "operating-points-v2"; 2638 2639 opp-200000000 { 2640 opp-hz = /bits/ 64 <200000000>; 2641 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2642 }; 2643 }; 2644 }; 2645 2646 gpucc: clock-controller@3d90000 { 2647 compatible = "qcom,sc7280-gpucc"; 2648 reg = <0 0x03d90000 0 0x9000>; 2649 clocks = <&rpmhcc RPMH_CXO_CLK>, 2650 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2651 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2652 clock-names = "bi_tcxo", 2653 "gcc_gpu_gpll0_clk_src", 2654 "gcc_gpu_gpll0_div_clk_src"; 2655 #clock-cells = <1>; 2656 #reset-cells = <1>; 2657 #power-domain-cells = <1>; 2658 }; 2659 2660 adreno_smmu: iommu@3da0000 { 2661 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2662 reg = <0 0x03da0000 0 0x20000>; 2663 #iommu-cells = <2>; 2664 #global-interrupts = <2>; 2665 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2676 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2677 2678 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2679 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2680 <&gpucc GPU_CC_AHB_CLK>, 2681 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2682 <&gpucc GPU_CC_CX_GMU_CLK>, 2683 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2684 <&gpucc GPU_CC_HUB_AON_CLK>; 2685 clock-names = "gcc_gpu_memnoc_gfx_clk", 2686 "gcc_gpu_snoc_dvm_gfx_clk", 2687 "gpu_cc_ahb_clk", 2688 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2689 "gpu_cc_cx_gmu_clk", 2690 "gpu_cc_hub_cx_int_clk", 2691 "gpu_cc_hub_aon_clk"; 2692 2693 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2694 }; 2695 2696 remoteproc_mpss: remoteproc@4080000 { 2697 compatible = "qcom,sc7280-mpss-pas"; 2698 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2699 reg-names = "qdsp6", "rmb"; 2700 2701 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2702 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2703 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2704 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2705 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2706 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2707 interrupt-names = "wdog", "fatal", "ready", "handover", 2708 "stop-ack", "shutdown-ack"; 2709 2710 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2711 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2712 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2713 <&rpmhcc RPMH_PKA_CLK>, 2714 <&rpmhcc RPMH_CXO_CLK>; 2715 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2716 2717 power-domains = <&rpmhpd SC7280_CX>, 2718 <&rpmhpd SC7280_MSS>; 2719 power-domain-names = "cx", "mss"; 2720 2721 memory-region = <&mpss_mem>; 2722 2723 qcom,qmp = <&aoss_qmp>; 2724 2725 qcom,smem-states = <&modem_smp2p_out 0>; 2726 qcom,smem-state-names = "stop"; 2727 2728 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2729 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2730 reset-names = "mss_restart", "pdc_reset"; 2731 2732 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2733 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2734 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2735 2736 status = "disabled"; 2737 2738 glink-edge { 2739 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2740 IPCC_MPROC_SIGNAL_GLINK_QMP 2741 IRQ_TYPE_EDGE_RISING>; 2742 mboxes = <&ipcc IPCC_CLIENT_MPSS 2743 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2744 label = "modem"; 2745 qcom,remote-pid = <1>; 2746 }; 2747 }; 2748 2749 stm@6002000 { 2750 compatible = "arm,coresight-stm", "arm,primecell"; 2751 reg = <0 0x06002000 0 0x1000>, 2752 <0 0x16280000 0 0x180000>; 2753 reg-names = "stm-base", "stm-stimulus-base"; 2754 2755 clocks = <&aoss_qmp>; 2756 clock-names = "apb_pclk"; 2757 2758 out-ports { 2759 port { 2760 stm_out: endpoint { 2761 remote-endpoint = <&funnel0_in7>; 2762 }; 2763 }; 2764 }; 2765 }; 2766 2767 funnel@6041000 { 2768 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2769 reg = <0 0x06041000 0 0x1000>; 2770 2771 clocks = <&aoss_qmp>; 2772 clock-names = "apb_pclk"; 2773 2774 out-ports { 2775 port { 2776 funnel0_out: endpoint { 2777 remote-endpoint = <&merge_funnel_in0>; 2778 }; 2779 }; 2780 }; 2781 2782 in-ports { 2783 #address-cells = <1>; 2784 #size-cells = <0>; 2785 2786 port@7 { 2787 reg = <7>; 2788 funnel0_in7: endpoint { 2789 remote-endpoint = <&stm_out>; 2790 }; 2791 }; 2792 }; 2793 }; 2794 2795 funnel@6042000 { 2796 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2797 reg = <0 0x06042000 0 0x1000>; 2798 2799 clocks = <&aoss_qmp>; 2800 clock-names = "apb_pclk"; 2801 2802 out-ports { 2803 port { 2804 funnel1_out: endpoint { 2805 remote-endpoint = <&merge_funnel_in1>; 2806 }; 2807 }; 2808 }; 2809 2810 in-ports { 2811 #address-cells = <1>; 2812 #size-cells = <0>; 2813 2814 port@4 { 2815 reg = <4>; 2816 funnel1_in4: endpoint { 2817 remote-endpoint = <&apss_merge_funnel_out>; 2818 }; 2819 }; 2820 }; 2821 }; 2822 2823 funnel@6045000 { 2824 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2825 reg = <0 0x06045000 0 0x1000>; 2826 2827 clocks = <&aoss_qmp>; 2828 clock-names = "apb_pclk"; 2829 2830 out-ports { 2831 port { 2832 merge_funnel_out: endpoint { 2833 remote-endpoint = <&swao_funnel_in>; 2834 }; 2835 }; 2836 }; 2837 2838 in-ports { 2839 #address-cells = <1>; 2840 #size-cells = <0>; 2841 2842 port@0 { 2843 reg = <0>; 2844 merge_funnel_in0: endpoint { 2845 remote-endpoint = <&funnel0_out>; 2846 }; 2847 }; 2848 2849 port@1 { 2850 reg = <1>; 2851 merge_funnel_in1: endpoint { 2852 remote-endpoint = <&funnel1_out>; 2853 }; 2854 }; 2855 }; 2856 }; 2857 2858 replicator@6046000 { 2859 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2860 reg = <0 0x06046000 0 0x1000>; 2861 2862 clocks = <&aoss_qmp>; 2863 clock-names = "apb_pclk"; 2864 2865 out-ports { 2866 port { 2867 replicator_out: endpoint { 2868 remote-endpoint = <&etr_in>; 2869 }; 2870 }; 2871 }; 2872 2873 in-ports { 2874 port { 2875 replicator_in: endpoint { 2876 remote-endpoint = <&swao_replicator_out>; 2877 }; 2878 }; 2879 }; 2880 }; 2881 2882 etr@6048000 { 2883 compatible = "arm,coresight-tmc", "arm,primecell"; 2884 reg = <0 0x06048000 0 0x1000>; 2885 iommus = <&apps_smmu 0x04c0 0>; 2886 2887 clocks = <&aoss_qmp>; 2888 clock-names = "apb_pclk"; 2889 arm,scatter-gather; 2890 2891 in-ports { 2892 port { 2893 etr_in: endpoint { 2894 remote-endpoint = <&replicator_out>; 2895 }; 2896 }; 2897 }; 2898 }; 2899 2900 funnel@6b04000 { 2901 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2902 reg = <0 0x06b04000 0 0x1000>; 2903 2904 clocks = <&aoss_qmp>; 2905 clock-names = "apb_pclk"; 2906 2907 out-ports { 2908 port { 2909 swao_funnel_out: endpoint { 2910 remote-endpoint = <&etf_in>; 2911 }; 2912 }; 2913 }; 2914 2915 in-ports { 2916 #address-cells = <1>; 2917 #size-cells = <0>; 2918 2919 port@7 { 2920 reg = <7>; 2921 swao_funnel_in: endpoint { 2922 remote-endpoint = <&merge_funnel_out>; 2923 }; 2924 }; 2925 }; 2926 }; 2927 2928 etf@6b05000 { 2929 compatible = "arm,coresight-tmc", "arm,primecell"; 2930 reg = <0 0x06b05000 0 0x1000>; 2931 2932 clocks = <&aoss_qmp>; 2933 clock-names = "apb_pclk"; 2934 2935 out-ports { 2936 port { 2937 etf_out: endpoint { 2938 remote-endpoint = <&swao_replicator_in>; 2939 }; 2940 }; 2941 }; 2942 2943 in-ports { 2944 port { 2945 etf_in: endpoint { 2946 remote-endpoint = <&swao_funnel_out>; 2947 }; 2948 }; 2949 }; 2950 }; 2951 2952 replicator@6b06000 { 2953 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2954 reg = <0 0x06b06000 0 0x1000>; 2955 2956 clocks = <&aoss_qmp>; 2957 clock-names = "apb_pclk"; 2958 qcom,replicator-loses-context; 2959 2960 out-ports { 2961 port { 2962 swao_replicator_out: endpoint { 2963 remote-endpoint = <&replicator_in>; 2964 }; 2965 }; 2966 }; 2967 2968 in-ports { 2969 port { 2970 swao_replicator_in: endpoint { 2971 remote-endpoint = <&etf_out>; 2972 }; 2973 }; 2974 }; 2975 }; 2976 2977 etm@7040000 { 2978 compatible = "arm,coresight-etm4x", "arm,primecell"; 2979 reg = <0 0x07040000 0 0x1000>; 2980 2981 cpu = <&CPU0>; 2982 2983 clocks = <&aoss_qmp>; 2984 clock-names = "apb_pclk"; 2985 arm,coresight-loses-context-with-cpu; 2986 qcom,skip-power-up; 2987 2988 out-ports { 2989 port { 2990 etm0_out: endpoint { 2991 remote-endpoint = <&apss_funnel_in0>; 2992 }; 2993 }; 2994 }; 2995 }; 2996 2997 etm@7140000 { 2998 compatible = "arm,coresight-etm4x", "arm,primecell"; 2999 reg = <0 0x07140000 0 0x1000>; 3000 3001 cpu = <&CPU1>; 3002 3003 clocks = <&aoss_qmp>; 3004 clock-names = "apb_pclk"; 3005 arm,coresight-loses-context-with-cpu; 3006 qcom,skip-power-up; 3007 3008 out-ports { 3009 port { 3010 etm1_out: endpoint { 3011 remote-endpoint = <&apss_funnel_in1>; 3012 }; 3013 }; 3014 }; 3015 }; 3016 3017 etm@7240000 { 3018 compatible = "arm,coresight-etm4x", "arm,primecell"; 3019 reg = <0 0x07240000 0 0x1000>; 3020 3021 cpu = <&CPU2>; 3022 3023 clocks = <&aoss_qmp>; 3024 clock-names = "apb_pclk"; 3025 arm,coresight-loses-context-with-cpu; 3026 qcom,skip-power-up; 3027 3028 out-ports { 3029 port { 3030 etm2_out: endpoint { 3031 remote-endpoint = <&apss_funnel_in2>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 3037 etm@7340000 { 3038 compatible = "arm,coresight-etm4x", "arm,primecell"; 3039 reg = <0 0x07340000 0 0x1000>; 3040 3041 cpu = <&CPU3>; 3042 3043 clocks = <&aoss_qmp>; 3044 clock-names = "apb_pclk"; 3045 arm,coresight-loses-context-with-cpu; 3046 qcom,skip-power-up; 3047 3048 out-ports { 3049 port { 3050 etm3_out: endpoint { 3051 remote-endpoint = <&apss_funnel_in3>; 3052 }; 3053 }; 3054 }; 3055 }; 3056 3057 etm@7440000 { 3058 compatible = "arm,coresight-etm4x", "arm,primecell"; 3059 reg = <0 0x07440000 0 0x1000>; 3060 3061 cpu = <&CPU4>; 3062 3063 clocks = <&aoss_qmp>; 3064 clock-names = "apb_pclk"; 3065 arm,coresight-loses-context-with-cpu; 3066 qcom,skip-power-up; 3067 3068 out-ports { 3069 port { 3070 etm4_out: endpoint { 3071 remote-endpoint = <&apss_funnel_in4>; 3072 }; 3073 }; 3074 }; 3075 }; 3076 3077 etm@7540000 { 3078 compatible = "arm,coresight-etm4x", "arm,primecell"; 3079 reg = <0 0x07540000 0 0x1000>; 3080 3081 cpu = <&CPU5>; 3082 3083 clocks = <&aoss_qmp>; 3084 clock-names = "apb_pclk"; 3085 arm,coresight-loses-context-with-cpu; 3086 qcom,skip-power-up; 3087 3088 out-ports { 3089 port { 3090 etm5_out: endpoint { 3091 remote-endpoint = <&apss_funnel_in5>; 3092 }; 3093 }; 3094 }; 3095 }; 3096 3097 etm@7640000 { 3098 compatible = "arm,coresight-etm4x", "arm,primecell"; 3099 reg = <0 0x07640000 0 0x1000>; 3100 3101 cpu = <&CPU6>; 3102 3103 clocks = <&aoss_qmp>; 3104 clock-names = "apb_pclk"; 3105 arm,coresight-loses-context-with-cpu; 3106 qcom,skip-power-up; 3107 3108 out-ports { 3109 port { 3110 etm6_out: endpoint { 3111 remote-endpoint = <&apss_funnel_in6>; 3112 }; 3113 }; 3114 }; 3115 }; 3116 3117 etm@7740000 { 3118 compatible = "arm,coresight-etm4x", "arm,primecell"; 3119 reg = <0 0x07740000 0 0x1000>; 3120 3121 cpu = <&CPU7>; 3122 3123 clocks = <&aoss_qmp>; 3124 clock-names = "apb_pclk"; 3125 arm,coresight-loses-context-with-cpu; 3126 qcom,skip-power-up; 3127 3128 out-ports { 3129 port { 3130 etm7_out: endpoint { 3131 remote-endpoint = <&apss_funnel_in7>; 3132 }; 3133 }; 3134 }; 3135 }; 3136 3137 funnel@7800000 { /* APSS Funnel */ 3138 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3139 reg = <0 0x07800000 0 0x1000>; 3140 3141 clocks = <&aoss_qmp>; 3142 clock-names = "apb_pclk"; 3143 3144 out-ports { 3145 port { 3146 apss_funnel_out: endpoint { 3147 remote-endpoint = <&apss_merge_funnel_in>; 3148 }; 3149 }; 3150 }; 3151 3152 in-ports { 3153 #address-cells = <1>; 3154 #size-cells = <0>; 3155 3156 port@0 { 3157 reg = <0>; 3158 apss_funnel_in0: endpoint { 3159 remote-endpoint = <&etm0_out>; 3160 }; 3161 }; 3162 3163 port@1 { 3164 reg = <1>; 3165 apss_funnel_in1: endpoint { 3166 remote-endpoint = <&etm1_out>; 3167 }; 3168 }; 3169 3170 port@2 { 3171 reg = <2>; 3172 apss_funnel_in2: endpoint { 3173 remote-endpoint = <&etm2_out>; 3174 }; 3175 }; 3176 3177 port@3 { 3178 reg = <3>; 3179 apss_funnel_in3: endpoint { 3180 remote-endpoint = <&etm3_out>; 3181 }; 3182 }; 3183 3184 port@4 { 3185 reg = <4>; 3186 apss_funnel_in4: endpoint { 3187 remote-endpoint = <&etm4_out>; 3188 }; 3189 }; 3190 3191 port@5 { 3192 reg = <5>; 3193 apss_funnel_in5: endpoint { 3194 remote-endpoint = <&etm5_out>; 3195 }; 3196 }; 3197 3198 port@6 { 3199 reg = <6>; 3200 apss_funnel_in6: endpoint { 3201 remote-endpoint = <&etm6_out>; 3202 }; 3203 }; 3204 3205 port@7 { 3206 reg = <7>; 3207 apss_funnel_in7: endpoint { 3208 remote-endpoint = <&etm7_out>; 3209 }; 3210 }; 3211 }; 3212 }; 3213 3214 funnel@7810000 { 3215 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3216 reg = <0 0x07810000 0 0x1000>; 3217 3218 clocks = <&aoss_qmp>; 3219 clock-names = "apb_pclk"; 3220 3221 out-ports { 3222 port { 3223 apss_merge_funnel_out: endpoint { 3224 remote-endpoint = <&funnel1_in4>; 3225 }; 3226 }; 3227 }; 3228 3229 in-ports { 3230 port { 3231 apss_merge_funnel_in: endpoint { 3232 remote-endpoint = <&apss_funnel_out>; 3233 }; 3234 }; 3235 }; 3236 }; 3237 3238 sdhc_2: mmc@8804000 { 3239 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3240 pinctrl-names = "default", "sleep"; 3241 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3242 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3243 status = "disabled"; 3244 3245 reg = <0 0x08804000 0 0x1000>; 3246 3247 iommus = <&apps_smmu 0x100 0x0>; 3248 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3250 interrupt-names = "hc_irq", "pwr_irq"; 3251 3252 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3253 <&gcc GCC_SDCC2_APPS_CLK>, 3254 <&rpmhcc RPMH_CXO_CLK>; 3255 clock-names = "iface", "core", "xo"; 3256 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3257 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3258 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3259 power-domains = <&rpmhpd SC7280_CX>; 3260 operating-points-v2 = <&sdhc2_opp_table>; 3261 3262 bus-width = <4>; 3263 3264 qcom,dll-config = <0x0007642c>; 3265 3266 resets = <&gcc GCC_SDCC2_BCR>; 3267 3268 sdhc2_opp_table: opp-table { 3269 compatible = "operating-points-v2"; 3270 3271 opp-100000000 { 3272 opp-hz = /bits/ 64 <100000000>; 3273 required-opps = <&rpmhpd_opp_low_svs>; 3274 opp-peak-kBps = <1800000 400000>; 3275 opp-avg-kBps = <100000 0>; 3276 }; 3277 3278 opp-202000000 { 3279 opp-hz = /bits/ 64 <202000000>; 3280 required-opps = <&rpmhpd_opp_nom>; 3281 opp-peak-kBps = <5400000 1600000>; 3282 opp-avg-kBps = <200000 0>; 3283 }; 3284 }; 3285 3286 }; 3287 3288 usb_1_hsphy: phy@88e3000 { 3289 compatible = "qcom,sc7280-usb-hs-phy", 3290 "qcom,usb-snps-hs-7nm-phy"; 3291 reg = <0 0x088e3000 0 0x400>; 3292 status = "disabled"; 3293 #phy-cells = <0>; 3294 3295 clocks = <&rpmhcc RPMH_CXO_CLK>; 3296 clock-names = "ref"; 3297 3298 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3299 }; 3300 3301 usb_2_hsphy: phy@88e4000 { 3302 compatible = "qcom,sc7280-usb-hs-phy", 3303 "qcom,usb-snps-hs-7nm-phy"; 3304 reg = <0 0x088e4000 0 0x400>; 3305 status = "disabled"; 3306 #phy-cells = <0>; 3307 3308 clocks = <&rpmhcc RPMH_CXO_CLK>; 3309 clock-names = "ref"; 3310 3311 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3312 }; 3313 3314 usb_1_qmpphy: phy-wrapper@88e9000 { 3315 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3316 "qcom,sm8250-qmp-usb3-dp-phy"; 3317 reg = <0 0x088e9000 0 0x200>, 3318 <0 0x088e8000 0 0x40>, 3319 <0 0x088ea000 0 0x200>; 3320 status = "disabled"; 3321 #address-cells = <2>; 3322 #size-cells = <2>; 3323 ranges; 3324 3325 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3326 <&rpmhcc RPMH_CXO_CLK>, 3327 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3328 clock-names = "aux", "ref_clk_src", "com_aux"; 3329 3330 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3331 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3332 reset-names = "phy", "common"; 3333 3334 usb_1_ssphy: usb3-phy@88e9200 { 3335 reg = <0 0x088e9200 0 0x200>, 3336 <0 0x088e9400 0 0x200>, 3337 <0 0x088e9c00 0 0x400>, 3338 <0 0x088e9600 0 0x200>, 3339 <0 0x088e9800 0 0x200>, 3340 <0 0x088e9a00 0 0x100>; 3341 #clock-cells = <0>; 3342 #phy-cells = <0>; 3343 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3344 clock-names = "pipe0"; 3345 clock-output-names = "usb3_phy_pipe_clk_src"; 3346 }; 3347 3348 dp_phy: dp-phy@88ea200 { 3349 reg = <0 0x088ea200 0 0x200>, 3350 <0 0x088ea400 0 0x200>, 3351 <0 0x088eaa00 0 0x200>, 3352 <0 0x088ea600 0 0x200>, 3353 <0 0x088ea800 0 0x200>; 3354 #phy-cells = <0>; 3355 #clock-cells = <1>; 3356 }; 3357 }; 3358 3359 usb_2: usb@8cf8800 { 3360 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3361 reg = <0 0x08cf8800 0 0x400>; 3362 status = "disabled"; 3363 #address-cells = <2>; 3364 #size-cells = <2>; 3365 ranges; 3366 dma-ranges; 3367 3368 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3369 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3370 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3371 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3372 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3373 clock-names = "cfg_noc", 3374 "core", 3375 "iface", 3376 "sleep", 3377 "mock_utmi"; 3378 3379 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3380 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3381 assigned-clock-rates = <19200000>, <200000000>; 3382 3383 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3384 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3385 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3386 interrupt-names = "hs_phy_irq", 3387 "dp_hs_phy_irq", 3388 "dm_hs_phy_irq"; 3389 3390 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3391 3392 resets = <&gcc GCC_USB30_SEC_BCR>; 3393 3394 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3395 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3396 interconnect-names = "usb-ddr", "apps-usb"; 3397 3398 usb_2_dwc3: usb@8c00000 { 3399 compatible = "snps,dwc3"; 3400 reg = <0 0x08c00000 0 0xe000>; 3401 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3402 iommus = <&apps_smmu 0xa0 0x0>; 3403 snps,dis_u2_susphy_quirk; 3404 snps,dis_enblslpm_quirk; 3405 phys = <&usb_2_hsphy>; 3406 phy-names = "usb2-phy"; 3407 maximum-speed = "high-speed"; 3408 usb-role-switch; 3409 port { 3410 usb2_role_switch: endpoint { 3411 remote-endpoint = <&eud_ep>; 3412 }; 3413 }; 3414 }; 3415 }; 3416 3417 qspi: spi@88dc000 { 3418 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3419 reg = <0 0x088dc000 0 0x1000>; 3420 #address-cells = <1>; 3421 #size-cells = <0>; 3422 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3423 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3424 <&gcc GCC_QSPI_CORE_CLK>; 3425 clock-names = "iface", "core"; 3426 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3427 &cnoc2 SLAVE_QSPI_0 0>; 3428 interconnect-names = "qspi-config"; 3429 power-domains = <&rpmhpd SC7280_CX>; 3430 operating-points-v2 = <&qspi_opp_table>; 3431 status = "disabled"; 3432 }; 3433 3434 remoteproc_wpss: remoteproc@8a00000 { 3435 compatible = "qcom,sc7280-wpss-pil"; 3436 reg = <0 0x08a00000 0 0x10000>; 3437 3438 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3439 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3440 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3441 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3442 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3443 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3444 interrupt-names = "wdog", "fatal", "ready", "handover", 3445 "stop-ack", "shutdown-ack"; 3446 3447 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3448 <&gcc GCC_WPSS_AHB_CLK>, 3449 <&gcc GCC_WPSS_RSCP_CLK>, 3450 <&rpmhcc RPMH_CXO_CLK>; 3451 clock-names = "ahb_bdg", "ahb", 3452 "rscp", "xo"; 3453 3454 power-domains = <&rpmhpd SC7280_CX>, 3455 <&rpmhpd SC7280_MX>; 3456 power-domain-names = "cx", "mx"; 3457 3458 memory-region = <&wpss_mem>; 3459 3460 qcom,qmp = <&aoss_qmp>; 3461 3462 qcom,smem-states = <&wpss_smp2p_out 0>; 3463 qcom,smem-state-names = "stop"; 3464 3465 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3466 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3467 reset-names = "restart", "pdc_sync"; 3468 3469 qcom,halt-regs = <&tcsr_1 0x17000>; 3470 3471 status = "disabled"; 3472 3473 glink-edge { 3474 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3475 IPCC_MPROC_SIGNAL_GLINK_QMP 3476 IRQ_TYPE_EDGE_RISING>; 3477 mboxes = <&ipcc IPCC_CLIENT_WPSS 3478 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3479 3480 label = "wpss"; 3481 qcom,remote-pid = <13>; 3482 }; 3483 }; 3484 3485 pmu@9091000 { 3486 compatible = "qcom,sc7280-llcc-bwmon"; 3487 reg = <0 0x9091000 0 0x1000>; 3488 3489 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3490 3491 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3492 3493 operating-points-v2 = <&llcc_bwmon_opp_table>; 3494 3495 llcc_bwmon_opp_table: opp-table { 3496 compatible = "operating-points-v2"; 3497 3498 opp-0 { 3499 opp-peak-kBps = <800000>; 3500 }; 3501 opp-1 { 3502 opp-peak-kBps = <1804000>; 3503 }; 3504 opp-2 { 3505 opp-peak-kBps = <2188000>; 3506 }; 3507 opp-3 { 3508 opp-peak-kBps = <3072000>; 3509 }; 3510 opp-4 { 3511 opp-peak-kBps = <4068000>; 3512 }; 3513 opp-5 { 3514 opp-peak-kBps = <6220000>; 3515 }; 3516 opp-6 { 3517 opp-peak-kBps = <6832000>; 3518 }; 3519 opp-7 { 3520 opp-peak-kBps = <8532000>; 3521 }; 3522 }; 3523 }; 3524 3525 pmu@90b6400 { 3526 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3527 reg = <0 0x090b6400 0 0x600>; 3528 3529 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3530 3531 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3532 operating-points-v2 = <&cpu_bwmon_opp_table>; 3533 3534 cpu_bwmon_opp_table: opp-table { 3535 compatible = "operating-points-v2"; 3536 3537 opp-0 { 3538 opp-peak-kBps = <2400000>; 3539 }; 3540 opp-1 { 3541 opp-peak-kBps = <4800000>; 3542 }; 3543 opp-2 { 3544 opp-peak-kBps = <7456000>; 3545 }; 3546 opp-3 { 3547 opp-peak-kBps = <9600000>; 3548 }; 3549 opp-4 { 3550 opp-peak-kBps = <12896000>; 3551 }; 3552 opp-5 { 3553 opp-peak-kBps = <14928000>; 3554 }; 3555 opp-6 { 3556 opp-peak-kBps = <17056000>; 3557 }; 3558 }; 3559 }; 3560 3561 dc_noc: interconnect@90e0000 { 3562 reg = <0 0x090e0000 0 0x5080>; 3563 compatible = "qcom,sc7280-dc-noc"; 3564 #interconnect-cells = <2>; 3565 qcom,bcm-voters = <&apps_bcm_voter>; 3566 }; 3567 3568 gem_noc: interconnect@9100000 { 3569 reg = <0 0x9100000 0 0xe2200>; 3570 compatible = "qcom,sc7280-gem-noc"; 3571 #interconnect-cells = <2>; 3572 qcom,bcm-voters = <&apps_bcm_voter>; 3573 }; 3574 3575 system-cache-controller@9200000 { 3576 compatible = "qcom,sc7280-llcc"; 3577 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3578 reg-names = "llcc_base", "llcc_broadcast_base"; 3579 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3580 }; 3581 3582 eud: eud@88e0000 { 3583 compatible = "qcom,sc7280-eud","qcom,eud"; 3584 reg = <0 0x88e0000 0 0x2000>, 3585 <0 0x88e2000 0 0x1000>; 3586 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3587 ports { 3588 port@0 { 3589 eud_ep: endpoint { 3590 remote-endpoint = <&usb2_role_switch>; 3591 }; 3592 }; 3593 port@1 { 3594 eud_con: endpoint { 3595 remote-endpoint = <&con_eud>; 3596 }; 3597 }; 3598 }; 3599 }; 3600 3601 eud_typec: connector { 3602 compatible = "usb-c-connector"; 3603 ports { 3604 port@0 { 3605 con_eud: endpoint { 3606 remote-endpoint = <&eud_con>; 3607 }; 3608 }; 3609 }; 3610 }; 3611 3612 nsp_noc: interconnect@a0c0000 { 3613 reg = <0 0x0a0c0000 0 0x10000>; 3614 compatible = "qcom,sc7280-nsp-noc"; 3615 #interconnect-cells = <2>; 3616 qcom,bcm-voters = <&apps_bcm_voter>; 3617 }; 3618 3619 usb_1: usb@a6f8800 { 3620 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3621 reg = <0 0x0a6f8800 0 0x400>; 3622 status = "disabled"; 3623 #address-cells = <2>; 3624 #size-cells = <2>; 3625 ranges; 3626 dma-ranges; 3627 3628 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3629 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3630 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3631 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3632 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3633 clock-names = "cfg_noc", 3634 "core", 3635 "iface", 3636 "sleep", 3637 "mock_utmi"; 3638 3639 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3640 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3641 assigned-clock-rates = <19200000>, <200000000>; 3642 3643 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3644 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3645 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3646 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3647 interrupt-names = "hs_phy_irq", 3648 "dp_hs_phy_irq", 3649 "dm_hs_phy_irq", 3650 "ss_phy_irq"; 3651 3652 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3653 3654 resets = <&gcc GCC_USB30_PRIM_BCR>; 3655 3656 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3657 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3658 interconnect-names = "usb-ddr", "apps-usb"; 3659 3660 usb_1_dwc3: usb@a600000 { 3661 compatible = "snps,dwc3"; 3662 reg = <0 0x0a600000 0 0xe000>; 3663 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3664 iommus = <&apps_smmu 0xe0 0x0>; 3665 snps,dis_u2_susphy_quirk; 3666 snps,dis_enblslpm_quirk; 3667 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3668 phy-names = "usb2-phy", "usb3-phy"; 3669 maximum-speed = "super-speed"; 3670 wakeup-source; 3671 }; 3672 }; 3673 3674 venus: video-codec@aa00000 { 3675 compatible = "qcom,sc7280-venus"; 3676 reg = <0 0x0aa00000 0 0xd0600>; 3677 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3678 3679 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3680 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3681 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3682 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3683 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3684 clock-names = "core", "bus", "iface", 3685 "vcodec_core", "vcodec_bus"; 3686 3687 power-domains = <&videocc MVSC_GDSC>, 3688 <&videocc MVS0_GDSC>, 3689 <&rpmhpd SC7280_CX>; 3690 power-domain-names = "venus", "vcodec0", "cx"; 3691 operating-points-v2 = <&venus_opp_table>; 3692 3693 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3694 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3695 interconnect-names = "cpu-cfg", "video-mem"; 3696 3697 iommus = <&apps_smmu 0x2180 0x20>, 3698 <&apps_smmu 0x2184 0x20>; 3699 memory-region = <&video_mem>; 3700 3701 video-decoder { 3702 compatible = "venus-decoder"; 3703 }; 3704 3705 video-encoder { 3706 compatible = "venus-encoder"; 3707 }; 3708 3709 video-firmware { 3710 iommus = <&apps_smmu 0x21a2 0x0>; 3711 }; 3712 3713 venus_opp_table: opp-table { 3714 compatible = "operating-points-v2"; 3715 3716 opp-133330000 { 3717 opp-hz = /bits/ 64 <133330000>; 3718 required-opps = <&rpmhpd_opp_low_svs>; 3719 }; 3720 3721 opp-240000000 { 3722 opp-hz = /bits/ 64 <240000000>; 3723 required-opps = <&rpmhpd_opp_svs>; 3724 }; 3725 3726 opp-335000000 { 3727 opp-hz = /bits/ 64 <335000000>; 3728 required-opps = <&rpmhpd_opp_svs_l1>; 3729 }; 3730 3731 opp-424000000 { 3732 opp-hz = /bits/ 64 <424000000>; 3733 required-opps = <&rpmhpd_opp_nom>; 3734 }; 3735 3736 opp-460000048 { 3737 opp-hz = /bits/ 64 <460000048>; 3738 required-opps = <&rpmhpd_opp_turbo>; 3739 }; 3740 }; 3741 3742 }; 3743 3744 videocc: clock-controller@aaf0000 { 3745 compatible = "qcom,sc7280-videocc"; 3746 reg = <0 0xaaf0000 0 0x10000>; 3747 clocks = <&rpmhcc RPMH_CXO_CLK>, 3748 <&rpmhcc RPMH_CXO_CLK_A>; 3749 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3750 #clock-cells = <1>; 3751 #reset-cells = <1>; 3752 #power-domain-cells = <1>; 3753 }; 3754 3755 camcc: clock-controller@ad00000 { 3756 compatible = "qcom,sc7280-camcc"; 3757 reg = <0 0x0ad00000 0 0x10000>; 3758 clocks = <&rpmhcc RPMH_CXO_CLK>, 3759 <&rpmhcc RPMH_CXO_CLK_A>, 3760 <&sleep_clk>; 3761 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3762 #clock-cells = <1>; 3763 #reset-cells = <1>; 3764 #power-domain-cells = <1>; 3765 }; 3766 3767 dispcc: clock-controller@af00000 { 3768 compatible = "qcom,sc7280-dispcc"; 3769 reg = <0 0xaf00000 0 0x20000>; 3770 clocks = <&rpmhcc RPMH_CXO_CLK>, 3771 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3772 <&mdss_dsi_phy 0>, 3773 <&mdss_dsi_phy 1>, 3774 <&dp_phy 0>, 3775 <&dp_phy 1>, 3776 <&mdss_edp_phy 0>, 3777 <&mdss_edp_phy 1>; 3778 clock-names = "bi_tcxo", 3779 "gcc_disp_gpll0_clk", 3780 "dsi0_phy_pll_out_byteclk", 3781 "dsi0_phy_pll_out_dsiclk", 3782 "dp_phy_pll_link_clk", 3783 "dp_phy_pll_vco_div_clk", 3784 "edp_phy_pll_link_clk", 3785 "edp_phy_pll_vco_div_clk"; 3786 #clock-cells = <1>; 3787 #reset-cells = <1>; 3788 #power-domain-cells = <1>; 3789 }; 3790 3791 mdss: display-subsystem@ae00000 { 3792 compatible = "qcom,sc7280-mdss"; 3793 reg = <0 0x0ae00000 0 0x1000>; 3794 reg-names = "mdss"; 3795 3796 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3797 3798 clocks = <&gcc GCC_DISP_AHB_CLK>, 3799 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3800 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3801 clock-names = "iface", 3802 "ahb", 3803 "core"; 3804 3805 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3806 interrupt-controller; 3807 #interrupt-cells = <1>; 3808 3809 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3810 interconnect-names = "mdp0-mem"; 3811 3812 iommus = <&apps_smmu 0x900 0x402>; 3813 3814 #address-cells = <2>; 3815 #size-cells = <2>; 3816 ranges; 3817 3818 status = "disabled"; 3819 3820 mdss_mdp: display-controller@ae01000 { 3821 compatible = "qcom,sc7280-dpu"; 3822 reg = <0 0x0ae01000 0 0x8f030>, 3823 <0 0x0aeb0000 0 0x2008>; 3824 reg-names = "mdp", "vbif"; 3825 3826 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3827 <&gcc GCC_DISP_SF_AXI_CLK>, 3828 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3829 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3830 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3831 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3832 clock-names = "bus", 3833 "nrt_bus", 3834 "iface", 3835 "lut", 3836 "core", 3837 "vsync"; 3838 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3839 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3840 assigned-clock-rates = <19200000>, 3841 <19200000>; 3842 operating-points-v2 = <&mdp_opp_table>; 3843 power-domains = <&rpmhpd SC7280_CX>; 3844 3845 interrupt-parent = <&mdss>; 3846 interrupts = <0>; 3847 3848 status = "disabled"; 3849 3850 ports { 3851 #address-cells = <1>; 3852 #size-cells = <0>; 3853 3854 port@0 { 3855 reg = <0>; 3856 dpu_intf1_out: endpoint { 3857 remote-endpoint = <&dsi0_in>; 3858 }; 3859 }; 3860 3861 port@1 { 3862 reg = <1>; 3863 dpu_intf5_out: endpoint { 3864 remote-endpoint = <&edp_in>; 3865 }; 3866 }; 3867 3868 port@2 { 3869 reg = <2>; 3870 dpu_intf0_out: endpoint { 3871 remote-endpoint = <&dp_in>; 3872 }; 3873 }; 3874 }; 3875 3876 mdp_opp_table: opp-table { 3877 compatible = "operating-points-v2"; 3878 3879 opp-200000000 { 3880 opp-hz = /bits/ 64 <200000000>; 3881 required-opps = <&rpmhpd_opp_low_svs>; 3882 }; 3883 3884 opp-300000000 { 3885 opp-hz = /bits/ 64 <300000000>; 3886 required-opps = <&rpmhpd_opp_svs>; 3887 }; 3888 3889 opp-380000000 { 3890 opp-hz = /bits/ 64 <380000000>; 3891 required-opps = <&rpmhpd_opp_svs_l1>; 3892 }; 3893 3894 opp-506666667 { 3895 opp-hz = /bits/ 64 <506666667>; 3896 required-opps = <&rpmhpd_opp_nom>; 3897 }; 3898 }; 3899 }; 3900 3901 mdss_dsi: dsi@ae94000 { 3902 compatible = "qcom,mdss-dsi-ctrl"; 3903 reg = <0 0x0ae94000 0 0x400>; 3904 reg-names = "dsi_ctrl"; 3905 3906 interrupt-parent = <&mdss>; 3907 interrupts = <4>; 3908 3909 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3910 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3911 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3912 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3913 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3914 <&gcc GCC_DISP_HF_AXI_CLK>; 3915 clock-names = "byte", 3916 "byte_intf", 3917 "pixel", 3918 "core", 3919 "iface", 3920 "bus"; 3921 3922 operating-points-v2 = <&dsi_opp_table>; 3923 power-domains = <&rpmhpd SC7280_CX>; 3924 3925 phys = <&mdss_dsi_phy>; 3926 phy-names = "dsi"; 3927 3928 #address-cells = <1>; 3929 #size-cells = <0>; 3930 3931 status = "disabled"; 3932 3933 ports { 3934 #address-cells = <1>; 3935 #size-cells = <0>; 3936 3937 port@0 { 3938 reg = <0>; 3939 dsi0_in: endpoint { 3940 remote-endpoint = <&dpu_intf1_out>; 3941 }; 3942 }; 3943 3944 port@1 { 3945 reg = <1>; 3946 dsi0_out: endpoint { 3947 }; 3948 }; 3949 }; 3950 3951 dsi_opp_table: opp-table { 3952 compatible = "operating-points-v2"; 3953 3954 opp-187500000 { 3955 opp-hz = /bits/ 64 <187500000>; 3956 required-opps = <&rpmhpd_opp_low_svs>; 3957 }; 3958 3959 opp-300000000 { 3960 opp-hz = /bits/ 64 <300000000>; 3961 required-opps = <&rpmhpd_opp_svs>; 3962 }; 3963 3964 opp-358000000 { 3965 opp-hz = /bits/ 64 <358000000>; 3966 required-opps = <&rpmhpd_opp_svs_l1>; 3967 }; 3968 }; 3969 }; 3970 3971 mdss_dsi_phy: phy@ae94400 { 3972 compatible = "qcom,sc7280-dsi-phy-7nm"; 3973 reg = <0 0x0ae94400 0 0x200>, 3974 <0 0x0ae94600 0 0x280>, 3975 <0 0x0ae94900 0 0x280>; 3976 reg-names = "dsi_phy", 3977 "dsi_phy_lane", 3978 "dsi_pll"; 3979 3980 #clock-cells = <1>; 3981 #phy-cells = <0>; 3982 3983 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3984 <&rpmhcc RPMH_CXO_CLK>; 3985 clock-names = "iface", "ref"; 3986 3987 status = "disabled"; 3988 }; 3989 3990 mdss_edp: edp@aea0000 { 3991 compatible = "qcom,sc7280-edp"; 3992 pinctrl-names = "default"; 3993 pinctrl-0 = <&edp_hot_plug_det>; 3994 3995 reg = <0 0xaea0000 0 0x200>, 3996 <0 0xaea0200 0 0x200>, 3997 <0 0xaea0400 0 0xc00>, 3998 <0 0xaea1000 0 0x400>; 3999 4000 interrupt-parent = <&mdss>; 4001 interrupts = <14>; 4002 4003 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4004 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4005 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4006 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4007 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4008 clock-names = "core_iface", 4009 "core_aux", 4010 "ctrl_link", 4011 "ctrl_link_iface", 4012 "stream_pixel"; 4013 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4014 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4015 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4016 4017 phys = <&mdss_edp_phy>; 4018 phy-names = "dp"; 4019 4020 operating-points-v2 = <&edp_opp_table>; 4021 power-domains = <&rpmhpd SC7280_CX>; 4022 4023 status = "disabled"; 4024 4025 ports { 4026 #address-cells = <1>; 4027 #size-cells = <0>; 4028 4029 port@0 { 4030 reg = <0>; 4031 edp_in: endpoint { 4032 remote-endpoint = <&dpu_intf5_out>; 4033 }; 4034 }; 4035 4036 port@1 { 4037 reg = <1>; 4038 mdss_edp_out: endpoint { }; 4039 }; 4040 }; 4041 4042 edp_opp_table: opp-table { 4043 compatible = "operating-points-v2"; 4044 4045 opp-160000000 { 4046 opp-hz = /bits/ 64 <160000000>; 4047 required-opps = <&rpmhpd_opp_low_svs>; 4048 }; 4049 4050 opp-270000000 { 4051 opp-hz = /bits/ 64 <270000000>; 4052 required-opps = <&rpmhpd_opp_svs>; 4053 }; 4054 4055 opp-540000000 { 4056 opp-hz = /bits/ 64 <540000000>; 4057 required-opps = <&rpmhpd_opp_nom>; 4058 }; 4059 4060 opp-810000000 { 4061 opp-hz = /bits/ 64 <810000000>; 4062 required-opps = <&rpmhpd_opp_nom>; 4063 }; 4064 }; 4065 }; 4066 4067 mdss_edp_phy: phy@aec2a00 { 4068 compatible = "qcom,sc7280-edp-phy"; 4069 4070 reg = <0 0xaec2a00 0 0x19c>, 4071 <0 0xaec2200 0 0xa0>, 4072 <0 0xaec2600 0 0xa0>, 4073 <0 0xaec2000 0 0x1c0>; 4074 4075 clocks = <&rpmhcc RPMH_CXO_CLK>, 4076 <&gcc GCC_EDP_CLKREF_EN>; 4077 clock-names = "aux", 4078 "cfg_ahb"; 4079 4080 #clock-cells = <1>; 4081 #phy-cells = <0>; 4082 4083 status = "disabled"; 4084 }; 4085 4086 mdss_dp: displayport-controller@ae90000 { 4087 compatible = "qcom,sc7280-dp"; 4088 4089 reg = <0 0xae90000 0 0x200>, 4090 <0 0xae90200 0 0x200>, 4091 <0 0xae90400 0 0xc00>, 4092 <0 0xae91000 0 0x400>, 4093 <0 0xae91400 0 0x400>; 4094 4095 interrupt-parent = <&mdss>; 4096 interrupts = <12>; 4097 4098 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4099 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4100 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4101 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4102 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4103 clock-names = "core_iface", 4104 "core_aux", 4105 "ctrl_link", 4106 "ctrl_link_iface", 4107 "stream_pixel"; 4108 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4109 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4110 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4111 phys = <&dp_phy>; 4112 phy-names = "dp"; 4113 4114 operating-points-v2 = <&dp_opp_table>; 4115 power-domains = <&rpmhpd SC7280_CX>; 4116 4117 #sound-dai-cells = <0>; 4118 4119 status = "disabled"; 4120 4121 ports { 4122 #address-cells = <1>; 4123 #size-cells = <0>; 4124 4125 port@0 { 4126 reg = <0>; 4127 dp_in: endpoint { 4128 remote-endpoint = <&dpu_intf0_out>; 4129 }; 4130 }; 4131 4132 port@1 { 4133 reg = <1>; 4134 dp_out: endpoint { }; 4135 }; 4136 }; 4137 4138 dp_opp_table: opp-table { 4139 compatible = "operating-points-v2"; 4140 4141 opp-160000000 { 4142 opp-hz = /bits/ 64 <160000000>; 4143 required-opps = <&rpmhpd_opp_low_svs>; 4144 }; 4145 4146 opp-270000000 { 4147 opp-hz = /bits/ 64 <270000000>; 4148 required-opps = <&rpmhpd_opp_svs>; 4149 }; 4150 4151 opp-540000000 { 4152 opp-hz = /bits/ 64 <540000000>; 4153 required-opps = <&rpmhpd_opp_svs_l1>; 4154 }; 4155 4156 opp-810000000 { 4157 opp-hz = /bits/ 64 <810000000>; 4158 required-opps = <&rpmhpd_opp_nom>; 4159 }; 4160 }; 4161 }; 4162 }; 4163 4164 pdc: interrupt-controller@b220000 { 4165 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4166 reg = <0 0x0b220000 0 0x30000>; 4167 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4168 <55 306 4>, <59 312 3>, <62 374 2>, 4169 <64 434 2>, <66 438 3>, <69 86 1>, 4170 <70 520 54>, <124 609 31>, <155 63 1>, 4171 <156 716 12>; 4172 #interrupt-cells = <2>; 4173 interrupt-parent = <&intc>; 4174 interrupt-controller; 4175 }; 4176 4177 pdc_reset: reset-controller@b5e0000 { 4178 compatible = "qcom,sc7280-pdc-global"; 4179 reg = <0 0x0b5e0000 0 0x20000>; 4180 #reset-cells = <1>; 4181 }; 4182 4183 tsens0: thermal-sensor@c263000 { 4184 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4185 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4186 <0 0x0c222000 0 0x1ff>; /* SROT */ 4187 #qcom,sensors = <15>; 4188 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4190 interrupt-names = "uplow","critical"; 4191 #thermal-sensor-cells = <1>; 4192 }; 4193 4194 tsens1: thermal-sensor@c265000 { 4195 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4196 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4197 <0 0x0c223000 0 0x1ff>; /* SROT */ 4198 #qcom,sensors = <12>; 4199 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4201 interrupt-names = "uplow","critical"; 4202 #thermal-sensor-cells = <1>; 4203 }; 4204 4205 aoss_reset: reset-controller@c2a0000 { 4206 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4207 reg = <0 0x0c2a0000 0 0x31000>; 4208 #reset-cells = <1>; 4209 }; 4210 4211 aoss_qmp: power-controller@c300000 { 4212 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4213 reg = <0 0x0c300000 0 0x400>; 4214 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4215 IPCC_MPROC_SIGNAL_GLINK_QMP 4216 IRQ_TYPE_EDGE_RISING>; 4217 mboxes = <&ipcc IPCC_CLIENT_AOP 4218 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4219 4220 #clock-cells = <0>; 4221 }; 4222 4223 sram@c3f0000 { 4224 compatible = "qcom,rpmh-stats"; 4225 reg = <0 0x0c3f0000 0 0x400>; 4226 }; 4227 4228 spmi_bus: spmi@c440000 { 4229 compatible = "qcom,spmi-pmic-arb"; 4230 reg = <0 0x0c440000 0 0x1100>, 4231 <0 0x0c600000 0 0x2000000>, 4232 <0 0x0e600000 0 0x100000>, 4233 <0 0x0e700000 0 0xa0000>, 4234 <0 0x0c40a000 0 0x26000>; 4235 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4236 interrupt-names = "periph_irq"; 4237 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4238 qcom,ee = <0>; 4239 qcom,channel = <0>; 4240 #address-cells = <1>; 4241 #size-cells = <1>; 4242 interrupt-controller; 4243 #interrupt-cells = <4>; 4244 }; 4245 4246 tlmm: pinctrl@f100000 { 4247 compatible = "qcom,sc7280-pinctrl"; 4248 reg = <0 0x0f100000 0 0x300000>; 4249 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4250 gpio-controller; 4251 #gpio-cells = <2>; 4252 interrupt-controller; 4253 #interrupt-cells = <2>; 4254 gpio-ranges = <&tlmm 0 0 175>; 4255 wakeup-parent = <&pdc>; 4256 4257 dp_hot_plug_det: dp-hot-plug-det-pins { 4258 pins = "gpio47"; 4259 function = "dp_hot"; 4260 }; 4261 4262 edp_hot_plug_det: edp-hot-plug-det-pins { 4263 pins = "gpio60"; 4264 function = "edp_hot"; 4265 }; 4266 4267 mi2s0_data0: mi2s0-data0-pins { 4268 pins = "gpio98"; 4269 function = "mi2s0_data0"; 4270 }; 4271 4272 mi2s0_data1: mi2s0-data1-pins { 4273 pins = "gpio99"; 4274 function = "mi2s0_data1"; 4275 }; 4276 4277 mi2s0_mclk: mi2s0-mclk-pins { 4278 pins = "gpio96"; 4279 function = "pri_mi2s"; 4280 }; 4281 4282 mi2s0_sclk: mi2s0-sclk-pins { 4283 pins = "gpio97"; 4284 function = "mi2s0_sck"; 4285 }; 4286 4287 mi2s0_ws: mi2s0-ws-pins { 4288 pins = "gpio100"; 4289 function = "mi2s0_ws"; 4290 }; 4291 4292 mi2s1_data0: mi2s1-data0-pins { 4293 pins = "gpio107"; 4294 function = "mi2s1_data0"; 4295 }; 4296 4297 mi2s1_sclk: mi2s1-sclk-pins { 4298 pins = "gpio106"; 4299 function = "mi2s1_sck"; 4300 }; 4301 4302 mi2s1_ws: mi2s1-ws-pins { 4303 pins = "gpio108"; 4304 function = "mi2s1_ws"; 4305 }; 4306 4307 pcie1_clkreq_n: pcie1-clkreq-n-pins { 4308 pins = "gpio79"; 4309 function = "pcie1_clkreqn"; 4310 }; 4311 4312 qspi_clk: qspi-clk-pins { 4313 pins = "gpio14"; 4314 function = "qspi_clk"; 4315 }; 4316 4317 qspi_cs0: qspi-cs0-pins { 4318 pins = "gpio15"; 4319 function = "qspi_cs"; 4320 }; 4321 4322 qspi_cs1: qspi-cs1-pins { 4323 pins = "gpio19"; 4324 function = "qspi_cs"; 4325 }; 4326 4327 qspi_data01: qspi-data01-pins { 4328 pins = "gpio12", "gpio13"; 4329 function = "qspi_data"; 4330 }; 4331 4332 qspi_data12: qspi-data12-pins { 4333 pins = "gpio16", "gpio17"; 4334 function = "qspi_data"; 4335 }; 4336 4337 qup_i2c0_data_clk: qup-i2c0-data-clk-pins { 4338 pins = "gpio0", "gpio1"; 4339 function = "qup00"; 4340 }; 4341 4342 qup_i2c1_data_clk: qup-i2c1-data-clk-pins { 4343 pins = "gpio4", "gpio5"; 4344 function = "qup01"; 4345 }; 4346 4347 qup_i2c2_data_clk: qup-i2c2-data-clk-pins { 4348 pins = "gpio8", "gpio9"; 4349 function = "qup02"; 4350 }; 4351 4352 qup_i2c3_data_clk: qup-i2c3-data-clk-pins { 4353 pins = "gpio12", "gpio13"; 4354 function = "qup03"; 4355 }; 4356 4357 qup_i2c4_data_clk: qup-i2c4-data-clk-pins { 4358 pins = "gpio16", "gpio17"; 4359 function = "qup04"; 4360 }; 4361 4362 qup_i2c5_data_clk: qup-i2c5-data-clk-pins { 4363 pins = "gpio20", "gpio21"; 4364 function = "qup05"; 4365 }; 4366 4367 qup_i2c6_data_clk: qup-i2c6-data-clk-pins { 4368 pins = "gpio24", "gpio25"; 4369 function = "qup06"; 4370 }; 4371 4372 qup_i2c7_data_clk: qup-i2c7-data-clk-pins { 4373 pins = "gpio28", "gpio29"; 4374 function = "qup07"; 4375 }; 4376 4377 qup_i2c8_data_clk: qup-i2c8-data-clk-pins { 4378 pins = "gpio32", "gpio33"; 4379 function = "qup10"; 4380 }; 4381 4382 qup_i2c9_data_clk: qup-i2c9-data-clk-pins { 4383 pins = "gpio36", "gpio37"; 4384 function = "qup11"; 4385 }; 4386 4387 qup_i2c10_data_clk: qup-i2c10-data-clk-pins { 4388 pins = "gpio40", "gpio41"; 4389 function = "qup12"; 4390 }; 4391 4392 qup_i2c11_data_clk: qup-i2c11-data-clk-pins { 4393 pins = "gpio44", "gpio45"; 4394 function = "qup13"; 4395 }; 4396 4397 qup_i2c12_data_clk: qup-i2c12-data-clk-pins { 4398 pins = "gpio48", "gpio49"; 4399 function = "qup14"; 4400 }; 4401 4402 qup_i2c13_data_clk: qup-i2c13-data-clk-pins { 4403 pins = "gpio52", "gpio53"; 4404 function = "qup15"; 4405 }; 4406 4407 qup_i2c14_data_clk: qup-i2c14-data-clk-pins { 4408 pins = "gpio56", "gpio57"; 4409 function = "qup16"; 4410 }; 4411 4412 qup_i2c15_data_clk: qup-i2c15-data-clk-pins { 4413 pins = "gpio60", "gpio61"; 4414 function = "qup17"; 4415 }; 4416 4417 qup_spi0_data_clk: qup-spi0-data-clk-pins { 4418 pins = "gpio0", "gpio1", "gpio2"; 4419 function = "qup00"; 4420 }; 4421 4422 qup_spi0_cs: qup-spi0-cs-pins { 4423 pins = "gpio3"; 4424 function = "qup00"; 4425 }; 4426 4427 qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins { 4428 pins = "gpio3"; 4429 function = "gpio"; 4430 }; 4431 4432 qup_spi1_data_clk: qup-spi1-data-clk-pins { 4433 pins = "gpio4", "gpio5", "gpio6"; 4434 function = "qup01"; 4435 }; 4436 4437 qup_spi1_cs: qup-spi1-cs-pins { 4438 pins = "gpio7"; 4439 function = "qup01"; 4440 }; 4441 4442 qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins { 4443 pins = "gpio7"; 4444 function = "gpio"; 4445 }; 4446 4447 qup_spi2_data_clk: qup-spi2-data-clk-pins { 4448 pins = "gpio8", "gpio9", "gpio10"; 4449 function = "qup02"; 4450 }; 4451 4452 qup_spi2_cs: qup-spi2-cs-pins { 4453 pins = "gpio11"; 4454 function = "qup02"; 4455 }; 4456 4457 qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins { 4458 pins = "gpio11"; 4459 function = "gpio"; 4460 }; 4461 4462 qup_spi3_data_clk: qup-spi3-data-clk-pins { 4463 pins = "gpio12", "gpio13", "gpio14"; 4464 function = "qup03"; 4465 }; 4466 4467 qup_spi3_cs: qup-spi3-cs-pins { 4468 pins = "gpio15"; 4469 function = "qup03"; 4470 }; 4471 4472 qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins { 4473 pins = "gpio15"; 4474 function = "gpio"; 4475 }; 4476 4477 qup_spi4_data_clk: qup-spi4-data-clk-pins { 4478 pins = "gpio16", "gpio17", "gpio18"; 4479 function = "qup04"; 4480 }; 4481 4482 qup_spi4_cs: qup-spi4-cs-pins { 4483 pins = "gpio19"; 4484 function = "qup04"; 4485 }; 4486 4487 qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins { 4488 pins = "gpio19"; 4489 function = "gpio"; 4490 }; 4491 4492 qup_spi5_data_clk: qup-spi5-data-clk-pins { 4493 pins = "gpio20", "gpio21", "gpio22"; 4494 function = "qup05"; 4495 }; 4496 4497 qup_spi5_cs: qup-spi5-cs-pins { 4498 pins = "gpio23"; 4499 function = "qup05"; 4500 }; 4501 4502 qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins { 4503 pins = "gpio23"; 4504 function = "gpio"; 4505 }; 4506 4507 qup_spi6_data_clk: qup-spi6-data-clk-pins { 4508 pins = "gpio24", "gpio25", "gpio26"; 4509 function = "qup06"; 4510 }; 4511 4512 qup_spi6_cs: qup-spi6-cs-pins { 4513 pins = "gpio27"; 4514 function = "qup06"; 4515 }; 4516 4517 qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins { 4518 pins = "gpio27"; 4519 function = "gpio"; 4520 }; 4521 4522 qup_spi7_data_clk: qup-spi7-data-clk-pins { 4523 pins = "gpio28", "gpio29", "gpio30"; 4524 function = "qup07"; 4525 }; 4526 4527 qup_spi7_cs: qup-spi7-cs-pins { 4528 pins = "gpio31"; 4529 function = "qup07"; 4530 }; 4531 4532 qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins { 4533 pins = "gpio31"; 4534 function = "gpio"; 4535 }; 4536 4537 qup_spi8_data_clk: qup-spi8-data-clk-pins { 4538 pins = "gpio32", "gpio33", "gpio34"; 4539 function = "qup10"; 4540 }; 4541 4542 qup_spi8_cs: qup-spi8-cs-pins { 4543 pins = "gpio35"; 4544 function = "qup10"; 4545 }; 4546 4547 qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins { 4548 pins = "gpio35"; 4549 function = "gpio"; 4550 }; 4551 4552 qup_spi9_data_clk: qup-spi9-data-clk-pins { 4553 pins = "gpio36", "gpio37", "gpio38"; 4554 function = "qup11"; 4555 }; 4556 4557 qup_spi9_cs: qup-spi9-cs-pins { 4558 pins = "gpio39"; 4559 function = "qup11"; 4560 }; 4561 4562 qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins { 4563 pins = "gpio39"; 4564 function = "gpio"; 4565 }; 4566 4567 qup_spi10_data_clk: qup-spi10-data-clk-pins { 4568 pins = "gpio40", "gpio41", "gpio42"; 4569 function = "qup12"; 4570 }; 4571 4572 qup_spi10_cs: qup-spi10-cs-pins { 4573 pins = "gpio43"; 4574 function = "qup12"; 4575 }; 4576 4577 qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins { 4578 pins = "gpio43"; 4579 function = "gpio"; 4580 }; 4581 4582 qup_spi11_data_clk: qup-spi11-data-clk-pins { 4583 pins = "gpio44", "gpio45", "gpio46"; 4584 function = "qup13"; 4585 }; 4586 4587 qup_spi11_cs: qup-spi11-cs-pins { 4588 pins = "gpio47"; 4589 function = "qup13"; 4590 }; 4591 4592 qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins { 4593 pins = "gpio47"; 4594 function = "gpio"; 4595 }; 4596 4597 qup_spi12_data_clk: qup-spi12-data-clk-pins { 4598 pins = "gpio48", "gpio49", "gpio50"; 4599 function = "qup14"; 4600 }; 4601 4602 qup_spi12_cs: qup-spi12-cs-pins { 4603 pins = "gpio51"; 4604 function = "qup14"; 4605 }; 4606 4607 qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins { 4608 pins = "gpio51"; 4609 function = "gpio"; 4610 }; 4611 4612 qup_spi13_data_clk: qup-spi13-data-clk-pins { 4613 pins = "gpio52", "gpio53", "gpio54"; 4614 function = "qup15"; 4615 }; 4616 4617 qup_spi13_cs: qup-spi13-cs-pins { 4618 pins = "gpio55"; 4619 function = "qup15"; 4620 }; 4621 4622 qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins { 4623 pins = "gpio55"; 4624 function = "gpio"; 4625 }; 4626 4627 qup_spi14_data_clk: qup-spi14-data-clk-pins { 4628 pins = "gpio56", "gpio57", "gpio58"; 4629 function = "qup16"; 4630 }; 4631 4632 qup_spi14_cs: qup-spi14-cs-pins { 4633 pins = "gpio59"; 4634 function = "qup16"; 4635 }; 4636 4637 qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins { 4638 pins = "gpio59"; 4639 function = "gpio"; 4640 }; 4641 4642 qup_spi15_data_clk: qup-spi15-data-clk-pins { 4643 pins = "gpio60", "gpio61", "gpio62"; 4644 function = "qup17"; 4645 }; 4646 4647 qup_spi15_cs: qup-spi15-cs-pins { 4648 pins = "gpio63"; 4649 function = "qup17"; 4650 }; 4651 4652 qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins { 4653 pins = "gpio63"; 4654 function = "gpio"; 4655 }; 4656 4657 qup_uart0_cts: qup-uart0-cts-pins { 4658 pins = "gpio0"; 4659 function = "qup00"; 4660 }; 4661 4662 qup_uart0_rts: qup-uart0-rts-pins { 4663 pins = "gpio1"; 4664 function = "qup00"; 4665 }; 4666 4667 qup_uart0_tx: qup-uart0-tx-pins { 4668 pins = "gpio2"; 4669 function = "qup00"; 4670 }; 4671 4672 qup_uart0_rx: qup-uart0-rx-pins { 4673 pins = "gpio3"; 4674 function = "qup00"; 4675 }; 4676 4677 qup_uart1_cts: qup-uart1-cts-pins { 4678 pins = "gpio4"; 4679 function = "qup01"; 4680 }; 4681 4682 qup_uart1_rts: qup-uart1-rts-pins { 4683 pins = "gpio5"; 4684 function = "qup01"; 4685 }; 4686 4687 qup_uart1_tx: qup-uart1-tx-pins { 4688 pins = "gpio6"; 4689 function = "qup01"; 4690 }; 4691 4692 qup_uart1_rx: qup-uart1-rx-pins { 4693 pins = "gpio7"; 4694 function = "qup01"; 4695 }; 4696 4697 qup_uart2_cts: qup-uart2-cts-pins { 4698 pins = "gpio8"; 4699 function = "qup02"; 4700 }; 4701 4702 qup_uart2_rts: qup-uart2-rts-pins { 4703 pins = "gpio9"; 4704 function = "qup02"; 4705 }; 4706 4707 qup_uart2_tx: qup-uart2-tx-pins { 4708 pins = "gpio10"; 4709 function = "qup02"; 4710 }; 4711 4712 qup_uart2_rx: qup-uart2-rx-pins { 4713 pins = "gpio11"; 4714 function = "qup02"; 4715 }; 4716 4717 qup_uart3_cts: qup-uart3-cts-pins { 4718 pins = "gpio12"; 4719 function = "qup03"; 4720 }; 4721 4722 qup_uart3_rts: qup-uart3-rts-pins { 4723 pins = "gpio13"; 4724 function = "qup03"; 4725 }; 4726 4727 qup_uart3_tx: qup-uart3-tx-pins { 4728 pins = "gpio14"; 4729 function = "qup03"; 4730 }; 4731 4732 qup_uart3_rx: qup-uart3-rx-pins { 4733 pins = "gpio15"; 4734 function = "qup03"; 4735 }; 4736 4737 qup_uart4_cts: qup-uart4-cts-pins { 4738 pins = "gpio16"; 4739 function = "qup04"; 4740 }; 4741 4742 qup_uart4_rts: qup-uart4-rts-pins { 4743 pins = "gpio17"; 4744 function = "qup04"; 4745 }; 4746 4747 qup_uart4_tx: qup-uart4-tx-pins { 4748 pins = "gpio18"; 4749 function = "qup04"; 4750 }; 4751 4752 qup_uart4_rx: qup-uart4-rx-pins { 4753 pins = "gpio19"; 4754 function = "qup04"; 4755 }; 4756 4757 qup_uart5_cts: qup-uart5-cts-pins { 4758 pins = "gpio20"; 4759 function = "qup05"; 4760 }; 4761 4762 qup_uart5_rts: qup-uart5-rts-pins { 4763 pins = "gpio21"; 4764 function = "qup05"; 4765 }; 4766 4767 qup_uart5_tx: qup-uart5-tx-pins { 4768 pins = "gpio22"; 4769 function = "qup05"; 4770 }; 4771 4772 qup_uart5_rx: qup-uart5-rx-pins { 4773 pins = "gpio23"; 4774 function = "qup05"; 4775 }; 4776 4777 qup_uart6_cts: qup-uart6-cts-pins { 4778 pins = "gpio24"; 4779 function = "qup06"; 4780 }; 4781 4782 qup_uart6_rts: qup-uart6-rts-pins { 4783 pins = "gpio25"; 4784 function = "qup06"; 4785 }; 4786 4787 qup_uart6_tx: qup-uart6-tx-pins { 4788 pins = "gpio26"; 4789 function = "qup06"; 4790 }; 4791 4792 qup_uart6_rx: qup-uart6-rx-pins { 4793 pins = "gpio27"; 4794 function = "qup06"; 4795 }; 4796 4797 qup_uart7_cts: qup-uart7-cts-pins { 4798 pins = "gpio28"; 4799 function = "qup07"; 4800 }; 4801 4802 qup_uart7_rts: qup-uart7-rts-pins { 4803 pins = "gpio29"; 4804 function = "qup07"; 4805 }; 4806 4807 qup_uart7_tx: qup-uart7-tx-pins { 4808 pins = "gpio30"; 4809 function = "qup07"; 4810 }; 4811 4812 qup_uart7_rx: qup-uart7-rx-pins { 4813 pins = "gpio31"; 4814 function = "qup07"; 4815 }; 4816 4817 qup_uart8_cts: qup-uart8-cts-pins { 4818 pins = "gpio32"; 4819 function = "qup10"; 4820 }; 4821 4822 qup_uart8_rts: qup-uart8-rts-pins { 4823 pins = "gpio33"; 4824 function = "qup10"; 4825 }; 4826 4827 qup_uart8_tx: qup-uart8-tx-pins { 4828 pins = "gpio34"; 4829 function = "qup10"; 4830 }; 4831 4832 qup_uart8_rx: qup-uart8-rx-pins { 4833 pins = "gpio35"; 4834 function = "qup10"; 4835 }; 4836 4837 qup_uart9_cts: qup-uart9-cts-pins { 4838 pins = "gpio36"; 4839 function = "qup11"; 4840 }; 4841 4842 qup_uart9_rts: qup-uart9-rts-pins { 4843 pins = "gpio37"; 4844 function = "qup11"; 4845 }; 4846 4847 qup_uart9_tx: qup-uart9-tx-pins { 4848 pins = "gpio38"; 4849 function = "qup11"; 4850 }; 4851 4852 qup_uart9_rx: qup-uart9-rx-pins { 4853 pins = "gpio39"; 4854 function = "qup11"; 4855 }; 4856 4857 qup_uart10_cts: qup-uart10-cts-pins { 4858 pins = "gpio40"; 4859 function = "qup12"; 4860 }; 4861 4862 qup_uart10_rts: qup-uart10-rts-pins { 4863 pins = "gpio41"; 4864 function = "qup12"; 4865 }; 4866 4867 qup_uart10_tx: qup-uart10-tx-pins { 4868 pins = "gpio42"; 4869 function = "qup12"; 4870 }; 4871 4872 qup_uart10_rx: qup-uart10-rx-pins { 4873 pins = "gpio43"; 4874 function = "qup12"; 4875 }; 4876 4877 qup_uart11_cts: qup-uart11-cts-pins { 4878 pins = "gpio44"; 4879 function = "qup13"; 4880 }; 4881 4882 qup_uart11_rts: qup-uart11-rts-pins { 4883 pins = "gpio45"; 4884 function = "qup13"; 4885 }; 4886 4887 qup_uart11_tx: qup-uart11-tx-pins { 4888 pins = "gpio46"; 4889 function = "qup13"; 4890 }; 4891 4892 qup_uart11_rx: qup-uart11-rx-pins { 4893 pins = "gpio47"; 4894 function = "qup13"; 4895 }; 4896 4897 qup_uart12_cts: qup-uart12-cts-pins { 4898 pins = "gpio48"; 4899 function = "qup14"; 4900 }; 4901 4902 qup_uart12_rts: qup-uart12-rts-pins { 4903 pins = "gpio49"; 4904 function = "qup14"; 4905 }; 4906 4907 qup_uart12_tx: qup-uart12-tx-pins { 4908 pins = "gpio50"; 4909 function = "qup14"; 4910 }; 4911 4912 qup_uart12_rx: qup-uart12-rx-pins { 4913 pins = "gpio51"; 4914 function = "qup14"; 4915 }; 4916 4917 qup_uart13_cts: qup-uart13-cts-pins { 4918 pins = "gpio52"; 4919 function = "qup15"; 4920 }; 4921 4922 qup_uart13_rts: qup-uart13-rts-pins { 4923 pins = "gpio53"; 4924 function = "qup15"; 4925 }; 4926 4927 qup_uart13_tx: qup-uart13-tx-pins { 4928 pins = "gpio54"; 4929 function = "qup15"; 4930 }; 4931 4932 qup_uart13_rx: qup-uart13-rx-pins { 4933 pins = "gpio55"; 4934 function = "qup15"; 4935 }; 4936 4937 qup_uart14_cts: qup-uart14-cts-pins { 4938 pins = "gpio56"; 4939 function = "qup16"; 4940 }; 4941 4942 qup_uart14_rts: qup-uart14-rts-pins { 4943 pins = "gpio57"; 4944 function = "qup16"; 4945 }; 4946 4947 qup_uart14_tx: qup-uart14-tx-pins { 4948 pins = "gpio58"; 4949 function = "qup16"; 4950 }; 4951 4952 qup_uart14_rx: qup-uart14-rx-pins { 4953 pins = "gpio59"; 4954 function = "qup16"; 4955 }; 4956 4957 qup_uart15_cts: qup-uart15-cts-pins { 4958 pins = "gpio60"; 4959 function = "qup17"; 4960 }; 4961 4962 qup_uart15_rts: qup-uart15-rts-pins { 4963 pins = "gpio61"; 4964 function = "qup17"; 4965 }; 4966 4967 qup_uart15_tx: qup-uart15-tx-pins { 4968 pins = "gpio62"; 4969 function = "qup17"; 4970 }; 4971 4972 qup_uart15_rx: qup-uart15-rx-pins { 4973 pins = "gpio63"; 4974 function = "qup17"; 4975 }; 4976 4977 sdc1_clk: sdc1-clk-pins { 4978 pins = "sdc1_clk"; 4979 }; 4980 4981 sdc1_cmd: sdc1-cmd-pins { 4982 pins = "sdc1_cmd"; 4983 }; 4984 4985 sdc1_data: sdc1-data-pins { 4986 pins = "sdc1_data"; 4987 }; 4988 4989 sdc1_rclk: sdc1-rclk-pins { 4990 pins = "sdc1_rclk"; 4991 }; 4992 4993 sdc1_clk_sleep: sdc1-clk-sleep-pins { 4994 pins = "sdc1_clk"; 4995 drive-strength = <2>; 4996 bias-bus-hold; 4997 }; 4998 4999 sdc1_cmd_sleep: sdc1-cmd-sleep-pins { 5000 pins = "sdc1_cmd"; 5001 drive-strength = <2>; 5002 bias-bus-hold; 5003 }; 5004 5005 sdc1_data_sleep: sdc1-data-sleep-pins { 5006 pins = "sdc1_data"; 5007 drive-strength = <2>; 5008 bias-bus-hold; 5009 }; 5010 5011 sdc1_rclk_sleep: sdc1-rclk-sleep-pins { 5012 pins = "sdc1_rclk"; 5013 drive-strength = <2>; 5014 bias-bus-hold; 5015 }; 5016 5017 sdc2_clk: sdc2-clk-pins { 5018 pins = "sdc2_clk"; 5019 }; 5020 5021 sdc2_cmd: sdc2-cmd-pins { 5022 pins = "sdc2_cmd"; 5023 }; 5024 5025 sdc2_data: sdc2-data-pins { 5026 pins = "sdc2_data"; 5027 }; 5028 5029 sdc2_clk_sleep: sdc2-clk-sleep-pins { 5030 pins = "sdc2_clk"; 5031 drive-strength = <2>; 5032 bias-bus-hold; 5033 }; 5034 5035 sdc2_cmd_sleep: sdc2-cmd-sleep-pins { 5036 pins = "sdc2_cmd"; 5037 drive-strength = <2>; 5038 bias-bus-hold; 5039 }; 5040 5041 sdc2_data_sleep: sdc2-data-sleep-pins { 5042 pins = "sdc2_data"; 5043 drive-strength = <2>; 5044 bias-bus-hold; 5045 }; 5046 }; 5047 5048 sram@146a5000 { 5049 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5050 reg = <0 0x146a5000 0 0x6000>; 5051 5052 #address-cells = <1>; 5053 #size-cells = <1>; 5054 5055 ranges = <0 0 0x146a5000 0x6000>; 5056 5057 pil-reloc@594c { 5058 compatible = "qcom,pil-reloc-info"; 5059 reg = <0x594c 0xc8>; 5060 }; 5061 }; 5062 5063 apps_smmu: iommu@15000000 { 5064 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5065 reg = <0 0x15000000 0 0x100000>; 5066 #iommu-cells = <2>; 5067 #global-interrupts = <1>; 5068 dma-coherent; 5069 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5150 }; 5151 5152 intc: interrupt-controller@17a00000 { 5153 compatible = "arm,gic-v3"; 5154 #address-cells = <2>; 5155 #size-cells = <2>; 5156 ranges; 5157 #interrupt-cells = <3>; 5158 interrupt-controller; 5159 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5160 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5161 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5162 5163 gic-its@17a40000 { 5164 compatible = "arm,gic-v3-its"; 5165 msi-controller; 5166 #msi-cells = <1>; 5167 reg = <0 0x17a40000 0 0x20000>; 5168 status = "disabled"; 5169 }; 5170 }; 5171 5172 watchdog@17c10000 { 5173 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5174 reg = <0 0x17c10000 0 0x1000>; 5175 clocks = <&sleep_clk>; 5176 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5177 }; 5178 5179 timer@17c20000 { 5180 #address-cells = <1>; 5181 #size-cells = <1>; 5182 ranges = <0 0 0 0x20000000>; 5183 compatible = "arm,armv7-timer-mem"; 5184 reg = <0 0x17c20000 0 0x1000>; 5185 5186 frame@17c21000 { 5187 frame-number = <0>; 5188 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5190 reg = <0x17c21000 0x1000>, 5191 <0x17c22000 0x1000>; 5192 }; 5193 5194 frame@17c23000 { 5195 frame-number = <1>; 5196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5197 reg = <0x17c23000 0x1000>; 5198 status = "disabled"; 5199 }; 5200 5201 frame@17c25000 { 5202 frame-number = <2>; 5203 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5204 reg = <0x17c25000 0x1000>; 5205 status = "disabled"; 5206 }; 5207 5208 frame@17c27000 { 5209 frame-number = <3>; 5210 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5211 reg = <0x17c27000 0x1000>; 5212 status = "disabled"; 5213 }; 5214 5215 frame@17c29000 { 5216 frame-number = <4>; 5217 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5218 reg = <0x17c29000 0x1000>; 5219 status = "disabled"; 5220 }; 5221 5222 frame@17c2b000 { 5223 frame-number = <5>; 5224 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5225 reg = <0x17c2b000 0x1000>; 5226 status = "disabled"; 5227 }; 5228 5229 frame@17c2d000 { 5230 frame-number = <6>; 5231 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5232 reg = <0x17c2d000 0x1000>; 5233 status = "disabled"; 5234 }; 5235 }; 5236 5237 apps_rsc: rsc@18200000 { 5238 compatible = "qcom,rpmh-rsc"; 5239 reg = <0 0x18200000 0 0x10000>, 5240 <0 0x18210000 0 0x10000>, 5241 <0 0x18220000 0 0x10000>; 5242 reg-names = "drv-0", "drv-1", "drv-2"; 5243 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5244 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5245 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5246 qcom,tcs-offset = <0xd00>; 5247 qcom,drv-id = <2>; 5248 qcom,tcs-config = <ACTIVE_TCS 2>, 5249 <SLEEP_TCS 3>, 5250 <WAKE_TCS 3>, 5251 <CONTROL_TCS 1>; 5252 5253 apps_bcm_voter: bcm-voter { 5254 compatible = "qcom,bcm-voter"; 5255 }; 5256 5257 rpmhpd: power-controller { 5258 compatible = "qcom,sc7280-rpmhpd"; 5259 #power-domain-cells = <1>; 5260 operating-points-v2 = <&rpmhpd_opp_table>; 5261 5262 rpmhpd_opp_table: opp-table { 5263 compatible = "operating-points-v2"; 5264 5265 rpmhpd_opp_ret: opp1 { 5266 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5267 }; 5268 5269 rpmhpd_opp_low_svs: opp2 { 5270 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5271 }; 5272 5273 rpmhpd_opp_svs: opp3 { 5274 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5275 }; 5276 5277 rpmhpd_opp_svs_l1: opp4 { 5278 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5279 }; 5280 5281 rpmhpd_opp_svs_l2: opp5 { 5282 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5283 }; 5284 5285 rpmhpd_opp_nom: opp6 { 5286 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5287 }; 5288 5289 rpmhpd_opp_nom_l1: opp7 { 5290 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5291 }; 5292 5293 rpmhpd_opp_turbo: opp8 { 5294 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5295 }; 5296 5297 rpmhpd_opp_turbo_l1: opp9 { 5298 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5299 }; 5300 }; 5301 }; 5302 5303 rpmhcc: clock-controller { 5304 compatible = "qcom,sc7280-rpmh-clk"; 5305 clocks = <&xo_board>; 5306 clock-names = "xo"; 5307 #clock-cells = <1>; 5308 }; 5309 }; 5310 5311 epss_l3: interconnect@18590000 { 5312 compatible = "qcom,sc7280-epss-l3"; 5313 reg = <0 0x18590000 0 0x1000>; 5314 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5315 clock-names = "xo", "alternate"; 5316 #interconnect-cells = <1>; 5317 }; 5318 5319 cpufreq_hw: cpufreq@18591000 { 5320 compatible = "qcom,cpufreq-epss"; 5321 reg = <0 0x18591000 0 0x1000>, 5322 <0 0x18592000 0 0x1000>, 5323 <0 0x18593000 0 0x1000>; 5324 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5325 clock-names = "xo", "alternate"; 5326 #freq-domain-cells = <1>; 5327 }; 5328 }; 5329 5330 thermal_zones: thermal-zones { 5331 cpu0-thermal { 5332 polling-delay-passive = <250>; 5333 polling-delay = <0>; 5334 5335 thermal-sensors = <&tsens0 1>; 5336 5337 trips { 5338 cpu0_alert0: trip-point0 { 5339 temperature = <90000>; 5340 hysteresis = <2000>; 5341 type = "passive"; 5342 }; 5343 5344 cpu0_alert1: trip-point1 { 5345 temperature = <95000>; 5346 hysteresis = <2000>; 5347 type = "passive"; 5348 }; 5349 5350 cpu0_crit: cpu-crit { 5351 temperature = <110000>; 5352 hysteresis = <0>; 5353 type = "critical"; 5354 }; 5355 }; 5356 5357 cooling-maps { 5358 map0 { 5359 trip = <&cpu0_alert0>; 5360 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5361 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5362 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5363 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5364 }; 5365 map1 { 5366 trip = <&cpu0_alert1>; 5367 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5368 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5369 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5370 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5371 }; 5372 }; 5373 }; 5374 5375 cpu1-thermal { 5376 polling-delay-passive = <250>; 5377 polling-delay = <0>; 5378 5379 thermal-sensors = <&tsens0 2>; 5380 5381 trips { 5382 cpu1_alert0: trip-point0 { 5383 temperature = <90000>; 5384 hysteresis = <2000>; 5385 type = "passive"; 5386 }; 5387 5388 cpu1_alert1: trip-point1 { 5389 temperature = <95000>; 5390 hysteresis = <2000>; 5391 type = "passive"; 5392 }; 5393 5394 cpu1_crit: cpu-crit { 5395 temperature = <110000>; 5396 hysteresis = <0>; 5397 type = "critical"; 5398 }; 5399 }; 5400 5401 cooling-maps { 5402 map0 { 5403 trip = <&cpu1_alert0>; 5404 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5405 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5406 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5407 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5408 }; 5409 map1 { 5410 trip = <&cpu1_alert1>; 5411 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5412 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5413 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5414 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5415 }; 5416 }; 5417 }; 5418 5419 cpu2-thermal { 5420 polling-delay-passive = <250>; 5421 polling-delay = <0>; 5422 5423 thermal-sensors = <&tsens0 3>; 5424 5425 trips { 5426 cpu2_alert0: trip-point0 { 5427 temperature = <90000>; 5428 hysteresis = <2000>; 5429 type = "passive"; 5430 }; 5431 5432 cpu2_alert1: trip-point1 { 5433 temperature = <95000>; 5434 hysteresis = <2000>; 5435 type = "passive"; 5436 }; 5437 5438 cpu2_crit: cpu-crit { 5439 temperature = <110000>; 5440 hysteresis = <0>; 5441 type = "critical"; 5442 }; 5443 }; 5444 5445 cooling-maps { 5446 map0 { 5447 trip = <&cpu2_alert0>; 5448 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5449 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5450 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5451 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5452 }; 5453 map1 { 5454 trip = <&cpu2_alert1>; 5455 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5456 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5457 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5458 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5459 }; 5460 }; 5461 }; 5462 5463 cpu3-thermal { 5464 polling-delay-passive = <250>; 5465 polling-delay = <0>; 5466 5467 thermal-sensors = <&tsens0 4>; 5468 5469 trips { 5470 cpu3_alert0: trip-point0 { 5471 temperature = <90000>; 5472 hysteresis = <2000>; 5473 type = "passive"; 5474 }; 5475 5476 cpu3_alert1: trip-point1 { 5477 temperature = <95000>; 5478 hysteresis = <2000>; 5479 type = "passive"; 5480 }; 5481 5482 cpu3_crit: cpu-crit { 5483 temperature = <110000>; 5484 hysteresis = <0>; 5485 type = "critical"; 5486 }; 5487 }; 5488 5489 cooling-maps { 5490 map0 { 5491 trip = <&cpu3_alert0>; 5492 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5493 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5494 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5495 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5496 }; 5497 map1 { 5498 trip = <&cpu3_alert1>; 5499 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5500 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5501 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5502 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5503 }; 5504 }; 5505 }; 5506 5507 cpu4-thermal { 5508 polling-delay-passive = <250>; 5509 polling-delay = <0>; 5510 5511 thermal-sensors = <&tsens0 7>; 5512 5513 trips { 5514 cpu4_alert0: trip-point0 { 5515 temperature = <90000>; 5516 hysteresis = <2000>; 5517 type = "passive"; 5518 }; 5519 5520 cpu4_alert1: trip-point1 { 5521 temperature = <95000>; 5522 hysteresis = <2000>; 5523 type = "passive"; 5524 }; 5525 5526 cpu4_crit: cpu-crit { 5527 temperature = <110000>; 5528 hysteresis = <0>; 5529 type = "critical"; 5530 }; 5531 }; 5532 5533 cooling-maps { 5534 map0 { 5535 trip = <&cpu4_alert0>; 5536 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5537 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5538 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5539 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5540 }; 5541 map1 { 5542 trip = <&cpu4_alert1>; 5543 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5544 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5545 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5546 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5547 }; 5548 }; 5549 }; 5550 5551 cpu5-thermal { 5552 polling-delay-passive = <250>; 5553 polling-delay = <0>; 5554 5555 thermal-sensors = <&tsens0 8>; 5556 5557 trips { 5558 cpu5_alert0: trip-point0 { 5559 temperature = <90000>; 5560 hysteresis = <2000>; 5561 type = "passive"; 5562 }; 5563 5564 cpu5_alert1: trip-point1 { 5565 temperature = <95000>; 5566 hysteresis = <2000>; 5567 type = "passive"; 5568 }; 5569 5570 cpu5_crit: cpu-crit { 5571 temperature = <110000>; 5572 hysteresis = <0>; 5573 type = "critical"; 5574 }; 5575 }; 5576 5577 cooling-maps { 5578 map0 { 5579 trip = <&cpu5_alert0>; 5580 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5581 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5582 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5583 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5584 }; 5585 map1 { 5586 trip = <&cpu5_alert1>; 5587 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5588 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5589 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5590 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5591 }; 5592 }; 5593 }; 5594 5595 cpu6-thermal { 5596 polling-delay-passive = <250>; 5597 polling-delay = <0>; 5598 5599 thermal-sensors = <&tsens0 9>; 5600 5601 trips { 5602 cpu6_alert0: trip-point0 { 5603 temperature = <90000>; 5604 hysteresis = <2000>; 5605 type = "passive"; 5606 }; 5607 5608 cpu6_alert1: trip-point1 { 5609 temperature = <95000>; 5610 hysteresis = <2000>; 5611 type = "passive"; 5612 }; 5613 5614 cpu6_crit: cpu-crit { 5615 temperature = <110000>; 5616 hysteresis = <0>; 5617 type = "critical"; 5618 }; 5619 }; 5620 5621 cooling-maps { 5622 map0 { 5623 trip = <&cpu6_alert0>; 5624 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5625 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5626 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5627 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5628 }; 5629 map1 { 5630 trip = <&cpu6_alert1>; 5631 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5632 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5633 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5634 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5635 }; 5636 }; 5637 }; 5638 5639 cpu7-thermal { 5640 polling-delay-passive = <250>; 5641 polling-delay = <0>; 5642 5643 thermal-sensors = <&tsens0 10>; 5644 5645 trips { 5646 cpu7_alert0: trip-point0 { 5647 temperature = <90000>; 5648 hysteresis = <2000>; 5649 type = "passive"; 5650 }; 5651 5652 cpu7_alert1: trip-point1 { 5653 temperature = <95000>; 5654 hysteresis = <2000>; 5655 type = "passive"; 5656 }; 5657 5658 cpu7_crit: cpu-crit { 5659 temperature = <110000>; 5660 hysteresis = <0>; 5661 type = "critical"; 5662 }; 5663 }; 5664 5665 cooling-maps { 5666 map0 { 5667 trip = <&cpu7_alert0>; 5668 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5669 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5670 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5671 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5672 }; 5673 map1 { 5674 trip = <&cpu7_alert1>; 5675 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5676 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5677 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5678 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5679 }; 5680 }; 5681 }; 5682 5683 cpu8-thermal { 5684 polling-delay-passive = <250>; 5685 polling-delay = <0>; 5686 5687 thermal-sensors = <&tsens0 11>; 5688 5689 trips { 5690 cpu8_alert0: trip-point0 { 5691 temperature = <90000>; 5692 hysteresis = <2000>; 5693 type = "passive"; 5694 }; 5695 5696 cpu8_alert1: trip-point1 { 5697 temperature = <95000>; 5698 hysteresis = <2000>; 5699 type = "passive"; 5700 }; 5701 5702 cpu8_crit: cpu-crit { 5703 temperature = <110000>; 5704 hysteresis = <0>; 5705 type = "critical"; 5706 }; 5707 }; 5708 5709 cooling-maps { 5710 map0 { 5711 trip = <&cpu8_alert0>; 5712 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5713 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5714 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5715 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5716 }; 5717 map1 { 5718 trip = <&cpu8_alert1>; 5719 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5720 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5721 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5722 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5723 }; 5724 }; 5725 }; 5726 5727 cpu9-thermal { 5728 polling-delay-passive = <250>; 5729 polling-delay = <0>; 5730 5731 thermal-sensors = <&tsens0 12>; 5732 5733 trips { 5734 cpu9_alert0: trip-point0 { 5735 temperature = <90000>; 5736 hysteresis = <2000>; 5737 type = "passive"; 5738 }; 5739 5740 cpu9_alert1: trip-point1 { 5741 temperature = <95000>; 5742 hysteresis = <2000>; 5743 type = "passive"; 5744 }; 5745 5746 cpu9_crit: cpu-crit { 5747 temperature = <110000>; 5748 hysteresis = <0>; 5749 type = "critical"; 5750 }; 5751 }; 5752 5753 cooling-maps { 5754 map0 { 5755 trip = <&cpu9_alert0>; 5756 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5757 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5758 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5759 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5760 }; 5761 map1 { 5762 trip = <&cpu9_alert1>; 5763 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5764 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5765 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5766 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5767 }; 5768 }; 5769 }; 5770 5771 cpu10-thermal { 5772 polling-delay-passive = <250>; 5773 polling-delay = <0>; 5774 5775 thermal-sensors = <&tsens0 13>; 5776 5777 trips { 5778 cpu10_alert0: trip-point0 { 5779 temperature = <90000>; 5780 hysteresis = <2000>; 5781 type = "passive"; 5782 }; 5783 5784 cpu10_alert1: trip-point1 { 5785 temperature = <95000>; 5786 hysteresis = <2000>; 5787 type = "passive"; 5788 }; 5789 5790 cpu10_crit: cpu-crit { 5791 temperature = <110000>; 5792 hysteresis = <0>; 5793 type = "critical"; 5794 }; 5795 }; 5796 5797 cooling-maps { 5798 map0 { 5799 trip = <&cpu10_alert0>; 5800 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5801 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5802 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5803 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5804 }; 5805 map1 { 5806 trip = <&cpu10_alert1>; 5807 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5808 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5809 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5810 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5811 }; 5812 }; 5813 }; 5814 5815 cpu11-thermal { 5816 polling-delay-passive = <250>; 5817 polling-delay = <0>; 5818 5819 thermal-sensors = <&tsens0 14>; 5820 5821 trips { 5822 cpu11_alert0: trip-point0 { 5823 temperature = <90000>; 5824 hysteresis = <2000>; 5825 type = "passive"; 5826 }; 5827 5828 cpu11_alert1: trip-point1 { 5829 temperature = <95000>; 5830 hysteresis = <2000>; 5831 type = "passive"; 5832 }; 5833 5834 cpu11_crit: cpu-crit { 5835 temperature = <110000>; 5836 hysteresis = <0>; 5837 type = "critical"; 5838 }; 5839 }; 5840 5841 cooling-maps { 5842 map0 { 5843 trip = <&cpu11_alert0>; 5844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5846 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5847 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5848 }; 5849 map1 { 5850 trip = <&cpu11_alert1>; 5851 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5852 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5853 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5855 }; 5856 }; 5857 }; 5858 5859 aoss0-thermal { 5860 polling-delay-passive = <0>; 5861 polling-delay = <0>; 5862 5863 thermal-sensors = <&tsens0 0>; 5864 5865 trips { 5866 aoss0_alert0: trip-point0 { 5867 temperature = <90000>; 5868 hysteresis = <2000>; 5869 type = "hot"; 5870 }; 5871 5872 aoss0_crit: aoss0-crit { 5873 temperature = <110000>; 5874 hysteresis = <0>; 5875 type = "critical"; 5876 }; 5877 }; 5878 }; 5879 5880 aoss1-thermal { 5881 polling-delay-passive = <0>; 5882 polling-delay = <0>; 5883 5884 thermal-sensors = <&tsens1 0>; 5885 5886 trips { 5887 aoss1_alert0: trip-point0 { 5888 temperature = <90000>; 5889 hysteresis = <2000>; 5890 type = "hot"; 5891 }; 5892 5893 aoss1_crit: aoss1-crit { 5894 temperature = <110000>; 5895 hysteresis = <0>; 5896 type = "critical"; 5897 }; 5898 }; 5899 }; 5900 5901 cpuss0-thermal { 5902 polling-delay-passive = <0>; 5903 polling-delay = <0>; 5904 5905 thermal-sensors = <&tsens0 5>; 5906 5907 trips { 5908 cpuss0_alert0: trip-point0 { 5909 temperature = <90000>; 5910 hysteresis = <2000>; 5911 type = "hot"; 5912 }; 5913 cpuss0_crit: cluster0-crit { 5914 temperature = <110000>; 5915 hysteresis = <0>; 5916 type = "critical"; 5917 }; 5918 }; 5919 }; 5920 5921 cpuss1-thermal { 5922 polling-delay-passive = <0>; 5923 polling-delay = <0>; 5924 5925 thermal-sensors = <&tsens0 6>; 5926 5927 trips { 5928 cpuss1_alert0: trip-point0 { 5929 temperature = <90000>; 5930 hysteresis = <2000>; 5931 type = "hot"; 5932 }; 5933 cpuss1_crit: cluster0-crit { 5934 temperature = <110000>; 5935 hysteresis = <0>; 5936 type = "critical"; 5937 }; 5938 }; 5939 }; 5940 5941 gpuss0-thermal { 5942 polling-delay-passive = <100>; 5943 polling-delay = <0>; 5944 5945 thermal-sensors = <&tsens1 1>; 5946 5947 trips { 5948 gpuss0_alert0: trip-point0 { 5949 temperature = <95000>; 5950 hysteresis = <2000>; 5951 type = "passive"; 5952 }; 5953 5954 gpuss0_crit: gpuss0-crit { 5955 temperature = <110000>; 5956 hysteresis = <0>; 5957 type = "critical"; 5958 }; 5959 }; 5960 5961 cooling-maps { 5962 map0 { 5963 trip = <&gpuss0_alert0>; 5964 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5965 }; 5966 }; 5967 }; 5968 5969 gpuss1-thermal { 5970 polling-delay-passive = <100>; 5971 polling-delay = <0>; 5972 5973 thermal-sensors = <&tsens1 2>; 5974 5975 trips { 5976 gpuss1_alert0: trip-point0 { 5977 temperature = <95000>; 5978 hysteresis = <2000>; 5979 type = "passive"; 5980 }; 5981 5982 gpuss1_crit: gpuss1-crit { 5983 temperature = <110000>; 5984 hysteresis = <0>; 5985 type = "critical"; 5986 }; 5987 }; 5988 5989 cooling-maps { 5990 map0 { 5991 trip = <&gpuss1_alert0>; 5992 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5993 }; 5994 }; 5995 }; 5996 5997 nspss0-thermal { 5998 polling-delay-passive = <0>; 5999 polling-delay = <0>; 6000 6001 thermal-sensors = <&tsens1 3>; 6002 6003 trips { 6004 nspss0_alert0: trip-point0 { 6005 temperature = <90000>; 6006 hysteresis = <2000>; 6007 type = "hot"; 6008 }; 6009 6010 nspss0_crit: nspss0-crit { 6011 temperature = <110000>; 6012 hysteresis = <0>; 6013 type = "critical"; 6014 }; 6015 }; 6016 }; 6017 6018 nspss1-thermal { 6019 polling-delay-passive = <0>; 6020 polling-delay = <0>; 6021 6022 thermal-sensors = <&tsens1 4>; 6023 6024 trips { 6025 nspss1_alert0: trip-point0 { 6026 temperature = <90000>; 6027 hysteresis = <2000>; 6028 type = "hot"; 6029 }; 6030 6031 nspss1_crit: nspss1-crit { 6032 temperature = <110000>; 6033 hysteresis = <0>; 6034 type = "critical"; 6035 }; 6036 }; 6037 }; 6038 6039 video-thermal { 6040 polling-delay-passive = <0>; 6041 polling-delay = <0>; 6042 6043 thermal-sensors = <&tsens1 5>; 6044 6045 trips { 6046 video_alert0: trip-point0 { 6047 temperature = <90000>; 6048 hysteresis = <2000>; 6049 type = "hot"; 6050 }; 6051 6052 video_crit: video-crit { 6053 temperature = <110000>; 6054 hysteresis = <0>; 6055 type = "critical"; 6056 }; 6057 }; 6058 }; 6059 6060 ddr-thermal { 6061 polling-delay-passive = <0>; 6062 polling-delay = <0>; 6063 6064 thermal-sensors = <&tsens1 6>; 6065 6066 trips { 6067 ddr_alert0: trip-point0 { 6068 temperature = <90000>; 6069 hysteresis = <2000>; 6070 type = "hot"; 6071 }; 6072 6073 ddr_crit: ddr-crit { 6074 temperature = <110000>; 6075 hysteresis = <0>; 6076 type = "critical"; 6077 }; 6078 }; 6079 }; 6080 6081 mdmss0-thermal { 6082 polling-delay-passive = <0>; 6083 polling-delay = <0>; 6084 6085 thermal-sensors = <&tsens1 7>; 6086 6087 trips { 6088 mdmss0_alert0: trip-point0 { 6089 temperature = <90000>; 6090 hysteresis = <2000>; 6091 type = "hot"; 6092 }; 6093 6094 mdmss0_crit: mdmss0-crit { 6095 temperature = <110000>; 6096 hysteresis = <0>; 6097 type = "critical"; 6098 }; 6099 }; 6100 }; 6101 6102 mdmss1-thermal { 6103 polling-delay-passive = <0>; 6104 polling-delay = <0>; 6105 6106 thermal-sensors = <&tsens1 8>; 6107 6108 trips { 6109 mdmss1_alert0: trip-point0 { 6110 temperature = <90000>; 6111 hysteresis = <2000>; 6112 type = "hot"; 6113 }; 6114 6115 mdmss1_crit: mdmss1-crit { 6116 temperature = <110000>; 6117 hysteresis = <0>; 6118 type = "critical"; 6119 }; 6120 }; 6121 }; 6122 6123 mdmss2-thermal { 6124 polling-delay-passive = <0>; 6125 polling-delay = <0>; 6126 6127 thermal-sensors = <&tsens1 9>; 6128 6129 trips { 6130 mdmss2_alert0: trip-point0 { 6131 temperature = <90000>; 6132 hysteresis = <2000>; 6133 type = "hot"; 6134 }; 6135 6136 mdmss2_crit: mdmss2-crit { 6137 temperature = <110000>; 6138 hysteresis = <0>; 6139 type = "critical"; 6140 }; 6141 }; 6142 }; 6143 6144 mdmss3-thermal { 6145 polling-delay-passive = <0>; 6146 polling-delay = <0>; 6147 6148 thermal-sensors = <&tsens1 10>; 6149 6150 trips { 6151 mdmss3_alert0: trip-point0 { 6152 temperature = <90000>; 6153 hysteresis = <2000>; 6154 type = "hot"; 6155 }; 6156 6157 mdmss3_crit: mdmss3-crit { 6158 temperature = <110000>; 6159 hysteresis = <0>; 6160 type = "critical"; 6161 }; 6162 }; 6163 }; 6164 6165 camera0-thermal { 6166 polling-delay-passive = <0>; 6167 polling-delay = <0>; 6168 6169 thermal-sensors = <&tsens1 11>; 6170 6171 trips { 6172 camera0_alert0: trip-point0 { 6173 temperature = <90000>; 6174 hysteresis = <2000>; 6175 type = "hot"; 6176 }; 6177 6178 camera0_crit: camera0-crit { 6179 temperature = <110000>; 6180 hysteresis = <0>; 6181 type = "critical"; 6182 }; 6183 }; 6184 }; 6185 }; 6186 6187 timer { 6188 compatible = "arm,armv8-timer"; 6189 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6190 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6191 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6192 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6193 }; 6194}; 6195