1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 756 wlan_smp2p_out: wlan-ap-to-wpss { 757 qcom,entry-name = "wlan"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 wlan_smp2p_in: wlan-wpss-to-ap { 762 qcom,entry-name = "wlan"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 }; 767 768 pmu { 769 compatible = "arm,armv8-pmuv3"; 770 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 771 }; 772 773 psci { 774 compatible = "arm,psci-1.0"; 775 method = "smc"; 776 }; 777 778 qspi_opp_table: opp-table-qspi { 779 compatible = "operating-points-v2"; 780 781 opp-75000000 { 782 opp-hz = /bits/ 64 <75000000>; 783 required-opps = <&rpmhpd_opp_low_svs>; 784 }; 785 786 opp-150000000 { 787 opp-hz = /bits/ 64 <150000000>; 788 required-opps = <&rpmhpd_opp_svs>; 789 }; 790 791 opp-200000000 { 792 opp-hz = /bits/ 64 <200000000>; 793 required-opps = <&rpmhpd_opp_svs_l1>; 794 }; 795 796 opp-300000000 { 797 opp-hz = /bits/ 64 <300000000>; 798 required-opps = <&rpmhpd_opp_nom>; 799 }; 800 }; 801 802 qup_opp_table: opp-table-qup { 803 compatible = "operating-points-v2"; 804 805 opp-75000000 { 806 opp-hz = /bits/ 64 <75000000>; 807 required-opps = <&rpmhpd_opp_low_svs>; 808 }; 809 810 opp-100000000 { 811 opp-hz = /bits/ 64 <100000000>; 812 required-opps = <&rpmhpd_opp_svs>; 813 }; 814 815 opp-128000000 { 816 opp-hz = /bits/ 64 <128000000>; 817 required-opps = <&rpmhpd_opp_nom>; 818 }; 819 }; 820 821 soc: soc@0 { 822 #address-cells = <2>; 823 #size-cells = <2>; 824 ranges = <0 0 0 0 0x10 0>; 825 dma-ranges = <0 0 0 0 0x10 0>; 826 compatible = "simple-bus"; 827 828 gcc: clock-controller@100000 { 829 compatible = "qcom,gcc-sc7280"; 830 reg = <0 0x00100000 0 0x1f0000>; 831 clocks = <&rpmhcc RPMH_CXO_CLK>, 832 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 833 <0>, <&pcie1_lane>, 834 <0>, <0>, <0>, <0>; 835 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 836 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 837 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 838 "ufs_phy_tx_symbol_0_clk", 839 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 840 #clock-cells = <1>; 841 #reset-cells = <1>; 842 #power-domain-cells = <1>; 843 power-domains = <&rpmhpd SC7280_CX>; 844 }; 845 846 ipcc: mailbox@408000 { 847 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 848 reg = <0 0x00408000 0 0x1000>; 849 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-controller; 851 #interrupt-cells = <3>; 852 #mbox-cells = <2>; 853 }; 854 855 qfprom: efuse@784000 { 856 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 857 reg = <0 0x00784000 0 0xa20>, 858 <0 0x00780000 0 0xa20>, 859 <0 0x00782000 0 0x120>, 860 <0 0x00786000 0 0x1fff>; 861 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 862 clock-names = "core"; 863 power-domains = <&rpmhpd SC7280_MX>; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 867 gpu_speed_bin: gpu_speed_bin@1e9 { 868 reg = <0x1e9 0x2>; 869 bits = <5 8>; 870 }; 871 }; 872 873 sdhc_1: mmc@7c4000 { 874 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 875 pinctrl-names = "default", "sleep"; 876 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 877 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 878 status = "disabled"; 879 880 reg = <0 0x007c4000 0 0x1000>, 881 <0 0x007c5000 0 0x1000>; 882 reg-names = "hc", "cqhci"; 883 884 iommus = <&apps_smmu 0xc0 0x0>; 885 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "hc_irq", "pwr_irq"; 888 889 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 890 <&gcc GCC_SDCC1_APPS_CLK>, 891 <&rpmhcc RPMH_CXO_CLK>; 892 clock-names = "iface", "core", "xo"; 893 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 895 interconnect-names = "sdhc-ddr","cpu-sdhc"; 896 power-domains = <&rpmhpd SC7280_CX>; 897 operating-points-v2 = <&sdhc1_opp_table>; 898 899 bus-width = <8>; 900 supports-cqe; 901 902 qcom,dll-config = <0x0007642c>; 903 qcom,ddr-config = <0x80040868>; 904 905 mmc-ddr-1_8v; 906 mmc-hs200-1_8v; 907 mmc-hs400-1_8v; 908 mmc-hs400-enhanced-strobe; 909 910 resets = <&gcc GCC_SDCC1_BCR>; 911 912 sdhc1_opp_table: opp-table { 913 compatible = "operating-points-v2"; 914 915 opp-100000000 { 916 opp-hz = /bits/ 64 <100000000>; 917 required-opps = <&rpmhpd_opp_low_svs>; 918 opp-peak-kBps = <1800000 400000>; 919 opp-avg-kBps = <100000 0>; 920 }; 921 922 opp-384000000 { 923 opp-hz = /bits/ 64 <384000000>; 924 required-opps = <&rpmhpd_opp_nom>; 925 opp-peak-kBps = <5400000 1600000>; 926 opp-avg-kBps = <390000 0>; 927 }; 928 }; 929 930 }; 931 932 gpi_dma0: dma-controller@900000 { 933 #dma-cells = <3>; 934 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 935 reg = <0 0x00900000 0 0x60000>; 936 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 948 dma-channels = <12>; 949 dma-channel-mask = <0x7f>; 950 iommus = <&apps_smmu 0x0136 0x0>; 951 status = "disabled"; 952 }; 953 954 qupv3_id_0: geniqup@9c0000 { 955 compatible = "qcom,geni-se-qup"; 956 reg = <0 0x009c0000 0 0x2000>; 957 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 958 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 959 clock-names = "m-ahb", "s-ahb"; 960 #address-cells = <2>; 961 #size-cells = <2>; 962 ranges; 963 iommus = <&apps_smmu 0x123 0x0>; 964 status = "disabled"; 965 966 i2c0: i2c@980000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0 0x00980000 0 0x4000>; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 970 clock-names = "se"; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c0_data_clk>; 973 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 978 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 979 interconnect-names = "qup-core", "qup-config", 980 "qup-memory"; 981 power-domains = <&rpmhpd SC7280_CX>; 982 required-opps = <&rpmhpd_opp_low_svs>; 983 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 984 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 spi0: spi@980000 { 990 compatible = "qcom,geni-spi"; 991 reg = <0 0x00980000 0 0x4000>; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 993 clock-names = "se"; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 996 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 power-domains = <&rpmhpd SC7280_CX>; 1000 operating-points-v2 = <&qup_opp_table>; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1003 interconnect-names = "qup-core", "qup-config"; 1004 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1005 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1006 dma-names = "tx", "rx"; 1007 status = "disabled"; 1008 }; 1009 1010 uart0: serial@980000 { 1011 compatible = "qcom,geni-uart"; 1012 reg = <0 0x00980000 0 0x4000>; 1013 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1014 clock-names = "se"; 1015 pinctrl-names = "default"; 1016 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1017 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1018 power-domains = <&rpmhpd SC7280_CX>; 1019 operating-points-v2 = <&qup_opp_table>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1021 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1022 interconnect-names = "qup-core", "qup-config"; 1023 status = "disabled"; 1024 }; 1025 1026 i2c1: i2c@984000 { 1027 compatible = "qcom,geni-i2c"; 1028 reg = <0 0x00984000 0 0x4000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1030 clock-names = "se"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_i2c1_data_clk>; 1033 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1038 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1039 interconnect-names = "qup-core", "qup-config", 1040 "qup-memory"; 1041 power-domains = <&rpmhpd SC7280_CX>; 1042 required-opps = <&rpmhpd_opp_low_svs>; 1043 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1044 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 status = "disabled"; 1047 }; 1048 1049 spi1: spi@984000 { 1050 compatible = "qcom,geni-spi"; 1051 reg = <0 0x00984000 0 0x4000>; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1053 clock-names = "se"; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1056 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 power-domains = <&rpmhpd SC7280_CX>; 1060 operating-points-v2 = <&qup_opp_table>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1063 interconnect-names = "qup-core", "qup-config"; 1064 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1065 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 status = "disabled"; 1068 }; 1069 1070 uart1: serial@984000 { 1071 compatible = "qcom,geni-uart"; 1072 reg = <0 0x00984000 0 0x4000>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1074 clock-names = "se"; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1077 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&rpmhpd SC7280_CX>; 1079 operating-points-v2 = <&qup_opp_table>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c2: i2c@988000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x00988000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_i2c2_data_clk>; 1093 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1098 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1099 interconnect-names = "qup-core", "qup-config", 1100 "qup-memory"; 1101 power-domains = <&rpmhpd SC7280_CX>; 1102 required-opps = <&rpmhpd_opp_low_svs>; 1103 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 status = "disabled"; 1107 }; 1108 1109 spi2: spi@988000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x00988000 0 0x4000>; 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1113 clock-names = "se"; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1116 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 power-domains = <&rpmhpd SC7280_CX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1125 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1126 dma-names = "tx", "rx"; 1127 status = "disabled"; 1128 }; 1129 1130 uart2: serial@988000 { 1131 compatible = "qcom,geni-uart"; 1132 reg = <0 0x00988000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1137 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd SC7280_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 status = "disabled"; 1144 }; 1145 1146 i2c3: i2c@98c000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x0098c000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c3_data_clk>; 1153 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1158 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1159 interconnect-names = "qup-core", "qup-config", 1160 "qup-memory"; 1161 power-domains = <&rpmhpd SC7280_CX>; 1162 required-opps = <&rpmhpd_opp_low_svs>; 1163 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 status = "disabled"; 1167 }; 1168 1169 spi3: spi@98c000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x0098c000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1176 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 power-domains = <&rpmhpd SC7280_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1183 interconnect-names = "qup-core", "qup-config"; 1184 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1185 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1186 dma-names = "tx", "rx"; 1187 status = "disabled"; 1188 }; 1189 1190 uart3: serial@98c000 { 1191 compatible = "qcom,geni-uart"; 1192 reg = <0 0x0098c000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1194 clock-names = "se"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1197 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1198 power-domains = <&rpmhpd SC7280_CX>; 1199 operating-points-v2 = <&qup_opp_table>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 status = "disabled"; 1204 }; 1205 1206 i2c4: i2c@990000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x00990000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c4_data_clk>; 1213 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1218 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1219 interconnect-names = "qup-core", "qup-config", 1220 "qup-memory"; 1221 power-domains = <&rpmhpd SC7280_CX>; 1222 required-opps = <&rpmhpd_opp_low_svs>; 1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1224 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1225 dma-names = "tx", "rx"; 1226 status = "disabled"; 1227 }; 1228 1229 spi4: spi@990000 { 1230 compatible = "qcom,geni-spi"; 1231 reg = <0 0x00990000 0 0x4000>; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1233 clock-names = "se"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1236 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 power-domains = <&rpmhpd SC7280_CX>; 1240 operating-points-v2 = <&qup_opp_table>; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1242 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1243 interconnect-names = "qup-core", "qup-config"; 1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1245 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1246 dma-names = "tx", "rx"; 1247 status = "disabled"; 1248 }; 1249 1250 uart4: serial@990000 { 1251 compatible = "qcom,geni-uart"; 1252 reg = <0 0x00990000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1254 clock-names = "se"; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1257 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1258 power-domains = <&rpmhpd SC7280_CX>; 1259 operating-points-v2 = <&qup_opp_table>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 status = "disabled"; 1264 }; 1265 1266 i2c5: i2c@994000 { 1267 compatible = "qcom,geni-i2c"; 1268 reg = <0 0x00994000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_i2c5_data_clk>; 1273 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1278 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1279 interconnect-names = "qup-core", "qup-config", 1280 "qup-memory"; 1281 power-domains = <&rpmhpd SC7280_CX>; 1282 required-opps = <&rpmhpd_opp_low_svs>; 1283 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1284 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1285 dma-names = "tx", "rx"; 1286 status = "disabled"; 1287 }; 1288 1289 spi5: spi@994000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00994000 0 0x4000>; 1292 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1293 clock-names = "se"; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1296 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 power-domains = <&rpmhpd SC7280_CX>; 1300 operating-points-v2 = <&qup_opp_table>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1303 interconnect-names = "qup-core", "qup-config"; 1304 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1305 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1306 dma-names = "tx", "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 uart5: serial@994000 { 1311 compatible = "qcom,geni-uart"; 1312 reg = <0 0x00994000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1314 clock-names = "se"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1317 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1318 power-domains = <&rpmhpd SC7280_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1322 interconnect-names = "qup-core", "qup-config"; 1323 status = "disabled"; 1324 }; 1325 1326 i2c6: i2c@998000 { 1327 compatible = "qcom,geni-i2c"; 1328 reg = <0 0x00998000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_i2c6_data_clk>; 1333 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", 1340 "qup-memory"; 1341 power-domains = <&rpmhpd SC7280_CX>; 1342 required-opps = <&rpmhpd_opp_low_svs>; 1343 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1344 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 status = "disabled"; 1347 }; 1348 1349 spi6: spi@998000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00998000 0 0x4000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1353 clock-names = "se"; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1356 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 power-domains = <&rpmhpd SC7280_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1365 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1366 dma-names = "tx", "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 uart6: serial@998000 { 1371 compatible = "qcom,geni-uart"; 1372 reg = <0 0x00998000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd SC7280_CX>; 1379 operating-points-v2 = <&qup_opp_table>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1382 interconnect-names = "qup-core", "qup-config"; 1383 status = "disabled"; 1384 }; 1385 1386 i2c7: i2c@99c000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x0099c000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c7_data_clk>; 1393 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1398 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1399 interconnect-names = "qup-core", "qup-config", 1400 "qup-memory"; 1401 power-domains = <&rpmhpd SC7280_CX>; 1402 required-opps = <&rpmhpd_opp_low_svs>; 1403 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1404 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1405 dma-names = "tx", "rx"; 1406 status = "disabled"; 1407 }; 1408 1409 spi7: spi@99c000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0 0x0099c000 0 0x4000>; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1413 clock-names = "se"; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1416 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 power-domains = <&rpmhpd SC7280_CX>; 1420 operating-points-v2 = <&qup_opp_table>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1425 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 uart7: serial@99c000 { 1431 compatible = "qcom,geni-uart"; 1432 reg = <0 0x0099c000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1437 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1438 power-domains = <&rpmhpd SC7280_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 status = "disabled"; 1444 }; 1445 }; 1446 1447 gpi_dma1: dma-controller@a00000 { 1448 #dma-cells = <3>; 1449 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1450 reg = <0 0x00a00000 0 0x60000>; 1451 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1463 dma-channels = <12>; 1464 dma-channel-mask = <0x1e>; 1465 iommus = <&apps_smmu 0x56 0x0>; 1466 status = "disabled"; 1467 }; 1468 1469 qupv3_id_1: geniqup@ac0000 { 1470 compatible = "qcom,geni-se-qup"; 1471 reg = <0 0x00ac0000 0 0x2000>; 1472 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1473 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1474 clock-names = "m-ahb", "s-ahb"; 1475 #address-cells = <2>; 1476 #size-cells = <2>; 1477 ranges; 1478 iommus = <&apps_smmu 0x43 0x0>; 1479 status = "disabled"; 1480 1481 i2c8: i2c@a80000 { 1482 compatible = "qcom,geni-i2c"; 1483 reg = <0 0x00a80000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1485 clock-names = "se"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_i2c8_data_clk>; 1488 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1492 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1493 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1494 interconnect-names = "qup-core", "qup-config", 1495 "qup-memory"; 1496 power-domains = <&rpmhpd SC7280_CX>; 1497 required-opps = <&rpmhpd_opp_low_svs>; 1498 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1499 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1500 dma-names = "tx", "rx"; 1501 status = "disabled"; 1502 }; 1503 1504 spi8: spi@a80000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0 0x00a80000 0 0x4000>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1508 clock-names = "se"; 1509 pinctrl-names = "default"; 1510 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1511 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 power-domains = <&rpmhpd SC7280_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1518 interconnect-names = "qup-core", "qup-config"; 1519 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1520 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1521 dma-names = "tx", "rx"; 1522 status = "disabled"; 1523 }; 1524 1525 uart8: serial@a80000 { 1526 compatible = "qcom,geni-uart"; 1527 reg = <0 0x00a80000 0 0x4000>; 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1529 clock-names = "se"; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1532 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1533 power-domains = <&rpmhpd SC7280_CX>; 1534 operating-points-v2 = <&qup_opp_table>; 1535 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1536 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1537 interconnect-names = "qup-core", "qup-config"; 1538 status = "disabled"; 1539 }; 1540 1541 i2c9: i2c@a84000 { 1542 compatible = "qcom,geni-i2c"; 1543 reg = <0 0x00a84000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_i2c9_data_clk>; 1548 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1552 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1553 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1554 interconnect-names = "qup-core", "qup-config", 1555 "qup-memory"; 1556 power-domains = <&rpmhpd SC7280_CX>; 1557 required-opps = <&rpmhpd_opp_low_svs>; 1558 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1559 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1560 dma-names = "tx", "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 spi9: spi@a84000 { 1565 compatible = "qcom,geni-spi"; 1566 reg = <0 0x00a84000 0 0x4000>; 1567 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1568 clock-names = "se"; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1571 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 power-domains = <&rpmhpd SC7280_CX>; 1575 operating-points-v2 = <&qup_opp_table>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1577 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1578 interconnect-names = "qup-core", "qup-config"; 1579 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1580 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1581 dma-names = "tx", "rx"; 1582 status = "disabled"; 1583 }; 1584 1585 uart9: serial@a84000 { 1586 compatible = "qcom,geni-uart"; 1587 reg = <0 0x00a84000 0 0x4000>; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1589 clock-names = "se"; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1592 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1593 power-domains = <&rpmhpd SC7280_CX>; 1594 operating-points-v2 = <&qup_opp_table>; 1595 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1596 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1597 interconnect-names = "qup-core", "qup-config"; 1598 status = "disabled"; 1599 }; 1600 1601 i2c10: i2c@a88000 { 1602 compatible = "qcom,geni-i2c"; 1603 reg = <0 0x00a88000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1605 clock-names = "se"; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_i2c10_data_clk>; 1608 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1612 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1613 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1614 interconnect-names = "qup-core", "qup-config", 1615 "qup-memory"; 1616 power-domains = <&rpmhpd SC7280_CX>; 1617 required-opps = <&rpmhpd_opp_low_svs>; 1618 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1619 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1620 dma-names = "tx", "rx"; 1621 status = "disabled"; 1622 }; 1623 1624 spi10: spi@a88000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a88000 0 0x4000>; 1627 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1628 clock-names = "se"; 1629 pinctrl-names = "default"; 1630 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1631 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 power-domains = <&rpmhpd SC7280_CX>; 1635 operating-points-v2 = <&qup_opp_table>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1638 interconnect-names = "qup-core", "qup-config"; 1639 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1640 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1641 dma-names = "tx", "rx"; 1642 status = "disabled"; 1643 }; 1644 1645 uart10: serial@a88000 { 1646 compatible = "qcom,geni-uart"; 1647 reg = <0 0x00a88000 0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1649 clock-names = "se"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1652 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1653 power-domains = <&rpmhpd SC7280_CX>; 1654 operating-points-v2 = <&qup_opp_table>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1657 interconnect-names = "qup-core", "qup-config"; 1658 status = "disabled"; 1659 }; 1660 1661 i2c11: i2c@a8c000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0 0x00a8c000 0 0x4000>; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1665 clock-names = "se"; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_i2c11_data_clk>; 1668 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", 1675 "qup-memory"; 1676 power-domains = <&rpmhpd SC7280_CX>; 1677 required-opps = <&rpmhpd_opp_low_svs>; 1678 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1679 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1680 dma-names = "tx", "rx"; 1681 status = "disabled"; 1682 }; 1683 1684 spi11: spi@a8c000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0 0x00a8c000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1691 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 power-domains = <&rpmhpd SC7280_CX>; 1695 operating-points-v2 = <&qup_opp_table>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1698 interconnect-names = "qup-core", "qup-config"; 1699 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1700 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 uart11: serial@a8c000 { 1706 compatible = "qcom,geni-uart"; 1707 reg = <0 0x00a8c000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1713 power-domains = <&rpmhpd SC7280_CX>; 1714 operating-points-v2 = <&qup_opp_table>; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1716 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1717 interconnect-names = "qup-core", "qup-config"; 1718 status = "disabled"; 1719 }; 1720 1721 i2c12: i2c@a90000 { 1722 compatible = "qcom,geni-i2c"; 1723 reg = <0 0x00a90000 0 0x4000>; 1724 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1725 clock-names = "se"; 1726 pinctrl-names = "default"; 1727 pinctrl-0 = <&qup_i2c12_data_clk>; 1728 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1732 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1733 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1734 interconnect-names = "qup-core", "qup-config", 1735 "qup-memory"; 1736 power-domains = <&rpmhpd SC7280_CX>; 1737 required-opps = <&rpmhpd_opp_low_svs>; 1738 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1739 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1740 dma-names = "tx", "rx"; 1741 status = "disabled"; 1742 }; 1743 1744 spi12: spi@a90000 { 1745 compatible = "qcom,geni-spi"; 1746 reg = <0 0x00a90000 0 0x4000>; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1748 clock-names = "se"; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1751 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 power-domains = <&rpmhpd SC7280_CX>; 1755 operating-points-v2 = <&qup_opp_table>; 1756 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1758 interconnect-names = "qup-core", "qup-config"; 1759 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1760 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 uart12: serial@a90000 { 1766 compatible = "qcom,geni-uart"; 1767 reg = <0 0x00a90000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 status = "disabled"; 1779 }; 1780 1781 i2c13: i2c@a94000 { 1782 compatible = "qcom,geni-i2c"; 1783 reg = <0 0x00a94000 0 0x4000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1785 clock-names = "se"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_i2c13_data_clk>; 1788 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1792 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1793 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1794 interconnect-names = "qup-core", "qup-config", 1795 "qup-memory"; 1796 power-domains = <&rpmhpd SC7280_CX>; 1797 required-opps = <&rpmhpd_opp_low_svs>; 1798 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1800 dma-names = "tx", "rx"; 1801 status = "disabled"; 1802 }; 1803 1804 spi13: spi@a94000 { 1805 compatible = "qcom,geni-spi"; 1806 reg = <0 0x00a94000 0 0x4000>; 1807 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1808 clock-names = "se"; 1809 pinctrl-names = "default"; 1810 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1811 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 power-domains = <&rpmhpd SC7280_CX>; 1815 operating-points-v2 = <&qup_opp_table>; 1816 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1818 interconnect-names = "qup-core", "qup-config"; 1819 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1820 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1821 dma-names = "tx", "rx"; 1822 status = "disabled"; 1823 }; 1824 1825 uart13: serial@a94000 { 1826 compatible = "qcom,geni-uart"; 1827 reg = <0 0x00a94000 0 0x4000>; 1828 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1829 clock-names = "se"; 1830 pinctrl-names = "default"; 1831 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1832 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 operating-points-v2 = <&qup_opp_table>; 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1837 interconnect-names = "qup-core", "qup-config"; 1838 status = "disabled"; 1839 }; 1840 1841 i2c14: i2c@a98000 { 1842 compatible = "qcom,geni-i2c"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1845 clock-names = "se"; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_i2c14_data_clk>; 1848 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1852 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1853 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1854 interconnect-names = "qup-core", "qup-config", 1855 "qup-memory"; 1856 power-domains = <&rpmhpd SC7280_CX>; 1857 required-opps = <&rpmhpd_opp_low_svs>; 1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1859 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1860 dma-names = "tx", "rx"; 1861 status = "disabled"; 1862 }; 1863 1864 spi14: spi@a98000 { 1865 compatible = "qcom,geni-spi"; 1866 reg = <0 0x00a98000 0 0x4000>; 1867 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1868 clock-names = "se"; 1869 pinctrl-names = "default"; 1870 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1871 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 power-domains = <&rpmhpd SC7280_CX>; 1875 operating-points-v2 = <&qup_opp_table>; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1878 interconnect-names = "qup-core", "qup-config"; 1879 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1880 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1881 dma-names = "tx", "rx"; 1882 status = "disabled"; 1883 }; 1884 1885 uart14: serial@a98000 { 1886 compatible = "qcom,geni-uart"; 1887 reg = <0 0x00a98000 0 0x4000>; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1889 clock-names = "se"; 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1892 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1893 power-domains = <&rpmhpd SC7280_CX>; 1894 operating-points-v2 = <&qup_opp_table>; 1895 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1896 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1897 interconnect-names = "qup-core", "qup-config"; 1898 status = "disabled"; 1899 }; 1900 1901 i2c15: i2c@a9c000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0 0x00a9c000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_i2c15_data_clk>; 1908 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1909 #address-cells = <1>; 1910 #size-cells = <0>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1913 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1914 interconnect-names = "qup-core", "qup-config", 1915 "qup-memory"; 1916 power-domains = <&rpmhpd SC7280_CX>; 1917 required-opps = <&rpmhpd_opp_low_svs>; 1918 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1919 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1920 dma-names = "tx", "rx"; 1921 status = "disabled"; 1922 }; 1923 1924 spi15: spi@a9c000 { 1925 compatible = "qcom,geni-spi"; 1926 reg = <0 0x00a9c000 0 0x4000>; 1927 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1928 clock-names = "se"; 1929 pinctrl-names = "default"; 1930 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1931 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1932 #address-cells = <1>; 1933 #size-cells = <0>; 1934 power-domains = <&rpmhpd SC7280_CX>; 1935 operating-points-v2 = <&qup_opp_table>; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1938 interconnect-names = "qup-core", "qup-config"; 1939 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1940 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1941 dma-names = "tx", "rx"; 1942 status = "disabled"; 1943 }; 1944 1945 uart15: serial@a9c000 { 1946 compatible = "qcom,geni-uart"; 1947 reg = <0 0x00a9c000 0 0x4000>; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1949 clock-names = "se"; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1952 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1953 power-domains = <&rpmhpd SC7280_CX>; 1954 operating-points-v2 = <&qup_opp_table>; 1955 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1956 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1957 interconnect-names = "qup-core", "qup-config"; 1958 status = "disabled"; 1959 }; 1960 }; 1961 1962 cnoc2: interconnect@1500000 { 1963 reg = <0 0x01500000 0 0x1000>; 1964 compatible = "qcom,sc7280-cnoc2"; 1965 #interconnect-cells = <2>; 1966 qcom,bcm-voters = <&apps_bcm_voter>; 1967 }; 1968 1969 cnoc3: interconnect@1502000 { 1970 reg = <0 0x01502000 0 0x1000>; 1971 compatible = "qcom,sc7280-cnoc3"; 1972 #interconnect-cells = <2>; 1973 qcom,bcm-voters = <&apps_bcm_voter>; 1974 }; 1975 1976 mc_virt: interconnect@1580000 { 1977 reg = <0 0x01580000 0 0x4>; 1978 compatible = "qcom,sc7280-mc-virt"; 1979 #interconnect-cells = <2>; 1980 qcom,bcm-voters = <&apps_bcm_voter>; 1981 }; 1982 1983 system_noc: interconnect@1680000 { 1984 reg = <0 0x01680000 0 0x15480>; 1985 compatible = "qcom,sc7280-system-noc"; 1986 #interconnect-cells = <2>; 1987 qcom,bcm-voters = <&apps_bcm_voter>; 1988 }; 1989 1990 aggre1_noc: interconnect@16e0000 { 1991 compatible = "qcom,sc7280-aggre1-noc"; 1992 reg = <0 0x016e0000 0 0x1c080>; 1993 #interconnect-cells = <2>; 1994 qcom,bcm-voters = <&apps_bcm_voter>; 1995 }; 1996 1997 aggre2_noc: interconnect@1700000 { 1998 reg = <0 0x01700000 0 0x2b080>; 1999 compatible = "qcom,sc7280-aggre2-noc"; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 }; 2003 2004 mmss_noc: interconnect@1740000 { 2005 reg = <0 0x01740000 0 0x1e080>; 2006 compatible = "qcom,sc7280-mmss-noc"; 2007 #interconnect-cells = <2>; 2008 qcom,bcm-voters = <&apps_bcm_voter>; 2009 }; 2010 2011 wifi: wifi@17a10040 { 2012 compatible = "qcom,wcn6750-wifi"; 2013 reg = <0 0x17a10040 0 0x0>; 2014 iommus = <&apps_smmu 0x1c00 0x1>; 2015 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2016 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2017 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2018 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2019 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2020 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2021 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2022 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2023 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2024 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2025 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2026 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2027 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2028 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2029 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2030 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2031 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2047 qcom,rproc = <&remoteproc_wpss>; 2048 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2049 status = "disabled"; 2050 qcom,smem-states = <&wlan_smp2p_out 0>; 2051 qcom,smem-state-names = "wlan-smp2p-out"; 2052 }; 2053 2054 pcie1: pci@1c08000 { 2055 compatible = "qcom,pcie-sc7280"; 2056 reg = <0 0x01c08000 0 0x3000>, 2057 <0 0x40000000 0 0xf1d>, 2058 <0 0x40000f20 0 0xa8>, 2059 <0 0x40001000 0 0x1000>, 2060 <0 0x40100000 0 0x100000>; 2061 2062 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2063 device_type = "pci"; 2064 linux,pci-domain = <1>; 2065 bus-range = <0x00 0xff>; 2066 num-lanes = <2>; 2067 2068 #address-cells = <3>; 2069 #size-cells = <2>; 2070 2071 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2072 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2073 2074 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2075 interrupt-names = "msi"; 2076 #interrupt-cells = <1>; 2077 interrupt-map-mask = <0 0 0 0x7>; 2078 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2079 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2080 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2081 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2082 2083 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2084 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2085 <&pcie1_lane>, 2086 <&rpmhcc RPMH_CXO_CLK>, 2087 <&gcc GCC_PCIE_1_AUX_CLK>, 2088 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2089 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2090 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2091 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2092 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2093 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2094 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2095 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2096 2097 clock-names = "pipe", 2098 "pipe_mux", 2099 "phy_pipe", 2100 "ref", 2101 "aux", 2102 "cfg", 2103 "bus_master", 2104 "bus_slave", 2105 "slave_q2a", 2106 "tbu", 2107 "ddrss_sf_tbu", 2108 "aggre0", 2109 "aggre1"; 2110 2111 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2112 assigned-clock-rates = <19200000>; 2113 2114 resets = <&gcc GCC_PCIE_1_BCR>; 2115 reset-names = "pci"; 2116 2117 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2118 2119 phys = <&pcie1_lane>; 2120 phy-names = "pciephy"; 2121 2122 pinctrl-names = "default"; 2123 pinctrl-0 = <&pcie1_clkreq_n>; 2124 2125 iommus = <&apps_smmu 0x1c80 0x1>; 2126 2127 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2128 <0x100 &apps_smmu 0x1c81 0x1>; 2129 2130 status = "disabled"; 2131 }; 2132 2133 pcie1_phy: phy@1c0e000 { 2134 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2135 reg = <0 0x01c0e000 0 0x1c0>; 2136 #address-cells = <2>; 2137 #size-cells = <2>; 2138 ranges; 2139 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2140 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2141 <&gcc GCC_PCIE_CLKREF_EN>, 2142 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2143 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2144 2145 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2146 reset-names = "phy"; 2147 2148 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2149 assigned-clock-rates = <100000000>; 2150 2151 status = "disabled"; 2152 2153 pcie1_lane: phy@1c0e200 { 2154 reg = <0 0x01c0e200 0 0x170>, 2155 <0 0x01c0e400 0 0x200>, 2156 <0 0x01c0ea00 0 0x1f0>, 2157 <0 0x01c0e600 0 0x170>, 2158 <0 0x01c0e800 0 0x200>, 2159 <0 0x01c0ee00 0 0xf4>; 2160 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2161 clock-names = "pipe0"; 2162 2163 #phy-cells = <0>; 2164 #clock-cells = <0>; 2165 clock-output-names = "pcie_1_pipe_clk"; 2166 }; 2167 }; 2168 2169 ipa: ipa@1e40000 { 2170 compatible = "qcom,sc7280-ipa"; 2171 2172 iommus = <&apps_smmu 0x480 0x0>, 2173 <&apps_smmu 0x482 0x0>; 2174 reg = <0 0x1e40000 0 0x8000>, 2175 <0 0x1e50000 0 0x4ad0>, 2176 <0 0x1e04000 0 0x23000>; 2177 reg-names = "ipa-reg", 2178 "ipa-shared", 2179 "gsi"; 2180 2181 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2182 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2183 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2184 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2185 interrupt-names = "ipa", 2186 "gsi", 2187 "ipa-clock-query", 2188 "ipa-setup-ready"; 2189 2190 clocks = <&rpmhcc RPMH_IPA_CLK>; 2191 clock-names = "core"; 2192 2193 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2195 interconnect-names = "memory", 2196 "config"; 2197 2198 qcom,qmp = <&aoss_qmp>; 2199 2200 qcom,smem-states = <&ipa_smp2p_out 0>, 2201 <&ipa_smp2p_out 1>; 2202 qcom,smem-state-names = "ipa-clock-enabled-valid", 2203 "ipa-clock-enabled"; 2204 2205 status = "disabled"; 2206 }; 2207 2208 tcsr_mutex: hwlock@1f40000 { 2209 compatible = "qcom,tcsr-mutex"; 2210 reg = <0 0x01f40000 0 0x20000>; 2211 #hwlock-cells = <1>; 2212 }; 2213 2214 tcsr_1: syscon@1f60000 { 2215 compatible = "qcom,sc7280-tcsr", "syscon"; 2216 reg = <0 0x01f60000 0 0x20000>; 2217 }; 2218 2219 tcsr_2: syscon@1fc0000 { 2220 compatible = "qcom,sc7280-tcsr", "syscon"; 2221 reg = <0 0x01fc0000 0 0x30000>; 2222 }; 2223 2224 lpasscc: lpasscc@3000000 { 2225 compatible = "qcom,sc7280-lpasscc"; 2226 reg = <0 0x03000000 0 0x40>, 2227 <0 0x03c04000 0 0x4>; 2228 reg-names = "qdsp6ss", "top_cc"; 2229 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2230 clock-names = "iface"; 2231 #clock-cells = <1>; 2232 }; 2233 2234 lpass_rx_macro: codec@3200000 { 2235 compatible = "qcom,sc7280-lpass-rx-macro"; 2236 reg = <0 0x03200000 0 0x1000>; 2237 2238 pinctrl-names = "default"; 2239 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2240 2241 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2242 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2243 <&lpass_va_macro>; 2244 clock-names = "mclk", "npl", "fsgen"; 2245 2246 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2247 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2248 power-domain-names = "macro", "dcodec"; 2249 2250 #clock-cells = <0>; 2251 #sound-dai-cells = <1>; 2252 2253 status = "disabled"; 2254 }; 2255 2256 swr0: soundwire@3210000 { 2257 compatible = "qcom,soundwire-v1.6.0"; 2258 reg = <0 0x03210000 0 0x2000>; 2259 2260 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2261 clocks = <&lpass_rx_macro>; 2262 clock-names = "iface"; 2263 2264 qcom,din-ports = <0>; 2265 qcom,dout-ports = <5>; 2266 2267 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2268 reset-names = "swr_audio_cgcr"; 2269 2270 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2271 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2272 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2273 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2274 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2275 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2276 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2277 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2279 2280 #sound-dai-cells = <1>; 2281 #address-cells = <2>; 2282 #size-cells = <0>; 2283 2284 status = "disabled"; 2285 }; 2286 2287 lpass_tx_macro: codec@3220000 { 2288 compatible = "qcom,sc7280-lpass-tx-macro"; 2289 reg = <0 0x03220000 0 0x1000>; 2290 2291 pinctrl-names = "default"; 2292 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2293 2294 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2295 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2296 <&lpass_va_macro>; 2297 clock-names = "mclk", "npl", "fsgen"; 2298 2299 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2300 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2301 power-domain-names = "macro", "dcodec"; 2302 2303 #clock-cells = <0>; 2304 #sound-dai-cells = <1>; 2305 2306 status = "disabled"; 2307 }; 2308 2309 swr1: soundwire@3230000 { 2310 compatible = "qcom,soundwire-v1.6.0"; 2311 reg = <0 0x03230000 0 0x2000>; 2312 2313 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2314 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2315 clocks = <&lpass_tx_macro>; 2316 clock-names = "iface"; 2317 2318 qcom,din-ports = <3>; 2319 qcom,dout-ports = <0>; 2320 2321 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2322 reset-names = "swr_audio_cgcr"; 2323 2324 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2325 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2326 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2327 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2328 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2329 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2330 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2331 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2332 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2333 2334 #sound-dai-cells = <1>; 2335 #address-cells = <2>; 2336 #size-cells = <0>; 2337 2338 status = "disabled"; 2339 }; 2340 2341 lpass_audiocc: clock-controller@3300000 { 2342 compatible = "qcom,sc7280-lpassaudiocc"; 2343 reg = <0 0x03300000 0 0x30000>, 2344 <0 0x032a9000 0 0x1000>; 2345 clocks = <&rpmhcc RPMH_CXO_CLK>, 2346 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2347 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2348 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2349 #clock-cells = <1>; 2350 #power-domain-cells = <1>; 2351 #reset-cells = <1>; 2352 }; 2353 2354 lpass_va_macro: codec@3370000 { 2355 compatible = "qcom,sc7280-lpass-va-macro"; 2356 reg = <0 0x03370000 0 0x1000>; 2357 2358 pinctrl-names = "default"; 2359 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2360 2361 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2362 clock-names = "mclk"; 2363 2364 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2365 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2366 power-domain-names = "macro", "dcodec"; 2367 2368 #clock-cells = <0>; 2369 #sound-dai-cells = <1>; 2370 2371 status = "disabled"; 2372 }; 2373 2374 lpass_aon: clock-controller@3380000 { 2375 compatible = "qcom,sc7280-lpassaoncc"; 2376 reg = <0 0x03380000 0 0x30000>; 2377 clocks = <&rpmhcc RPMH_CXO_CLK>, 2378 <&rpmhcc RPMH_CXO_CLK_A>, 2379 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2380 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2381 #clock-cells = <1>; 2382 #power-domain-cells = <1>; 2383 }; 2384 2385 lpass_core: clock-controller@3900000 { 2386 compatible = "qcom,sc7280-lpasscorecc"; 2387 reg = <0 0x03900000 0 0x50000>; 2388 clocks = <&rpmhcc RPMH_CXO_CLK>; 2389 clock-names = "bi_tcxo"; 2390 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2391 #clock-cells = <1>; 2392 #power-domain-cells = <1>; 2393 }; 2394 2395 lpass_cpu: audio@3987000 { 2396 compatible = "qcom,sc7280-lpass-cpu"; 2397 2398 reg = <0 0x03987000 0 0x68000>, 2399 <0 0x03b00000 0 0x29000>, 2400 <0 0x03260000 0 0xc000>, 2401 <0 0x03280000 0 0x29000>, 2402 <0 0x03340000 0 0x29000>, 2403 <0 0x0336c000 0 0x3000>; 2404 reg-names = "lpass-hdmiif", 2405 "lpass-lpaif", 2406 "lpass-rxtx-cdc-dma-lpm", 2407 "lpass-rxtx-lpaif", 2408 "lpass-va-lpaif", 2409 "lpass-va-cdc-dma-lpm"; 2410 2411 iommus = <&apps_smmu 0x1820 0>, 2412 <&apps_smmu 0x1821 0>, 2413 <&apps_smmu 0x1832 0>; 2414 2415 power-domains = <&rpmhpd SC7280_LCX>; 2416 power-domain-names = "lcx"; 2417 required-opps = <&rpmhpd_opp_nom>; 2418 2419 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2420 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2421 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2422 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2423 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2424 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2425 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2426 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2427 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2428 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2429 clock-names = "aon_cc_audio_hm_h", 2430 "audio_cc_ext_mclk0", 2431 "core_cc_sysnoc_mport_core", 2432 "core_cc_ext_if0_ibit", 2433 "core_cc_ext_if1_ibit", 2434 "audio_cc_codec_mem", 2435 "audio_cc_codec_mem0", 2436 "audio_cc_codec_mem1", 2437 "audio_cc_codec_mem2", 2438 "aon_cc_va_mem0"; 2439 2440 #sound-dai-cells = <1>; 2441 #address-cells = <1>; 2442 #size-cells = <0>; 2443 2444 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2448 interrupt-names = "lpass-irq-lpaif", 2449 "lpass-irq-hdmi", 2450 "lpass-irq-vaif", 2451 "lpass-irq-rxtxif"; 2452 2453 status = "disabled"; 2454 }; 2455 2456 lpass_hm: clock-controller@3c00000 { 2457 compatible = "qcom,sc7280-lpasshm"; 2458 reg = <0 0x3c00000 0 0x28>; 2459 clocks = <&rpmhcc RPMH_CXO_CLK>; 2460 clock-names = "bi_tcxo"; 2461 #clock-cells = <1>; 2462 #power-domain-cells = <1>; 2463 }; 2464 2465 lpass_ag_noc: interconnect@3c40000 { 2466 reg = <0 0x03c40000 0 0xf080>; 2467 compatible = "qcom,sc7280-lpass-ag-noc"; 2468 #interconnect-cells = <2>; 2469 qcom,bcm-voters = <&apps_bcm_voter>; 2470 }; 2471 2472 lpass_tlmm: pinctrl@33c0000 { 2473 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2474 reg = <0 0x033c0000 0x0 0x20000>, 2475 <0 0x03550000 0x0 0x10000>; 2476 qcom,adsp-bypass-mode; 2477 gpio-controller; 2478 #gpio-cells = <2>; 2479 gpio-ranges = <&lpass_tlmm 0 0 15>; 2480 2481 lpass_dmic01_clk: dmic01-clk-state { 2482 pins = "gpio6"; 2483 function = "dmic1_clk"; 2484 }; 2485 2486 lpass_dmic01_clk_sleep: dmic01-clk-sleep-state { 2487 pins = "gpio6"; 2488 function = "dmic1_clk"; 2489 }; 2490 2491 lpass_dmic01_data: dmic01-data-state { 2492 pins = "gpio7"; 2493 function = "dmic1_data"; 2494 }; 2495 2496 lpass_dmic01_data_sleep: dmic01-data-sleep-state { 2497 pins = "gpio7"; 2498 function = "dmic1_data"; 2499 }; 2500 2501 lpass_dmic23_clk: dmic23-clk-state { 2502 pins = "gpio8"; 2503 function = "dmic2_clk"; 2504 }; 2505 2506 lpass_dmic23_clk_sleep: dmic23-clk-sleep-state { 2507 pins = "gpio8"; 2508 function = "dmic2_clk"; 2509 }; 2510 2511 lpass_dmic23_data: dmic23-data-state { 2512 pins = "gpio9"; 2513 function = "dmic2_data"; 2514 }; 2515 2516 lpass_dmic23_data_sleep: dmic23-data-sleep-state { 2517 pins = "gpio9"; 2518 function = "dmic2_data"; 2519 }; 2520 2521 lpass_rx_swr_clk: rx-swr-clk-state { 2522 pins = "gpio3"; 2523 function = "swr_rx_clk"; 2524 }; 2525 2526 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep-state { 2527 pins = "gpio3"; 2528 function = "swr_rx_clk"; 2529 }; 2530 2531 lpass_rx_swr_data: rx-swr-data-state { 2532 pins = "gpio4", "gpio5"; 2533 function = "swr_rx_data"; 2534 }; 2535 2536 lpass_rx_swr_data_sleep: rx-swr-data-sleep-state { 2537 pins = "gpio4", "gpio5"; 2538 function = "swr_rx_data"; 2539 }; 2540 2541 lpass_tx_swr_clk: tx-swr-clk-state { 2542 pins = "gpio0"; 2543 function = "swr_tx_clk"; 2544 }; 2545 2546 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep-state { 2547 pins = "gpio0"; 2548 function = "swr_tx_clk"; 2549 }; 2550 2551 lpass_tx_swr_data: tx-swr-data-state { 2552 pins = "gpio1", "gpio2", "gpio14"; 2553 function = "swr_tx_data"; 2554 }; 2555 2556 lpass_tx_swr_data_sleep: tx-swr-data-sleep-state { 2557 pins = "gpio1", "gpio2", "gpio14"; 2558 function = "swr_tx_data"; 2559 }; 2560 }; 2561 2562 gpu: gpu@3d00000 { 2563 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2564 reg = <0 0x03d00000 0 0x40000>, 2565 <0 0x03d9e000 0 0x1000>, 2566 <0 0x03d61000 0 0x800>; 2567 reg-names = "kgsl_3d0_reg_memory", 2568 "cx_mem", 2569 "cx_dbgc"; 2570 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2571 iommus = <&adreno_smmu 0 0x401>; 2572 operating-points-v2 = <&gpu_opp_table>; 2573 qcom,gmu = <&gmu>; 2574 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2575 interconnect-names = "gfx-mem"; 2576 #cooling-cells = <2>; 2577 2578 nvmem-cells = <&gpu_speed_bin>; 2579 nvmem-cell-names = "speed_bin"; 2580 2581 gpu_opp_table: opp-table { 2582 compatible = "operating-points-v2"; 2583 2584 opp-315000000 { 2585 opp-hz = /bits/ 64 <315000000>; 2586 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2587 opp-peak-kBps = <1804000>; 2588 opp-supported-hw = <0x03>; 2589 }; 2590 2591 opp-450000000 { 2592 opp-hz = /bits/ 64 <450000000>; 2593 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2594 opp-peak-kBps = <4068000>; 2595 opp-supported-hw = <0x03>; 2596 }; 2597 2598 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2599 opp-550000000-0 { 2600 opp-hz = /bits/ 64 <550000000>; 2601 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2602 opp-peak-kBps = <8368000>; 2603 opp-supported-hw = <0x01>; 2604 }; 2605 2606 opp-550000000-1 { 2607 opp-hz = /bits/ 64 <550000000>; 2608 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2609 opp-peak-kBps = <6832000>; 2610 opp-supported-hw = <0x02>; 2611 }; 2612 2613 opp-608000000 { 2614 opp-hz = /bits/ 64 <608000000>; 2615 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2616 opp-peak-kBps = <8368000>; 2617 opp-supported-hw = <0x02>; 2618 }; 2619 2620 opp-700000000 { 2621 opp-hz = /bits/ 64 <700000000>; 2622 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2623 opp-peak-kBps = <8532000>; 2624 opp-supported-hw = <0x02>; 2625 }; 2626 2627 opp-812000000 { 2628 opp-hz = /bits/ 64 <812000000>; 2629 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2630 opp-peak-kBps = <8532000>; 2631 opp-supported-hw = <0x02>; 2632 }; 2633 2634 opp-840000000 { 2635 opp-hz = /bits/ 64 <840000000>; 2636 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2637 opp-peak-kBps = <8532000>; 2638 opp-supported-hw = <0x02>; 2639 }; 2640 2641 opp-900000000 { 2642 opp-hz = /bits/ 64 <900000000>; 2643 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2644 opp-peak-kBps = <8532000>; 2645 opp-supported-hw = <0x02>; 2646 }; 2647 }; 2648 }; 2649 2650 gmu: gmu@3d6a000 { 2651 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2652 reg = <0 0x03d6a000 0 0x34000>, 2653 <0 0x3de0000 0 0x10000>, 2654 <0 0x0b290000 0 0x10000>; 2655 reg-names = "gmu", "rscc", "gmu_pdc"; 2656 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2657 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2658 interrupt-names = "hfi", "gmu"; 2659 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2660 <&gpucc GPU_CC_CXO_CLK>, 2661 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2662 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2663 <&gpucc GPU_CC_AHB_CLK>, 2664 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2665 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2666 clock-names = "gmu", 2667 "cxo", 2668 "axi", 2669 "memnoc", 2670 "ahb", 2671 "hub", 2672 "smmu_vote"; 2673 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2674 <&gpucc GPU_CC_GX_GDSC>; 2675 power-domain-names = "cx", 2676 "gx"; 2677 iommus = <&adreno_smmu 5 0x400>; 2678 operating-points-v2 = <&gmu_opp_table>; 2679 2680 gmu_opp_table: opp-table { 2681 compatible = "operating-points-v2"; 2682 2683 opp-200000000 { 2684 opp-hz = /bits/ 64 <200000000>; 2685 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2686 }; 2687 }; 2688 }; 2689 2690 gpucc: clock-controller@3d90000 { 2691 compatible = "qcom,sc7280-gpucc"; 2692 reg = <0 0x03d90000 0 0x9000>; 2693 clocks = <&rpmhcc RPMH_CXO_CLK>, 2694 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2695 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2696 clock-names = "bi_tcxo", 2697 "gcc_gpu_gpll0_clk_src", 2698 "gcc_gpu_gpll0_div_clk_src"; 2699 #clock-cells = <1>; 2700 #reset-cells = <1>; 2701 #power-domain-cells = <1>; 2702 }; 2703 2704 adreno_smmu: iommu@3da0000 { 2705 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2706 reg = <0 0x03da0000 0 0x20000>; 2707 #iommu-cells = <2>; 2708 #global-interrupts = <2>; 2709 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2721 2722 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2723 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2724 <&gpucc GPU_CC_AHB_CLK>, 2725 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2726 <&gpucc GPU_CC_CX_GMU_CLK>, 2727 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2728 <&gpucc GPU_CC_HUB_AON_CLK>; 2729 clock-names = "gcc_gpu_memnoc_gfx_clk", 2730 "gcc_gpu_snoc_dvm_gfx_clk", 2731 "gpu_cc_ahb_clk", 2732 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2733 "gpu_cc_cx_gmu_clk", 2734 "gpu_cc_hub_cx_int_clk", 2735 "gpu_cc_hub_aon_clk"; 2736 2737 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2738 }; 2739 2740 remoteproc_mpss: remoteproc@4080000 { 2741 compatible = "qcom,sc7280-mpss-pas"; 2742 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2743 reg-names = "qdsp6", "rmb"; 2744 2745 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2746 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2747 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2748 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2749 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2750 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2751 interrupt-names = "wdog", "fatal", "ready", "handover", 2752 "stop-ack", "shutdown-ack"; 2753 2754 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2755 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2756 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2757 <&rpmhcc RPMH_PKA_CLK>, 2758 <&rpmhcc RPMH_CXO_CLK>; 2759 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2760 2761 power-domains = <&rpmhpd SC7280_CX>, 2762 <&rpmhpd SC7280_MSS>; 2763 power-domain-names = "cx", "mss"; 2764 2765 memory-region = <&mpss_mem>; 2766 2767 qcom,qmp = <&aoss_qmp>; 2768 2769 qcom,smem-states = <&modem_smp2p_out 0>; 2770 qcom,smem-state-names = "stop"; 2771 2772 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2773 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2774 reset-names = "mss_restart", "pdc_reset"; 2775 2776 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2777 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2778 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2779 2780 status = "disabled"; 2781 2782 glink-edge { 2783 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2784 IPCC_MPROC_SIGNAL_GLINK_QMP 2785 IRQ_TYPE_EDGE_RISING>; 2786 mboxes = <&ipcc IPCC_CLIENT_MPSS 2787 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2788 label = "modem"; 2789 qcom,remote-pid = <1>; 2790 }; 2791 }; 2792 2793 stm@6002000 { 2794 compatible = "arm,coresight-stm", "arm,primecell"; 2795 reg = <0 0x06002000 0 0x1000>, 2796 <0 0x16280000 0 0x180000>; 2797 reg-names = "stm-base", "stm-stimulus-base"; 2798 2799 clocks = <&aoss_qmp>; 2800 clock-names = "apb_pclk"; 2801 2802 out-ports { 2803 port { 2804 stm_out: endpoint { 2805 remote-endpoint = <&funnel0_in7>; 2806 }; 2807 }; 2808 }; 2809 }; 2810 2811 funnel@6041000 { 2812 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2813 reg = <0 0x06041000 0 0x1000>; 2814 2815 clocks = <&aoss_qmp>; 2816 clock-names = "apb_pclk"; 2817 2818 out-ports { 2819 port { 2820 funnel0_out: endpoint { 2821 remote-endpoint = <&merge_funnel_in0>; 2822 }; 2823 }; 2824 }; 2825 2826 in-ports { 2827 #address-cells = <1>; 2828 #size-cells = <0>; 2829 2830 port@7 { 2831 reg = <7>; 2832 funnel0_in7: endpoint { 2833 remote-endpoint = <&stm_out>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 2839 funnel@6042000 { 2840 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2841 reg = <0 0x06042000 0 0x1000>; 2842 2843 clocks = <&aoss_qmp>; 2844 clock-names = "apb_pclk"; 2845 2846 out-ports { 2847 port { 2848 funnel1_out: endpoint { 2849 remote-endpoint = <&merge_funnel_in1>; 2850 }; 2851 }; 2852 }; 2853 2854 in-ports { 2855 #address-cells = <1>; 2856 #size-cells = <0>; 2857 2858 port@4 { 2859 reg = <4>; 2860 funnel1_in4: endpoint { 2861 remote-endpoint = <&apss_merge_funnel_out>; 2862 }; 2863 }; 2864 }; 2865 }; 2866 2867 funnel@6045000 { 2868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2869 reg = <0 0x06045000 0 0x1000>; 2870 2871 clocks = <&aoss_qmp>; 2872 clock-names = "apb_pclk"; 2873 2874 out-ports { 2875 port { 2876 merge_funnel_out: endpoint { 2877 remote-endpoint = <&swao_funnel_in>; 2878 }; 2879 }; 2880 }; 2881 2882 in-ports { 2883 #address-cells = <1>; 2884 #size-cells = <0>; 2885 2886 port@0 { 2887 reg = <0>; 2888 merge_funnel_in0: endpoint { 2889 remote-endpoint = <&funnel0_out>; 2890 }; 2891 }; 2892 2893 port@1 { 2894 reg = <1>; 2895 merge_funnel_in1: endpoint { 2896 remote-endpoint = <&funnel1_out>; 2897 }; 2898 }; 2899 }; 2900 }; 2901 2902 replicator@6046000 { 2903 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2904 reg = <0 0x06046000 0 0x1000>; 2905 2906 clocks = <&aoss_qmp>; 2907 clock-names = "apb_pclk"; 2908 2909 out-ports { 2910 port { 2911 replicator_out: endpoint { 2912 remote-endpoint = <&etr_in>; 2913 }; 2914 }; 2915 }; 2916 2917 in-ports { 2918 port { 2919 replicator_in: endpoint { 2920 remote-endpoint = <&swao_replicator_out>; 2921 }; 2922 }; 2923 }; 2924 }; 2925 2926 etr@6048000 { 2927 compatible = "arm,coresight-tmc", "arm,primecell"; 2928 reg = <0 0x06048000 0 0x1000>; 2929 iommus = <&apps_smmu 0x04c0 0>; 2930 2931 clocks = <&aoss_qmp>; 2932 clock-names = "apb_pclk"; 2933 arm,scatter-gather; 2934 2935 in-ports { 2936 port { 2937 etr_in: endpoint { 2938 remote-endpoint = <&replicator_out>; 2939 }; 2940 }; 2941 }; 2942 }; 2943 2944 funnel@6b04000 { 2945 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2946 reg = <0 0x06b04000 0 0x1000>; 2947 2948 clocks = <&aoss_qmp>; 2949 clock-names = "apb_pclk"; 2950 2951 out-ports { 2952 port { 2953 swao_funnel_out: endpoint { 2954 remote-endpoint = <&etf_in>; 2955 }; 2956 }; 2957 }; 2958 2959 in-ports { 2960 #address-cells = <1>; 2961 #size-cells = <0>; 2962 2963 port@7 { 2964 reg = <7>; 2965 swao_funnel_in: endpoint { 2966 remote-endpoint = <&merge_funnel_out>; 2967 }; 2968 }; 2969 }; 2970 }; 2971 2972 etf@6b05000 { 2973 compatible = "arm,coresight-tmc", "arm,primecell"; 2974 reg = <0 0x06b05000 0 0x1000>; 2975 2976 clocks = <&aoss_qmp>; 2977 clock-names = "apb_pclk"; 2978 2979 out-ports { 2980 port { 2981 etf_out: endpoint { 2982 remote-endpoint = <&swao_replicator_in>; 2983 }; 2984 }; 2985 }; 2986 2987 in-ports { 2988 port { 2989 etf_in: endpoint { 2990 remote-endpoint = <&swao_funnel_out>; 2991 }; 2992 }; 2993 }; 2994 }; 2995 2996 replicator@6b06000 { 2997 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2998 reg = <0 0x06b06000 0 0x1000>; 2999 3000 clocks = <&aoss_qmp>; 3001 clock-names = "apb_pclk"; 3002 qcom,replicator-loses-context; 3003 3004 out-ports { 3005 port { 3006 swao_replicator_out: endpoint { 3007 remote-endpoint = <&replicator_in>; 3008 }; 3009 }; 3010 }; 3011 3012 in-ports { 3013 port { 3014 swao_replicator_in: endpoint { 3015 remote-endpoint = <&etf_out>; 3016 }; 3017 }; 3018 }; 3019 }; 3020 3021 etm@7040000 { 3022 compatible = "arm,coresight-etm4x", "arm,primecell"; 3023 reg = <0 0x07040000 0 0x1000>; 3024 3025 cpu = <&CPU0>; 3026 3027 clocks = <&aoss_qmp>; 3028 clock-names = "apb_pclk"; 3029 arm,coresight-loses-context-with-cpu; 3030 qcom,skip-power-up; 3031 3032 out-ports { 3033 port { 3034 etm0_out: endpoint { 3035 remote-endpoint = <&apss_funnel_in0>; 3036 }; 3037 }; 3038 }; 3039 }; 3040 3041 etm@7140000 { 3042 compatible = "arm,coresight-etm4x", "arm,primecell"; 3043 reg = <0 0x07140000 0 0x1000>; 3044 3045 cpu = <&CPU1>; 3046 3047 clocks = <&aoss_qmp>; 3048 clock-names = "apb_pclk"; 3049 arm,coresight-loses-context-with-cpu; 3050 qcom,skip-power-up; 3051 3052 out-ports { 3053 port { 3054 etm1_out: endpoint { 3055 remote-endpoint = <&apss_funnel_in1>; 3056 }; 3057 }; 3058 }; 3059 }; 3060 3061 etm@7240000 { 3062 compatible = "arm,coresight-etm4x", "arm,primecell"; 3063 reg = <0 0x07240000 0 0x1000>; 3064 3065 cpu = <&CPU2>; 3066 3067 clocks = <&aoss_qmp>; 3068 clock-names = "apb_pclk"; 3069 arm,coresight-loses-context-with-cpu; 3070 qcom,skip-power-up; 3071 3072 out-ports { 3073 port { 3074 etm2_out: endpoint { 3075 remote-endpoint = <&apss_funnel_in2>; 3076 }; 3077 }; 3078 }; 3079 }; 3080 3081 etm@7340000 { 3082 compatible = "arm,coresight-etm4x", "arm,primecell"; 3083 reg = <0 0x07340000 0 0x1000>; 3084 3085 cpu = <&CPU3>; 3086 3087 clocks = <&aoss_qmp>; 3088 clock-names = "apb_pclk"; 3089 arm,coresight-loses-context-with-cpu; 3090 qcom,skip-power-up; 3091 3092 out-ports { 3093 port { 3094 etm3_out: endpoint { 3095 remote-endpoint = <&apss_funnel_in3>; 3096 }; 3097 }; 3098 }; 3099 }; 3100 3101 etm@7440000 { 3102 compatible = "arm,coresight-etm4x", "arm,primecell"; 3103 reg = <0 0x07440000 0 0x1000>; 3104 3105 cpu = <&CPU4>; 3106 3107 clocks = <&aoss_qmp>; 3108 clock-names = "apb_pclk"; 3109 arm,coresight-loses-context-with-cpu; 3110 qcom,skip-power-up; 3111 3112 out-ports { 3113 port { 3114 etm4_out: endpoint { 3115 remote-endpoint = <&apss_funnel_in4>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 etm@7540000 { 3122 compatible = "arm,coresight-etm4x", "arm,primecell"; 3123 reg = <0 0x07540000 0 0x1000>; 3124 3125 cpu = <&CPU5>; 3126 3127 clocks = <&aoss_qmp>; 3128 clock-names = "apb_pclk"; 3129 arm,coresight-loses-context-with-cpu; 3130 qcom,skip-power-up; 3131 3132 out-ports { 3133 port { 3134 etm5_out: endpoint { 3135 remote-endpoint = <&apss_funnel_in5>; 3136 }; 3137 }; 3138 }; 3139 }; 3140 3141 etm@7640000 { 3142 compatible = "arm,coresight-etm4x", "arm,primecell"; 3143 reg = <0 0x07640000 0 0x1000>; 3144 3145 cpu = <&CPU6>; 3146 3147 clocks = <&aoss_qmp>; 3148 clock-names = "apb_pclk"; 3149 arm,coresight-loses-context-with-cpu; 3150 qcom,skip-power-up; 3151 3152 out-ports { 3153 port { 3154 etm6_out: endpoint { 3155 remote-endpoint = <&apss_funnel_in6>; 3156 }; 3157 }; 3158 }; 3159 }; 3160 3161 etm@7740000 { 3162 compatible = "arm,coresight-etm4x", "arm,primecell"; 3163 reg = <0 0x07740000 0 0x1000>; 3164 3165 cpu = <&CPU7>; 3166 3167 clocks = <&aoss_qmp>; 3168 clock-names = "apb_pclk"; 3169 arm,coresight-loses-context-with-cpu; 3170 qcom,skip-power-up; 3171 3172 out-ports { 3173 port { 3174 etm7_out: endpoint { 3175 remote-endpoint = <&apss_funnel_in7>; 3176 }; 3177 }; 3178 }; 3179 }; 3180 3181 funnel@7800000 { /* APSS Funnel */ 3182 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3183 reg = <0 0x07800000 0 0x1000>; 3184 3185 clocks = <&aoss_qmp>; 3186 clock-names = "apb_pclk"; 3187 3188 out-ports { 3189 port { 3190 apss_funnel_out: endpoint { 3191 remote-endpoint = <&apss_merge_funnel_in>; 3192 }; 3193 }; 3194 }; 3195 3196 in-ports { 3197 #address-cells = <1>; 3198 #size-cells = <0>; 3199 3200 port@0 { 3201 reg = <0>; 3202 apss_funnel_in0: endpoint { 3203 remote-endpoint = <&etm0_out>; 3204 }; 3205 }; 3206 3207 port@1 { 3208 reg = <1>; 3209 apss_funnel_in1: endpoint { 3210 remote-endpoint = <&etm1_out>; 3211 }; 3212 }; 3213 3214 port@2 { 3215 reg = <2>; 3216 apss_funnel_in2: endpoint { 3217 remote-endpoint = <&etm2_out>; 3218 }; 3219 }; 3220 3221 port@3 { 3222 reg = <3>; 3223 apss_funnel_in3: endpoint { 3224 remote-endpoint = <&etm3_out>; 3225 }; 3226 }; 3227 3228 port@4 { 3229 reg = <4>; 3230 apss_funnel_in4: endpoint { 3231 remote-endpoint = <&etm4_out>; 3232 }; 3233 }; 3234 3235 port@5 { 3236 reg = <5>; 3237 apss_funnel_in5: endpoint { 3238 remote-endpoint = <&etm5_out>; 3239 }; 3240 }; 3241 3242 port@6 { 3243 reg = <6>; 3244 apss_funnel_in6: endpoint { 3245 remote-endpoint = <&etm6_out>; 3246 }; 3247 }; 3248 3249 port@7 { 3250 reg = <7>; 3251 apss_funnel_in7: endpoint { 3252 remote-endpoint = <&etm7_out>; 3253 }; 3254 }; 3255 }; 3256 }; 3257 3258 funnel@7810000 { 3259 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3260 reg = <0 0x07810000 0 0x1000>; 3261 3262 clocks = <&aoss_qmp>; 3263 clock-names = "apb_pclk"; 3264 3265 out-ports { 3266 port { 3267 apss_merge_funnel_out: endpoint { 3268 remote-endpoint = <&funnel1_in4>; 3269 }; 3270 }; 3271 }; 3272 3273 in-ports { 3274 port { 3275 apss_merge_funnel_in: endpoint { 3276 remote-endpoint = <&apss_funnel_out>; 3277 }; 3278 }; 3279 }; 3280 }; 3281 3282 sdhc_2: mmc@8804000 { 3283 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3284 pinctrl-names = "default", "sleep"; 3285 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3286 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3287 status = "disabled"; 3288 3289 reg = <0 0x08804000 0 0x1000>; 3290 3291 iommus = <&apps_smmu 0x100 0x0>; 3292 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3294 interrupt-names = "hc_irq", "pwr_irq"; 3295 3296 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3297 <&gcc GCC_SDCC2_APPS_CLK>, 3298 <&rpmhcc RPMH_CXO_CLK>; 3299 clock-names = "iface", "core", "xo"; 3300 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3301 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3302 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3303 power-domains = <&rpmhpd SC7280_CX>; 3304 operating-points-v2 = <&sdhc2_opp_table>; 3305 3306 bus-width = <4>; 3307 3308 qcom,dll-config = <0x0007642c>; 3309 3310 resets = <&gcc GCC_SDCC2_BCR>; 3311 3312 sdhc2_opp_table: opp-table { 3313 compatible = "operating-points-v2"; 3314 3315 opp-100000000 { 3316 opp-hz = /bits/ 64 <100000000>; 3317 required-opps = <&rpmhpd_opp_low_svs>; 3318 opp-peak-kBps = <1800000 400000>; 3319 opp-avg-kBps = <100000 0>; 3320 }; 3321 3322 opp-202000000 { 3323 opp-hz = /bits/ 64 <202000000>; 3324 required-opps = <&rpmhpd_opp_nom>; 3325 opp-peak-kBps = <5400000 1600000>; 3326 opp-avg-kBps = <200000 0>; 3327 }; 3328 }; 3329 3330 }; 3331 3332 usb_1_hsphy: phy@88e3000 { 3333 compatible = "qcom,sc7280-usb-hs-phy", 3334 "qcom,usb-snps-hs-7nm-phy"; 3335 reg = <0 0x088e3000 0 0x400>; 3336 status = "disabled"; 3337 #phy-cells = <0>; 3338 3339 clocks = <&rpmhcc RPMH_CXO_CLK>; 3340 clock-names = "ref"; 3341 3342 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3343 }; 3344 3345 usb_2_hsphy: phy@88e4000 { 3346 compatible = "qcom,sc7280-usb-hs-phy", 3347 "qcom,usb-snps-hs-7nm-phy"; 3348 reg = <0 0x088e4000 0 0x400>; 3349 status = "disabled"; 3350 #phy-cells = <0>; 3351 3352 clocks = <&rpmhcc RPMH_CXO_CLK>; 3353 clock-names = "ref"; 3354 3355 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3356 }; 3357 3358 usb_1_qmpphy: phy-wrapper@88e9000 { 3359 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3360 "qcom,sm8250-qmp-usb3-dp-phy"; 3361 reg = <0 0x088e9000 0 0x200>, 3362 <0 0x088e8000 0 0x40>, 3363 <0 0x088ea000 0 0x200>; 3364 status = "disabled"; 3365 #address-cells = <2>; 3366 #size-cells = <2>; 3367 ranges; 3368 3369 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3370 <&rpmhcc RPMH_CXO_CLK>, 3371 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3372 clock-names = "aux", "ref_clk_src", "com_aux"; 3373 3374 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3375 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3376 reset-names = "phy", "common"; 3377 3378 usb_1_ssphy: usb3-phy@88e9200 { 3379 reg = <0 0x088e9200 0 0x200>, 3380 <0 0x088e9400 0 0x200>, 3381 <0 0x088e9c00 0 0x400>, 3382 <0 0x088e9600 0 0x200>, 3383 <0 0x088e9800 0 0x200>, 3384 <0 0x088e9a00 0 0x100>; 3385 #clock-cells = <0>; 3386 #phy-cells = <0>; 3387 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3388 clock-names = "pipe0"; 3389 clock-output-names = "usb3_phy_pipe_clk_src"; 3390 }; 3391 3392 dp_phy: dp-phy@88ea200 { 3393 reg = <0 0x088ea200 0 0x200>, 3394 <0 0x088ea400 0 0x200>, 3395 <0 0x088eaa00 0 0x200>, 3396 <0 0x088ea600 0 0x200>, 3397 <0 0x088ea800 0 0x200>; 3398 #phy-cells = <0>; 3399 #clock-cells = <1>; 3400 }; 3401 }; 3402 3403 usb_2: usb@8cf8800 { 3404 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3405 reg = <0 0x08cf8800 0 0x400>; 3406 status = "disabled"; 3407 #address-cells = <2>; 3408 #size-cells = <2>; 3409 ranges; 3410 dma-ranges; 3411 3412 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3413 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3414 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3415 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3416 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3417 clock-names = "cfg_noc", 3418 "core", 3419 "iface", 3420 "sleep", 3421 "mock_utmi"; 3422 3423 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3424 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3425 assigned-clock-rates = <19200000>, <200000000>; 3426 3427 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3428 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3429 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3430 interrupt-names = "hs_phy_irq", 3431 "dp_hs_phy_irq", 3432 "dm_hs_phy_irq"; 3433 3434 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3435 required-opps = <&rpmhpd_opp_nom>; 3436 3437 resets = <&gcc GCC_USB30_SEC_BCR>; 3438 3439 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3440 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3441 interconnect-names = "usb-ddr", "apps-usb"; 3442 3443 usb_2_dwc3: usb@8c00000 { 3444 compatible = "snps,dwc3"; 3445 reg = <0 0x08c00000 0 0xe000>; 3446 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3447 iommus = <&apps_smmu 0xa0 0x0>; 3448 snps,dis_u2_susphy_quirk; 3449 snps,dis_enblslpm_quirk; 3450 phys = <&usb_2_hsphy>; 3451 phy-names = "usb2-phy"; 3452 maximum-speed = "high-speed"; 3453 usb-role-switch; 3454 port { 3455 usb2_role_switch: endpoint { 3456 remote-endpoint = <&eud_ep>; 3457 }; 3458 }; 3459 }; 3460 }; 3461 3462 qspi: spi@88dc000 { 3463 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3464 reg = <0 0x088dc000 0 0x1000>; 3465 #address-cells = <1>; 3466 #size-cells = <0>; 3467 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3468 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3469 <&gcc GCC_QSPI_CORE_CLK>; 3470 clock-names = "iface", "core"; 3471 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3472 &cnoc2 SLAVE_QSPI_0 0>; 3473 interconnect-names = "qspi-config"; 3474 power-domains = <&rpmhpd SC7280_CX>; 3475 operating-points-v2 = <&qspi_opp_table>; 3476 status = "disabled"; 3477 }; 3478 3479 remoteproc_wpss: remoteproc@8a00000 { 3480 compatible = "qcom,sc7280-wpss-pil"; 3481 reg = <0 0x08a00000 0 0x10000>; 3482 3483 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3484 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3485 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3486 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3487 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3488 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3489 interrupt-names = "wdog", "fatal", "ready", "handover", 3490 "stop-ack", "shutdown-ack"; 3491 3492 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3493 <&gcc GCC_WPSS_AHB_CLK>, 3494 <&gcc GCC_WPSS_RSCP_CLK>, 3495 <&rpmhcc RPMH_CXO_CLK>; 3496 clock-names = "ahb_bdg", "ahb", 3497 "rscp", "xo"; 3498 3499 power-domains = <&rpmhpd SC7280_CX>, 3500 <&rpmhpd SC7280_MX>; 3501 power-domain-names = "cx", "mx"; 3502 3503 memory-region = <&wpss_mem>; 3504 3505 qcom,qmp = <&aoss_qmp>; 3506 3507 qcom,smem-states = <&wpss_smp2p_out 0>; 3508 qcom,smem-state-names = "stop"; 3509 3510 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3511 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3512 reset-names = "restart", "pdc_sync"; 3513 3514 qcom,halt-regs = <&tcsr_1 0x17000>; 3515 3516 status = "disabled"; 3517 3518 glink-edge { 3519 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3520 IPCC_MPROC_SIGNAL_GLINK_QMP 3521 IRQ_TYPE_EDGE_RISING>; 3522 mboxes = <&ipcc IPCC_CLIENT_WPSS 3523 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3524 3525 label = "wpss"; 3526 qcom,remote-pid = <13>; 3527 }; 3528 }; 3529 3530 pmu@9091000 { 3531 compatible = "qcom,sc7280-llcc-bwmon"; 3532 reg = <0 0x9091000 0 0x1000>; 3533 3534 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3535 3536 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3537 3538 operating-points-v2 = <&llcc_bwmon_opp_table>; 3539 3540 llcc_bwmon_opp_table: opp-table { 3541 compatible = "operating-points-v2"; 3542 3543 opp-0 { 3544 opp-peak-kBps = <800000>; 3545 }; 3546 opp-1 { 3547 opp-peak-kBps = <1804000>; 3548 }; 3549 opp-2 { 3550 opp-peak-kBps = <2188000>; 3551 }; 3552 opp-3 { 3553 opp-peak-kBps = <3072000>; 3554 }; 3555 opp-4 { 3556 opp-peak-kBps = <4068000>; 3557 }; 3558 opp-5 { 3559 opp-peak-kBps = <6220000>; 3560 }; 3561 opp-6 { 3562 opp-peak-kBps = <6832000>; 3563 }; 3564 opp-7 { 3565 opp-peak-kBps = <8532000>; 3566 }; 3567 }; 3568 }; 3569 3570 pmu@90b6400 { 3571 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3572 reg = <0 0x090b6400 0 0x600>; 3573 3574 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3575 3576 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3577 operating-points-v2 = <&cpu_bwmon_opp_table>; 3578 3579 cpu_bwmon_opp_table: opp-table { 3580 compatible = "operating-points-v2"; 3581 3582 opp-0 { 3583 opp-peak-kBps = <2400000>; 3584 }; 3585 opp-1 { 3586 opp-peak-kBps = <4800000>; 3587 }; 3588 opp-2 { 3589 opp-peak-kBps = <7456000>; 3590 }; 3591 opp-3 { 3592 opp-peak-kBps = <9600000>; 3593 }; 3594 opp-4 { 3595 opp-peak-kBps = <12896000>; 3596 }; 3597 opp-5 { 3598 opp-peak-kBps = <14928000>; 3599 }; 3600 opp-6 { 3601 opp-peak-kBps = <17056000>; 3602 }; 3603 }; 3604 }; 3605 3606 dc_noc: interconnect@90e0000 { 3607 reg = <0 0x090e0000 0 0x5080>; 3608 compatible = "qcom,sc7280-dc-noc"; 3609 #interconnect-cells = <2>; 3610 qcom,bcm-voters = <&apps_bcm_voter>; 3611 }; 3612 3613 gem_noc: interconnect@9100000 { 3614 reg = <0 0x9100000 0 0xe2200>; 3615 compatible = "qcom,sc7280-gem-noc"; 3616 #interconnect-cells = <2>; 3617 qcom,bcm-voters = <&apps_bcm_voter>; 3618 }; 3619 3620 system-cache-controller@9200000 { 3621 compatible = "qcom,sc7280-llcc"; 3622 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3623 reg-names = "llcc_base", "llcc_broadcast_base"; 3624 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3625 }; 3626 3627 eud: eud@88e0000 { 3628 compatible = "qcom,sc7280-eud","qcom,eud"; 3629 reg = <0 0x88e0000 0 0x2000>, 3630 <0 0x88e2000 0 0x1000>; 3631 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3632 ports { 3633 port@0 { 3634 eud_ep: endpoint { 3635 remote-endpoint = <&usb2_role_switch>; 3636 }; 3637 }; 3638 port@1 { 3639 eud_con: endpoint { 3640 remote-endpoint = <&con_eud>; 3641 }; 3642 }; 3643 }; 3644 }; 3645 3646 eud_typec: connector { 3647 compatible = "usb-c-connector"; 3648 ports { 3649 port@0 { 3650 con_eud: endpoint { 3651 remote-endpoint = <&eud_con>; 3652 }; 3653 }; 3654 }; 3655 }; 3656 3657 nsp_noc: interconnect@a0c0000 { 3658 reg = <0 0x0a0c0000 0 0x10000>; 3659 compatible = "qcom,sc7280-nsp-noc"; 3660 #interconnect-cells = <2>; 3661 qcom,bcm-voters = <&apps_bcm_voter>; 3662 }; 3663 3664 usb_1: usb@a6f8800 { 3665 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3666 reg = <0 0x0a6f8800 0 0x400>; 3667 status = "disabled"; 3668 #address-cells = <2>; 3669 #size-cells = <2>; 3670 ranges; 3671 dma-ranges; 3672 3673 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3674 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3675 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3676 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3677 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3678 clock-names = "cfg_noc", 3679 "core", 3680 "iface", 3681 "sleep", 3682 "mock_utmi"; 3683 3684 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3685 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3686 assigned-clock-rates = <19200000>, <200000000>; 3687 3688 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3689 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3690 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3691 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3692 interrupt-names = "hs_phy_irq", 3693 "dp_hs_phy_irq", 3694 "dm_hs_phy_irq", 3695 "ss_phy_irq"; 3696 3697 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3698 required-opps = <&rpmhpd_opp_nom>; 3699 3700 resets = <&gcc GCC_USB30_PRIM_BCR>; 3701 3702 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3703 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3704 interconnect-names = "usb-ddr", "apps-usb"; 3705 3706 wakeup-source; 3707 3708 usb_1_dwc3: usb@a600000 { 3709 compatible = "snps,dwc3"; 3710 reg = <0 0x0a600000 0 0xe000>; 3711 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3712 iommus = <&apps_smmu 0xe0 0x0>; 3713 snps,dis_u2_susphy_quirk; 3714 snps,dis_enblslpm_quirk; 3715 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3716 phy-names = "usb2-phy", "usb3-phy"; 3717 maximum-speed = "super-speed"; 3718 }; 3719 }; 3720 3721 venus: video-codec@aa00000 { 3722 compatible = "qcom,sc7280-venus"; 3723 reg = <0 0x0aa00000 0 0xd0600>; 3724 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3725 3726 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3727 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3728 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3729 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3730 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3731 clock-names = "core", "bus", "iface", 3732 "vcodec_core", "vcodec_bus"; 3733 3734 power-domains = <&videocc MVSC_GDSC>, 3735 <&videocc MVS0_GDSC>, 3736 <&rpmhpd SC7280_CX>; 3737 power-domain-names = "venus", "vcodec0", "cx"; 3738 operating-points-v2 = <&venus_opp_table>; 3739 3740 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3741 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3742 interconnect-names = "cpu-cfg", "video-mem"; 3743 3744 iommus = <&apps_smmu 0x2180 0x20>, 3745 <&apps_smmu 0x2184 0x20>; 3746 memory-region = <&video_mem>; 3747 3748 video-decoder { 3749 compatible = "venus-decoder"; 3750 }; 3751 3752 video-encoder { 3753 compatible = "venus-encoder"; 3754 }; 3755 3756 video-firmware { 3757 iommus = <&apps_smmu 0x21a2 0x0>; 3758 }; 3759 3760 venus_opp_table: opp-table { 3761 compatible = "operating-points-v2"; 3762 3763 opp-133330000 { 3764 opp-hz = /bits/ 64 <133330000>; 3765 required-opps = <&rpmhpd_opp_low_svs>; 3766 }; 3767 3768 opp-240000000 { 3769 opp-hz = /bits/ 64 <240000000>; 3770 required-opps = <&rpmhpd_opp_svs>; 3771 }; 3772 3773 opp-335000000 { 3774 opp-hz = /bits/ 64 <335000000>; 3775 required-opps = <&rpmhpd_opp_svs_l1>; 3776 }; 3777 3778 opp-424000000 { 3779 opp-hz = /bits/ 64 <424000000>; 3780 required-opps = <&rpmhpd_opp_nom>; 3781 }; 3782 3783 opp-460000048 { 3784 opp-hz = /bits/ 64 <460000048>; 3785 required-opps = <&rpmhpd_opp_turbo>; 3786 }; 3787 }; 3788 3789 }; 3790 3791 videocc: clock-controller@aaf0000 { 3792 compatible = "qcom,sc7280-videocc"; 3793 reg = <0 0xaaf0000 0 0x10000>; 3794 clocks = <&rpmhcc RPMH_CXO_CLK>, 3795 <&rpmhcc RPMH_CXO_CLK_A>; 3796 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3797 #clock-cells = <1>; 3798 #reset-cells = <1>; 3799 #power-domain-cells = <1>; 3800 }; 3801 3802 camcc: clock-controller@ad00000 { 3803 compatible = "qcom,sc7280-camcc"; 3804 reg = <0 0x0ad00000 0 0x10000>; 3805 clocks = <&rpmhcc RPMH_CXO_CLK>, 3806 <&rpmhcc RPMH_CXO_CLK_A>, 3807 <&sleep_clk>; 3808 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3809 #clock-cells = <1>; 3810 #reset-cells = <1>; 3811 #power-domain-cells = <1>; 3812 }; 3813 3814 dispcc: clock-controller@af00000 { 3815 compatible = "qcom,sc7280-dispcc"; 3816 reg = <0 0xaf00000 0 0x20000>; 3817 clocks = <&rpmhcc RPMH_CXO_CLK>, 3818 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3819 <&mdss_dsi_phy 0>, 3820 <&mdss_dsi_phy 1>, 3821 <&dp_phy 0>, 3822 <&dp_phy 1>, 3823 <&mdss_edp_phy 0>, 3824 <&mdss_edp_phy 1>; 3825 clock-names = "bi_tcxo", 3826 "gcc_disp_gpll0_clk", 3827 "dsi0_phy_pll_out_byteclk", 3828 "dsi0_phy_pll_out_dsiclk", 3829 "dp_phy_pll_link_clk", 3830 "dp_phy_pll_vco_div_clk", 3831 "edp_phy_pll_link_clk", 3832 "edp_phy_pll_vco_div_clk"; 3833 #clock-cells = <1>; 3834 #reset-cells = <1>; 3835 #power-domain-cells = <1>; 3836 }; 3837 3838 mdss: display-subsystem@ae00000 { 3839 compatible = "qcom,sc7280-mdss"; 3840 reg = <0 0x0ae00000 0 0x1000>; 3841 reg-names = "mdss"; 3842 3843 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3844 3845 clocks = <&gcc GCC_DISP_AHB_CLK>, 3846 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3847 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3848 clock-names = "iface", 3849 "ahb", 3850 "core"; 3851 3852 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3853 interrupt-controller; 3854 #interrupt-cells = <1>; 3855 3856 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3857 interconnect-names = "mdp0-mem"; 3858 3859 iommus = <&apps_smmu 0x900 0x402>; 3860 3861 #address-cells = <2>; 3862 #size-cells = <2>; 3863 ranges; 3864 3865 status = "disabled"; 3866 3867 mdss_mdp: display-controller@ae01000 { 3868 compatible = "qcom,sc7280-dpu"; 3869 reg = <0 0x0ae01000 0 0x8f030>, 3870 <0 0x0aeb0000 0 0x2008>; 3871 reg-names = "mdp", "vbif"; 3872 3873 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3874 <&gcc GCC_DISP_SF_AXI_CLK>, 3875 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3876 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3877 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3878 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3879 clock-names = "bus", 3880 "nrt_bus", 3881 "iface", 3882 "lut", 3883 "core", 3884 "vsync"; 3885 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3886 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3887 assigned-clock-rates = <19200000>, 3888 <19200000>; 3889 operating-points-v2 = <&mdp_opp_table>; 3890 power-domains = <&rpmhpd SC7280_CX>; 3891 3892 interrupt-parent = <&mdss>; 3893 interrupts = <0>; 3894 3895 status = "disabled"; 3896 3897 ports { 3898 #address-cells = <1>; 3899 #size-cells = <0>; 3900 3901 port@0 { 3902 reg = <0>; 3903 dpu_intf1_out: endpoint { 3904 remote-endpoint = <&dsi0_in>; 3905 }; 3906 }; 3907 3908 port@1 { 3909 reg = <1>; 3910 dpu_intf5_out: endpoint { 3911 remote-endpoint = <&edp_in>; 3912 }; 3913 }; 3914 3915 port@2 { 3916 reg = <2>; 3917 dpu_intf0_out: endpoint { 3918 remote-endpoint = <&dp_in>; 3919 }; 3920 }; 3921 }; 3922 3923 mdp_opp_table: opp-table { 3924 compatible = "operating-points-v2"; 3925 3926 opp-200000000 { 3927 opp-hz = /bits/ 64 <200000000>; 3928 required-opps = <&rpmhpd_opp_low_svs>; 3929 }; 3930 3931 opp-300000000 { 3932 opp-hz = /bits/ 64 <300000000>; 3933 required-opps = <&rpmhpd_opp_svs>; 3934 }; 3935 3936 opp-380000000 { 3937 opp-hz = /bits/ 64 <380000000>; 3938 required-opps = <&rpmhpd_opp_svs_l1>; 3939 }; 3940 3941 opp-506666667 { 3942 opp-hz = /bits/ 64 <506666667>; 3943 required-opps = <&rpmhpd_opp_nom>; 3944 }; 3945 }; 3946 }; 3947 3948 mdss_dsi: dsi@ae94000 { 3949 compatible = "qcom,mdss-dsi-ctrl"; 3950 reg = <0 0x0ae94000 0 0x400>; 3951 reg-names = "dsi_ctrl"; 3952 3953 interrupt-parent = <&mdss>; 3954 interrupts = <4>; 3955 3956 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3957 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3958 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3959 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3960 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3961 <&gcc GCC_DISP_HF_AXI_CLK>; 3962 clock-names = "byte", 3963 "byte_intf", 3964 "pixel", 3965 "core", 3966 "iface", 3967 "bus"; 3968 3969 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3970 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3971 3972 operating-points-v2 = <&dsi_opp_table>; 3973 power-domains = <&rpmhpd SC7280_CX>; 3974 3975 phys = <&mdss_dsi_phy>; 3976 3977 #address-cells = <1>; 3978 #size-cells = <0>; 3979 3980 status = "disabled"; 3981 3982 ports { 3983 #address-cells = <1>; 3984 #size-cells = <0>; 3985 3986 port@0 { 3987 reg = <0>; 3988 dsi0_in: endpoint { 3989 remote-endpoint = <&dpu_intf1_out>; 3990 }; 3991 }; 3992 3993 port@1 { 3994 reg = <1>; 3995 dsi0_out: endpoint { 3996 }; 3997 }; 3998 }; 3999 4000 dsi_opp_table: opp-table { 4001 compatible = "operating-points-v2"; 4002 4003 opp-187500000 { 4004 opp-hz = /bits/ 64 <187500000>; 4005 required-opps = <&rpmhpd_opp_low_svs>; 4006 }; 4007 4008 opp-300000000 { 4009 opp-hz = /bits/ 64 <300000000>; 4010 required-opps = <&rpmhpd_opp_svs>; 4011 }; 4012 4013 opp-358000000 { 4014 opp-hz = /bits/ 64 <358000000>; 4015 required-opps = <&rpmhpd_opp_svs_l1>; 4016 }; 4017 }; 4018 }; 4019 4020 mdss_dsi_phy: phy@ae94400 { 4021 compatible = "qcom,sc7280-dsi-phy-7nm"; 4022 reg = <0 0x0ae94400 0 0x200>, 4023 <0 0x0ae94600 0 0x280>, 4024 <0 0x0ae94900 0 0x280>; 4025 reg-names = "dsi_phy", 4026 "dsi_phy_lane", 4027 "dsi_pll"; 4028 4029 #clock-cells = <1>; 4030 #phy-cells = <0>; 4031 4032 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4033 <&rpmhcc RPMH_CXO_CLK>; 4034 clock-names = "iface", "ref"; 4035 4036 status = "disabled"; 4037 }; 4038 4039 mdss_edp: edp@aea0000 { 4040 compatible = "qcom,sc7280-edp"; 4041 pinctrl-names = "default"; 4042 pinctrl-0 = <&edp_hot_plug_det>; 4043 4044 reg = <0 0xaea0000 0 0x200>, 4045 <0 0xaea0200 0 0x200>, 4046 <0 0xaea0400 0 0xc00>, 4047 <0 0xaea1000 0 0x400>; 4048 4049 interrupt-parent = <&mdss>; 4050 interrupts = <14>; 4051 4052 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4053 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4054 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4055 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4056 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4057 clock-names = "core_iface", 4058 "core_aux", 4059 "ctrl_link", 4060 "ctrl_link_iface", 4061 "stream_pixel"; 4062 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4063 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4064 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4065 4066 phys = <&mdss_edp_phy>; 4067 phy-names = "dp"; 4068 4069 operating-points-v2 = <&edp_opp_table>; 4070 power-domains = <&rpmhpd SC7280_CX>; 4071 4072 status = "disabled"; 4073 4074 ports { 4075 #address-cells = <1>; 4076 #size-cells = <0>; 4077 4078 port@0 { 4079 reg = <0>; 4080 edp_in: endpoint { 4081 remote-endpoint = <&dpu_intf5_out>; 4082 }; 4083 }; 4084 4085 port@1 { 4086 reg = <1>; 4087 mdss_edp_out: endpoint { }; 4088 }; 4089 }; 4090 4091 edp_opp_table: opp-table { 4092 compatible = "operating-points-v2"; 4093 4094 opp-160000000 { 4095 opp-hz = /bits/ 64 <160000000>; 4096 required-opps = <&rpmhpd_opp_low_svs>; 4097 }; 4098 4099 opp-270000000 { 4100 opp-hz = /bits/ 64 <270000000>; 4101 required-opps = <&rpmhpd_opp_svs>; 4102 }; 4103 4104 opp-540000000 { 4105 opp-hz = /bits/ 64 <540000000>; 4106 required-opps = <&rpmhpd_opp_nom>; 4107 }; 4108 4109 opp-810000000 { 4110 opp-hz = /bits/ 64 <810000000>; 4111 required-opps = <&rpmhpd_opp_nom>; 4112 }; 4113 }; 4114 }; 4115 4116 mdss_edp_phy: phy@aec2a00 { 4117 compatible = "qcom,sc7280-edp-phy"; 4118 4119 reg = <0 0xaec2a00 0 0x19c>, 4120 <0 0xaec2200 0 0xa0>, 4121 <0 0xaec2600 0 0xa0>, 4122 <0 0xaec2000 0 0x1c0>; 4123 4124 clocks = <&rpmhcc RPMH_CXO_CLK>, 4125 <&gcc GCC_EDP_CLKREF_EN>; 4126 clock-names = "aux", 4127 "cfg_ahb"; 4128 4129 #clock-cells = <1>; 4130 #phy-cells = <0>; 4131 4132 status = "disabled"; 4133 }; 4134 4135 mdss_dp: displayport-controller@ae90000 { 4136 compatible = "qcom,sc7280-dp"; 4137 4138 reg = <0 0xae90000 0 0x200>, 4139 <0 0xae90200 0 0x200>, 4140 <0 0xae90400 0 0xc00>, 4141 <0 0xae91000 0 0x400>, 4142 <0 0xae91400 0 0x400>; 4143 4144 interrupt-parent = <&mdss>; 4145 interrupts = <12>; 4146 4147 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4148 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4149 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4150 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4151 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4152 clock-names = "core_iface", 4153 "core_aux", 4154 "ctrl_link", 4155 "ctrl_link_iface", 4156 "stream_pixel"; 4157 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4158 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4159 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4160 phys = <&dp_phy>; 4161 phy-names = "dp"; 4162 4163 operating-points-v2 = <&dp_opp_table>; 4164 power-domains = <&rpmhpd SC7280_CX>; 4165 4166 #sound-dai-cells = <0>; 4167 4168 status = "disabled"; 4169 4170 ports { 4171 #address-cells = <1>; 4172 #size-cells = <0>; 4173 4174 port@0 { 4175 reg = <0>; 4176 dp_in: endpoint { 4177 remote-endpoint = <&dpu_intf0_out>; 4178 }; 4179 }; 4180 4181 port@1 { 4182 reg = <1>; 4183 dp_out: endpoint { }; 4184 }; 4185 }; 4186 4187 dp_opp_table: opp-table { 4188 compatible = "operating-points-v2"; 4189 4190 opp-160000000 { 4191 opp-hz = /bits/ 64 <160000000>; 4192 required-opps = <&rpmhpd_opp_low_svs>; 4193 }; 4194 4195 opp-270000000 { 4196 opp-hz = /bits/ 64 <270000000>; 4197 required-opps = <&rpmhpd_opp_svs>; 4198 }; 4199 4200 opp-540000000 { 4201 opp-hz = /bits/ 64 <540000000>; 4202 required-opps = <&rpmhpd_opp_svs_l1>; 4203 }; 4204 4205 opp-810000000 { 4206 opp-hz = /bits/ 64 <810000000>; 4207 required-opps = <&rpmhpd_opp_nom>; 4208 }; 4209 }; 4210 }; 4211 }; 4212 4213 pdc: interrupt-controller@b220000 { 4214 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4215 reg = <0 0x0b220000 0 0x30000>; 4216 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4217 <55 306 4>, <59 312 3>, <62 374 2>, 4218 <64 434 2>, <66 438 3>, <69 86 1>, 4219 <70 520 54>, <124 609 31>, <155 63 1>, 4220 <156 716 12>; 4221 #interrupt-cells = <2>; 4222 interrupt-parent = <&intc>; 4223 interrupt-controller; 4224 }; 4225 4226 pdc_reset: reset-controller@b5e0000 { 4227 compatible = "qcom,sc7280-pdc-global"; 4228 reg = <0 0x0b5e0000 0 0x20000>; 4229 #reset-cells = <1>; 4230 }; 4231 4232 tsens0: thermal-sensor@c263000 { 4233 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4234 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4235 <0 0x0c222000 0 0x1ff>; /* SROT */ 4236 #qcom,sensors = <15>; 4237 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4239 interrupt-names = "uplow","critical"; 4240 #thermal-sensor-cells = <1>; 4241 }; 4242 4243 tsens1: thermal-sensor@c265000 { 4244 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4245 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4246 <0 0x0c223000 0 0x1ff>; /* SROT */ 4247 #qcom,sensors = <12>; 4248 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4250 interrupt-names = "uplow","critical"; 4251 #thermal-sensor-cells = <1>; 4252 }; 4253 4254 aoss_reset: reset-controller@c2a0000 { 4255 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4256 reg = <0 0x0c2a0000 0 0x31000>; 4257 #reset-cells = <1>; 4258 }; 4259 4260 aoss_qmp: power-controller@c300000 { 4261 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4262 reg = <0 0x0c300000 0 0x400>; 4263 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4264 IPCC_MPROC_SIGNAL_GLINK_QMP 4265 IRQ_TYPE_EDGE_RISING>; 4266 mboxes = <&ipcc IPCC_CLIENT_AOP 4267 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4268 4269 #clock-cells = <0>; 4270 }; 4271 4272 sram@c3f0000 { 4273 compatible = "qcom,rpmh-stats"; 4274 reg = <0 0x0c3f0000 0 0x400>; 4275 }; 4276 4277 spmi_bus: spmi@c440000 { 4278 compatible = "qcom,spmi-pmic-arb"; 4279 reg = <0 0x0c440000 0 0x1100>, 4280 <0 0x0c600000 0 0x2000000>, 4281 <0 0x0e600000 0 0x100000>, 4282 <0 0x0e700000 0 0xa0000>, 4283 <0 0x0c40a000 0 0x26000>; 4284 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4285 interrupt-names = "periph_irq"; 4286 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4287 qcom,ee = <0>; 4288 qcom,channel = <0>; 4289 #address-cells = <1>; 4290 #size-cells = <1>; 4291 interrupt-controller; 4292 #interrupt-cells = <4>; 4293 }; 4294 4295 tlmm: pinctrl@f100000 { 4296 compatible = "qcom,sc7280-pinctrl"; 4297 reg = <0 0x0f100000 0 0x300000>; 4298 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4299 gpio-controller; 4300 #gpio-cells = <2>; 4301 interrupt-controller; 4302 #interrupt-cells = <2>; 4303 gpio-ranges = <&tlmm 0 0 175>; 4304 wakeup-parent = <&pdc>; 4305 4306 dp_hot_plug_det: dp-hot-plug-det-state { 4307 pins = "gpio47"; 4308 function = "dp_hot"; 4309 }; 4310 4311 edp_hot_plug_det: edp-hot-plug-det-state { 4312 pins = "gpio60"; 4313 function = "edp_hot"; 4314 }; 4315 4316 mi2s0_data0: mi2s0-data0-state { 4317 pins = "gpio98"; 4318 function = "mi2s0_data0"; 4319 }; 4320 4321 mi2s0_data1: mi2s0-data1-state { 4322 pins = "gpio99"; 4323 function = "mi2s0_data1"; 4324 }; 4325 4326 mi2s0_mclk: mi2s0-mclk-state { 4327 pins = "gpio96"; 4328 function = "pri_mi2s"; 4329 }; 4330 4331 mi2s0_sclk: mi2s0-sclk-state { 4332 pins = "gpio97"; 4333 function = "mi2s0_sck"; 4334 }; 4335 4336 mi2s0_ws: mi2s0-ws-state { 4337 pins = "gpio100"; 4338 function = "mi2s0_ws"; 4339 }; 4340 4341 mi2s1_data0: mi2s1-data0-state { 4342 pins = "gpio107"; 4343 function = "mi2s1_data0"; 4344 }; 4345 4346 mi2s1_sclk: mi2s1-sclk-state { 4347 pins = "gpio106"; 4348 function = "mi2s1_sck"; 4349 }; 4350 4351 mi2s1_ws: mi2s1-ws-state { 4352 pins = "gpio108"; 4353 function = "mi2s1_ws"; 4354 }; 4355 4356 pcie1_clkreq_n: pcie1-clkreq-n-state { 4357 pins = "gpio79"; 4358 function = "pcie1_clkreqn"; 4359 }; 4360 4361 qspi_clk: qspi-clk-state { 4362 pins = "gpio14"; 4363 function = "qspi_clk"; 4364 }; 4365 4366 qspi_cs0: qspi-cs0-state { 4367 pins = "gpio15"; 4368 function = "qspi_cs"; 4369 }; 4370 4371 qspi_cs1: qspi-cs1-state { 4372 pins = "gpio19"; 4373 function = "qspi_cs"; 4374 }; 4375 4376 qspi_data01: qspi-data01-state { 4377 pins = "gpio12", "gpio13"; 4378 function = "qspi_data"; 4379 }; 4380 4381 qspi_data12: qspi-data12-state { 4382 pins = "gpio16", "gpio17"; 4383 function = "qspi_data"; 4384 }; 4385 4386 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4387 pins = "gpio0", "gpio1"; 4388 function = "qup00"; 4389 }; 4390 4391 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4392 pins = "gpio4", "gpio5"; 4393 function = "qup01"; 4394 }; 4395 4396 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4397 pins = "gpio8", "gpio9"; 4398 function = "qup02"; 4399 }; 4400 4401 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4402 pins = "gpio12", "gpio13"; 4403 function = "qup03"; 4404 }; 4405 4406 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4407 pins = "gpio16", "gpio17"; 4408 function = "qup04"; 4409 }; 4410 4411 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4412 pins = "gpio20", "gpio21"; 4413 function = "qup05"; 4414 }; 4415 4416 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4417 pins = "gpio24", "gpio25"; 4418 function = "qup06"; 4419 }; 4420 4421 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4422 pins = "gpio28", "gpio29"; 4423 function = "qup07"; 4424 }; 4425 4426 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4427 pins = "gpio32", "gpio33"; 4428 function = "qup10"; 4429 }; 4430 4431 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4432 pins = "gpio36", "gpio37"; 4433 function = "qup11"; 4434 }; 4435 4436 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4437 pins = "gpio40", "gpio41"; 4438 function = "qup12"; 4439 }; 4440 4441 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4442 pins = "gpio44", "gpio45"; 4443 function = "qup13"; 4444 }; 4445 4446 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4447 pins = "gpio48", "gpio49"; 4448 function = "qup14"; 4449 }; 4450 4451 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4452 pins = "gpio52", "gpio53"; 4453 function = "qup15"; 4454 }; 4455 4456 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4457 pins = "gpio56", "gpio57"; 4458 function = "qup16"; 4459 }; 4460 4461 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4462 pins = "gpio60", "gpio61"; 4463 function = "qup17"; 4464 }; 4465 4466 qup_spi0_data_clk: qup-spi0-data-clk-state { 4467 pins = "gpio0", "gpio1", "gpio2"; 4468 function = "qup00"; 4469 }; 4470 4471 qup_spi0_cs: qup-spi0-cs-state { 4472 pins = "gpio3"; 4473 function = "qup00"; 4474 }; 4475 4476 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4477 pins = "gpio3"; 4478 function = "gpio"; 4479 }; 4480 4481 qup_spi1_data_clk: qup-spi1-data-clk-state { 4482 pins = "gpio4", "gpio5", "gpio6"; 4483 function = "qup01"; 4484 }; 4485 4486 qup_spi1_cs: qup-spi1-cs-state { 4487 pins = "gpio7"; 4488 function = "qup01"; 4489 }; 4490 4491 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4492 pins = "gpio7"; 4493 function = "gpio"; 4494 }; 4495 4496 qup_spi2_data_clk: qup-spi2-data-clk-state { 4497 pins = "gpio8", "gpio9", "gpio10"; 4498 function = "qup02"; 4499 }; 4500 4501 qup_spi2_cs: qup-spi2-cs-state { 4502 pins = "gpio11"; 4503 function = "qup02"; 4504 }; 4505 4506 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4507 pins = "gpio11"; 4508 function = "gpio"; 4509 }; 4510 4511 qup_spi3_data_clk: qup-spi3-data-clk-state { 4512 pins = "gpio12", "gpio13", "gpio14"; 4513 function = "qup03"; 4514 }; 4515 4516 qup_spi3_cs: qup-spi3-cs-state { 4517 pins = "gpio15"; 4518 function = "qup03"; 4519 }; 4520 4521 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4522 pins = "gpio15"; 4523 function = "gpio"; 4524 }; 4525 4526 qup_spi4_data_clk: qup-spi4-data-clk-state { 4527 pins = "gpio16", "gpio17", "gpio18"; 4528 function = "qup04"; 4529 }; 4530 4531 qup_spi4_cs: qup-spi4-cs-state { 4532 pins = "gpio19"; 4533 function = "qup04"; 4534 }; 4535 4536 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4537 pins = "gpio19"; 4538 function = "gpio"; 4539 }; 4540 4541 qup_spi5_data_clk: qup-spi5-data-clk-state { 4542 pins = "gpio20", "gpio21", "gpio22"; 4543 function = "qup05"; 4544 }; 4545 4546 qup_spi5_cs: qup-spi5-cs-state { 4547 pins = "gpio23"; 4548 function = "qup05"; 4549 }; 4550 4551 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4552 pins = "gpio23"; 4553 function = "gpio"; 4554 }; 4555 4556 qup_spi6_data_clk: qup-spi6-data-clk-state { 4557 pins = "gpio24", "gpio25", "gpio26"; 4558 function = "qup06"; 4559 }; 4560 4561 qup_spi6_cs: qup-spi6-cs-state { 4562 pins = "gpio27"; 4563 function = "qup06"; 4564 }; 4565 4566 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4567 pins = "gpio27"; 4568 function = "gpio"; 4569 }; 4570 4571 qup_spi7_data_clk: qup-spi7-data-clk-state { 4572 pins = "gpio28", "gpio29", "gpio30"; 4573 function = "qup07"; 4574 }; 4575 4576 qup_spi7_cs: qup-spi7-cs-state { 4577 pins = "gpio31"; 4578 function = "qup07"; 4579 }; 4580 4581 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4582 pins = "gpio31"; 4583 function = "gpio"; 4584 }; 4585 4586 qup_spi8_data_clk: qup-spi8-data-clk-state { 4587 pins = "gpio32", "gpio33", "gpio34"; 4588 function = "qup10"; 4589 }; 4590 4591 qup_spi8_cs: qup-spi8-cs-state { 4592 pins = "gpio35"; 4593 function = "qup10"; 4594 }; 4595 4596 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4597 pins = "gpio35"; 4598 function = "gpio"; 4599 }; 4600 4601 qup_spi9_data_clk: qup-spi9-data-clk-state { 4602 pins = "gpio36", "gpio37", "gpio38"; 4603 function = "qup11"; 4604 }; 4605 4606 qup_spi9_cs: qup-spi9-cs-state { 4607 pins = "gpio39"; 4608 function = "qup11"; 4609 }; 4610 4611 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4612 pins = "gpio39"; 4613 function = "gpio"; 4614 }; 4615 4616 qup_spi10_data_clk: qup-spi10-data-clk-state { 4617 pins = "gpio40", "gpio41", "gpio42"; 4618 function = "qup12"; 4619 }; 4620 4621 qup_spi10_cs: qup-spi10-cs-state { 4622 pins = "gpio43"; 4623 function = "qup12"; 4624 }; 4625 4626 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4627 pins = "gpio43"; 4628 function = "gpio"; 4629 }; 4630 4631 qup_spi11_data_clk: qup-spi11-data-clk-state { 4632 pins = "gpio44", "gpio45", "gpio46"; 4633 function = "qup13"; 4634 }; 4635 4636 qup_spi11_cs: qup-spi11-cs-state { 4637 pins = "gpio47"; 4638 function = "qup13"; 4639 }; 4640 4641 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4642 pins = "gpio47"; 4643 function = "gpio"; 4644 }; 4645 4646 qup_spi12_data_clk: qup-spi12-data-clk-state { 4647 pins = "gpio48", "gpio49", "gpio50"; 4648 function = "qup14"; 4649 }; 4650 4651 qup_spi12_cs: qup-spi12-cs-state { 4652 pins = "gpio51"; 4653 function = "qup14"; 4654 }; 4655 4656 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4657 pins = "gpio51"; 4658 function = "gpio"; 4659 }; 4660 4661 qup_spi13_data_clk: qup-spi13-data-clk-state { 4662 pins = "gpio52", "gpio53", "gpio54"; 4663 function = "qup15"; 4664 }; 4665 4666 qup_spi13_cs: qup-spi13-cs-state { 4667 pins = "gpio55"; 4668 function = "qup15"; 4669 }; 4670 4671 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4672 pins = "gpio55"; 4673 function = "gpio"; 4674 }; 4675 4676 qup_spi14_data_clk: qup-spi14-data-clk-state { 4677 pins = "gpio56", "gpio57", "gpio58"; 4678 function = "qup16"; 4679 }; 4680 4681 qup_spi14_cs: qup-spi14-cs-state { 4682 pins = "gpio59"; 4683 function = "qup16"; 4684 }; 4685 4686 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4687 pins = "gpio59"; 4688 function = "gpio"; 4689 }; 4690 4691 qup_spi15_data_clk: qup-spi15-data-clk-state { 4692 pins = "gpio60", "gpio61", "gpio62"; 4693 function = "qup17"; 4694 }; 4695 4696 qup_spi15_cs: qup-spi15-cs-state { 4697 pins = "gpio63"; 4698 function = "qup17"; 4699 }; 4700 4701 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4702 pins = "gpio63"; 4703 function = "gpio"; 4704 }; 4705 4706 qup_uart0_cts: qup-uart0-cts-state { 4707 pins = "gpio0"; 4708 function = "qup00"; 4709 }; 4710 4711 qup_uart0_rts: qup-uart0-rts-state { 4712 pins = "gpio1"; 4713 function = "qup00"; 4714 }; 4715 4716 qup_uart0_tx: qup-uart0-tx-state { 4717 pins = "gpio2"; 4718 function = "qup00"; 4719 }; 4720 4721 qup_uart0_rx: qup-uart0-rx-state { 4722 pins = "gpio3"; 4723 function = "qup00"; 4724 }; 4725 4726 qup_uart1_cts: qup-uart1-cts-state { 4727 pins = "gpio4"; 4728 function = "qup01"; 4729 }; 4730 4731 qup_uart1_rts: qup-uart1-rts-state { 4732 pins = "gpio5"; 4733 function = "qup01"; 4734 }; 4735 4736 qup_uart1_tx: qup-uart1-tx-state { 4737 pins = "gpio6"; 4738 function = "qup01"; 4739 }; 4740 4741 qup_uart1_rx: qup-uart1-rx-state { 4742 pins = "gpio7"; 4743 function = "qup01"; 4744 }; 4745 4746 qup_uart2_cts: qup-uart2-cts-state { 4747 pins = "gpio8"; 4748 function = "qup02"; 4749 }; 4750 4751 qup_uart2_rts: qup-uart2-rts-state { 4752 pins = "gpio9"; 4753 function = "qup02"; 4754 }; 4755 4756 qup_uart2_tx: qup-uart2-tx-state { 4757 pins = "gpio10"; 4758 function = "qup02"; 4759 }; 4760 4761 qup_uart2_rx: qup-uart2-rx-state { 4762 pins = "gpio11"; 4763 function = "qup02"; 4764 }; 4765 4766 qup_uart3_cts: qup-uart3-cts-state { 4767 pins = "gpio12"; 4768 function = "qup03"; 4769 }; 4770 4771 qup_uart3_rts: qup-uart3-rts-state { 4772 pins = "gpio13"; 4773 function = "qup03"; 4774 }; 4775 4776 qup_uart3_tx: qup-uart3-tx-state { 4777 pins = "gpio14"; 4778 function = "qup03"; 4779 }; 4780 4781 qup_uart3_rx: qup-uart3-rx-state { 4782 pins = "gpio15"; 4783 function = "qup03"; 4784 }; 4785 4786 qup_uart4_cts: qup-uart4-cts-state { 4787 pins = "gpio16"; 4788 function = "qup04"; 4789 }; 4790 4791 qup_uart4_rts: qup-uart4-rts-state { 4792 pins = "gpio17"; 4793 function = "qup04"; 4794 }; 4795 4796 qup_uart4_tx: qup-uart4-tx-state { 4797 pins = "gpio18"; 4798 function = "qup04"; 4799 }; 4800 4801 qup_uart4_rx: qup-uart4-rx-state { 4802 pins = "gpio19"; 4803 function = "qup04"; 4804 }; 4805 4806 qup_uart5_cts: qup-uart5-cts-state { 4807 pins = "gpio20"; 4808 function = "qup05"; 4809 }; 4810 4811 qup_uart5_rts: qup-uart5-rts-state { 4812 pins = "gpio21"; 4813 function = "qup05"; 4814 }; 4815 4816 qup_uart5_tx: qup-uart5-tx-state { 4817 pins = "gpio22"; 4818 function = "qup05"; 4819 }; 4820 4821 qup_uart5_rx: qup-uart5-rx-state { 4822 pins = "gpio23"; 4823 function = "qup05"; 4824 }; 4825 4826 qup_uart6_cts: qup-uart6-cts-state { 4827 pins = "gpio24"; 4828 function = "qup06"; 4829 }; 4830 4831 qup_uart6_rts: qup-uart6-rts-state { 4832 pins = "gpio25"; 4833 function = "qup06"; 4834 }; 4835 4836 qup_uart6_tx: qup-uart6-tx-state { 4837 pins = "gpio26"; 4838 function = "qup06"; 4839 }; 4840 4841 qup_uart6_rx: qup-uart6-rx-state { 4842 pins = "gpio27"; 4843 function = "qup06"; 4844 }; 4845 4846 qup_uart7_cts: qup-uart7-cts-state { 4847 pins = "gpio28"; 4848 function = "qup07"; 4849 }; 4850 4851 qup_uart7_rts: qup-uart7-rts-state { 4852 pins = "gpio29"; 4853 function = "qup07"; 4854 }; 4855 4856 qup_uart7_tx: qup-uart7-tx-state { 4857 pins = "gpio30"; 4858 function = "qup07"; 4859 }; 4860 4861 qup_uart7_rx: qup-uart7-rx-state { 4862 pins = "gpio31"; 4863 function = "qup07"; 4864 }; 4865 4866 qup_uart8_cts: qup-uart8-cts-state { 4867 pins = "gpio32"; 4868 function = "qup10"; 4869 }; 4870 4871 qup_uart8_rts: qup-uart8-rts-state { 4872 pins = "gpio33"; 4873 function = "qup10"; 4874 }; 4875 4876 qup_uart8_tx: qup-uart8-tx-state { 4877 pins = "gpio34"; 4878 function = "qup10"; 4879 }; 4880 4881 qup_uart8_rx: qup-uart8-rx-state { 4882 pins = "gpio35"; 4883 function = "qup10"; 4884 }; 4885 4886 qup_uart9_cts: qup-uart9-cts-state { 4887 pins = "gpio36"; 4888 function = "qup11"; 4889 }; 4890 4891 qup_uart9_rts: qup-uart9-rts-state { 4892 pins = "gpio37"; 4893 function = "qup11"; 4894 }; 4895 4896 qup_uart9_tx: qup-uart9-tx-state { 4897 pins = "gpio38"; 4898 function = "qup11"; 4899 }; 4900 4901 qup_uart9_rx: qup-uart9-rx-state { 4902 pins = "gpio39"; 4903 function = "qup11"; 4904 }; 4905 4906 qup_uart10_cts: qup-uart10-cts-state { 4907 pins = "gpio40"; 4908 function = "qup12"; 4909 }; 4910 4911 qup_uart10_rts: qup-uart10-rts-state { 4912 pins = "gpio41"; 4913 function = "qup12"; 4914 }; 4915 4916 qup_uart10_tx: qup-uart10-tx-state { 4917 pins = "gpio42"; 4918 function = "qup12"; 4919 }; 4920 4921 qup_uart10_rx: qup-uart10-rx-state { 4922 pins = "gpio43"; 4923 function = "qup12"; 4924 }; 4925 4926 qup_uart11_cts: qup-uart11-cts-state { 4927 pins = "gpio44"; 4928 function = "qup13"; 4929 }; 4930 4931 qup_uart11_rts: qup-uart11-rts-state { 4932 pins = "gpio45"; 4933 function = "qup13"; 4934 }; 4935 4936 qup_uart11_tx: qup-uart11-tx-state { 4937 pins = "gpio46"; 4938 function = "qup13"; 4939 }; 4940 4941 qup_uart11_rx: qup-uart11-rx-state { 4942 pins = "gpio47"; 4943 function = "qup13"; 4944 }; 4945 4946 qup_uart12_cts: qup-uart12-cts-state { 4947 pins = "gpio48"; 4948 function = "qup14"; 4949 }; 4950 4951 qup_uart12_rts: qup-uart12-rts-state { 4952 pins = "gpio49"; 4953 function = "qup14"; 4954 }; 4955 4956 qup_uart12_tx: qup-uart12-tx-state { 4957 pins = "gpio50"; 4958 function = "qup14"; 4959 }; 4960 4961 qup_uart12_rx: qup-uart12-rx-state { 4962 pins = "gpio51"; 4963 function = "qup14"; 4964 }; 4965 4966 qup_uart13_cts: qup-uart13-cts-state { 4967 pins = "gpio52"; 4968 function = "qup15"; 4969 }; 4970 4971 qup_uart13_rts: qup-uart13-rts-state { 4972 pins = "gpio53"; 4973 function = "qup15"; 4974 }; 4975 4976 qup_uart13_tx: qup-uart13-tx-state { 4977 pins = "gpio54"; 4978 function = "qup15"; 4979 }; 4980 4981 qup_uart13_rx: qup-uart13-rx-state { 4982 pins = "gpio55"; 4983 function = "qup15"; 4984 }; 4985 4986 qup_uart14_cts: qup-uart14-cts-state { 4987 pins = "gpio56"; 4988 function = "qup16"; 4989 }; 4990 4991 qup_uart14_rts: qup-uart14-rts-state { 4992 pins = "gpio57"; 4993 function = "qup16"; 4994 }; 4995 4996 qup_uart14_tx: qup-uart14-tx-state { 4997 pins = "gpio58"; 4998 function = "qup16"; 4999 }; 5000 5001 qup_uart14_rx: qup-uart14-rx-state { 5002 pins = "gpio59"; 5003 function = "qup16"; 5004 }; 5005 5006 qup_uart15_cts: qup-uart15-cts-state { 5007 pins = "gpio60"; 5008 function = "qup17"; 5009 }; 5010 5011 qup_uart15_rts: qup-uart15-rts-state { 5012 pins = "gpio61"; 5013 function = "qup17"; 5014 }; 5015 5016 qup_uart15_tx: qup-uart15-tx-state { 5017 pins = "gpio62"; 5018 function = "qup17"; 5019 }; 5020 5021 qup_uart15_rx: qup-uart15-rx-state { 5022 pins = "gpio63"; 5023 function = "qup17"; 5024 }; 5025 5026 sdc1_clk: sdc1-clk-state { 5027 pins = "sdc1_clk"; 5028 }; 5029 5030 sdc1_cmd: sdc1-cmd-state { 5031 pins = "sdc1_cmd"; 5032 }; 5033 5034 sdc1_data: sdc1-data-state { 5035 pins = "sdc1_data"; 5036 }; 5037 5038 sdc1_rclk: sdc1-rclk-state { 5039 pins = "sdc1_rclk"; 5040 }; 5041 5042 sdc1_clk_sleep: sdc1-clk-sleep-state { 5043 pins = "sdc1_clk"; 5044 drive-strength = <2>; 5045 bias-bus-hold; 5046 }; 5047 5048 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5049 pins = "sdc1_cmd"; 5050 drive-strength = <2>; 5051 bias-bus-hold; 5052 }; 5053 5054 sdc1_data_sleep: sdc1-data-sleep-state { 5055 pins = "sdc1_data"; 5056 drive-strength = <2>; 5057 bias-bus-hold; 5058 }; 5059 5060 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5061 pins = "sdc1_rclk"; 5062 drive-strength = <2>; 5063 bias-bus-hold; 5064 }; 5065 5066 sdc2_clk: sdc2-clk-state { 5067 pins = "sdc2_clk"; 5068 }; 5069 5070 sdc2_cmd: sdc2-cmd-state { 5071 pins = "sdc2_cmd"; 5072 }; 5073 5074 sdc2_data: sdc2-data-state { 5075 pins = "sdc2_data"; 5076 }; 5077 5078 sdc2_clk_sleep: sdc2-clk-sleep-state { 5079 pins = "sdc2_clk"; 5080 drive-strength = <2>; 5081 bias-bus-hold; 5082 }; 5083 5084 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5085 pins = "sdc2_cmd"; 5086 drive-strength = <2>; 5087 bias-bus-hold; 5088 }; 5089 5090 sdc2_data_sleep: sdc2-data-sleep-state { 5091 pins = "sdc2_data"; 5092 drive-strength = <2>; 5093 bias-bus-hold; 5094 }; 5095 }; 5096 5097 sram@146a5000 { 5098 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5099 reg = <0 0x146a5000 0 0x6000>; 5100 5101 #address-cells = <1>; 5102 #size-cells = <1>; 5103 5104 ranges = <0 0 0x146a5000 0x6000>; 5105 5106 pil-reloc@594c { 5107 compatible = "qcom,pil-reloc-info"; 5108 reg = <0x594c 0xc8>; 5109 }; 5110 }; 5111 5112 apps_smmu: iommu@15000000 { 5113 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5114 reg = <0 0x15000000 0 0x100000>; 5115 #iommu-cells = <2>; 5116 #global-interrupts = <1>; 5117 dma-coherent; 5118 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5196 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5197 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5198 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5199 }; 5200 5201 intc: interrupt-controller@17a00000 { 5202 compatible = "arm,gic-v3"; 5203 #address-cells = <2>; 5204 #size-cells = <2>; 5205 ranges; 5206 #interrupt-cells = <3>; 5207 interrupt-controller; 5208 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5209 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5210 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5211 5212 gic-its@17a40000 { 5213 compatible = "arm,gic-v3-its"; 5214 msi-controller; 5215 #msi-cells = <1>; 5216 reg = <0 0x17a40000 0 0x20000>; 5217 status = "disabled"; 5218 }; 5219 }; 5220 5221 watchdog@17c10000 { 5222 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5223 reg = <0 0x17c10000 0 0x1000>; 5224 clocks = <&sleep_clk>; 5225 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5226 }; 5227 5228 timer@17c20000 { 5229 #address-cells = <1>; 5230 #size-cells = <1>; 5231 ranges = <0 0 0 0x20000000>; 5232 compatible = "arm,armv7-timer-mem"; 5233 reg = <0 0x17c20000 0 0x1000>; 5234 5235 frame@17c21000 { 5236 frame-number = <0>; 5237 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5238 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5239 reg = <0x17c21000 0x1000>, 5240 <0x17c22000 0x1000>; 5241 }; 5242 5243 frame@17c23000 { 5244 frame-number = <1>; 5245 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5246 reg = <0x17c23000 0x1000>; 5247 status = "disabled"; 5248 }; 5249 5250 frame@17c25000 { 5251 frame-number = <2>; 5252 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5253 reg = <0x17c25000 0x1000>; 5254 status = "disabled"; 5255 }; 5256 5257 frame@17c27000 { 5258 frame-number = <3>; 5259 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5260 reg = <0x17c27000 0x1000>; 5261 status = "disabled"; 5262 }; 5263 5264 frame@17c29000 { 5265 frame-number = <4>; 5266 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5267 reg = <0x17c29000 0x1000>; 5268 status = "disabled"; 5269 }; 5270 5271 frame@17c2b000 { 5272 frame-number = <5>; 5273 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5274 reg = <0x17c2b000 0x1000>; 5275 status = "disabled"; 5276 }; 5277 5278 frame@17c2d000 { 5279 frame-number = <6>; 5280 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5281 reg = <0x17c2d000 0x1000>; 5282 status = "disabled"; 5283 }; 5284 }; 5285 5286 apps_rsc: rsc@18200000 { 5287 compatible = "qcom,rpmh-rsc"; 5288 reg = <0 0x18200000 0 0x10000>, 5289 <0 0x18210000 0 0x10000>, 5290 <0 0x18220000 0 0x10000>; 5291 reg-names = "drv-0", "drv-1", "drv-2"; 5292 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5293 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5294 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5295 qcom,tcs-offset = <0xd00>; 5296 qcom,drv-id = <2>; 5297 qcom,tcs-config = <ACTIVE_TCS 2>, 5298 <SLEEP_TCS 3>, 5299 <WAKE_TCS 3>, 5300 <CONTROL_TCS 1>; 5301 5302 apps_bcm_voter: bcm-voter { 5303 compatible = "qcom,bcm-voter"; 5304 }; 5305 5306 rpmhpd: power-controller { 5307 compatible = "qcom,sc7280-rpmhpd"; 5308 #power-domain-cells = <1>; 5309 operating-points-v2 = <&rpmhpd_opp_table>; 5310 5311 rpmhpd_opp_table: opp-table { 5312 compatible = "operating-points-v2"; 5313 5314 rpmhpd_opp_ret: opp1 { 5315 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5316 }; 5317 5318 rpmhpd_opp_low_svs: opp2 { 5319 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5320 }; 5321 5322 rpmhpd_opp_svs: opp3 { 5323 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5324 }; 5325 5326 rpmhpd_opp_svs_l1: opp4 { 5327 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5328 }; 5329 5330 rpmhpd_opp_svs_l2: opp5 { 5331 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5332 }; 5333 5334 rpmhpd_opp_nom: opp6 { 5335 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5336 }; 5337 5338 rpmhpd_opp_nom_l1: opp7 { 5339 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5340 }; 5341 5342 rpmhpd_opp_turbo: opp8 { 5343 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5344 }; 5345 5346 rpmhpd_opp_turbo_l1: opp9 { 5347 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5348 }; 5349 }; 5350 }; 5351 5352 rpmhcc: clock-controller { 5353 compatible = "qcom,sc7280-rpmh-clk"; 5354 clocks = <&xo_board>; 5355 clock-names = "xo"; 5356 #clock-cells = <1>; 5357 }; 5358 }; 5359 5360 epss_l3: interconnect@18590000 { 5361 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5362 reg = <0 0x18590000 0 0x1000>; 5363 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5364 clock-names = "xo", "alternate"; 5365 #interconnect-cells = <1>; 5366 }; 5367 5368 cpufreq_hw: cpufreq@18591000 { 5369 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5370 reg = <0 0x18591000 0 0x1000>, 5371 <0 0x18592000 0 0x1000>, 5372 <0 0x18593000 0 0x1000>; 5373 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5374 clock-names = "xo", "alternate"; 5375 #freq-domain-cells = <1>; 5376 }; 5377 }; 5378 5379 thermal_zones: thermal-zones { 5380 cpu0-thermal { 5381 polling-delay-passive = <250>; 5382 polling-delay = <0>; 5383 5384 thermal-sensors = <&tsens0 1>; 5385 5386 trips { 5387 cpu0_alert0: trip-point0 { 5388 temperature = <90000>; 5389 hysteresis = <2000>; 5390 type = "passive"; 5391 }; 5392 5393 cpu0_alert1: trip-point1 { 5394 temperature = <95000>; 5395 hysteresis = <2000>; 5396 type = "passive"; 5397 }; 5398 5399 cpu0_crit: cpu-crit { 5400 temperature = <110000>; 5401 hysteresis = <0>; 5402 type = "critical"; 5403 }; 5404 }; 5405 5406 cooling-maps { 5407 map0 { 5408 trip = <&cpu0_alert0>; 5409 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5412 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5413 }; 5414 map1 { 5415 trip = <&cpu0_alert1>; 5416 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5417 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5418 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5419 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5420 }; 5421 }; 5422 }; 5423 5424 cpu1-thermal { 5425 polling-delay-passive = <250>; 5426 polling-delay = <0>; 5427 5428 thermal-sensors = <&tsens0 2>; 5429 5430 trips { 5431 cpu1_alert0: trip-point0 { 5432 temperature = <90000>; 5433 hysteresis = <2000>; 5434 type = "passive"; 5435 }; 5436 5437 cpu1_alert1: trip-point1 { 5438 temperature = <95000>; 5439 hysteresis = <2000>; 5440 type = "passive"; 5441 }; 5442 5443 cpu1_crit: cpu-crit { 5444 temperature = <110000>; 5445 hysteresis = <0>; 5446 type = "critical"; 5447 }; 5448 }; 5449 5450 cooling-maps { 5451 map0 { 5452 trip = <&cpu1_alert0>; 5453 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5456 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5457 }; 5458 map1 { 5459 trip = <&cpu1_alert1>; 5460 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5461 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5462 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5463 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5464 }; 5465 }; 5466 }; 5467 5468 cpu2-thermal { 5469 polling-delay-passive = <250>; 5470 polling-delay = <0>; 5471 5472 thermal-sensors = <&tsens0 3>; 5473 5474 trips { 5475 cpu2_alert0: trip-point0 { 5476 temperature = <90000>; 5477 hysteresis = <2000>; 5478 type = "passive"; 5479 }; 5480 5481 cpu2_alert1: trip-point1 { 5482 temperature = <95000>; 5483 hysteresis = <2000>; 5484 type = "passive"; 5485 }; 5486 5487 cpu2_crit: cpu-crit { 5488 temperature = <110000>; 5489 hysteresis = <0>; 5490 type = "critical"; 5491 }; 5492 }; 5493 5494 cooling-maps { 5495 map0 { 5496 trip = <&cpu2_alert0>; 5497 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5500 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5501 }; 5502 map1 { 5503 trip = <&cpu2_alert1>; 5504 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5505 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5506 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5507 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5508 }; 5509 }; 5510 }; 5511 5512 cpu3-thermal { 5513 polling-delay-passive = <250>; 5514 polling-delay = <0>; 5515 5516 thermal-sensors = <&tsens0 4>; 5517 5518 trips { 5519 cpu3_alert0: trip-point0 { 5520 temperature = <90000>; 5521 hysteresis = <2000>; 5522 type = "passive"; 5523 }; 5524 5525 cpu3_alert1: trip-point1 { 5526 temperature = <95000>; 5527 hysteresis = <2000>; 5528 type = "passive"; 5529 }; 5530 5531 cpu3_crit: cpu-crit { 5532 temperature = <110000>; 5533 hysteresis = <0>; 5534 type = "critical"; 5535 }; 5536 }; 5537 5538 cooling-maps { 5539 map0 { 5540 trip = <&cpu3_alert0>; 5541 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5544 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5545 }; 5546 map1 { 5547 trip = <&cpu3_alert1>; 5548 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5549 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5550 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5551 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5552 }; 5553 }; 5554 }; 5555 5556 cpu4-thermal { 5557 polling-delay-passive = <250>; 5558 polling-delay = <0>; 5559 5560 thermal-sensors = <&tsens0 7>; 5561 5562 trips { 5563 cpu4_alert0: trip-point0 { 5564 temperature = <90000>; 5565 hysteresis = <2000>; 5566 type = "passive"; 5567 }; 5568 5569 cpu4_alert1: trip-point1 { 5570 temperature = <95000>; 5571 hysteresis = <2000>; 5572 type = "passive"; 5573 }; 5574 5575 cpu4_crit: cpu-crit { 5576 temperature = <110000>; 5577 hysteresis = <0>; 5578 type = "critical"; 5579 }; 5580 }; 5581 5582 cooling-maps { 5583 map0 { 5584 trip = <&cpu4_alert0>; 5585 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5588 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5589 }; 5590 map1 { 5591 trip = <&cpu4_alert1>; 5592 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5593 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5594 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5595 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5596 }; 5597 }; 5598 }; 5599 5600 cpu5-thermal { 5601 polling-delay-passive = <250>; 5602 polling-delay = <0>; 5603 5604 thermal-sensors = <&tsens0 8>; 5605 5606 trips { 5607 cpu5_alert0: trip-point0 { 5608 temperature = <90000>; 5609 hysteresis = <2000>; 5610 type = "passive"; 5611 }; 5612 5613 cpu5_alert1: trip-point1 { 5614 temperature = <95000>; 5615 hysteresis = <2000>; 5616 type = "passive"; 5617 }; 5618 5619 cpu5_crit: cpu-crit { 5620 temperature = <110000>; 5621 hysteresis = <0>; 5622 type = "critical"; 5623 }; 5624 }; 5625 5626 cooling-maps { 5627 map0 { 5628 trip = <&cpu5_alert0>; 5629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5632 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5633 }; 5634 map1 { 5635 trip = <&cpu5_alert1>; 5636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5637 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5638 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5639 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5640 }; 5641 }; 5642 }; 5643 5644 cpu6-thermal { 5645 polling-delay-passive = <250>; 5646 polling-delay = <0>; 5647 5648 thermal-sensors = <&tsens0 9>; 5649 5650 trips { 5651 cpu6_alert0: trip-point0 { 5652 temperature = <90000>; 5653 hysteresis = <2000>; 5654 type = "passive"; 5655 }; 5656 5657 cpu6_alert1: trip-point1 { 5658 temperature = <95000>; 5659 hysteresis = <2000>; 5660 type = "passive"; 5661 }; 5662 5663 cpu6_crit: cpu-crit { 5664 temperature = <110000>; 5665 hysteresis = <0>; 5666 type = "critical"; 5667 }; 5668 }; 5669 5670 cooling-maps { 5671 map0 { 5672 trip = <&cpu6_alert0>; 5673 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5676 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5677 }; 5678 map1 { 5679 trip = <&cpu6_alert1>; 5680 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5681 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5682 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5683 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5684 }; 5685 }; 5686 }; 5687 5688 cpu7-thermal { 5689 polling-delay-passive = <250>; 5690 polling-delay = <0>; 5691 5692 thermal-sensors = <&tsens0 10>; 5693 5694 trips { 5695 cpu7_alert0: trip-point0 { 5696 temperature = <90000>; 5697 hysteresis = <2000>; 5698 type = "passive"; 5699 }; 5700 5701 cpu7_alert1: trip-point1 { 5702 temperature = <95000>; 5703 hysteresis = <2000>; 5704 type = "passive"; 5705 }; 5706 5707 cpu7_crit: cpu-crit { 5708 temperature = <110000>; 5709 hysteresis = <0>; 5710 type = "critical"; 5711 }; 5712 }; 5713 5714 cooling-maps { 5715 map0 { 5716 trip = <&cpu7_alert0>; 5717 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5720 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5721 }; 5722 map1 { 5723 trip = <&cpu7_alert1>; 5724 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5725 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5726 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5727 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5728 }; 5729 }; 5730 }; 5731 5732 cpu8-thermal { 5733 polling-delay-passive = <250>; 5734 polling-delay = <0>; 5735 5736 thermal-sensors = <&tsens0 11>; 5737 5738 trips { 5739 cpu8_alert0: trip-point0 { 5740 temperature = <90000>; 5741 hysteresis = <2000>; 5742 type = "passive"; 5743 }; 5744 5745 cpu8_alert1: trip-point1 { 5746 temperature = <95000>; 5747 hysteresis = <2000>; 5748 type = "passive"; 5749 }; 5750 5751 cpu8_crit: cpu-crit { 5752 temperature = <110000>; 5753 hysteresis = <0>; 5754 type = "critical"; 5755 }; 5756 }; 5757 5758 cooling-maps { 5759 map0 { 5760 trip = <&cpu8_alert0>; 5761 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5764 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5765 }; 5766 map1 { 5767 trip = <&cpu8_alert1>; 5768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5770 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5772 }; 5773 }; 5774 }; 5775 5776 cpu9-thermal { 5777 polling-delay-passive = <250>; 5778 polling-delay = <0>; 5779 5780 thermal-sensors = <&tsens0 12>; 5781 5782 trips { 5783 cpu9_alert0: trip-point0 { 5784 temperature = <90000>; 5785 hysteresis = <2000>; 5786 type = "passive"; 5787 }; 5788 5789 cpu9_alert1: trip-point1 { 5790 temperature = <95000>; 5791 hysteresis = <2000>; 5792 type = "passive"; 5793 }; 5794 5795 cpu9_crit: cpu-crit { 5796 temperature = <110000>; 5797 hysteresis = <0>; 5798 type = "critical"; 5799 }; 5800 }; 5801 5802 cooling-maps { 5803 map0 { 5804 trip = <&cpu9_alert0>; 5805 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5808 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5809 }; 5810 map1 { 5811 trip = <&cpu9_alert1>; 5812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5813 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5814 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5815 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5816 }; 5817 }; 5818 }; 5819 5820 cpu10-thermal { 5821 polling-delay-passive = <250>; 5822 polling-delay = <0>; 5823 5824 thermal-sensors = <&tsens0 13>; 5825 5826 trips { 5827 cpu10_alert0: trip-point0 { 5828 temperature = <90000>; 5829 hysteresis = <2000>; 5830 type = "passive"; 5831 }; 5832 5833 cpu10_alert1: trip-point1 { 5834 temperature = <95000>; 5835 hysteresis = <2000>; 5836 type = "passive"; 5837 }; 5838 5839 cpu10_crit: cpu-crit { 5840 temperature = <110000>; 5841 hysteresis = <0>; 5842 type = "critical"; 5843 }; 5844 }; 5845 5846 cooling-maps { 5847 map0 { 5848 trip = <&cpu10_alert0>; 5849 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5852 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5853 }; 5854 map1 { 5855 trip = <&cpu10_alert1>; 5856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5858 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5860 }; 5861 }; 5862 }; 5863 5864 cpu11-thermal { 5865 polling-delay-passive = <250>; 5866 polling-delay = <0>; 5867 5868 thermal-sensors = <&tsens0 14>; 5869 5870 trips { 5871 cpu11_alert0: trip-point0 { 5872 temperature = <90000>; 5873 hysteresis = <2000>; 5874 type = "passive"; 5875 }; 5876 5877 cpu11_alert1: trip-point1 { 5878 temperature = <95000>; 5879 hysteresis = <2000>; 5880 type = "passive"; 5881 }; 5882 5883 cpu11_crit: cpu-crit { 5884 temperature = <110000>; 5885 hysteresis = <0>; 5886 type = "critical"; 5887 }; 5888 }; 5889 5890 cooling-maps { 5891 map0 { 5892 trip = <&cpu11_alert0>; 5893 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5894 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5895 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5896 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5897 }; 5898 map1 { 5899 trip = <&cpu11_alert1>; 5900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5901 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5902 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5903 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5904 }; 5905 }; 5906 }; 5907 5908 aoss0-thermal { 5909 polling-delay-passive = <0>; 5910 polling-delay = <0>; 5911 5912 thermal-sensors = <&tsens0 0>; 5913 5914 trips { 5915 aoss0_alert0: trip-point0 { 5916 temperature = <90000>; 5917 hysteresis = <2000>; 5918 type = "hot"; 5919 }; 5920 5921 aoss0_crit: aoss0-crit { 5922 temperature = <110000>; 5923 hysteresis = <0>; 5924 type = "critical"; 5925 }; 5926 }; 5927 }; 5928 5929 aoss1-thermal { 5930 polling-delay-passive = <0>; 5931 polling-delay = <0>; 5932 5933 thermal-sensors = <&tsens1 0>; 5934 5935 trips { 5936 aoss1_alert0: trip-point0 { 5937 temperature = <90000>; 5938 hysteresis = <2000>; 5939 type = "hot"; 5940 }; 5941 5942 aoss1_crit: aoss1-crit { 5943 temperature = <110000>; 5944 hysteresis = <0>; 5945 type = "critical"; 5946 }; 5947 }; 5948 }; 5949 5950 cpuss0-thermal { 5951 polling-delay-passive = <0>; 5952 polling-delay = <0>; 5953 5954 thermal-sensors = <&tsens0 5>; 5955 5956 trips { 5957 cpuss0_alert0: trip-point0 { 5958 temperature = <90000>; 5959 hysteresis = <2000>; 5960 type = "hot"; 5961 }; 5962 cpuss0_crit: cluster0-crit { 5963 temperature = <110000>; 5964 hysteresis = <0>; 5965 type = "critical"; 5966 }; 5967 }; 5968 }; 5969 5970 cpuss1-thermal { 5971 polling-delay-passive = <0>; 5972 polling-delay = <0>; 5973 5974 thermal-sensors = <&tsens0 6>; 5975 5976 trips { 5977 cpuss1_alert0: trip-point0 { 5978 temperature = <90000>; 5979 hysteresis = <2000>; 5980 type = "hot"; 5981 }; 5982 cpuss1_crit: cluster0-crit { 5983 temperature = <110000>; 5984 hysteresis = <0>; 5985 type = "critical"; 5986 }; 5987 }; 5988 }; 5989 5990 gpuss0-thermal { 5991 polling-delay-passive = <100>; 5992 polling-delay = <0>; 5993 5994 thermal-sensors = <&tsens1 1>; 5995 5996 trips { 5997 gpuss0_alert0: trip-point0 { 5998 temperature = <95000>; 5999 hysteresis = <2000>; 6000 type = "passive"; 6001 }; 6002 6003 gpuss0_crit: gpuss0-crit { 6004 temperature = <110000>; 6005 hysteresis = <0>; 6006 type = "critical"; 6007 }; 6008 }; 6009 6010 cooling-maps { 6011 map0 { 6012 trip = <&gpuss0_alert0>; 6013 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6014 }; 6015 }; 6016 }; 6017 6018 gpuss1-thermal { 6019 polling-delay-passive = <100>; 6020 polling-delay = <0>; 6021 6022 thermal-sensors = <&tsens1 2>; 6023 6024 trips { 6025 gpuss1_alert0: trip-point0 { 6026 temperature = <95000>; 6027 hysteresis = <2000>; 6028 type = "passive"; 6029 }; 6030 6031 gpuss1_crit: gpuss1-crit { 6032 temperature = <110000>; 6033 hysteresis = <0>; 6034 type = "critical"; 6035 }; 6036 }; 6037 6038 cooling-maps { 6039 map0 { 6040 trip = <&gpuss1_alert0>; 6041 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6042 }; 6043 }; 6044 }; 6045 6046 nspss0-thermal { 6047 polling-delay-passive = <0>; 6048 polling-delay = <0>; 6049 6050 thermal-sensors = <&tsens1 3>; 6051 6052 trips { 6053 nspss0_alert0: trip-point0 { 6054 temperature = <90000>; 6055 hysteresis = <2000>; 6056 type = "hot"; 6057 }; 6058 6059 nspss0_crit: nspss0-crit { 6060 temperature = <110000>; 6061 hysteresis = <0>; 6062 type = "critical"; 6063 }; 6064 }; 6065 }; 6066 6067 nspss1-thermal { 6068 polling-delay-passive = <0>; 6069 polling-delay = <0>; 6070 6071 thermal-sensors = <&tsens1 4>; 6072 6073 trips { 6074 nspss1_alert0: trip-point0 { 6075 temperature = <90000>; 6076 hysteresis = <2000>; 6077 type = "hot"; 6078 }; 6079 6080 nspss1_crit: nspss1-crit { 6081 temperature = <110000>; 6082 hysteresis = <0>; 6083 type = "critical"; 6084 }; 6085 }; 6086 }; 6087 6088 video-thermal { 6089 polling-delay-passive = <0>; 6090 polling-delay = <0>; 6091 6092 thermal-sensors = <&tsens1 5>; 6093 6094 trips { 6095 video_alert0: trip-point0 { 6096 temperature = <90000>; 6097 hysteresis = <2000>; 6098 type = "hot"; 6099 }; 6100 6101 video_crit: video-crit { 6102 temperature = <110000>; 6103 hysteresis = <0>; 6104 type = "critical"; 6105 }; 6106 }; 6107 }; 6108 6109 ddr-thermal { 6110 polling-delay-passive = <0>; 6111 polling-delay = <0>; 6112 6113 thermal-sensors = <&tsens1 6>; 6114 6115 trips { 6116 ddr_alert0: trip-point0 { 6117 temperature = <90000>; 6118 hysteresis = <2000>; 6119 type = "hot"; 6120 }; 6121 6122 ddr_crit: ddr-crit { 6123 temperature = <110000>; 6124 hysteresis = <0>; 6125 type = "critical"; 6126 }; 6127 }; 6128 }; 6129 6130 mdmss0-thermal { 6131 polling-delay-passive = <0>; 6132 polling-delay = <0>; 6133 6134 thermal-sensors = <&tsens1 7>; 6135 6136 trips { 6137 mdmss0_alert0: trip-point0 { 6138 temperature = <90000>; 6139 hysteresis = <2000>; 6140 type = "hot"; 6141 }; 6142 6143 mdmss0_crit: mdmss0-crit { 6144 temperature = <110000>; 6145 hysteresis = <0>; 6146 type = "critical"; 6147 }; 6148 }; 6149 }; 6150 6151 mdmss1-thermal { 6152 polling-delay-passive = <0>; 6153 polling-delay = <0>; 6154 6155 thermal-sensors = <&tsens1 8>; 6156 6157 trips { 6158 mdmss1_alert0: trip-point0 { 6159 temperature = <90000>; 6160 hysteresis = <2000>; 6161 type = "hot"; 6162 }; 6163 6164 mdmss1_crit: mdmss1-crit { 6165 temperature = <110000>; 6166 hysteresis = <0>; 6167 type = "critical"; 6168 }; 6169 }; 6170 }; 6171 6172 mdmss2-thermal { 6173 polling-delay-passive = <0>; 6174 polling-delay = <0>; 6175 6176 thermal-sensors = <&tsens1 9>; 6177 6178 trips { 6179 mdmss2_alert0: trip-point0 { 6180 temperature = <90000>; 6181 hysteresis = <2000>; 6182 type = "hot"; 6183 }; 6184 6185 mdmss2_crit: mdmss2-crit { 6186 temperature = <110000>; 6187 hysteresis = <0>; 6188 type = "critical"; 6189 }; 6190 }; 6191 }; 6192 6193 mdmss3-thermal { 6194 polling-delay-passive = <0>; 6195 polling-delay = <0>; 6196 6197 thermal-sensors = <&tsens1 10>; 6198 6199 trips { 6200 mdmss3_alert0: trip-point0 { 6201 temperature = <90000>; 6202 hysteresis = <2000>; 6203 type = "hot"; 6204 }; 6205 6206 mdmss3_crit: mdmss3-crit { 6207 temperature = <110000>; 6208 hysteresis = <0>; 6209 type = "critical"; 6210 }; 6211 }; 6212 }; 6213 6214 camera0-thermal { 6215 polling-delay-passive = <0>; 6216 polling-delay = <0>; 6217 6218 thermal-sensors = <&tsens1 11>; 6219 6220 trips { 6221 camera0_alert0: trip-point0 { 6222 temperature = <90000>; 6223 hysteresis = <2000>; 6224 type = "hot"; 6225 }; 6226 6227 camera0_crit: camera0-crit { 6228 temperature = <110000>; 6229 hysteresis = <0>; 6230 type = "critical"; 6231 }; 6232 }; 6233 }; 6234 }; 6235 6236 timer { 6237 compatible = "arm,armv8-timer"; 6238 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6239 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6240 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6241 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6242 }; 6243}; 6244