1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-aoss-qmp.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 clock-frequency = <76800000>; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32000>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 aop_mem: memory@80800000 { 45 reg = <0x0 0x80800000 0x0 0x60000>; 46 no-map; 47 }; 48 49 aop_cmd_db_mem: memory@80860000 { 50 reg = <0x0 0x80860000 0x0 0x20000>; 51 compatible = "qcom,cmd-db"; 52 no-map; 53 }; 54 55 cpucp_mem: memory@80b00000 { 56 no-map; 57 reg = <0x0 0x80b00000 0x0 0x100000>; 58 }; 59 }; 60 61 cpus { 62 #address-cells = <2>; 63 #size-cells = <0>; 64 65 CPU0: cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,kryo"; 68 reg = <0x0 0x0>; 69 enable-method = "psci"; 70 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 71 &LITTLE_CPU_SLEEP_1 72 &CLUSTER_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 L2_0: l2-cache { 76 compatible = "cache"; 77 next-level-cache = <&L3_0>; 78 L3_0: l3-cache { 79 compatible = "cache"; 80 }; 81 }; 82 }; 83 84 CPU1: cpu@100 { 85 device_type = "cpu"; 86 compatible = "arm,kryo"; 87 reg = <0x0 0x100>; 88 enable-method = "psci"; 89 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 90 &LITTLE_CPU_SLEEP_1 91 &CLUSTER_SLEEP_0>; 92 next-level-cache = <&L2_100>; 93 #cooling-cells = <2>; 94 L2_100: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "arm,kryo"; 103 reg = <0x0 0x200>; 104 enable-method = "psci"; 105 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 106 &LITTLE_CPU_SLEEP_1 107 &CLUSTER_SLEEP_0>; 108 next-level-cache = <&L2_200>; 109 #cooling-cells = <2>; 110 L2_200: l2-cache { 111 compatible = "cache"; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,kryo"; 119 reg = <0x0 0x300>; 120 enable-method = "psci"; 121 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 122 &LITTLE_CPU_SLEEP_1 123 &CLUSTER_SLEEP_0>; 124 next-level-cache = <&L2_300>; 125 #cooling-cells = <2>; 126 L2_300: l2-cache { 127 compatible = "cache"; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,kryo"; 135 reg = <0x0 0x400>; 136 enable-method = "psci"; 137 cpu-idle-states = <&BIG_CPU_SLEEP_0 138 &BIG_CPU_SLEEP_1 139 &CLUSTER_SLEEP_0>; 140 next-level-cache = <&L2_400>; 141 #cooling-cells = <2>; 142 L2_400: l2-cache { 143 compatible = "cache"; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,kryo"; 151 reg = <0x0 0x500>; 152 enable-method = "psci"; 153 cpu-idle-states = <&BIG_CPU_SLEEP_0 154 &BIG_CPU_SLEEP_1 155 &CLUSTER_SLEEP_0>; 156 next-level-cache = <&L2_500>; 157 #cooling-cells = <2>; 158 L2_500: l2-cache { 159 compatible = "cache"; 160 next-level-cache = <&L3_0>; 161 }; 162 }; 163 164 CPU6: cpu@600 { 165 device_type = "cpu"; 166 compatible = "arm,kryo"; 167 reg = <0x0 0x600>; 168 enable-method = "psci"; 169 cpu-idle-states = <&BIG_CPU_SLEEP_0 170 &BIG_CPU_SLEEP_1 171 &CLUSTER_SLEEP_0>; 172 next-level-cache = <&L2_600>; 173 #cooling-cells = <2>; 174 L2_600: l2-cache { 175 compatible = "cache"; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU7: cpu@700 { 181 device_type = "cpu"; 182 compatible = "arm,kryo"; 183 reg = <0x0 0x700>; 184 enable-method = "psci"; 185 cpu-idle-states = <&BIG_CPU_SLEEP_0 186 &BIG_CPU_SLEEP_1 187 &CLUSTER_SLEEP_0>; 188 next-level-cache = <&L2_700>; 189 #cooling-cells = <2>; 190 L2_700: l2-cache { 191 compatible = "cache"; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 idle-states { 197 entry-method = "psci"; 198 199 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 200 compatible = "arm,idle-state"; 201 idle-state-name = "little-power-down"; 202 arm,psci-suspend-param = <0x40000003>; 203 entry-latency-us = <549>; 204 exit-latency-us = <901>; 205 min-residency-us = <1774>; 206 local-timer-stop; 207 }; 208 209 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 210 compatible = "arm,idle-state"; 211 idle-state-name = "little-rail-power-down"; 212 arm,psci-suspend-param = <0x40000004>; 213 entry-latency-us = <702>; 214 exit-latency-us = <915>; 215 min-residency-us = <4001>; 216 local-timer-stop; 217 }; 218 219 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "big-power-down"; 222 arm,psci-suspend-param = <0x40000003>; 223 entry-latency-us = <523>; 224 exit-latency-us = <1244>; 225 min-residency-us = <2207>; 226 local-timer-stop; 227 }; 228 229 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 230 compatible = "arm,idle-state"; 231 idle-state-name = "big-rail-power-down"; 232 arm,psci-suspend-param = <0x40000004>; 233 entry-latency-us = <526>; 234 exit-latency-us = <1854>; 235 min-residency-us = <5555>; 236 local-timer-stop; 237 }; 238 239 CLUSTER_SLEEP_0: cluster-sleep-0 { 240 compatible = "arm,idle-state"; 241 idle-state-name = "cluster-power-down"; 242 arm,psci-suspend-param = <0x40003444>; 243 entry-latency-us = <3263>; 244 exit-latency-us = <6562>; 245 min-residency-us = <9926>; 246 local-timer-stop; 247 }; 248 }; 249 }; 250 251 memory@80000000 { 252 device_type = "memory"; 253 /* We expect the bootloader to fill in the size */ 254 reg = <0 0x80000000 0 0>; 255 }; 256 257 firmware { 258 scm { 259 compatible = "qcom,scm-sc7280", "qcom,scm"; 260 }; 261 }; 262 263 pmu { 264 compatible = "arm,armv8-pmuv3"; 265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 266 }; 267 268 psci { 269 compatible = "arm,psci-1.0"; 270 method = "smc"; 271 }; 272 273 soc: soc@0 { 274 #address-cells = <2>; 275 #size-cells = <2>; 276 ranges = <0 0 0 0 0x10 0>; 277 dma-ranges = <0 0 0 0 0x10 0>; 278 compatible = "simple-bus"; 279 280 gcc: clock-controller@100000 { 281 compatible = "qcom,gcc-sc7280"; 282 reg = <0 0x00100000 0 0x1f0000>; 283 clocks = <&rpmhcc RPMH_CXO_CLK>, 284 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 285 <0>, <0>, <0>, <0>, <0>, <0>; 286 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 287 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 288 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 289 "ufs_phy_tx_symbol_0_clk", 290 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 291 #clock-cells = <1>; 292 #reset-cells = <1>; 293 #power-domain-cells = <1>; 294 }; 295 296 ipcc: mailbox@408000 { 297 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 298 reg = <0 0x00408000 0 0x1000>; 299 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-controller; 301 #interrupt-cells = <3>; 302 #mbox-cells = <2>; 303 }; 304 305 qupv3_id_0: geniqup@9c0000 { 306 compatible = "qcom,geni-se-qup"; 307 reg = <0 0x009c0000 0 0x2000>; 308 clock-names = "m-ahb", "s-ahb"; 309 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 310 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 311 #address-cells = <2>; 312 #size-cells = <2>; 313 ranges; 314 status = "disabled"; 315 316 uart5: serial@994000 { 317 compatible = "qcom,geni-debug-uart"; 318 reg = <0 0x00994000 0 0x4000>; 319 clock-names = "se"; 320 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&qup_uart5_default>; 323 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 324 status = "disabled"; 325 }; 326 }; 327 328 stm@6002000 { 329 compatible = "arm,coresight-stm", "arm,primecell"; 330 reg = <0 0x06002000 0 0x1000>, 331 <0 0x16280000 0 0x180000>; 332 reg-names = "stm-base", "stm-stimulus-base"; 333 334 clocks = <&aoss_qmp>; 335 clock-names = "apb_pclk"; 336 337 out-ports { 338 port { 339 stm_out: endpoint { 340 remote-endpoint = <&funnel0_in7>; 341 }; 342 }; 343 }; 344 }; 345 346 funnel@6041000 { 347 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 348 reg = <0 0x06041000 0 0x1000>; 349 350 clocks = <&aoss_qmp>; 351 clock-names = "apb_pclk"; 352 353 out-ports { 354 port { 355 funnel0_out: endpoint { 356 remote-endpoint = <&merge_funnel_in0>; 357 }; 358 }; 359 }; 360 361 in-ports { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 port@7 { 366 reg = <7>; 367 funnel0_in7: endpoint { 368 remote-endpoint = <&stm_out>; 369 }; 370 }; 371 }; 372 }; 373 374 funnel@6042000 { 375 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 376 reg = <0 0x06042000 0 0x1000>; 377 378 clocks = <&aoss_qmp>; 379 clock-names = "apb_pclk"; 380 381 out-ports { 382 port { 383 funnel1_out: endpoint { 384 remote-endpoint = <&merge_funnel_in1>; 385 }; 386 }; 387 }; 388 389 in-ports { 390 #address-cells = <1>; 391 #size-cells = <0>; 392 393 port@4 { 394 reg = <4>; 395 funnel1_in4: endpoint { 396 remote-endpoint = <&apss_merge_funnel_out>; 397 }; 398 }; 399 }; 400 }; 401 402 funnel@6045000 { 403 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 404 reg = <0 0x06045000 0 0x1000>; 405 406 clocks = <&aoss_qmp>; 407 clock-names = "apb_pclk"; 408 409 out-ports { 410 port { 411 merge_funnel_out: endpoint { 412 remote-endpoint = <&swao_funnel_in>; 413 }; 414 }; 415 }; 416 417 in-ports { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 421 port@0 { 422 reg = <0>; 423 merge_funnel_in0: endpoint { 424 remote-endpoint = <&funnel0_out>; 425 }; 426 }; 427 428 port@1 { 429 reg = <1>; 430 merge_funnel_in1: endpoint { 431 remote-endpoint = <&funnel1_out>; 432 }; 433 }; 434 }; 435 }; 436 437 replicator@6046000 { 438 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 439 reg = <0 0x06046000 0 0x1000>; 440 441 clocks = <&aoss_qmp>; 442 clock-names = "apb_pclk"; 443 444 out-ports { 445 port { 446 replicator_out: endpoint { 447 remote-endpoint = <&etr_in>; 448 }; 449 }; 450 }; 451 452 in-ports { 453 port { 454 replicator_in: endpoint { 455 remote-endpoint = <&swao_replicator_out>; 456 }; 457 }; 458 }; 459 }; 460 461 etr@6048000 { 462 compatible = "arm,coresight-tmc", "arm,primecell"; 463 reg = <0 0x06048000 0 0x1000>; 464 iommus = <&apps_smmu 0x04c0 0>; 465 466 clocks = <&aoss_qmp>; 467 clock-names = "apb_pclk"; 468 arm,scatter-gather; 469 470 in-ports { 471 port { 472 etr_in: endpoint { 473 remote-endpoint = <&replicator_out>; 474 }; 475 }; 476 }; 477 }; 478 479 funnel@6b04000 { 480 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 481 reg = <0 0x06b04000 0 0x1000>; 482 483 clocks = <&aoss_qmp>; 484 clock-names = "apb_pclk"; 485 486 out-ports { 487 port { 488 swao_funnel_out: endpoint { 489 remote-endpoint = <&etf_in>; 490 }; 491 }; 492 }; 493 494 in-ports { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 498 port@7 { 499 reg = <7>; 500 swao_funnel_in: endpoint { 501 remote-endpoint = <&merge_funnel_out>; 502 }; 503 }; 504 }; 505 }; 506 507 etf@6b05000 { 508 compatible = "arm,coresight-tmc", "arm,primecell"; 509 reg = <0 0x06b05000 0 0x1000>; 510 511 clocks = <&aoss_qmp>; 512 clock-names = "apb_pclk"; 513 514 out-ports { 515 port { 516 etf_out: endpoint { 517 remote-endpoint = <&swao_replicator_in>; 518 }; 519 }; 520 }; 521 522 in-ports { 523 port { 524 etf_in: endpoint { 525 remote-endpoint = <&swao_funnel_out>; 526 }; 527 }; 528 }; 529 }; 530 531 replicator@6b06000 { 532 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 533 reg = <0 0x06b06000 0 0x1000>; 534 535 clocks = <&aoss_qmp>; 536 clock-names = "apb_pclk"; 537 qcom,replicator-loses-context; 538 539 out-ports { 540 port { 541 swao_replicator_out: endpoint { 542 remote-endpoint = <&replicator_in>; 543 }; 544 }; 545 }; 546 547 in-ports { 548 port { 549 swao_replicator_in: endpoint { 550 remote-endpoint = <&etf_out>; 551 }; 552 }; 553 }; 554 }; 555 556 etm@7040000 { 557 compatible = "arm,coresight-etm4x", "arm,primecell"; 558 reg = <0 0x07040000 0 0x1000>; 559 560 cpu = <&CPU0>; 561 562 clocks = <&aoss_qmp>; 563 clock-names = "apb_pclk"; 564 arm,coresight-loses-context-with-cpu; 565 qcom,skip-power-up; 566 567 out-ports { 568 port { 569 etm0_out: endpoint { 570 remote-endpoint = <&apss_funnel_in0>; 571 }; 572 }; 573 }; 574 }; 575 576 etm@7140000 { 577 compatible = "arm,coresight-etm4x", "arm,primecell"; 578 reg = <0 0x07140000 0 0x1000>; 579 580 cpu = <&CPU1>; 581 582 clocks = <&aoss_qmp>; 583 clock-names = "apb_pclk"; 584 arm,coresight-loses-context-with-cpu; 585 qcom,skip-power-up; 586 587 out-ports { 588 port { 589 etm1_out: endpoint { 590 remote-endpoint = <&apss_funnel_in1>; 591 }; 592 }; 593 }; 594 }; 595 596 etm@7240000 { 597 compatible = "arm,coresight-etm4x", "arm,primecell"; 598 reg = <0 0x07240000 0 0x1000>; 599 600 cpu = <&CPU2>; 601 602 clocks = <&aoss_qmp>; 603 clock-names = "apb_pclk"; 604 arm,coresight-loses-context-with-cpu; 605 qcom,skip-power-up; 606 607 out-ports { 608 port { 609 etm2_out: endpoint { 610 remote-endpoint = <&apss_funnel_in2>; 611 }; 612 }; 613 }; 614 }; 615 616 etm@7340000 { 617 compatible = "arm,coresight-etm4x", "arm,primecell"; 618 reg = <0 0x07340000 0 0x1000>; 619 620 cpu = <&CPU3>; 621 622 clocks = <&aoss_qmp>; 623 clock-names = "apb_pclk"; 624 arm,coresight-loses-context-with-cpu; 625 qcom,skip-power-up; 626 627 out-ports { 628 port { 629 etm3_out: endpoint { 630 remote-endpoint = <&apss_funnel_in3>; 631 }; 632 }; 633 }; 634 }; 635 636 etm@7440000 { 637 compatible = "arm,coresight-etm4x", "arm,primecell"; 638 reg = <0 0x07440000 0 0x1000>; 639 640 cpu = <&CPU4>; 641 642 clocks = <&aoss_qmp>; 643 clock-names = "apb_pclk"; 644 arm,coresight-loses-context-with-cpu; 645 qcom,skip-power-up; 646 647 out-ports { 648 port { 649 etm4_out: endpoint { 650 remote-endpoint = <&apss_funnel_in4>; 651 }; 652 }; 653 }; 654 }; 655 656 etm@7540000 { 657 compatible = "arm,coresight-etm4x", "arm,primecell"; 658 reg = <0 0x07540000 0 0x1000>; 659 660 cpu = <&CPU5>; 661 662 clocks = <&aoss_qmp>; 663 clock-names = "apb_pclk"; 664 arm,coresight-loses-context-with-cpu; 665 qcom,skip-power-up; 666 667 out-ports { 668 port { 669 etm5_out: endpoint { 670 remote-endpoint = <&apss_funnel_in5>; 671 }; 672 }; 673 }; 674 }; 675 676 etm@7640000 { 677 compatible = "arm,coresight-etm4x", "arm,primecell"; 678 reg = <0 0x07640000 0 0x1000>; 679 680 cpu = <&CPU6>; 681 682 clocks = <&aoss_qmp>; 683 clock-names = "apb_pclk"; 684 arm,coresight-loses-context-with-cpu; 685 qcom,skip-power-up; 686 687 out-ports { 688 port { 689 etm6_out: endpoint { 690 remote-endpoint = <&apss_funnel_in6>; 691 }; 692 }; 693 }; 694 }; 695 696 etm@7740000 { 697 compatible = "arm,coresight-etm4x", "arm,primecell"; 698 reg = <0 0x07740000 0 0x1000>; 699 700 cpu = <&CPU7>; 701 702 clocks = <&aoss_qmp>; 703 clock-names = "apb_pclk"; 704 arm,coresight-loses-context-with-cpu; 705 qcom,skip-power-up; 706 707 out-ports { 708 port { 709 etm7_out: endpoint { 710 remote-endpoint = <&apss_funnel_in7>; 711 }; 712 }; 713 }; 714 }; 715 716 funnel@7800000 { /* APSS Funnel */ 717 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 718 reg = <0 0x07800000 0 0x1000>; 719 720 clocks = <&aoss_qmp>; 721 clock-names = "apb_pclk"; 722 723 out-ports { 724 port { 725 apss_funnel_out: endpoint { 726 remote-endpoint = <&apss_merge_funnel_in>; 727 }; 728 }; 729 }; 730 731 in-ports { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 735 port@0 { 736 reg = <0>; 737 apss_funnel_in0: endpoint { 738 remote-endpoint = <&etm0_out>; 739 }; 740 }; 741 742 port@1 { 743 reg = <1>; 744 apss_funnel_in1: endpoint { 745 remote-endpoint = <&etm1_out>; 746 }; 747 }; 748 749 port@2 { 750 reg = <2>; 751 apss_funnel_in2: endpoint { 752 remote-endpoint = <&etm2_out>; 753 }; 754 }; 755 756 port@3 { 757 reg = <3>; 758 apss_funnel_in3: endpoint { 759 remote-endpoint = <&etm3_out>; 760 }; 761 }; 762 763 port@4 { 764 reg = <4>; 765 apss_funnel_in4: endpoint { 766 remote-endpoint = <&etm4_out>; 767 }; 768 }; 769 770 port@5 { 771 reg = <5>; 772 apss_funnel_in5: endpoint { 773 remote-endpoint = <&etm5_out>; 774 }; 775 }; 776 777 port@6 { 778 reg = <6>; 779 apss_funnel_in6: endpoint { 780 remote-endpoint = <&etm6_out>; 781 }; 782 }; 783 784 port@7 { 785 reg = <7>; 786 apss_funnel_in7: endpoint { 787 remote-endpoint = <&etm7_out>; 788 }; 789 }; 790 }; 791 }; 792 793 funnel@7810000 { 794 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 795 reg = <0 0x07810000 0 0x1000>; 796 797 clocks = <&aoss_qmp>; 798 clock-names = "apb_pclk"; 799 800 out-ports { 801 port { 802 apss_merge_funnel_out: endpoint { 803 remote-endpoint = <&funnel1_in4>; 804 }; 805 }; 806 }; 807 808 in-ports { 809 port { 810 apss_merge_funnel_in: endpoint { 811 remote-endpoint = <&apss_funnel_out>; 812 }; 813 }; 814 }; 815 }; 816 817 system-cache-controller@9200000 { 818 compatible = "qcom,sc7280-llcc"; 819 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 820 reg-names = "llcc_base", "llcc_broadcast_base"; 821 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 822 }; 823 824 pdc: interrupt-controller@b220000 { 825 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 826 reg = <0 0x0b220000 0 0x30000>; 827 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 828 <55 306 4>, <59 312 3>, <62 374 2>, 829 <64 434 2>, <66 438 3>, <69 86 1>, 830 <70 520 54>, <124 609 31>, <155 63 1>, 831 <156 716 12>; 832 #interrupt-cells = <2>; 833 interrupt-parent = <&intc>; 834 interrupt-controller; 835 }; 836 837 tsens0: thermal-sensor@c263000 { 838 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 839 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 840 <0 0x0c222000 0 0x1ff>; /* SROT */ 841 #qcom,sensors = <15>; 842 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 844 interrupt-names = "uplow","critical"; 845 #thermal-sensor-cells = <1>; 846 }; 847 848 tsens1: thermal-sensor@c265000 { 849 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 850 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 851 <0 0x0c223000 0 0x1ff>; /* SROT */ 852 #qcom,sensors = <12>; 853 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "uplow","critical"; 856 #thermal-sensor-cells = <1>; 857 }; 858 859 aoss_qmp: power-controller@c300000 { 860 compatible = "qcom,sc7280-aoss-qmp"; 861 reg = <0 0x0c300000 0 0x100000>; 862 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 863 IPCC_MPROC_SIGNAL_GLINK_QMP 864 IRQ_TYPE_EDGE_RISING>; 865 mboxes = <&ipcc IPCC_CLIENT_AOP 866 IPCC_MPROC_SIGNAL_GLINK_QMP>; 867 868 #clock-cells = <0>; 869 #power-domain-cells = <1>; 870 }; 871 872 spmi_bus: spmi@c440000 { 873 compatible = "qcom,spmi-pmic-arb"; 874 reg = <0 0x0c440000 0 0x1100>, 875 <0 0x0c600000 0 0x2000000>, 876 <0 0x0e600000 0 0x100000>, 877 <0 0x0e700000 0 0xa0000>, 878 <0 0x0c40a000 0 0x26000>; 879 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 880 interrupt-names = "periph_irq"; 881 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 882 qcom,ee = <0>; 883 qcom,channel = <0>; 884 #address-cells = <1>; 885 #size-cells = <1>; 886 interrupt-controller; 887 #interrupt-cells = <4>; 888 }; 889 890 tlmm: pinctrl@f100000 { 891 compatible = "qcom,sc7280-pinctrl"; 892 reg = <0 0x0f100000 0 0x300000>; 893 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 894 gpio-controller; 895 #gpio-cells = <2>; 896 interrupt-controller; 897 #interrupt-cells = <2>; 898 gpio-ranges = <&tlmm 0 0 175>; 899 wakeup-parent = <&pdc>; 900 901 qup_uart5_default: qup-uart5-default { 902 pins = "gpio46", "gpio47"; 903 function = "qup13"; 904 }; 905 }; 906 907 apps_smmu: iommu@15000000 { 908 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 909 reg = <0 0x15000000 0 0x100000>; 910 #iommu-cells = <2>; 911 #global-interrupts = <1>; 912 dma-coherent; 913 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 994 }; 995 996 intc: interrupt-controller@17a00000 { 997 compatible = "arm,gic-v3"; 998 #address-cells = <2>; 999 #size-cells = <2>; 1000 ranges; 1001 #interrupt-cells = <3>; 1002 interrupt-controller; 1003 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1004 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1005 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1006 1007 gic-its@17a40000 { 1008 compatible = "arm,gic-v3-its"; 1009 msi-controller; 1010 #msi-cells = <1>; 1011 reg = <0 0x17a40000 0 0x20000>; 1012 status = "disabled"; 1013 }; 1014 }; 1015 1016 watchdog@17c10000 { 1017 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1018 reg = <0 0x17c10000 0 0x1000>; 1019 clocks = <&sleep_clk>; 1020 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1021 }; 1022 1023 timer@17c20000 { 1024 #address-cells = <2>; 1025 #size-cells = <2>; 1026 ranges; 1027 compatible = "arm,armv7-timer-mem"; 1028 reg = <0 0x17c20000 0 0x1000>; 1029 1030 frame@17c21000 { 1031 frame-number = <0>; 1032 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1034 reg = <0 0x17c21000 0 0x1000>, 1035 <0 0x17c22000 0 0x1000>; 1036 }; 1037 1038 frame@17c23000 { 1039 frame-number = <1>; 1040 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1041 reg = <0 0x17c23000 0 0x1000>; 1042 status = "disabled"; 1043 }; 1044 1045 frame@17c25000 { 1046 frame-number = <2>; 1047 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1048 reg = <0 0x17c25000 0 0x1000>; 1049 status = "disabled"; 1050 }; 1051 1052 frame@17c27000 { 1053 frame-number = <3>; 1054 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1055 reg = <0 0x17c27000 0 0x1000>; 1056 status = "disabled"; 1057 }; 1058 1059 frame@17c29000 { 1060 frame-number = <4>; 1061 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1062 reg = <0 0x17c29000 0 0x1000>; 1063 status = "disabled"; 1064 }; 1065 1066 frame@17c2b000 { 1067 frame-number = <5>; 1068 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1069 reg = <0 0x17c2b000 0 0x1000>; 1070 status = "disabled"; 1071 }; 1072 1073 frame@17c2d000 { 1074 frame-number = <6>; 1075 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1076 reg = <0 0x17c2d000 0 0x1000>; 1077 status = "disabled"; 1078 }; 1079 }; 1080 1081 apps_rsc: rsc@18200000 { 1082 compatible = "qcom,rpmh-rsc"; 1083 reg = <0 0x18200000 0 0x10000>, 1084 <0 0x18210000 0 0x10000>, 1085 <0 0x18220000 0 0x10000>; 1086 reg-names = "drv-0", "drv-1", "drv-2"; 1087 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1090 qcom,tcs-offset = <0xd00>; 1091 qcom,drv-id = <2>; 1092 qcom,tcs-config = <ACTIVE_TCS 2>, 1093 <SLEEP_TCS 3>, 1094 <WAKE_TCS 3>, 1095 <CONTROL_TCS 1>; 1096 1097 rpmhpd: power-controller { 1098 compatible = "qcom,sc7280-rpmhpd"; 1099 #power-domain-cells = <1>; 1100 operating-points-v2 = <&rpmhpd_opp_table>; 1101 1102 rpmhpd_opp_table: opp-table { 1103 compatible = "operating-points-v2"; 1104 1105 rpmhpd_opp_ret: opp1 { 1106 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1107 }; 1108 1109 rpmhpd_opp_low_svs: opp2 { 1110 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1111 }; 1112 1113 rpmhpd_opp_svs: opp3 { 1114 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1115 }; 1116 1117 rpmhpd_opp_svs_l1: opp4 { 1118 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1119 }; 1120 1121 rpmhpd_opp_svs_l2: opp5 { 1122 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1123 }; 1124 1125 rpmhpd_opp_nom: opp6 { 1126 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1127 }; 1128 1129 rpmhpd_opp_nom_l1: opp7 { 1130 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1131 }; 1132 1133 rpmhpd_opp_turbo: opp8 { 1134 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1135 }; 1136 1137 rpmhpd_opp_turbo_l1: opp9 { 1138 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1139 }; 1140 }; 1141 }; 1142 1143 rpmhcc: clock-controller { 1144 compatible = "qcom,sc7280-rpmh-clk"; 1145 clocks = <&xo_board>; 1146 clock-names = "xo"; 1147 #clock-cells = <1>; 1148 }; 1149 }; 1150 }; 1151 1152 thermal_zones: thermal-zones { 1153 cpu0-thermal { 1154 polling-delay-passive = <250>; 1155 polling-delay = <0>; 1156 1157 thermal-sensors = <&tsens0 1>; 1158 1159 trips { 1160 cpu0_alert0: trip-point0 { 1161 temperature = <90000>; 1162 hysteresis = <2000>; 1163 type = "passive"; 1164 }; 1165 1166 cpu0_alert1: trip-point1 { 1167 temperature = <95000>; 1168 hysteresis = <2000>; 1169 type = "passive"; 1170 }; 1171 1172 cpu0_crit: cpu-crit { 1173 temperature = <110000>; 1174 hysteresis = <0>; 1175 type = "critical"; 1176 }; 1177 }; 1178 1179 cooling-maps { 1180 map0 { 1181 trip = <&cpu0_alert0>; 1182 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1183 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1184 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1185 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1186 }; 1187 map1 { 1188 trip = <&cpu0_alert1>; 1189 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1190 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1191 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1192 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1193 }; 1194 }; 1195 }; 1196 1197 cpu1-thermal { 1198 polling-delay-passive = <250>; 1199 polling-delay = <0>; 1200 1201 thermal-sensors = <&tsens0 2>; 1202 1203 trips { 1204 cpu1_alert0: trip-point0 { 1205 temperature = <90000>; 1206 hysteresis = <2000>; 1207 type = "passive"; 1208 }; 1209 1210 cpu1_alert1: trip-point1 { 1211 temperature = <95000>; 1212 hysteresis = <2000>; 1213 type = "passive"; 1214 }; 1215 1216 cpu1_crit: cpu-crit { 1217 temperature = <110000>; 1218 hysteresis = <0>; 1219 type = "critical"; 1220 }; 1221 }; 1222 1223 cooling-maps { 1224 map0 { 1225 trip = <&cpu1_alert0>; 1226 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1227 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1228 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1229 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1230 }; 1231 map1 { 1232 trip = <&cpu1_alert1>; 1233 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1234 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1235 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1236 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1237 }; 1238 }; 1239 }; 1240 1241 cpu2-thermal { 1242 polling-delay-passive = <250>; 1243 polling-delay = <0>; 1244 1245 thermal-sensors = <&tsens0 3>; 1246 1247 trips { 1248 cpu2_alert0: trip-point0 { 1249 temperature = <90000>; 1250 hysteresis = <2000>; 1251 type = "passive"; 1252 }; 1253 1254 cpu2_alert1: trip-point1 { 1255 temperature = <95000>; 1256 hysteresis = <2000>; 1257 type = "passive"; 1258 }; 1259 1260 cpu2_crit: cpu-crit { 1261 temperature = <110000>; 1262 hysteresis = <0>; 1263 type = "critical"; 1264 }; 1265 }; 1266 1267 cooling-maps { 1268 map0 { 1269 trip = <&cpu2_alert0>; 1270 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1271 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1272 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1273 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1274 }; 1275 map1 { 1276 trip = <&cpu2_alert1>; 1277 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1278 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1279 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1280 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1281 }; 1282 }; 1283 }; 1284 1285 cpu3-thermal { 1286 polling-delay-passive = <250>; 1287 polling-delay = <0>; 1288 1289 thermal-sensors = <&tsens0 4>; 1290 1291 trips { 1292 cpu3_alert0: trip-point0 { 1293 temperature = <90000>; 1294 hysteresis = <2000>; 1295 type = "passive"; 1296 }; 1297 1298 cpu3_alert1: trip-point1 { 1299 temperature = <95000>; 1300 hysteresis = <2000>; 1301 type = "passive"; 1302 }; 1303 1304 cpu3_crit: cpu-crit { 1305 temperature = <110000>; 1306 hysteresis = <0>; 1307 type = "critical"; 1308 }; 1309 }; 1310 1311 cooling-maps { 1312 map0 { 1313 trip = <&cpu3_alert0>; 1314 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1315 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1316 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1317 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1318 }; 1319 map1 { 1320 trip = <&cpu3_alert1>; 1321 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1322 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1323 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1324 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1325 }; 1326 }; 1327 }; 1328 1329 cpu4-thermal { 1330 polling-delay-passive = <250>; 1331 polling-delay = <0>; 1332 1333 thermal-sensors = <&tsens0 7>; 1334 1335 trips { 1336 cpu4_alert0: trip-point0 { 1337 temperature = <90000>; 1338 hysteresis = <2000>; 1339 type = "passive"; 1340 }; 1341 1342 cpu4_alert1: trip-point1 { 1343 temperature = <95000>; 1344 hysteresis = <2000>; 1345 type = "passive"; 1346 }; 1347 1348 cpu4_crit: cpu-crit { 1349 temperature = <110000>; 1350 hysteresis = <0>; 1351 type = "critical"; 1352 }; 1353 }; 1354 1355 cooling-maps { 1356 map0 { 1357 trip = <&cpu4_alert0>; 1358 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1359 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1360 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1361 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1362 }; 1363 map1 { 1364 trip = <&cpu4_alert1>; 1365 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1366 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1367 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1368 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1369 }; 1370 }; 1371 }; 1372 1373 cpu5-thermal { 1374 polling-delay-passive = <250>; 1375 polling-delay = <0>; 1376 1377 thermal-sensors = <&tsens0 8>; 1378 1379 trips { 1380 cpu5_alert0: trip-point0 { 1381 temperature = <90000>; 1382 hysteresis = <2000>; 1383 type = "passive"; 1384 }; 1385 1386 cpu5_alert1: trip-point1 { 1387 temperature = <95000>; 1388 hysteresis = <2000>; 1389 type = "passive"; 1390 }; 1391 1392 cpu5_crit: cpu-crit { 1393 temperature = <110000>; 1394 hysteresis = <0>; 1395 type = "critical"; 1396 }; 1397 }; 1398 1399 cooling-maps { 1400 map0 { 1401 trip = <&cpu5_alert0>; 1402 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1403 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1404 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1405 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1406 }; 1407 map1 { 1408 trip = <&cpu5_alert1>; 1409 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1410 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1411 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1412 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1413 }; 1414 }; 1415 }; 1416 1417 cpu6-thermal { 1418 polling-delay-passive = <250>; 1419 polling-delay = <0>; 1420 1421 thermal-sensors = <&tsens0 9>; 1422 1423 trips { 1424 cpu6_alert0: trip-point0 { 1425 temperature = <90000>; 1426 hysteresis = <2000>; 1427 type = "passive"; 1428 }; 1429 1430 cpu6_alert1: trip-point1 { 1431 temperature = <95000>; 1432 hysteresis = <2000>; 1433 type = "passive"; 1434 }; 1435 1436 cpu6_crit: cpu-crit { 1437 temperature = <110000>; 1438 hysteresis = <0>; 1439 type = "critical"; 1440 }; 1441 }; 1442 1443 cooling-maps { 1444 map0 { 1445 trip = <&cpu6_alert0>; 1446 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1447 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1448 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1449 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1450 }; 1451 map1 { 1452 trip = <&cpu6_alert1>; 1453 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1454 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1455 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1456 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1457 }; 1458 }; 1459 }; 1460 1461 cpu7-thermal { 1462 polling-delay-passive = <250>; 1463 polling-delay = <0>; 1464 1465 thermal-sensors = <&tsens0 10>; 1466 1467 trips { 1468 cpu7_alert0: trip-point0 { 1469 temperature = <90000>; 1470 hysteresis = <2000>; 1471 type = "passive"; 1472 }; 1473 1474 cpu7_alert1: trip-point1 { 1475 temperature = <95000>; 1476 hysteresis = <2000>; 1477 type = "passive"; 1478 }; 1479 1480 cpu7_crit: cpu-crit { 1481 temperature = <110000>; 1482 hysteresis = <0>; 1483 type = "critical"; 1484 }; 1485 }; 1486 1487 cooling-maps { 1488 map0 { 1489 trip = <&cpu7_alert0>; 1490 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1491 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1492 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1493 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1494 }; 1495 map1 { 1496 trip = <&cpu7_alert1>; 1497 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1498 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1499 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1500 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1501 }; 1502 }; 1503 }; 1504 1505 cpu8-thermal { 1506 polling-delay-passive = <250>; 1507 polling-delay = <0>; 1508 1509 thermal-sensors = <&tsens0 11>; 1510 1511 trips { 1512 cpu8_alert0: trip-point0 { 1513 temperature = <90000>; 1514 hysteresis = <2000>; 1515 type = "passive"; 1516 }; 1517 1518 cpu8_alert1: trip-point1 { 1519 temperature = <95000>; 1520 hysteresis = <2000>; 1521 type = "passive"; 1522 }; 1523 1524 cpu8_crit: cpu-crit { 1525 temperature = <110000>; 1526 hysteresis = <0>; 1527 type = "critical"; 1528 }; 1529 }; 1530 1531 cooling-maps { 1532 map0 { 1533 trip = <&cpu8_alert0>; 1534 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1535 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1536 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1537 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1538 }; 1539 map1 { 1540 trip = <&cpu8_alert1>; 1541 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1542 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1543 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1544 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1545 }; 1546 }; 1547 }; 1548 1549 cpu9-thermal { 1550 polling-delay-passive = <250>; 1551 polling-delay = <0>; 1552 1553 thermal-sensors = <&tsens0 12>; 1554 1555 trips { 1556 cpu9_alert0: trip-point0 { 1557 temperature = <90000>; 1558 hysteresis = <2000>; 1559 type = "passive"; 1560 }; 1561 1562 cpu9_alert1: trip-point1 { 1563 temperature = <95000>; 1564 hysteresis = <2000>; 1565 type = "passive"; 1566 }; 1567 1568 cpu9_crit: cpu-crit { 1569 temperature = <110000>; 1570 hysteresis = <0>; 1571 type = "critical"; 1572 }; 1573 }; 1574 1575 cooling-maps { 1576 map0 { 1577 trip = <&cpu9_alert0>; 1578 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1579 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1580 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1581 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1582 }; 1583 map1 { 1584 trip = <&cpu9_alert1>; 1585 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1586 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1587 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1588 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1589 }; 1590 }; 1591 }; 1592 1593 cpu10-thermal { 1594 polling-delay-passive = <250>; 1595 polling-delay = <0>; 1596 1597 thermal-sensors = <&tsens0 13>; 1598 1599 trips { 1600 cpu10_alert0: trip-point0 { 1601 temperature = <90000>; 1602 hysteresis = <2000>; 1603 type = "passive"; 1604 }; 1605 1606 cpu10_alert1: trip-point1 { 1607 temperature = <95000>; 1608 hysteresis = <2000>; 1609 type = "passive"; 1610 }; 1611 1612 cpu10_crit: cpu-crit { 1613 temperature = <110000>; 1614 hysteresis = <0>; 1615 type = "critical"; 1616 }; 1617 }; 1618 1619 cooling-maps { 1620 map0 { 1621 trip = <&cpu10_alert0>; 1622 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1623 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1624 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1625 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1626 }; 1627 map1 { 1628 trip = <&cpu10_alert1>; 1629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1630 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1631 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1632 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1633 }; 1634 }; 1635 }; 1636 1637 cpu11-thermal { 1638 polling-delay-passive = <250>; 1639 polling-delay = <0>; 1640 1641 thermal-sensors = <&tsens0 14>; 1642 1643 trips { 1644 cpu11_alert0: trip-point0 { 1645 temperature = <90000>; 1646 hysteresis = <2000>; 1647 type = "passive"; 1648 }; 1649 1650 cpu11_alert1: trip-point1 { 1651 temperature = <95000>; 1652 hysteresis = <2000>; 1653 type = "passive"; 1654 }; 1655 1656 cpu11_crit: cpu-crit { 1657 temperature = <110000>; 1658 hysteresis = <0>; 1659 type = "critical"; 1660 }; 1661 }; 1662 1663 cooling-maps { 1664 map0 { 1665 trip = <&cpu11_alert0>; 1666 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1667 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1668 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1669 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1670 }; 1671 map1 { 1672 trip = <&cpu11_alert1>; 1673 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1674 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1675 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1676 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1677 }; 1678 }; 1679 }; 1680 1681 aoss0-thermal { 1682 polling-delay-passive = <0>; 1683 polling-delay = <0>; 1684 1685 thermal-sensors = <&tsens0 0>; 1686 1687 trips { 1688 aoss0_alert0: trip-point0 { 1689 temperature = <90000>; 1690 hysteresis = <2000>; 1691 type = "hot"; 1692 }; 1693 1694 aoss0_crit: aoss0-crit { 1695 temperature = <110000>; 1696 hysteresis = <0>; 1697 type = "critical"; 1698 }; 1699 }; 1700 }; 1701 1702 aoss1-thermal { 1703 polling-delay-passive = <0>; 1704 polling-delay = <0>; 1705 1706 thermal-sensors = <&tsens1 0>; 1707 1708 trips { 1709 aoss1_alert0: trip-point0 { 1710 temperature = <90000>; 1711 hysteresis = <2000>; 1712 type = "hot"; 1713 }; 1714 1715 aoss1_crit: aoss1-crit { 1716 temperature = <110000>; 1717 hysteresis = <0>; 1718 type = "critical"; 1719 }; 1720 }; 1721 }; 1722 1723 cpuss0-thermal { 1724 polling-delay-passive = <0>; 1725 polling-delay = <0>; 1726 1727 thermal-sensors = <&tsens0 5>; 1728 1729 trips { 1730 cpuss0_alert0: trip-point0 { 1731 temperature = <90000>; 1732 hysteresis = <2000>; 1733 type = "hot"; 1734 }; 1735 cpuss0_crit: cluster0-crit { 1736 temperature = <110000>; 1737 hysteresis = <0>; 1738 type = "critical"; 1739 }; 1740 }; 1741 }; 1742 1743 cpuss1-thermal { 1744 polling-delay-passive = <0>; 1745 polling-delay = <0>; 1746 1747 thermal-sensors = <&tsens0 6>; 1748 1749 trips { 1750 cpuss1_alert0: trip-point0 { 1751 temperature = <90000>; 1752 hysteresis = <2000>; 1753 type = "hot"; 1754 }; 1755 cpuss1_crit: cluster0-crit { 1756 temperature = <110000>; 1757 hysteresis = <0>; 1758 type = "critical"; 1759 }; 1760 }; 1761 }; 1762 1763 gpuss0-thermal { 1764 polling-delay-passive = <0>; 1765 polling-delay = <0>; 1766 1767 thermal-sensors = <&tsens1 1>; 1768 1769 trips { 1770 gpuss0_alert0: trip-point0 { 1771 temperature = <90000>; 1772 hysteresis = <2000>; 1773 type = "hot"; 1774 }; 1775 1776 gpuss0_crit: gpuss0-crit { 1777 temperature = <110000>; 1778 hysteresis = <0>; 1779 type = "critical"; 1780 }; 1781 }; 1782 }; 1783 1784 gpuss1-thermal { 1785 polling-delay-passive = <0>; 1786 polling-delay = <0>; 1787 1788 thermal-sensors = <&tsens1 2>; 1789 1790 trips { 1791 gpuss1_alert0: trip-point0 { 1792 temperature = <90000>; 1793 hysteresis = <2000>; 1794 type = "hot"; 1795 }; 1796 1797 gpuss1_crit: gpuss1-crit { 1798 temperature = <110000>; 1799 hysteresis = <0>; 1800 type = "critical"; 1801 }; 1802 }; 1803 }; 1804 1805 nspss0-thermal { 1806 polling-delay-passive = <0>; 1807 polling-delay = <0>; 1808 1809 thermal-sensors = <&tsens1 3>; 1810 1811 trips { 1812 nspss0_alert0: trip-point0 { 1813 temperature = <90000>; 1814 hysteresis = <2000>; 1815 type = "hot"; 1816 }; 1817 1818 nspss0_crit: nspss0-crit { 1819 temperature = <110000>; 1820 hysteresis = <0>; 1821 type = "critical"; 1822 }; 1823 }; 1824 }; 1825 1826 nspss1-thermal { 1827 polling-delay-passive = <0>; 1828 polling-delay = <0>; 1829 1830 thermal-sensors = <&tsens1 4>; 1831 1832 trips { 1833 nspss1_alert0: trip-point0 { 1834 temperature = <90000>; 1835 hysteresis = <2000>; 1836 type = "hot"; 1837 }; 1838 1839 nspss1_crit: nspss1-crit { 1840 temperature = <110000>; 1841 hysteresis = <0>; 1842 type = "critical"; 1843 }; 1844 }; 1845 }; 1846 1847 video-thermal { 1848 polling-delay-passive = <0>; 1849 polling-delay = <0>; 1850 1851 thermal-sensors = <&tsens1 5>; 1852 1853 trips { 1854 video_alert0: trip-point0 { 1855 temperature = <90000>; 1856 hysteresis = <2000>; 1857 type = "hot"; 1858 }; 1859 1860 video_crit: video-crit { 1861 temperature = <110000>; 1862 hysteresis = <0>; 1863 type = "critical"; 1864 }; 1865 }; 1866 }; 1867 1868 ddr-thermal { 1869 polling-delay-passive = <0>; 1870 polling-delay = <0>; 1871 1872 thermal-sensors = <&tsens1 6>; 1873 1874 trips { 1875 ddr_alert0: trip-point0 { 1876 temperature = <90000>; 1877 hysteresis = <2000>; 1878 type = "hot"; 1879 }; 1880 1881 ddr_crit: ddr-crit { 1882 temperature = <110000>; 1883 hysteresis = <0>; 1884 type = "critical"; 1885 }; 1886 }; 1887 }; 1888 1889 mdmss0-thermal { 1890 polling-delay-passive = <0>; 1891 polling-delay = <0>; 1892 1893 thermal-sensors = <&tsens1 7>; 1894 1895 trips { 1896 mdmss0_alert0: trip-point0 { 1897 temperature = <90000>; 1898 hysteresis = <2000>; 1899 type = "hot"; 1900 }; 1901 1902 mdmss0_crit: mdmss0-crit { 1903 temperature = <110000>; 1904 hysteresis = <0>; 1905 type = "critical"; 1906 }; 1907 }; 1908 }; 1909 1910 mdmss1-thermal { 1911 polling-delay-passive = <0>; 1912 polling-delay = <0>; 1913 1914 thermal-sensors = <&tsens1 8>; 1915 1916 trips { 1917 mdmss1_alert0: trip-point0 { 1918 temperature = <90000>; 1919 hysteresis = <2000>; 1920 type = "hot"; 1921 }; 1922 1923 mdmss1_crit: mdmss1-crit { 1924 temperature = <110000>; 1925 hysteresis = <0>; 1926 type = "critical"; 1927 }; 1928 }; 1929 }; 1930 1931 mdmss2-thermal { 1932 polling-delay-passive = <0>; 1933 polling-delay = <0>; 1934 1935 thermal-sensors = <&tsens1 9>; 1936 1937 trips { 1938 mdmss2_alert0: trip-point0 { 1939 temperature = <90000>; 1940 hysteresis = <2000>; 1941 type = "hot"; 1942 }; 1943 1944 mdmss2_crit: mdmss2-crit { 1945 temperature = <110000>; 1946 hysteresis = <0>; 1947 type = "critical"; 1948 }; 1949 }; 1950 }; 1951 1952 mdmss3-thermal { 1953 polling-delay-passive = <0>; 1954 polling-delay = <0>; 1955 1956 thermal-sensors = <&tsens1 10>; 1957 1958 trips { 1959 mdmss3_alert0: trip-point0 { 1960 temperature = <90000>; 1961 hysteresis = <2000>; 1962 type = "hot"; 1963 }; 1964 1965 mdmss3_crit: mdmss3-crit { 1966 temperature = <110000>; 1967 hysteresis = <0>; 1968 type = "critical"; 1969 }; 1970 }; 1971 }; 1972 1973 camera0-thermal { 1974 polling-delay-passive = <0>; 1975 polling-delay = <0>; 1976 1977 thermal-sensors = <&tsens1 11>; 1978 1979 trips { 1980 camera0_alert0: trip-point0 { 1981 temperature = <90000>; 1982 hysteresis = <2000>; 1983 type = "hot"; 1984 }; 1985 1986 camera0_crit: camera0-crit { 1987 temperature = <110000>; 1988 hysteresis = <0>; 1989 type = "critical"; 1990 }; 1991 }; 1992 }; 1993 }; 1994 1995 timer { 1996 compatible = "arm,armv8-timer"; 1997 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1998 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1999 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2000 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2001 }; 2002}; 2003