1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 aop_mem: memory@80800000 { 56 reg = <0x0 0x80800000 0x0 0x60000>; 57 no-map; 58 }; 59 60 aop_cmd_db_mem: memory@80860000 { 61 reg = <0x0 0x80860000 0x0 0x20000>; 62 compatible = "qcom,cmd-db"; 63 no-map; 64 }; 65 66 smem_mem: memory@80900000 { 67 reg = <0x0 0x80900000 0x0 0x200000>; 68 no-map; 69 }; 70 71 cpucp_mem: memory@80b00000 { 72 no-map; 73 reg = <0x0 0x80b00000 0x0 0x100000>; 74 }; 75 76 ipa_fw_mem: memory@8b700000 { 77 reg = <0 0x8b700000 0 0x10000>; 78 no-map; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <2>; 84 #size-cells = <0>; 85 86 CPU0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,kryo"; 89 reg = <0x0 0x0>; 90 enable-method = "psci"; 91 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 92 &LITTLE_CPU_SLEEP_1 93 &CLUSTER_SLEEP_0>; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_0: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 L3_0: l3-cache { 101 compatible = "cache"; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,kryo"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_100>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "arm,kryo"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_200>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_200: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x300>; 144 enable-method = "psci"; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 146 &LITTLE_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_300>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x400>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "arm,kryo"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 cpu-idle-states = <&BIG_CPU_SLEEP_0 180 &BIG_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,kryo"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 197 &BIG_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 cpu-idle-states = <&BIG_CPU_SLEEP_0 214 &BIG_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-power-down"; 267 arm,psci-suspend-param = <0x40000003>; 268 entry-latency-us = <549>; 269 exit-latency-us = <901>; 270 min-residency-us = <1774>; 271 local-timer-stop; 272 }; 273 274 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-down"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <702>; 279 exit-latency-us = <915>; 280 min-residency-us = <4001>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-power-down"; 287 arm,psci-suspend-param = <0x40000003>; 288 entry-latency-us = <523>; 289 exit-latency-us = <1244>; 290 min-residency-us = <2207>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "big-rail-power-down"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <526>; 299 exit-latency-us = <1854>; 300 min-residency-us = <5555>; 301 local-timer-stop; 302 }; 303 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "cluster-power-down"; 307 arm,psci-suspend-param = <0x40003444>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9926>; 311 local-timer-stop; 312 }; 313 }; 314 }; 315 316 memory@80000000 { 317 device_type = "memory"; 318 /* We expect the bootloader to fill in the size */ 319 reg = <0 0x80000000 0 0>; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-sc7280", "qcom,scm"; 325 }; 326 }; 327 328 clk_virt: interconnect { 329 compatible = "qcom,sc7280-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 smem { 335 compatible = "qcom,smem"; 336 memory-region = <&smem_mem>; 337 hwlocks = <&tcsr_mutex 3>; 338 }; 339 340 smp2p-adsp { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <443>, <429>; 343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P 345 IRQ_TYPE_EDGE_RISING>; 346 mboxes = <&ipcc IPCC_CLIENT_LPASS 347 IPCC_MPROC_SIGNAL_SMP2P>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <2>; 351 352 adsp_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 adsp_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 }; 363 364 smp2p-cdsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <94>, <432>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_CDSP 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <5>; 375 376 cdsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 cdsp_smp2p_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-mpss { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <435>, <428>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_MPSS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <1>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 ipa_smp2p_out: ipa-ap-to-modem { 412 qcom,entry-name = "ipa"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 ipa_smp2p_in: ipa-modem-to-ap { 417 qcom,entry-name = "ipa"; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smp2p-wpss { 424 compatible = "qcom,smp2p"; 425 qcom,smem = <617>, <616>; 426 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P 428 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&ipcc IPCC_CLIENT_WPSS 430 IPCC_MPROC_SIGNAL_SMP2P>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <13>; 434 435 wpss_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 wpss_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 }; 446 447 pmu { 448 compatible = "arm,armv8-pmuv3"; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 450 }; 451 452 psci { 453 compatible = "arm,psci-1.0"; 454 method = "smc"; 455 }; 456 457 soc: soc@0 { 458 #address-cells = <2>; 459 #size-cells = <2>; 460 ranges = <0 0 0 0 0x10 0>; 461 dma-ranges = <0 0 0 0 0x10 0>; 462 compatible = "simple-bus"; 463 464 gcc: clock-controller@100000 { 465 compatible = "qcom,gcc-sc7280"; 466 reg = <0 0x00100000 0 0x1f0000>; 467 clocks = <&rpmhcc RPMH_CXO_CLK>, 468 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 469 <0>, <0>, <0>, <0>, <0>, <0>; 470 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 471 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 472 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 473 "ufs_phy_tx_symbol_0_clk", 474 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 475 #clock-cells = <1>; 476 #reset-cells = <1>; 477 #power-domain-cells = <1>; 478 }; 479 480 ipcc: mailbox@408000 { 481 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 482 reg = <0 0x00408000 0 0x1000>; 483 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-controller; 485 #interrupt-cells = <3>; 486 #mbox-cells = <2>; 487 }; 488 489 qfprom: efuse@784000 { 490 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 491 reg = <0 0x00784000 0 0xa20>, 492 <0 0x00780000 0 0xa20>, 493 <0 0x00782000 0 0x120>, 494 <0 0x00786000 0 0x1fff>; 495 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 496 clock-names = "core"; 497 power-domains = <&rpmhpd SC7280_MX>; 498 #address-cells = <1>; 499 #size-cells = <1>; 500 }; 501 502 sdhc_1: sdhci@7c4000 { 503 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 504 status = "disabled"; 505 506 reg = <0 0x007c4000 0 0x1000>, 507 <0 0x007c5000 0 0x1000>; 508 reg-names = "hc", "cqhci"; 509 510 iommus = <&apps_smmu 0xc0 0x0>; 511 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "hc_irq", "pwr_irq"; 514 515 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 516 <&gcc GCC_SDCC1_AHB_CLK>, 517 <&rpmhcc RPMH_CXO_CLK>; 518 clock-names = "core", "iface", "xo"; 519 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 521 interconnect-names = "sdhc-ddr","cpu-sdhc"; 522 power-domains = <&rpmhpd SC7280_CX>; 523 operating-points-v2 = <&sdhc1_opp_table>; 524 525 bus-width = <8>; 526 supports-cqe; 527 528 qcom,dll-config = <0x0007642c>; 529 qcom,ddr-config = <0x80040868>; 530 531 mmc-ddr-1_8v; 532 mmc-hs200-1_8v; 533 mmc-hs400-1_8v; 534 mmc-hs400-enhanced-strobe; 535 536 sdhc1_opp_table: opp-table { 537 compatible = "operating-points-v2"; 538 539 opp-100000000 { 540 opp-hz = /bits/ 64 <100000000>; 541 required-opps = <&rpmhpd_opp_low_svs>; 542 opp-peak-kBps = <1800000 400000>; 543 opp-avg-kBps = <100000 0>; 544 }; 545 546 opp-384000000 { 547 opp-hz = /bits/ 64 <384000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 opp-peak-kBps = <5400000 1600000>; 550 opp-avg-kBps = <390000 0>; 551 }; 552 }; 553 554 }; 555 556 qupv3_id_0: geniqup@9c0000 { 557 compatible = "qcom,geni-se-qup"; 558 reg = <0 0x009c0000 0 0x2000>; 559 clock-names = "m-ahb", "s-ahb"; 560 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 561 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 562 #address-cells = <2>; 563 #size-cells = <2>; 564 ranges; 565 status = "disabled"; 566 567 uart5: serial@994000 { 568 compatible = "qcom,geni-debug-uart"; 569 reg = <0 0x00994000 0 0x4000>; 570 clock-names = "se"; 571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&qup_uart5_default>; 574 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 575 status = "disabled"; 576 }; 577 }; 578 579 cnoc2: interconnect@1500000 { 580 reg = <0 0x01500000 0 0x1000>; 581 compatible = "qcom,sc7280-cnoc2"; 582 #interconnect-cells = <2>; 583 qcom,bcm-voters = <&apps_bcm_voter>; 584 }; 585 586 cnoc3: interconnect@1502000 { 587 reg = <0 0x01502000 0 0x1000>; 588 compatible = "qcom,sc7280-cnoc3"; 589 #interconnect-cells = <2>; 590 qcom,bcm-voters = <&apps_bcm_voter>; 591 }; 592 593 mc_virt: interconnect@1580000 { 594 reg = <0 0x01580000 0 0x4>; 595 compatible = "qcom,sc7280-mc-virt"; 596 #interconnect-cells = <2>; 597 qcom,bcm-voters = <&apps_bcm_voter>; 598 }; 599 600 system_noc: interconnect@1680000 { 601 reg = <0 0x01680000 0 0x15480>; 602 compatible = "qcom,sc7280-system-noc"; 603 #interconnect-cells = <2>; 604 qcom,bcm-voters = <&apps_bcm_voter>; 605 }; 606 607 aggre1_noc: interconnect@16e0000 { 608 compatible = "qcom,sc7280-aggre1-noc"; 609 reg = <0 0x016e0000 0 0x1c080>; 610 #interconnect-cells = <2>; 611 qcom,bcm-voters = <&apps_bcm_voter>; 612 }; 613 614 aggre2_noc: interconnect@1700000 { 615 reg = <0 0x01700000 0 0x2b080>; 616 compatible = "qcom,sc7280-aggre2-noc"; 617 #interconnect-cells = <2>; 618 qcom,bcm-voters = <&apps_bcm_voter>; 619 }; 620 621 mmss_noc: interconnect@1740000 { 622 reg = <0 0x01740000 0 0x1e080>; 623 compatible = "qcom,sc7280-mmss-noc"; 624 #interconnect-cells = <2>; 625 qcom,bcm-voters = <&apps_bcm_voter>; 626 }; 627 628 ipa: ipa@1e40000 { 629 compatible = "qcom,sc7280-ipa"; 630 631 iommus = <&apps_smmu 0x480 0x0>, 632 <&apps_smmu 0x482 0x0>; 633 reg = <0 0x1e40000 0 0x8000>, 634 <0 0x1e50000 0 0x4ad0>, 635 <0 0x1e04000 0 0x23000>; 636 reg-names = "ipa-reg", 637 "ipa-shared", 638 "gsi"; 639 640 interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, 641 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 642 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 643 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 644 interrupt-names = "ipa", 645 "gsi", 646 "ipa-clock-query", 647 "ipa-setup-ready"; 648 649 clocks = <&rpmhcc RPMH_IPA_CLK>; 650 clock-names = "core"; 651 652 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 653 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 654 interconnect-names = "memory", 655 "config"; 656 657 qcom,smem-states = <&ipa_smp2p_out 0>, 658 <&ipa_smp2p_out 1>; 659 qcom,smem-state-names = "ipa-clock-enabled-valid", 660 "ipa-clock-enabled"; 661 662 status = "disabled"; 663 }; 664 665 tcsr_mutex: hwlock@1f40000 { 666 compatible = "qcom,tcsr-mutex", "syscon"; 667 reg = <0 0x01f40000 0 0x40000>; 668 #hwlock-cells = <1>; 669 }; 670 671 lpasscc: lpasscc@3000000 { 672 compatible = "qcom,sc7280-lpasscc"; 673 reg = <0 0x03000000 0 0x40>, 674 <0 0x03c04000 0 0x4>, 675 <0 0x03389000 0 0x24>; 676 reg-names = "qdsp6ss", "top_cc", "cc"; 677 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 678 clock-names = "iface"; 679 #clock-cells = <1>; 680 }; 681 682 lpass_ag_noc: interconnect@3c40000 { 683 reg = <0 0x03c40000 0 0xf080>; 684 compatible = "qcom,sc7280-lpass-ag-noc"; 685 #interconnect-cells = <2>; 686 qcom,bcm-voters = <&apps_bcm_voter>; 687 }; 688 689 gpu@3d00000 { 690 compatible = "qcom,adreno-635.0", "qcom,adreno"; 691 #stream-id-cells = <16>; 692 reg = <0 0x03d00000 0 0x40000>, 693 <0 0x03d9e000 0 0x1000>, 694 <0 0x03d61000 0 0x800>; 695 reg-names = "kgsl_3d0_reg_memory", 696 "cx_mem", 697 "cx_dbgc"; 698 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 699 iommus = <&adreno_smmu 0 0x401>; 700 operating-points-v2 = <&gpu_opp_table>; 701 qcom,gmu = <&gmu>; 702 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 703 interconnect-names = "gfx-mem"; 704 705 gpu_opp_table: opp-table { 706 compatible = "operating-points-v2"; 707 708 opp-315000000 { 709 opp-hz = /bits/ 64 <315000000>; 710 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 711 opp-peak-kBps = <1804000>; 712 }; 713 714 opp-450000000 { 715 opp-hz = /bits/ 64 <450000000>; 716 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 717 opp-peak-kBps = <4068000>; 718 }; 719 720 opp-550000000 { 721 opp-hz = /bits/ 64 <550000000>; 722 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 723 opp-peak-kBps = <6832000>; 724 }; 725 }; 726 }; 727 728 gmu: gmu@3d69000 { 729 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 730 reg = <0 0x03d6a000 0 0x34000>, 731 <0 0x3de0000 0 0x10000>, 732 <0 0x0b290000 0 0x10000>; 733 reg-names = "gmu", "rscc", "gmu_pdc"; 734 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 736 interrupt-names = "hfi", "gmu"; 737 clocks = <&gpucc 5>, 738 <&gpucc 8>, 739 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 740 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 741 <&gpucc 2>, 742 <&gpucc 15>, 743 <&gpucc 11>; 744 clock-names = "gmu", 745 "cxo", 746 "axi", 747 "memnoc", 748 "ahb", 749 "hub", 750 "smmu_vote"; 751 power-domains = <&gpucc 0>, 752 <&gpucc 1>; 753 power-domain-names = "cx", 754 "gx"; 755 iommus = <&adreno_smmu 5 0x400>; 756 operating-points-v2 = <&gmu_opp_table>; 757 758 gmu_opp_table: opp-table { 759 compatible = "operating-points-v2"; 760 761 opp-200000000 { 762 opp-hz = /bits/ 64 <200000000>; 763 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 764 }; 765 }; 766 }; 767 768 gpucc: clock-controller@3d90000 { 769 compatible = "qcom,sc7280-gpucc"; 770 reg = <0 0x03d90000 0 0x9000>; 771 clocks = <&rpmhcc RPMH_CXO_CLK>, 772 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 773 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 774 clock-names = "bi_tcxo", 775 "gcc_gpu_gpll0_clk_src", 776 "gcc_gpu_gpll0_div_clk_src"; 777 #clock-cells = <1>; 778 #reset-cells = <1>; 779 #power-domain-cells = <1>; 780 }; 781 782 adreno_smmu: iommu@3da0000 { 783 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 784 reg = <0 0x03da0000 0 0x20000>; 785 #iommu-cells = <2>; 786 #global-interrupts = <2>; 787 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 799 800 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 801 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 802 <&gpucc 2>, 803 <&gpucc 11>, 804 <&gpucc 5>, 805 <&gpucc 15>, 806 <&gpucc 13>; 807 clock-names = "gcc_gpu_memnoc_gfx_clk", 808 "gcc_gpu_snoc_dvm_gfx_clk", 809 "gpu_cc_ahb_clk", 810 "gpu_cc_hlos1_vote_gpu_smmu_clk", 811 "gpu_cc_cx_gmu_clk", 812 "gpu_cc_hub_cx_int_clk", 813 "gpu_cc_hub_aon_clk"; 814 815 power-domains = <&gpucc 0>; 816 }; 817 818 stm@6002000 { 819 compatible = "arm,coresight-stm", "arm,primecell"; 820 reg = <0 0x06002000 0 0x1000>, 821 <0 0x16280000 0 0x180000>; 822 reg-names = "stm-base", "stm-stimulus-base"; 823 824 clocks = <&aoss_qmp>; 825 clock-names = "apb_pclk"; 826 827 out-ports { 828 port { 829 stm_out: endpoint { 830 remote-endpoint = <&funnel0_in7>; 831 }; 832 }; 833 }; 834 }; 835 836 funnel@6041000 { 837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 838 reg = <0 0x06041000 0 0x1000>; 839 840 clocks = <&aoss_qmp>; 841 clock-names = "apb_pclk"; 842 843 out-ports { 844 port { 845 funnel0_out: endpoint { 846 remote-endpoint = <&merge_funnel_in0>; 847 }; 848 }; 849 }; 850 851 in-ports { 852 #address-cells = <1>; 853 #size-cells = <0>; 854 855 port@7 { 856 reg = <7>; 857 funnel0_in7: endpoint { 858 remote-endpoint = <&stm_out>; 859 }; 860 }; 861 }; 862 }; 863 864 funnel@6042000 { 865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 866 reg = <0 0x06042000 0 0x1000>; 867 868 clocks = <&aoss_qmp>; 869 clock-names = "apb_pclk"; 870 871 out-ports { 872 port { 873 funnel1_out: endpoint { 874 remote-endpoint = <&merge_funnel_in1>; 875 }; 876 }; 877 }; 878 879 in-ports { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 883 port@4 { 884 reg = <4>; 885 funnel1_in4: endpoint { 886 remote-endpoint = <&apss_merge_funnel_out>; 887 }; 888 }; 889 }; 890 }; 891 892 funnel@6045000 { 893 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 894 reg = <0 0x06045000 0 0x1000>; 895 896 clocks = <&aoss_qmp>; 897 clock-names = "apb_pclk"; 898 899 out-ports { 900 port { 901 merge_funnel_out: endpoint { 902 remote-endpoint = <&swao_funnel_in>; 903 }; 904 }; 905 }; 906 907 in-ports { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 port@0 { 912 reg = <0>; 913 merge_funnel_in0: endpoint { 914 remote-endpoint = <&funnel0_out>; 915 }; 916 }; 917 918 port@1 { 919 reg = <1>; 920 merge_funnel_in1: endpoint { 921 remote-endpoint = <&funnel1_out>; 922 }; 923 }; 924 }; 925 }; 926 927 replicator@6046000 { 928 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 929 reg = <0 0x06046000 0 0x1000>; 930 931 clocks = <&aoss_qmp>; 932 clock-names = "apb_pclk"; 933 934 out-ports { 935 port { 936 replicator_out: endpoint { 937 remote-endpoint = <&etr_in>; 938 }; 939 }; 940 }; 941 942 in-ports { 943 port { 944 replicator_in: endpoint { 945 remote-endpoint = <&swao_replicator_out>; 946 }; 947 }; 948 }; 949 }; 950 951 etr@6048000 { 952 compatible = "arm,coresight-tmc", "arm,primecell"; 953 reg = <0 0x06048000 0 0x1000>; 954 iommus = <&apps_smmu 0x04c0 0>; 955 956 clocks = <&aoss_qmp>; 957 clock-names = "apb_pclk"; 958 arm,scatter-gather; 959 960 in-ports { 961 port { 962 etr_in: endpoint { 963 remote-endpoint = <&replicator_out>; 964 }; 965 }; 966 }; 967 }; 968 969 funnel@6b04000 { 970 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 971 reg = <0 0x06b04000 0 0x1000>; 972 973 clocks = <&aoss_qmp>; 974 clock-names = "apb_pclk"; 975 976 out-ports { 977 port { 978 swao_funnel_out: endpoint { 979 remote-endpoint = <&etf_in>; 980 }; 981 }; 982 }; 983 984 in-ports { 985 #address-cells = <1>; 986 #size-cells = <0>; 987 988 port@7 { 989 reg = <7>; 990 swao_funnel_in: endpoint { 991 remote-endpoint = <&merge_funnel_out>; 992 }; 993 }; 994 }; 995 }; 996 997 etf@6b05000 { 998 compatible = "arm,coresight-tmc", "arm,primecell"; 999 reg = <0 0x06b05000 0 0x1000>; 1000 1001 clocks = <&aoss_qmp>; 1002 clock-names = "apb_pclk"; 1003 1004 out-ports { 1005 port { 1006 etf_out: endpoint { 1007 remote-endpoint = <&swao_replicator_in>; 1008 }; 1009 }; 1010 }; 1011 1012 in-ports { 1013 port { 1014 etf_in: endpoint { 1015 remote-endpoint = <&swao_funnel_out>; 1016 }; 1017 }; 1018 }; 1019 }; 1020 1021 replicator@6b06000 { 1022 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1023 reg = <0 0x06b06000 0 0x1000>; 1024 1025 clocks = <&aoss_qmp>; 1026 clock-names = "apb_pclk"; 1027 qcom,replicator-loses-context; 1028 1029 out-ports { 1030 port { 1031 swao_replicator_out: endpoint { 1032 remote-endpoint = <&replicator_in>; 1033 }; 1034 }; 1035 }; 1036 1037 in-ports { 1038 port { 1039 swao_replicator_in: endpoint { 1040 remote-endpoint = <&etf_out>; 1041 }; 1042 }; 1043 }; 1044 }; 1045 1046 etm@7040000 { 1047 compatible = "arm,coresight-etm4x", "arm,primecell"; 1048 reg = <0 0x07040000 0 0x1000>; 1049 1050 cpu = <&CPU0>; 1051 1052 clocks = <&aoss_qmp>; 1053 clock-names = "apb_pclk"; 1054 arm,coresight-loses-context-with-cpu; 1055 qcom,skip-power-up; 1056 1057 out-ports { 1058 port { 1059 etm0_out: endpoint { 1060 remote-endpoint = <&apss_funnel_in0>; 1061 }; 1062 }; 1063 }; 1064 }; 1065 1066 etm@7140000 { 1067 compatible = "arm,coresight-etm4x", "arm,primecell"; 1068 reg = <0 0x07140000 0 0x1000>; 1069 1070 cpu = <&CPU1>; 1071 1072 clocks = <&aoss_qmp>; 1073 clock-names = "apb_pclk"; 1074 arm,coresight-loses-context-with-cpu; 1075 qcom,skip-power-up; 1076 1077 out-ports { 1078 port { 1079 etm1_out: endpoint { 1080 remote-endpoint = <&apss_funnel_in1>; 1081 }; 1082 }; 1083 }; 1084 }; 1085 1086 etm@7240000 { 1087 compatible = "arm,coresight-etm4x", "arm,primecell"; 1088 reg = <0 0x07240000 0 0x1000>; 1089 1090 cpu = <&CPU2>; 1091 1092 clocks = <&aoss_qmp>; 1093 clock-names = "apb_pclk"; 1094 arm,coresight-loses-context-with-cpu; 1095 qcom,skip-power-up; 1096 1097 out-ports { 1098 port { 1099 etm2_out: endpoint { 1100 remote-endpoint = <&apss_funnel_in2>; 1101 }; 1102 }; 1103 }; 1104 }; 1105 1106 etm@7340000 { 1107 compatible = "arm,coresight-etm4x", "arm,primecell"; 1108 reg = <0 0x07340000 0 0x1000>; 1109 1110 cpu = <&CPU3>; 1111 1112 clocks = <&aoss_qmp>; 1113 clock-names = "apb_pclk"; 1114 arm,coresight-loses-context-with-cpu; 1115 qcom,skip-power-up; 1116 1117 out-ports { 1118 port { 1119 etm3_out: endpoint { 1120 remote-endpoint = <&apss_funnel_in3>; 1121 }; 1122 }; 1123 }; 1124 }; 1125 1126 etm@7440000 { 1127 compatible = "arm,coresight-etm4x", "arm,primecell"; 1128 reg = <0 0x07440000 0 0x1000>; 1129 1130 cpu = <&CPU4>; 1131 1132 clocks = <&aoss_qmp>; 1133 clock-names = "apb_pclk"; 1134 arm,coresight-loses-context-with-cpu; 1135 qcom,skip-power-up; 1136 1137 out-ports { 1138 port { 1139 etm4_out: endpoint { 1140 remote-endpoint = <&apss_funnel_in4>; 1141 }; 1142 }; 1143 }; 1144 }; 1145 1146 etm@7540000 { 1147 compatible = "arm,coresight-etm4x", "arm,primecell"; 1148 reg = <0 0x07540000 0 0x1000>; 1149 1150 cpu = <&CPU5>; 1151 1152 clocks = <&aoss_qmp>; 1153 clock-names = "apb_pclk"; 1154 arm,coresight-loses-context-with-cpu; 1155 qcom,skip-power-up; 1156 1157 out-ports { 1158 port { 1159 etm5_out: endpoint { 1160 remote-endpoint = <&apss_funnel_in5>; 1161 }; 1162 }; 1163 }; 1164 }; 1165 1166 etm@7640000 { 1167 compatible = "arm,coresight-etm4x", "arm,primecell"; 1168 reg = <0 0x07640000 0 0x1000>; 1169 1170 cpu = <&CPU6>; 1171 1172 clocks = <&aoss_qmp>; 1173 clock-names = "apb_pclk"; 1174 arm,coresight-loses-context-with-cpu; 1175 qcom,skip-power-up; 1176 1177 out-ports { 1178 port { 1179 etm6_out: endpoint { 1180 remote-endpoint = <&apss_funnel_in6>; 1181 }; 1182 }; 1183 }; 1184 }; 1185 1186 etm@7740000 { 1187 compatible = "arm,coresight-etm4x", "arm,primecell"; 1188 reg = <0 0x07740000 0 0x1000>; 1189 1190 cpu = <&CPU7>; 1191 1192 clocks = <&aoss_qmp>; 1193 clock-names = "apb_pclk"; 1194 arm,coresight-loses-context-with-cpu; 1195 qcom,skip-power-up; 1196 1197 out-ports { 1198 port { 1199 etm7_out: endpoint { 1200 remote-endpoint = <&apss_funnel_in7>; 1201 }; 1202 }; 1203 }; 1204 }; 1205 1206 funnel@7800000 { /* APSS Funnel */ 1207 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1208 reg = <0 0x07800000 0 0x1000>; 1209 1210 clocks = <&aoss_qmp>; 1211 clock-names = "apb_pclk"; 1212 1213 out-ports { 1214 port { 1215 apss_funnel_out: endpoint { 1216 remote-endpoint = <&apss_merge_funnel_in>; 1217 }; 1218 }; 1219 }; 1220 1221 in-ports { 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 1225 port@0 { 1226 reg = <0>; 1227 apss_funnel_in0: endpoint { 1228 remote-endpoint = <&etm0_out>; 1229 }; 1230 }; 1231 1232 port@1 { 1233 reg = <1>; 1234 apss_funnel_in1: endpoint { 1235 remote-endpoint = <&etm1_out>; 1236 }; 1237 }; 1238 1239 port@2 { 1240 reg = <2>; 1241 apss_funnel_in2: endpoint { 1242 remote-endpoint = <&etm2_out>; 1243 }; 1244 }; 1245 1246 port@3 { 1247 reg = <3>; 1248 apss_funnel_in3: endpoint { 1249 remote-endpoint = <&etm3_out>; 1250 }; 1251 }; 1252 1253 port@4 { 1254 reg = <4>; 1255 apss_funnel_in4: endpoint { 1256 remote-endpoint = <&etm4_out>; 1257 }; 1258 }; 1259 1260 port@5 { 1261 reg = <5>; 1262 apss_funnel_in5: endpoint { 1263 remote-endpoint = <&etm5_out>; 1264 }; 1265 }; 1266 1267 port@6 { 1268 reg = <6>; 1269 apss_funnel_in6: endpoint { 1270 remote-endpoint = <&etm6_out>; 1271 }; 1272 }; 1273 1274 port@7 { 1275 reg = <7>; 1276 apss_funnel_in7: endpoint { 1277 remote-endpoint = <&etm7_out>; 1278 }; 1279 }; 1280 }; 1281 }; 1282 1283 funnel@7810000 { 1284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1285 reg = <0 0x07810000 0 0x1000>; 1286 1287 clocks = <&aoss_qmp>; 1288 clock-names = "apb_pclk"; 1289 1290 out-ports { 1291 port { 1292 apss_merge_funnel_out: endpoint { 1293 remote-endpoint = <&funnel1_in4>; 1294 }; 1295 }; 1296 }; 1297 1298 in-ports { 1299 port { 1300 apss_merge_funnel_in: endpoint { 1301 remote-endpoint = <&apss_funnel_out>; 1302 }; 1303 }; 1304 }; 1305 }; 1306 1307 sdhc_2: sdhci@8804000 { 1308 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1309 status = "disabled"; 1310 1311 reg = <0 0x08804000 0 0x1000>; 1312 1313 iommus = <&apps_smmu 0x100 0x0>; 1314 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1316 interrupt-names = "hc_irq", "pwr_irq"; 1317 1318 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1319 <&gcc GCC_SDCC2_AHB_CLK>, 1320 <&rpmhcc RPMH_CXO_CLK>; 1321 clock-names = "core", "iface", "xo"; 1322 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1323 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1324 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1325 power-domains = <&rpmhpd SC7280_CX>; 1326 operating-points-v2 = <&sdhc2_opp_table>; 1327 1328 bus-width = <4>; 1329 1330 qcom,dll-config = <0x0007642c>; 1331 1332 sdhc2_opp_table: opp-table { 1333 compatible = "operating-points-v2"; 1334 1335 opp-100000000 { 1336 opp-hz = /bits/ 64 <100000000>; 1337 required-opps = <&rpmhpd_opp_low_svs>; 1338 opp-peak-kBps = <1800000 400000>; 1339 opp-avg-kBps = <100000 0>; 1340 }; 1341 1342 opp-202000000 { 1343 opp-hz = /bits/ 64 <202000000>; 1344 required-opps = <&rpmhpd_opp_nom>; 1345 opp-peak-kBps = <5400000 1600000>; 1346 opp-avg-kBps = <200000 0>; 1347 }; 1348 }; 1349 1350 }; 1351 1352 usb_1_hsphy: phy@88e3000 { 1353 compatible = "qcom,sc7280-usb-hs-phy", 1354 "qcom,usb-snps-hs-7nm-phy"; 1355 reg = <0 0x088e3000 0 0x400>; 1356 status = "disabled"; 1357 #phy-cells = <0>; 1358 1359 clocks = <&rpmhcc RPMH_CXO_CLK>; 1360 clock-names = "ref"; 1361 1362 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1363 }; 1364 1365 usb_2_hsphy: phy@88e4000 { 1366 compatible = "qcom,sc7280-usb-hs-phy", 1367 "qcom,usb-snps-hs-7nm-phy"; 1368 reg = <0 0x088e4000 0 0x400>; 1369 status = "disabled"; 1370 #phy-cells = <0>; 1371 1372 clocks = <&rpmhcc RPMH_CXO_CLK>; 1373 clock-names = "ref"; 1374 1375 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1376 }; 1377 1378 usb_1_qmpphy: phy-wrapper@88e9000 { 1379 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1380 "qcom,sm8250-qmp-usb3-dp-phy"; 1381 reg = <0 0x088e9000 0 0x200>, 1382 <0 0x088e8000 0 0x40>, 1383 <0 0x088ea000 0 0x200>; 1384 status = "disabled"; 1385 #address-cells = <2>; 1386 #size-cells = <2>; 1387 ranges; 1388 1389 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1390 <&rpmhcc RPMH_CXO_CLK>, 1391 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1392 clock-names = "aux", "ref_clk_src", "com_aux"; 1393 1394 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1395 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1396 reset-names = "phy", "common"; 1397 1398 usb_1_ssphy: usb3-phy@88e9200 { 1399 reg = <0 0x088e9200 0 0x200>, 1400 <0 0x088e9400 0 0x200>, 1401 <0 0x088e9c00 0 0x400>, 1402 <0 0x088e9600 0 0x200>, 1403 <0 0x088e9800 0 0x200>, 1404 <0 0x088e9a00 0 0x100>; 1405 #clock-cells = <0>; 1406 #phy-cells = <0>; 1407 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1408 clock-names = "pipe0"; 1409 clock-output-names = "usb3_phy_pipe_clk_src"; 1410 }; 1411 1412 dp_phy: dp-phy@88ea200 { 1413 reg = <0 0x088ea200 0 0x200>, 1414 <0 0x088ea400 0 0x200>, 1415 <0 0x088eaa00 0 0x200>, 1416 <0 0x088ea600 0 0x200>, 1417 <0 0x088ea800 0 0x200>; 1418 #phy-cells = <0>; 1419 #clock-cells = <1>; 1420 }; 1421 }; 1422 1423 usb_2: usb@8cf8800 { 1424 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1425 reg = <0 0x08cf8800 0 0x400>; 1426 status = "disabled"; 1427 #address-cells = <2>; 1428 #size-cells = <2>; 1429 ranges; 1430 dma-ranges; 1431 1432 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1433 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1434 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1435 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1436 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1437 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1438 "sleep"; 1439 1440 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1441 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1442 assigned-clock-rates = <19200000>, <200000000>; 1443 1444 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1445 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1446 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1447 interrupt-names = "hs_phy_irq", 1448 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1449 1450 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1451 1452 resets = <&gcc GCC_USB30_SEC_BCR>; 1453 1454 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1456 interconnect-names = "usb-ddr", "apps-usb"; 1457 1458 usb_2_dwc3: usb@8c00000 { 1459 compatible = "snps,dwc3"; 1460 reg = <0 0x08c00000 0 0xe000>; 1461 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1462 iommus = <&apps_smmu 0xa0 0x0>; 1463 snps,dis_u2_susphy_quirk; 1464 snps,dis_enblslpm_quirk; 1465 phys = <&usb_2_hsphy>; 1466 phy-names = "usb2-phy"; 1467 maximum-speed = "high-speed"; 1468 }; 1469 }; 1470 1471 dc_noc: interconnect@90e0000 { 1472 reg = <0 0x090e0000 0 0x5080>; 1473 compatible = "qcom,sc7280-dc-noc"; 1474 #interconnect-cells = <2>; 1475 qcom,bcm-voters = <&apps_bcm_voter>; 1476 }; 1477 1478 gem_noc: interconnect@9100000 { 1479 reg = <0 0x9100000 0 0xe2200>; 1480 compatible = "qcom,sc7280-gem-noc"; 1481 #interconnect-cells = <2>; 1482 qcom,bcm-voters = <&apps_bcm_voter>; 1483 }; 1484 1485 system-cache-controller@9200000 { 1486 compatible = "qcom,sc7280-llcc"; 1487 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1488 reg-names = "llcc_base", "llcc_broadcast_base"; 1489 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1490 }; 1491 1492 nsp_noc: interconnect@a0c0000 { 1493 reg = <0 0x0a0c0000 0 0x10000>; 1494 compatible = "qcom,sc7280-nsp-noc"; 1495 #interconnect-cells = <2>; 1496 qcom,bcm-voters = <&apps_bcm_voter>; 1497 }; 1498 1499 usb_1: usb@a6f8800 { 1500 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1501 reg = <0 0x0a6f8800 0 0x400>; 1502 status = "disabled"; 1503 #address-cells = <2>; 1504 #size-cells = <2>; 1505 ranges; 1506 dma-ranges; 1507 1508 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1509 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1510 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1511 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1512 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1513 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1514 "sleep"; 1515 1516 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1517 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1518 assigned-clock-rates = <19200000>, <200000000>; 1519 1520 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1521 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1522 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1523 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1524 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1525 "dm_hs_phy_irq", "ss_phy_irq"; 1526 1527 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1528 1529 resets = <&gcc GCC_USB30_PRIM_BCR>; 1530 1531 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1532 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1533 interconnect-names = "usb-ddr", "apps-usb"; 1534 1535 usb_1_dwc3: usb@a600000 { 1536 compatible = "snps,dwc3"; 1537 reg = <0 0x0a600000 0 0xe000>; 1538 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1539 iommus = <&apps_smmu 0xe0 0x0>; 1540 snps,dis_u2_susphy_quirk; 1541 snps,dis_enblslpm_quirk; 1542 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1543 phy-names = "usb2-phy", "usb3-phy"; 1544 maximum-speed = "super-speed"; 1545 }; 1546 }; 1547 1548 videocc: clock-controller@aaf0000 { 1549 compatible = "qcom,sc7280-videocc"; 1550 reg = <0 0xaaf0000 0 0x10000>; 1551 clocks = <&rpmhcc RPMH_CXO_CLK>, 1552 <&rpmhcc RPMH_CXO_CLK_A>; 1553 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1554 #clock-cells = <1>; 1555 #reset-cells = <1>; 1556 #power-domain-cells = <1>; 1557 }; 1558 1559 dispcc: clock-controller@af00000 { 1560 compatible = "qcom,sc7280-dispcc"; 1561 reg = <0 0xaf00000 0 0x20000>; 1562 clocks = <&rpmhcc RPMH_CXO_CLK>, 1563 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1564 <0>, <0>, <0>, <0>, <0>, <0>; 1565 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1566 "dsi0_phy_pll_out_byteclk", 1567 "dsi0_phy_pll_out_dsiclk", 1568 "dp_phy_pll_link_clk", 1569 "dp_phy_pll_vco_div_clk", 1570 "edp_phy_pll_link_clk", 1571 "edp_phy_pll_vco_div_clk"; 1572 #clock-cells = <1>; 1573 #reset-cells = <1>; 1574 #power-domain-cells = <1>; 1575 }; 1576 1577 pdc: interrupt-controller@b220000 { 1578 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1579 reg = <0 0x0b220000 0 0x30000>; 1580 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1581 <55 306 4>, <59 312 3>, <62 374 2>, 1582 <64 434 2>, <66 438 3>, <69 86 1>, 1583 <70 520 54>, <124 609 31>, <155 63 1>, 1584 <156 716 12>; 1585 #interrupt-cells = <2>; 1586 interrupt-parent = <&intc>; 1587 interrupt-controller; 1588 }; 1589 1590 pdc_reset: reset-controller@b5e0000 { 1591 compatible = "qcom,sc7280-pdc-global"; 1592 reg = <0 0x0b5e0000 0 0x20000>; 1593 #reset-cells = <1>; 1594 }; 1595 1596 tsens0: thermal-sensor@c263000 { 1597 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1598 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1599 <0 0x0c222000 0 0x1ff>; /* SROT */ 1600 #qcom,sensors = <15>; 1601 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1603 interrupt-names = "uplow","critical"; 1604 #thermal-sensor-cells = <1>; 1605 }; 1606 1607 tsens1: thermal-sensor@c265000 { 1608 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1609 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1610 <0 0x0c223000 0 0x1ff>; /* SROT */ 1611 #qcom,sensors = <12>; 1612 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1614 interrupt-names = "uplow","critical"; 1615 #thermal-sensor-cells = <1>; 1616 }; 1617 1618 aoss_reset: reset-controller@c2a0000 { 1619 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1620 reg = <0 0x0c2a0000 0 0x31000>; 1621 #reset-cells = <1>; 1622 }; 1623 1624 aoss_qmp: power-controller@c300000 { 1625 compatible = "qcom,sc7280-aoss-qmp"; 1626 reg = <0 0x0c300000 0 0x100000>; 1627 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1628 IPCC_MPROC_SIGNAL_GLINK_QMP 1629 IRQ_TYPE_EDGE_RISING>; 1630 mboxes = <&ipcc IPCC_CLIENT_AOP 1631 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1632 1633 #clock-cells = <0>; 1634 #power-domain-cells = <1>; 1635 }; 1636 1637 spmi_bus: spmi@c440000 { 1638 compatible = "qcom,spmi-pmic-arb"; 1639 reg = <0 0x0c440000 0 0x1100>, 1640 <0 0x0c600000 0 0x2000000>, 1641 <0 0x0e600000 0 0x100000>, 1642 <0 0x0e700000 0 0xa0000>, 1643 <0 0x0c40a000 0 0x26000>; 1644 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1645 interrupt-names = "periph_irq"; 1646 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1647 qcom,ee = <0>; 1648 qcom,channel = <0>; 1649 #address-cells = <1>; 1650 #size-cells = <1>; 1651 interrupt-controller; 1652 #interrupt-cells = <4>; 1653 }; 1654 1655 tlmm: pinctrl@f100000 { 1656 compatible = "qcom,sc7280-pinctrl"; 1657 reg = <0 0x0f100000 0 0x300000>; 1658 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1659 gpio-controller; 1660 #gpio-cells = <2>; 1661 interrupt-controller; 1662 #interrupt-cells = <2>; 1663 gpio-ranges = <&tlmm 0 0 175>; 1664 wakeup-parent = <&pdc>; 1665 1666 qup_uart5_default: qup-uart5-default { 1667 pins = "gpio46", "gpio47"; 1668 function = "qup13"; 1669 }; 1670 1671 sdc1_on: sdc1-on { 1672 clk { 1673 pins = "sdc1_clk"; 1674 }; 1675 1676 cmd { 1677 pins = "sdc1_cmd"; 1678 }; 1679 1680 data { 1681 pins = "sdc1_data"; 1682 }; 1683 1684 rclk { 1685 pins = "sdc1_rclk"; 1686 }; 1687 }; 1688 1689 sdc1_off: sdc1-off { 1690 clk { 1691 pins = "sdc1_clk"; 1692 drive-strength = <2>; 1693 bias-bus-hold; 1694 }; 1695 1696 cmd { 1697 pins = "sdc1_cmd"; 1698 drive-strength = <2>; 1699 bias-bus-hold; 1700 }; 1701 1702 data { 1703 pins = "sdc1_data"; 1704 drive-strength = <2>; 1705 bias-bus-hold; 1706 }; 1707 1708 rclk { 1709 pins = "sdc1_rclk"; 1710 bias-bus-hold; 1711 }; 1712 }; 1713 1714 sdc2_on: sdc2-on { 1715 clk { 1716 pins = "sdc2_clk"; 1717 }; 1718 1719 cmd { 1720 pins = "sdc2_cmd"; 1721 }; 1722 1723 data { 1724 pins = "sdc2_data"; 1725 }; 1726 }; 1727 1728 sdc2_off: sdc2-off { 1729 clk { 1730 pins = "sdc2_clk"; 1731 drive-strength = <2>; 1732 bias-bus-hold; 1733 }; 1734 1735 cmd { 1736 pins ="sdc2_cmd"; 1737 drive-strength = <2>; 1738 bias-bus-hold; 1739 }; 1740 1741 data { 1742 pins ="sdc2_data"; 1743 drive-strength = <2>; 1744 bias-bus-hold; 1745 }; 1746 }; 1747 }; 1748 1749 apps_smmu: iommu@15000000 { 1750 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1751 reg = <0 0x15000000 0 0x100000>; 1752 #iommu-cells = <2>; 1753 #global-interrupts = <1>; 1754 dma-coherent; 1755 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1836 }; 1837 1838 intc: interrupt-controller@17a00000 { 1839 compatible = "arm,gic-v3"; 1840 #address-cells = <2>; 1841 #size-cells = <2>; 1842 ranges; 1843 #interrupt-cells = <3>; 1844 interrupt-controller; 1845 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1846 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1847 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1848 1849 gic-its@17a40000 { 1850 compatible = "arm,gic-v3-its"; 1851 msi-controller; 1852 #msi-cells = <1>; 1853 reg = <0 0x17a40000 0 0x20000>; 1854 status = "disabled"; 1855 }; 1856 }; 1857 1858 watchdog@17c10000 { 1859 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1860 reg = <0 0x17c10000 0 0x1000>; 1861 clocks = <&sleep_clk>; 1862 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1863 }; 1864 1865 timer@17c20000 { 1866 #address-cells = <2>; 1867 #size-cells = <2>; 1868 ranges; 1869 compatible = "arm,armv7-timer-mem"; 1870 reg = <0 0x17c20000 0 0x1000>; 1871 1872 frame@17c21000 { 1873 frame-number = <0>; 1874 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1876 reg = <0 0x17c21000 0 0x1000>, 1877 <0 0x17c22000 0 0x1000>; 1878 }; 1879 1880 frame@17c23000 { 1881 frame-number = <1>; 1882 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1883 reg = <0 0x17c23000 0 0x1000>; 1884 status = "disabled"; 1885 }; 1886 1887 frame@17c25000 { 1888 frame-number = <2>; 1889 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1890 reg = <0 0x17c25000 0 0x1000>; 1891 status = "disabled"; 1892 }; 1893 1894 frame@17c27000 { 1895 frame-number = <3>; 1896 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1897 reg = <0 0x17c27000 0 0x1000>; 1898 status = "disabled"; 1899 }; 1900 1901 frame@17c29000 { 1902 frame-number = <4>; 1903 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1904 reg = <0 0x17c29000 0 0x1000>; 1905 status = "disabled"; 1906 }; 1907 1908 frame@17c2b000 { 1909 frame-number = <5>; 1910 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1911 reg = <0 0x17c2b000 0 0x1000>; 1912 status = "disabled"; 1913 }; 1914 1915 frame@17c2d000 { 1916 frame-number = <6>; 1917 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1918 reg = <0 0x17c2d000 0 0x1000>; 1919 status = "disabled"; 1920 }; 1921 }; 1922 1923 apps_rsc: rsc@18200000 { 1924 compatible = "qcom,rpmh-rsc"; 1925 reg = <0 0x18200000 0 0x10000>, 1926 <0 0x18210000 0 0x10000>, 1927 <0 0x18220000 0 0x10000>; 1928 reg-names = "drv-0", "drv-1", "drv-2"; 1929 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1932 qcom,tcs-offset = <0xd00>; 1933 qcom,drv-id = <2>; 1934 qcom,tcs-config = <ACTIVE_TCS 2>, 1935 <SLEEP_TCS 3>, 1936 <WAKE_TCS 3>, 1937 <CONTROL_TCS 1>; 1938 1939 apps_bcm_voter: bcm-voter { 1940 compatible = "qcom,bcm-voter"; 1941 }; 1942 1943 rpmhpd: power-controller { 1944 compatible = "qcom,sc7280-rpmhpd"; 1945 #power-domain-cells = <1>; 1946 operating-points-v2 = <&rpmhpd_opp_table>; 1947 1948 rpmhpd_opp_table: opp-table { 1949 compatible = "operating-points-v2"; 1950 1951 rpmhpd_opp_ret: opp1 { 1952 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1953 }; 1954 1955 rpmhpd_opp_low_svs: opp2 { 1956 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1957 }; 1958 1959 rpmhpd_opp_svs: opp3 { 1960 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1961 }; 1962 1963 rpmhpd_opp_svs_l1: opp4 { 1964 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1965 }; 1966 1967 rpmhpd_opp_svs_l2: opp5 { 1968 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1969 }; 1970 1971 rpmhpd_opp_nom: opp6 { 1972 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1973 }; 1974 1975 rpmhpd_opp_nom_l1: opp7 { 1976 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1977 }; 1978 1979 rpmhpd_opp_turbo: opp8 { 1980 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1981 }; 1982 1983 rpmhpd_opp_turbo_l1: opp9 { 1984 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1985 }; 1986 }; 1987 }; 1988 1989 rpmhcc: clock-controller { 1990 compatible = "qcom,sc7280-rpmh-clk"; 1991 clocks = <&xo_board>; 1992 clock-names = "xo"; 1993 #clock-cells = <1>; 1994 }; 1995 }; 1996 1997 cpufreq_hw: cpufreq@18591000 { 1998 compatible = "qcom,cpufreq-epss"; 1999 reg = <0 0x18591100 0 0x900>, 2000 <0 0x18592100 0 0x900>, 2001 <0 0x18593100 0 0x900>; 2002 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2003 clock-names = "xo", "alternate"; 2004 #freq-domain-cells = <1>; 2005 }; 2006 }; 2007 2008 thermal_zones: thermal-zones { 2009 cpu0-thermal { 2010 polling-delay-passive = <250>; 2011 polling-delay = <0>; 2012 2013 thermal-sensors = <&tsens0 1>; 2014 2015 trips { 2016 cpu0_alert0: trip-point0 { 2017 temperature = <90000>; 2018 hysteresis = <2000>; 2019 type = "passive"; 2020 }; 2021 2022 cpu0_alert1: trip-point1 { 2023 temperature = <95000>; 2024 hysteresis = <2000>; 2025 type = "passive"; 2026 }; 2027 2028 cpu0_crit: cpu-crit { 2029 temperature = <110000>; 2030 hysteresis = <0>; 2031 type = "critical"; 2032 }; 2033 }; 2034 2035 cooling-maps { 2036 map0 { 2037 trip = <&cpu0_alert0>; 2038 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2039 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2040 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2041 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2042 }; 2043 map1 { 2044 trip = <&cpu0_alert1>; 2045 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2046 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2047 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2048 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2049 }; 2050 }; 2051 }; 2052 2053 cpu1-thermal { 2054 polling-delay-passive = <250>; 2055 polling-delay = <0>; 2056 2057 thermal-sensors = <&tsens0 2>; 2058 2059 trips { 2060 cpu1_alert0: trip-point0 { 2061 temperature = <90000>; 2062 hysteresis = <2000>; 2063 type = "passive"; 2064 }; 2065 2066 cpu1_alert1: trip-point1 { 2067 temperature = <95000>; 2068 hysteresis = <2000>; 2069 type = "passive"; 2070 }; 2071 2072 cpu1_crit: cpu-crit { 2073 temperature = <110000>; 2074 hysteresis = <0>; 2075 type = "critical"; 2076 }; 2077 }; 2078 2079 cooling-maps { 2080 map0 { 2081 trip = <&cpu1_alert0>; 2082 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2083 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2084 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2085 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2086 }; 2087 map1 { 2088 trip = <&cpu1_alert1>; 2089 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2090 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2091 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2092 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2093 }; 2094 }; 2095 }; 2096 2097 cpu2-thermal { 2098 polling-delay-passive = <250>; 2099 polling-delay = <0>; 2100 2101 thermal-sensors = <&tsens0 3>; 2102 2103 trips { 2104 cpu2_alert0: trip-point0 { 2105 temperature = <90000>; 2106 hysteresis = <2000>; 2107 type = "passive"; 2108 }; 2109 2110 cpu2_alert1: trip-point1 { 2111 temperature = <95000>; 2112 hysteresis = <2000>; 2113 type = "passive"; 2114 }; 2115 2116 cpu2_crit: cpu-crit { 2117 temperature = <110000>; 2118 hysteresis = <0>; 2119 type = "critical"; 2120 }; 2121 }; 2122 2123 cooling-maps { 2124 map0 { 2125 trip = <&cpu2_alert0>; 2126 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2127 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2128 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2129 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2130 }; 2131 map1 { 2132 trip = <&cpu2_alert1>; 2133 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2134 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2135 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2136 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2137 }; 2138 }; 2139 }; 2140 2141 cpu3-thermal { 2142 polling-delay-passive = <250>; 2143 polling-delay = <0>; 2144 2145 thermal-sensors = <&tsens0 4>; 2146 2147 trips { 2148 cpu3_alert0: trip-point0 { 2149 temperature = <90000>; 2150 hysteresis = <2000>; 2151 type = "passive"; 2152 }; 2153 2154 cpu3_alert1: trip-point1 { 2155 temperature = <95000>; 2156 hysteresis = <2000>; 2157 type = "passive"; 2158 }; 2159 2160 cpu3_crit: cpu-crit { 2161 temperature = <110000>; 2162 hysteresis = <0>; 2163 type = "critical"; 2164 }; 2165 }; 2166 2167 cooling-maps { 2168 map0 { 2169 trip = <&cpu3_alert0>; 2170 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2171 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2172 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2173 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2174 }; 2175 map1 { 2176 trip = <&cpu3_alert1>; 2177 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2178 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2179 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2180 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2181 }; 2182 }; 2183 }; 2184 2185 cpu4-thermal { 2186 polling-delay-passive = <250>; 2187 polling-delay = <0>; 2188 2189 thermal-sensors = <&tsens0 7>; 2190 2191 trips { 2192 cpu4_alert0: trip-point0 { 2193 temperature = <90000>; 2194 hysteresis = <2000>; 2195 type = "passive"; 2196 }; 2197 2198 cpu4_alert1: trip-point1 { 2199 temperature = <95000>; 2200 hysteresis = <2000>; 2201 type = "passive"; 2202 }; 2203 2204 cpu4_crit: cpu-crit { 2205 temperature = <110000>; 2206 hysteresis = <0>; 2207 type = "critical"; 2208 }; 2209 }; 2210 2211 cooling-maps { 2212 map0 { 2213 trip = <&cpu4_alert0>; 2214 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2215 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2216 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2217 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2218 }; 2219 map1 { 2220 trip = <&cpu4_alert1>; 2221 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2222 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2223 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2224 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2225 }; 2226 }; 2227 }; 2228 2229 cpu5-thermal { 2230 polling-delay-passive = <250>; 2231 polling-delay = <0>; 2232 2233 thermal-sensors = <&tsens0 8>; 2234 2235 trips { 2236 cpu5_alert0: trip-point0 { 2237 temperature = <90000>; 2238 hysteresis = <2000>; 2239 type = "passive"; 2240 }; 2241 2242 cpu5_alert1: trip-point1 { 2243 temperature = <95000>; 2244 hysteresis = <2000>; 2245 type = "passive"; 2246 }; 2247 2248 cpu5_crit: cpu-crit { 2249 temperature = <110000>; 2250 hysteresis = <0>; 2251 type = "critical"; 2252 }; 2253 }; 2254 2255 cooling-maps { 2256 map0 { 2257 trip = <&cpu5_alert0>; 2258 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2259 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2260 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2261 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2262 }; 2263 map1 { 2264 trip = <&cpu5_alert1>; 2265 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2266 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2267 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2268 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2269 }; 2270 }; 2271 }; 2272 2273 cpu6-thermal { 2274 polling-delay-passive = <250>; 2275 polling-delay = <0>; 2276 2277 thermal-sensors = <&tsens0 9>; 2278 2279 trips { 2280 cpu6_alert0: trip-point0 { 2281 temperature = <90000>; 2282 hysteresis = <2000>; 2283 type = "passive"; 2284 }; 2285 2286 cpu6_alert1: trip-point1 { 2287 temperature = <95000>; 2288 hysteresis = <2000>; 2289 type = "passive"; 2290 }; 2291 2292 cpu6_crit: cpu-crit { 2293 temperature = <110000>; 2294 hysteresis = <0>; 2295 type = "critical"; 2296 }; 2297 }; 2298 2299 cooling-maps { 2300 map0 { 2301 trip = <&cpu6_alert0>; 2302 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2303 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2304 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2305 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2306 }; 2307 map1 { 2308 trip = <&cpu6_alert1>; 2309 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2310 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2311 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2312 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2313 }; 2314 }; 2315 }; 2316 2317 cpu7-thermal { 2318 polling-delay-passive = <250>; 2319 polling-delay = <0>; 2320 2321 thermal-sensors = <&tsens0 10>; 2322 2323 trips { 2324 cpu7_alert0: trip-point0 { 2325 temperature = <90000>; 2326 hysteresis = <2000>; 2327 type = "passive"; 2328 }; 2329 2330 cpu7_alert1: trip-point1 { 2331 temperature = <95000>; 2332 hysteresis = <2000>; 2333 type = "passive"; 2334 }; 2335 2336 cpu7_crit: cpu-crit { 2337 temperature = <110000>; 2338 hysteresis = <0>; 2339 type = "critical"; 2340 }; 2341 }; 2342 2343 cooling-maps { 2344 map0 { 2345 trip = <&cpu7_alert0>; 2346 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2347 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2348 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2349 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2350 }; 2351 map1 { 2352 trip = <&cpu7_alert1>; 2353 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2354 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2355 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2356 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2357 }; 2358 }; 2359 }; 2360 2361 cpu8-thermal { 2362 polling-delay-passive = <250>; 2363 polling-delay = <0>; 2364 2365 thermal-sensors = <&tsens0 11>; 2366 2367 trips { 2368 cpu8_alert0: trip-point0 { 2369 temperature = <90000>; 2370 hysteresis = <2000>; 2371 type = "passive"; 2372 }; 2373 2374 cpu8_alert1: trip-point1 { 2375 temperature = <95000>; 2376 hysteresis = <2000>; 2377 type = "passive"; 2378 }; 2379 2380 cpu8_crit: cpu-crit { 2381 temperature = <110000>; 2382 hysteresis = <0>; 2383 type = "critical"; 2384 }; 2385 }; 2386 2387 cooling-maps { 2388 map0 { 2389 trip = <&cpu8_alert0>; 2390 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2391 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2392 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2393 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2394 }; 2395 map1 { 2396 trip = <&cpu8_alert1>; 2397 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2398 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2399 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2400 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2401 }; 2402 }; 2403 }; 2404 2405 cpu9-thermal { 2406 polling-delay-passive = <250>; 2407 polling-delay = <0>; 2408 2409 thermal-sensors = <&tsens0 12>; 2410 2411 trips { 2412 cpu9_alert0: trip-point0 { 2413 temperature = <90000>; 2414 hysteresis = <2000>; 2415 type = "passive"; 2416 }; 2417 2418 cpu9_alert1: trip-point1 { 2419 temperature = <95000>; 2420 hysteresis = <2000>; 2421 type = "passive"; 2422 }; 2423 2424 cpu9_crit: cpu-crit { 2425 temperature = <110000>; 2426 hysteresis = <0>; 2427 type = "critical"; 2428 }; 2429 }; 2430 2431 cooling-maps { 2432 map0 { 2433 trip = <&cpu9_alert0>; 2434 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2435 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2436 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2437 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2438 }; 2439 map1 { 2440 trip = <&cpu9_alert1>; 2441 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2442 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2443 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2444 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2445 }; 2446 }; 2447 }; 2448 2449 cpu10-thermal { 2450 polling-delay-passive = <250>; 2451 polling-delay = <0>; 2452 2453 thermal-sensors = <&tsens0 13>; 2454 2455 trips { 2456 cpu10_alert0: trip-point0 { 2457 temperature = <90000>; 2458 hysteresis = <2000>; 2459 type = "passive"; 2460 }; 2461 2462 cpu10_alert1: trip-point1 { 2463 temperature = <95000>; 2464 hysteresis = <2000>; 2465 type = "passive"; 2466 }; 2467 2468 cpu10_crit: cpu-crit { 2469 temperature = <110000>; 2470 hysteresis = <0>; 2471 type = "critical"; 2472 }; 2473 }; 2474 2475 cooling-maps { 2476 map0 { 2477 trip = <&cpu10_alert0>; 2478 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2479 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2480 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2481 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2482 }; 2483 map1 { 2484 trip = <&cpu10_alert1>; 2485 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2486 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2487 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2488 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2489 }; 2490 }; 2491 }; 2492 2493 cpu11-thermal { 2494 polling-delay-passive = <250>; 2495 polling-delay = <0>; 2496 2497 thermal-sensors = <&tsens0 14>; 2498 2499 trips { 2500 cpu11_alert0: trip-point0 { 2501 temperature = <90000>; 2502 hysteresis = <2000>; 2503 type = "passive"; 2504 }; 2505 2506 cpu11_alert1: trip-point1 { 2507 temperature = <95000>; 2508 hysteresis = <2000>; 2509 type = "passive"; 2510 }; 2511 2512 cpu11_crit: cpu-crit { 2513 temperature = <110000>; 2514 hysteresis = <0>; 2515 type = "critical"; 2516 }; 2517 }; 2518 2519 cooling-maps { 2520 map0 { 2521 trip = <&cpu11_alert0>; 2522 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2523 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2524 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2525 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2526 }; 2527 map1 { 2528 trip = <&cpu11_alert1>; 2529 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2530 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2531 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2532 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2533 }; 2534 }; 2535 }; 2536 2537 aoss0-thermal { 2538 polling-delay-passive = <0>; 2539 polling-delay = <0>; 2540 2541 thermal-sensors = <&tsens0 0>; 2542 2543 trips { 2544 aoss0_alert0: trip-point0 { 2545 temperature = <90000>; 2546 hysteresis = <2000>; 2547 type = "hot"; 2548 }; 2549 2550 aoss0_crit: aoss0-crit { 2551 temperature = <110000>; 2552 hysteresis = <0>; 2553 type = "critical"; 2554 }; 2555 }; 2556 }; 2557 2558 aoss1-thermal { 2559 polling-delay-passive = <0>; 2560 polling-delay = <0>; 2561 2562 thermal-sensors = <&tsens1 0>; 2563 2564 trips { 2565 aoss1_alert0: trip-point0 { 2566 temperature = <90000>; 2567 hysteresis = <2000>; 2568 type = "hot"; 2569 }; 2570 2571 aoss1_crit: aoss1-crit { 2572 temperature = <110000>; 2573 hysteresis = <0>; 2574 type = "critical"; 2575 }; 2576 }; 2577 }; 2578 2579 cpuss0-thermal { 2580 polling-delay-passive = <0>; 2581 polling-delay = <0>; 2582 2583 thermal-sensors = <&tsens0 5>; 2584 2585 trips { 2586 cpuss0_alert0: trip-point0 { 2587 temperature = <90000>; 2588 hysteresis = <2000>; 2589 type = "hot"; 2590 }; 2591 cpuss0_crit: cluster0-crit { 2592 temperature = <110000>; 2593 hysteresis = <0>; 2594 type = "critical"; 2595 }; 2596 }; 2597 }; 2598 2599 cpuss1-thermal { 2600 polling-delay-passive = <0>; 2601 polling-delay = <0>; 2602 2603 thermal-sensors = <&tsens0 6>; 2604 2605 trips { 2606 cpuss1_alert0: trip-point0 { 2607 temperature = <90000>; 2608 hysteresis = <2000>; 2609 type = "hot"; 2610 }; 2611 cpuss1_crit: cluster0-crit { 2612 temperature = <110000>; 2613 hysteresis = <0>; 2614 type = "critical"; 2615 }; 2616 }; 2617 }; 2618 2619 gpuss0-thermal { 2620 polling-delay-passive = <0>; 2621 polling-delay = <0>; 2622 2623 thermal-sensors = <&tsens1 1>; 2624 2625 trips { 2626 gpuss0_alert0: trip-point0 { 2627 temperature = <90000>; 2628 hysteresis = <2000>; 2629 type = "hot"; 2630 }; 2631 2632 gpuss0_crit: gpuss0-crit { 2633 temperature = <110000>; 2634 hysteresis = <0>; 2635 type = "critical"; 2636 }; 2637 }; 2638 }; 2639 2640 gpuss1-thermal { 2641 polling-delay-passive = <0>; 2642 polling-delay = <0>; 2643 2644 thermal-sensors = <&tsens1 2>; 2645 2646 trips { 2647 gpuss1_alert0: trip-point0 { 2648 temperature = <90000>; 2649 hysteresis = <2000>; 2650 type = "hot"; 2651 }; 2652 2653 gpuss1_crit: gpuss1-crit { 2654 temperature = <110000>; 2655 hysteresis = <0>; 2656 type = "critical"; 2657 }; 2658 }; 2659 }; 2660 2661 nspss0-thermal { 2662 polling-delay-passive = <0>; 2663 polling-delay = <0>; 2664 2665 thermal-sensors = <&tsens1 3>; 2666 2667 trips { 2668 nspss0_alert0: trip-point0 { 2669 temperature = <90000>; 2670 hysteresis = <2000>; 2671 type = "hot"; 2672 }; 2673 2674 nspss0_crit: nspss0-crit { 2675 temperature = <110000>; 2676 hysteresis = <0>; 2677 type = "critical"; 2678 }; 2679 }; 2680 }; 2681 2682 nspss1-thermal { 2683 polling-delay-passive = <0>; 2684 polling-delay = <0>; 2685 2686 thermal-sensors = <&tsens1 4>; 2687 2688 trips { 2689 nspss1_alert0: trip-point0 { 2690 temperature = <90000>; 2691 hysteresis = <2000>; 2692 type = "hot"; 2693 }; 2694 2695 nspss1_crit: nspss1-crit { 2696 temperature = <110000>; 2697 hysteresis = <0>; 2698 type = "critical"; 2699 }; 2700 }; 2701 }; 2702 2703 video-thermal { 2704 polling-delay-passive = <0>; 2705 polling-delay = <0>; 2706 2707 thermal-sensors = <&tsens1 5>; 2708 2709 trips { 2710 video_alert0: trip-point0 { 2711 temperature = <90000>; 2712 hysteresis = <2000>; 2713 type = "hot"; 2714 }; 2715 2716 video_crit: video-crit { 2717 temperature = <110000>; 2718 hysteresis = <0>; 2719 type = "critical"; 2720 }; 2721 }; 2722 }; 2723 2724 ddr-thermal { 2725 polling-delay-passive = <0>; 2726 polling-delay = <0>; 2727 2728 thermal-sensors = <&tsens1 6>; 2729 2730 trips { 2731 ddr_alert0: trip-point0 { 2732 temperature = <90000>; 2733 hysteresis = <2000>; 2734 type = "hot"; 2735 }; 2736 2737 ddr_crit: ddr-crit { 2738 temperature = <110000>; 2739 hysteresis = <0>; 2740 type = "critical"; 2741 }; 2742 }; 2743 }; 2744 2745 mdmss0-thermal { 2746 polling-delay-passive = <0>; 2747 polling-delay = <0>; 2748 2749 thermal-sensors = <&tsens1 7>; 2750 2751 trips { 2752 mdmss0_alert0: trip-point0 { 2753 temperature = <90000>; 2754 hysteresis = <2000>; 2755 type = "hot"; 2756 }; 2757 2758 mdmss0_crit: mdmss0-crit { 2759 temperature = <110000>; 2760 hysteresis = <0>; 2761 type = "critical"; 2762 }; 2763 }; 2764 }; 2765 2766 mdmss1-thermal { 2767 polling-delay-passive = <0>; 2768 polling-delay = <0>; 2769 2770 thermal-sensors = <&tsens1 8>; 2771 2772 trips { 2773 mdmss1_alert0: trip-point0 { 2774 temperature = <90000>; 2775 hysteresis = <2000>; 2776 type = "hot"; 2777 }; 2778 2779 mdmss1_crit: mdmss1-crit { 2780 temperature = <110000>; 2781 hysteresis = <0>; 2782 type = "critical"; 2783 }; 2784 }; 2785 }; 2786 2787 mdmss2-thermal { 2788 polling-delay-passive = <0>; 2789 polling-delay = <0>; 2790 2791 thermal-sensors = <&tsens1 9>; 2792 2793 trips { 2794 mdmss2_alert0: trip-point0 { 2795 temperature = <90000>; 2796 hysteresis = <2000>; 2797 type = "hot"; 2798 }; 2799 2800 mdmss2_crit: mdmss2-crit { 2801 temperature = <110000>; 2802 hysteresis = <0>; 2803 type = "critical"; 2804 }; 2805 }; 2806 }; 2807 2808 mdmss3-thermal { 2809 polling-delay-passive = <0>; 2810 polling-delay = <0>; 2811 2812 thermal-sensors = <&tsens1 10>; 2813 2814 trips { 2815 mdmss3_alert0: trip-point0 { 2816 temperature = <90000>; 2817 hysteresis = <2000>; 2818 type = "hot"; 2819 }; 2820 2821 mdmss3_crit: mdmss3-crit { 2822 temperature = <110000>; 2823 hysteresis = <0>; 2824 type = "critical"; 2825 }; 2826 }; 2827 }; 2828 2829 camera0-thermal { 2830 polling-delay-passive = <0>; 2831 polling-delay = <0>; 2832 2833 thermal-sensors = <&tsens1 11>; 2834 2835 trips { 2836 camera0_alert0: trip-point0 { 2837 temperature = <90000>; 2838 hysteresis = <2000>; 2839 type = "hot"; 2840 }; 2841 2842 camera0_crit: camera0-crit { 2843 temperature = <110000>; 2844 hysteresis = <0>; 2845 type = "critical"; 2846 }; 2847 }; 2848 }; 2849 }; 2850 2851 timer { 2852 compatible = "arm,armv8-timer"; 2853 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2854 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2855 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2856 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2857 }; 2858}; 2859