1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7280.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 mmc1 = &sdhc_1; 50 mmc2 = &sdhc_2; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi2 = &spi2; 54 spi3 = &spi3; 55 spi4 = &spi4; 56 spi5 = &spi5; 57 spi6 = &spi6; 58 spi7 = &spi7; 59 spi8 = &spi8; 60 spi9 = &spi9; 61 spi10 = &spi10; 62 spi11 = &spi11; 63 spi12 = &spi12; 64 spi13 = &spi13; 65 spi14 = &spi14; 66 spi15 = &spi15; 67 }; 68 69 clocks { 70 xo_board: xo-board { 71 compatible = "fixed-clock"; 72 clock-frequency = <76800000>; 73 #clock-cells = <0>; 74 }; 75 76 sleep_clk: sleep-clk { 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 #clock-cells = <0>; 80 }; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 wlan_ce_mem: memory@4cd000 { 89 no-map; 90 reg = <0x0 0x004cd000 0x0 0x1000>; 91 }; 92 93 hyp_mem: memory@80000000 { 94 reg = <0x0 0x80000000 0x0 0x600000>; 95 no-map; 96 }; 97 98 xbl_mem: memory@80600000 { 99 reg = <0x0 0x80600000 0x0 0x200000>; 100 no-map; 101 }; 102 103 aop_mem: memory@80800000 { 104 reg = <0x0 0x80800000 0x0 0x60000>; 105 no-map; 106 }; 107 108 aop_cmd_db_mem: memory@80860000 { 109 reg = <0x0 0x80860000 0x0 0x20000>; 110 compatible = "qcom,cmd-db"; 111 no-map; 112 }; 113 114 reserved_xbl_uefi_log: memory@80880000 { 115 reg = <0x0 0x80884000 0x0 0x10000>; 116 no-map; 117 }; 118 119 sec_apps_mem: memory@808ff000 { 120 reg = <0x0 0x808ff000 0x0 0x1000>; 121 no-map; 122 }; 123 124 smem_mem: memory@80900000 { 125 reg = <0x0 0x80900000 0x0 0x200000>; 126 no-map; 127 }; 128 129 cpucp_mem: memory@80b00000 { 130 no-map; 131 reg = <0x0 0x80b00000 0x0 0x100000>; 132 }; 133 134 wlan_fw_mem: memory@80c00000 { 135 reg = <0x0 0x80c00000 0x0 0xc00000>; 136 no-map; 137 }; 138 139 video_mem: memory@8b200000 { 140 reg = <0x0 0x8b200000 0x0 0x500000>; 141 no-map; 142 }; 143 144 ipa_fw_mem: memory@8b700000 { 145 reg = <0 0x8b700000 0 0x10000>; 146 no-map; 147 }; 148 149 rmtfs_mem: memory@9c900000 { 150 compatible = "qcom,rmtfs-mem"; 151 reg = <0x0 0x9c900000 0x0 0x280000>; 152 no-map; 153 154 qcom,client-id = <1>; 155 qcom,vmid = <15>; 156 }; 157 }; 158 159 cpus { 160 #address-cells = <2>; 161 #size-cells = <0>; 162 163 CPU0: cpu@0 { 164 device_type = "cpu"; 165 compatible = "arm,kryo"; 166 reg = <0x0 0x0>; 167 enable-method = "psci"; 168 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 169 &LITTLE_CPU_SLEEP_1 170 &CLUSTER_SLEEP_0>; 171 next-level-cache = <&L2_0>; 172 operating-points-v2 = <&cpu0_opp_table>; 173 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 174 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 175 qcom,freq-domain = <&cpufreq_hw 0>; 176 #cooling-cells = <2>; 177 L2_0: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 L3_0: l3-cache { 181 compatible = "cache"; 182 }; 183 }; 184 }; 185 186 CPU1: cpu@100 { 187 device_type = "cpu"; 188 compatible = "arm,kryo"; 189 reg = <0x0 0x100>; 190 enable-method = "psci"; 191 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 192 &LITTLE_CPU_SLEEP_1 193 &CLUSTER_SLEEP_0>; 194 next-level-cache = <&L2_100>; 195 operating-points-v2 = <&cpu0_opp_table>; 196 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 197 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 198 qcom,freq-domain = <&cpufreq_hw 0>; 199 #cooling-cells = <2>; 200 L2_100: l2-cache { 201 compatible = "cache"; 202 next-level-cache = <&L3_0>; 203 }; 204 }; 205 206 CPU2: cpu@200 { 207 device_type = "cpu"; 208 compatible = "arm,kryo"; 209 reg = <0x0 0x200>; 210 enable-method = "psci"; 211 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 212 &LITTLE_CPU_SLEEP_1 213 &CLUSTER_SLEEP_0>; 214 next-level-cache = <&L2_200>; 215 operating-points-v2 = <&cpu0_opp_table>; 216 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 217 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 qcom,freq-domain = <&cpufreq_hw 0>; 219 #cooling-cells = <2>; 220 L2_200: l2-cache { 221 compatible = "cache"; 222 next-level-cache = <&L3_0>; 223 }; 224 }; 225 226 CPU3: cpu@300 { 227 device_type = "cpu"; 228 compatible = "arm,kryo"; 229 reg = <0x0 0x300>; 230 enable-method = "psci"; 231 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 232 &LITTLE_CPU_SLEEP_1 233 &CLUSTER_SLEEP_0>; 234 next-level-cache = <&L2_300>; 235 operating-points-v2 = <&cpu0_opp_table>; 236 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 237 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 238 qcom,freq-domain = <&cpufreq_hw 0>; 239 #cooling-cells = <2>; 240 L2_300: l2-cache { 241 compatible = "cache"; 242 next-level-cache = <&L3_0>; 243 }; 244 }; 245 246 CPU4: cpu@400 { 247 device_type = "cpu"; 248 compatible = "arm,kryo"; 249 reg = <0x0 0x400>; 250 enable-method = "psci"; 251 cpu-idle-states = <&BIG_CPU_SLEEP_0 252 &BIG_CPU_SLEEP_1 253 &CLUSTER_SLEEP_0>; 254 next-level-cache = <&L2_400>; 255 operating-points-v2 = <&cpu4_opp_table>; 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 257 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 258 qcom,freq-domain = <&cpufreq_hw 1>; 259 #cooling-cells = <2>; 260 L2_400: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU5: cpu@500 { 267 device_type = "cpu"; 268 compatible = "arm,kryo"; 269 reg = <0x0 0x500>; 270 enable-method = "psci"; 271 cpu-idle-states = <&BIG_CPU_SLEEP_0 272 &BIG_CPU_SLEEP_1 273 &CLUSTER_SLEEP_0>; 274 next-level-cache = <&L2_500>; 275 operating-points-v2 = <&cpu4_opp_table>; 276 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 277 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 278 qcom,freq-domain = <&cpufreq_hw 1>; 279 #cooling-cells = <2>; 280 L2_500: l2-cache { 281 compatible = "cache"; 282 next-level-cache = <&L3_0>; 283 }; 284 }; 285 286 CPU6: cpu@600 { 287 device_type = "cpu"; 288 compatible = "arm,kryo"; 289 reg = <0x0 0x600>; 290 enable-method = "psci"; 291 cpu-idle-states = <&BIG_CPU_SLEEP_0 292 &BIG_CPU_SLEEP_1 293 &CLUSTER_SLEEP_0>; 294 next-level-cache = <&L2_600>; 295 operating-points-v2 = <&cpu4_opp_table>; 296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 297 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 298 qcom,freq-domain = <&cpufreq_hw 1>; 299 #cooling-cells = <2>; 300 L2_600: l2-cache { 301 compatible = "cache"; 302 next-level-cache = <&L3_0>; 303 }; 304 }; 305 306 CPU7: cpu@700 { 307 device_type = "cpu"; 308 compatible = "arm,kryo"; 309 reg = <0x0 0x700>; 310 enable-method = "psci"; 311 cpu-idle-states = <&BIG_CPU_SLEEP_0 312 &BIG_CPU_SLEEP_1 313 &CLUSTER_SLEEP_0>; 314 next-level-cache = <&L2_700>; 315 operating-points-v2 = <&cpu7_opp_table>; 316 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 317 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 318 qcom,freq-domain = <&cpufreq_hw 2>; 319 #cooling-cells = <2>; 320 L2_700: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 cpu-map { 327 cluster0 { 328 core0 { 329 cpu = <&CPU0>; 330 }; 331 332 core1 { 333 cpu = <&CPU1>; 334 }; 335 336 core2 { 337 cpu = <&CPU2>; 338 }; 339 340 core3 { 341 cpu = <&CPU3>; 342 }; 343 344 core4 { 345 cpu = <&CPU4>; 346 }; 347 348 core5 { 349 cpu = <&CPU5>; 350 }; 351 352 core6 { 353 cpu = <&CPU6>; 354 }; 355 356 core7 { 357 cpu = <&CPU7>; 358 }; 359 }; 360 }; 361 362 idle-states { 363 entry-method = "psci"; 364 365 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "little-power-down"; 368 arm,psci-suspend-param = <0x40000003>; 369 entry-latency-us = <549>; 370 exit-latency-us = <901>; 371 min-residency-us = <1774>; 372 local-timer-stop; 373 }; 374 375 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "little-rail-power-down"; 378 arm,psci-suspend-param = <0x40000004>; 379 entry-latency-us = <702>; 380 exit-latency-us = <915>; 381 min-residency-us = <4001>; 382 local-timer-stop; 383 }; 384 385 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 386 compatible = "arm,idle-state"; 387 idle-state-name = "big-power-down"; 388 arm,psci-suspend-param = <0x40000003>; 389 entry-latency-us = <523>; 390 exit-latency-us = <1244>; 391 min-residency-us = <2207>; 392 local-timer-stop; 393 }; 394 395 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "big-rail-power-down"; 398 arm,psci-suspend-param = <0x40000004>; 399 entry-latency-us = <526>; 400 exit-latency-us = <1854>; 401 min-residency-us = <5555>; 402 local-timer-stop; 403 }; 404 405 CLUSTER_SLEEP_0: cluster-sleep-0 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "cluster-power-down"; 408 arm,psci-suspend-param = <0x40003444>; 409 entry-latency-us = <3263>; 410 exit-latency-us = <6562>; 411 min-residency-us = <9926>; 412 local-timer-stop; 413 }; 414 }; 415 }; 416 417 cpu0_opp_table: cpu0-opp-table { 418 compatible = "operating-points-v2"; 419 opp-shared; 420 421 cpu0_opp_300mhz: opp-300000000 { 422 opp-hz = /bits/ 64 <300000000>; 423 opp-peak-kBps = <800000 9600000>; 424 }; 425 426 cpu0_opp_691mhz: opp-691200000 { 427 opp-hz = /bits/ 64 <691200000>; 428 opp-peak-kBps = <800000 17817600>; 429 }; 430 431 cpu0_opp_806mhz: opp-806400000 { 432 opp-hz = /bits/ 64 <806400000>; 433 opp-peak-kBps = <800000 20889600>; 434 }; 435 436 cpu0_opp_941mhz: opp-940800000 { 437 opp-hz = /bits/ 64 <940800000>; 438 opp-peak-kBps = <1804000 24576000>; 439 }; 440 441 cpu0_opp_1152mhz: opp-1152000000 { 442 opp-hz = /bits/ 64 <1152000000>; 443 opp-peak-kBps = <2188000 27033600>; 444 }; 445 446 cpu0_opp_1325mhz: opp-1324800000 { 447 opp-hz = /bits/ 64 <1324800000>; 448 opp-peak-kBps = <2188000 33792000>; 449 }; 450 451 cpu0_opp_1517mhz: opp-1516800000 { 452 opp-hz = /bits/ 64 <1516800000>; 453 opp-peak-kBps = <3072000 38092800>; 454 }; 455 456 cpu0_opp_1651mhz: opp-1651200000 { 457 opp-hz = /bits/ 64 <1651200000>; 458 opp-peak-kBps = <3072000 41779200>; 459 }; 460 461 cpu0_opp_1805mhz: opp-1804800000 { 462 opp-hz = /bits/ 64 <1804800000>; 463 opp-peak-kBps = <4068000 48537600>; 464 }; 465 466 cpu0_opp_1958mhz: opp-1958400000 { 467 opp-hz = /bits/ 64 <1958400000>; 468 opp-peak-kBps = <4068000 48537600>; 469 }; 470 471 cpu0_opp_2016mhz: opp-2016000000 { 472 opp-hz = /bits/ 64 <2016000000>; 473 opp-peak-kBps = <6220000 48537600>; 474 }; 475 }; 476 477 cpu4_opp_table: cpu4-opp-table { 478 compatible = "operating-points-v2"; 479 opp-shared; 480 481 cpu4_opp_691mhz: opp-691200000 { 482 opp-hz = /bits/ 64 <691200000>; 483 opp-peak-kBps = <1804000 9600000>; 484 }; 485 486 cpu4_opp_941mhz: opp-940800000 { 487 opp-hz = /bits/ 64 <940800000>; 488 opp-peak-kBps = <2188000 17817600>; 489 }; 490 491 cpu4_opp_1229mhz: opp-1228800000 { 492 opp-hz = /bits/ 64 <1228800000>; 493 opp-peak-kBps = <4068000 24576000>; 494 }; 495 496 cpu4_opp_1344mhz: opp-1344000000 { 497 opp-hz = /bits/ 64 <1344000000>; 498 opp-peak-kBps = <4068000 24576000>; 499 }; 500 501 cpu4_opp_1517mhz: opp-1516800000 { 502 opp-hz = /bits/ 64 <1516800000>; 503 opp-peak-kBps = <4068000 24576000>; 504 }; 505 506 cpu4_opp_1651mhz: opp-1651200000 { 507 opp-hz = /bits/ 64 <1651200000>; 508 opp-peak-kBps = <6220000 38092800>; 509 }; 510 511 cpu4_opp_1901mhz: opp-1900800000 { 512 opp-hz = /bits/ 64 <1900800000>; 513 opp-peak-kBps = <6220000 44851200>; 514 }; 515 516 cpu4_opp_2054mhz: opp-2054400000 { 517 opp-hz = /bits/ 64 <2054400000>; 518 opp-peak-kBps = <6220000 44851200>; 519 }; 520 521 cpu4_opp_2112mhz: opp-2112000000 { 522 opp-hz = /bits/ 64 <2112000000>; 523 opp-peak-kBps = <6220000 44851200>; 524 }; 525 526 cpu4_opp_2131mhz: opp-2131200000 { 527 opp-hz = /bits/ 64 <2131200000>; 528 opp-peak-kBps = <6220000 44851200>; 529 }; 530 531 cpu4_opp_2208mhz: opp-2208000000 { 532 opp-hz = /bits/ 64 <2208000000>; 533 opp-peak-kBps = <6220000 44851200>; 534 }; 535 536 cpu4_opp_2400mhz: opp-2400000000 { 537 opp-hz = /bits/ 64 <2400000000>; 538 opp-peak-kBps = <8532000 48537600>; 539 }; 540 541 cpu4_opp_2611mhz: opp-2611200000 { 542 opp-hz = /bits/ 64 <2611200000>; 543 opp-peak-kBps = <8532000 48537600>; 544 }; 545 }; 546 547 cpu7_opp_table: cpu7-opp-table { 548 compatible = "operating-points-v2"; 549 opp-shared; 550 551 cpu7_opp_806mhz: opp-806400000 { 552 opp-hz = /bits/ 64 <806400000>; 553 opp-peak-kBps = <1804000 9600000>; 554 }; 555 556 cpu7_opp_1056mhz: opp-1056000000 { 557 opp-hz = /bits/ 64 <1056000000>; 558 opp-peak-kBps = <2188000 17817600>; 559 }; 560 561 cpu7_opp_1325mhz: opp-1324800000 { 562 opp-hz = /bits/ 64 <1324800000>; 563 opp-peak-kBps = <4068000 24576000>; 564 }; 565 566 cpu7_opp_1517mhz: opp-1516800000 { 567 opp-hz = /bits/ 64 <1516800000>; 568 opp-peak-kBps = <4068000 24576000>; 569 }; 570 571 cpu7_opp_1766mhz: opp-1766400000 { 572 opp-hz = /bits/ 64 <1766400000>; 573 opp-peak-kBps = <6220000 38092800>; 574 }; 575 576 cpu7_opp_1862mhz: opp-1862400000 { 577 opp-hz = /bits/ 64 <1862400000>; 578 opp-peak-kBps = <6220000 38092800>; 579 }; 580 581 cpu7_opp_2035mhz: opp-2035200000 { 582 opp-hz = /bits/ 64 <2035200000>; 583 opp-peak-kBps = <6220000 38092800>; 584 }; 585 586 cpu7_opp_2112mhz: opp-2112000000 { 587 opp-hz = /bits/ 64 <2112000000>; 588 opp-peak-kBps = <6220000 44851200>; 589 }; 590 591 cpu7_opp_2208mhz: opp-2208000000 { 592 opp-hz = /bits/ 64 <2208000000>; 593 opp-peak-kBps = <6220000 44851200>; 594 }; 595 596 cpu7_opp_2381mhz: opp-2380800000 { 597 opp-hz = /bits/ 64 <2380800000>; 598 opp-peak-kBps = <6832000 44851200>; 599 }; 600 601 cpu7_opp_2400mhz: opp-2400000000 { 602 opp-hz = /bits/ 64 <2400000000>; 603 opp-peak-kBps = <8532000 48537600>; 604 }; 605 606 cpu7_opp_2515mhz: opp-2515200000 { 607 opp-hz = /bits/ 64 <2515200000>; 608 opp-peak-kBps = <8532000 48537600>; 609 }; 610 611 cpu7_opp_2707mhz: opp-2707200000 { 612 opp-hz = /bits/ 64 <2707200000>; 613 opp-peak-kBps = <8532000 48537600>; 614 }; 615 616 cpu7_opp_3014mhz: opp-3014400000 { 617 opp-hz = /bits/ 64 <3014400000>; 618 opp-peak-kBps = <8532000 48537600>; 619 }; 620 }; 621 622 memory@80000000 { 623 device_type = "memory"; 624 /* We expect the bootloader to fill in the size */ 625 reg = <0 0x80000000 0 0>; 626 }; 627 628 firmware { 629 scm { 630 compatible = "qcom,scm-sc7280", "qcom,scm"; 631 }; 632 }; 633 634 clk_virt: interconnect { 635 compatible = "qcom,sc7280-clk-virt"; 636 #interconnect-cells = <2>; 637 qcom,bcm-voters = <&apps_bcm_voter>; 638 }; 639 640 smem { 641 compatible = "qcom,smem"; 642 memory-region = <&smem_mem>; 643 hwlocks = <&tcsr_mutex 3>; 644 }; 645 646 smp2p-adsp { 647 compatible = "qcom,smp2p"; 648 qcom,smem = <443>, <429>; 649 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 650 IPCC_MPROC_SIGNAL_SMP2P 651 IRQ_TYPE_EDGE_RISING>; 652 mboxes = <&ipcc IPCC_CLIENT_LPASS 653 IPCC_MPROC_SIGNAL_SMP2P>; 654 655 qcom,local-pid = <0>; 656 qcom,remote-pid = <2>; 657 658 adsp_smp2p_out: master-kernel { 659 qcom,entry-name = "master-kernel"; 660 #qcom,smem-state-cells = <1>; 661 }; 662 663 adsp_smp2p_in: slave-kernel { 664 qcom,entry-name = "slave-kernel"; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 }; 668 }; 669 670 smp2p-cdsp { 671 compatible = "qcom,smp2p"; 672 qcom,smem = <94>, <432>; 673 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 674 IPCC_MPROC_SIGNAL_SMP2P 675 IRQ_TYPE_EDGE_RISING>; 676 mboxes = <&ipcc IPCC_CLIENT_CDSP 677 IPCC_MPROC_SIGNAL_SMP2P>; 678 679 qcom,local-pid = <0>; 680 qcom,remote-pid = <5>; 681 682 cdsp_smp2p_out: master-kernel { 683 qcom,entry-name = "master-kernel"; 684 #qcom,smem-state-cells = <1>; 685 }; 686 687 cdsp_smp2p_in: slave-kernel { 688 qcom,entry-name = "slave-kernel"; 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 }; 692 }; 693 694 smp2p-mpss { 695 compatible = "qcom,smp2p"; 696 qcom,smem = <435>, <428>; 697 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 698 IPCC_MPROC_SIGNAL_SMP2P 699 IRQ_TYPE_EDGE_RISING>; 700 mboxes = <&ipcc IPCC_CLIENT_MPSS 701 IPCC_MPROC_SIGNAL_SMP2P>; 702 703 qcom,local-pid = <0>; 704 qcom,remote-pid = <1>; 705 706 modem_smp2p_out: master-kernel { 707 qcom,entry-name = "master-kernel"; 708 #qcom,smem-state-cells = <1>; 709 }; 710 711 modem_smp2p_in: slave-kernel { 712 qcom,entry-name = "slave-kernel"; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 717 ipa_smp2p_out: ipa-ap-to-modem { 718 qcom,entry-name = "ipa"; 719 #qcom,smem-state-cells = <1>; 720 }; 721 722 ipa_smp2p_in: ipa-modem-to-ap { 723 qcom,entry-name = "ipa"; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 }; 728 729 smp2p-wpss { 730 compatible = "qcom,smp2p"; 731 qcom,smem = <617>, <616>; 732 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 733 IPCC_MPROC_SIGNAL_SMP2P 734 IRQ_TYPE_EDGE_RISING>; 735 mboxes = <&ipcc IPCC_CLIENT_WPSS 736 IPCC_MPROC_SIGNAL_SMP2P>; 737 738 qcom,local-pid = <0>; 739 qcom,remote-pid = <13>; 740 741 wpss_smp2p_out: master-kernel { 742 qcom,entry-name = "master-kernel"; 743 #qcom,smem-state-cells = <1>; 744 }; 745 746 wpss_smp2p_in: slave-kernel { 747 qcom,entry-name = "slave-kernel"; 748 interrupt-controller; 749 #interrupt-cells = <2>; 750 }; 751 }; 752 753 pmu { 754 compatible = "arm,armv8-pmuv3"; 755 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 756 }; 757 758 psci { 759 compatible = "arm,psci-1.0"; 760 method = "smc"; 761 }; 762 763 qspi_opp_table: qspi-opp-table { 764 compatible = "operating-points-v2"; 765 766 opp-75000000 { 767 opp-hz = /bits/ 64 <75000000>; 768 required-opps = <&rpmhpd_opp_low_svs>; 769 }; 770 771 opp-150000000 { 772 opp-hz = /bits/ 64 <150000000>; 773 required-opps = <&rpmhpd_opp_svs>; 774 }; 775 776 opp-200000000 { 777 opp-hz = /bits/ 64 <200000000>; 778 required-opps = <&rpmhpd_opp_svs_l1>; 779 }; 780 781 opp-300000000 { 782 opp-hz = /bits/ 64 <300000000>; 783 required-opps = <&rpmhpd_opp_nom>; 784 }; 785 }; 786 787 qup_opp_table: qup-opp-table { 788 compatible = "operating-points-v2"; 789 790 opp-75000000 { 791 opp-hz = /bits/ 64 <75000000>; 792 required-opps = <&rpmhpd_opp_low_svs>; 793 }; 794 795 opp-100000000 { 796 opp-hz = /bits/ 64 <100000000>; 797 required-opps = <&rpmhpd_opp_svs>; 798 }; 799 800 opp-128000000 { 801 opp-hz = /bits/ 64 <128000000>; 802 required-opps = <&rpmhpd_opp_nom>; 803 }; 804 }; 805 806 soc: soc@0 { 807 #address-cells = <2>; 808 #size-cells = <2>; 809 ranges = <0 0 0 0 0x10 0>; 810 dma-ranges = <0 0 0 0 0x10 0>; 811 compatible = "simple-bus"; 812 813 gcc: clock-controller@100000 { 814 compatible = "qcom,gcc-sc7280"; 815 reg = <0 0x00100000 0 0x1f0000>; 816 clocks = <&rpmhcc RPMH_CXO_CLK>, 817 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 818 <0>, <&pcie1_lane 0>, 819 <0>, <0>, <0>, <0>; 820 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 821 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 822 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 823 "ufs_phy_tx_symbol_0_clk", 824 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 825 #clock-cells = <1>; 826 #reset-cells = <1>; 827 #power-domain-cells = <1>; 828 }; 829 830 ipcc: mailbox@408000 { 831 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 832 reg = <0 0x00408000 0 0x1000>; 833 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-controller; 835 #interrupt-cells = <3>; 836 #mbox-cells = <2>; 837 }; 838 839 qfprom: efuse@784000 { 840 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 841 reg = <0 0x00784000 0 0xa20>, 842 <0 0x00780000 0 0xa20>, 843 <0 0x00782000 0 0x120>, 844 <0 0x00786000 0 0x1fff>; 845 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 846 clock-names = "core"; 847 power-domains = <&rpmhpd SC7280_MX>; 848 #address-cells = <1>; 849 #size-cells = <1>; 850 }; 851 852 sdhc_1: sdhci@7c4000 { 853 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 854 pinctrl-names = "default", "sleep"; 855 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 856 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 857 status = "disabled"; 858 859 reg = <0 0x007c4000 0 0x1000>, 860 <0 0x007c5000 0 0x1000>; 861 reg-names = "hc", "cqhci"; 862 863 iommus = <&apps_smmu 0xc0 0x0>; 864 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 866 interrupt-names = "hc_irq", "pwr_irq"; 867 868 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 869 <&gcc GCC_SDCC1_AHB_CLK>, 870 <&rpmhcc RPMH_CXO_CLK>; 871 clock-names = "core", "iface", "xo"; 872 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 874 interconnect-names = "sdhc-ddr","cpu-sdhc"; 875 power-domains = <&rpmhpd SC7280_CX>; 876 operating-points-v2 = <&sdhc1_opp_table>; 877 878 bus-width = <8>; 879 supports-cqe; 880 881 qcom,dll-config = <0x0007642c>; 882 qcom,ddr-config = <0x80040868>; 883 884 mmc-ddr-1_8v; 885 mmc-hs200-1_8v; 886 mmc-hs400-1_8v; 887 mmc-hs400-enhanced-strobe; 888 889 resets = <&gcc GCC_SDCC1_BCR>; 890 891 sdhc1_opp_table: opp-table { 892 compatible = "operating-points-v2"; 893 894 opp-100000000 { 895 opp-hz = /bits/ 64 <100000000>; 896 required-opps = <&rpmhpd_opp_low_svs>; 897 opp-peak-kBps = <1800000 400000>; 898 opp-avg-kBps = <100000 0>; 899 }; 900 901 opp-384000000 { 902 opp-hz = /bits/ 64 <384000000>; 903 required-opps = <&rpmhpd_opp_nom>; 904 opp-peak-kBps = <5400000 1600000>; 905 opp-avg-kBps = <390000 0>; 906 }; 907 }; 908 909 }; 910 911 qupv3_id_0: geniqup@9c0000 { 912 compatible = "qcom,geni-se-qup"; 913 reg = <0 0x009c0000 0 0x2000>; 914 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 915 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 916 clock-names = "m-ahb", "s-ahb"; 917 #address-cells = <2>; 918 #size-cells = <2>; 919 ranges; 920 iommus = <&apps_smmu 0x123 0x0>; 921 status = "disabled"; 922 923 i2c0: i2c@980000 { 924 compatible = "qcom,geni-i2c"; 925 reg = <0 0x00980000 0 0x4000>; 926 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 927 clock-names = "se"; 928 pinctrl-names = "default"; 929 pinctrl-0 = <&qup_i2c0_data_clk>; 930 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 934 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 935 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 936 interconnect-names = "qup-core", "qup-config", 937 "qup-memory"; 938 status = "disabled"; 939 }; 940 941 spi0: spi@980000 { 942 compatible = "qcom,geni-spi"; 943 reg = <0 0x00980000 0 0x4000>; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 945 clock-names = "se"; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 948 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 power-domains = <&rpmhpd SC7280_CX>; 952 operating-points-v2 = <&qup_opp_table>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 954 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 955 interconnect-names = "qup-core", "qup-config"; 956 status = "disabled"; 957 }; 958 959 uart0: serial@980000 { 960 compatible = "qcom,geni-uart"; 961 reg = <0 0x00980000 0 0x4000>; 962 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 963 clock-names = "se"; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 966 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 967 power-domains = <&rpmhpd SC7280_CX>; 968 operating-points-v2 = <&qup_opp_table>; 969 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 970 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 971 interconnect-names = "qup-core", "qup-config"; 972 status = "disabled"; 973 }; 974 975 i2c1: i2c@984000 { 976 compatible = "qcom,geni-i2c"; 977 reg = <0 0x00984000 0 0x4000>; 978 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 979 clock-names = "se"; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&qup_i2c1_data_clk>; 982 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 986 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 987 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 988 interconnect-names = "qup-core", "qup-config", 989 "qup-memory"; 990 status = "disabled"; 991 }; 992 993 spi1: spi@984000 { 994 compatible = "qcom,geni-spi"; 995 reg = <0 0x00984000 0 0x4000>; 996 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 997 clock-names = "se"; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1000 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 power-domains = <&rpmhpd SC7280_CX>; 1004 operating-points-v2 = <&qup_opp_table>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1007 interconnect-names = "qup-core", "qup-config"; 1008 status = "disabled"; 1009 }; 1010 1011 uart1: serial@984000 { 1012 compatible = "qcom,geni-uart"; 1013 reg = <0 0x00984000 0 0x4000>; 1014 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1015 clock-names = "se"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1018 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1019 power-domains = <&rpmhpd SC7280_CX>; 1020 operating-points-v2 = <&qup_opp_table>; 1021 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1022 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1023 interconnect-names = "qup-core", "qup-config"; 1024 status = "disabled"; 1025 }; 1026 1027 i2c2: i2c@988000 { 1028 compatible = "qcom,geni-i2c"; 1029 reg = <0 0x00988000 0 0x4000>; 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1031 clock-names = "se"; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_i2c2_data_clk>; 1034 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1039 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1040 interconnect-names = "qup-core", "qup-config", 1041 "qup-memory"; 1042 status = "disabled"; 1043 }; 1044 1045 spi2: spi@988000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0 0x00988000 0 0x4000>; 1048 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1049 clock-names = "se"; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1052 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 power-domains = <&rpmhpd SC7280_CX>; 1056 operating-points-v2 = <&qup_opp_table>; 1057 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1058 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1059 interconnect-names = "qup-core", "qup-config"; 1060 status = "disabled"; 1061 }; 1062 1063 uart2: serial@988000 { 1064 compatible = "qcom,geni-uart"; 1065 reg = <0 0x00988000 0 0x4000>; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1067 clock-names = "se"; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1070 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1071 power-domains = <&rpmhpd SC7280_CX>; 1072 operating-points-v2 = <&qup_opp_table>; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1074 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1075 interconnect-names = "qup-core", "qup-config"; 1076 status = "disabled"; 1077 }; 1078 1079 i2c3: i2c@98c000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x0098c000 0 0x4000>; 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1083 clock-names = "se"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_i2c3_data_clk>; 1086 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1091 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1092 interconnect-names = "qup-core", "qup-config", 1093 "qup-memory"; 1094 status = "disabled"; 1095 }; 1096 1097 spi3: spi@98c000 { 1098 compatible = "qcom,geni-spi"; 1099 reg = <0 0x0098c000 0 0x4000>; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1101 clock-names = "se"; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1104 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 power-domains = <&rpmhpd SC7280_CX>; 1108 operating-points-v2 = <&qup_opp_table>; 1109 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1110 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1111 interconnect-names = "qup-core", "qup-config"; 1112 status = "disabled"; 1113 }; 1114 1115 uart3: serial@98c000 { 1116 compatible = "qcom,geni-uart"; 1117 reg = <0 0x0098c000 0 0x4000>; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1119 clock-names = "se"; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1122 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1123 power-domains = <&rpmhpd SC7280_CX>; 1124 operating-points-v2 = <&qup_opp_table>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1126 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1127 interconnect-names = "qup-core", "qup-config"; 1128 status = "disabled"; 1129 }; 1130 1131 i2c4: i2c@990000 { 1132 compatible = "qcom,geni-i2c"; 1133 reg = <0 0x00990000 0 0x4000>; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1135 clock-names = "se"; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&qup_i2c4_data_clk>; 1138 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1143 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1144 interconnect-names = "qup-core", "qup-config", 1145 "qup-memory"; 1146 status = "disabled"; 1147 }; 1148 1149 spi4: spi@990000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0 0x00990000 0 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1153 clock-names = "se"; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1156 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 power-domains = <&rpmhpd SC7280_CX>; 1160 operating-points-v2 = <&qup_opp_table>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1162 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 status = "disabled"; 1165 }; 1166 1167 uart4: serial@990000 { 1168 compatible = "qcom,geni-uart"; 1169 reg = <0 0x00990000 0 0x4000>; 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1171 clock-names = "se"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1174 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1175 power-domains = <&rpmhpd SC7280_CX>; 1176 operating-points-v2 = <&qup_opp_table>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1179 interconnect-names = "qup-core", "qup-config"; 1180 status = "disabled"; 1181 }; 1182 1183 i2c5: i2c@994000 { 1184 compatible = "qcom,geni-i2c"; 1185 reg = <0 0x00994000 0 0x4000>; 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1187 clock-names = "se"; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&qup_i2c5_data_clk>; 1190 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1195 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1196 interconnect-names = "qup-core", "qup-config", 1197 "qup-memory"; 1198 status = "disabled"; 1199 }; 1200 1201 spi5: spi@994000 { 1202 compatible = "qcom,geni-spi"; 1203 reg = <0 0x00994000 0 0x4000>; 1204 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1205 clock-names = "se"; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1208 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 power-domains = <&rpmhpd SC7280_CX>; 1212 operating-points-v2 = <&qup_opp_table>; 1213 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1214 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1215 interconnect-names = "qup-core", "qup-config"; 1216 status = "disabled"; 1217 }; 1218 1219 uart5: serial@994000 { 1220 compatible = "qcom,geni-uart"; 1221 reg = <0 0x00994000 0 0x4000>; 1222 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1223 clock-names = "se"; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1226 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1227 power-domains = <&rpmhpd SC7280_CX>; 1228 operating-points-v2 = <&qup_opp_table>; 1229 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1230 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1231 interconnect-names = "qup-core", "qup-config"; 1232 status = "disabled"; 1233 }; 1234 1235 i2c6: i2c@998000 { 1236 compatible = "qcom,geni-i2c"; 1237 reg = <0 0x00998000 0 0x4000>; 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1239 clock-names = "se"; 1240 pinctrl-names = "default"; 1241 pinctrl-0 = <&qup_i2c6_data_clk>; 1242 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1246 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1247 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1248 interconnect-names = "qup-core", "qup-config", 1249 "qup-memory"; 1250 status = "disabled"; 1251 }; 1252 1253 spi6: spi@998000 { 1254 compatible = "qcom,geni-spi"; 1255 reg = <0 0x00998000 0 0x4000>; 1256 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1257 clock-names = "se"; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1260 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 power-domains = <&rpmhpd SC7280_CX>; 1264 operating-points-v2 = <&qup_opp_table>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1267 interconnect-names = "qup-core", "qup-config"; 1268 status = "disabled"; 1269 }; 1270 1271 uart6: serial@998000 { 1272 compatible = "qcom,geni-uart"; 1273 reg = <0 0x00998000 0 0x4000>; 1274 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1275 clock-names = "se"; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1278 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1279 power-domains = <&rpmhpd SC7280_CX>; 1280 operating-points-v2 = <&qup_opp_table>; 1281 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1282 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1283 interconnect-names = "qup-core", "qup-config"; 1284 status = "disabled"; 1285 }; 1286 1287 i2c7: i2c@99c000 { 1288 compatible = "qcom,geni-i2c"; 1289 reg = <0 0x0099c000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1291 clock-names = "se"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_i2c7_data_clk>; 1294 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1299 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1300 interconnect-names = "qup-core", "qup-config", 1301 "qup-memory"; 1302 status = "disabled"; 1303 }; 1304 1305 spi7: spi@99c000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0 0x0099c000 0 0x4000>; 1308 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1309 clock-names = "se"; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1312 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 power-domains = <&rpmhpd SC7280_CX>; 1316 operating-points-v2 = <&qup_opp_table>; 1317 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1318 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1319 interconnect-names = "qup-core", "qup-config"; 1320 status = "disabled"; 1321 }; 1322 1323 uart7: serial@99c000 { 1324 compatible = "qcom,geni-uart"; 1325 reg = <0 0x0099c000 0 0x4000>; 1326 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1327 clock-names = "se"; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1330 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1331 power-domains = <&rpmhpd SC7280_CX>; 1332 operating-points-v2 = <&qup_opp_table>; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1334 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1335 interconnect-names = "qup-core", "qup-config"; 1336 status = "disabled"; 1337 }; 1338 }; 1339 1340 qupv3_id_1: geniqup@ac0000 { 1341 compatible = "qcom,geni-se-qup"; 1342 reg = <0 0x00ac0000 0 0x2000>; 1343 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1344 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1345 clock-names = "m-ahb", "s-ahb"; 1346 #address-cells = <2>; 1347 #size-cells = <2>; 1348 ranges; 1349 iommus = <&apps_smmu 0x43 0x0>; 1350 status = "disabled"; 1351 1352 i2c8: i2c@a80000 { 1353 compatible = "qcom,geni-i2c"; 1354 reg = <0 0x00a80000 0 0x4000>; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1356 clock-names = "se"; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_i2c8_data_clk>; 1359 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1364 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", 1366 "qup-memory"; 1367 status = "disabled"; 1368 }; 1369 1370 spi8: spi@a80000 { 1371 compatible = "qcom,geni-spi"; 1372 reg = <0 0x00a80000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1377 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 power-domains = <&rpmhpd SC7280_CX>; 1381 operating-points-v2 = <&qup_opp_table>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1383 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1384 interconnect-names = "qup-core", "qup-config"; 1385 status = "disabled"; 1386 }; 1387 1388 uart8: serial@a80000 { 1389 compatible = "qcom,geni-uart"; 1390 reg = <0 0x00a80000 0 0x4000>; 1391 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1392 clock-names = "se"; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1395 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1396 power-domains = <&rpmhpd SC7280_CX>; 1397 operating-points-v2 = <&qup_opp_table>; 1398 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1399 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1400 interconnect-names = "qup-core", "qup-config"; 1401 status = "disabled"; 1402 }; 1403 1404 i2c9: i2c@a84000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0 0x00a84000 0 0x4000>; 1407 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1408 clock-names = "se"; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_i2c9_data_clk>; 1411 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1415 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1416 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1417 interconnect-names = "qup-core", "qup-config", 1418 "qup-memory"; 1419 status = "disabled"; 1420 }; 1421 1422 spi9: spi@a84000 { 1423 compatible = "qcom,geni-spi"; 1424 reg = <0 0x00a84000 0 0x4000>; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1426 clock-names = "se"; 1427 pinctrl-names = "default"; 1428 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1429 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 power-domains = <&rpmhpd SC7280_CX>; 1433 operating-points-v2 = <&qup_opp_table>; 1434 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1435 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1436 interconnect-names = "qup-core", "qup-config"; 1437 status = "disabled"; 1438 }; 1439 1440 uart9: serial@a84000 { 1441 compatible = "qcom,geni-uart"; 1442 reg = <0 0x00a84000 0 0x4000>; 1443 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1444 clock-names = "se"; 1445 pinctrl-names = "default"; 1446 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1447 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1448 power-domains = <&rpmhpd SC7280_CX>; 1449 operating-points-v2 = <&qup_opp_table>; 1450 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1451 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1452 interconnect-names = "qup-core", "qup-config"; 1453 status = "disabled"; 1454 }; 1455 1456 i2c10: i2c@a88000 { 1457 compatible = "qcom,geni-i2c"; 1458 reg = <0 0x00a88000 0 0x4000>; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1460 clock-names = "se"; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_i2c10_data_clk>; 1463 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1467 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1468 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1469 interconnect-names = "qup-core", "qup-config", 1470 "qup-memory"; 1471 status = "disabled"; 1472 }; 1473 1474 spi10: spi@a88000 { 1475 compatible = "qcom,geni-spi"; 1476 reg = <0 0x00a88000 0 0x4000>; 1477 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1478 clock-names = "se"; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1481 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 power-domains = <&rpmhpd SC7280_CX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1487 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1488 interconnect-names = "qup-core", "qup-config"; 1489 status = "disabled"; 1490 }; 1491 1492 uart10: serial@a88000 { 1493 compatible = "qcom,geni-uart"; 1494 reg = <0 0x00a88000 0 0x4000>; 1495 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1496 clock-names = "se"; 1497 pinctrl-names = "default"; 1498 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1499 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1500 power-domains = <&rpmhpd SC7280_CX>; 1501 operating-points-v2 = <&qup_opp_table>; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1503 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1504 interconnect-names = "qup-core", "qup-config"; 1505 status = "disabled"; 1506 }; 1507 1508 i2c11: i2c@a8c000 { 1509 compatible = "qcom,geni-i2c"; 1510 reg = <0 0x00a8c000 0 0x4000>; 1511 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1512 clock-names = "se"; 1513 pinctrl-names = "default"; 1514 pinctrl-0 = <&qup_i2c11_data_clk>; 1515 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1519 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1520 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1521 interconnect-names = "qup-core", "qup-config", 1522 "qup-memory"; 1523 status = "disabled"; 1524 }; 1525 1526 spi11: spi@a8c000 { 1527 compatible = "qcom,geni-spi"; 1528 reg = <0 0x00a8c000 0 0x4000>; 1529 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1530 clock-names = "se"; 1531 pinctrl-names = "default"; 1532 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1533 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 power-domains = <&rpmhpd SC7280_CX>; 1537 operating-points-v2 = <&qup_opp_table>; 1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1539 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1540 interconnect-names = "qup-core", "qup-config"; 1541 status = "disabled"; 1542 }; 1543 1544 uart11: serial@a8c000 { 1545 compatible = "qcom,geni-uart"; 1546 reg = <0 0x00a8c000 0 0x4000>; 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1548 clock-names = "se"; 1549 pinctrl-names = "default"; 1550 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1551 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1552 power-domains = <&rpmhpd SC7280_CX>; 1553 operating-points-v2 = <&qup_opp_table>; 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1555 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1556 interconnect-names = "qup-core", "qup-config"; 1557 status = "disabled"; 1558 }; 1559 1560 i2c12: i2c@a90000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00a90000 0 0x4000>; 1563 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1564 clock-names = "se"; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c12_data_clk>; 1567 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1571 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1572 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1573 interconnect-names = "qup-core", "qup-config", 1574 "qup-memory"; 1575 status = "disabled"; 1576 }; 1577 1578 spi12: spi@a90000 { 1579 compatible = "qcom,geni-spi"; 1580 reg = <0 0x00a90000 0 0x4000>; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1582 clock-names = "se"; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1585 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 power-domains = <&rpmhpd SC7280_CX>; 1589 operating-points-v2 = <&qup_opp_table>; 1590 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1591 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1592 interconnect-names = "qup-core", "qup-config"; 1593 status = "disabled"; 1594 }; 1595 1596 uart12: serial@a90000 { 1597 compatible = "qcom,geni-uart"; 1598 reg = <0 0x00a90000 0 0x4000>; 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1600 clock-names = "se"; 1601 pinctrl-names = "default"; 1602 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1603 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1604 power-domains = <&rpmhpd SC7280_CX>; 1605 operating-points-v2 = <&qup_opp_table>; 1606 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1607 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1608 interconnect-names = "qup-core", "qup-config"; 1609 status = "disabled"; 1610 }; 1611 1612 i2c13: i2c@a94000 { 1613 compatible = "qcom,geni-i2c"; 1614 reg = <0 0x00a94000 0 0x4000>; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1616 clock-names = "se"; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_i2c13_data_clk>; 1619 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1624 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1625 interconnect-names = "qup-core", "qup-config", 1626 "qup-memory"; 1627 status = "disabled"; 1628 }; 1629 1630 spi13: spi@a94000 { 1631 compatible = "qcom,geni-spi"; 1632 reg = <0 0x00a94000 0 0x4000>; 1633 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1634 clock-names = "se"; 1635 pinctrl-names = "default"; 1636 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1637 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 power-domains = <&rpmhpd SC7280_CX>; 1641 operating-points-v2 = <&qup_opp_table>; 1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1643 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1644 interconnect-names = "qup-core", "qup-config"; 1645 status = "disabled"; 1646 }; 1647 1648 uart13: serial@a94000 { 1649 compatible = "qcom,geni-uart"; 1650 reg = <0 0x00a94000 0 0x4000>; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1652 clock-names = "se"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1655 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1656 power-domains = <&rpmhpd SC7280_CX>; 1657 operating-points-v2 = <&qup_opp_table>; 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1659 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1660 interconnect-names = "qup-core", "qup-config"; 1661 status = "disabled"; 1662 }; 1663 1664 i2c14: i2c@a98000 { 1665 compatible = "qcom,geni-i2c"; 1666 reg = <0 0x00a98000 0 0x4000>; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1668 clock-names = "se"; 1669 pinctrl-names = "default"; 1670 pinctrl-0 = <&qup_i2c14_data_clk>; 1671 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1675 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1676 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1677 interconnect-names = "qup-core", "qup-config", 1678 "qup-memory"; 1679 status = "disabled"; 1680 }; 1681 1682 spi14: spi@a98000 { 1683 compatible = "qcom,geni-spi"; 1684 reg = <0 0x00a98000 0 0x4000>; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1686 clock-names = "se"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1689 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 power-domains = <&rpmhpd SC7280_CX>; 1693 operating-points-v2 = <&qup_opp_table>; 1694 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1695 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1696 interconnect-names = "qup-core", "qup-config"; 1697 status = "disabled"; 1698 }; 1699 1700 uart14: serial@a98000 { 1701 compatible = "qcom,geni-uart"; 1702 reg = <0 0x00a98000 0 0x4000>; 1703 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1704 clock-names = "se"; 1705 pinctrl-names = "default"; 1706 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1707 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1708 power-domains = <&rpmhpd SC7280_CX>; 1709 operating-points-v2 = <&qup_opp_table>; 1710 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1711 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1712 interconnect-names = "qup-core", "qup-config"; 1713 status = "disabled"; 1714 }; 1715 1716 i2c15: i2c@a9c000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00a9c000 0 0x4000>; 1719 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1720 clock-names = "se"; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_i2c15_data_clk>; 1723 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1727 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1728 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1729 interconnect-names = "qup-core", "qup-config", 1730 "qup-memory"; 1731 status = "disabled"; 1732 }; 1733 1734 spi15: spi@a9c000 { 1735 compatible = "qcom,geni-spi"; 1736 reg = <0 0x00a9c000 0 0x4000>; 1737 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1738 clock-names = "se"; 1739 pinctrl-names = "default"; 1740 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1741 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 power-domains = <&rpmhpd SC7280_CX>; 1745 operating-points-v2 = <&qup_opp_table>; 1746 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1747 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1748 interconnect-names = "qup-core", "qup-config"; 1749 status = "disabled"; 1750 }; 1751 1752 uart15: serial@a9c000 { 1753 compatible = "qcom,geni-uart"; 1754 reg = <0 0x00a9c000 0 0x4000>; 1755 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1756 clock-names = "se"; 1757 pinctrl-names = "default"; 1758 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1759 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1760 power-domains = <&rpmhpd SC7280_CX>; 1761 operating-points-v2 = <&qup_opp_table>; 1762 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1763 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1764 interconnect-names = "qup-core", "qup-config"; 1765 status = "disabled"; 1766 }; 1767 }; 1768 1769 cnoc2: interconnect@1500000 { 1770 reg = <0 0x01500000 0 0x1000>; 1771 compatible = "qcom,sc7280-cnoc2"; 1772 #interconnect-cells = <2>; 1773 qcom,bcm-voters = <&apps_bcm_voter>; 1774 }; 1775 1776 cnoc3: interconnect@1502000 { 1777 reg = <0 0x01502000 0 0x1000>; 1778 compatible = "qcom,sc7280-cnoc3"; 1779 #interconnect-cells = <2>; 1780 qcom,bcm-voters = <&apps_bcm_voter>; 1781 }; 1782 1783 mc_virt: interconnect@1580000 { 1784 reg = <0 0x01580000 0 0x4>; 1785 compatible = "qcom,sc7280-mc-virt"; 1786 #interconnect-cells = <2>; 1787 qcom,bcm-voters = <&apps_bcm_voter>; 1788 }; 1789 1790 system_noc: interconnect@1680000 { 1791 reg = <0 0x01680000 0 0x15480>; 1792 compatible = "qcom,sc7280-system-noc"; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 aggre1_noc: interconnect@16e0000 { 1798 compatible = "qcom,sc7280-aggre1-noc"; 1799 reg = <0 0x016e0000 0 0x1c080>; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 aggre2_noc: interconnect@1700000 { 1805 reg = <0 0x01700000 0 0x2b080>; 1806 compatible = "qcom,sc7280-aggre2-noc"; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 mmss_noc: interconnect@1740000 { 1812 reg = <0 0x01740000 0 0x1e080>; 1813 compatible = "qcom,sc7280-mmss-noc"; 1814 #interconnect-cells = <2>; 1815 qcom,bcm-voters = <&apps_bcm_voter>; 1816 }; 1817 1818 wifi: wifi@17a10040 { 1819 compatible = "qcom,wcn6750-wifi"; 1820 reg = <0 0x17a10040 0 0x0>; 1821 iommus = <&apps_smmu 0x1c00 0x1>; 1822 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1823 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1824 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1825 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1826 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1827 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1828 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1829 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1830 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1831 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1832 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1833 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1834 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1835 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1836 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1837 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1838 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1839 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1840 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1841 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1842 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1843 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1844 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1845 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1846 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1847 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1848 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1849 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1850 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1851 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 1852 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 1853 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 1854 qcom,rproc = <&remoteproc_wpss>; 1855 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 1856 status = "disabled"; 1857 }; 1858 1859 pcie1: pci@1c08000 { 1860 compatible = "qcom,pcie-sc7280"; 1861 reg = <0 0x01c08000 0 0x3000>, 1862 <0 0x40000000 0 0xf1d>, 1863 <0 0x40000f20 0 0xa8>, 1864 <0 0x40001000 0 0x1000>, 1865 <0 0x40100000 0 0x100000>; 1866 1867 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1868 device_type = "pci"; 1869 linux,pci-domain = <1>; 1870 bus-range = <0x00 0xff>; 1871 num-lanes = <2>; 1872 1873 #address-cells = <3>; 1874 #size-cells = <2>; 1875 1876 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1877 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1878 1879 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1880 interrupt-names = "msi"; 1881 #interrupt-cells = <1>; 1882 interrupt-map-mask = <0 0 0 0x7>; 1883 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1884 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1885 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1886 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1887 1888 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1889 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1890 <&pcie1_lane 0>, 1891 <&rpmhcc RPMH_CXO_CLK>, 1892 <&gcc GCC_PCIE_1_AUX_CLK>, 1893 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1894 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1895 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1896 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1897 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1898 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1899 1900 clock-names = "pipe", 1901 "pipe_mux", 1902 "phy_pipe", 1903 "ref", 1904 "aux", 1905 "cfg", 1906 "bus_master", 1907 "bus_slave", 1908 "slave_q2a", 1909 "tbu", 1910 "ddrss_sf_tbu"; 1911 1912 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1913 assigned-clock-rates = <19200000>; 1914 1915 resets = <&gcc GCC_PCIE_1_BCR>; 1916 reset-names = "pci"; 1917 1918 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1919 1920 phys = <&pcie1_lane>; 1921 phy-names = "pciephy"; 1922 1923 pinctrl-names = "default"; 1924 pinctrl-0 = <&pcie1_clkreq_n>; 1925 1926 iommus = <&apps_smmu 0x1c80 0x1>; 1927 1928 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1929 <0x100 &apps_smmu 0x1c81 0x1>; 1930 1931 status = "disabled"; 1932 }; 1933 1934 pcie1_phy: phy@1c0e000 { 1935 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1936 reg = <0 0x01c0e000 0 0x1c0>; 1937 #address-cells = <2>; 1938 #size-cells = <2>; 1939 ranges; 1940 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1941 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1942 <&gcc GCC_PCIE_CLKREF_EN>, 1943 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1944 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1945 1946 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1947 reset-names = "phy"; 1948 1949 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1950 assigned-clock-rates = <100000000>; 1951 1952 status = "disabled"; 1953 1954 pcie1_lane: phy@1c0e200 { 1955 reg = <0 0x01c0e200 0 0x170>, 1956 <0 0x01c0e400 0 0x200>, 1957 <0 0x01c0ea00 0 0x1f0>, 1958 <0 0x01c0e600 0 0x170>, 1959 <0 0x01c0e800 0 0x200>, 1960 <0 0x01c0ee00 0 0xf4>; 1961 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1962 clock-names = "pipe0"; 1963 1964 #phy-cells = <0>; 1965 #clock-cells = <1>; 1966 clock-output-names = "pcie_1_pipe_clk"; 1967 }; 1968 }; 1969 1970 ipa: ipa@1e40000 { 1971 compatible = "qcom,sc7280-ipa"; 1972 1973 iommus = <&apps_smmu 0x480 0x0>, 1974 <&apps_smmu 0x482 0x0>; 1975 reg = <0 0x1e40000 0 0x8000>, 1976 <0 0x1e50000 0 0x4ad0>, 1977 <0 0x1e04000 0 0x23000>; 1978 reg-names = "ipa-reg", 1979 "ipa-shared", 1980 "gsi"; 1981 1982 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1983 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1984 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1985 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1986 interrupt-names = "ipa", 1987 "gsi", 1988 "ipa-clock-query", 1989 "ipa-setup-ready"; 1990 1991 clocks = <&rpmhcc RPMH_IPA_CLK>; 1992 clock-names = "core"; 1993 1994 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1995 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1996 interconnect-names = "memory", 1997 "config"; 1998 1999 qcom,qmp = <&aoss_qmp>; 2000 2001 qcom,smem-states = <&ipa_smp2p_out 0>, 2002 <&ipa_smp2p_out 1>; 2003 qcom,smem-state-names = "ipa-clock-enabled-valid", 2004 "ipa-clock-enabled"; 2005 2006 status = "disabled"; 2007 }; 2008 2009 tcsr_mutex: hwlock@1f40000 { 2010 compatible = "qcom,tcsr-mutex", "syscon"; 2011 reg = <0 0x01f40000 0 0x40000>; 2012 #hwlock-cells = <1>; 2013 }; 2014 2015 tcsr: syscon@1fc0000 { 2016 compatible = "qcom,sc7280-tcsr", "syscon"; 2017 reg = <0 0x01fc0000 0 0x30000>; 2018 }; 2019 2020 lpasscc: lpasscc@3000000 { 2021 compatible = "qcom,sc7280-lpasscc"; 2022 reg = <0 0x03000000 0 0x40>, 2023 <0 0x03c04000 0 0x4>, 2024 <0 0x03389000 0 0x24>; 2025 reg-names = "qdsp6ss", "top_cc", "cc"; 2026 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2027 clock-names = "iface"; 2028 #clock-cells = <1>; 2029 }; 2030 2031 lpass_ag_noc: interconnect@3c40000 { 2032 reg = <0 0x03c40000 0 0xf080>; 2033 compatible = "qcom,sc7280-lpass-ag-noc"; 2034 #interconnect-cells = <2>; 2035 qcom,bcm-voters = <&apps_bcm_voter>; 2036 }; 2037 2038 gpu: gpu@3d00000 { 2039 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2040 reg = <0 0x03d00000 0 0x40000>, 2041 <0 0x03d9e000 0 0x1000>, 2042 <0 0x03d61000 0 0x800>; 2043 reg-names = "kgsl_3d0_reg_memory", 2044 "cx_mem", 2045 "cx_dbgc"; 2046 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2047 iommus = <&adreno_smmu 0 0x401>; 2048 operating-points-v2 = <&gpu_opp_table>; 2049 qcom,gmu = <&gmu>; 2050 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2051 interconnect-names = "gfx-mem"; 2052 #cooling-cells = <2>; 2053 2054 gpu_opp_table: opp-table { 2055 compatible = "operating-points-v2"; 2056 2057 opp-315000000 { 2058 opp-hz = /bits/ 64 <315000000>; 2059 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2060 opp-peak-kBps = <1804000>; 2061 }; 2062 2063 opp-450000000 { 2064 opp-hz = /bits/ 64 <450000000>; 2065 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2066 opp-peak-kBps = <4068000>; 2067 }; 2068 2069 opp-550000000 { 2070 opp-hz = /bits/ 64 <550000000>; 2071 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2072 opp-peak-kBps = <6832000>; 2073 }; 2074 }; 2075 }; 2076 2077 gmu: gmu@3d6a000 { 2078 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2079 reg = <0 0x03d6a000 0 0x34000>, 2080 <0 0x3de0000 0 0x10000>, 2081 <0 0x0b290000 0 0x10000>; 2082 reg-names = "gmu", "rscc", "gmu_pdc"; 2083 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2085 interrupt-names = "hfi", "gmu"; 2086 clocks = <&gpucc 5>, 2087 <&gpucc 8>, 2088 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2089 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2090 <&gpucc 2>, 2091 <&gpucc 15>, 2092 <&gpucc 11>; 2093 clock-names = "gmu", 2094 "cxo", 2095 "axi", 2096 "memnoc", 2097 "ahb", 2098 "hub", 2099 "smmu_vote"; 2100 power-domains = <&gpucc 0>, 2101 <&gpucc 1>; 2102 power-domain-names = "cx", 2103 "gx"; 2104 iommus = <&adreno_smmu 5 0x400>; 2105 operating-points-v2 = <&gmu_opp_table>; 2106 2107 gmu_opp_table: opp-table { 2108 compatible = "operating-points-v2"; 2109 2110 opp-200000000 { 2111 opp-hz = /bits/ 64 <200000000>; 2112 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2113 }; 2114 }; 2115 }; 2116 2117 gpucc: clock-controller@3d90000 { 2118 compatible = "qcom,sc7280-gpucc"; 2119 reg = <0 0x03d90000 0 0x9000>; 2120 clocks = <&rpmhcc RPMH_CXO_CLK>, 2121 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2122 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2123 clock-names = "bi_tcxo", 2124 "gcc_gpu_gpll0_clk_src", 2125 "gcc_gpu_gpll0_div_clk_src"; 2126 #clock-cells = <1>; 2127 #reset-cells = <1>; 2128 #power-domain-cells = <1>; 2129 }; 2130 2131 adreno_smmu: iommu@3da0000 { 2132 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2133 reg = <0 0x03da0000 0 0x20000>; 2134 #iommu-cells = <2>; 2135 #global-interrupts = <2>; 2136 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2148 2149 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2150 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2151 <&gpucc 2>, 2152 <&gpucc 11>, 2153 <&gpucc 5>, 2154 <&gpucc 15>, 2155 <&gpucc 13>; 2156 clock-names = "gcc_gpu_memnoc_gfx_clk", 2157 "gcc_gpu_snoc_dvm_gfx_clk", 2158 "gpu_cc_ahb_clk", 2159 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2160 "gpu_cc_cx_gmu_clk", 2161 "gpu_cc_hub_cx_int_clk", 2162 "gpu_cc_hub_aon_clk"; 2163 2164 power-domains = <&gpucc 0>; 2165 }; 2166 2167 remoteproc_mpss: remoteproc@4080000 { 2168 compatible = "qcom,sc7280-mpss-pas"; 2169 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2170 reg-names = "qdsp6", "rmb"; 2171 2172 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2173 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2174 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2175 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2176 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2177 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2178 interrupt-names = "wdog", "fatal", "ready", "handover", 2179 "stop-ack", "shutdown-ack"; 2180 2181 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2182 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2183 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2184 <&rpmhcc RPMH_PKA_CLK>, 2185 <&rpmhcc RPMH_CXO_CLK>; 2186 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2187 2188 power-domains = <&rpmhpd SC7280_CX>, 2189 <&rpmhpd SC7280_MSS>; 2190 power-domain-names = "cx", "mss"; 2191 2192 memory-region = <&mpss_mem>; 2193 2194 qcom,qmp = <&aoss_qmp>; 2195 2196 qcom,smem-states = <&modem_smp2p_out 0>; 2197 qcom,smem-state-names = "stop"; 2198 2199 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2200 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2201 reset-names = "mss_restart", "pdc_reset"; 2202 2203 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 2204 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 2205 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 2206 2207 status = "disabled"; 2208 2209 glink-edge { 2210 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2211 IPCC_MPROC_SIGNAL_GLINK_QMP 2212 IRQ_TYPE_EDGE_RISING>; 2213 mboxes = <&ipcc IPCC_CLIENT_MPSS 2214 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2215 label = "modem"; 2216 qcom,remote-pid = <1>; 2217 }; 2218 }; 2219 2220 stm@6002000 { 2221 compatible = "arm,coresight-stm", "arm,primecell"; 2222 reg = <0 0x06002000 0 0x1000>, 2223 <0 0x16280000 0 0x180000>; 2224 reg-names = "stm-base", "stm-stimulus-base"; 2225 2226 clocks = <&aoss_qmp>; 2227 clock-names = "apb_pclk"; 2228 2229 out-ports { 2230 port { 2231 stm_out: endpoint { 2232 remote-endpoint = <&funnel0_in7>; 2233 }; 2234 }; 2235 }; 2236 }; 2237 2238 funnel@6041000 { 2239 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2240 reg = <0 0x06041000 0 0x1000>; 2241 2242 clocks = <&aoss_qmp>; 2243 clock-names = "apb_pclk"; 2244 2245 out-ports { 2246 port { 2247 funnel0_out: endpoint { 2248 remote-endpoint = <&merge_funnel_in0>; 2249 }; 2250 }; 2251 }; 2252 2253 in-ports { 2254 #address-cells = <1>; 2255 #size-cells = <0>; 2256 2257 port@7 { 2258 reg = <7>; 2259 funnel0_in7: endpoint { 2260 remote-endpoint = <&stm_out>; 2261 }; 2262 }; 2263 }; 2264 }; 2265 2266 funnel@6042000 { 2267 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2268 reg = <0 0x06042000 0 0x1000>; 2269 2270 clocks = <&aoss_qmp>; 2271 clock-names = "apb_pclk"; 2272 2273 out-ports { 2274 port { 2275 funnel1_out: endpoint { 2276 remote-endpoint = <&merge_funnel_in1>; 2277 }; 2278 }; 2279 }; 2280 2281 in-ports { 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 2285 port@4 { 2286 reg = <4>; 2287 funnel1_in4: endpoint { 2288 remote-endpoint = <&apss_merge_funnel_out>; 2289 }; 2290 }; 2291 }; 2292 }; 2293 2294 funnel@6045000 { 2295 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2296 reg = <0 0x06045000 0 0x1000>; 2297 2298 clocks = <&aoss_qmp>; 2299 clock-names = "apb_pclk"; 2300 2301 out-ports { 2302 port { 2303 merge_funnel_out: endpoint { 2304 remote-endpoint = <&swao_funnel_in>; 2305 }; 2306 }; 2307 }; 2308 2309 in-ports { 2310 #address-cells = <1>; 2311 #size-cells = <0>; 2312 2313 port@0 { 2314 reg = <0>; 2315 merge_funnel_in0: endpoint { 2316 remote-endpoint = <&funnel0_out>; 2317 }; 2318 }; 2319 2320 port@1 { 2321 reg = <1>; 2322 merge_funnel_in1: endpoint { 2323 remote-endpoint = <&funnel1_out>; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 replicator@6046000 { 2330 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2331 reg = <0 0x06046000 0 0x1000>; 2332 2333 clocks = <&aoss_qmp>; 2334 clock-names = "apb_pclk"; 2335 2336 out-ports { 2337 port { 2338 replicator_out: endpoint { 2339 remote-endpoint = <&etr_in>; 2340 }; 2341 }; 2342 }; 2343 2344 in-ports { 2345 port { 2346 replicator_in: endpoint { 2347 remote-endpoint = <&swao_replicator_out>; 2348 }; 2349 }; 2350 }; 2351 }; 2352 2353 etr@6048000 { 2354 compatible = "arm,coresight-tmc", "arm,primecell"; 2355 reg = <0 0x06048000 0 0x1000>; 2356 iommus = <&apps_smmu 0x04c0 0>; 2357 2358 clocks = <&aoss_qmp>; 2359 clock-names = "apb_pclk"; 2360 arm,scatter-gather; 2361 2362 in-ports { 2363 port { 2364 etr_in: endpoint { 2365 remote-endpoint = <&replicator_out>; 2366 }; 2367 }; 2368 }; 2369 }; 2370 2371 funnel@6b04000 { 2372 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2373 reg = <0 0x06b04000 0 0x1000>; 2374 2375 clocks = <&aoss_qmp>; 2376 clock-names = "apb_pclk"; 2377 2378 out-ports { 2379 port { 2380 swao_funnel_out: endpoint { 2381 remote-endpoint = <&etf_in>; 2382 }; 2383 }; 2384 }; 2385 2386 in-ports { 2387 #address-cells = <1>; 2388 #size-cells = <0>; 2389 2390 port@7 { 2391 reg = <7>; 2392 swao_funnel_in: endpoint { 2393 remote-endpoint = <&merge_funnel_out>; 2394 }; 2395 }; 2396 }; 2397 }; 2398 2399 etf@6b05000 { 2400 compatible = "arm,coresight-tmc", "arm,primecell"; 2401 reg = <0 0x06b05000 0 0x1000>; 2402 2403 clocks = <&aoss_qmp>; 2404 clock-names = "apb_pclk"; 2405 2406 out-ports { 2407 port { 2408 etf_out: endpoint { 2409 remote-endpoint = <&swao_replicator_in>; 2410 }; 2411 }; 2412 }; 2413 2414 in-ports { 2415 port { 2416 etf_in: endpoint { 2417 remote-endpoint = <&swao_funnel_out>; 2418 }; 2419 }; 2420 }; 2421 }; 2422 2423 replicator@6b06000 { 2424 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2425 reg = <0 0x06b06000 0 0x1000>; 2426 2427 clocks = <&aoss_qmp>; 2428 clock-names = "apb_pclk"; 2429 qcom,replicator-loses-context; 2430 2431 out-ports { 2432 port { 2433 swao_replicator_out: endpoint { 2434 remote-endpoint = <&replicator_in>; 2435 }; 2436 }; 2437 }; 2438 2439 in-ports { 2440 port { 2441 swao_replicator_in: endpoint { 2442 remote-endpoint = <&etf_out>; 2443 }; 2444 }; 2445 }; 2446 }; 2447 2448 etm@7040000 { 2449 compatible = "arm,coresight-etm4x", "arm,primecell"; 2450 reg = <0 0x07040000 0 0x1000>; 2451 2452 cpu = <&CPU0>; 2453 2454 clocks = <&aoss_qmp>; 2455 clock-names = "apb_pclk"; 2456 arm,coresight-loses-context-with-cpu; 2457 qcom,skip-power-up; 2458 2459 out-ports { 2460 port { 2461 etm0_out: endpoint { 2462 remote-endpoint = <&apss_funnel_in0>; 2463 }; 2464 }; 2465 }; 2466 }; 2467 2468 etm@7140000 { 2469 compatible = "arm,coresight-etm4x", "arm,primecell"; 2470 reg = <0 0x07140000 0 0x1000>; 2471 2472 cpu = <&CPU1>; 2473 2474 clocks = <&aoss_qmp>; 2475 clock-names = "apb_pclk"; 2476 arm,coresight-loses-context-with-cpu; 2477 qcom,skip-power-up; 2478 2479 out-ports { 2480 port { 2481 etm1_out: endpoint { 2482 remote-endpoint = <&apss_funnel_in1>; 2483 }; 2484 }; 2485 }; 2486 }; 2487 2488 etm@7240000 { 2489 compatible = "arm,coresight-etm4x", "arm,primecell"; 2490 reg = <0 0x07240000 0 0x1000>; 2491 2492 cpu = <&CPU2>; 2493 2494 clocks = <&aoss_qmp>; 2495 clock-names = "apb_pclk"; 2496 arm,coresight-loses-context-with-cpu; 2497 qcom,skip-power-up; 2498 2499 out-ports { 2500 port { 2501 etm2_out: endpoint { 2502 remote-endpoint = <&apss_funnel_in2>; 2503 }; 2504 }; 2505 }; 2506 }; 2507 2508 etm@7340000 { 2509 compatible = "arm,coresight-etm4x", "arm,primecell"; 2510 reg = <0 0x07340000 0 0x1000>; 2511 2512 cpu = <&CPU3>; 2513 2514 clocks = <&aoss_qmp>; 2515 clock-names = "apb_pclk"; 2516 arm,coresight-loses-context-with-cpu; 2517 qcom,skip-power-up; 2518 2519 out-ports { 2520 port { 2521 etm3_out: endpoint { 2522 remote-endpoint = <&apss_funnel_in3>; 2523 }; 2524 }; 2525 }; 2526 }; 2527 2528 etm@7440000 { 2529 compatible = "arm,coresight-etm4x", "arm,primecell"; 2530 reg = <0 0x07440000 0 0x1000>; 2531 2532 cpu = <&CPU4>; 2533 2534 clocks = <&aoss_qmp>; 2535 clock-names = "apb_pclk"; 2536 arm,coresight-loses-context-with-cpu; 2537 qcom,skip-power-up; 2538 2539 out-ports { 2540 port { 2541 etm4_out: endpoint { 2542 remote-endpoint = <&apss_funnel_in4>; 2543 }; 2544 }; 2545 }; 2546 }; 2547 2548 etm@7540000 { 2549 compatible = "arm,coresight-etm4x", "arm,primecell"; 2550 reg = <0 0x07540000 0 0x1000>; 2551 2552 cpu = <&CPU5>; 2553 2554 clocks = <&aoss_qmp>; 2555 clock-names = "apb_pclk"; 2556 arm,coresight-loses-context-with-cpu; 2557 qcom,skip-power-up; 2558 2559 out-ports { 2560 port { 2561 etm5_out: endpoint { 2562 remote-endpoint = <&apss_funnel_in5>; 2563 }; 2564 }; 2565 }; 2566 }; 2567 2568 etm@7640000 { 2569 compatible = "arm,coresight-etm4x", "arm,primecell"; 2570 reg = <0 0x07640000 0 0x1000>; 2571 2572 cpu = <&CPU6>; 2573 2574 clocks = <&aoss_qmp>; 2575 clock-names = "apb_pclk"; 2576 arm,coresight-loses-context-with-cpu; 2577 qcom,skip-power-up; 2578 2579 out-ports { 2580 port { 2581 etm6_out: endpoint { 2582 remote-endpoint = <&apss_funnel_in6>; 2583 }; 2584 }; 2585 }; 2586 }; 2587 2588 etm@7740000 { 2589 compatible = "arm,coresight-etm4x", "arm,primecell"; 2590 reg = <0 0x07740000 0 0x1000>; 2591 2592 cpu = <&CPU7>; 2593 2594 clocks = <&aoss_qmp>; 2595 clock-names = "apb_pclk"; 2596 arm,coresight-loses-context-with-cpu; 2597 qcom,skip-power-up; 2598 2599 out-ports { 2600 port { 2601 etm7_out: endpoint { 2602 remote-endpoint = <&apss_funnel_in7>; 2603 }; 2604 }; 2605 }; 2606 }; 2607 2608 funnel@7800000 { /* APSS Funnel */ 2609 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2610 reg = <0 0x07800000 0 0x1000>; 2611 2612 clocks = <&aoss_qmp>; 2613 clock-names = "apb_pclk"; 2614 2615 out-ports { 2616 port { 2617 apss_funnel_out: endpoint { 2618 remote-endpoint = <&apss_merge_funnel_in>; 2619 }; 2620 }; 2621 }; 2622 2623 in-ports { 2624 #address-cells = <1>; 2625 #size-cells = <0>; 2626 2627 port@0 { 2628 reg = <0>; 2629 apss_funnel_in0: endpoint { 2630 remote-endpoint = <&etm0_out>; 2631 }; 2632 }; 2633 2634 port@1 { 2635 reg = <1>; 2636 apss_funnel_in1: endpoint { 2637 remote-endpoint = <&etm1_out>; 2638 }; 2639 }; 2640 2641 port@2 { 2642 reg = <2>; 2643 apss_funnel_in2: endpoint { 2644 remote-endpoint = <&etm2_out>; 2645 }; 2646 }; 2647 2648 port@3 { 2649 reg = <3>; 2650 apss_funnel_in3: endpoint { 2651 remote-endpoint = <&etm3_out>; 2652 }; 2653 }; 2654 2655 port@4 { 2656 reg = <4>; 2657 apss_funnel_in4: endpoint { 2658 remote-endpoint = <&etm4_out>; 2659 }; 2660 }; 2661 2662 port@5 { 2663 reg = <5>; 2664 apss_funnel_in5: endpoint { 2665 remote-endpoint = <&etm5_out>; 2666 }; 2667 }; 2668 2669 port@6 { 2670 reg = <6>; 2671 apss_funnel_in6: endpoint { 2672 remote-endpoint = <&etm6_out>; 2673 }; 2674 }; 2675 2676 port@7 { 2677 reg = <7>; 2678 apss_funnel_in7: endpoint { 2679 remote-endpoint = <&etm7_out>; 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 funnel@7810000 { 2686 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2687 reg = <0 0x07810000 0 0x1000>; 2688 2689 clocks = <&aoss_qmp>; 2690 clock-names = "apb_pclk"; 2691 2692 out-ports { 2693 port { 2694 apss_merge_funnel_out: endpoint { 2695 remote-endpoint = <&funnel1_in4>; 2696 }; 2697 }; 2698 }; 2699 2700 in-ports { 2701 port { 2702 apss_merge_funnel_in: endpoint { 2703 remote-endpoint = <&apss_funnel_out>; 2704 }; 2705 }; 2706 }; 2707 }; 2708 2709 sdhc_2: sdhci@8804000 { 2710 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2711 pinctrl-names = "default", "sleep"; 2712 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 2713 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 2714 status = "disabled"; 2715 2716 reg = <0 0x08804000 0 0x1000>; 2717 2718 iommus = <&apps_smmu 0x100 0x0>; 2719 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2721 interrupt-names = "hc_irq", "pwr_irq"; 2722 2723 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2724 <&gcc GCC_SDCC2_AHB_CLK>, 2725 <&rpmhcc RPMH_CXO_CLK>; 2726 clock-names = "core", "iface", "xo"; 2727 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2728 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2729 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2730 power-domains = <&rpmhpd SC7280_CX>; 2731 operating-points-v2 = <&sdhc2_opp_table>; 2732 2733 bus-width = <4>; 2734 2735 qcom,dll-config = <0x0007642c>; 2736 2737 resets = <&gcc GCC_SDCC2_BCR>; 2738 2739 sdhc2_opp_table: opp-table { 2740 compatible = "operating-points-v2"; 2741 2742 opp-100000000 { 2743 opp-hz = /bits/ 64 <100000000>; 2744 required-opps = <&rpmhpd_opp_low_svs>; 2745 opp-peak-kBps = <1800000 400000>; 2746 opp-avg-kBps = <100000 0>; 2747 }; 2748 2749 opp-202000000 { 2750 opp-hz = /bits/ 64 <202000000>; 2751 required-opps = <&rpmhpd_opp_nom>; 2752 opp-peak-kBps = <5400000 1600000>; 2753 opp-avg-kBps = <200000 0>; 2754 }; 2755 }; 2756 2757 }; 2758 2759 usb_1_hsphy: phy@88e3000 { 2760 compatible = "qcom,sc7280-usb-hs-phy", 2761 "qcom,usb-snps-hs-7nm-phy"; 2762 reg = <0 0x088e3000 0 0x400>; 2763 status = "disabled"; 2764 #phy-cells = <0>; 2765 2766 clocks = <&rpmhcc RPMH_CXO_CLK>; 2767 clock-names = "ref"; 2768 2769 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2770 }; 2771 2772 usb_2_hsphy: phy@88e4000 { 2773 compatible = "qcom,sc7280-usb-hs-phy", 2774 "qcom,usb-snps-hs-7nm-phy"; 2775 reg = <0 0x088e4000 0 0x400>; 2776 status = "disabled"; 2777 #phy-cells = <0>; 2778 2779 clocks = <&rpmhcc RPMH_CXO_CLK>; 2780 clock-names = "ref"; 2781 2782 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2783 }; 2784 2785 usb_1_qmpphy: phy-wrapper@88e9000 { 2786 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2787 "qcom,sm8250-qmp-usb3-dp-phy"; 2788 reg = <0 0x088e9000 0 0x200>, 2789 <0 0x088e8000 0 0x40>, 2790 <0 0x088ea000 0 0x200>; 2791 status = "disabled"; 2792 #address-cells = <2>; 2793 #size-cells = <2>; 2794 ranges; 2795 2796 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2797 <&rpmhcc RPMH_CXO_CLK>, 2798 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2799 clock-names = "aux", "ref_clk_src", "com_aux"; 2800 2801 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2802 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2803 reset-names = "phy", "common"; 2804 2805 usb_1_ssphy: usb3-phy@88e9200 { 2806 reg = <0 0x088e9200 0 0x200>, 2807 <0 0x088e9400 0 0x200>, 2808 <0 0x088e9c00 0 0x400>, 2809 <0 0x088e9600 0 0x200>, 2810 <0 0x088e9800 0 0x200>, 2811 <0 0x088e9a00 0 0x100>; 2812 #clock-cells = <0>; 2813 #phy-cells = <0>; 2814 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2815 clock-names = "pipe0"; 2816 clock-output-names = "usb3_phy_pipe_clk_src"; 2817 }; 2818 2819 dp_phy: dp-phy@88ea200 { 2820 reg = <0 0x088ea200 0 0x200>, 2821 <0 0x088ea400 0 0x200>, 2822 <0 0x088eaa00 0 0x200>, 2823 <0 0x088ea600 0 0x200>, 2824 <0 0x088ea800 0 0x200>; 2825 #phy-cells = <0>; 2826 #clock-cells = <1>; 2827 }; 2828 }; 2829 2830 usb_2: usb@8cf8800 { 2831 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2832 reg = <0 0x08cf8800 0 0x400>; 2833 status = "disabled"; 2834 #address-cells = <2>; 2835 #size-cells = <2>; 2836 ranges; 2837 dma-ranges; 2838 2839 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2840 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2841 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2842 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2843 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2844 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2845 "sleep"; 2846 2847 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2848 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2849 assigned-clock-rates = <19200000>, <200000000>; 2850 2851 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2852 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2853 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2854 interrupt-names = "hs_phy_irq", 2855 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2856 2857 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2858 2859 resets = <&gcc GCC_USB30_SEC_BCR>; 2860 2861 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2862 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2863 interconnect-names = "usb-ddr", "apps-usb"; 2864 2865 usb_2_dwc3: usb@8c00000 { 2866 compatible = "snps,dwc3"; 2867 reg = <0 0x08c00000 0 0xe000>; 2868 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2869 iommus = <&apps_smmu 0xa0 0x0>; 2870 snps,dis_u2_susphy_quirk; 2871 snps,dis_enblslpm_quirk; 2872 phys = <&usb_2_hsphy>; 2873 phy-names = "usb2-phy"; 2874 maximum-speed = "high-speed"; 2875 }; 2876 }; 2877 2878 qspi: spi@88dc000 { 2879 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2880 reg = <0 0x088dc000 0 0x1000>; 2881 #address-cells = <1>; 2882 #size-cells = <0>; 2883 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2884 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2885 <&gcc GCC_QSPI_CORE_CLK>; 2886 clock-names = "iface", "core"; 2887 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2888 &cnoc2 SLAVE_QSPI_0 0>; 2889 interconnect-names = "qspi-config"; 2890 power-domains = <&rpmhpd SC7280_CX>; 2891 operating-points-v2 = <&qspi_opp_table>; 2892 status = "disabled"; 2893 }; 2894 2895 remoteproc_wpss: remoteproc@8a00000 { 2896 compatible = "qcom,sc7280-wpss-pil"; 2897 reg = <0 0x08a00000 0 0x10000>; 2898 2899 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 2900 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2901 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2902 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2903 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2904 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2905 interrupt-names = "wdog", "fatal", "ready", "handover", 2906 "stop-ack", "shutdown-ack"; 2907 2908 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 2909 <&gcc GCC_WPSS_AHB_CLK>, 2910 <&gcc GCC_WPSS_RSCP_CLK>, 2911 <&rpmhcc RPMH_CXO_CLK>; 2912 clock-names = "ahb_bdg", "ahb", 2913 "rscp", "xo"; 2914 2915 power-domains = <&rpmhpd SC7280_CX>, 2916 <&rpmhpd SC7280_MX>; 2917 power-domain-names = "cx", "mx"; 2918 2919 memory-region = <&wpss_mem>; 2920 2921 qcom,qmp = <&aoss_qmp>; 2922 2923 qcom,smem-states = <&wpss_smp2p_out 0>; 2924 qcom,smem-state-names = "stop"; 2925 2926 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 2927 <&pdc_reset PDC_WPSS_SYNC_RESET>; 2928 reset-names = "restart", "pdc_sync"; 2929 2930 qcom,halt-regs = <&tcsr_mutex 0x37000>; 2931 2932 status = "disabled"; 2933 2934 glink-edge { 2935 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 2936 IPCC_MPROC_SIGNAL_GLINK_QMP 2937 IRQ_TYPE_EDGE_RISING>; 2938 mboxes = <&ipcc IPCC_CLIENT_WPSS 2939 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2940 2941 label = "wpss"; 2942 qcom,remote-pid = <13>; 2943 }; 2944 }; 2945 2946 dc_noc: interconnect@90e0000 { 2947 reg = <0 0x090e0000 0 0x5080>; 2948 compatible = "qcom,sc7280-dc-noc"; 2949 #interconnect-cells = <2>; 2950 qcom,bcm-voters = <&apps_bcm_voter>; 2951 }; 2952 2953 gem_noc: interconnect@9100000 { 2954 reg = <0 0x9100000 0 0xe2200>; 2955 compatible = "qcom,sc7280-gem-noc"; 2956 #interconnect-cells = <2>; 2957 qcom,bcm-voters = <&apps_bcm_voter>; 2958 }; 2959 2960 system-cache-controller@9200000 { 2961 compatible = "qcom,sc7280-llcc"; 2962 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2963 reg-names = "llcc_base", "llcc_broadcast_base"; 2964 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2965 }; 2966 2967 nsp_noc: interconnect@a0c0000 { 2968 reg = <0 0x0a0c0000 0 0x10000>; 2969 compatible = "qcom,sc7280-nsp-noc"; 2970 #interconnect-cells = <2>; 2971 qcom,bcm-voters = <&apps_bcm_voter>; 2972 }; 2973 2974 usb_1: usb@a6f8800 { 2975 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2976 reg = <0 0x0a6f8800 0 0x400>; 2977 status = "disabled"; 2978 #address-cells = <2>; 2979 #size-cells = <2>; 2980 ranges; 2981 dma-ranges; 2982 2983 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2984 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2985 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2986 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2987 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2988 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2989 "sleep"; 2990 2991 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2992 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2993 assigned-clock-rates = <19200000>, <200000000>; 2994 2995 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2996 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2997 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2998 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2999 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3000 "dm_hs_phy_irq", "ss_phy_irq"; 3001 3002 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3003 3004 resets = <&gcc GCC_USB30_PRIM_BCR>; 3005 3006 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3007 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3008 interconnect-names = "usb-ddr", "apps-usb"; 3009 3010 usb_1_dwc3: usb@a600000 { 3011 compatible = "snps,dwc3"; 3012 reg = <0 0x0a600000 0 0xe000>; 3013 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3014 iommus = <&apps_smmu 0xe0 0x0>; 3015 snps,dis_u2_susphy_quirk; 3016 snps,dis_enblslpm_quirk; 3017 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3018 phy-names = "usb2-phy", "usb3-phy"; 3019 maximum-speed = "super-speed"; 3020 }; 3021 }; 3022 3023 venus: video-codec@aa00000 { 3024 compatible = "qcom,sc7280-venus"; 3025 reg = <0 0x0aa00000 0 0xd0600>; 3026 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3027 3028 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3029 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3030 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3031 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3032 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3033 clock-names = "core", "bus", "iface", 3034 "vcodec_core", "vcodec_bus"; 3035 3036 power-domains = <&videocc MVSC_GDSC>, 3037 <&videocc MVS0_GDSC>, 3038 <&rpmhpd SC7280_CX>; 3039 power-domain-names = "venus", "vcodec0", "cx"; 3040 operating-points-v2 = <&venus_opp_table>; 3041 3042 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3043 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3044 interconnect-names = "cpu-cfg", "video-mem"; 3045 3046 iommus = <&apps_smmu 0x2180 0x20>, 3047 <&apps_smmu 0x2184 0x20>; 3048 memory-region = <&video_mem>; 3049 3050 video-decoder { 3051 compatible = "venus-decoder"; 3052 }; 3053 3054 video-encoder { 3055 compatible = "venus-encoder"; 3056 }; 3057 3058 video-firmware { 3059 iommus = <&apps_smmu 0x21a2 0x0>; 3060 }; 3061 3062 venus_opp_table: venus-opp-table { 3063 compatible = "operating-points-v2"; 3064 3065 opp-133330000 { 3066 opp-hz = /bits/ 64 <133330000>; 3067 required-opps = <&rpmhpd_opp_low_svs>; 3068 }; 3069 3070 opp-240000000 { 3071 opp-hz = /bits/ 64 <240000000>; 3072 required-opps = <&rpmhpd_opp_svs>; 3073 }; 3074 3075 opp-335000000 { 3076 opp-hz = /bits/ 64 <335000000>; 3077 required-opps = <&rpmhpd_opp_svs_l1>; 3078 }; 3079 3080 opp-424000000 { 3081 opp-hz = /bits/ 64 <424000000>; 3082 required-opps = <&rpmhpd_opp_nom>; 3083 }; 3084 3085 opp-460000048 { 3086 opp-hz = /bits/ 64 <460000048>; 3087 required-opps = <&rpmhpd_opp_turbo>; 3088 }; 3089 }; 3090 3091 }; 3092 3093 videocc: clock-controller@aaf0000 { 3094 compatible = "qcom,sc7280-videocc"; 3095 reg = <0 0xaaf0000 0 0x10000>; 3096 clocks = <&rpmhcc RPMH_CXO_CLK>, 3097 <&rpmhcc RPMH_CXO_CLK_A>; 3098 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3099 #clock-cells = <1>; 3100 #reset-cells = <1>; 3101 #power-domain-cells = <1>; 3102 }; 3103 3104 camcc: clock-controller@ad00000 { 3105 compatible = "qcom,sc7280-camcc"; 3106 reg = <0 0x0ad00000 0 0x10000>; 3107 clocks = <&rpmhcc RPMH_CXO_CLK>, 3108 <&rpmhcc RPMH_CXO_CLK_A>, 3109 <&sleep_clk>; 3110 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3111 #clock-cells = <1>; 3112 #reset-cells = <1>; 3113 #power-domain-cells = <1>; 3114 }; 3115 3116 dispcc: clock-controller@af00000 { 3117 compatible = "qcom,sc7280-dispcc"; 3118 reg = <0 0xaf00000 0 0x20000>; 3119 clocks = <&rpmhcc RPMH_CXO_CLK>, 3120 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3121 <&mdss_dsi_phy 0>, 3122 <&mdss_dsi_phy 1>, 3123 <&dp_phy 0>, 3124 <&dp_phy 1>, 3125 <&mdss_edp_phy 0>, 3126 <&mdss_edp_phy 1>; 3127 clock-names = "bi_tcxo", 3128 "gcc_disp_gpll0_clk", 3129 "dsi0_phy_pll_out_byteclk", 3130 "dsi0_phy_pll_out_dsiclk", 3131 "dp_phy_pll_link_clk", 3132 "dp_phy_pll_vco_div_clk", 3133 "edp_phy_pll_link_clk", 3134 "edp_phy_pll_vco_div_clk"; 3135 #clock-cells = <1>; 3136 #reset-cells = <1>; 3137 #power-domain-cells = <1>; 3138 }; 3139 3140 mdss: display-subsystem@ae00000 { 3141 compatible = "qcom,sc7280-mdss"; 3142 reg = <0 0x0ae00000 0 0x1000>; 3143 reg-names = "mdss"; 3144 3145 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3146 3147 clocks = <&gcc GCC_DISP_AHB_CLK>, 3148 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3149 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3150 clock-names = "iface", 3151 "ahb", 3152 "core"; 3153 3154 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3155 assigned-clock-rates = <300000000>; 3156 3157 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3158 interrupt-controller; 3159 #interrupt-cells = <1>; 3160 3161 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3162 interconnect-names = "mdp0-mem"; 3163 3164 iommus = <&apps_smmu 0x900 0x402>; 3165 3166 #address-cells = <2>; 3167 #size-cells = <2>; 3168 ranges; 3169 3170 status = "disabled"; 3171 3172 mdss_mdp: display-controller@ae01000 { 3173 compatible = "qcom,sc7280-dpu"; 3174 reg = <0 0x0ae01000 0 0x8f030>, 3175 <0 0x0aeb0000 0 0x2008>; 3176 reg-names = "mdp", "vbif"; 3177 3178 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3179 <&gcc GCC_DISP_SF_AXI_CLK>, 3180 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3181 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3182 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3183 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3184 clock-names = "bus", 3185 "nrt_bus", 3186 "iface", 3187 "lut", 3188 "core", 3189 "vsync"; 3190 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3191 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3192 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3193 assigned-clock-rates = <300000000>, 3194 <19200000>, 3195 <19200000>; 3196 operating-points-v2 = <&mdp_opp_table>; 3197 power-domains = <&rpmhpd SC7280_CX>; 3198 3199 interrupt-parent = <&mdss>; 3200 interrupts = <0>; 3201 3202 status = "disabled"; 3203 3204 ports { 3205 #address-cells = <1>; 3206 #size-cells = <0>; 3207 3208 port@0 { 3209 reg = <0>; 3210 dpu_intf1_out: endpoint { 3211 remote-endpoint = <&dsi0_in>; 3212 }; 3213 }; 3214 3215 port@1 { 3216 reg = <1>; 3217 dpu_intf5_out: endpoint { 3218 remote-endpoint = <&edp_in>; 3219 }; 3220 }; 3221 3222 port@2 { 3223 reg = <2>; 3224 dpu_intf0_out: endpoint { 3225 remote-endpoint = <&dp_in>; 3226 }; 3227 }; 3228 }; 3229 3230 mdp_opp_table: opp-table { 3231 compatible = "operating-points-v2"; 3232 3233 opp-200000000 { 3234 opp-hz = /bits/ 64 <200000000>; 3235 required-opps = <&rpmhpd_opp_low_svs>; 3236 }; 3237 3238 opp-300000000 { 3239 opp-hz = /bits/ 64 <300000000>; 3240 required-opps = <&rpmhpd_opp_svs>; 3241 }; 3242 3243 opp-380000000 { 3244 opp-hz = /bits/ 64 <380000000>; 3245 required-opps = <&rpmhpd_opp_svs_l1>; 3246 }; 3247 3248 opp-506666667 { 3249 opp-hz = /bits/ 64 <506666667>; 3250 required-opps = <&rpmhpd_opp_nom>; 3251 }; 3252 }; 3253 }; 3254 3255 mdss_dsi: dsi@ae94000 { 3256 compatible = "qcom,mdss-dsi-ctrl"; 3257 reg = <0 0x0ae94000 0 0x400>; 3258 reg-names = "dsi_ctrl"; 3259 3260 interrupt-parent = <&mdss>; 3261 interrupts = <4>; 3262 3263 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3264 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3265 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3266 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3267 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3268 <&gcc GCC_DISP_HF_AXI_CLK>; 3269 clock-names = "byte", 3270 "byte_intf", 3271 "pixel", 3272 "core", 3273 "iface", 3274 "bus"; 3275 3276 operating-points-v2 = <&dsi_opp_table>; 3277 power-domains = <&rpmhpd SC7280_CX>; 3278 3279 phys = <&mdss_dsi_phy>; 3280 phy-names = "dsi"; 3281 3282 #address-cells = <1>; 3283 #size-cells = <0>; 3284 3285 status = "disabled"; 3286 3287 ports { 3288 #address-cells = <1>; 3289 #size-cells = <0>; 3290 3291 port@0 { 3292 reg = <0>; 3293 dsi0_in: endpoint { 3294 remote-endpoint = <&dpu_intf1_out>; 3295 }; 3296 }; 3297 3298 port@1 { 3299 reg = <1>; 3300 dsi0_out: endpoint { 3301 }; 3302 }; 3303 }; 3304 3305 dsi_opp_table: opp-table { 3306 compatible = "operating-points-v2"; 3307 3308 opp-187500000 { 3309 opp-hz = /bits/ 64 <187500000>; 3310 required-opps = <&rpmhpd_opp_low_svs>; 3311 }; 3312 3313 opp-300000000 { 3314 opp-hz = /bits/ 64 <300000000>; 3315 required-opps = <&rpmhpd_opp_svs>; 3316 }; 3317 3318 opp-358000000 { 3319 opp-hz = /bits/ 64 <358000000>; 3320 required-opps = <&rpmhpd_opp_svs_l1>; 3321 }; 3322 }; 3323 }; 3324 3325 mdss_dsi_phy: phy@ae94400 { 3326 compatible = "qcom,sc7280-dsi-phy-7nm"; 3327 reg = <0 0x0ae94400 0 0x200>, 3328 <0 0x0ae94600 0 0x280>, 3329 <0 0x0ae94900 0 0x280>; 3330 reg-names = "dsi_phy", 3331 "dsi_phy_lane", 3332 "dsi_pll"; 3333 3334 #clock-cells = <1>; 3335 #phy-cells = <0>; 3336 3337 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3338 <&rpmhcc RPMH_CXO_CLK>; 3339 clock-names = "iface", "ref"; 3340 3341 status = "disabled"; 3342 }; 3343 3344 mdss_edp: edp@aea0000 { 3345 compatible = "qcom,sc7280-edp"; 3346 pinctrl-names = "default"; 3347 pinctrl-0 = <&edp_hot_plug_det>; 3348 3349 reg = <0 0xaea0000 0 0x200>, 3350 <0 0xaea0200 0 0x200>, 3351 <0 0xaea0400 0 0xc00>, 3352 <0 0xaea1000 0 0x400>; 3353 3354 interrupt-parent = <&mdss>; 3355 interrupts = <14>; 3356 3357 clocks = <&rpmhcc RPMH_CXO_CLK>, 3358 <&gcc GCC_EDP_CLKREF_EN>, 3359 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3360 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3361 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3362 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3363 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3364 clock-names = "core_xo", 3365 "core_ref", 3366 "core_iface", 3367 "core_aux", 3368 "ctrl_link", 3369 "ctrl_link_iface", 3370 "stream_pixel"; 3371 #clock-cells = <1>; 3372 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3373 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3374 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3375 3376 phys = <&mdss_edp_phy>; 3377 phy-names = "dp"; 3378 3379 operating-points-v2 = <&edp_opp_table>; 3380 power-domains = <&rpmhpd SC7280_CX>; 3381 3382 #address-cells = <1>; 3383 #size-cells = <0>; 3384 3385 status = "disabled"; 3386 3387 ports { 3388 #address-cells = <1>; 3389 #size-cells = <0>; 3390 3391 port@0 { 3392 reg = <0>; 3393 edp_in: endpoint { 3394 remote-endpoint = <&dpu_intf5_out>; 3395 }; 3396 }; 3397 3398 port@1 { 3399 reg = <1>; 3400 mdss_edp_out: endpoint { }; 3401 }; 3402 }; 3403 3404 edp_opp_table: opp-table { 3405 compatible = "operating-points-v2"; 3406 3407 opp-160000000 { 3408 opp-hz = /bits/ 64 <160000000>; 3409 required-opps = <&rpmhpd_opp_low_svs>; 3410 }; 3411 3412 opp-270000000 { 3413 opp-hz = /bits/ 64 <270000000>; 3414 required-opps = <&rpmhpd_opp_svs>; 3415 }; 3416 3417 opp-540000000 { 3418 opp-hz = /bits/ 64 <540000000>; 3419 required-opps = <&rpmhpd_opp_nom>; 3420 }; 3421 3422 opp-810000000 { 3423 opp-hz = /bits/ 64 <810000000>; 3424 required-opps = <&rpmhpd_opp_nom>; 3425 }; 3426 }; 3427 }; 3428 3429 mdss_edp_phy: phy@aec2a00 { 3430 compatible = "qcom,sc7280-edp-phy"; 3431 3432 reg = <0 0xaec2a00 0 0x19c>, 3433 <0 0xaec2200 0 0xa0>, 3434 <0 0xaec2600 0 0xa0>, 3435 <0 0xaec2000 0 0x1c0>; 3436 3437 clocks = <&rpmhcc RPMH_CXO_CLK>, 3438 <&gcc GCC_EDP_CLKREF_EN>; 3439 clock-names = "aux", 3440 "cfg_ahb"; 3441 3442 #clock-cells = <1>; 3443 #phy-cells = <0>; 3444 3445 status = "disabled"; 3446 }; 3447 3448 mdss_dp: displayport-controller@ae90000 { 3449 compatible = "qcom,sc7280-dp"; 3450 3451 reg = <0 0x0ae90000 0 0x1400>; 3452 3453 interrupt-parent = <&mdss>; 3454 interrupts = <12>; 3455 3456 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3457 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3458 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3459 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3460 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3461 clock-names = "core_iface", 3462 "core_aux", 3463 "ctrl_link", 3464 "ctrl_link_iface", 3465 "stream_pixel"; 3466 #clock-cells = <1>; 3467 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3468 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3469 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3470 phys = <&dp_phy>; 3471 phy-names = "dp"; 3472 3473 operating-points-v2 = <&dp_opp_table>; 3474 power-domains = <&rpmhpd SC7280_CX>; 3475 3476 #sound-dai-cells = <0>; 3477 3478 status = "disabled"; 3479 3480 ports { 3481 #address-cells = <1>; 3482 #size-cells = <0>; 3483 3484 port@0 { 3485 reg = <0>; 3486 dp_in: endpoint { 3487 remote-endpoint = <&dpu_intf0_out>; 3488 }; 3489 }; 3490 3491 port@1 { 3492 reg = <1>; 3493 dp_out: endpoint { }; 3494 }; 3495 }; 3496 3497 dp_opp_table: opp-table { 3498 compatible = "operating-points-v2"; 3499 3500 opp-160000000 { 3501 opp-hz = /bits/ 64 <160000000>; 3502 required-opps = <&rpmhpd_opp_low_svs>; 3503 }; 3504 3505 opp-270000000 { 3506 opp-hz = /bits/ 64 <270000000>; 3507 required-opps = <&rpmhpd_opp_svs>; 3508 }; 3509 3510 opp-540000000 { 3511 opp-hz = /bits/ 64 <540000000>; 3512 required-opps = <&rpmhpd_opp_svs_l1>; 3513 }; 3514 3515 opp-810000000 { 3516 opp-hz = /bits/ 64 <810000000>; 3517 required-opps = <&rpmhpd_opp_nom>; 3518 }; 3519 }; 3520 }; 3521 }; 3522 3523 pdc: interrupt-controller@b220000 { 3524 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3525 reg = <0 0x0b220000 0 0x30000>; 3526 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3527 <55 306 4>, <59 312 3>, <62 374 2>, 3528 <64 434 2>, <66 438 3>, <69 86 1>, 3529 <70 520 54>, <124 609 31>, <155 63 1>, 3530 <156 716 12>; 3531 #interrupt-cells = <2>; 3532 interrupt-parent = <&intc>; 3533 interrupt-controller; 3534 }; 3535 3536 pdc_reset: reset-controller@b5e0000 { 3537 compatible = "qcom,sc7280-pdc-global"; 3538 reg = <0 0x0b5e0000 0 0x20000>; 3539 #reset-cells = <1>; 3540 }; 3541 3542 tsens0: thermal-sensor@c263000 { 3543 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3544 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3545 <0 0x0c222000 0 0x1ff>; /* SROT */ 3546 #qcom,sensors = <15>; 3547 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3549 interrupt-names = "uplow","critical"; 3550 #thermal-sensor-cells = <1>; 3551 }; 3552 3553 tsens1: thermal-sensor@c265000 { 3554 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3555 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3556 <0 0x0c223000 0 0x1ff>; /* SROT */ 3557 #qcom,sensors = <12>; 3558 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3560 interrupt-names = "uplow","critical"; 3561 #thermal-sensor-cells = <1>; 3562 }; 3563 3564 aoss_reset: reset-controller@c2a0000 { 3565 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3566 reg = <0 0x0c2a0000 0 0x31000>; 3567 #reset-cells = <1>; 3568 }; 3569 3570 aoss_qmp: power-controller@c300000 { 3571 compatible = "qcom,sc7280-aoss-qmp"; 3572 reg = <0 0x0c300000 0 0x400>; 3573 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3574 IPCC_MPROC_SIGNAL_GLINK_QMP 3575 IRQ_TYPE_EDGE_RISING>; 3576 mboxes = <&ipcc IPCC_CLIENT_AOP 3577 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3578 3579 #clock-cells = <0>; 3580 }; 3581 3582 sram@c3f0000 { 3583 compatible = "qcom,rpmh-stats"; 3584 reg = <0 0x0c3f0000 0 0x400>; 3585 }; 3586 3587 spmi_bus: spmi@c440000 { 3588 compatible = "qcom,spmi-pmic-arb"; 3589 reg = <0 0x0c440000 0 0x1100>, 3590 <0 0x0c600000 0 0x2000000>, 3591 <0 0x0e600000 0 0x100000>, 3592 <0 0x0e700000 0 0xa0000>, 3593 <0 0x0c40a000 0 0x26000>; 3594 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3595 interrupt-names = "periph_irq"; 3596 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3597 qcom,ee = <0>; 3598 qcom,channel = <0>; 3599 #address-cells = <1>; 3600 #size-cells = <1>; 3601 interrupt-controller; 3602 #interrupt-cells = <4>; 3603 }; 3604 3605 tlmm: pinctrl@f100000 { 3606 compatible = "qcom,sc7280-pinctrl"; 3607 reg = <0 0x0f100000 0 0x300000>; 3608 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3609 gpio-controller; 3610 #gpio-cells = <2>; 3611 interrupt-controller; 3612 #interrupt-cells = <2>; 3613 gpio-ranges = <&tlmm 0 0 175>; 3614 wakeup-parent = <&pdc>; 3615 3616 dp_hot_plug_det: dp-hot-plug-det { 3617 pins = "gpio47"; 3618 function = "dp_hot"; 3619 }; 3620 3621 edp_hot_plug_det: edp-hot-plug-det { 3622 pins = "gpio60"; 3623 function = "edp_hot"; 3624 }; 3625 3626 pcie1_clkreq_n: pcie1-clkreq-n { 3627 pins = "gpio79"; 3628 function = "pcie1_clkreqn"; 3629 }; 3630 3631 qspi_clk: qspi-clk { 3632 pins = "gpio14"; 3633 function = "qspi_clk"; 3634 }; 3635 3636 qspi_cs0: qspi-cs0 { 3637 pins = "gpio15"; 3638 function = "qspi_cs"; 3639 }; 3640 3641 qspi_cs1: qspi-cs1 { 3642 pins = "gpio19"; 3643 function = "qspi_cs"; 3644 }; 3645 3646 qspi_data01: qspi-data01 { 3647 pins = "gpio12", "gpio13"; 3648 function = "qspi_data"; 3649 }; 3650 3651 qspi_data12: qspi-data12 { 3652 pins = "gpio16", "gpio17"; 3653 function = "qspi_data"; 3654 }; 3655 3656 qup_i2c0_data_clk: qup-i2c0-data-clk { 3657 pins = "gpio0", "gpio1"; 3658 function = "qup00"; 3659 }; 3660 3661 qup_i2c1_data_clk: qup-i2c1-data-clk { 3662 pins = "gpio4", "gpio5"; 3663 function = "qup01"; 3664 }; 3665 3666 qup_i2c2_data_clk: qup-i2c2-data-clk { 3667 pins = "gpio8", "gpio9"; 3668 function = "qup02"; 3669 }; 3670 3671 qup_i2c3_data_clk: qup-i2c3-data-clk { 3672 pins = "gpio12", "gpio13"; 3673 function = "qup03"; 3674 }; 3675 3676 qup_i2c4_data_clk: qup-i2c4-data-clk { 3677 pins = "gpio16", "gpio17"; 3678 function = "qup04"; 3679 }; 3680 3681 qup_i2c5_data_clk: qup-i2c5-data-clk { 3682 pins = "gpio20", "gpio21"; 3683 function = "qup05"; 3684 }; 3685 3686 qup_i2c6_data_clk: qup-i2c6-data-clk { 3687 pins = "gpio24", "gpio25"; 3688 function = "qup06"; 3689 }; 3690 3691 qup_i2c7_data_clk: qup-i2c7-data-clk { 3692 pins = "gpio28", "gpio29"; 3693 function = "qup07"; 3694 }; 3695 3696 qup_i2c8_data_clk: qup-i2c8-data-clk { 3697 pins = "gpio32", "gpio33"; 3698 function = "qup10"; 3699 }; 3700 3701 qup_i2c9_data_clk: qup-i2c9-data-clk { 3702 pins = "gpio36", "gpio37"; 3703 function = "qup11"; 3704 }; 3705 3706 qup_i2c10_data_clk: qup-i2c10-data-clk { 3707 pins = "gpio40", "gpio41"; 3708 function = "qup12"; 3709 }; 3710 3711 qup_i2c11_data_clk: qup-i2c11-data-clk { 3712 pins = "gpio44", "gpio45"; 3713 function = "qup13"; 3714 }; 3715 3716 qup_i2c12_data_clk: qup-i2c12-data-clk { 3717 pins = "gpio48", "gpio49"; 3718 function = "qup14"; 3719 }; 3720 3721 qup_i2c13_data_clk: qup-i2c13-data-clk { 3722 pins = "gpio52", "gpio53"; 3723 function = "qup15"; 3724 }; 3725 3726 qup_i2c14_data_clk: qup-i2c14-data-clk { 3727 pins = "gpio56", "gpio57"; 3728 function = "qup16"; 3729 }; 3730 3731 qup_i2c15_data_clk: qup-i2c15-data-clk { 3732 pins = "gpio60", "gpio61"; 3733 function = "qup17"; 3734 }; 3735 3736 qup_spi0_data_clk: qup-spi0-data-clk { 3737 pins = "gpio0", "gpio1", "gpio2"; 3738 function = "qup00"; 3739 }; 3740 3741 qup_spi0_cs: qup-spi0-cs { 3742 pins = "gpio3"; 3743 function = "qup00"; 3744 }; 3745 3746 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3747 pins = "gpio3"; 3748 function = "gpio"; 3749 }; 3750 3751 qup_spi1_data_clk: qup-spi1-data-clk { 3752 pins = "gpio4", "gpio5", "gpio6"; 3753 function = "qup01"; 3754 }; 3755 3756 qup_spi1_cs: qup-spi1-cs { 3757 pins = "gpio7"; 3758 function = "qup01"; 3759 }; 3760 3761 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3762 pins = "gpio7"; 3763 function = "gpio"; 3764 }; 3765 3766 qup_spi2_data_clk: qup-spi2-data-clk { 3767 pins = "gpio8", "gpio9", "gpio10"; 3768 function = "qup02"; 3769 }; 3770 3771 qup_spi2_cs: qup-spi2-cs { 3772 pins = "gpio11"; 3773 function = "qup02"; 3774 }; 3775 3776 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3777 pins = "gpio11"; 3778 function = "gpio"; 3779 }; 3780 3781 qup_spi3_data_clk: qup-spi3-data-clk { 3782 pins = "gpio12", "gpio13", "gpio14"; 3783 function = "qup03"; 3784 }; 3785 3786 qup_spi3_cs: qup-spi3-cs { 3787 pins = "gpio15"; 3788 function = "qup03"; 3789 }; 3790 3791 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3792 pins = "gpio15"; 3793 function = "gpio"; 3794 }; 3795 3796 qup_spi4_data_clk: qup-spi4-data-clk { 3797 pins = "gpio16", "gpio17", "gpio18"; 3798 function = "qup04"; 3799 }; 3800 3801 qup_spi4_cs: qup-spi4-cs { 3802 pins = "gpio19"; 3803 function = "qup04"; 3804 }; 3805 3806 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3807 pins = "gpio19"; 3808 function = "gpio"; 3809 }; 3810 3811 qup_spi5_data_clk: qup-spi5-data-clk { 3812 pins = "gpio20", "gpio21", "gpio22"; 3813 function = "qup05"; 3814 }; 3815 3816 qup_spi5_cs: qup-spi5-cs { 3817 pins = "gpio23"; 3818 function = "qup05"; 3819 }; 3820 3821 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3822 pins = "gpio23"; 3823 function = "gpio"; 3824 }; 3825 3826 qup_spi6_data_clk: qup-spi6-data-clk { 3827 pins = "gpio24", "gpio25", "gpio26"; 3828 function = "qup06"; 3829 }; 3830 3831 qup_spi6_cs: qup-spi6-cs { 3832 pins = "gpio27"; 3833 function = "qup06"; 3834 }; 3835 3836 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3837 pins = "gpio27"; 3838 function = "gpio"; 3839 }; 3840 3841 qup_spi7_data_clk: qup-spi7-data-clk { 3842 pins = "gpio28", "gpio29", "gpio30"; 3843 function = "qup07"; 3844 }; 3845 3846 qup_spi7_cs: qup-spi7-cs { 3847 pins = "gpio31"; 3848 function = "qup07"; 3849 }; 3850 3851 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3852 pins = "gpio31"; 3853 function = "gpio"; 3854 }; 3855 3856 qup_spi8_data_clk: qup-spi8-data-clk { 3857 pins = "gpio32", "gpio33", "gpio34"; 3858 function = "qup10"; 3859 }; 3860 3861 qup_spi8_cs: qup-spi8-cs { 3862 pins = "gpio35"; 3863 function = "qup10"; 3864 }; 3865 3866 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3867 pins = "gpio35"; 3868 function = "gpio"; 3869 }; 3870 3871 qup_spi9_data_clk: qup-spi9-data-clk { 3872 pins = "gpio36", "gpio37", "gpio38"; 3873 function = "qup11"; 3874 }; 3875 3876 qup_spi9_cs: qup-spi9-cs { 3877 pins = "gpio39"; 3878 function = "qup11"; 3879 }; 3880 3881 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3882 pins = "gpio39"; 3883 function = "gpio"; 3884 }; 3885 3886 qup_spi10_data_clk: qup-spi10-data-clk { 3887 pins = "gpio40", "gpio41", "gpio42"; 3888 function = "qup12"; 3889 }; 3890 3891 qup_spi10_cs: qup-spi10-cs { 3892 pins = "gpio43"; 3893 function = "qup12"; 3894 }; 3895 3896 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3897 pins = "gpio43"; 3898 function = "gpio"; 3899 }; 3900 3901 qup_spi11_data_clk: qup-spi11-data-clk { 3902 pins = "gpio44", "gpio45", "gpio46"; 3903 function = "qup13"; 3904 }; 3905 3906 qup_spi11_cs: qup-spi11-cs { 3907 pins = "gpio47"; 3908 function = "qup13"; 3909 }; 3910 3911 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3912 pins = "gpio47"; 3913 function = "gpio"; 3914 }; 3915 3916 qup_spi12_data_clk: qup-spi12-data-clk { 3917 pins = "gpio48", "gpio49", "gpio50"; 3918 function = "qup14"; 3919 }; 3920 3921 qup_spi12_cs: qup-spi12-cs { 3922 pins = "gpio51"; 3923 function = "qup14"; 3924 }; 3925 3926 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3927 pins = "gpio51"; 3928 function = "gpio"; 3929 }; 3930 3931 qup_spi13_data_clk: qup-spi13-data-clk { 3932 pins = "gpio52", "gpio53", "gpio54"; 3933 function = "qup15"; 3934 }; 3935 3936 qup_spi13_cs: qup-spi13-cs { 3937 pins = "gpio55"; 3938 function = "qup15"; 3939 }; 3940 3941 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3942 pins = "gpio55"; 3943 function = "gpio"; 3944 }; 3945 3946 qup_spi14_data_clk: qup-spi14-data-clk { 3947 pins = "gpio56", "gpio57", "gpio58"; 3948 function = "qup16"; 3949 }; 3950 3951 qup_spi14_cs: qup-spi14-cs { 3952 pins = "gpio59"; 3953 function = "qup16"; 3954 }; 3955 3956 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3957 pins = "gpio59"; 3958 function = "gpio"; 3959 }; 3960 3961 qup_spi15_data_clk: qup-spi15-data-clk { 3962 pins = "gpio60", "gpio61", "gpio62"; 3963 function = "qup17"; 3964 }; 3965 3966 qup_spi15_cs: qup-spi15-cs { 3967 pins = "gpio63"; 3968 function = "qup17"; 3969 }; 3970 3971 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3972 pins = "gpio63"; 3973 function = "gpio"; 3974 }; 3975 3976 qup_uart0_cts: qup-uart0-cts { 3977 pins = "gpio0"; 3978 function = "qup00"; 3979 }; 3980 3981 qup_uart0_rts: qup-uart0-rts { 3982 pins = "gpio1"; 3983 function = "qup00"; 3984 }; 3985 3986 qup_uart0_tx: qup-uart0-tx { 3987 pins = "gpio2"; 3988 function = "qup00"; 3989 }; 3990 3991 qup_uart0_rx: qup-uart0-rx { 3992 pins = "gpio3"; 3993 function = "qup00"; 3994 }; 3995 3996 qup_uart1_cts: qup-uart1-cts { 3997 pins = "gpio4"; 3998 function = "qup01"; 3999 }; 4000 4001 qup_uart1_rts: qup-uart1-rts { 4002 pins = "gpio5"; 4003 function = "qup01"; 4004 }; 4005 4006 qup_uart1_tx: qup-uart1-tx { 4007 pins = "gpio6"; 4008 function = "qup01"; 4009 }; 4010 4011 qup_uart1_rx: qup-uart1-rx { 4012 pins = "gpio7"; 4013 function = "qup01"; 4014 }; 4015 4016 qup_uart2_cts: qup-uart2-cts { 4017 pins = "gpio8"; 4018 function = "qup02"; 4019 }; 4020 4021 qup_uart2_rts: qup-uart2-rts { 4022 pins = "gpio9"; 4023 function = "qup02"; 4024 }; 4025 4026 qup_uart2_tx: qup-uart2-tx { 4027 pins = "gpio10"; 4028 function = "qup02"; 4029 }; 4030 4031 qup_uart2_rx: qup-uart2-rx { 4032 pins = "gpio11"; 4033 function = "qup02"; 4034 }; 4035 4036 qup_uart3_cts: qup-uart3-cts { 4037 pins = "gpio12"; 4038 function = "qup03"; 4039 }; 4040 4041 qup_uart3_rts: qup-uart3-rts { 4042 pins = "gpio13"; 4043 function = "qup03"; 4044 }; 4045 4046 qup_uart3_tx: qup-uart3-tx { 4047 pins = "gpio14"; 4048 function = "qup03"; 4049 }; 4050 4051 qup_uart3_rx: qup-uart3-rx { 4052 pins = "gpio15"; 4053 function = "qup03"; 4054 }; 4055 4056 qup_uart4_cts: qup-uart4-cts { 4057 pins = "gpio16"; 4058 function = "qup04"; 4059 }; 4060 4061 qup_uart4_rts: qup-uart4-rts { 4062 pins = "gpio17"; 4063 function = "qup04"; 4064 }; 4065 4066 qup_uart4_tx: qup-uart4-tx { 4067 pins = "gpio18"; 4068 function = "qup04"; 4069 }; 4070 4071 qup_uart4_rx: qup-uart4-rx { 4072 pins = "gpio19"; 4073 function = "qup04"; 4074 }; 4075 4076 qup_uart5_cts: qup-uart5-cts { 4077 pins = "gpio20"; 4078 function = "qup05"; 4079 }; 4080 4081 qup_uart5_rts: qup-uart5-rts { 4082 pins = "gpio21"; 4083 function = "qup05"; 4084 }; 4085 4086 qup_uart5_tx: qup-uart5-tx { 4087 pins = "gpio22"; 4088 function = "qup05"; 4089 }; 4090 4091 qup_uart5_rx: qup-uart5-rx { 4092 pins = "gpio23"; 4093 function = "qup05"; 4094 }; 4095 4096 qup_uart6_cts: qup-uart6-cts { 4097 pins = "gpio24"; 4098 function = "qup06"; 4099 }; 4100 4101 qup_uart6_rts: qup-uart6-rts { 4102 pins = "gpio25"; 4103 function = "qup06"; 4104 }; 4105 4106 qup_uart6_tx: qup-uart6-tx { 4107 pins = "gpio26"; 4108 function = "qup06"; 4109 }; 4110 4111 qup_uart6_rx: qup-uart6-rx { 4112 pins = "gpio27"; 4113 function = "qup06"; 4114 }; 4115 4116 qup_uart7_cts: qup-uart7-cts { 4117 pins = "gpio28"; 4118 function = "qup07"; 4119 }; 4120 4121 qup_uart7_rts: qup-uart7-rts { 4122 pins = "gpio29"; 4123 function = "qup07"; 4124 }; 4125 4126 qup_uart7_tx: qup-uart7-tx { 4127 pins = "gpio30"; 4128 function = "qup07"; 4129 }; 4130 4131 qup_uart7_rx: qup-uart7-rx { 4132 pins = "gpio31"; 4133 function = "qup07"; 4134 }; 4135 4136 qup_uart8_cts: qup-uart8-cts { 4137 pins = "gpio32"; 4138 function = "qup10"; 4139 }; 4140 4141 qup_uart8_rts: qup-uart8-rts { 4142 pins = "gpio33"; 4143 function = "qup10"; 4144 }; 4145 4146 qup_uart8_tx: qup-uart8-tx { 4147 pins = "gpio34"; 4148 function = "qup10"; 4149 }; 4150 4151 qup_uart8_rx: qup-uart8-rx { 4152 pins = "gpio35"; 4153 function = "qup10"; 4154 }; 4155 4156 qup_uart9_cts: qup-uart9-cts { 4157 pins = "gpio36"; 4158 function = "qup11"; 4159 }; 4160 4161 qup_uart9_rts: qup-uart9-rts { 4162 pins = "gpio37"; 4163 function = "qup11"; 4164 }; 4165 4166 qup_uart9_tx: qup-uart9-tx { 4167 pins = "gpio38"; 4168 function = "qup11"; 4169 }; 4170 4171 qup_uart9_rx: qup-uart9-rx { 4172 pins = "gpio39"; 4173 function = "qup11"; 4174 }; 4175 4176 qup_uart10_cts: qup-uart10-cts { 4177 pins = "gpio40"; 4178 function = "qup12"; 4179 }; 4180 4181 qup_uart10_rts: qup-uart10-rts { 4182 pins = "gpio41"; 4183 function = "qup12"; 4184 }; 4185 4186 qup_uart10_tx: qup-uart10-tx { 4187 pins = "gpio42"; 4188 function = "qup12"; 4189 }; 4190 4191 qup_uart10_rx: qup-uart10-rx { 4192 pins = "gpio43"; 4193 function = "qup12"; 4194 }; 4195 4196 qup_uart11_cts: qup-uart11-cts { 4197 pins = "gpio44"; 4198 function = "qup13"; 4199 }; 4200 4201 qup_uart11_rts: qup-uart11-rts { 4202 pins = "gpio45"; 4203 function = "qup13"; 4204 }; 4205 4206 qup_uart11_tx: qup-uart11-tx { 4207 pins = "gpio46"; 4208 function = "qup13"; 4209 }; 4210 4211 qup_uart11_rx: qup-uart11-rx { 4212 pins = "gpio47"; 4213 function = "qup13"; 4214 }; 4215 4216 qup_uart12_cts: qup-uart12-cts { 4217 pins = "gpio48"; 4218 function = "qup14"; 4219 }; 4220 4221 qup_uart12_rts: qup-uart12-rts { 4222 pins = "gpio49"; 4223 function = "qup14"; 4224 }; 4225 4226 qup_uart12_tx: qup-uart12-tx { 4227 pins = "gpio50"; 4228 function = "qup14"; 4229 }; 4230 4231 qup_uart12_rx: qup-uart12-rx { 4232 pins = "gpio51"; 4233 function = "qup14"; 4234 }; 4235 4236 qup_uart13_cts: qup-uart13-cts { 4237 pins = "gpio52"; 4238 function = "qup15"; 4239 }; 4240 4241 qup_uart13_rts: qup-uart13-rts { 4242 pins = "gpio53"; 4243 function = "qup15"; 4244 }; 4245 4246 qup_uart13_tx: qup-uart13-tx { 4247 pins = "gpio54"; 4248 function = "qup15"; 4249 }; 4250 4251 qup_uart13_rx: qup-uart13-rx { 4252 pins = "gpio55"; 4253 function = "qup15"; 4254 }; 4255 4256 qup_uart14_cts: qup-uart14-cts { 4257 pins = "gpio56"; 4258 function = "qup16"; 4259 }; 4260 4261 qup_uart14_rts: qup-uart14-rts { 4262 pins = "gpio57"; 4263 function = "qup16"; 4264 }; 4265 4266 qup_uart14_tx: qup-uart14-tx { 4267 pins = "gpio58"; 4268 function = "qup16"; 4269 }; 4270 4271 qup_uart14_rx: qup-uart14-rx { 4272 pins = "gpio59"; 4273 function = "qup16"; 4274 }; 4275 4276 qup_uart15_cts: qup-uart15-cts { 4277 pins = "gpio60"; 4278 function = "qup17"; 4279 }; 4280 4281 qup_uart15_rts: qup-uart15-rts { 4282 pins = "gpio61"; 4283 function = "qup17"; 4284 }; 4285 4286 qup_uart15_tx: qup-uart15-tx { 4287 pins = "gpio62"; 4288 function = "qup17"; 4289 }; 4290 4291 qup_uart15_rx: qup-uart15-rx { 4292 pins = "gpio63"; 4293 function = "qup17"; 4294 }; 4295 4296 sdc1_clk: sdc1-clk { 4297 pins = "sdc1_clk"; 4298 }; 4299 4300 sdc1_cmd: sdc1-cmd { 4301 pins = "sdc1_cmd"; 4302 }; 4303 4304 sdc1_data: sdc1-data { 4305 pins = "sdc1_data"; 4306 }; 4307 4308 sdc1_rclk: sdc1-rclk { 4309 pins = "sdc1_rclk"; 4310 }; 4311 4312 sdc1_clk_sleep: sdc1-clk-sleep { 4313 pins = "sdc1_clk"; 4314 drive-strength = <2>; 4315 bias-bus-hold; 4316 }; 4317 4318 sdc1_cmd_sleep: sdc1-cmd-sleep { 4319 pins = "sdc1_cmd"; 4320 drive-strength = <2>; 4321 bias-bus-hold; 4322 }; 4323 4324 sdc1_data_sleep: sdc1-data-sleep { 4325 pins = "sdc1_data"; 4326 drive-strength = <2>; 4327 bias-bus-hold; 4328 }; 4329 4330 sdc1_rclk_sleep: sdc1-rclk-sleep { 4331 pins = "sdc1_rclk"; 4332 drive-strength = <2>; 4333 bias-bus-hold; 4334 }; 4335 4336 sdc2_clk: sdc2-clk { 4337 pins = "sdc2_clk"; 4338 }; 4339 4340 sdc2_cmd: sdc2-cmd { 4341 pins = "sdc2_cmd"; 4342 }; 4343 4344 sdc2_data: sdc2-data { 4345 pins = "sdc2_data"; 4346 }; 4347 4348 sdc2_clk_sleep: sdc2-clk-sleep { 4349 pins = "sdc2_clk"; 4350 drive-strength = <2>; 4351 bias-bus-hold; 4352 }; 4353 4354 sdc2_cmd_sleep: sdc2-cmd-sleep { 4355 pins = "sdc2_cmd"; 4356 drive-strength = <2>; 4357 bias-bus-hold; 4358 }; 4359 4360 sdc2_data_sleep: sdc2-data-sleep { 4361 pins = "sdc2_data"; 4362 drive-strength = <2>; 4363 bias-bus-hold; 4364 }; 4365 }; 4366 4367 imem@146a5000 { 4368 compatible = "qcom,sc7280-imem", "syscon"; 4369 reg = <0 0x146a5000 0 0x6000>; 4370 4371 #address-cells = <1>; 4372 #size-cells = <1>; 4373 4374 ranges = <0 0 0x146a5000 0x6000>; 4375 4376 pil-reloc@594c { 4377 compatible = "qcom,pil-reloc-info"; 4378 reg = <0x594c 0xc8>; 4379 }; 4380 }; 4381 4382 apps_smmu: iommu@15000000 { 4383 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4384 reg = <0 0x15000000 0 0x100000>; 4385 #iommu-cells = <2>; 4386 #global-interrupts = <1>; 4387 dma-coherent; 4388 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4399 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4409 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4410 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4411 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4412 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4413 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4414 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4415 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4416 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4417 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4418 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4419 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4420 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4421 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4422 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4423 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4424 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4425 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4426 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4427 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4428 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4429 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4430 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4431 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4432 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4433 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4434 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4435 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4436 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4437 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4438 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4440 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4441 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4442 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4443 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4444 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4445 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4446 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4447 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4448 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4449 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4450 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4451 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4452 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4453 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4454 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4455 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4456 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4457 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4458 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4459 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4460 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4461 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4462 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4463 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4464 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4465 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4466 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4467 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4468 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4469 }; 4470 4471 intc: interrupt-controller@17a00000 { 4472 compatible = "arm,gic-v3"; 4473 #address-cells = <2>; 4474 #size-cells = <2>; 4475 ranges; 4476 #interrupt-cells = <3>; 4477 interrupt-controller; 4478 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4479 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4480 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4481 4482 gic-its@17a40000 { 4483 compatible = "arm,gic-v3-its"; 4484 msi-controller; 4485 #msi-cells = <1>; 4486 reg = <0 0x17a40000 0 0x20000>; 4487 status = "disabled"; 4488 }; 4489 }; 4490 4491 watchdog@17c10000 { 4492 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4493 reg = <0 0x17c10000 0 0x1000>; 4494 clocks = <&sleep_clk>; 4495 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4496 }; 4497 4498 timer@17c20000 { 4499 #address-cells = <2>; 4500 #size-cells = <2>; 4501 ranges; 4502 compatible = "arm,armv7-timer-mem"; 4503 reg = <0 0x17c20000 0 0x1000>; 4504 4505 frame@17c21000 { 4506 frame-number = <0>; 4507 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4509 reg = <0 0x17c21000 0 0x1000>, 4510 <0 0x17c22000 0 0x1000>; 4511 }; 4512 4513 frame@17c23000 { 4514 frame-number = <1>; 4515 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4516 reg = <0 0x17c23000 0 0x1000>; 4517 status = "disabled"; 4518 }; 4519 4520 frame@17c25000 { 4521 frame-number = <2>; 4522 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4523 reg = <0 0x17c25000 0 0x1000>; 4524 status = "disabled"; 4525 }; 4526 4527 frame@17c27000 { 4528 frame-number = <3>; 4529 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4530 reg = <0 0x17c27000 0 0x1000>; 4531 status = "disabled"; 4532 }; 4533 4534 frame@17c29000 { 4535 frame-number = <4>; 4536 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4537 reg = <0 0x17c29000 0 0x1000>; 4538 status = "disabled"; 4539 }; 4540 4541 frame@17c2b000 { 4542 frame-number = <5>; 4543 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4544 reg = <0 0x17c2b000 0 0x1000>; 4545 status = "disabled"; 4546 }; 4547 4548 frame@17c2d000 { 4549 frame-number = <6>; 4550 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4551 reg = <0 0x17c2d000 0 0x1000>; 4552 status = "disabled"; 4553 }; 4554 }; 4555 4556 apps_rsc: rsc@18200000 { 4557 compatible = "qcom,rpmh-rsc"; 4558 reg = <0 0x18200000 0 0x10000>, 4559 <0 0x18210000 0 0x10000>, 4560 <0 0x18220000 0 0x10000>; 4561 reg-names = "drv-0", "drv-1", "drv-2"; 4562 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4563 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4564 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4565 qcom,tcs-offset = <0xd00>; 4566 qcom,drv-id = <2>; 4567 qcom,tcs-config = <ACTIVE_TCS 2>, 4568 <SLEEP_TCS 3>, 4569 <WAKE_TCS 3>, 4570 <CONTROL_TCS 1>; 4571 4572 apps_bcm_voter: bcm-voter { 4573 compatible = "qcom,bcm-voter"; 4574 }; 4575 4576 rpmhpd: power-controller { 4577 compatible = "qcom,sc7280-rpmhpd"; 4578 #power-domain-cells = <1>; 4579 operating-points-v2 = <&rpmhpd_opp_table>; 4580 4581 rpmhpd_opp_table: opp-table { 4582 compatible = "operating-points-v2"; 4583 4584 rpmhpd_opp_ret: opp1 { 4585 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4586 }; 4587 4588 rpmhpd_opp_low_svs: opp2 { 4589 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4590 }; 4591 4592 rpmhpd_opp_svs: opp3 { 4593 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4594 }; 4595 4596 rpmhpd_opp_svs_l1: opp4 { 4597 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4598 }; 4599 4600 rpmhpd_opp_svs_l2: opp5 { 4601 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4602 }; 4603 4604 rpmhpd_opp_nom: opp6 { 4605 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4606 }; 4607 4608 rpmhpd_opp_nom_l1: opp7 { 4609 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4610 }; 4611 4612 rpmhpd_opp_turbo: opp8 { 4613 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4614 }; 4615 4616 rpmhpd_opp_turbo_l1: opp9 { 4617 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4618 }; 4619 }; 4620 }; 4621 4622 rpmhcc: clock-controller { 4623 compatible = "qcom,sc7280-rpmh-clk"; 4624 clocks = <&xo_board>; 4625 clock-names = "xo"; 4626 #clock-cells = <1>; 4627 }; 4628 }; 4629 4630 epss_l3: interconnect@18590000 { 4631 compatible = "qcom,sc7280-epss-l3"; 4632 reg = <0 0x18590000 0 0x1000>; 4633 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4634 clock-names = "xo", "alternate"; 4635 #interconnect-cells = <1>; 4636 }; 4637 4638 cpufreq_hw: cpufreq@18591000 { 4639 compatible = "qcom,cpufreq-epss"; 4640 reg = <0 0x18591000 0 0x1000>, 4641 <0 0x18592000 0 0x1000>, 4642 <0 0x18593000 0 0x1000>; 4643 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4644 clock-names = "xo", "alternate"; 4645 #freq-domain-cells = <1>; 4646 }; 4647 }; 4648 4649 thermal_zones: thermal-zones { 4650 cpu0-thermal { 4651 polling-delay-passive = <250>; 4652 polling-delay = <0>; 4653 4654 thermal-sensors = <&tsens0 1>; 4655 4656 trips { 4657 cpu0_alert0: trip-point0 { 4658 temperature = <90000>; 4659 hysteresis = <2000>; 4660 type = "passive"; 4661 }; 4662 4663 cpu0_alert1: trip-point1 { 4664 temperature = <95000>; 4665 hysteresis = <2000>; 4666 type = "passive"; 4667 }; 4668 4669 cpu0_crit: cpu-crit { 4670 temperature = <110000>; 4671 hysteresis = <0>; 4672 type = "critical"; 4673 }; 4674 }; 4675 4676 cooling-maps { 4677 map0 { 4678 trip = <&cpu0_alert0>; 4679 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4681 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4683 }; 4684 map1 { 4685 trip = <&cpu0_alert1>; 4686 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4687 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4688 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4689 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4690 }; 4691 }; 4692 }; 4693 4694 cpu1-thermal { 4695 polling-delay-passive = <250>; 4696 polling-delay = <0>; 4697 4698 thermal-sensors = <&tsens0 2>; 4699 4700 trips { 4701 cpu1_alert0: trip-point0 { 4702 temperature = <90000>; 4703 hysteresis = <2000>; 4704 type = "passive"; 4705 }; 4706 4707 cpu1_alert1: trip-point1 { 4708 temperature = <95000>; 4709 hysteresis = <2000>; 4710 type = "passive"; 4711 }; 4712 4713 cpu1_crit: cpu-crit { 4714 temperature = <110000>; 4715 hysteresis = <0>; 4716 type = "critical"; 4717 }; 4718 }; 4719 4720 cooling-maps { 4721 map0 { 4722 trip = <&cpu1_alert0>; 4723 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4727 }; 4728 map1 { 4729 trip = <&cpu1_alert1>; 4730 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4731 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4732 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4733 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4734 }; 4735 }; 4736 }; 4737 4738 cpu2-thermal { 4739 polling-delay-passive = <250>; 4740 polling-delay = <0>; 4741 4742 thermal-sensors = <&tsens0 3>; 4743 4744 trips { 4745 cpu2_alert0: trip-point0 { 4746 temperature = <90000>; 4747 hysteresis = <2000>; 4748 type = "passive"; 4749 }; 4750 4751 cpu2_alert1: trip-point1 { 4752 temperature = <95000>; 4753 hysteresis = <2000>; 4754 type = "passive"; 4755 }; 4756 4757 cpu2_crit: cpu-crit { 4758 temperature = <110000>; 4759 hysteresis = <0>; 4760 type = "critical"; 4761 }; 4762 }; 4763 4764 cooling-maps { 4765 map0 { 4766 trip = <&cpu2_alert0>; 4767 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4771 }; 4772 map1 { 4773 trip = <&cpu2_alert1>; 4774 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4777 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4778 }; 4779 }; 4780 }; 4781 4782 cpu3-thermal { 4783 polling-delay-passive = <250>; 4784 polling-delay = <0>; 4785 4786 thermal-sensors = <&tsens0 4>; 4787 4788 trips { 4789 cpu3_alert0: trip-point0 { 4790 temperature = <90000>; 4791 hysteresis = <2000>; 4792 type = "passive"; 4793 }; 4794 4795 cpu3_alert1: trip-point1 { 4796 temperature = <95000>; 4797 hysteresis = <2000>; 4798 type = "passive"; 4799 }; 4800 4801 cpu3_crit: cpu-crit { 4802 temperature = <110000>; 4803 hysteresis = <0>; 4804 type = "critical"; 4805 }; 4806 }; 4807 4808 cooling-maps { 4809 map0 { 4810 trip = <&cpu3_alert0>; 4811 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4815 }; 4816 map1 { 4817 trip = <&cpu3_alert1>; 4818 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4821 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4822 }; 4823 }; 4824 }; 4825 4826 cpu4-thermal { 4827 polling-delay-passive = <250>; 4828 polling-delay = <0>; 4829 4830 thermal-sensors = <&tsens0 7>; 4831 4832 trips { 4833 cpu4_alert0: trip-point0 { 4834 temperature = <90000>; 4835 hysteresis = <2000>; 4836 type = "passive"; 4837 }; 4838 4839 cpu4_alert1: trip-point1 { 4840 temperature = <95000>; 4841 hysteresis = <2000>; 4842 type = "passive"; 4843 }; 4844 4845 cpu4_crit: cpu-crit { 4846 temperature = <110000>; 4847 hysteresis = <0>; 4848 type = "critical"; 4849 }; 4850 }; 4851 4852 cooling-maps { 4853 map0 { 4854 trip = <&cpu4_alert0>; 4855 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4859 }; 4860 map1 { 4861 trip = <&cpu4_alert1>; 4862 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4863 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4864 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4865 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4866 }; 4867 }; 4868 }; 4869 4870 cpu5-thermal { 4871 polling-delay-passive = <250>; 4872 polling-delay = <0>; 4873 4874 thermal-sensors = <&tsens0 8>; 4875 4876 trips { 4877 cpu5_alert0: trip-point0 { 4878 temperature = <90000>; 4879 hysteresis = <2000>; 4880 type = "passive"; 4881 }; 4882 4883 cpu5_alert1: trip-point1 { 4884 temperature = <95000>; 4885 hysteresis = <2000>; 4886 type = "passive"; 4887 }; 4888 4889 cpu5_crit: cpu-crit { 4890 temperature = <110000>; 4891 hysteresis = <0>; 4892 type = "critical"; 4893 }; 4894 }; 4895 4896 cooling-maps { 4897 map0 { 4898 trip = <&cpu5_alert0>; 4899 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4900 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4901 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4902 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4903 }; 4904 map1 { 4905 trip = <&cpu5_alert1>; 4906 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4907 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4908 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4909 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4910 }; 4911 }; 4912 }; 4913 4914 cpu6-thermal { 4915 polling-delay-passive = <250>; 4916 polling-delay = <0>; 4917 4918 thermal-sensors = <&tsens0 9>; 4919 4920 trips { 4921 cpu6_alert0: trip-point0 { 4922 temperature = <90000>; 4923 hysteresis = <2000>; 4924 type = "passive"; 4925 }; 4926 4927 cpu6_alert1: trip-point1 { 4928 temperature = <95000>; 4929 hysteresis = <2000>; 4930 type = "passive"; 4931 }; 4932 4933 cpu6_crit: cpu-crit { 4934 temperature = <110000>; 4935 hysteresis = <0>; 4936 type = "critical"; 4937 }; 4938 }; 4939 4940 cooling-maps { 4941 map0 { 4942 trip = <&cpu6_alert0>; 4943 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4944 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4945 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4946 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4947 }; 4948 map1 { 4949 trip = <&cpu6_alert1>; 4950 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4951 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4952 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4953 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4954 }; 4955 }; 4956 }; 4957 4958 cpu7-thermal { 4959 polling-delay-passive = <250>; 4960 polling-delay = <0>; 4961 4962 thermal-sensors = <&tsens0 10>; 4963 4964 trips { 4965 cpu7_alert0: trip-point0 { 4966 temperature = <90000>; 4967 hysteresis = <2000>; 4968 type = "passive"; 4969 }; 4970 4971 cpu7_alert1: trip-point1 { 4972 temperature = <95000>; 4973 hysteresis = <2000>; 4974 type = "passive"; 4975 }; 4976 4977 cpu7_crit: cpu-crit { 4978 temperature = <110000>; 4979 hysteresis = <0>; 4980 type = "critical"; 4981 }; 4982 }; 4983 4984 cooling-maps { 4985 map0 { 4986 trip = <&cpu7_alert0>; 4987 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4988 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4989 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4990 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4991 }; 4992 map1 { 4993 trip = <&cpu7_alert1>; 4994 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4995 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4996 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4997 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4998 }; 4999 }; 5000 }; 5001 5002 cpu8-thermal { 5003 polling-delay-passive = <250>; 5004 polling-delay = <0>; 5005 5006 thermal-sensors = <&tsens0 11>; 5007 5008 trips { 5009 cpu8_alert0: trip-point0 { 5010 temperature = <90000>; 5011 hysteresis = <2000>; 5012 type = "passive"; 5013 }; 5014 5015 cpu8_alert1: trip-point1 { 5016 temperature = <95000>; 5017 hysteresis = <2000>; 5018 type = "passive"; 5019 }; 5020 5021 cpu8_crit: cpu-crit { 5022 temperature = <110000>; 5023 hysteresis = <0>; 5024 type = "critical"; 5025 }; 5026 }; 5027 5028 cooling-maps { 5029 map0 { 5030 trip = <&cpu8_alert0>; 5031 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5032 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5033 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5034 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5035 }; 5036 map1 { 5037 trip = <&cpu8_alert1>; 5038 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5039 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5040 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5041 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5042 }; 5043 }; 5044 }; 5045 5046 cpu9-thermal { 5047 polling-delay-passive = <250>; 5048 polling-delay = <0>; 5049 5050 thermal-sensors = <&tsens0 12>; 5051 5052 trips { 5053 cpu9_alert0: trip-point0 { 5054 temperature = <90000>; 5055 hysteresis = <2000>; 5056 type = "passive"; 5057 }; 5058 5059 cpu9_alert1: trip-point1 { 5060 temperature = <95000>; 5061 hysteresis = <2000>; 5062 type = "passive"; 5063 }; 5064 5065 cpu9_crit: cpu-crit { 5066 temperature = <110000>; 5067 hysteresis = <0>; 5068 type = "critical"; 5069 }; 5070 }; 5071 5072 cooling-maps { 5073 map0 { 5074 trip = <&cpu9_alert0>; 5075 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5076 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5077 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5078 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5079 }; 5080 map1 { 5081 trip = <&cpu9_alert1>; 5082 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5083 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5084 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5085 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5086 }; 5087 }; 5088 }; 5089 5090 cpu10-thermal { 5091 polling-delay-passive = <250>; 5092 polling-delay = <0>; 5093 5094 thermal-sensors = <&tsens0 13>; 5095 5096 trips { 5097 cpu10_alert0: trip-point0 { 5098 temperature = <90000>; 5099 hysteresis = <2000>; 5100 type = "passive"; 5101 }; 5102 5103 cpu10_alert1: trip-point1 { 5104 temperature = <95000>; 5105 hysteresis = <2000>; 5106 type = "passive"; 5107 }; 5108 5109 cpu10_crit: cpu-crit { 5110 temperature = <110000>; 5111 hysteresis = <0>; 5112 type = "critical"; 5113 }; 5114 }; 5115 5116 cooling-maps { 5117 map0 { 5118 trip = <&cpu10_alert0>; 5119 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5120 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5121 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5122 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5123 }; 5124 map1 { 5125 trip = <&cpu10_alert1>; 5126 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5127 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5128 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5129 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5130 }; 5131 }; 5132 }; 5133 5134 cpu11-thermal { 5135 polling-delay-passive = <250>; 5136 polling-delay = <0>; 5137 5138 thermal-sensors = <&tsens0 14>; 5139 5140 trips { 5141 cpu11_alert0: trip-point0 { 5142 temperature = <90000>; 5143 hysteresis = <2000>; 5144 type = "passive"; 5145 }; 5146 5147 cpu11_alert1: trip-point1 { 5148 temperature = <95000>; 5149 hysteresis = <2000>; 5150 type = "passive"; 5151 }; 5152 5153 cpu11_crit: cpu-crit { 5154 temperature = <110000>; 5155 hysteresis = <0>; 5156 type = "critical"; 5157 }; 5158 }; 5159 5160 cooling-maps { 5161 map0 { 5162 trip = <&cpu11_alert0>; 5163 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5164 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5165 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5166 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5167 }; 5168 map1 { 5169 trip = <&cpu11_alert1>; 5170 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5171 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5172 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5173 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5174 }; 5175 }; 5176 }; 5177 5178 aoss0-thermal { 5179 polling-delay-passive = <0>; 5180 polling-delay = <0>; 5181 5182 thermal-sensors = <&tsens0 0>; 5183 5184 trips { 5185 aoss0_alert0: trip-point0 { 5186 temperature = <90000>; 5187 hysteresis = <2000>; 5188 type = "hot"; 5189 }; 5190 5191 aoss0_crit: aoss0-crit { 5192 temperature = <110000>; 5193 hysteresis = <0>; 5194 type = "critical"; 5195 }; 5196 }; 5197 }; 5198 5199 aoss1-thermal { 5200 polling-delay-passive = <0>; 5201 polling-delay = <0>; 5202 5203 thermal-sensors = <&tsens1 0>; 5204 5205 trips { 5206 aoss1_alert0: trip-point0 { 5207 temperature = <90000>; 5208 hysteresis = <2000>; 5209 type = "hot"; 5210 }; 5211 5212 aoss1_crit: aoss1-crit { 5213 temperature = <110000>; 5214 hysteresis = <0>; 5215 type = "critical"; 5216 }; 5217 }; 5218 }; 5219 5220 cpuss0-thermal { 5221 polling-delay-passive = <0>; 5222 polling-delay = <0>; 5223 5224 thermal-sensors = <&tsens0 5>; 5225 5226 trips { 5227 cpuss0_alert0: trip-point0 { 5228 temperature = <90000>; 5229 hysteresis = <2000>; 5230 type = "hot"; 5231 }; 5232 cpuss0_crit: cluster0-crit { 5233 temperature = <110000>; 5234 hysteresis = <0>; 5235 type = "critical"; 5236 }; 5237 }; 5238 }; 5239 5240 cpuss1-thermal { 5241 polling-delay-passive = <0>; 5242 polling-delay = <0>; 5243 5244 thermal-sensors = <&tsens0 6>; 5245 5246 trips { 5247 cpuss1_alert0: trip-point0 { 5248 temperature = <90000>; 5249 hysteresis = <2000>; 5250 type = "hot"; 5251 }; 5252 cpuss1_crit: cluster0-crit { 5253 temperature = <110000>; 5254 hysteresis = <0>; 5255 type = "critical"; 5256 }; 5257 }; 5258 }; 5259 5260 gpuss0-thermal { 5261 polling-delay-passive = <100>; 5262 polling-delay = <0>; 5263 5264 thermal-sensors = <&tsens1 1>; 5265 5266 trips { 5267 gpuss0_alert0: trip-point0 { 5268 temperature = <95000>; 5269 hysteresis = <2000>; 5270 type = "passive"; 5271 }; 5272 5273 gpuss0_crit: gpuss0-crit { 5274 temperature = <110000>; 5275 hysteresis = <0>; 5276 type = "critical"; 5277 }; 5278 }; 5279 5280 cooling-maps { 5281 map0 { 5282 trip = <&gpuss0_alert0>; 5283 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5284 }; 5285 }; 5286 }; 5287 5288 gpuss1-thermal { 5289 polling-delay-passive = <100>; 5290 polling-delay = <0>; 5291 5292 thermal-sensors = <&tsens1 2>; 5293 5294 trips { 5295 gpuss1_alert0: trip-point0 { 5296 temperature = <95000>; 5297 hysteresis = <2000>; 5298 type = "passive"; 5299 }; 5300 5301 gpuss1_crit: gpuss1-crit { 5302 temperature = <110000>; 5303 hysteresis = <0>; 5304 type = "critical"; 5305 }; 5306 }; 5307 5308 cooling-maps { 5309 map0 { 5310 trip = <&gpuss1_alert0>; 5311 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5312 }; 5313 }; 5314 }; 5315 5316 nspss0-thermal { 5317 polling-delay-passive = <0>; 5318 polling-delay = <0>; 5319 5320 thermal-sensors = <&tsens1 3>; 5321 5322 trips { 5323 nspss0_alert0: trip-point0 { 5324 temperature = <90000>; 5325 hysteresis = <2000>; 5326 type = "hot"; 5327 }; 5328 5329 nspss0_crit: nspss0-crit { 5330 temperature = <110000>; 5331 hysteresis = <0>; 5332 type = "critical"; 5333 }; 5334 }; 5335 }; 5336 5337 nspss1-thermal { 5338 polling-delay-passive = <0>; 5339 polling-delay = <0>; 5340 5341 thermal-sensors = <&tsens1 4>; 5342 5343 trips { 5344 nspss1_alert0: trip-point0 { 5345 temperature = <90000>; 5346 hysteresis = <2000>; 5347 type = "hot"; 5348 }; 5349 5350 nspss1_crit: nspss1-crit { 5351 temperature = <110000>; 5352 hysteresis = <0>; 5353 type = "critical"; 5354 }; 5355 }; 5356 }; 5357 5358 video-thermal { 5359 polling-delay-passive = <0>; 5360 polling-delay = <0>; 5361 5362 thermal-sensors = <&tsens1 5>; 5363 5364 trips { 5365 video_alert0: trip-point0 { 5366 temperature = <90000>; 5367 hysteresis = <2000>; 5368 type = "hot"; 5369 }; 5370 5371 video_crit: video-crit { 5372 temperature = <110000>; 5373 hysteresis = <0>; 5374 type = "critical"; 5375 }; 5376 }; 5377 }; 5378 5379 ddr-thermal { 5380 polling-delay-passive = <0>; 5381 polling-delay = <0>; 5382 5383 thermal-sensors = <&tsens1 6>; 5384 5385 trips { 5386 ddr_alert0: trip-point0 { 5387 temperature = <90000>; 5388 hysteresis = <2000>; 5389 type = "hot"; 5390 }; 5391 5392 ddr_crit: ddr-crit { 5393 temperature = <110000>; 5394 hysteresis = <0>; 5395 type = "critical"; 5396 }; 5397 }; 5398 }; 5399 5400 mdmss0-thermal { 5401 polling-delay-passive = <0>; 5402 polling-delay = <0>; 5403 5404 thermal-sensors = <&tsens1 7>; 5405 5406 trips { 5407 mdmss0_alert0: trip-point0 { 5408 temperature = <90000>; 5409 hysteresis = <2000>; 5410 type = "hot"; 5411 }; 5412 5413 mdmss0_crit: mdmss0-crit { 5414 temperature = <110000>; 5415 hysteresis = <0>; 5416 type = "critical"; 5417 }; 5418 }; 5419 }; 5420 5421 mdmss1-thermal { 5422 polling-delay-passive = <0>; 5423 polling-delay = <0>; 5424 5425 thermal-sensors = <&tsens1 8>; 5426 5427 trips { 5428 mdmss1_alert0: trip-point0 { 5429 temperature = <90000>; 5430 hysteresis = <2000>; 5431 type = "hot"; 5432 }; 5433 5434 mdmss1_crit: mdmss1-crit { 5435 temperature = <110000>; 5436 hysteresis = <0>; 5437 type = "critical"; 5438 }; 5439 }; 5440 }; 5441 5442 mdmss2-thermal { 5443 polling-delay-passive = <0>; 5444 polling-delay = <0>; 5445 5446 thermal-sensors = <&tsens1 9>; 5447 5448 trips { 5449 mdmss2_alert0: trip-point0 { 5450 temperature = <90000>; 5451 hysteresis = <2000>; 5452 type = "hot"; 5453 }; 5454 5455 mdmss2_crit: mdmss2-crit { 5456 temperature = <110000>; 5457 hysteresis = <0>; 5458 type = "critical"; 5459 }; 5460 }; 5461 }; 5462 5463 mdmss3-thermal { 5464 polling-delay-passive = <0>; 5465 polling-delay = <0>; 5466 5467 thermal-sensors = <&tsens1 10>; 5468 5469 trips { 5470 mdmss3_alert0: trip-point0 { 5471 temperature = <90000>; 5472 hysteresis = <2000>; 5473 type = "hot"; 5474 }; 5475 5476 mdmss3_crit: mdmss3-crit { 5477 temperature = <110000>; 5478 hysteresis = <0>; 5479 type = "critical"; 5480 }; 5481 }; 5482 }; 5483 5484 camera0-thermal { 5485 polling-delay-passive = <0>; 5486 polling-delay = <0>; 5487 5488 thermal-sensors = <&tsens1 11>; 5489 5490 trips { 5491 camera0_alert0: trip-point0 { 5492 temperature = <90000>; 5493 hysteresis = <2000>; 5494 type = "hot"; 5495 }; 5496 5497 camera0_crit: camera0-crit { 5498 temperature = <110000>; 5499 hysteresis = <0>; 5500 type = "critical"; 5501 }; 5502 }; 5503 }; 5504 }; 5505 5506 timer { 5507 compatible = "arm,armv8-timer"; 5508 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5509 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5510 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5511 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5512 }; 5513}; 5514