1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sc7280.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/reset/qcom,sdm845-aoss.h> 22#include <dt-bindings/reset/qcom,sdm845-pdc.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 aliases { 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 i2c12 = &i2c12; 48 i2c13 = &i2c13; 49 i2c14 = &i2c14; 50 i2c15 = &i2c15; 51 mmc1 = &sdhc_1; 52 mmc2 = &sdhc_2; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 }; 70 71 clocks { 72 xo_board: xo-board { 73 compatible = "fixed-clock"; 74 clock-frequency = <76800000>; 75 #clock-cells = <0>; 76 }; 77 78 sleep_clk: sleep-clk { 79 compatible = "fixed-clock"; 80 clock-frequency = <32000>; 81 #clock-cells = <0>; 82 }; 83 }; 84 85 reserved-memory { 86 #address-cells = <2>; 87 #size-cells = <2>; 88 ranges; 89 90 wlan_ce_mem: memory@4cd000 { 91 no-map; 92 reg = <0x0 0x004cd000 0x0 0x1000>; 93 }; 94 95 hyp_mem: memory@80000000 { 96 reg = <0x0 0x80000000 0x0 0x600000>; 97 no-map; 98 }; 99 100 xbl_mem: memory@80600000 { 101 reg = <0x0 0x80600000 0x0 0x200000>; 102 no-map; 103 }; 104 105 aop_mem: memory@80800000 { 106 reg = <0x0 0x80800000 0x0 0x60000>; 107 no-map; 108 }; 109 110 aop_cmd_db_mem: memory@80860000 { 111 reg = <0x0 0x80860000 0x0 0x20000>; 112 compatible = "qcom,cmd-db"; 113 no-map; 114 }; 115 116 reserved_xbl_uefi_log: memory@80880000 { 117 reg = <0x0 0x80884000 0x0 0x10000>; 118 no-map; 119 }; 120 121 sec_apps_mem: memory@808ff000 { 122 reg = <0x0 0x808ff000 0x0 0x1000>; 123 no-map; 124 }; 125 126 smem_mem: memory@80900000 { 127 reg = <0x0 0x80900000 0x0 0x200000>; 128 no-map; 129 }; 130 131 cpucp_mem: memory@80b00000 { 132 no-map; 133 reg = <0x0 0x80b00000 0x0 0x100000>; 134 }; 135 136 wlan_fw_mem: memory@80c00000 { 137 reg = <0x0 0x80c00000 0x0 0xc00000>; 138 no-map; 139 }; 140 141 video_mem: memory@8b200000 { 142 reg = <0x0 0x8b200000 0x0 0x500000>; 143 no-map; 144 }; 145 146 ipa_fw_mem: memory@8b700000 { 147 reg = <0 0x8b700000 0 0x10000>; 148 no-map; 149 }; 150 151 rmtfs_mem: memory@9c900000 { 152 compatible = "qcom,rmtfs-mem"; 153 reg = <0x0 0x9c900000 0x0 0x280000>; 154 no-map; 155 156 qcom,client-id = <1>; 157 qcom,vmid = <15>; 158 }; 159 }; 160 161 cpus { 162 #address-cells = <2>; 163 #size-cells = <0>; 164 165 CPU0: cpu@0 { 166 device_type = "cpu"; 167 compatible = "arm,kryo"; 168 reg = <0x0 0x0>; 169 enable-method = "psci"; 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 171 &LITTLE_CPU_SLEEP_1 172 &CLUSTER_SLEEP_0>; 173 next-level-cache = <&L2_0>; 174 operating-points-v2 = <&cpu0_opp_table>; 175 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 176 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 177 qcom,freq-domain = <&cpufreq_hw 0>; 178 #cooling-cells = <2>; 179 L2_0: l2-cache { 180 compatible = "cache"; 181 next-level-cache = <&L3_0>; 182 L3_0: l3-cache { 183 compatible = "cache"; 184 }; 185 }; 186 }; 187 188 CPU1: cpu@100 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x100>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_100>; 197 operating-points-v2 = <&cpu0_opp_table>; 198 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 199 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 200 qcom,freq-domain = <&cpufreq_hw 0>; 201 #cooling-cells = <2>; 202 L2_100: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU2: cpu@200 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x200>; 212 enable-method = "psci"; 213 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 214 &LITTLE_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_200>; 217 operating-points-v2 = <&cpu0_opp_table>; 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 219 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 L2_200: l2-cache { 223 compatible = "cache"; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU3: cpu@300 { 229 device_type = "cpu"; 230 compatible = "arm,kryo"; 231 reg = <0x0 0x300>; 232 enable-method = "psci"; 233 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 234 &LITTLE_CPU_SLEEP_1 235 &CLUSTER_SLEEP_0>; 236 next-level-cache = <&L2_300>; 237 operating-points-v2 = <&cpu0_opp_table>; 238 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 239 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 240 qcom,freq-domain = <&cpufreq_hw 0>; 241 #cooling-cells = <2>; 242 L2_300: l2-cache { 243 compatible = "cache"; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU4: cpu@400 { 249 device_type = "cpu"; 250 compatible = "arm,kryo"; 251 reg = <0x0 0x400>; 252 enable-method = "psci"; 253 cpu-idle-states = <&BIG_CPU_SLEEP_0 254 &BIG_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 next-level-cache = <&L2_400>; 257 operating-points-v2 = <&cpu4_opp_table>; 258 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 259 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 260 qcom,freq-domain = <&cpufreq_hw 1>; 261 #cooling-cells = <2>; 262 L2_400: l2-cache { 263 compatible = "cache"; 264 next-level-cache = <&L3_0>; 265 }; 266 }; 267 268 CPU5: cpu@500 { 269 device_type = "cpu"; 270 compatible = "arm,kryo"; 271 reg = <0x0 0x500>; 272 enable-method = "psci"; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276 next-level-cache = <&L2_500>; 277 operating-points-v2 = <&cpu4_opp_table>; 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 279 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 280 qcom,freq-domain = <&cpufreq_hw 1>; 281 #cooling-cells = <2>; 282 L2_500: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU6: cpu@600 { 289 device_type = "cpu"; 290 compatible = "arm,kryo"; 291 reg = <0x0 0x600>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_600>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_600: l2-cache { 303 compatible = "cache"; 304 next-level-cache = <&L3_0>; 305 }; 306 }; 307 308 CPU7: cpu@700 { 309 device_type = "cpu"; 310 compatible = "arm,kryo"; 311 reg = <0x0 0x700>; 312 enable-method = "psci"; 313 cpu-idle-states = <&BIG_CPU_SLEEP_0 314 &BIG_CPU_SLEEP_1 315 &CLUSTER_SLEEP_0>; 316 next-level-cache = <&L2_700>; 317 operating-points-v2 = <&cpu7_opp_table>; 318 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 319 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 320 qcom,freq-domain = <&cpufreq_hw 2>; 321 #cooling-cells = <2>; 322 L2_700: l2-cache { 323 compatible = "cache"; 324 next-level-cache = <&L3_0>; 325 }; 326 }; 327 328 cpu-map { 329 cluster0 { 330 core0 { 331 cpu = <&CPU0>; 332 }; 333 334 core1 { 335 cpu = <&CPU1>; 336 }; 337 338 core2 { 339 cpu = <&CPU2>; 340 }; 341 342 core3 { 343 cpu = <&CPU3>; 344 }; 345 346 core4 { 347 cpu = <&CPU4>; 348 }; 349 350 core5 { 351 cpu = <&CPU5>; 352 }; 353 354 core6 { 355 cpu = <&CPU6>; 356 }; 357 358 core7 { 359 cpu = <&CPU7>; 360 }; 361 }; 362 }; 363 364 idle-states { 365 entry-method = "psci"; 366 367 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 368 compatible = "arm,idle-state"; 369 idle-state-name = "little-power-down"; 370 arm,psci-suspend-param = <0x40000003>; 371 entry-latency-us = <549>; 372 exit-latency-us = <901>; 373 min-residency-us = <1774>; 374 local-timer-stop; 375 }; 376 377 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 378 compatible = "arm,idle-state"; 379 idle-state-name = "little-rail-power-down"; 380 arm,psci-suspend-param = <0x40000004>; 381 entry-latency-us = <702>; 382 exit-latency-us = <915>; 383 min-residency-us = <4001>; 384 local-timer-stop; 385 }; 386 387 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 388 compatible = "arm,idle-state"; 389 idle-state-name = "big-power-down"; 390 arm,psci-suspend-param = <0x40000003>; 391 entry-latency-us = <523>; 392 exit-latency-us = <1244>; 393 min-residency-us = <2207>; 394 local-timer-stop; 395 }; 396 397 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 398 compatible = "arm,idle-state"; 399 idle-state-name = "big-rail-power-down"; 400 arm,psci-suspend-param = <0x40000004>; 401 entry-latency-us = <526>; 402 exit-latency-us = <1854>; 403 min-residency-us = <5555>; 404 local-timer-stop; 405 }; 406 407 CLUSTER_SLEEP_0: cluster-sleep-0 { 408 compatible = "arm,idle-state"; 409 idle-state-name = "cluster-power-down"; 410 arm,psci-suspend-param = <0x40003444>; 411 entry-latency-us = <3263>; 412 exit-latency-us = <6562>; 413 min-residency-us = <9926>; 414 local-timer-stop; 415 }; 416 }; 417 }; 418 419 cpu0_opp_table: cpu0-opp-table { 420 compatible = "operating-points-v2"; 421 opp-shared; 422 423 cpu0_opp_300mhz: opp-300000000 { 424 opp-hz = /bits/ 64 <300000000>; 425 opp-peak-kBps = <800000 9600000>; 426 }; 427 428 cpu0_opp_691mhz: opp-691200000 { 429 opp-hz = /bits/ 64 <691200000>; 430 opp-peak-kBps = <800000 17817600>; 431 }; 432 433 cpu0_opp_806mhz: opp-806400000 { 434 opp-hz = /bits/ 64 <806400000>; 435 opp-peak-kBps = <800000 20889600>; 436 }; 437 438 cpu0_opp_941mhz: opp-940800000 { 439 opp-hz = /bits/ 64 <940800000>; 440 opp-peak-kBps = <1804000 24576000>; 441 }; 442 443 cpu0_opp_1152mhz: opp-1152000000 { 444 opp-hz = /bits/ 64 <1152000000>; 445 opp-peak-kBps = <2188000 27033600>; 446 }; 447 448 cpu0_opp_1325mhz: opp-1324800000 { 449 opp-hz = /bits/ 64 <1324800000>; 450 opp-peak-kBps = <2188000 33792000>; 451 }; 452 453 cpu0_opp_1517mhz: opp-1516800000 { 454 opp-hz = /bits/ 64 <1516800000>; 455 opp-peak-kBps = <3072000 38092800>; 456 }; 457 458 cpu0_opp_1651mhz: opp-1651200000 { 459 opp-hz = /bits/ 64 <1651200000>; 460 opp-peak-kBps = <3072000 41779200>; 461 }; 462 463 cpu0_opp_1805mhz: opp-1804800000 { 464 opp-hz = /bits/ 64 <1804800000>; 465 opp-peak-kBps = <4068000 48537600>; 466 }; 467 468 cpu0_opp_1958mhz: opp-1958400000 { 469 opp-hz = /bits/ 64 <1958400000>; 470 opp-peak-kBps = <4068000 48537600>; 471 }; 472 473 cpu0_opp_2016mhz: opp-2016000000 { 474 opp-hz = /bits/ 64 <2016000000>; 475 opp-peak-kBps = <6220000 48537600>; 476 }; 477 }; 478 479 cpu4_opp_table: cpu4-opp-table { 480 compatible = "operating-points-v2"; 481 opp-shared; 482 483 cpu4_opp_691mhz: opp-691200000 { 484 opp-hz = /bits/ 64 <691200000>; 485 opp-peak-kBps = <1804000 9600000>; 486 }; 487 488 cpu4_opp_941mhz: opp-940800000 { 489 opp-hz = /bits/ 64 <940800000>; 490 opp-peak-kBps = <2188000 17817600>; 491 }; 492 493 cpu4_opp_1229mhz: opp-1228800000 { 494 opp-hz = /bits/ 64 <1228800000>; 495 opp-peak-kBps = <4068000 24576000>; 496 }; 497 498 cpu4_opp_1344mhz: opp-1344000000 { 499 opp-hz = /bits/ 64 <1344000000>; 500 opp-peak-kBps = <4068000 24576000>; 501 }; 502 503 cpu4_opp_1517mhz: opp-1516800000 { 504 opp-hz = /bits/ 64 <1516800000>; 505 opp-peak-kBps = <4068000 24576000>; 506 }; 507 508 cpu4_opp_1651mhz: opp-1651200000 { 509 opp-hz = /bits/ 64 <1651200000>; 510 opp-peak-kBps = <6220000 38092800>; 511 }; 512 513 cpu4_opp_1901mhz: opp-1900800000 { 514 opp-hz = /bits/ 64 <1900800000>; 515 opp-peak-kBps = <6220000 44851200>; 516 }; 517 518 cpu4_opp_2054mhz: opp-2054400000 { 519 opp-hz = /bits/ 64 <2054400000>; 520 opp-peak-kBps = <6220000 44851200>; 521 }; 522 523 cpu4_opp_2112mhz: opp-2112000000 { 524 opp-hz = /bits/ 64 <2112000000>; 525 opp-peak-kBps = <6220000 44851200>; 526 }; 527 528 cpu4_opp_2131mhz: opp-2131200000 { 529 opp-hz = /bits/ 64 <2131200000>; 530 opp-peak-kBps = <6220000 44851200>; 531 }; 532 533 cpu4_opp_2208mhz: opp-2208000000 { 534 opp-hz = /bits/ 64 <2208000000>; 535 opp-peak-kBps = <6220000 44851200>; 536 }; 537 538 cpu4_opp_2400mhz: opp-2400000000 { 539 opp-hz = /bits/ 64 <2400000000>; 540 opp-peak-kBps = <8532000 48537600>; 541 }; 542 543 cpu4_opp_2611mhz: opp-2611200000 { 544 opp-hz = /bits/ 64 <2611200000>; 545 opp-peak-kBps = <8532000 48537600>; 546 }; 547 }; 548 549 cpu7_opp_table: cpu7-opp-table { 550 compatible = "operating-points-v2"; 551 opp-shared; 552 553 cpu7_opp_806mhz: opp-806400000 { 554 opp-hz = /bits/ 64 <806400000>; 555 opp-peak-kBps = <1804000 9600000>; 556 }; 557 558 cpu7_opp_1056mhz: opp-1056000000 { 559 opp-hz = /bits/ 64 <1056000000>; 560 opp-peak-kBps = <2188000 17817600>; 561 }; 562 563 cpu7_opp_1325mhz: opp-1324800000 { 564 opp-hz = /bits/ 64 <1324800000>; 565 opp-peak-kBps = <4068000 24576000>; 566 }; 567 568 cpu7_opp_1517mhz: opp-1516800000 { 569 opp-hz = /bits/ 64 <1516800000>; 570 opp-peak-kBps = <4068000 24576000>; 571 }; 572 573 cpu7_opp_1766mhz: opp-1766400000 { 574 opp-hz = /bits/ 64 <1766400000>; 575 opp-peak-kBps = <6220000 38092800>; 576 }; 577 578 cpu7_opp_1862mhz: opp-1862400000 { 579 opp-hz = /bits/ 64 <1862400000>; 580 opp-peak-kBps = <6220000 38092800>; 581 }; 582 583 cpu7_opp_2035mhz: opp-2035200000 { 584 opp-hz = /bits/ 64 <2035200000>; 585 opp-peak-kBps = <6220000 38092800>; 586 }; 587 588 cpu7_opp_2112mhz: opp-2112000000 { 589 opp-hz = /bits/ 64 <2112000000>; 590 opp-peak-kBps = <6220000 44851200>; 591 }; 592 593 cpu7_opp_2208mhz: opp-2208000000 { 594 opp-hz = /bits/ 64 <2208000000>; 595 opp-peak-kBps = <6220000 44851200>; 596 }; 597 598 cpu7_opp_2381mhz: opp-2380800000 { 599 opp-hz = /bits/ 64 <2380800000>; 600 opp-peak-kBps = <6832000 44851200>; 601 }; 602 603 cpu7_opp_2400mhz: opp-2400000000 { 604 opp-hz = /bits/ 64 <2400000000>; 605 opp-peak-kBps = <8532000 48537600>; 606 }; 607 608 cpu7_opp_2515mhz: opp-2515200000 { 609 opp-hz = /bits/ 64 <2515200000>; 610 opp-peak-kBps = <8532000 48537600>; 611 }; 612 613 cpu7_opp_2707mhz: opp-2707200000 { 614 opp-hz = /bits/ 64 <2707200000>; 615 opp-peak-kBps = <8532000 48537600>; 616 }; 617 618 cpu7_opp_3014mhz: opp-3014400000 { 619 opp-hz = /bits/ 64 <3014400000>; 620 opp-peak-kBps = <8532000 48537600>; 621 }; 622 }; 623 624 memory@80000000 { 625 device_type = "memory"; 626 /* We expect the bootloader to fill in the size */ 627 reg = <0 0x80000000 0 0>; 628 }; 629 630 firmware { 631 scm { 632 compatible = "qcom,scm-sc7280", "qcom,scm"; 633 }; 634 }; 635 636 clk_virt: interconnect { 637 compatible = "qcom,sc7280-clk-virt"; 638 #interconnect-cells = <2>; 639 qcom,bcm-voters = <&apps_bcm_voter>; 640 }; 641 642 smem { 643 compatible = "qcom,smem"; 644 memory-region = <&smem_mem>; 645 hwlocks = <&tcsr_mutex 3>; 646 }; 647 648 smp2p-adsp { 649 compatible = "qcom,smp2p"; 650 qcom,smem = <443>, <429>; 651 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 652 IPCC_MPROC_SIGNAL_SMP2P 653 IRQ_TYPE_EDGE_RISING>; 654 mboxes = <&ipcc IPCC_CLIENT_LPASS 655 IPCC_MPROC_SIGNAL_SMP2P>; 656 657 qcom,local-pid = <0>; 658 qcom,remote-pid = <2>; 659 660 adsp_smp2p_out: master-kernel { 661 qcom,entry-name = "master-kernel"; 662 #qcom,smem-state-cells = <1>; 663 }; 664 665 adsp_smp2p_in: slave-kernel { 666 qcom,entry-name = "slave-kernel"; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 }; 670 }; 671 672 smp2p-cdsp { 673 compatible = "qcom,smp2p"; 674 qcom,smem = <94>, <432>; 675 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 676 IPCC_MPROC_SIGNAL_SMP2P 677 IRQ_TYPE_EDGE_RISING>; 678 mboxes = <&ipcc IPCC_CLIENT_CDSP 679 IPCC_MPROC_SIGNAL_SMP2P>; 680 681 qcom,local-pid = <0>; 682 qcom,remote-pid = <5>; 683 684 cdsp_smp2p_out: master-kernel { 685 qcom,entry-name = "master-kernel"; 686 #qcom,smem-state-cells = <1>; 687 }; 688 689 cdsp_smp2p_in: slave-kernel { 690 qcom,entry-name = "slave-kernel"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 }; 695 696 smp2p-mpss { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <435>, <428>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_MPSS 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <1>; 707 708 modem_smp2p_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 modem_smp2p_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 719 ipa_smp2p_out: ipa-ap-to-modem { 720 qcom,entry-name = "ipa"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 ipa_smp2p_in: ipa-modem-to-ap { 725 qcom,entry-name = "ipa"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 }; 730 731 smp2p-wpss { 732 compatible = "qcom,smp2p"; 733 qcom,smem = <617>, <616>; 734 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 735 IPCC_MPROC_SIGNAL_SMP2P 736 IRQ_TYPE_EDGE_RISING>; 737 mboxes = <&ipcc IPCC_CLIENT_WPSS 738 IPCC_MPROC_SIGNAL_SMP2P>; 739 740 qcom,local-pid = <0>; 741 qcom,remote-pid = <13>; 742 743 wpss_smp2p_out: master-kernel { 744 qcom,entry-name = "master-kernel"; 745 #qcom,smem-state-cells = <1>; 746 }; 747 748 wpss_smp2p_in: slave-kernel { 749 qcom,entry-name = "slave-kernel"; 750 interrupt-controller; 751 #interrupt-cells = <2>; 752 }; 753 }; 754 755 pmu { 756 compatible = "arm,armv8-pmuv3"; 757 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 758 }; 759 760 psci { 761 compatible = "arm,psci-1.0"; 762 method = "smc"; 763 }; 764 765 qspi_opp_table: qspi-opp-table { 766 compatible = "operating-points-v2"; 767 768 opp-75000000 { 769 opp-hz = /bits/ 64 <75000000>; 770 required-opps = <&rpmhpd_opp_low_svs>; 771 }; 772 773 opp-150000000 { 774 opp-hz = /bits/ 64 <150000000>; 775 required-opps = <&rpmhpd_opp_svs>; 776 }; 777 778 opp-200000000 { 779 opp-hz = /bits/ 64 <200000000>; 780 required-opps = <&rpmhpd_opp_svs_l1>; 781 }; 782 783 opp-300000000 { 784 opp-hz = /bits/ 64 <300000000>; 785 required-opps = <&rpmhpd_opp_nom>; 786 }; 787 }; 788 789 qup_opp_table: qup-opp-table { 790 compatible = "operating-points-v2"; 791 792 opp-75000000 { 793 opp-hz = /bits/ 64 <75000000>; 794 required-opps = <&rpmhpd_opp_low_svs>; 795 }; 796 797 opp-100000000 { 798 opp-hz = /bits/ 64 <100000000>; 799 required-opps = <&rpmhpd_opp_svs>; 800 }; 801 802 opp-128000000 { 803 opp-hz = /bits/ 64 <128000000>; 804 required-opps = <&rpmhpd_opp_nom>; 805 }; 806 }; 807 808 soc: soc@0 { 809 #address-cells = <2>; 810 #size-cells = <2>; 811 ranges = <0 0 0 0 0x10 0>; 812 dma-ranges = <0 0 0 0 0x10 0>; 813 compatible = "simple-bus"; 814 815 gcc: clock-controller@100000 { 816 compatible = "qcom,gcc-sc7280"; 817 reg = <0 0x00100000 0 0x1f0000>; 818 clocks = <&rpmhcc RPMH_CXO_CLK>, 819 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 820 <0>, <&pcie1_lane 0>, 821 <0>, <0>, <0>, <0>; 822 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 823 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 824 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 825 "ufs_phy_tx_symbol_0_clk", 826 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 827 #clock-cells = <1>; 828 #reset-cells = <1>; 829 #power-domain-cells = <1>; 830 }; 831 832 ipcc: mailbox@408000 { 833 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 834 reg = <0 0x00408000 0 0x1000>; 835 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-controller; 837 #interrupt-cells = <3>; 838 #mbox-cells = <2>; 839 }; 840 841 qfprom: efuse@784000 { 842 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 843 reg = <0 0x00784000 0 0xa20>, 844 <0 0x00780000 0 0xa20>, 845 <0 0x00782000 0 0x120>, 846 <0 0x00786000 0 0x1fff>; 847 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 848 clock-names = "core"; 849 power-domains = <&rpmhpd SC7280_MX>; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 }; 853 854 sdhc_1: sdhci@7c4000 { 855 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 856 pinctrl-names = "default", "sleep"; 857 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 858 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 859 status = "disabled"; 860 861 reg = <0 0x007c4000 0 0x1000>, 862 <0 0x007c5000 0 0x1000>; 863 reg-names = "hc", "cqhci"; 864 865 iommus = <&apps_smmu 0xc0 0x0>; 866 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "hc_irq", "pwr_irq"; 869 870 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 871 <&gcc GCC_SDCC1_AHB_CLK>, 872 <&rpmhcc RPMH_CXO_CLK>; 873 clock-names = "core", "iface", "xo"; 874 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 875 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 876 interconnect-names = "sdhc-ddr","cpu-sdhc"; 877 power-domains = <&rpmhpd SC7280_CX>; 878 operating-points-v2 = <&sdhc1_opp_table>; 879 880 bus-width = <8>; 881 supports-cqe; 882 883 qcom,dll-config = <0x0007642c>; 884 qcom,ddr-config = <0x80040868>; 885 886 mmc-ddr-1_8v; 887 mmc-hs200-1_8v; 888 mmc-hs400-1_8v; 889 mmc-hs400-enhanced-strobe; 890 891 resets = <&gcc GCC_SDCC1_BCR>; 892 893 sdhc1_opp_table: opp-table { 894 compatible = "operating-points-v2"; 895 896 opp-100000000 { 897 opp-hz = /bits/ 64 <100000000>; 898 required-opps = <&rpmhpd_opp_low_svs>; 899 opp-peak-kBps = <1800000 400000>; 900 opp-avg-kBps = <100000 0>; 901 }; 902 903 opp-384000000 { 904 opp-hz = /bits/ 64 <384000000>; 905 required-opps = <&rpmhpd_opp_nom>; 906 opp-peak-kBps = <5400000 1600000>; 907 opp-avg-kBps = <390000 0>; 908 }; 909 }; 910 911 }; 912 913 qupv3_id_0: geniqup@9c0000 { 914 compatible = "qcom,geni-se-qup"; 915 reg = <0 0x009c0000 0 0x2000>; 916 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 917 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 918 clock-names = "m-ahb", "s-ahb"; 919 #address-cells = <2>; 920 #size-cells = <2>; 921 ranges; 922 iommus = <&apps_smmu 0x123 0x0>; 923 status = "disabled"; 924 925 i2c0: i2c@980000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0 0x00980000 0 0x4000>; 928 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 929 clock-names = "se"; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_i2c0_data_clk>; 932 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 937 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", 939 "qup-memory"; 940 status = "disabled"; 941 }; 942 943 spi0: spi@980000 { 944 compatible = "qcom,geni-spi"; 945 reg = <0 0x00980000 0 0x4000>; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 947 clock-names = "se"; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 950 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 power-domains = <&rpmhpd SC7280_CX>; 954 operating-points-v2 = <&qup_opp_table>; 955 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 956 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 957 interconnect-names = "qup-core", "qup-config"; 958 status = "disabled"; 959 }; 960 961 uart0: serial@980000 { 962 compatible = "qcom,geni-uart"; 963 reg = <0 0x00980000 0 0x4000>; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 965 clock-names = "se"; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 968 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 969 power-domains = <&rpmhpd SC7280_CX>; 970 operating-points-v2 = <&qup_opp_table>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 972 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 973 interconnect-names = "qup-core", "qup-config"; 974 status = "disabled"; 975 }; 976 977 i2c1: i2c@984000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00984000 0 0x4000>; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 981 clock-names = "se"; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_i2c1_data_clk>; 984 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 989 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", 991 "qup-memory"; 992 status = "disabled"; 993 }; 994 995 spi1: spi@984000 { 996 compatible = "qcom,geni-spi"; 997 reg = <0 0x00984000 0 0x4000>; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 999 clock-names = "se"; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1002 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 power-domains = <&rpmhpd SC7280_CX>; 1006 operating-points-v2 = <&qup_opp_table>; 1007 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1008 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1009 interconnect-names = "qup-core", "qup-config"; 1010 status = "disabled"; 1011 }; 1012 1013 uart1: serial@984000 { 1014 compatible = "qcom,geni-uart"; 1015 reg = <0 0x00984000 0 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1017 clock-names = "se"; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1020 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1021 power-domains = <&rpmhpd SC7280_CX>; 1022 operating-points-v2 = <&qup_opp_table>; 1023 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1024 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1025 interconnect-names = "qup-core", "qup-config"; 1026 status = "disabled"; 1027 }; 1028 1029 i2c2: i2c@988000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0 0x00988000 0 0x4000>; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1033 clock-names = "se"; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_i2c2_data_clk>; 1036 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1040 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1041 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1042 interconnect-names = "qup-core", "qup-config", 1043 "qup-memory"; 1044 status = "disabled"; 1045 }; 1046 1047 spi2: spi@988000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0 0x00988000 0 0x4000>; 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1051 clock-names = "se"; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1054 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 power-domains = <&rpmhpd SC7280_CX>; 1058 operating-points-v2 = <&qup_opp_table>; 1059 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1060 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1061 interconnect-names = "qup-core", "qup-config"; 1062 status = "disabled"; 1063 }; 1064 1065 uart2: serial@988000 { 1066 compatible = "qcom,geni-uart"; 1067 reg = <0 0x00988000 0 0x4000>; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1069 clock-names = "se"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1072 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1073 power-domains = <&rpmhpd SC7280_CX>; 1074 operating-points-v2 = <&qup_opp_table>; 1075 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1076 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1077 interconnect-names = "qup-core", "qup-config"; 1078 status = "disabled"; 1079 }; 1080 1081 i2c3: i2c@98c000 { 1082 compatible = "qcom,geni-i2c"; 1083 reg = <0 0x0098c000 0 0x4000>; 1084 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1085 clock-names = "se"; 1086 pinctrl-names = "default"; 1087 pinctrl-0 = <&qup_i2c3_data_clk>; 1088 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1092 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1093 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1094 interconnect-names = "qup-core", "qup-config", 1095 "qup-memory"; 1096 status = "disabled"; 1097 }; 1098 1099 spi3: spi@98c000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0 0x0098c000 0 0x4000>; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1103 clock-names = "se"; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1106 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 power-domains = <&rpmhpd SC7280_CX>; 1110 operating-points-v2 = <&qup_opp_table>; 1111 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1112 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1113 interconnect-names = "qup-core", "qup-config"; 1114 status = "disabled"; 1115 }; 1116 1117 uart3: serial@98c000 { 1118 compatible = "qcom,geni-uart"; 1119 reg = <0 0x0098c000 0 0x4000>; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1121 clock-names = "se"; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1124 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1125 power-domains = <&rpmhpd SC7280_CX>; 1126 operating-points-v2 = <&qup_opp_table>; 1127 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1128 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1129 interconnect-names = "qup-core", "qup-config"; 1130 status = "disabled"; 1131 }; 1132 1133 i2c4: i2c@990000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0 0x00990000 0 0x4000>; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1137 clock-names = "se"; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_i2c4_data_clk>; 1140 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1145 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1146 interconnect-names = "qup-core", "qup-config", 1147 "qup-memory"; 1148 status = "disabled"; 1149 }; 1150 1151 spi4: spi@990000 { 1152 compatible = "qcom,geni-spi"; 1153 reg = <0 0x00990000 0 0x4000>; 1154 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1155 clock-names = "se"; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1158 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 power-domains = <&rpmhpd SC7280_CX>; 1162 operating-points-v2 = <&qup_opp_table>; 1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1164 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1165 interconnect-names = "qup-core", "qup-config"; 1166 status = "disabled"; 1167 }; 1168 1169 uart4: serial@990000 { 1170 compatible = "qcom,geni-uart"; 1171 reg = <0 0x00990000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1176 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC7280_CX>; 1178 operating-points-v2 = <&qup_opp_table>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1181 interconnect-names = "qup-core", "qup-config"; 1182 status = "disabled"; 1183 }; 1184 1185 i2c5: i2c@994000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x00994000 0 0x4000>; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1189 clock-names = "se"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&qup_i2c5_data_clk>; 1192 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1196 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1197 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1198 interconnect-names = "qup-core", "qup-config", 1199 "qup-memory"; 1200 status = "disabled"; 1201 }; 1202 1203 spi5: spi@994000 { 1204 compatible = "qcom,geni-spi"; 1205 reg = <0 0x00994000 0 0x4000>; 1206 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1207 clock-names = "se"; 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1210 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 power-domains = <&rpmhpd SC7280_CX>; 1214 operating-points-v2 = <&qup_opp_table>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1216 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1217 interconnect-names = "qup-core", "qup-config"; 1218 status = "disabled"; 1219 }; 1220 1221 uart5: serial@994000 { 1222 compatible = "qcom,geni-uart"; 1223 reg = <0 0x00994000 0 0x4000>; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1225 clock-names = "se"; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1228 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1229 power-domains = <&rpmhpd SC7280_CX>; 1230 operating-points-v2 = <&qup_opp_table>; 1231 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1232 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1233 interconnect-names = "qup-core", "qup-config"; 1234 status = "disabled"; 1235 }; 1236 1237 i2c6: i2c@998000 { 1238 compatible = "qcom,geni-i2c"; 1239 reg = <0 0x00998000 0 0x4000>; 1240 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1241 clock-names = "se"; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&qup_i2c6_data_clk>; 1244 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1248 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1249 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1250 interconnect-names = "qup-core", "qup-config", 1251 "qup-memory"; 1252 status = "disabled"; 1253 }; 1254 1255 spi6: spi@998000 { 1256 compatible = "qcom,geni-spi"; 1257 reg = <0 0x00998000 0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1259 clock-names = "se"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1262 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 power-domains = <&rpmhpd SC7280_CX>; 1266 operating-points-v2 = <&qup_opp_table>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 status = "disabled"; 1271 }; 1272 1273 uart6: serial@998000 { 1274 compatible = "qcom,geni-uart"; 1275 reg = <0 0x00998000 0 0x4000>; 1276 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1277 clock-names = "se"; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1280 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1281 power-domains = <&rpmhpd SC7280_CX>; 1282 operating-points-v2 = <&qup_opp_table>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1284 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1285 interconnect-names = "qup-core", "qup-config"; 1286 status = "disabled"; 1287 }; 1288 1289 i2c7: i2c@99c000 { 1290 compatible = "qcom,geni-i2c"; 1291 reg = <0 0x0099c000 0 0x4000>; 1292 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1293 clock-names = "se"; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_i2c7_data_clk>; 1296 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1300 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1301 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1302 interconnect-names = "qup-core", "qup-config", 1303 "qup-memory"; 1304 status = "disabled"; 1305 }; 1306 1307 spi7: spi@99c000 { 1308 compatible = "qcom,geni-spi"; 1309 reg = <0 0x0099c000 0 0x4000>; 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1311 clock-names = "se"; 1312 pinctrl-names = "default"; 1313 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1314 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 power-domains = <&rpmhpd SC7280_CX>; 1318 operating-points-v2 = <&qup_opp_table>; 1319 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1320 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1321 interconnect-names = "qup-core", "qup-config"; 1322 status = "disabled"; 1323 }; 1324 1325 uart7: serial@99c000 { 1326 compatible = "qcom,geni-uart"; 1327 reg = <0 0x0099c000 0 0x4000>; 1328 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1329 clock-names = "se"; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1332 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1333 power-domains = <&rpmhpd SC7280_CX>; 1334 operating-points-v2 = <&qup_opp_table>; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1336 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1337 interconnect-names = "qup-core", "qup-config"; 1338 status = "disabled"; 1339 }; 1340 }; 1341 1342 qupv3_id_1: geniqup@ac0000 { 1343 compatible = "qcom,geni-se-qup"; 1344 reg = <0 0x00ac0000 0 0x2000>; 1345 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1346 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1347 clock-names = "m-ahb", "s-ahb"; 1348 #address-cells = <2>; 1349 #size-cells = <2>; 1350 ranges; 1351 iommus = <&apps_smmu 0x43 0x0>; 1352 status = "disabled"; 1353 1354 i2c8: i2c@a80000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00a80000 0 0x4000>; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1358 clock-names = "se"; 1359 pinctrl-names = "default"; 1360 pinctrl-0 = <&qup_i2c8_data_clk>; 1361 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1365 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1366 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1367 interconnect-names = "qup-core", "qup-config", 1368 "qup-memory"; 1369 status = "disabled"; 1370 }; 1371 1372 spi8: spi@a80000 { 1373 compatible = "qcom,geni-spi"; 1374 reg = <0 0x00a80000 0 0x4000>; 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1376 clock-names = "se"; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1379 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 power-domains = <&rpmhpd SC7280_CX>; 1383 operating-points-v2 = <&qup_opp_table>; 1384 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1385 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1386 interconnect-names = "qup-core", "qup-config"; 1387 status = "disabled"; 1388 }; 1389 1390 uart8: serial@a80000 { 1391 compatible = "qcom,geni-uart"; 1392 reg = <0 0x00a80000 0 0x4000>; 1393 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1394 clock-names = "se"; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1397 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1398 power-domains = <&rpmhpd SC7280_CX>; 1399 operating-points-v2 = <&qup_opp_table>; 1400 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1401 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1402 interconnect-names = "qup-core", "qup-config"; 1403 status = "disabled"; 1404 }; 1405 1406 i2c9: i2c@a84000 { 1407 compatible = "qcom,geni-i2c"; 1408 reg = <0 0x00a84000 0 0x4000>; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1410 clock-names = "se"; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_i2c9_data_clk>; 1413 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1418 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1419 interconnect-names = "qup-core", "qup-config", 1420 "qup-memory"; 1421 status = "disabled"; 1422 }; 1423 1424 spi9: spi@a84000 { 1425 compatible = "qcom,geni-spi"; 1426 reg = <0 0x00a84000 0 0x4000>; 1427 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1428 clock-names = "se"; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1431 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 power-domains = <&rpmhpd SC7280_CX>; 1435 operating-points-v2 = <&qup_opp_table>; 1436 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1437 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1438 interconnect-names = "qup-core", "qup-config"; 1439 status = "disabled"; 1440 }; 1441 1442 uart9: serial@a84000 { 1443 compatible = "qcom,geni-uart"; 1444 reg = <0 0x00a84000 0 0x4000>; 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1446 clock-names = "se"; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1449 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1450 power-domains = <&rpmhpd SC7280_CX>; 1451 operating-points-v2 = <&qup_opp_table>; 1452 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1453 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1454 interconnect-names = "qup-core", "qup-config"; 1455 status = "disabled"; 1456 }; 1457 1458 i2c10: i2c@a88000 { 1459 compatible = "qcom,geni-i2c"; 1460 reg = <0 0x00a88000 0 0x4000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1462 clock-names = "se"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_i2c10_data_clk>; 1465 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1469 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1470 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1471 interconnect-names = "qup-core", "qup-config", 1472 "qup-memory"; 1473 status = "disabled"; 1474 }; 1475 1476 spi10: spi@a88000 { 1477 compatible = "qcom,geni-spi"; 1478 reg = <0 0x00a88000 0 0x4000>; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1480 clock-names = "se"; 1481 pinctrl-names = "default"; 1482 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1483 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 power-domains = <&rpmhpd SC7280_CX>; 1487 operating-points-v2 = <&qup_opp_table>; 1488 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1489 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1490 interconnect-names = "qup-core", "qup-config"; 1491 status = "disabled"; 1492 }; 1493 1494 uart10: serial@a88000 { 1495 compatible = "qcom,geni-uart"; 1496 reg = <0 0x00a88000 0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1498 clock-names = "se"; 1499 pinctrl-names = "default"; 1500 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1501 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1502 power-domains = <&rpmhpd SC7280_CX>; 1503 operating-points-v2 = <&qup_opp_table>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1506 interconnect-names = "qup-core", "qup-config"; 1507 status = "disabled"; 1508 }; 1509 1510 i2c11: i2c@a8c000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0 0x00a8c000 0 0x4000>; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1514 clock-names = "se"; 1515 pinctrl-names = "default"; 1516 pinctrl-0 = <&qup_i2c11_data_clk>; 1517 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1523 interconnect-names = "qup-core", "qup-config", 1524 "qup-memory"; 1525 status = "disabled"; 1526 }; 1527 1528 spi11: spi@a8c000 { 1529 compatible = "qcom,geni-spi"; 1530 reg = <0 0x00a8c000 0 0x4000>; 1531 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1532 clock-names = "se"; 1533 pinctrl-names = "default"; 1534 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1535 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 power-domains = <&rpmhpd SC7280_CX>; 1539 operating-points-v2 = <&qup_opp_table>; 1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1541 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1542 interconnect-names = "qup-core", "qup-config"; 1543 status = "disabled"; 1544 }; 1545 1546 uart11: serial@a8c000 { 1547 compatible = "qcom,geni-uart"; 1548 reg = <0 0x00a8c000 0 0x4000>; 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1550 clock-names = "se"; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1553 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1554 power-domains = <&rpmhpd SC7280_CX>; 1555 operating-points-v2 = <&qup_opp_table>; 1556 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1557 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 status = "disabled"; 1560 }; 1561 1562 i2c12: i2c@a90000 { 1563 compatible = "qcom,geni-i2c"; 1564 reg = <0 0x00a90000 0 0x4000>; 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1566 clock-names = "se"; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_i2c12_data_clk>; 1569 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1574 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1575 interconnect-names = "qup-core", "qup-config", 1576 "qup-memory"; 1577 status = "disabled"; 1578 }; 1579 1580 spi12: spi@a90000 { 1581 compatible = "qcom,geni-spi"; 1582 reg = <0 0x00a90000 0 0x4000>; 1583 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1584 clock-names = "se"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1587 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 power-domains = <&rpmhpd SC7280_CX>; 1591 operating-points-v2 = <&qup_opp_table>; 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1593 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1594 interconnect-names = "qup-core", "qup-config"; 1595 status = "disabled"; 1596 }; 1597 1598 uart12: serial@a90000 { 1599 compatible = "qcom,geni-uart"; 1600 reg = <0 0x00a90000 0 0x4000>; 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1602 clock-names = "se"; 1603 pinctrl-names = "default"; 1604 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1605 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1606 power-domains = <&rpmhpd SC7280_CX>; 1607 operating-points-v2 = <&qup_opp_table>; 1608 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1609 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1610 interconnect-names = "qup-core", "qup-config"; 1611 status = "disabled"; 1612 }; 1613 1614 i2c13: i2c@a94000 { 1615 compatible = "qcom,geni-i2c"; 1616 reg = <0 0x00a94000 0 0x4000>; 1617 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1618 clock-names = "se"; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&qup_i2c13_data_clk>; 1621 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1625 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1626 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1627 interconnect-names = "qup-core", "qup-config", 1628 "qup-memory"; 1629 status = "disabled"; 1630 }; 1631 1632 spi13: spi@a94000 { 1633 compatible = "qcom,geni-spi"; 1634 reg = <0 0x00a94000 0 0x4000>; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1636 clock-names = "se"; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1639 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 power-domains = <&rpmhpd SC7280_CX>; 1643 operating-points-v2 = <&qup_opp_table>; 1644 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1645 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1646 interconnect-names = "qup-core", "qup-config"; 1647 status = "disabled"; 1648 }; 1649 1650 uart13: serial@a94000 { 1651 compatible = "qcom,geni-uart"; 1652 reg = <0 0x00a94000 0 0x4000>; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1654 clock-names = "se"; 1655 pinctrl-names = "default"; 1656 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1657 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1658 power-domains = <&rpmhpd SC7280_CX>; 1659 operating-points-v2 = <&qup_opp_table>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1662 interconnect-names = "qup-core", "qup-config"; 1663 status = "disabled"; 1664 }; 1665 1666 i2c14: i2c@a98000 { 1667 compatible = "qcom,geni-i2c"; 1668 reg = <0 0x00a98000 0 0x4000>; 1669 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1670 clock-names = "se"; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_i2c14_data_clk>; 1673 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1677 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1678 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1679 interconnect-names = "qup-core", "qup-config", 1680 "qup-memory"; 1681 status = "disabled"; 1682 }; 1683 1684 spi14: spi@a98000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0 0x00a98000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1691 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 power-domains = <&rpmhpd SC7280_CX>; 1695 operating-points-v2 = <&qup_opp_table>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1698 interconnect-names = "qup-core", "qup-config"; 1699 status = "disabled"; 1700 }; 1701 1702 uart14: serial@a98000 { 1703 compatible = "qcom,geni-uart"; 1704 reg = <0 0x00a98000 0 0x4000>; 1705 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1706 clock-names = "se"; 1707 pinctrl-names = "default"; 1708 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1709 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1710 power-domains = <&rpmhpd SC7280_CX>; 1711 operating-points-v2 = <&qup_opp_table>; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1713 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1714 interconnect-names = "qup-core", "qup-config"; 1715 status = "disabled"; 1716 }; 1717 1718 i2c15: i2c@a9c000 { 1719 compatible = "qcom,geni-i2c"; 1720 reg = <0 0x00a9c000 0 0x4000>; 1721 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1722 clock-names = "se"; 1723 pinctrl-names = "default"; 1724 pinctrl-0 = <&qup_i2c15_data_clk>; 1725 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1726 #address-cells = <1>; 1727 #size-cells = <0>; 1728 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1729 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1730 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1731 interconnect-names = "qup-core", "qup-config", 1732 "qup-memory"; 1733 status = "disabled"; 1734 }; 1735 1736 spi15: spi@a9c000 { 1737 compatible = "qcom,geni-spi"; 1738 reg = <0 0x00a9c000 0 0x4000>; 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1740 clock-names = "se"; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1743 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1744 #address-cells = <1>; 1745 #size-cells = <0>; 1746 power-domains = <&rpmhpd SC7280_CX>; 1747 operating-points-v2 = <&qup_opp_table>; 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1749 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1750 interconnect-names = "qup-core", "qup-config"; 1751 status = "disabled"; 1752 }; 1753 1754 uart15: serial@a9c000 { 1755 compatible = "qcom,geni-uart"; 1756 reg = <0 0x00a9c000 0 0x4000>; 1757 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1758 clock-names = "se"; 1759 pinctrl-names = "default"; 1760 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1761 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1762 power-domains = <&rpmhpd SC7280_CX>; 1763 operating-points-v2 = <&qup_opp_table>; 1764 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1765 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1766 interconnect-names = "qup-core", "qup-config"; 1767 status = "disabled"; 1768 }; 1769 }; 1770 1771 cnoc2: interconnect@1500000 { 1772 reg = <0 0x01500000 0 0x1000>; 1773 compatible = "qcom,sc7280-cnoc2"; 1774 #interconnect-cells = <2>; 1775 qcom,bcm-voters = <&apps_bcm_voter>; 1776 }; 1777 1778 cnoc3: interconnect@1502000 { 1779 reg = <0 0x01502000 0 0x1000>; 1780 compatible = "qcom,sc7280-cnoc3"; 1781 #interconnect-cells = <2>; 1782 qcom,bcm-voters = <&apps_bcm_voter>; 1783 }; 1784 1785 mc_virt: interconnect@1580000 { 1786 reg = <0 0x01580000 0 0x4>; 1787 compatible = "qcom,sc7280-mc-virt"; 1788 #interconnect-cells = <2>; 1789 qcom,bcm-voters = <&apps_bcm_voter>; 1790 }; 1791 1792 system_noc: interconnect@1680000 { 1793 reg = <0 0x01680000 0 0x15480>; 1794 compatible = "qcom,sc7280-system-noc"; 1795 #interconnect-cells = <2>; 1796 qcom,bcm-voters = <&apps_bcm_voter>; 1797 }; 1798 1799 aggre1_noc: interconnect@16e0000 { 1800 compatible = "qcom,sc7280-aggre1-noc"; 1801 reg = <0 0x016e0000 0 0x1c080>; 1802 #interconnect-cells = <2>; 1803 qcom,bcm-voters = <&apps_bcm_voter>; 1804 }; 1805 1806 aggre2_noc: interconnect@1700000 { 1807 reg = <0 0x01700000 0 0x2b080>; 1808 compatible = "qcom,sc7280-aggre2-noc"; 1809 #interconnect-cells = <2>; 1810 qcom,bcm-voters = <&apps_bcm_voter>; 1811 }; 1812 1813 mmss_noc: interconnect@1740000 { 1814 reg = <0 0x01740000 0 0x1e080>; 1815 compatible = "qcom,sc7280-mmss-noc"; 1816 #interconnect-cells = <2>; 1817 qcom,bcm-voters = <&apps_bcm_voter>; 1818 }; 1819 1820 wifi: wifi@17a10040 { 1821 compatible = "qcom,wcn6750-wifi"; 1822 reg = <0 0x17a10040 0 0x0>; 1823 iommus = <&apps_smmu 0x1c00 0x1>; 1824 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1825 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1826 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1827 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1828 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1829 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1830 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1831 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1832 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1833 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1834 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1835 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1836 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1837 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1838 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1839 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1840 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1841 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1842 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1843 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1844 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1845 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1846 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1847 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1848 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1849 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1850 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1851 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 1852 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 1853 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 1854 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 1855 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 1856 qcom,rproc = <&remoteproc_wpss>; 1857 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 1858 status = "disabled"; 1859 }; 1860 1861 pcie1: pci@1c08000 { 1862 compatible = "qcom,pcie-sc7280"; 1863 reg = <0 0x01c08000 0 0x3000>, 1864 <0 0x40000000 0 0xf1d>, 1865 <0 0x40000f20 0 0xa8>, 1866 <0 0x40001000 0 0x1000>, 1867 <0 0x40100000 0 0x100000>; 1868 1869 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1870 device_type = "pci"; 1871 linux,pci-domain = <1>; 1872 bus-range = <0x00 0xff>; 1873 num-lanes = <2>; 1874 1875 #address-cells = <3>; 1876 #size-cells = <2>; 1877 1878 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1879 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1880 1881 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1882 interrupt-names = "msi"; 1883 #interrupt-cells = <1>; 1884 interrupt-map-mask = <0 0 0 0x7>; 1885 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 1886 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 1887 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 1888 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 1889 1890 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1891 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1892 <&pcie1_lane 0>, 1893 <&rpmhcc RPMH_CXO_CLK>, 1894 <&gcc GCC_PCIE_1_AUX_CLK>, 1895 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1896 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1897 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1898 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1899 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1900 <&gcc GCC_DDRSS_PCIE_SF_CLK>; 1901 1902 clock-names = "pipe", 1903 "pipe_mux", 1904 "phy_pipe", 1905 "ref", 1906 "aux", 1907 "cfg", 1908 "bus_master", 1909 "bus_slave", 1910 "slave_q2a", 1911 "tbu", 1912 "ddrss_sf_tbu"; 1913 1914 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1915 assigned-clock-rates = <19200000>; 1916 1917 resets = <&gcc GCC_PCIE_1_BCR>; 1918 reset-names = "pci"; 1919 1920 power-domains = <&gcc GCC_PCIE_1_GDSC>; 1921 1922 phys = <&pcie1_lane>; 1923 phy-names = "pciephy"; 1924 1925 pinctrl-names = "default"; 1926 pinctrl-0 = <&pcie1_clkreq_n>; 1927 1928 iommus = <&apps_smmu 0x1c80 0x1>; 1929 1930 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1931 <0x100 &apps_smmu 0x1c81 0x1>; 1932 1933 status = "disabled"; 1934 }; 1935 1936 pcie1_phy: phy@1c0e000 { 1937 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1938 reg = <0 0x01c0e000 0 0x1c0>; 1939 #address-cells = <2>; 1940 #size-cells = <2>; 1941 ranges; 1942 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1943 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1944 <&gcc GCC_PCIE_CLKREF_EN>, 1945 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1946 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1947 1948 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1949 reset-names = "phy"; 1950 1951 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1952 assigned-clock-rates = <100000000>; 1953 1954 status = "disabled"; 1955 1956 pcie1_lane: phy@1c0e200 { 1957 reg = <0 0x01c0e200 0 0x170>, 1958 <0 0x01c0e400 0 0x200>, 1959 <0 0x01c0ea00 0 0x1f0>, 1960 <0 0x01c0e600 0 0x170>, 1961 <0 0x01c0e800 0 0x200>, 1962 <0 0x01c0ee00 0 0xf4>; 1963 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1964 clock-names = "pipe0"; 1965 1966 #phy-cells = <0>; 1967 #clock-cells = <1>; 1968 clock-output-names = "pcie_1_pipe_clk"; 1969 }; 1970 }; 1971 1972 ipa: ipa@1e40000 { 1973 compatible = "qcom,sc7280-ipa"; 1974 1975 iommus = <&apps_smmu 0x480 0x0>, 1976 <&apps_smmu 0x482 0x0>; 1977 reg = <0 0x1e40000 0 0x8000>, 1978 <0 0x1e50000 0 0x4ad0>, 1979 <0 0x1e04000 0 0x23000>; 1980 reg-names = "ipa-reg", 1981 "ipa-shared", 1982 "gsi"; 1983 1984 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1985 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1986 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1987 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1988 interrupt-names = "ipa", 1989 "gsi", 1990 "ipa-clock-query", 1991 "ipa-setup-ready"; 1992 1993 clocks = <&rpmhcc RPMH_IPA_CLK>; 1994 clock-names = "core"; 1995 1996 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1997 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1998 interconnect-names = "memory", 1999 "config"; 2000 2001 qcom,qmp = <&aoss_qmp>; 2002 2003 qcom,smem-states = <&ipa_smp2p_out 0>, 2004 <&ipa_smp2p_out 1>; 2005 qcom,smem-state-names = "ipa-clock-enabled-valid", 2006 "ipa-clock-enabled"; 2007 2008 status = "disabled"; 2009 }; 2010 2011 tcsr_mutex: hwlock@1f40000 { 2012 compatible = "qcom,tcsr-mutex", "syscon"; 2013 reg = <0 0x01f40000 0 0x40000>; 2014 #hwlock-cells = <1>; 2015 }; 2016 2017 tcsr: syscon@1fc0000 { 2018 compatible = "qcom,sc7280-tcsr", "syscon"; 2019 reg = <0 0x01fc0000 0 0x30000>; 2020 }; 2021 2022 lpasscc: lpasscc@3000000 { 2023 compatible = "qcom,sc7280-lpasscc"; 2024 reg = <0 0x03000000 0 0x40>, 2025 <0 0x03c04000 0 0x4>, 2026 <0 0x03389000 0 0x24>; 2027 reg-names = "qdsp6ss", "top_cc", "cc"; 2028 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2029 clock-names = "iface"; 2030 #clock-cells = <1>; 2031 }; 2032 2033 lpass_audiocc: clock-controller@3300000 { 2034 compatible = "qcom,sc7280-lpassaudiocc"; 2035 reg = <0 0x03300000 0 0x30000>; 2036 clocks = <&rpmhcc RPMH_CXO_CLK>, 2037 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2038 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2039 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2040 #clock-cells = <1>; 2041 #power-domain-cells = <1>; 2042 }; 2043 2044 lpass_aon: clock-controller@3380000 { 2045 compatible = "qcom,sc7280-lpassaoncc"; 2046 reg = <0 0x03380000 0 0x30000>; 2047 clocks = <&rpmhcc RPMH_CXO_CLK>, 2048 <&rpmhcc RPMH_CXO_CLK_A>, 2049 <&lpasscore LPASS_CORE_CC_CORE_CLK>; 2050 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2051 #clock-cells = <1>; 2052 #power-domain-cells = <1>; 2053 }; 2054 2055 lpasscore: clock-controller@3900000 { 2056 compatible = "qcom,sc7280-lpasscorecc"; 2057 reg = <0 0x03900000 0 0x50000>; 2058 clocks = <&rpmhcc RPMH_CXO_CLK>; 2059 clock-names = "bi_tcxo"; 2060 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2061 #clock-cells = <1>; 2062 #power-domain-cells = <1>; 2063 }; 2064 2065 lpass_hm: clock-controller@3c00000 { 2066 compatible = "qcom,sc7280-lpasshm"; 2067 reg = <0 0x3c00000 0 0x28>; 2068 clocks = <&rpmhcc RPMH_CXO_CLK>; 2069 clock-names = "bi_tcxo"; 2070 #clock-cells = <1>; 2071 #power-domain-cells = <1>; 2072 }; 2073 2074 lpass_ag_noc: interconnect@3c40000 { 2075 reg = <0 0x03c40000 0 0xf080>; 2076 compatible = "qcom,sc7280-lpass-ag-noc"; 2077 #interconnect-cells = <2>; 2078 qcom,bcm-voters = <&apps_bcm_voter>; 2079 }; 2080 2081 gpu: gpu@3d00000 { 2082 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2083 reg = <0 0x03d00000 0 0x40000>, 2084 <0 0x03d9e000 0 0x1000>, 2085 <0 0x03d61000 0 0x800>; 2086 reg-names = "kgsl_3d0_reg_memory", 2087 "cx_mem", 2088 "cx_dbgc"; 2089 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2090 iommus = <&adreno_smmu 0 0x401>; 2091 operating-points-v2 = <&gpu_opp_table>; 2092 qcom,gmu = <&gmu>; 2093 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2094 interconnect-names = "gfx-mem"; 2095 #cooling-cells = <2>; 2096 2097 gpu_opp_table: opp-table { 2098 compatible = "operating-points-v2"; 2099 2100 opp-315000000 { 2101 opp-hz = /bits/ 64 <315000000>; 2102 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2103 opp-peak-kBps = <1804000>; 2104 }; 2105 2106 opp-450000000 { 2107 opp-hz = /bits/ 64 <450000000>; 2108 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2109 opp-peak-kBps = <4068000>; 2110 }; 2111 2112 opp-550000000 { 2113 opp-hz = /bits/ 64 <550000000>; 2114 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2115 opp-peak-kBps = <6832000>; 2116 }; 2117 }; 2118 }; 2119 2120 gmu: gmu@3d6a000 { 2121 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2122 reg = <0 0x03d6a000 0 0x34000>, 2123 <0 0x3de0000 0 0x10000>, 2124 <0 0x0b290000 0 0x10000>; 2125 reg-names = "gmu", "rscc", "gmu_pdc"; 2126 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2128 interrupt-names = "hfi", "gmu"; 2129 clocks = <&gpucc 5>, 2130 <&gpucc 8>, 2131 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2132 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2133 <&gpucc 2>, 2134 <&gpucc 15>, 2135 <&gpucc 11>; 2136 clock-names = "gmu", 2137 "cxo", 2138 "axi", 2139 "memnoc", 2140 "ahb", 2141 "hub", 2142 "smmu_vote"; 2143 power-domains = <&gpucc 0>, 2144 <&gpucc 1>; 2145 power-domain-names = "cx", 2146 "gx"; 2147 iommus = <&adreno_smmu 5 0x400>; 2148 operating-points-v2 = <&gmu_opp_table>; 2149 2150 gmu_opp_table: opp-table { 2151 compatible = "operating-points-v2"; 2152 2153 opp-200000000 { 2154 opp-hz = /bits/ 64 <200000000>; 2155 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2156 }; 2157 }; 2158 }; 2159 2160 gpucc: clock-controller@3d90000 { 2161 compatible = "qcom,sc7280-gpucc"; 2162 reg = <0 0x03d90000 0 0x9000>; 2163 clocks = <&rpmhcc RPMH_CXO_CLK>, 2164 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2165 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2166 clock-names = "bi_tcxo", 2167 "gcc_gpu_gpll0_clk_src", 2168 "gcc_gpu_gpll0_div_clk_src"; 2169 #clock-cells = <1>; 2170 #reset-cells = <1>; 2171 #power-domain-cells = <1>; 2172 }; 2173 2174 adreno_smmu: iommu@3da0000 { 2175 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2176 reg = <0 0x03da0000 0 0x20000>; 2177 #iommu-cells = <2>; 2178 #global-interrupts = <2>; 2179 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2191 2192 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2193 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2194 <&gpucc 2>, 2195 <&gpucc 11>, 2196 <&gpucc 5>, 2197 <&gpucc 15>, 2198 <&gpucc 13>; 2199 clock-names = "gcc_gpu_memnoc_gfx_clk", 2200 "gcc_gpu_snoc_dvm_gfx_clk", 2201 "gpu_cc_ahb_clk", 2202 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2203 "gpu_cc_cx_gmu_clk", 2204 "gpu_cc_hub_cx_int_clk", 2205 "gpu_cc_hub_aon_clk"; 2206 2207 power-domains = <&gpucc 0>; 2208 }; 2209 2210 remoteproc_mpss: remoteproc@4080000 { 2211 compatible = "qcom,sc7280-mpss-pas"; 2212 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2213 reg-names = "qdsp6", "rmb"; 2214 2215 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2216 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2217 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2218 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2219 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2220 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2221 interrupt-names = "wdog", "fatal", "ready", "handover", 2222 "stop-ack", "shutdown-ack"; 2223 2224 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2225 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2226 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2227 <&rpmhcc RPMH_PKA_CLK>, 2228 <&rpmhcc RPMH_CXO_CLK>; 2229 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2230 2231 power-domains = <&rpmhpd SC7280_CX>, 2232 <&rpmhpd SC7280_MSS>; 2233 power-domain-names = "cx", "mss"; 2234 2235 memory-region = <&mpss_mem>; 2236 2237 qcom,qmp = <&aoss_qmp>; 2238 2239 qcom,smem-states = <&modem_smp2p_out 0>; 2240 qcom,smem-state-names = "stop"; 2241 2242 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2243 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2244 reset-names = "mss_restart", "pdc_reset"; 2245 2246 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 2247 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 2248 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 2249 2250 status = "disabled"; 2251 2252 glink-edge { 2253 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2254 IPCC_MPROC_SIGNAL_GLINK_QMP 2255 IRQ_TYPE_EDGE_RISING>; 2256 mboxes = <&ipcc IPCC_CLIENT_MPSS 2257 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2258 label = "modem"; 2259 qcom,remote-pid = <1>; 2260 }; 2261 }; 2262 2263 stm@6002000 { 2264 compatible = "arm,coresight-stm", "arm,primecell"; 2265 reg = <0 0x06002000 0 0x1000>, 2266 <0 0x16280000 0 0x180000>; 2267 reg-names = "stm-base", "stm-stimulus-base"; 2268 2269 clocks = <&aoss_qmp>; 2270 clock-names = "apb_pclk"; 2271 2272 out-ports { 2273 port { 2274 stm_out: endpoint { 2275 remote-endpoint = <&funnel0_in7>; 2276 }; 2277 }; 2278 }; 2279 }; 2280 2281 funnel@6041000 { 2282 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2283 reg = <0 0x06041000 0 0x1000>; 2284 2285 clocks = <&aoss_qmp>; 2286 clock-names = "apb_pclk"; 2287 2288 out-ports { 2289 port { 2290 funnel0_out: endpoint { 2291 remote-endpoint = <&merge_funnel_in0>; 2292 }; 2293 }; 2294 }; 2295 2296 in-ports { 2297 #address-cells = <1>; 2298 #size-cells = <0>; 2299 2300 port@7 { 2301 reg = <7>; 2302 funnel0_in7: endpoint { 2303 remote-endpoint = <&stm_out>; 2304 }; 2305 }; 2306 }; 2307 }; 2308 2309 funnel@6042000 { 2310 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2311 reg = <0 0x06042000 0 0x1000>; 2312 2313 clocks = <&aoss_qmp>; 2314 clock-names = "apb_pclk"; 2315 2316 out-ports { 2317 port { 2318 funnel1_out: endpoint { 2319 remote-endpoint = <&merge_funnel_in1>; 2320 }; 2321 }; 2322 }; 2323 2324 in-ports { 2325 #address-cells = <1>; 2326 #size-cells = <0>; 2327 2328 port@4 { 2329 reg = <4>; 2330 funnel1_in4: endpoint { 2331 remote-endpoint = <&apss_merge_funnel_out>; 2332 }; 2333 }; 2334 }; 2335 }; 2336 2337 funnel@6045000 { 2338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2339 reg = <0 0x06045000 0 0x1000>; 2340 2341 clocks = <&aoss_qmp>; 2342 clock-names = "apb_pclk"; 2343 2344 out-ports { 2345 port { 2346 merge_funnel_out: endpoint { 2347 remote-endpoint = <&swao_funnel_in>; 2348 }; 2349 }; 2350 }; 2351 2352 in-ports { 2353 #address-cells = <1>; 2354 #size-cells = <0>; 2355 2356 port@0 { 2357 reg = <0>; 2358 merge_funnel_in0: endpoint { 2359 remote-endpoint = <&funnel0_out>; 2360 }; 2361 }; 2362 2363 port@1 { 2364 reg = <1>; 2365 merge_funnel_in1: endpoint { 2366 remote-endpoint = <&funnel1_out>; 2367 }; 2368 }; 2369 }; 2370 }; 2371 2372 replicator@6046000 { 2373 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2374 reg = <0 0x06046000 0 0x1000>; 2375 2376 clocks = <&aoss_qmp>; 2377 clock-names = "apb_pclk"; 2378 2379 out-ports { 2380 port { 2381 replicator_out: endpoint { 2382 remote-endpoint = <&etr_in>; 2383 }; 2384 }; 2385 }; 2386 2387 in-ports { 2388 port { 2389 replicator_in: endpoint { 2390 remote-endpoint = <&swao_replicator_out>; 2391 }; 2392 }; 2393 }; 2394 }; 2395 2396 etr@6048000 { 2397 compatible = "arm,coresight-tmc", "arm,primecell"; 2398 reg = <0 0x06048000 0 0x1000>; 2399 iommus = <&apps_smmu 0x04c0 0>; 2400 2401 clocks = <&aoss_qmp>; 2402 clock-names = "apb_pclk"; 2403 arm,scatter-gather; 2404 2405 in-ports { 2406 port { 2407 etr_in: endpoint { 2408 remote-endpoint = <&replicator_out>; 2409 }; 2410 }; 2411 }; 2412 }; 2413 2414 funnel@6b04000 { 2415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2416 reg = <0 0x06b04000 0 0x1000>; 2417 2418 clocks = <&aoss_qmp>; 2419 clock-names = "apb_pclk"; 2420 2421 out-ports { 2422 port { 2423 swao_funnel_out: endpoint { 2424 remote-endpoint = <&etf_in>; 2425 }; 2426 }; 2427 }; 2428 2429 in-ports { 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 2433 port@7 { 2434 reg = <7>; 2435 swao_funnel_in: endpoint { 2436 remote-endpoint = <&merge_funnel_out>; 2437 }; 2438 }; 2439 }; 2440 }; 2441 2442 etf@6b05000 { 2443 compatible = "arm,coresight-tmc", "arm,primecell"; 2444 reg = <0 0x06b05000 0 0x1000>; 2445 2446 clocks = <&aoss_qmp>; 2447 clock-names = "apb_pclk"; 2448 2449 out-ports { 2450 port { 2451 etf_out: endpoint { 2452 remote-endpoint = <&swao_replicator_in>; 2453 }; 2454 }; 2455 }; 2456 2457 in-ports { 2458 port { 2459 etf_in: endpoint { 2460 remote-endpoint = <&swao_funnel_out>; 2461 }; 2462 }; 2463 }; 2464 }; 2465 2466 replicator@6b06000 { 2467 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2468 reg = <0 0x06b06000 0 0x1000>; 2469 2470 clocks = <&aoss_qmp>; 2471 clock-names = "apb_pclk"; 2472 qcom,replicator-loses-context; 2473 2474 out-ports { 2475 port { 2476 swao_replicator_out: endpoint { 2477 remote-endpoint = <&replicator_in>; 2478 }; 2479 }; 2480 }; 2481 2482 in-ports { 2483 port { 2484 swao_replicator_in: endpoint { 2485 remote-endpoint = <&etf_out>; 2486 }; 2487 }; 2488 }; 2489 }; 2490 2491 etm@7040000 { 2492 compatible = "arm,coresight-etm4x", "arm,primecell"; 2493 reg = <0 0x07040000 0 0x1000>; 2494 2495 cpu = <&CPU0>; 2496 2497 clocks = <&aoss_qmp>; 2498 clock-names = "apb_pclk"; 2499 arm,coresight-loses-context-with-cpu; 2500 qcom,skip-power-up; 2501 2502 out-ports { 2503 port { 2504 etm0_out: endpoint { 2505 remote-endpoint = <&apss_funnel_in0>; 2506 }; 2507 }; 2508 }; 2509 }; 2510 2511 etm@7140000 { 2512 compatible = "arm,coresight-etm4x", "arm,primecell"; 2513 reg = <0 0x07140000 0 0x1000>; 2514 2515 cpu = <&CPU1>; 2516 2517 clocks = <&aoss_qmp>; 2518 clock-names = "apb_pclk"; 2519 arm,coresight-loses-context-with-cpu; 2520 qcom,skip-power-up; 2521 2522 out-ports { 2523 port { 2524 etm1_out: endpoint { 2525 remote-endpoint = <&apss_funnel_in1>; 2526 }; 2527 }; 2528 }; 2529 }; 2530 2531 etm@7240000 { 2532 compatible = "arm,coresight-etm4x", "arm,primecell"; 2533 reg = <0 0x07240000 0 0x1000>; 2534 2535 cpu = <&CPU2>; 2536 2537 clocks = <&aoss_qmp>; 2538 clock-names = "apb_pclk"; 2539 arm,coresight-loses-context-with-cpu; 2540 qcom,skip-power-up; 2541 2542 out-ports { 2543 port { 2544 etm2_out: endpoint { 2545 remote-endpoint = <&apss_funnel_in2>; 2546 }; 2547 }; 2548 }; 2549 }; 2550 2551 etm@7340000 { 2552 compatible = "arm,coresight-etm4x", "arm,primecell"; 2553 reg = <0 0x07340000 0 0x1000>; 2554 2555 cpu = <&CPU3>; 2556 2557 clocks = <&aoss_qmp>; 2558 clock-names = "apb_pclk"; 2559 arm,coresight-loses-context-with-cpu; 2560 qcom,skip-power-up; 2561 2562 out-ports { 2563 port { 2564 etm3_out: endpoint { 2565 remote-endpoint = <&apss_funnel_in3>; 2566 }; 2567 }; 2568 }; 2569 }; 2570 2571 etm@7440000 { 2572 compatible = "arm,coresight-etm4x", "arm,primecell"; 2573 reg = <0 0x07440000 0 0x1000>; 2574 2575 cpu = <&CPU4>; 2576 2577 clocks = <&aoss_qmp>; 2578 clock-names = "apb_pclk"; 2579 arm,coresight-loses-context-with-cpu; 2580 qcom,skip-power-up; 2581 2582 out-ports { 2583 port { 2584 etm4_out: endpoint { 2585 remote-endpoint = <&apss_funnel_in4>; 2586 }; 2587 }; 2588 }; 2589 }; 2590 2591 etm@7540000 { 2592 compatible = "arm,coresight-etm4x", "arm,primecell"; 2593 reg = <0 0x07540000 0 0x1000>; 2594 2595 cpu = <&CPU5>; 2596 2597 clocks = <&aoss_qmp>; 2598 clock-names = "apb_pclk"; 2599 arm,coresight-loses-context-with-cpu; 2600 qcom,skip-power-up; 2601 2602 out-ports { 2603 port { 2604 etm5_out: endpoint { 2605 remote-endpoint = <&apss_funnel_in5>; 2606 }; 2607 }; 2608 }; 2609 }; 2610 2611 etm@7640000 { 2612 compatible = "arm,coresight-etm4x", "arm,primecell"; 2613 reg = <0 0x07640000 0 0x1000>; 2614 2615 cpu = <&CPU6>; 2616 2617 clocks = <&aoss_qmp>; 2618 clock-names = "apb_pclk"; 2619 arm,coresight-loses-context-with-cpu; 2620 qcom,skip-power-up; 2621 2622 out-ports { 2623 port { 2624 etm6_out: endpoint { 2625 remote-endpoint = <&apss_funnel_in6>; 2626 }; 2627 }; 2628 }; 2629 }; 2630 2631 etm@7740000 { 2632 compatible = "arm,coresight-etm4x", "arm,primecell"; 2633 reg = <0 0x07740000 0 0x1000>; 2634 2635 cpu = <&CPU7>; 2636 2637 clocks = <&aoss_qmp>; 2638 clock-names = "apb_pclk"; 2639 arm,coresight-loses-context-with-cpu; 2640 qcom,skip-power-up; 2641 2642 out-ports { 2643 port { 2644 etm7_out: endpoint { 2645 remote-endpoint = <&apss_funnel_in7>; 2646 }; 2647 }; 2648 }; 2649 }; 2650 2651 funnel@7800000 { /* APSS Funnel */ 2652 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2653 reg = <0 0x07800000 0 0x1000>; 2654 2655 clocks = <&aoss_qmp>; 2656 clock-names = "apb_pclk"; 2657 2658 out-ports { 2659 port { 2660 apss_funnel_out: endpoint { 2661 remote-endpoint = <&apss_merge_funnel_in>; 2662 }; 2663 }; 2664 }; 2665 2666 in-ports { 2667 #address-cells = <1>; 2668 #size-cells = <0>; 2669 2670 port@0 { 2671 reg = <0>; 2672 apss_funnel_in0: endpoint { 2673 remote-endpoint = <&etm0_out>; 2674 }; 2675 }; 2676 2677 port@1 { 2678 reg = <1>; 2679 apss_funnel_in1: endpoint { 2680 remote-endpoint = <&etm1_out>; 2681 }; 2682 }; 2683 2684 port@2 { 2685 reg = <2>; 2686 apss_funnel_in2: endpoint { 2687 remote-endpoint = <&etm2_out>; 2688 }; 2689 }; 2690 2691 port@3 { 2692 reg = <3>; 2693 apss_funnel_in3: endpoint { 2694 remote-endpoint = <&etm3_out>; 2695 }; 2696 }; 2697 2698 port@4 { 2699 reg = <4>; 2700 apss_funnel_in4: endpoint { 2701 remote-endpoint = <&etm4_out>; 2702 }; 2703 }; 2704 2705 port@5 { 2706 reg = <5>; 2707 apss_funnel_in5: endpoint { 2708 remote-endpoint = <&etm5_out>; 2709 }; 2710 }; 2711 2712 port@6 { 2713 reg = <6>; 2714 apss_funnel_in6: endpoint { 2715 remote-endpoint = <&etm6_out>; 2716 }; 2717 }; 2718 2719 port@7 { 2720 reg = <7>; 2721 apss_funnel_in7: endpoint { 2722 remote-endpoint = <&etm7_out>; 2723 }; 2724 }; 2725 }; 2726 }; 2727 2728 funnel@7810000 { 2729 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2730 reg = <0 0x07810000 0 0x1000>; 2731 2732 clocks = <&aoss_qmp>; 2733 clock-names = "apb_pclk"; 2734 2735 out-ports { 2736 port { 2737 apss_merge_funnel_out: endpoint { 2738 remote-endpoint = <&funnel1_in4>; 2739 }; 2740 }; 2741 }; 2742 2743 in-ports { 2744 port { 2745 apss_merge_funnel_in: endpoint { 2746 remote-endpoint = <&apss_funnel_out>; 2747 }; 2748 }; 2749 }; 2750 }; 2751 2752 sdhc_2: sdhci@8804000 { 2753 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2754 pinctrl-names = "default", "sleep"; 2755 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 2756 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 2757 status = "disabled"; 2758 2759 reg = <0 0x08804000 0 0x1000>; 2760 2761 iommus = <&apps_smmu 0x100 0x0>; 2762 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2764 interrupt-names = "hc_irq", "pwr_irq"; 2765 2766 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2767 <&gcc GCC_SDCC2_AHB_CLK>, 2768 <&rpmhcc RPMH_CXO_CLK>; 2769 clock-names = "core", "iface", "xo"; 2770 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2771 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2772 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2773 power-domains = <&rpmhpd SC7280_CX>; 2774 operating-points-v2 = <&sdhc2_opp_table>; 2775 2776 bus-width = <4>; 2777 2778 qcom,dll-config = <0x0007642c>; 2779 2780 resets = <&gcc GCC_SDCC2_BCR>; 2781 2782 sdhc2_opp_table: opp-table { 2783 compatible = "operating-points-v2"; 2784 2785 opp-100000000 { 2786 opp-hz = /bits/ 64 <100000000>; 2787 required-opps = <&rpmhpd_opp_low_svs>; 2788 opp-peak-kBps = <1800000 400000>; 2789 opp-avg-kBps = <100000 0>; 2790 }; 2791 2792 opp-202000000 { 2793 opp-hz = /bits/ 64 <202000000>; 2794 required-opps = <&rpmhpd_opp_nom>; 2795 opp-peak-kBps = <5400000 1600000>; 2796 opp-avg-kBps = <200000 0>; 2797 }; 2798 }; 2799 2800 }; 2801 2802 usb_1_hsphy: phy@88e3000 { 2803 compatible = "qcom,sc7280-usb-hs-phy", 2804 "qcom,usb-snps-hs-7nm-phy"; 2805 reg = <0 0x088e3000 0 0x400>; 2806 status = "disabled"; 2807 #phy-cells = <0>; 2808 2809 clocks = <&rpmhcc RPMH_CXO_CLK>; 2810 clock-names = "ref"; 2811 2812 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2813 }; 2814 2815 usb_2_hsphy: phy@88e4000 { 2816 compatible = "qcom,sc7280-usb-hs-phy", 2817 "qcom,usb-snps-hs-7nm-phy"; 2818 reg = <0 0x088e4000 0 0x400>; 2819 status = "disabled"; 2820 #phy-cells = <0>; 2821 2822 clocks = <&rpmhcc RPMH_CXO_CLK>; 2823 clock-names = "ref"; 2824 2825 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2826 }; 2827 2828 usb_1_qmpphy: phy-wrapper@88e9000 { 2829 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2830 "qcom,sm8250-qmp-usb3-dp-phy"; 2831 reg = <0 0x088e9000 0 0x200>, 2832 <0 0x088e8000 0 0x40>, 2833 <0 0x088ea000 0 0x200>; 2834 status = "disabled"; 2835 #address-cells = <2>; 2836 #size-cells = <2>; 2837 ranges; 2838 2839 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2840 <&rpmhcc RPMH_CXO_CLK>, 2841 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2842 clock-names = "aux", "ref_clk_src", "com_aux"; 2843 2844 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2845 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2846 reset-names = "phy", "common"; 2847 2848 usb_1_ssphy: usb3-phy@88e9200 { 2849 reg = <0 0x088e9200 0 0x200>, 2850 <0 0x088e9400 0 0x200>, 2851 <0 0x088e9c00 0 0x400>, 2852 <0 0x088e9600 0 0x200>, 2853 <0 0x088e9800 0 0x200>, 2854 <0 0x088e9a00 0 0x100>; 2855 #clock-cells = <0>; 2856 #phy-cells = <0>; 2857 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2858 clock-names = "pipe0"; 2859 clock-output-names = "usb3_phy_pipe_clk_src"; 2860 }; 2861 2862 dp_phy: dp-phy@88ea200 { 2863 reg = <0 0x088ea200 0 0x200>, 2864 <0 0x088ea400 0 0x200>, 2865 <0 0x088eaa00 0 0x200>, 2866 <0 0x088ea600 0 0x200>, 2867 <0 0x088ea800 0 0x200>; 2868 #phy-cells = <0>; 2869 #clock-cells = <1>; 2870 }; 2871 }; 2872 2873 usb_2: usb@8cf8800 { 2874 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2875 reg = <0 0x08cf8800 0 0x400>; 2876 status = "disabled"; 2877 #address-cells = <2>; 2878 #size-cells = <2>; 2879 ranges; 2880 dma-ranges; 2881 2882 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2883 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2884 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2885 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2886 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2887 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2888 "sleep"; 2889 2890 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2891 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2892 assigned-clock-rates = <19200000>, <200000000>; 2893 2894 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2895 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2896 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2897 interrupt-names = "hs_phy_irq", 2898 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2899 2900 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2901 2902 resets = <&gcc GCC_USB30_SEC_BCR>; 2903 2904 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2905 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2906 interconnect-names = "usb-ddr", "apps-usb"; 2907 2908 usb_2_dwc3: usb@8c00000 { 2909 compatible = "snps,dwc3"; 2910 reg = <0 0x08c00000 0 0xe000>; 2911 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2912 iommus = <&apps_smmu 0xa0 0x0>; 2913 snps,dis_u2_susphy_quirk; 2914 snps,dis_enblslpm_quirk; 2915 phys = <&usb_2_hsphy>; 2916 phy-names = "usb2-phy"; 2917 maximum-speed = "high-speed"; 2918 }; 2919 }; 2920 2921 qspi: spi@88dc000 { 2922 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2923 reg = <0 0x088dc000 0 0x1000>; 2924 #address-cells = <1>; 2925 #size-cells = <0>; 2926 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2927 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2928 <&gcc GCC_QSPI_CORE_CLK>; 2929 clock-names = "iface", "core"; 2930 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2931 &cnoc2 SLAVE_QSPI_0 0>; 2932 interconnect-names = "qspi-config"; 2933 power-domains = <&rpmhpd SC7280_CX>; 2934 operating-points-v2 = <&qspi_opp_table>; 2935 status = "disabled"; 2936 }; 2937 2938 remoteproc_wpss: remoteproc@8a00000 { 2939 compatible = "qcom,sc7280-wpss-pil"; 2940 reg = <0 0x08a00000 0 0x10000>; 2941 2942 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 2943 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2944 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2945 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2946 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2947 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2948 interrupt-names = "wdog", "fatal", "ready", "handover", 2949 "stop-ack", "shutdown-ack"; 2950 2951 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 2952 <&gcc GCC_WPSS_AHB_CLK>, 2953 <&gcc GCC_WPSS_RSCP_CLK>, 2954 <&rpmhcc RPMH_CXO_CLK>; 2955 clock-names = "ahb_bdg", "ahb", 2956 "rscp", "xo"; 2957 2958 power-domains = <&rpmhpd SC7280_CX>, 2959 <&rpmhpd SC7280_MX>; 2960 power-domain-names = "cx", "mx"; 2961 2962 memory-region = <&wpss_mem>; 2963 2964 qcom,qmp = <&aoss_qmp>; 2965 2966 qcom,smem-states = <&wpss_smp2p_out 0>; 2967 qcom,smem-state-names = "stop"; 2968 2969 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 2970 <&pdc_reset PDC_WPSS_SYNC_RESET>; 2971 reset-names = "restart", "pdc_sync"; 2972 2973 qcom,halt-regs = <&tcsr_mutex 0x37000>; 2974 2975 status = "disabled"; 2976 2977 glink-edge { 2978 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 2979 IPCC_MPROC_SIGNAL_GLINK_QMP 2980 IRQ_TYPE_EDGE_RISING>; 2981 mboxes = <&ipcc IPCC_CLIENT_WPSS 2982 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2983 2984 label = "wpss"; 2985 qcom,remote-pid = <13>; 2986 }; 2987 }; 2988 2989 dc_noc: interconnect@90e0000 { 2990 reg = <0 0x090e0000 0 0x5080>; 2991 compatible = "qcom,sc7280-dc-noc"; 2992 #interconnect-cells = <2>; 2993 qcom,bcm-voters = <&apps_bcm_voter>; 2994 }; 2995 2996 gem_noc: interconnect@9100000 { 2997 reg = <0 0x9100000 0 0xe2200>; 2998 compatible = "qcom,sc7280-gem-noc"; 2999 #interconnect-cells = <2>; 3000 qcom,bcm-voters = <&apps_bcm_voter>; 3001 }; 3002 3003 system-cache-controller@9200000 { 3004 compatible = "qcom,sc7280-llcc"; 3005 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3006 reg-names = "llcc_base", "llcc_broadcast_base"; 3007 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3008 }; 3009 3010 nsp_noc: interconnect@a0c0000 { 3011 reg = <0 0x0a0c0000 0 0x10000>; 3012 compatible = "qcom,sc7280-nsp-noc"; 3013 #interconnect-cells = <2>; 3014 qcom,bcm-voters = <&apps_bcm_voter>; 3015 }; 3016 3017 usb_1: usb@a6f8800 { 3018 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3019 reg = <0 0x0a6f8800 0 0x400>; 3020 status = "disabled"; 3021 #address-cells = <2>; 3022 #size-cells = <2>; 3023 ranges; 3024 dma-ranges; 3025 3026 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3027 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3028 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3029 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3030 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3031 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3032 "sleep"; 3033 3034 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3035 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3036 assigned-clock-rates = <19200000>, <200000000>; 3037 3038 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3039 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3040 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3041 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3042 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3043 "dm_hs_phy_irq", "ss_phy_irq"; 3044 3045 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3046 3047 resets = <&gcc GCC_USB30_PRIM_BCR>; 3048 3049 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3050 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3051 interconnect-names = "usb-ddr", "apps-usb"; 3052 3053 usb_1_dwc3: usb@a600000 { 3054 compatible = "snps,dwc3"; 3055 reg = <0 0x0a600000 0 0xe000>; 3056 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3057 iommus = <&apps_smmu 0xe0 0x0>; 3058 snps,dis_u2_susphy_quirk; 3059 snps,dis_enblslpm_quirk; 3060 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3061 phy-names = "usb2-phy", "usb3-phy"; 3062 maximum-speed = "super-speed"; 3063 }; 3064 }; 3065 3066 venus: video-codec@aa00000 { 3067 compatible = "qcom,sc7280-venus"; 3068 reg = <0 0x0aa00000 0 0xd0600>; 3069 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3070 3071 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3072 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3073 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3074 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3075 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3076 clock-names = "core", "bus", "iface", 3077 "vcodec_core", "vcodec_bus"; 3078 3079 power-domains = <&videocc MVSC_GDSC>, 3080 <&videocc MVS0_GDSC>, 3081 <&rpmhpd SC7280_CX>; 3082 power-domain-names = "venus", "vcodec0", "cx"; 3083 operating-points-v2 = <&venus_opp_table>; 3084 3085 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3086 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3087 interconnect-names = "cpu-cfg", "video-mem"; 3088 3089 iommus = <&apps_smmu 0x2180 0x20>, 3090 <&apps_smmu 0x2184 0x20>; 3091 memory-region = <&video_mem>; 3092 3093 video-decoder { 3094 compatible = "venus-decoder"; 3095 }; 3096 3097 video-encoder { 3098 compatible = "venus-encoder"; 3099 }; 3100 3101 video-firmware { 3102 iommus = <&apps_smmu 0x21a2 0x0>; 3103 }; 3104 3105 venus_opp_table: venus-opp-table { 3106 compatible = "operating-points-v2"; 3107 3108 opp-133330000 { 3109 opp-hz = /bits/ 64 <133330000>; 3110 required-opps = <&rpmhpd_opp_low_svs>; 3111 }; 3112 3113 opp-240000000 { 3114 opp-hz = /bits/ 64 <240000000>; 3115 required-opps = <&rpmhpd_opp_svs>; 3116 }; 3117 3118 opp-335000000 { 3119 opp-hz = /bits/ 64 <335000000>; 3120 required-opps = <&rpmhpd_opp_svs_l1>; 3121 }; 3122 3123 opp-424000000 { 3124 opp-hz = /bits/ 64 <424000000>; 3125 required-opps = <&rpmhpd_opp_nom>; 3126 }; 3127 3128 opp-460000048 { 3129 opp-hz = /bits/ 64 <460000048>; 3130 required-opps = <&rpmhpd_opp_turbo>; 3131 }; 3132 }; 3133 3134 }; 3135 3136 videocc: clock-controller@aaf0000 { 3137 compatible = "qcom,sc7280-videocc"; 3138 reg = <0 0xaaf0000 0 0x10000>; 3139 clocks = <&rpmhcc RPMH_CXO_CLK>, 3140 <&rpmhcc RPMH_CXO_CLK_A>; 3141 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3142 #clock-cells = <1>; 3143 #reset-cells = <1>; 3144 #power-domain-cells = <1>; 3145 }; 3146 3147 camcc: clock-controller@ad00000 { 3148 compatible = "qcom,sc7280-camcc"; 3149 reg = <0 0x0ad00000 0 0x10000>; 3150 clocks = <&rpmhcc RPMH_CXO_CLK>, 3151 <&rpmhcc RPMH_CXO_CLK_A>, 3152 <&sleep_clk>; 3153 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3154 #clock-cells = <1>; 3155 #reset-cells = <1>; 3156 #power-domain-cells = <1>; 3157 }; 3158 3159 dispcc: clock-controller@af00000 { 3160 compatible = "qcom,sc7280-dispcc"; 3161 reg = <0 0xaf00000 0 0x20000>; 3162 clocks = <&rpmhcc RPMH_CXO_CLK>, 3163 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3164 <&mdss_dsi_phy 0>, 3165 <&mdss_dsi_phy 1>, 3166 <&dp_phy 0>, 3167 <&dp_phy 1>, 3168 <&mdss_edp_phy 0>, 3169 <&mdss_edp_phy 1>; 3170 clock-names = "bi_tcxo", 3171 "gcc_disp_gpll0_clk", 3172 "dsi0_phy_pll_out_byteclk", 3173 "dsi0_phy_pll_out_dsiclk", 3174 "dp_phy_pll_link_clk", 3175 "dp_phy_pll_vco_div_clk", 3176 "edp_phy_pll_link_clk", 3177 "edp_phy_pll_vco_div_clk"; 3178 #clock-cells = <1>; 3179 #reset-cells = <1>; 3180 #power-domain-cells = <1>; 3181 }; 3182 3183 mdss: display-subsystem@ae00000 { 3184 compatible = "qcom,sc7280-mdss"; 3185 reg = <0 0x0ae00000 0 0x1000>; 3186 reg-names = "mdss"; 3187 3188 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3189 3190 clocks = <&gcc GCC_DISP_AHB_CLK>, 3191 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3192 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3193 clock-names = "iface", 3194 "ahb", 3195 "core"; 3196 3197 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3198 assigned-clock-rates = <300000000>; 3199 3200 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3201 interrupt-controller; 3202 #interrupt-cells = <1>; 3203 3204 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3205 interconnect-names = "mdp0-mem"; 3206 3207 iommus = <&apps_smmu 0x900 0x402>; 3208 3209 #address-cells = <2>; 3210 #size-cells = <2>; 3211 ranges; 3212 3213 status = "disabled"; 3214 3215 mdss_mdp: display-controller@ae01000 { 3216 compatible = "qcom,sc7280-dpu"; 3217 reg = <0 0x0ae01000 0 0x8f030>, 3218 <0 0x0aeb0000 0 0x2008>; 3219 reg-names = "mdp", "vbif"; 3220 3221 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3222 <&gcc GCC_DISP_SF_AXI_CLK>, 3223 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3224 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3225 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3226 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3227 clock-names = "bus", 3228 "nrt_bus", 3229 "iface", 3230 "lut", 3231 "core", 3232 "vsync"; 3233 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3234 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3235 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3236 assigned-clock-rates = <300000000>, 3237 <19200000>, 3238 <19200000>; 3239 operating-points-v2 = <&mdp_opp_table>; 3240 power-domains = <&rpmhpd SC7280_CX>; 3241 3242 interrupt-parent = <&mdss>; 3243 interrupts = <0>; 3244 3245 status = "disabled"; 3246 3247 ports { 3248 #address-cells = <1>; 3249 #size-cells = <0>; 3250 3251 port@0 { 3252 reg = <0>; 3253 dpu_intf1_out: endpoint { 3254 remote-endpoint = <&dsi0_in>; 3255 }; 3256 }; 3257 3258 port@1 { 3259 reg = <1>; 3260 dpu_intf5_out: endpoint { 3261 remote-endpoint = <&edp_in>; 3262 }; 3263 }; 3264 3265 port@2 { 3266 reg = <2>; 3267 dpu_intf0_out: endpoint { 3268 remote-endpoint = <&dp_in>; 3269 }; 3270 }; 3271 }; 3272 3273 mdp_opp_table: opp-table { 3274 compatible = "operating-points-v2"; 3275 3276 opp-200000000 { 3277 opp-hz = /bits/ 64 <200000000>; 3278 required-opps = <&rpmhpd_opp_low_svs>; 3279 }; 3280 3281 opp-300000000 { 3282 opp-hz = /bits/ 64 <300000000>; 3283 required-opps = <&rpmhpd_opp_svs>; 3284 }; 3285 3286 opp-380000000 { 3287 opp-hz = /bits/ 64 <380000000>; 3288 required-opps = <&rpmhpd_opp_svs_l1>; 3289 }; 3290 3291 opp-506666667 { 3292 opp-hz = /bits/ 64 <506666667>; 3293 required-opps = <&rpmhpd_opp_nom>; 3294 }; 3295 }; 3296 }; 3297 3298 mdss_dsi: dsi@ae94000 { 3299 compatible = "qcom,mdss-dsi-ctrl"; 3300 reg = <0 0x0ae94000 0 0x400>; 3301 reg-names = "dsi_ctrl"; 3302 3303 interrupt-parent = <&mdss>; 3304 interrupts = <4>; 3305 3306 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3307 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3308 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3309 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3310 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3311 <&gcc GCC_DISP_HF_AXI_CLK>; 3312 clock-names = "byte", 3313 "byte_intf", 3314 "pixel", 3315 "core", 3316 "iface", 3317 "bus"; 3318 3319 operating-points-v2 = <&dsi_opp_table>; 3320 power-domains = <&rpmhpd SC7280_CX>; 3321 3322 phys = <&mdss_dsi_phy>; 3323 phy-names = "dsi"; 3324 3325 #address-cells = <1>; 3326 #size-cells = <0>; 3327 3328 status = "disabled"; 3329 3330 ports { 3331 #address-cells = <1>; 3332 #size-cells = <0>; 3333 3334 port@0 { 3335 reg = <0>; 3336 dsi0_in: endpoint { 3337 remote-endpoint = <&dpu_intf1_out>; 3338 }; 3339 }; 3340 3341 port@1 { 3342 reg = <1>; 3343 dsi0_out: endpoint { 3344 }; 3345 }; 3346 }; 3347 3348 dsi_opp_table: opp-table { 3349 compatible = "operating-points-v2"; 3350 3351 opp-187500000 { 3352 opp-hz = /bits/ 64 <187500000>; 3353 required-opps = <&rpmhpd_opp_low_svs>; 3354 }; 3355 3356 opp-300000000 { 3357 opp-hz = /bits/ 64 <300000000>; 3358 required-opps = <&rpmhpd_opp_svs>; 3359 }; 3360 3361 opp-358000000 { 3362 opp-hz = /bits/ 64 <358000000>; 3363 required-opps = <&rpmhpd_opp_svs_l1>; 3364 }; 3365 }; 3366 }; 3367 3368 mdss_dsi_phy: phy@ae94400 { 3369 compatible = "qcom,sc7280-dsi-phy-7nm"; 3370 reg = <0 0x0ae94400 0 0x200>, 3371 <0 0x0ae94600 0 0x280>, 3372 <0 0x0ae94900 0 0x280>; 3373 reg-names = "dsi_phy", 3374 "dsi_phy_lane", 3375 "dsi_pll"; 3376 3377 #clock-cells = <1>; 3378 #phy-cells = <0>; 3379 3380 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3381 <&rpmhcc RPMH_CXO_CLK>; 3382 clock-names = "iface", "ref"; 3383 3384 status = "disabled"; 3385 }; 3386 3387 mdss_edp: edp@aea0000 { 3388 compatible = "qcom,sc7280-edp"; 3389 pinctrl-names = "default"; 3390 pinctrl-0 = <&edp_hot_plug_det>; 3391 3392 reg = <0 0xaea0000 0 0x200>, 3393 <0 0xaea0200 0 0x200>, 3394 <0 0xaea0400 0 0xc00>, 3395 <0 0xaea1000 0 0x400>; 3396 3397 interrupt-parent = <&mdss>; 3398 interrupts = <14>; 3399 3400 clocks = <&rpmhcc RPMH_CXO_CLK>, 3401 <&gcc GCC_EDP_CLKREF_EN>, 3402 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3403 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3404 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3405 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3406 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3407 clock-names = "core_xo", 3408 "core_ref", 3409 "core_iface", 3410 "core_aux", 3411 "ctrl_link", 3412 "ctrl_link_iface", 3413 "stream_pixel"; 3414 #clock-cells = <1>; 3415 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3416 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3417 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 3418 3419 phys = <&mdss_edp_phy>; 3420 phy-names = "dp"; 3421 3422 operating-points-v2 = <&edp_opp_table>; 3423 power-domains = <&rpmhpd SC7280_CX>; 3424 3425 #address-cells = <1>; 3426 #size-cells = <0>; 3427 3428 status = "disabled"; 3429 3430 ports { 3431 #address-cells = <1>; 3432 #size-cells = <0>; 3433 3434 port@0 { 3435 reg = <0>; 3436 edp_in: endpoint { 3437 remote-endpoint = <&dpu_intf5_out>; 3438 }; 3439 }; 3440 3441 port@1 { 3442 reg = <1>; 3443 mdss_edp_out: endpoint { }; 3444 }; 3445 }; 3446 3447 edp_opp_table: opp-table { 3448 compatible = "operating-points-v2"; 3449 3450 opp-160000000 { 3451 opp-hz = /bits/ 64 <160000000>; 3452 required-opps = <&rpmhpd_opp_low_svs>; 3453 }; 3454 3455 opp-270000000 { 3456 opp-hz = /bits/ 64 <270000000>; 3457 required-opps = <&rpmhpd_opp_svs>; 3458 }; 3459 3460 opp-540000000 { 3461 opp-hz = /bits/ 64 <540000000>; 3462 required-opps = <&rpmhpd_opp_nom>; 3463 }; 3464 3465 opp-810000000 { 3466 opp-hz = /bits/ 64 <810000000>; 3467 required-opps = <&rpmhpd_opp_nom>; 3468 }; 3469 }; 3470 }; 3471 3472 mdss_edp_phy: phy@aec2a00 { 3473 compatible = "qcom,sc7280-edp-phy"; 3474 3475 reg = <0 0xaec2a00 0 0x19c>, 3476 <0 0xaec2200 0 0xa0>, 3477 <0 0xaec2600 0 0xa0>, 3478 <0 0xaec2000 0 0x1c0>; 3479 3480 clocks = <&rpmhcc RPMH_CXO_CLK>, 3481 <&gcc GCC_EDP_CLKREF_EN>; 3482 clock-names = "aux", 3483 "cfg_ahb"; 3484 3485 #clock-cells = <1>; 3486 #phy-cells = <0>; 3487 3488 status = "disabled"; 3489 }; 3490 3491 mdss_dp: displayport-controller@ae90000 { 3492 compatible = "qcom,sc7280-dp"; 3493 3494 reg = <0 0x0ae90000 0 0x1400>; 3495 3496 interrupt-parent = <&mdss>; 3497 interrupts = <12>; 3498 3499 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3500 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3501 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3502 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3503 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3504 clock-names = "core_iface", 3505 "core_aux", 3506 "ctrl_link", 3507 "ctrl_link_iface", 3508 "stream_pixel"; 3509 #clock-cells = <1>; 3510 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3511 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3512 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3513 phys = <&dp_phy>; 3514 phy-names = "dp"; 3515 3516 operating-points-v2 = <&dp_opp_table>; 3517 power-domains = <&rpmhpd SC7280_CX>; 3518 3519 #sound-dai-cells = <0>; 3520 3521 status = "disabled"; 3522 3523 ports { 3524 #address-cells = <1>; 3525 #size-cells = <0>; 3526 3527 port@0 { 3528 reg = <0>; 3529 dp_in: endpoint { 3530 remote-endpoint = <&dpu_intf0_out>; 3531 }; 3532 }; 3533 3534 port@1 { 3535 reg = <1>; 3536 dp_out: endpoint { }; 3537 }; 3538 }; 3539 3540 dp_opp_table: opp-table { 3541 compatible = "operating-points-v2"; 3542 3543 opp-160000000 { 3544 opp-hz = /bits/ 64 <160000000>; 3545 required-opps = <&rpmhpd_opp_low_svs>; 3546 }; 3547 3548 opp-270000000 { 3549 opp-hz = /bits/ 64 <270000000>; 3550 required-opps = <&rpmhpd_opp_svs>; 3551 }; 3552 3553 opp-540000000 { 3554 opp-hz = /bits/ 64 <540000000>; 3555 required-opps = <&rpmhpd_opp_svs_l1>; 3556 }; 3557 3558 opp-810000000 { 3559 opp-hz = /bits/ 64 <810000000>; 3560 required-opps = <&rpmhpd_opp_nom>; 3561 }; 3562 }; 3563 }; 3564 }; 3565 3566 pdc: interrupt-controller@b220000 { 3567 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 3568 reg = <0 0x0b220000 0 0x30000>; 3569 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 3570 <55 306 4>, <59 312 3>, <62 374 2>, 3571 <64 434 2>, <66 438 3>, <69 86 1>, 3572 <70 520 54>, <124 609 31>, <155 63 1>, 3573 <156 716 12>; 3574 #interrupt-cells = <2>; 3575 interrupt-parent = <&intc>; 3576 interrupt-controller; 3577 }; 3578 3579 pdc_reset: reset-controller@b5e0000 { 3580 compatible = "qcom,sc7280-pdc-global"; 3581 reg = <0 0x0b5e0000 0 0x20000>; 3582 #reset-cells = <1>; 3583 }; 3584 3585 tsens0: thermal-sensor@c263000 { 3586 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3587 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3588 <0 0x0c222000 0 0x1ff>; /* SROT */ 3589 #qcom,sensors = <15>; 3590 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3592 interrupt-names = "uplow","critical"; 3593 #thermal-sensor-cells = <1>; 3594 }; 3595 3596 tsens1: thermal-sensor@c265000 { 3597 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 3598 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3599 <0 0x0c223000 0 0x1ff>; /* SROT */ 3600 #qcom,sensors = <12>; 3601 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3603 interrupt-names = "uplow","critical"; 3604 #thermal-sensor-cells = <1>; 3605 }; 3606 3607 aoss_reset: reset-controller@c2a0000 { 3608 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 3609 reg = <0 0x0c2a0000 0 0x31000>; 3610 #reset-cells = <1>; 3611 }; 3612 3613 aoss_qmp: power-controller@c300000 { 3614 compatible = "qcom,sc7280-aoss-qmp"; 3615 reg = <0 0x0c300000 0 0x400>; 3616 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3617 IPCC_MPROC_SIGNAL_GLINK_QMP 3618 IRQ_TYPE_EDGE_RISING>; 3619 mboxes = <&ipcc IPCC_CLIENT_AOP 3620 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3621 3622 #clock-cells = <0>; 3623 }; 3624 3625 sram@c3f0000 { 3626 compatible = "qcom,rpmh-stats"; 3627 reg = <0 0x0c3f0000 0 0x400>; 3628 }; 3629 3630 spmi_bus: spmi@c440000 { 3631 compatible = "qcom,spmi-pmic-arb"; 3632 reg = <0 0x0c440000 0 0x1100>, 3633 <0 0x0c600000 0 0x2000000>, 3634 <0 0x0e600000 0 0x100000>, 3635 <0 0x0e700000 0 0xa0000>, 3636 <0 0x0c40a000 0 0x26000>; 3637 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3638 interrupt-names = "periph_irq"; 3639 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3640 qcom,ee = <0>; 3641 qcom,channel = <0>; 3642 #address-cells = <1>; 3643 #size-cells = <1>; 3644 interrupt-controller; 3645 #interrupt-cells = <4>; 3646 }; 3647 3648 tlmm: pinctrl@f100000 { 3649 compatible = "qcom,sc7280-pinctrl"; 3650 reg = <0 0x0f100000 0 0x300000>; 3651 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3652 gpio-controller; 3653 #gpio-cells = <2>; 3654 interrupt-controller; 3655 #interrupt-cells = <2>; 3656 gpio-ranges = <&tlmm 0 0 175>; 3657 wakeup-parent = <&pdc>; 3658 3659 dp_hot_plug_det: dp-hot-plug-det { 3660 pins = "gpio47"; 3661 function = "dp_hot"; 3662 }; 3663 3664 edp_hot_plug_det: edp-hot-plug-det { 3665 pins = "gpio60"; 3666 function = "edp_hot"; 3667 }; 3668 3669 pcie1_clkreq_n: pcie1-clkreq-n { 3670 pins = "gpio79"; 3671 function = "pcie1_clkreqn"; 3672 }; 3673 3674 qspi_clk: qspi-clk { 3675 pins = "gpio14"; 3676 function = "qspi_clk"; 3677 }; 3678 3679 qspi_cs0: qspi-cs0 { 3680 pins = "gpio15"; 3681 function = "qspi_cs"; 3682 }; 3683 3684 qspi_cs1: qspi-cs1 { 3685 pins = "gpio19"; 3686 function = "qspi_cs"; 3687 }; 3688 3689 qspi_data01: qspi-data01 { 3690 pins = "gpio12", "gpio13"; 3691 function = "qspi_data"; 3692 }; 3693 3694 qspi_data12: qspi-data12 { 3695 pins = "gpio16", "gpio17"; 3696 function = "qspi_data"; 3697 }; 3698 3699 qup_i2c0_data_clk: qup-i2c0-data-clk { 3700 pins = "gpio0", "gpio1"; 3701 function = "qup00"; 3702 }; 3703 3704 qup_i2c1_data_clk: qup-i2c1-data-clk { 3705 pins = "gpio4", "gpio5"; 3706 function = "qup01"; 3707 }; 3708 3709 qup_i2c2_data_clk: qup-i2c2-data-clk { 3710 pins = "gpio8", "gpio9"; 3711 function = "qup02"; 3712 }; 3713 3714 qup_i2c3_data_clk: qup-i2c3-data-clk { 3715 pins = "gpio12", "gpio13"; 3716 function = "qup03"; 3717 }; 3718 3719 qup_i2c4_data_clk: qup-i2c4-data-clk { 3720 pins = "gpio16", "gpio17"; 3721 function = "qup04"; 3722 }; 3723 3724 qup_i2c5_data_clk: qup-i2c5-data-clk { 3725 pins = "gpio20", "gpio21"; 3726 function = "qup05"; 3727 }; 3728 3729 qup_i2c6_data_clk: qup-i2c6-data-clk { 3730 pins = "gpio24", "gpio25"; 3731 function = "qup06"; 3732 }; 3733 3734 qup_i2c7_data_clk: qup-i2c7-data-clk { 3735 pins = "gpio28", "gpio29"; 3736 function = "qup07"; 3737 }; 3738 3739 qup_i2c8_data_clk: qup-i2c8-data-clk { 3740 pins = "gpio32", "gpio33"; 3741 function = "qup10"; 3742 }; 3743 3744 qup_i2c9_data_clk: qup-i2c9-data-clk { 3745 pins = "gpio36", "gpio37"; 3746 function = "qup11"; 3747 }; 3748 3749 qup_i2c10_data_clk: qup-i2c10-data-clk { 3750 pins = "gpio40", "gpio41"; 3751 function = "qup12"; 3752 }; 3753 3754 qup_i2c11_data_clk: qup-i2c11-data-clk { 3755 pins = "gpio44", "gpio45"; 3756 function = "qup13"; 3757 }; 3758 3759 qup_i2c12_data_clk: qup-i2c12-data-clk { 3760 pins = "gpio48", "gpio49"; 3761 function = "qup14"; 3762 }; 3763 3764 qup_i2c13_data_clk: qup-i2c13-data-clk { 3765 pins = "gpio52", "gpio53"; 3766 function = "qup15"; 3767 }; 3768 3769 qup_i2c14_data_clk: qup-i2c14-data-clk { 3770 pins = "gpio56", "gpio57"; 3771 function = "qup16"; 3772 }; 3773 3774 qup_i2c15_data_clk: qup-i2c15-data-clk { 3775 pins = "gpio60", "gpio61"; 3776 function = "qup17"; 3777 }; 3778 3779 qup_spi0_data_clk: qup-spi0-data-clk { 3780 pins = "gpio0", "gpio1", "gpio2"; 3781 function = "qup00"; 3782 }; 3783 3784 qup_spi0_cs: qup-spi0-cs { 3785 pins = "gpio3"; 3786 function = "qup00"; 3787 }; 3788 3789 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3790 pins = "gpio3"; 3791 function = "gpio"; 3792 }; 3793 3794 qup_spi1_data_clk: qup-spi1-data-clk { 3795 pins = "gpio4", "gpio5", "gpio6"; 3796 function = "qup01"; 3797 }; 3798 3799 qup_spi1_cs: qup-spi1-cs { 3800 pins = "gpio7"; 3801 function = "qup01"; 3802 }; 3803 3804 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3805 pins = "gpio7"; 3806 function = "gpio"; 3807 }; 3808 3809 qup_spi2_data_clk: qup-spi2-data-clk { 3810 pins = "gpio8", "gpio9", "gpio10"; 3811 function = "qup02"; 3812 }; 3813 3814 qup_spi2_cs: qup-spi2-cs { 3815 pins = "gpio11"; 3816 function = "qup02"; 3817 }; 3818 3819 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3820 pins = "gpio11"; 3821 function = "gpio"; 3822 }; 3823 3824 qup_spi3_data_clk: qup-spi3-data-clk { 3825 pins = "gpio12", "gpio13", "gpio14"; 3826 function = "qup03"; 3827 }; 3828 3829 qup_spi3_cs: qup-spi3-cs { 3830 pins = "gpio15"; 3831 function = "qup03"; 3832 }; 3833 3834 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3835 pins = "gpio15"; 3836 function = "gpio"; 3837 }; 3838 3839 qup_spi4_data_clk: qup-spi4-data-clk { 3840 pins = "gpio16", "gpio17", "gpio18"; 3841 function = "qup04"; 3842 }; 3843 3844 qup_spi4_cs: qup-spi4-cs { 3845 pins = "gpio19"; 3846 function = "qup04"; 3847 }; 3848 3849 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3850 pins = "gpio19"; 3851 function = "gpio"; 3852 }; 3853 3854 qup_spi5_data_clk: qup-spi5-data-clk { 3855 pins = "gpio20", "gpio21", "gpio22"; 3856 function = "qup05"; 3857 }; 3858 3859 qup_spi5_cs: qup-spi5-cs { 3860 pins = "gpio23"; 3861 function = "qup05"; 3862 }; 3863 3864 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3865 pins = "gpio23"; 3866 function = "gpio"; 3867 }; 3868 3869 qup_spi6_data_clk: qup-spi6-data-clk { 3870 pins = "gpio24", "gpio25", "gpio26"; 3871 function = "qup06"; 3872 }; 3873 3874 qup_spi6_cs: qup-spi6-cs { 3875 pins = "gpio27"; 3876 function = "qup06"; 3877 }; 3878 3879 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3880 pins = "gpio27"; 3881 function = "gpio"; 3882 }; 3883 3884 qup_spi7_data_clk: qup-spi7-data-clk { 3885 pins = "gpio28", "gpio29", "gpio30"; 3886 function = "qup07"; 3887 }; 3888 3889 qup_spi7_cs: qup-spi7-cs { 3890 pins = "gpio31"; 3891 function = "qup07"; 3892 }; 3893 3894 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3895 pins = "gpio31"; 3896 function = "gpio"; 3897 }; 3898 3899 qup_spi8_data_clk: qup-spi8-data-clk { 3900 pins = "gpio32", "gpio33", "gpio34"; 3901 function = "qup10"; 3902 }; 3903 3904 qup_spi8_cs: qup-spi8-cs { 3905 pins = "gpio35"; 3906 function = "qup10"; 3907 }; 3908 3909 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3910 pins = "gpio35"; 3911 function = "gpio"; 3912 }; 3913 3914 qup_spi9_data_clk: qup-spi9-data-clk { 3915 pins = "gpio36", "gpio37", "gpio38"; 3916 function = "qup11"; 3917 }; 3918 3919 qup_spi9_cs: qup-spi9-cs { 3920 pins = "gpio39"; 3921 function = "qup11"; 3922 }; 3923 3924 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3925 pins = "gpio39"; 3926 function = "gpio"; 3927 }; 3928 3929 qup_spi10_data_clk: qup-spi10-data-clk { 3930 pins = "gpio40", "gpio41", "gpio42"; 3931 function = "qup12"; 3932 }; 3933 3934 qup_spi10_cs: qup-spi10-cs { 3935 pins = "gpio43"; 3936 function = "qup12"; 3937 }; 3938 3939 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3940 pins = "gpio43"; 3941 function = "gpio"; 3942 }; 3943 3944 qup_spi11_data_clk: qup-spi11-data-clk { 3945 pins = "gpio44", "gpio45", "gpio46"; 3946 function = "qup13"; 3947 }; 3948 3949 qup_spi11_cs: qup-spi11-cs { 3950 pins = "gpio47"; 3951 function = "qup13"; 3952 }; 3953 3954 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3955 pins = "gpio47"; 3956 function = "gpio"; 3957 }; 3958 3959 qup_spi12_data_clk: qup-spi12-data-clk { 3960 pins = "gpio48", "gpio49", "gpio50"; 3961 function = "qup14"; 3962 }; 3963 3964 qup_spi12_cs: qup-spi12-cs { 3965 pins = "gpio51"; 3966 function = "qup14"; 3967 }; 3968 3969 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3970 pins = "gpio51"; 3971 function = "gpio"; 3972 }; 3973 3974 qup_spi13_data_clk: qup-spi13-data-clk { 3975 pins = "gpio52", "gpio53", "gpio54"; 3976 function = "qup15"; 3977 }; 3978 3979 qup_spi13_cs: qup-spi13-cs { 3980 pins = "gpio55"; 3981 function = "qup15"; 3982 }; 3983 3984 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3985 pins = "gpio55"; 3986 function = "gpio"; 3987 }; 3988 3989 qup_spi14_data_clk: qup-spi14-data-clk { 3990 pins = "gpio56", "gpio57", "gpio58"; 3991 function = "qup16"; 3992 }; 3993 3994 qup_spi14_cs: qup-spi14-cs { 3995 pins = "gpio59"; 3996 function = "qup16"; 3997 }; 3998 3999 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4000 pins = "gpio59"; 4001 function = "gpio"; 4002 }; 4003 4004 qup_spi15_data_clk: qup-spi15-data-clk { 4005 pins = "gpio60", "gpio61", "gpio62"; 4006 function = "qup17"; 4007 }; 4008 4009 qup_spi15_cs: qup-spi15-cs { 4010 pins = "gpio63"; 4011 function = "qup17"; 4012 }; 4013 4014 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4015 pins = "gpio63"; 4016 function = "gpio"; 4017 }; 4018 4019 qup_uart0_cts: qup-uart0-cts { 4020 pins = "gpio0"; 4021 function = "qup00"; 4022 }; 4023 4024 qup_uart0_rts: qup-uart0-rts { 4025 pins = "gpio1"; 4026 function = "qup00"; 4027 }; 4028 4029 qup_uart0_tx: qup-uart0-tx { 4030 pins = "gpio2"; 4031 function = "qup00"; 4032 }; 4033 4034 qup_uart0_rx: qup-uart0-rx { 4035 pins = "gpio3"; 4036 function = "qup00"; 4037 }; 4038 4039 qup_uart1_cts: qup-uart1-cts { 4040 pins = "gpio4"; 4041 function = "qup01"; 4042 }; 4043 4044 qup_uart1_rts: qup-uart1-rts { 4045 pins = "gpio5"; 4046 function = "qup01"; 4047 }; 4048 4049 qup_uart1_tx: qup-uart1-tx { 4050 pins = "gpio6"; 4051 function = "qup01"; 4052 }; 4053 4054 qup_uart1_rx: qup-uart1-rx { 4055 pins = "gpio7"; 4056 function = "qup01"; 4057 }; 4058 4059 qup_uart2_cts: qup-uart2-cts { 4060 pins = "gpio8"; 4061 function = "qup02"; 4062 }; 4063 4064 qup_uart2_rts: qup-uart2-rts { 4065 pins = "gpio9"; 4066 function = "qup02"; 4067 }; 4068 4069 qup_uart2_tx: qup-uart2-tx { 4070 pins = "gpio10"; 4071 function = "qup02"; 4072 }; 4073 4074 qup_uart2_rx: qup-uart2-rx { 4075 pins = "gpio11"; 4076 function = "qup02"; 4077 }; 4078 4079 qup_uart3_cts: qup-uart3-cts { 4080 pins = "gpio12"; 4081 function = "qup03"; 4082 }; 4083 4084 qup_uart3_rts: qup-uart3-rts { 4085 pins = "gpio13"; 4086 function = "qup03"; 4087 }; 4088 4089 qup_uart3_tx: qup-uart3-tx { 4090 pins = "gpio14"; 4091 function = "qup03"; 4092 }; 4093 4094 qup_uart3_rx: qup-uart3-rx { 4095 pins = "gpio15"; 4096 function = "qup03"; 4097 }; 4098 4099 qup_uart4_cts: qup-uart4-cts { 4100 pins = "gpio16"; 4101 function = "qup04"; 4102 }; 4103 4104 qup_uart4_rts: qup-uart4-rts { 4105 pins = "gpio17"; 4106 function = "qup04"; 4107 }; 4108 4109 qup_uart4_tx: qup-uart4-tx { 4110 pins = "gpio18"; 4111 function = "qup04"; 4112 }; 4113 4114 qup_uart4_rx: qup-uart4-rx { 4115 pins = "gpio19"; 4116 function = "qup04"; 4117 }; 4118 4119 qup_uart5_cts: qup-uart5-cts { 4120 pins = "gpio20"; 4121 function = "qup05"; 4122 }; 4123 4124 qup_uart5_rts: qup-uart5-rts { 4125 pins = "gpio21"; 4126 function = "qup05"; 4127 }; 4128 4129 qup_uart5_tx: qup-uart5-tx { 4130 pins = "gpio22"; 4131 function = "qup05"; 4132 }; 4133 4134 qup_uart5_rx: qup-uart5-rx { 4135 pins = "gpio23"; 4136 function = "qup05"; 4137 }; 4138 4139 qup_uart6_cts: qup-uart6-cts { 4140 pins = "gpio24"; 4141 function = "qup06"; 4142 }; 4143 4144 qup_uart6_rts: qup-uart6-rts { 4145 pins = "gpio25"; 4146 function = "qup06"; 4147 }; 4148 4149 qup_uart6_tx: qup-uart6-tx { 4150 pins = "gpio26"; 4151 function = "qup06"; 4152 }; 4153 4154 qup_uart6_rx: qup-uart6-rx { 4155 pins = "gpio27"; 4156 function = "qup06"; 4157 }; 4158 4159 qup_uart7_cts: qup-uart7-cts { 4160 pins = "gpio28"; 4161 function = "qup07"; 4162 }; 4163 4164 qup_uart7_rts: qup-uart7-rts { 4165 pins = "gpio29"; 4166 function = "qup07"; 4167 }; 4168 4169 qup_uart7_tx: qup-uart7-tx { 4170 pins = "gpio30"; 4171 function = "qup07"; 4172 }; 4173 4174 qup_uart7_rx: qup-uart7-rx { 4175 pins = "gpio31"; 4176 function = "qup07"; 4177 }; 4178 4179 qup_uart8_cts: qup-uart8-cts { 4180 pins = "gpio32"; 4181 function = "qup10"; 4182 }; 4183 4184 qup_uart8_rts: qup-uart8-rts { 4185 pins = "gpio33"; 4186 function = "qup10"; 4187 }; 4188 4189 qup_uart8_tx: qup-uart8-tx { 4190 pins = "gpio34"; 4191 function = "qup10"; 4192 }; 4193 4194 qup_uart8_rx: qup-uart8-rx { 4195 pins = "gpio35"; 4196 function = "qup10"; 4197 }; 4198 4199 qup_uart9_cts: qup-uart9-cts { 4200 pins = "gpio36"; 4201 function = "qup11"; 4202 }; 4203 4204 qup_uart9_rts: qup-uart9-rts { 4205 pins = "gpio37"; 4206 function = "qup11"; 4207 }; 4208 4209 qup_uart9_tx: qup-uart9-tx { 4210 pins = "gpio38"; 4211 function = "qup11"; 4212 }; 4213 4214 qup_uart9_rx: qup-uart9-rx { 4215 pins = "gpio39"; 4216 function = "qup11"; 4217 }; 4218 4219 qup_uart10_cts: qup-uart10-cts { 4220 pins = "gpio40"; 4221 function = "qup12"; 4222 }; 4223 4224 qup_uart10_rts: qup-uart10-rts { 4225 pins = "gpio41"; 4226 function = "qup12"; 4227 }; 4228 4229 qup_uart10_tx: qup-uart10-tx { 4230 pins = "gpio42"; 4231 function = "qup12"; 4232 }; 4233 4234 qup_uart10_rx: qup-uart10-rx { 4235 pins = "gpio43"; 4236 function = "qup12"; 4237 }; 4238 4239 qup_uart11_cts: qup-uart11-cts { 4240 pins = "gpio44"; 4241 function = "qup13"; 4242 }; 4243 4244 qup_uart11_rts: qup-uart11-rts { 4245 pins = "gpio45"; 4246 function = "qup13"; 4247 }; 4248 4249 qup_uart11_tx: qup-uart11-tx { 4250 pins = "gpio46"; 4251 function = "qup13"; 4252 }; 4253 4254 qup_uart11_rx: qup-uart11-rx { 4255 pins = "gpio47"; 4256 function = "qup13"; 4257 }; 4258 4259 qup_uart12_cts: qup-uart12-cts { 4260 pins = "gpio48"; 4261 function = "qup14"; 4262 }; 4263 4264 qup_uart12_rts: qup-uart12-rts { 4265 pins = "gpio49"; 4266 function = "qup14"; 4267 }; 4268 4269 qup_uart12_tx: qup-uart12-tx { 4270 pins = "gpio50"; 4271 function = "qup14"; 4272 }; 4273 4274 qup_uart12_rx: qup-uart12-rx { 4275 pins = "gpio51"; 4276 function = "qup14"; 4277 }; 4278 4279 qup_uart13_cts: qup-uart13-cts { 4280 pins = "gpio52"; 4281 function = "qup15"; 4282 }; 4283 4284 qup_uart13_rts: qup-uart13-rts { 4285 pins = "gpio53"; 4286 function = "qup15"; 4287 }; 4288 4289 qup_uart13_tx: qup-uart13-tx { 4290 pins = "gpio54"; 4291 function = "qup15"; 4292 }; 4293 4294 qup_uart13_rx: qup-uart13-rx { 4295 pins = "gpio55"; 4296 function = "qup15"; 4297 }; 4298 4299 qup_uart14_cts: qup-uart14-cts { 4300 pins = "gpio56"; 4301 function = "qup16"; 4302 }; 4303 4304 qup_uart14_rts: qup-uart14-rts { 4305 pins = "gpio57"; 4306 function = "qup16"; 4307 }; 4308 4309 qup_uart14_tx: qup-uart14-tx { 4310 pins = "gpio58"; 4311 function = "qup16"; 4312 }; 4313 4314 qup_uart14_rx: qup-uart14-rx { 4315 pins = "gpio59"; 4316 function = "qup16"; 4317 }; 4318 4319 qup_uart15_cts: qup-uart15-cts { 4320 pins = "gpio60"; 4321 function = "qup17"; 4322 }; 4323 4324 qup_uart15_rts: qup-uart15-rts { 4325 pins = "gpio61"; 4326 function = "qup17"; 4327 }; 4328 4329 qup_uart15_tx: qup-uart15-tx { 4330 pins = "gpio62"; 4331 function = "qup17"; 4332 }; 4333 4334 qup_uart15_rx: qup-uart15-rx { 4335 pins = "gpio63"; 4336 function = "qup17"; 4337 }; 4338 4339 sdc1_clk: sdc1-clk { 4340 pins = "sdc1_clk"; 4341 }; 4342 4343 sdc1_cmd: sdc1-cmd { 4344 pins = "sdc1_cmd"; 4345 }; 4346 4347 sdc1_data: sdc1-data { 4348 pins = "sdc1_data"; 4349 }; 4350 4351 sdc1_rclk: sdc1-rclk { 4352 pins = "sdc1_rclk"; 4353 }; 4354 4355 sdc1_clk_sleep: sdc1-clk-sleep { 4356 pins = "sdc1_clk"; 4357 drive-strength = <2>; 4358 bias-bus-hold; 4359 }; 4360 4361 sdc1_cmd_sleep: sdc1-cmd-sleep { 4362 pins = "sdc1_cmd"; 4363 drive-strength = <2>; 4364 bias-bus-hold; 4365 }; 4366 4367 sdc1_data_sleep: sdc1-data-sleep { 4368 pins = "sdc1_data"; 4369 drive-strength = <2>; 4370 bias-bus-hold; 4371 }; 4372 4373 sdc1_rclk_sleep: sdc1-rclk-sleep { 4374 pins = "sdc1_rclk"; 4375 drive-strength = <2>; 4376 bias-bus-hold; 4377 }; 4378 4379 sdc2_clk: sdc2-clk { 4380 pins = "sdc2_clk"; 4381 }; 4382 4383 sdc2_cmd: sdc2-cmd { 4384 pins = "sdc2_cmd"; 4385 }; 4386 4387 sdc2_data: sdc2-data { 4388 pins = "sdc2_data"; 4389 }; 4390 4391 sdc2_clk_sleep: sdc2-clk-sleep { 4392 pins = "sdc2_clk"; 4393 drive-strength = <2>; 4394 bias-bus-hold; 4395 }; 4396 4397 sdc2_cmd_sleep: sdc2-cmd-sleep { 4398 pins = "sdc2_cmd"; 4399 drive-strength = <2>; 4400 bias-bus-hold; 4401 }; 4402 4403 sdc2_data_sleep: sdc2-data-sleep { 4404 pins = "sdc2_data"; 4405 drive-strength = <2>; 4406 bias-bus-hold; 4407 }; 4408 }; 4409 4410 imem@146a5000 { 4411 compatible = "qcom,sc7280-imem", "syscon"; 4412 reg = <0 0x146a5000 0 0x6000>; 4413 4414 #address-cells = <1>; 4415 #size-cells = <1>; 4416 4417 ranges = <0 0 0x146a5000 0x6000>; 4418 4419 pil-reloc@594c { 4420 compatible = "qcom,pil-reloc-info"; 4421 reg = <0x594c 0xc8>; 4422 }; 4423 }; 4424 4425 apps_smmu: iommu@15000000 { 4426 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 4427 reg = <0 0x15000000 0 0x100000>; 4428 #iommu-cells = <2>; 4429 #global-interrupts = <1>; 4430 dma-coherent; 4431 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4432 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4433 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4434 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4435 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4436 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4437 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4438 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4440 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4441 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4442 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4443 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4444 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4445 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4446 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4447 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4448 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4449 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4450 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4451 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4452 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4453 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4454 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4455 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4456 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4457 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4458 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4459 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4460 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4461 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4462 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4463 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4464 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4465 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4466 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4467 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4468 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4469 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4470 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4471 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4472 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4473 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4474 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4475 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4476 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4477 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4478 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4479 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4480 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4481 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4482 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4483 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4484 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4485 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4486 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4487 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4488 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4489 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4490 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4491 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4492 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4493 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4494 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4495 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4496 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4497 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4498 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4499 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4500 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4501 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4502 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4503 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4504 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4505 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4506 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4507 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4508 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4509 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4510 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4511 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 4512 }; 4513 4514 intc: interrupt-controller@17a00000 { 4515 compatible = "arm,gic-v3"; 4516 #address-cells = <2>; 4517 #size-cells = <2>; 4518 ranges; 4519 #interrupt-cells = <3>; 4520 interrupt-controller; 4521 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4522 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4523 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4524 4525 gic-its@17a40000 { 4526 compatible = "arm,gic-v3-its"; 4527 msi-controller; 4528 #msi-cells = <1>; 4529 reg = <0 0x17a40000 0 0x20000>; 4530 status = "disabled"; 4531 }; 4532 }; 4533 4534 watchdog@17c10000 { 4535 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 4536 reg = <0 0x17c10000 0 0x1000>; 4537 clocks = <&sleep_clk>; 4538 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4539 }; 4540 4541 timer@17c20000 { 4542 #address-cells = <2>; 4543 #size-cells = <2>; 4544 ranges; 4545 compatible = "arm,armv7-timer-mem"; 4546 reg = <0 0x17c20000 0 0x1000>; 4547 4548 frame@17c21000 { 4549 frame-number = <0>; 4550 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4551 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4552 reg = <0 0x17c21000 0 0x1000>, 4553 <0 0x17c22000 0 0x1000>; 4554 }; 4555 4556 frame@17c23000 { 4557 frame-number = <1>; 4558 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4559 reg = <0 0x17c23000 0 0x1000>; 4560 status = "disabled"; 4561 }; 4562 4563 frame@17c25000 { 4564 frame-number = <2>; 4565 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4566 reg = <0 0x17c25000 0 0x1000>; 4567 status = "disabled"; 4568 }; 4569 4570 frame@17c27000 { 4571 frame-number = <3>; 4572 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4573 reg = <0 0x17c27000 0 0x1000>; 4574 status = "disabled"; 4575 }; 4576 4577 frame@17c29000 { 4578 frame-number = <4>; 4579 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4580 reg = <0 0x17c29000 0 0x1000>; 4581 status = "disabled"; 4582 }; 4583 4584 frame@17c2b000 { 4585 frame-number = <5>; 4586 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4587 reg = <0 0x17c2b000 0 0x1000>; 4588 status = "disabled"; 4589 }; 4590 4591 frame@17c2d000 { 4592 frame-number = <6>; 4593 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4594 reg = <0 0x17c2d000 0 0x1000>; 4595 status = "disabled"; 4596 }; 4597 }; 4598 4599 apps_rsc: rsc@18200000 { 4600 compatible = "qcom,rpmh-rsc"; 4601 reg = <0 0x18200000 0 0x10000>, 4602 <0 0x18210000 0 0x10000>, 4603 <0 0x18220000 0 0x10000>; 4604 reg-names = "drv-0", "drv-1", "drv-2"; 4605 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4606 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4607 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4608 qcom,tcs-offset = <0xd00>; 4609 qcom,drv-id = <2>; 4610 qcom,tcs-config = <ACTIVE_TCS 2>, 4611 <SLEEP_TCS 3>, 4612 <WAKE_TCS 3>, 4613 <CONTROL_TCS 1>; 4614 4615 apps_bcm_voter: bcm-voter { 4616 compatible = "qcom,bcm-voter"; 4617 }; 4618 4619 rpmhpd: power-controller { 4620 compatible = "qcom,sc7280-rpmhpd"; 4621 #power-domain-cells = <1>; 4622 operating-points-v2 = <&rpmhpd_opp_table>; 4623 4624 rpmhpd_opp_table: opp-table { 4625 compatible = "operating-points-v2"; 4626 4627 rpmhpd_opp_ret: opp1 { 4628 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4629 }; 4630 4631 rpmhpd_opp_low_svs: opp2 { 4632 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4633 }; 4634 4635 rpmhpd_opp_svs: opp3 { 4636 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4637 }; 4638 4639 rpmhpd_opp_svs_l1: opp4 { 4640 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4641 }; 4642 4643 rpmhpd_opp_svs_l2: opp5 { 4644 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4645 }; 4646 4647 rpmhpd_opp_nom: opp6 { 4648 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4649 }; 4650 4651 rpmhpd_opp_nom_l1: opp7 { 4652 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4653 }; 4654 4655 rpmhpd_opp_turbo: opp8 { 4656 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4657 }; 4658 4659 rpmhpd_opp_turbo_l1: opp9 { 4660 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4661 }; 4662 }; 4663 }; 4664 4665 rpmhcc: clock-controller { 4666 compatible = "qcom,sc7280-rpmh-clk"; 4667 clocks = <&xo_board>; 4668 clock-names = "xo"; 4669 #clock-cells = <1>; 4670 }; 4671 }; 4672 4673 epss_l3: interconnect@18590000 { 4674 compatible = "qcom,sc7280-epss-l3"; 4675 reg = <0 0x18590000 0 0x1000>; 4676 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4677 clock-names = "xo", "alternate"; 4678 #interconnect-cells = <1>; 4679 }; 4680 4681 cpufreq_hw: cpufreq@18591000 { 4682 compatible = "qcom,cpufreq-epss"; 4683 reg = <0 0x18591000 0 0x1000>, 4684 <0 0x18592000 0 0x1000>, 4685 <0 0x18593000 0 0x1000>; 4686 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4687 clock-names = "xo", "alternate"; 4688 #freq-domain-cells = <1>; 4689 }; 4690 }; 4691 4692 thermal_zones: thermal-zones { 4693 cpu0-thermal { 4694 polling-delay-passive = <250>; 4695 polling-delay = <0>; 4696 4697 thermal-sensors = <&tsens0 1>; 4698 4699 trips { 4700 cpu0_alert0: trip-point0 { 4701 temperature = <90000>; 4702 hysteresis = <2000>; 4703 type = "passive"; 4704 }; 4705 4706 cpu0_alert1: trip-point1 { 4707 temperature = <95000>; 4708 hysteresis = <2000>; 4709 type = "passive"; 4710 }; 4711 4712 cpu0_crit: cpu-crit { 4713 temperature = <110000>; 4714 hysteresis = <0>; 4715 type = "critical"; 4716 }; 4717 }; 4718 4719 cooling-maps { 4720 map0 { 4721 trip = <&cpu0_alert0>; 4722 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4723 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4726 }; 4727 map1 { 4728 trip = <&cpu0_alert1>; 4729 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4730 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4731 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4732 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4733 }; 4734 }; 4735 }; 4736 4737 cpu1-thermal { 4738 polling-delay-passive = <250>; 4739 polling-delay = <0>; 4740 4741 thermal-sensors = <&tsens0 2>; 4742 4743 trips { 4744 cpu1_alert0: trip-point0 { 4745 temperature = <90000>; 4746 hysteresis = <2000>; 4747 type = "passive"; 4748 }; 4749 4750 cpu1_alert1: trip-point1 { 4751 temperature = <95000>; 4752 hysteresis = <2000>; 4753 type = "passive"; 4754 }; 4755 4756 cpu1_crit: cpu-crit { 4757 temperature = <110000>; 4758 hysteresis = <0>; 4759 type = "critical"; 4760 }; 4761 }; 4762 4763 cooling-maps { 4764 map0 { 4765 trip = <&cpu1_alert0>; 4766 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4767 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4769 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4770 }; 4771 map1 { 4772 trip = <&cpu1_alert1>; 4773 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4774 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4777 }; 4778 }; 4779 }; 4780 4781 cpu2-thermal { 4782 polling-delay-passive = <250>; 4783 polling-delay = <0>; 4784 4785 thermal-sensors = <&tsens0 3>; 4786 4787 trips { 4788 cpu2_alert0: trip-point0 { 4789 temperature = <90000>; 4790 hysteresis = <2000>; 4791 type = "passive"; 4792 }; 4793 4794 cpu2_alert1: trip-point1 { 4795 temperature = <95000>; 4796 hysteresis = <2000>; 4797 type = "passive"; 4798 }; 4799 4800 cpu2_crit: cpu-crit { 4801 temperature = <110000>; 4802 hysteresis = <0>; 4803 type = "critical"; 4804 }; 4805 }; 4806 4807 cooling-maps { 4808 map0 { 4809 trip = <&cpu2_alert0>; 4810 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4811 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4813 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4814 }; 4815 map1 { 4816 trip = <&cpu2_alert1>; 4817 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4818 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4821 }; 4822 }; 4823 }; 4824 4825 cpu3-thermal { 4826 polling-delay-passive = <250>; 4827 polling-delay = <0>; 4828 4829 thermal-sensors = <&tsens0 4>; 4830 4831 trips { 4832 cpu3_alert0: trip-point0 { 4833 temperature = <90000>; 4834 hysteresis = <2000>; 4835 type = "passive"; 4836 }; 4837 4838 cpu3_alert1: trip-point1 { 4839 temperature = <95000>; 4840 hysteresis = <2000>; 4841 type = "passive"; 4842 }; 4843 4844 cpu3_crit: cpu-crit { 4845 temperature = <110000>; 4846 hysteresis = <0>; 4847 type = "critical"; 4848 }; 4849 }; 4850 4851 cooling-maps { 4852 map0 { 4853 trip = <&cpu3_alert0>; 4854 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4855 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4857 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4858 }; 4859 map1 { 4860 trip = <&cpu3_alert1>; 4861 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4862 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4863 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4864 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4865 }; 4866 }; 4867 }; 4868 4869 cpu4-thermal { 4870 polling-delay-passive = <250>; 4871 polling-delay = <0>; 4872 4873 thermal-sensors = <&tsens0 7>; 4874 4875 trips { 4876 cpu4_alert0: trip-point0 { 4877 temperature = <90000>; 4878 hysteresis = <2000>; 4879 type = "passive"; 4880 }; 4881 4882 cpu4_alert1: trip-point1 { 4883 temperature = <95000>; 4884 hysteresis = <2000>; 4885 type = "passive"; 4886 }; 4887 4888 cpu4_crit: cpu-crit { 4889 temperature = <110000>; 4890 hysteresis = <0>; 4891 type = "critical"; 4892 }; 4893 }; 4894 4895 cooling-maps { 4896 map0 { 4897 trip = <&cpu4_alert0>; 4898 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4899 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4900 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4901 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4902 }; 4903 map1 { 4904 trip = <&cpu4_alert1>; 4905 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4906 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4907 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4908 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4909 }; 4910 }; 4911 }; 4912 4913 cpu5-thermal { 4914 polling-delay-passive = <250>; 4915 polling-delay = <0>; 4916 4917 thermal-sensors = <&tsens0 8>; 4918 4919 trips { 4920 cpu5_alert0: trip-point0 { 4921 temperature = <90000>; 4922 hysteresis = <2000>; 4923 type = "passive"; 4924 }; 4925 4926 cpu5_alert1: trip-point1 { 4927 temperature = <95000>; 4928 hysteresis = <2000>; 4929 type = "passive"; 4930 }; 4931 4932 cpu5_crit: cpu-crit { 4933 temperature = <110000>; 4934 hysteresis = <0>; 4935 type = "critical"; 4936 }; 4937 }; 4938 4939 cooling-maps { 4940 map0 { 4941 trip = <&cpu5_alert0>; 4942 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4943 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4944 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4945 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4946 }; 4947 map1 { 4948 trip = <&cpu5_alert1>; 4949 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4950 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4951 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4952 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4953 }; 4954 }; 4955 }; 4956 4957 cpu6-thermal { 4958 polling-delay-passive = <250>; 4959 polling-delay = <0>; 4960 4961 thermal-sensors = <&tsens0 9>; 4962 4963 trips { 4964 cpu6_alert0: trip-point0 { 4965 temperature = <90000>; 4966 hysteresis = <2000>; 4967 type = "passive"; 4968 }; 4969 4970 cpu6_alert1: trip-point1 { 4971 temperature = <95000>; 4972 hysteresis = <2000>; 4973 type = "passive"; 4974 }; 4975 4976 cpu6_crit: cpu-crit { 4977 temperature = <110000>; 4978 hysteresis = <0>; 4979 type = "critical"; 4980 }; 4981 }; 4982 4983 cooling-maps { 4984 map0 { 4985 trip = <&cpu6_alert0>; 4986 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4987 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4988 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4989 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4990 }; 4991 map1 { 4992 trip = <&cpu6_alert1>; 4993 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4994 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4995 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4996 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4997 }; 4998 }; 4999 }; 5000 5001 cpu7-thermal { 5002 polling-delay-passive = <250>; 5003 polling-delay = <0>; 5004 5005 thermal-sensors = <&tsens0 10>; 5006 5007 trips { 5008 cpu7_alert0: trip-point0 { 5009 temperature = <90000>; 5010 hysteresis = <2000>; 5011 type = "passive"; 5012 }; 5013 5014 cpu7_alert1: trip-point1 { 5015 temperature = <95000>; 5016 hysteresis = <2000>; 5017 type = "passive"; 5018 }; 5019 5020 cpu7_crit: cpu-crit { 5021 temperature = <110000>; 5022 hysteresis = <0>; 5023 type = "critical"; 5024 }; 5025 }; 5026 5027 cooling-maps { 5028 map0 { 5029 trip = <&cpu7_alert0>; 5030 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5031 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5032 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5033 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5034 }; 5035 map1 { 5036 trip = <&cpu7_alert1>; 5037 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5038 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5039 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5041 }; 5042 }; 5043 }; 5044 5045 cpu8-thermal { 5046 polling-delay-passive = <250>; 5047 polling-delay = <0>; 5048 5049 thermal-sensors = <&tsens0 11>; 5050 5051 trips { 5052 cpu8_alert0: trip-point0 { 5053 temperature = <90000>; 5054 hysteresis = <2000>; 5055 type = "passive"; 5056 }; 5057 5058 cpu8_alert1: trip-point1 { 5059 temperature = <95000>; 5060 hysteresis = <2000>; 5061 type = "passive"; 5062 }; 5063 5064 cpu8_crit: cpu-crit { 5065 temperature = <110000>; 5066 hysteresis = <0>; 5067 type = "critical"; 5068 }; 5069 }; 5070 5071 cooling-maps { 5072 map0 { 5073 trip = <&cpu8_alert0>; 5074 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5075 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5076 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5077 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5078 }; 5079 map1 { 5080 trip = <&cpu8_alert1>; 5081 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5082 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5083 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5084 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5085 }; 5086 }; 5087 }; 5088 5089 cpu9-thermal { 5090 polling-delay-passive = <250>; 5091 polling-delay = <0>; 5092 5093 thermal-sensors = <&tsens0 12>; 5094 5095 trips { 5096 cpu9_alert0: trip-point0 { 5097 temperature = <90000>; 5098 hysteresis = <2000>; 5099 type = "passive"; 5100 }; 5101 5102 cpu9_alert1: trip-point1 { 5103 temperature = <95000>; 5104 hysteresis = <2000>; 5105 type = "passive"; 5106 }; 5107 5108 cpu9_crit: cpu-crit { 5109 temperature = <110000>; 5110 hysteresis = <0>; 5111 type = "critical"; 5112 }; 5113 }; 5114 5115 cooling-maps { 5116 map0 { 5117 trip = <&cpu9_alert0>; 5118 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5119 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5120 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5121 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5122 }; 5123 map1 { 5124 trip = <&cpu9_alert1>; 5125 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5126 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5127 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5128 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5129 }; 5130 }; 5131 }; 5132 5133 cpu10-thermal { 5134 polling-delay-passive = <250>; 5135 polling-delay = <0>; 5136 5137 thermal-sensors = <&tsens0 13>; 5138 5139 trips { 5140 cpu10_alert0: trip-point0 { 5141 temperature = <90000>; 5142 hysteresis = <2000>; 5143 type = "passive"; 5144 }; 5145 5146 cpu10_alert1: trip-point1 { 5147 temperature = <95000>; 5148 hysteresis = <2000>; 5149 type = "passive"; 5150 }; 5151 5152 cpu10_crit: cpu-crit { 5153 temperature = <110000>; 5154 hysteresis = <0>; 5155 type = "critical"; 5156 }; 5157 }; 5158 5159 cooling-maps { 5160 map0 { 5161 trip = <&cpu10_alert0>; 5162 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5163 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5164 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5165 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5166 }; 5167 map1 { 5168 trip = <&cpu10_alert1>; 5169 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5170 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5171 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5172 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5173 }; 5174 }; 5175 }; 5176 5177 cpu11-thermal { 5178 polling-delay-passive = <250>; 5179 polling-delay = <0>; 5180 5181 thermal-sensors = <&tsens0 14>; 5182 5183 trips { 5184 cpu11_alert0: trip-point0 { 5185 temperature = <90000>; 5186 hysteresis = <2000>; 5187 type = "passive"; 5188 }; 5189 5190 cpu11_alert1: trip-point1 { 5191 temperature = <95000>; 5192 hysteresis = <2000>; 5193 type = "passive"; 5194 }; 5195 5196 cpu11_crit: cpu-crit { 5197 temperature = <110000>; 5198 hysteresis = <0>; 5199 type = "critical"; 5200 }; 5201 }; 5202 5203 cooling-maps { 5204 map0 { 5205 trip = <&cpu11_alert0>; 5206 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5207 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5208 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5209 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5210 }; 5211 map1 { 5212 trip = <&cpu11_alert1>; 5213 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5214 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5215 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5216 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5217 }; 5218 }; 5219 }; 5220 5221 aoss0-thermal { 5222 polling-delay-passive = <0>; 5223 polling-delay = <0>; 5224 5225 thermal-sensors = <&tsens0 0>; 5226 5227 trips { 5228 aoss0_alert0: trip-point0 { 5229 temperature = <90000>; 5230 hysteresis = <2000>; 5231 type = "hot"; 5232 }; 5233 5234 aoss0_crit: aoss0-crit { 5235 temperature = <110000>; 5236 hysteresis = <0>; 5237 type = "critical"; 5238 }; 5239 }; 5240 }; 5241 5242 aoss1-thermal { 5243 polling-delay-passive = <0>; 5244 polling-delay = <0>; 5245 5246 thermal-sensors = <&tsens1 0>; 5247 5248 trips { 5249 aoss1_alert0: trip-point0 { 5250 temperature = <90000>; 5251 hysteresis = <2000>; 5252 type = "hot"; 5253 }; 5254 5255 aoss1_crit: aoss1-crit { 5256 temperature = <110000>; 5257 hysteresis = <0>; 5258 type = "critical"; 5259 }; 5260 }; 5261 }; 5262 5263 cpuss0-thermal { 5264 polling-delay-passive = <0>; 5265 polling-delay = <0>; 5266 5267 thermal-sensors = <&tsens0 5>; 5268 5269 trips { 5270 cpuss0_alert0: trip-point0 { 5271 temperature = <90000>; 5272 hysteresis = <2000>; 5273 type = "hot"; 5274 }; 5275 cpuss0_crit: cluster0-crit { 5276 temperature = <110000>; 5277 hysteresis = <0>; 5278 type = "critical"; 5279 }; 5280 }; 5281 }; 5282 5283 cpuss1-thermal { 5284 polling-delay-passive = <0>; 5285 polling-delay = <0>; 5286 5287 thermal-sensors = <&tsens0 6>; 5288 5289 trips { 5290 cpuss1_alert0: trip-point0 { 5291 temperature = <90000>; 5292 hysteresis = <2000>; 5293 type = "hot"; 5294 }; 5295 cpuss1_crit: cluster0-crit { 5296 temperature = <110000>; 5297 hysteresis = <0>; 5298 type = "critical"; 5299 }; 5300 }; 5301 }; 5302 5303 gpuss0-thermal { 5304 polling-delay-passive = <100>; 5305 polling-delay = <0>; 5306 5307 thermal-sensors = <&tsens1 1>; 5308 5309 trips { 5310 gpuss0_alert0: trip-point0 { 5311 temperature = <95000>; 5312 hysteresis = <2000>; 5313 type = "passive"; 5314 }; 5315 5316 gpuss0_crit: gpuss0-crit { 5317 temperature = <110000>; 5318 hysteresis = <0>; 5319 type = "critical"; 5320 }; 5321 }; 5322 5323 cooling-maps { 5324 map0 { 5325 trip = <&gpuss0_alert0>; 5326 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5327 }; 5328 }; 5329 }; 5330 5331 gpuss1-thermal { 5332 polling-delay-passive = <100>; 5333 polling-delay = <0>; 5334 5335 thermal-sensors = <&tsens1 2>; 5336 5337 trips { 5338 gpuss1_alert0: trip-point0 { 5339 temperature = <95000>; 5340 hysteresis = <2000>; 5341 type = "passive"; 5342 }; 5343 5344 gpuss1_crit: gpuss1-crit { 5345 temperature = <110000>; 5346 hysteresis = <0>; 5347 type = "critical"; 5348 }; 5349 }; 5350 5351 cooling-maps { 5352 map0 { 5353 trip = <&gpuss1_alert0>; 5354 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5355 }; 5356 }; 5357 }; 5358 5359 nspss0-thermal { 5360 polling-delay-passive = <0>; 5361 polling-delay = <0>; 5362 5363 thermal-sensors = <&tsens1 3>; 5364 5365 trips { 5366 nspss0_alert0: trip-point0 { 5367 temperature = <90000>; 5368 hysteresis = <2000>; 5369 type = "hot"; 5370 }; 5371 5372 nspss0_crit: nspss0-crit { 5373 temperature = <110000>; 5374 hysteresis = <0>; 5375 type = "critical"; 5376 }; 5377 }; 5378 }; 5379 5380 nspss1-thermal { 5381 polling-delay-passive = <0>; 5382 polling-delay = <0>; 5383 5384 thermal-sensors = <&tsens1 4>; 5385 5386 trips { 5387 nspss1_alert0: trip-point0 { 5388 temperature = <90000>; 5389 hysteresis = <2000>; 5390 type = "hot"; 5391 }; 5392 5393 nspss1_crit: nspss1-crit { 5394 temperature = <110000>; 5395 hysteresis = <0>; 5396 type = "critical"; 5397 }; 5398 }; 5399 }; 5400 5401 video-thermal { 5402 polling-delay-passive = <0>; 5403 polling-delay = <0>; 5404 5405 thermal-sensors = <&tsens1 5>; 5406 5407 trips { 5408 video_alert0: trip-point0 { 5409 temperature = <90000>; 5410 hysteresis = <2000>; 5411 type = "hot"; 5412 }; 5413 5414 video_crit: video-crit { 5415 temperature = <110000>; 5416 hysteresis = <0>; 5417 type = "critical"; 5418 }; 5419 }; 5420 }; 5421 5422 ddr-thermal { 5423 polling-delay-passive = <0>; 5424 polling-delay = <0>; 5425 5426 thermal-sensors = <&tsens1 6>; 5427 5428 trips { 5429 ddr_alert0: trip-point0 { 5430 temperature = <90000>; 5431 hysteresis = <2000>; 5432 type = "hot"; 5433 }; 5434 5435 ddr_crit: ddr-crit { 5436 temperature = <110000>; 5437 hysteresis = <0>; 5438 type = "critical"; 5439 }; 5440 }; 5441 }; 5442 5443 mdmss0-thermal { 5444 polling-delay-passive = <0>; 5445 polling-delay = <0>; 5446 5447 thermal-sensors = <&tsens1 7>; 5448 5449 trips { 5450 mdmss0_alert0: trip-point0 { 5451 temperature = <90000>; 5452 hysteresis = <2000>; 5453 type = "hot"; 5454 }; 5455 5456 mdmss0_crit: mdmss0-crit { 5457 temperature = <110000>; 5458 hysteresis = <0>; 5459 type = "critical"; 5460 }; 5461 }; 5462 }; 5463 5464 mdmss1-thermal { 5465 polling-delay-passive = <0>; 5466 polling-delay = <0>; 5467 5468 thermal-sensors = <&tsens1 8>; 5469 5470 trips { 5471 mdmss1_alert0: trip-point0 { 5472 temperature = <90000>; 5473 hysteresis = <2000>; 5474 type = "hot"; 5475 }; 5476 5477 mdmss1_crit: mdmss1-crit { 5478 temperature = <110000>; 5479 hysteresis = <0>; 5480 type = "critical"; 5481 }; 5482 }; 5483 }; 5484 5485 mdmss2-thermal { 5486 polling-delay-passive = <0>; 5487 polling-delay = <0>; 5488 5489 thermal-sensors = <&tsens1 9>; 5490 5491 trips { 5492 mdmss2_alert0: trip-point0 { 5493 temperature = <90000>; 5494 hysteresis = <2000>; 5495 type = "hot"; 5496 }; 5497 5498 mdmss2_crit: mdmss2-crit { 5499 temperature = <110000>; 5500 hysteresis = <0>; 5501 type = "critical"; 5502 }; 5503 }; 5504 }; 5505 5506 mdmss3-thermal { 5507 polling-delay-passive = <0>; 5508 polling-delay = <0>; 5509 5510 thermal-sensors = <&tsens1 10>; 5511 5512 trips { 5513 mdmss3_alert0: trip-point0 { 5514 temperature = <90000>; 5515 hysteresis = <2000>; 5516 type = "hot"; 5517 }; 5518 5519 mdmss3_crit: mdmss3-crit { 5520 temperature = <110000>; 5521 hysteresis = <0>; 5522 type = "critical"; 5523 }; 5524 }; 5525 }; 5526 5527 camera0-thermal { 5528 polling-delay-passive = <0>; 5529 polling-delay = <0>; 5530 5531 thermal-sensors = <&tsens1 11>; 5532 5533 trips { 5534 camera0_alert0: trip-point0 { 5535 temperature = <90000>; 5536 hysteresis = <2000>; 5537 type = "hot"; 5538 }; 5539 5540 camera0_crit: camera0-crit { 5541 temperature = <110000>; 5542 hysteresis = <0>; 5543 type = "critical"; 5544 }; 5545 }; 5546 }; 5547 }; 5548 5549 timer { 5550 compatible = "arm,armv8-timer"; 5551 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5552 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5553 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5554 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5555 }; 5556}; 5557