1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 L3_0: l3-cache { 188 compatible = "cache"; 189 cache-level = <3>; 190 cache-unified; 191 }; 192 }; 193 }; 194 195 CPU1: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x100>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 &LITTLE_CPU_SLEEP_1 226 &CLUSTER_SLEEP_0>; 227 next-level-cache = <&L2_200>; 228 operating-points-v2 = <&cpu0_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 #cooling-cells = <2>; 233 L2_200: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU3: cpu@300 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo"; 244 reg = <0x0 0x300>; 245 clocks = <&cpufreq_hw 0>; 246 enable-method = "psci"; 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 248 &LITTLE_CPU_SLEEP_1 249 &CLUSTER_SLEEP_0>; 250 next-level-cache = <&L2_300>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 254 qcom,freq-domain = <&cpufreq_hw 0>; 255 #cooling-cells = <2>; 256 L2_300: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-unified; 260 next-level-cache = <&L3_0>; 261 }; 262 }; 263 264 CPU4: cpu@400 { 265 device_type = "cpu"; 266 compatible = "qcom,kryo"; 267 reg = <0x0 0x400>; 268 clocks = <&cpufreq_hw 1>; 269 enable-method = "psci"; 270 cpu-idle-states = <&BIG_CPU_SLEEP_0 271 &BIG_CPU_SLEEP_1 272 &CLUSTER_SLEEP_0>; 273 next-level-cache = <&L2_400>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 276 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 L2_400: l2-cache { 280 compatible = "cache"; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo"; 290 reg = <0x0 0x500>; 291 clocks = <&cpufreq_hw 1>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_500>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_500: l2-cache { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-unified; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU6: cpu@600 { 311 device_type = "cpu"; 312 compatible = "qcom,kryo"; 313 reg = <0x0 0x600>; 314 clocks = <&cpufreq_hw 1>; 315 enable-method = "psci"; 316 cpu-idle-states = <&BIG_CPU_SLEEP_0 317 &BIG_CPU_SLEEP_1 318 &CLUSTER_SLEEP_0>; 319 next-level-cache = <&L2_600>; 320 operating-points-v2 = <&cpu4_opp_table>; 321 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 322 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 323 qcom,freq-domain = <&cpufreq_hw 1>; 324 #cooling-cells = <2>; 325 L2_600: l2-cache { 326 compatible = "cache"; 327 cache-level = <2>; 328 cache-unified; 329 next-level-cache = <&L3_0>; 330 }; 331 }; 332 333 CPU7: cpu@700 { 334 device_type = "cpu"; 335 compatible = "qcom,kryo"; 336 reg = <0x0 0x700>; 337 clocks = <&cpufreq_hw 2>; 338 enable-method = "psci"; 339 cpu-idle-states = <&BIG_CPU_SLEEP_0 340 &BIG_CPU_SLEEP_1 341 &CLUSTER_SLEEP_0>; 342 next-level-cache = <&L2_700>; 343 operating-points-v2 = <&cpu7_opp_table>; 344 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 345 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 346 qcom,freq-domain = <&cpufreq_hw 2>; 347 #cooling-cells = <2>; 348 L2_700: l2-cache { 349 compatible = "cache"; 350 cache-level = <2>; 351 cache-unified; 352 next-level-cache = <&L3_0>; 353 }; 354 }; 355 356 cpu-map { 357 cluster0 { 358 core0 { 359 cpu = <&CPU0>; 360 }; 361 362 core1 { 363 cpu = <&CPU1>; 364 }; 365 366 core2 { 367 cpu = <&CPU2>; 368 }; 369 370 core3 { 371 cpu = <&CPU3>; 372 }; 373 374 core4 { 375 cpu = <&CPU4>; 376 }; 377 378 core5 { 379 cpu = <&CPU5>; 380 }; 381 382 core6 { 383 cpu = <&CPU6>; 384 }; 385 386 core7 { 387 cpu = <&CPU7>; 388 }; 389 }; 390 }; 391 392 idle-states { 393 entry-method = "psci"; 394 395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "little-power-down"; 398 arm,psci-suspend-param = <0x40000003>; 399 entry-latency-us = <549>; 400 exit-latency-us = <901>; 401 min-residency-us = <1774>; 402 local-timer-stop; 403 }; 404 405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-down"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <702>; 410 exit-latency-us = <915>; 411 min-residency-us = <4001>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-power-down"; 418 arm,psci-suspend-param = <0x40000003>; 419 entry-latency-us = <523>; 420 exit-latency-us = <1244>; 421 min-residency-us = <2207>; 422 local-timer-stop; 423 }; 424 425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 426 compatible = "arm,idle-state"; 427 idle-state-name = "big-rail-power-down"; 428 arm,psci-suspend-param = <0x40000004>; 429 entry-latency-us = <526>; 430 exit-latency-us = <1854>; 431 min-residency-us = <5555>; 432 local-timer-stop; 433 }; 434 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "cluster-power-down"; 438 arm,psci-suspend-param = <0x40003444>; 439 entry-latency-us = <3263>; 440 exit-latency-us = <6562>; 441 min-residency-us = <9926>; 442 local-timer-stop; 443 }; 444 }; 445 }; 446 447 cpu0_opp_table: opp-table-cpu0 { 448 compatible = "operating-points-v2"; 449 opp-shared; 450 451 cpu0_opp_300mhz: opp-300000000 { 452 opp-hz = /bits/ 64 <300000000>; 453 opp-peak-kBps = <800000 9600000>; 454 }; 455 456 cpu0_opp_691mhz: opp-691200000 { 457 opp-hz = /bits/ 64 <691200000>; 458 opp-peak-kBps = <800000 17817600>; 459 }; 460 461 cpu0_opp_806mhz: opp-806400000 { 462 opp-hz = /bits/ 64 <806400000>; 463 opp-peak-kBps = <800000 20889600>; 464 }; 465 466 cpu0_opp_941mhz: opp-940800000 { 467 opp-hz = /bits/ 64 <940800000>; 468 opp-peak-kBps = <1804000 24576000>; 469 }; 470 471 cpu0_opp_1152mhz: opp-1152000000 { 472 opp-hz = /bits/ 64 <1152000000>; 473 opp-peak-kBps = <2188000 27033600>; 474 }; 475 476 cpu0_opp_1325mhz: opp-1324800000 { 477 opp-hz = /bits/ 64 <1324800000>; 478 opp-peak-kBps = <2188000 33792000>; 479 }; 480 481 cpu0_opp_1517mhz: opp-1516800000 { 482 opp-hz = /bits/ 64 <1516800000>; 483 opp-peak-kBps = <3072000 38092800>; 484 }; 485 486 cpu0_opp_1651mhz: opp-1651200000 { 487 opp-hz = /bits/ 64 <1651200000>; 488 opp-peak-kBps = <3072000 41779200>; 489 }; 490 491 cpu0_opp_1805mhz: opp-1804800000 { 492 opp-hz = /bits/ 64 <1804800000>; 493 opp-peak-kBps = <4068000 48537600>; 494 }; 495 496 cpu0_opp_1958mhz: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <4068000 48537600>; 499 }; 500 501 cpu0_opp_2016mhz: opp-2016000000 { 502 opp-hz = /bits/ 64 <2016000000>; 503 opp-peak-kBps = <6220000 48537600>; 504 }; 505 }; 506 507 cpu4_opp_table: opp-table-cpu4 { 508 compatible = "operating-points-v2"; 509 opp-shared; 510 511 cpu4_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <1804000 9600000>; 514 }; 515 516 cpu4_opp_941mhz: opp-940800000 { 517 opp-hz = /bits/ 64 <940800000>; 518 opp-peak-kBps = <2188000 17817600>; 519 }; 520 521 cpu4_opp_1229mhz: opp-1228800000 { 522 opp-hz = /bits/ 64 <1228800000>; 523 opp-peak-kBps = <4068000 24576000>; 524 }; 525 526 cpu4_opp_1344mhz: opp-1344000000 { 527 opp-hz = /bits/ 64 <1344000000>; 528 opp-peak-kBps = <4068000 24576000>; 529 }; 530 531 cpu4_opp_1517mhz: opp-1516800000 { 532 opp-hz = /bits/ 64 <1516800000>; 533 opp-peak-kBps = <4068000 24576000>; 534 }; 535 536 cpu4_opp_1651mhz: opp-1651200000 { 537 opp-hz = /bits/ 64 <1651200000>; 538 opp-peak-kBps = <6220000 38092800>; 539 }; 540 541 cpu4_opp_1901mhz: opp-1900800000 { 542 opp-hz = /bits/ 64 <1900800000>; 543 opp-peak-kBps = <6220000 44851200>; 544 }; 545 546 cpu4_opp_2054mhz: opp-2054400000 { 547 opp-hz = /bits/ 64 <2054400000>; 548 opp-peak-kBps = <6220000 44851200>; 549 }; 550 551 cpu4_opp_2112mhz: opp-2112000000 { 552 opp-hz = /bits/ 64 <2112000000>; 553 opp-peak-kBps = <6220000 44851200>; 554 }; 555 556 cpu4_opp_2131mhz: opp-2131200000 { 557 opp-hz = /bits/ 64 <2131200000>; 558 opp-peak-kBps = <6220000 44851200>; 559 }; 560 561 cpu4_opp_2208mhz: opp-2208000000 { 562 opp-hz = /bits/ 64 <2208000000>; 563 opp-peak-kBps = <6220000 44851200>; 564 }; 565 566 cpu4_opp_2400mhz: opp-2400000000 { 567 opp-hz = /bits/ 64 <2400000000>; 568 opp-peak-kBps = <8532000 48537600>; 569 }; 570 571 cpu4_opp_2611mhz: opp-2611200000 { 572 opp-hz = /bits/ 64 <2611200000>; 573 opp-peak-kBps = <8532000 48537600>; 574 }; 575 }; 576 577 cpu7_opp_table: opp-table-cpu7 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 cpu7_opp_806mhz: opp-806400000 { 582 opp-hz = /bits/ 64 <806400000>; 583 opp-peak-kBps = <1804000 9600000>; 584 }; 585 586 cpu7_opp_1056mhz: opp-1056000000 { 587 opp-hz = /bits/ 64 <1056000000>; 588 opp-peak-kBps = <2188000 17817600>; 589 }; 590 591 cpu7_opp_1325mhz: opp-1324800000 { 592 opp-hz = /bits/ 64 <1324800000>; 593 opp-peak-kBps = <4068000 24576000>; 594 }; 595 596 cpu7_opp_1517mhz: opp-1516800000 { 597 opp-hz = /bits/ 64 <1516800000>; 598 opp-peak-kBps = <4068000 24576000>; 599 }; 600 601 cpu7_opp_1766mhz: opp-1766400000 { 602 opp-hz = /bits/ 64 <1766400000>; 603 opp-peak-kBps = <6220000 38092800>; 604 }; 605 606 cpu7_opp_1862mhz: opp-1862400000 { 607 opp-hz = /bits/ 64 <1862400000>; 608 opp-peak-kBps = <6220000 38092800>; 609 }; 610 611 cpu7_opp_2035mhz: opp-2035200000 { 612 opp-hz = /bits/ 64 <2035200000>; 613 opp-peak-kBps = <6220000 38092800>; 614 }; 615 616 cpu7_opp_2112mhz: opp-2112000000 { 617 opp-hz = /bits/ 64 <2112000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu7_opp_2208mhz: opp-2208000000 { 622 opp-hz = /bits/ 64 <2208000000>; 623 opp-peak-kBps = <6220000 44851200>; 624 }; 625 626 cpu7_opp_2381mhz: opp-2380800000 { 627 opp-hz = /bits/ 64 <2380800000>; 628 opp-peak-kBps = <6832000 44851200>; 629 }; 630 631 cpu7_opp_2400mhz: opp-2400000000 { 632 opp-hz = /bits/ 64 <2400000000>; 633 opp-peak-kBps = <8532000 48537600>; 634 }; 635 636 cpu7_opp_2515mhz: opp-2515200000 { 637 opp-hz = /bits/ 64 <2515200000>; 638 opp-peak-kBps = <8532000 48537600>; 639 }; 640 641 cpu7_opp_2707mhz: opp-2707200000 { 642 opp-hz = /bits/ 64 <2707200000>; 643 opp-peak-kBps = <8532000 48537600>; 644 }; 645 646 cpu7_opp_3014mhz: opp-3014400000 { 647 opp-hz = /bits/ 64 <3014400000>; 648 opp-peak-kBps = <8532000 48537600>; 649 }; 650 }; 651 652 memory@80000000 { 653 device_type = "memory"; 654 /* We expect the bootloader to fill in the size */ 655 reg = <0 0x80000000 0 0>; 656 }; 657 658 firmware { 659 scm: scm { 660 compatible = "qcom,scm-sc7280", "qcom,scm"; 661 }; 662 }; 663 664 clk_virt: interconnect { 665 compatible = "qcom,sc7280-clk-virt"; 666 #interconnect-cells = <2>; 667 qcom,bcm-voters = <&apps_bcm_voter>; 668 }; 669 670 smem { 671 compatible = "qcom,smem"; 672 memory-region = <&smem_mem>; 673 hwlocks = <&tcsr_mutex 3>; 674 }; 675 676 smp2p-adsp { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 680 IPCC_MPROC_SIGNAL_SMP2P 681 IRQ_TYPE_EDGE_RISING>; 682 mboxes = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <2>; 687 688 adsp_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 adsp_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-cdsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <94>, <432>; 703 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 mboxes = <&ipcc IPCC_CLIENT_CDSP 707 IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-mpss { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <435>, <428>; 727 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 mboxes = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <1>; 735 736 modem_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 modem_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 ipa_smp2p_out: ipa-ap-to-modem { 748 qcom,entry-name = "ipa"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 ipa_smp2p_in: ipa-modem-to-ap { 753 qcom,entry-name = "ipa"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-wpss { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <617>, <616>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_WPSS 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <13>; 770 771 wpss_smp2p_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 wpss_smp2p_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 782 wlan_smp2p_out: wlan-ap-to-wpss { 783 qcom,entry-name = "wlan"; 784 #qcom,smem-state-cells = <1>; 785 }; 786 787 wlan_smp2p_in: wlan-wpss-to-ap { 788 qcom,entry-name = "wlan"; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 }; 792 }; 793 794 pmu { 795 compatible = "arm,armv8-pmuv3"; 796 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 797 }; 798 799 psci { 800 compatible = "arm,psci-1.0"; 801 method = "smc"; 802 }; 803 804 qspi_opp_table: opp-table-qspi { 805 compatible = "operating-points-v2"; 806 807 opp-75000000 { 808 opp-hz = /bits/ 64 <75000000>; 809 required-opps = <&rpmhpd_opp_low_svs>; 810 }; 811 812 opp-150000000 { 813 opp-hz = /bits/ 64 <150000000>; 814 required-opps = <&rpmhpd_opp_svs>; 815 }; 816 817 opp-200000000 { 818 opp-hz = /bits/ 64 <200000000>; 819 required-opps = <&rpmhpd_opp_svs_l1>; 820 }; 821 822 opp-300000000 { 823 opp-hz = /bits/ 64 <300000000>; 824 required-opps = <&rpmhpd_opp_nom>; 825 }; 826 }; 827 828 qup_opp_table: opp-table-qup { 829 compatible = "operating-points-v2"; 830 831 opp-75000000 { 832 opp-hz = /bits/ 64 <75000000>; 833 required-opps = <&rpmhpd_opp_low_svs>; 834 }; 835 836 opp-100000000 { 837 opp-hz = /bits/ 64 <100000000>; 838 required-opps = <&rpmhpd_opp_svs>; 839 }; 840 841 opp-128000000 { 842 opp-hz = /bits/ 64 <128000000>; 843 required-opps = <&rpmhpd_opp_nom>; 844 }; 845 }; 846 847 soc: soc@0 { 848 #address-cells = <2>; 849 #size-cells = <2>; 850 ranges = <0 0 0 0 0x10 0>; 851 dma-ranges = <0 0 0 0 0x10 0>; 852 compatible = "simple-bus"; 853 854 gcc: clock-controller@100000 { 855 compatible = "qcom,gcc-sc7280"; 856 reg = <0 0x00100000 0 0x1f0000>; 857 clocks = <&rpmhcc RPMH_CXO_CLK>, 858 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 859 <0>, <&pcie1_lane>, 860 <0>, <0>, <0>, 861 <&usb_1_ssphy>; 862 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 863 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 864 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 865 "ufs_phy_tx_symbol_0_clk", 866 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 #power-domain-cells = <1>; 870 power-domains = <&rpmhpd SC7280_CX>; 871 }; 872 873 ipcc: mailbox@408000 { 874 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 875 reg = <0 0x00408000 0 0x1000>; 876 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-controller; 878 #interrupt-cells = <3>; 879 #mbox-cells = <2>; 880 }; 881 882 qfprom: efuse@784000 { 883 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 884 reg = <0 0x00784000 0 0xa20>, 885 <0 0x00780000 0 0xa20>, 886 <0 0x00782000 0 0x120>, 887 <0 0x00786000 0 0x1fff>; 888 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 889 clock-names = "core"; 890 power-domains = <&rpmhpd SC7280_MX>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 894 gpu_speed_bin: gpu_speed_bin@1e9 { 895 reg = <0x1e9 0x2>; 896 bits = <5 8>; 897 }; 898 }; 899 900 sdhc_1: mmc@7c4000 { 901 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 902 pinctrl-names = "default", "sleep"; 903 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 904 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 905 status = "disabled"; 906 907 reg = <0 0x007c4000 0 0x1000>, 908 <0 0x007c5000 0 0x1000>; 909 reg-names = "hc", "cqhci"; 910 911 iommus = <&apps_smmu 0xc0 0x0>; 912 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "hc_irq", "pwr_irq"; 915 916 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 917 <&gcc GCC_SDCC1_APPS_CLK>, 918 <&rpmhcc RPMH_CXO_CLK>; 919 clock-names = "iface", "core", "xo"; 920 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 922 interconnect-names = "sdhc-ddr","cpu-sdhc"; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&sdhc1_opp_table>; 925 926 bus-width = <8>; 927 supports-cqe; 928 929 qcom,dll-config = <0x0007642c>; 930 qcom,ddr-config = <0x80040868>; 931 932 mmc-ddr-1_8v; 933 mmc-hs200-1_8v; 934 mmc-hs400-1_8v; 935 mmc-hs400-enhanced-strobe; 936 937 resets = <&gcc GCC_SDCC1_BCR>; 938 939 sdhc1_opp_table: opp-table { 940 compatible = "operating-points-v2"; 941 942 opp-100000000 { 943 opp-hz = /bits/ 64 <100000000>; 944 required-opps = <&rpmhpd_opp_low_svs>; 945 opp-peak-kBps = <1800000 400000>; 946 opp-avg-kBps = <100000 0>; 947 }; 948 949 opp-384000000 { 950 opp-hz = /bits/ 64 <384000000>; 951 required-opps = <&rpmhpd_opp_nom>; 952 opp-peak-kBps = <5400000 1600000>; 953 opp-avg-kBps = <390000 0>; 954 }; 955 }; 956 }; 957 958 gpi_dma0: dma-controller@900000 { 959 #dma-cells = <3>; 960 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 961 reg = <0 0x00900000 0 0x60000>; 962 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 974 dma-channels = <12>; 975 dma-channel-mask = <0x7f>; 976 iommus = <&apps_smmu 0x0136 0x0>; 977 status = "disabled"; 978 }; 979 980 qupv3_id_0: geniqup@9c0000 { 981 compatible = "qcom,geni-se-qup"; 982 reg = <0 0x009c0000 0 0x2000>; 983 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 984 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 985 clock-names = "m-ahb", "s-ahb"; 986 #address-cells = <2>; 987 #size-cells = <2>; 988 ranges; 989 iommus = <&apps_smmu 0x123 0x0>; 990 status = "disabled"; 991 992 i2c0: i2c@980000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0 0x00980000 0 0x4000>; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 996 clock-names = "se"; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_i2c0_data_clk>; 999 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1003 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1004 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1005 interconnect-names = "qup-core", "qup-config", 1006 "qup-memory"; 1007 power-domains = <&rpmhpd SC7280_CX>; 1008 required-opps = <&rpmhpd_opp_low_svs>; 1009 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1010 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1011 dma-names = "tx", "rx"; 1012 status = "disabled"; 1013 }; 1014 1015 spi0: spi@980000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00980000 0 0x4000>; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1019 clock-names = "se"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1022 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 power-domains = <&rpmhpd SC7280_CX>; 1026 operating-points-v2 = <&qup_opp_table>; 1027 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1028 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1029 interconnect-names = "qup-core", "qup-config"; 1030 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1031 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1032 dma-names = "tx", "rx"; 1033 status = "disabled"; 1034 }; 1035 1036 uart0: serial@980000 { 1037 compatible = "qcom,geni-uart"; 1038 reg = <0 0x00980000 0 0x4000>; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1040 clock-names = "se"; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1043 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SC7280_CX>; 1045 operating-points-v2 = <&qup_opp_table>; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1048 interconnect-names = "qup-core", "qup-config"; 1049 status = "disabled"; 1050 }; 1051 1052 i2c1: i2c@984000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x00984000 0 0x4000>; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1056 clock-names = "se"; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_i2c1_data_clk>; 1059 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1063 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1064 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1065 interconnect-names = "qup-core", "qup-config", 1066 "qup-memory"; 1067 power-domains = <&rpmhpd SC7280_CX>; 1068 required-opps = <&rpmhpd_opp_low_svs>; 1069 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1070 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1071 dma-names = "tx", "rx"; 1072 status = "disabled"; 1073 }; 1074 1075 spi1: spi@984000 { 1076 compatible = "qcom,geni-spi"; 1077 reg = <0 0x00984000 0 0x4000>; 1078 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1079 clock-names = "se"; 1080 pinctrl-names = "default"; 1081 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1082 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 power-domains = <&rpmhpd SC7280_CX>; 1086 operating-points-v2 = <&qup_opp_table>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1088 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1089 interconnect-names = "qup-core", "qup-config"; 1090 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1091 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1092 dma-names = "tx", "rx"; 1093 status = "disabled"; 1094 }; 1095 1096 uart1: serial@984000 { 1097 compatible = "qcom,geni-uart"; 1098 reg = <0 0x00984000 0 0x4000>; 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1100 clock-names = "se"; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1103 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1104 power-domains = <&rpmhpd SC7280_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1107 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1108 interconnect-names = "qup-core", "qup-config"; 1109 status = "disabled"; 1110 }; 1111 1112 i2c2: i2c@988000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00988000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1116 clock-names = "se"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c2_data_clk>; 1119 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1124 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1125 interconnect-names = "qup-core", "qup-config", 1126 "qup-memory"; 1127 power-domains = <&rpmhpd SC7280_CX>; 1128 required-opps = <&rpmhpd_opp_low_svs>; 1129 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1130 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1131 dma-names = "tx", "rx"; 1132 status = "disabled"; 1133 }; 1134 1135 spi2: spi@988000 { 1136 compatible = "qcom,geni-spi"; 1137 reg = <0 0x00988000 0 0x4000>; 1138 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1139 clock-names = "se"; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1142 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 power-domains = <&rpmhpd SC7280_CX>; 1146 operating-points-v2 = <&qup_opp_table>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1148 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1149 interconnect-names = "qup-core", "qup-config"; 1150 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1151 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1152 dma-names = "tx", "rx"; 1153 status = "disabled"; 1154 }; 1155 1156 uart2: serial@988000 { 1157 compatible = "qcom,geni-uart"; 1158 reg = <0 0x00988000 0 0x4000>; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1160 clock-names = "se"; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1163 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1164 power-domains = <&rpmhpd SC7280_CX>; 1165 operating-points-v2 = <&qup_opp_table>; 1166 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1167 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1168 interconnect-names = "qup-core", "qup-config"; 1169 status = "disabled"; 1170 }; 1171 1172 i2c3: i2c@98c000 { 1173 compatible = "qcom,geni-i2c"; 1174 reg = <0 0x0098c000 0 0x4000>; 1175 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1176 clock-names = "se"; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&qup_i2c3_data_clk>; 1179 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1184 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1185 interconnect-names = "qup-core", "qup-config", 1186 "qup-memory"; 1187 power-domains = <&rpmhpd SC7280_CX>; 1188 required-opps = <&rpmhpd_opp_low_svs>; 1189 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1190 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1191 dma-names = "tx", "rx"; 1192 status = "disabled"; 1193 }; 1194 1195 spi3: spi@98c000 { 1196 compatible = "qcom,geni-spi"; 1197 reg = <0 0x0098c000 0 0x4000>; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1199 clock-names = "se"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1202 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 power-domains = <&rpmhpd SC7280_CX>; 1206 operating-points-v2 = <&qup_opp_table>; 1207 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1208 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1209 interconnect-names = "qup-core", "qup-config"; 1210 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1211 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1212 dma-names = "tx", "rx"; 1213 status = "disabled"; 1214 }; 1215 1216 uart3: serial@98c000 { 1217 compatible = "qcom,geni-uart"; 1218 reg = <0 0x0098c000 0 0x4000>; 1219 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1220 clock-names = "se"; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1223 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1224 power-domains = <&rpmhpd SC7280_CX>; 1225 operating-points-v2 = <&qup_opp_table>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1228 interconnect-names = "qup-core", "qup-config"; 1229 status = "disabled"; 1230 }; 1231 1232 i2c4: i2c@990000 { 1233 compatible = "qcom,geni-i2c"; 1234 reg = <0 0x00990000 0 0x4000>; 1235 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1236 clock-names = "se"; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_i2c4_data_clk>; 1239 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1244 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", 1246 "qup-memory"; 1247 power-domains = <&rpmhpd SC7280_CX>; 1248 required-opps = <&rpmhpd_opp_low_svs>; 1249 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1250 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1251 dma-names = "tx", "rx"; 1252 status = "disabled"; 1253 }; 1254 1255 spi4: spi@990000 { 1256 compatible = "qcom,geni-spi"; 1257 reg = <0 0x00990000 0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1259 clock-names = "se"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1262 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 power-domains = <&rpmhpd SC7280_CX>; 1266 operating-points-v2 = <&qup_opp_table>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1271 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1272 dma-names = "tx", "rx"; 1273 status = "disabled"; 1274 }; 1275 1276 uart4: serial@990000 { 1277 compatible = "qcom,geni-uart"; 1278 reg = <0 0x00990000 0 0x4000>; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1280 clock-names = "se"; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1283 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1284 power-domains = <&rpmhpd SC7280_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1288 interconnect-names = "qup-core", "qup-config"; 1289 status = "disabled"; 1290 }; 1291 1292 i2c5: i2c@994000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00994000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1296 clock-names = "se"; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c5_data_clk>; 1299 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1304 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1305 interconnect-names = "qup-core", "qup-config", 1306 "qup-memory"; 1307 power-domains = <&rpmhpd SC7280_CX>; 1308 required-opps = <&rpmhpd_opp_low_svs>; 1309 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1310 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1311 dma-names = "tx", "rx"; 1312 status = "disabled"; 1313 }; 1314 1315 spi5: spi@994000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0 0x00994000 0 0x4000>; 1318 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1319 clock-names = "se"; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1322 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 power-domains = <&rpmhpd SC7280_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1328 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1329 interconnect-names = "qup-core", "qup-config"; 1330 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1331 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1332 dma-names = "tx", "rx"; 1333 status = "disabled"; 1334 }; 1335 1336 uart5: serial@994000 { 1337 compatible = "qcom,geni-uart"; 1338 reg = <0 0x00994000 0 0x4000>; 1339 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1340 clock-names = "se"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1343 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd SC7280_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1348 interconnect-names = "qup-core", "qup-config"; 1349 status = "disabled"; 1350 }; 1351 1352 i2c6: i2c@998000 { 1353 compatible = "qcom,geni-i2c"; 1354 reg = <0 0x00998000 0 0x4000>; 1355 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1356 clock-names = "se"; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_i2c6_data_clk>; 1359 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", 1366 "qup-memory"; 1367 power-domains = <&rpmhpd SC7280_CX>; 1368 required-opps = <&rpmhpd_opp_low_svs>; 1369 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1370 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1371 dma-names = "tx", "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 spi6: spi@998000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0 0x00998000 0 0x4000>; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1379 clock-names = "se"; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1382 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 power-domains = <&rpmhpd SC7280_CX>; 1386 operating-points-v2 = <&qup_opp_table>; 1387 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1388 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1389 interconnect-names = "qup-core", "qup-config"; 1390 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1391 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1392 dma-names = "tx", "rx"; 1393 status = "disabled"; 1394 }; 1395 1396 uart6: serial@998000 { 1397 compatible = "qcom,geni-uart"; 1398 reg = <0 0x00998000 0 0x4000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1400 clock-names = "se"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1403 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1404 power-domains = <&rpmhpd SC7280_CX>; 1405 operating-points-v2 = <&qup_opp_table>; 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1407 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1408 interconnect-names = "qup-core", "qup-config"; 1409 status = "disabled"; 1410 }; 1411 1412 i2c7: i2c@99c000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x0099c000 0 0x4000>; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1416 clock-names = "se"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c7_data_clk>; 1419 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1424 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1425 interconnect-names = "qup-core", "qup-config", 1426 "qup-memory"; 1427 power-domains = <&rpmhpd SC7280_CX>; 1428 required-opps = <&rpmhpd_opp_low_svs>; 1429 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1430 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1431 dma-names = "tx", "rx"; 1432 status = "disabled"; 1433 }; 1434 1435 spi7: spi@99c000 { 1436 compatible = "qcom,geni-spi"; 1437 reg = <0 0x0099c000 0 0x4000>; 1438 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1439 clock-names = "se"; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1442 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 power-domains = <&rpmhpd SC7280_CX>; 1446 operating-points-v2 = <&qup_opp_table>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1451 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1452 dma-names = "tx", "rx"; 1453 status = "disabled"; 1454 }; 1455 1456 uart7: serial@99c000 { 1457 compatible = "qcom,geni-uart"; 1458 reg = <0 0x0099c000 0 0x4000>; 1459 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1460 clock-names = "se"; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1463 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1464 power-domains = <&rpmhpd SC7280_CX>; 1465 operating-points-v2 = <&qup_opp_table>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1467 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1468 interconnect-names = "qup-core", "qup-config"; 1469 status = "disabled"; 1470 }; 1471 }; 1472 1473 gpi_dma1: dma-controller@a00000 { 1474 #dma-cells = <3>; 1475 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1476 reg = <0 0x00a00000 0 0x60000>; 1477 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1489 dma-channels = <12>; 1490 dma-channel-mask = <0x1e>; 1491 iommus = <&apps_smmu 0x56 0x0>; 1492 status = "disabled"; 1493 }; 1494 1495 qupv3_id_1: geniqup@ac0000 { 1496 compatible = "qcom,geni-se-qup"; 1497 reg = <0 0x00ac0000 0 0x2000>; 1498 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1499 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1500 clock-names = "m-ahb", "s-ahb"; 1501 #address-cells = <2>; 1502 #size-cells = <2>; 1503 ranges; 1504 iommus = <&apps_smmu 0x43 0x0>; 1505 status = "disabled"; 1506 1507 i2c8: i2c@a80000 { 1508 compatible = "qcom,geni-i2c"; 1509 reg = <0 0x00a80000 0 0x4000>; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1511 clock-names = "se"; 1512 pinctrl-names = "default"; 1513 pinctrl-0 = <&qup_i2c8_data_clk>; 1514 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1518 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1519 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1520 interconnect-names = "qup-core", "qup-config", 1521 "qup-memory"; 1522 power-domains = <&rpmhpd SC7280_CX>; 1523 required-opps = <&rpmhpd_opp_low_svs>; 1524 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1525 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1526 dma-names = "tx", "rx"; 1527 status = "disabled"; 1528 }; 1529 1530 spi8: spi@a80000 { 1531 compatible = "qcom,geni-spi"; 1532 reg = <0 0x00a80000 0 0x4000>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1534 clock-names = "se"; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1537 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 power-domains = <&rpmhpd SC7280_CX>; 1541 operating-points-v2 = <&qup_opp_table>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1543 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1544 interconnect-names = "qup-core", "qup-config"; 1545 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1546 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1547 dma-names = "tx", "rx"; 1548 status = "disabled"; 1549 }; 1550 1551 uart8: serial@a80000 { 1552 compatible = "qcom,geni-uart"; 1553 reg = <0 0x00a80000 0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1555 clock-names = "se"; 1556 pinctrl-names = "default"; 1557 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1559 power-domains = <&rpmhpd SC7280_CX>; 1560 operating-points-v2 = <&qup_opp_table>; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1562 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1563 interconnect-names = "qup-core", "qup-config"; 1564 status = "disabled"; 1565 }; 1566 1567 i2c9: i2c@a84000 { 1568 compatible = "qcom,geni-i2c"; 1569 reg = <0 0x00a84000 0 0x4000>; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 clock-names = "se"; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_i2c9_data_clk>; 1574 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1578 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1579 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1580 interconnect-names = "qup-core", "qup-config", 1581 "qup-memory"; 1582 power-domains = <&rpmhpd SC7280_CX>; 1583 required-opps = <&rpmhpd_opp_low_svs>; 1584 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1585 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1586 dma-names = "tx", "rx"; 1587 status = "disabled"; 1588 }; 1589 1590 spi9: spi@a84000 { 1591 compatible = "qcom,geni-spi"; 1592 reg = <0 0x00a84000 0 0x4000>; 1593 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1594 clock-names = "se"; 1595 pinctrl-names = "default"; 1596 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1597 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 power-domains = <&rpmhpd SC7280_CX>; 1601 operating-points-v2 = <&qup_opp_table>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1604 interconnect-names = "qup-core", "qup-config"; 1605 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1606 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1607 dma-names = "tx", "rx"; 1608 status = "disabled"; 1609 }; 1610 1611 uart9: serial@a84000 { 1612 compatible = "qcom,geni-uart"; 1613 reg = <0 0x00a84000 0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1615 clock-names = "se"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1618 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1619 power-domains = <&rpmhpd SC7280_CX>; 1620 operating-points-v2 = <&qup_opp_table>; 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1622 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1623 interconnect-names = "qup-core", "qup-config"; 1624 status = "disabled"; 1625 }; 1626 1627 i2c10: i2c@a88000 { 1628 compatible = "qcom,geni-i2c"; 1629 reg = <0 0x00a88000 0 0x4000>; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1631 clock-names = "se"; 1632 pinctrl-names = "default"; 1633 pinctrl-0 = <&qup_i2c10_data_clk>; 1634 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1639 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1640 interconnect-names = "qup-core", "qup-config", 1641 "qup-memory"; 1642 power-domains = <&rpmhpd SC7280_CX>; 1643 required-opps = <&rpmhpd_opp_low_svs>; 1644 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1645 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1646 dma-names = "tx", "rx"; 1647 status = "disabled"; 1648 }; 1649 1650 spi10: spi@a88000 { 1651 compatible = "qcom,geni-spi"; 1652 reg = <0 0x00a88000 0 0x4000>; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1654 clock-names = "se"; 1655 pinctrl-names = "default"; 1656 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1657 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 power-domains = <&rpmhpd SC7280_CX>; 1661 operating-points-v2 = <&qup_opp_table>; 1662 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1663 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1664 interconnect-names = "qup-core", "qup-config"; 1665 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1666 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1667 dma-names = "tx", "rx"; 1668 status = "disabled"; 1669 }; 1670 1671 uart10: serial@a88000 { 1672 compatible = "qcom,geni-uart"; 1673 reg = <0 0x00a88000 0 0x4000>; 1674 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1675 clock-names = "se"; 1676 pinctrl-names = "default"; 1677 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1678 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1679 power-domains = <&rpmhpd SC7280_CX>; 1680 operating-points-v2 = <&qup_opp_table>; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1683 interconnect-names = "qup-core", "qup-config"; 1684 status = "disabled"; 1685 }; 1686 1687 i2c11: i2c@a8c000 { 1688 compatible = "qcom,geni-i2c"; 1689 reg = <0 0x00a8c000 0 0x4000>; 1690 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1691 clock-names = "se"; 1692 pinctrl-names = "default"; 1693 pinctrl-0 = <&qup_i2c11_data_clk>; 1694 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1699 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", 1701 "qup-memory"; 1702 power-domains = <&rpmhpd SC7280_CX>; 1703 required-opps = <&rpmhpd_opp_low_svs>; 1704 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1705 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1706 dma-names = "tx", "rx"; 1707 status = "disabled"; 1708 }; 1709 1710 spi11: spi@a8c000 { 1711 compatible = "qcom,geni-spi"; 1712 reg = <0 0x00a8c000 0 0x4000>; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1714 clock-names = "se"; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1717 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 power-domains = <&rpmhpd SC7280_CX>; 1721 operating-points-v2 = <&qup_opp_table>; 1722 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1723 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1724 interconnect-names = "qup-core", "qup-config"; 1725 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1726 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1727 dma-names = "tx", "rx"; 1728 status = "disabled"; 1729 }; 1730 1731 uart11: serial@a8c000 { 1732 compatible = "qcom,geni-uart"; 1733 reg = <0 0x00a8c000 0 0x4000>; 1734 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1735 clock-names = "se"; 1736 pinctrl-names = "default"; 1737 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1738 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1739 power-domains = <&rpmhpd SC7280_CX>; 1740 operating-points-v2 = <&qup_opp_table>; 1741 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1742 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1743 interconnect-names = "qup-core", "qup-config"; 1744 status = "disabled"; 1745 }; 1746 1747 i2c12: i2c@a90000 { 1748 compatible = "qcom,geni-i2c"; 1749 reg = <0 0x00a90000 0 0x4000>; 1750 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1751 clock-names = "se"; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&qup_i2c12_data_clk>; 1754 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1758 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1759 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1760 interconnect-names = "qup-core", "qup-config", 1761 "qup-memory"; 1762 power-domains = <&rpmhpd SC7280_CX>; 1763 required-opps = <&rpmhpd_opp_low_svs>; 1764 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1765 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1766 dma-names = "tx", "rx"; 1767 status = "disabled"; 1768 }; 1769 1770 spi12: spi@a90000 { 1771 compatible = "qcom,geni-spi"; 1772 reg = <0 0x00a90000 0 0x4000>; 1773 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1774 clock-names = "se"; 1775 pinctrl-names = "default"; 1776 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1777 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 power-domains = <&rpmhpd SC7280_CX>; 1781 operating-points-v2 = <&qup_opp_table>; 1782 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1783 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1784 interconnect-names = "qup-core", "qup-config"; 1785 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1786 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1787 dma-names = "tx", "rx"; 1788 status = "disabled"; 1789 }; 1790 1791 uart12: serial@a90000 { 1792 compatible = "qcom,geni-uart"; 1793 reg = <0 0x00a90000 0 0x4000>; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1795 clock-names = "se"; 1796 pinctrl-names = "default"; 1797 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1798 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1799 power-domains = <&rpmhpd SC7280_CX>; 1800 operating-points-v2 = <&qup_opp_table>; 1801 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1802 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1803 interconnect-names = "qup-core", "qup-config"; 1804 status = "disabled"; 1805 }; 1806 1807 i2c13: i2c@a94000 { 1808 compatible = "qcom,geni-i2c"; 1809 reg = <0 0x00a94000 0 0x4000>; 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1811 clock-names = "se"; 1812 pinctrl-names = "default"; 1813 pinctrl-0 = <&qup_i2c13_data_clk>; 1814 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1818 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1819 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1820 interconnect-names = "qup-core", "qup-config", 1821 "qup-memory"; 1822 power-domains = <&rpmhpd SC7280_CX>; 1823 required-opps = <&rpmhpd_opp_low_svs>; 1824 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1825 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1826 dma-names = "tx", "rx"; 1827 status = "disabled"; 1828 }; 1829 1830 spi13: spi@a94000 { 1831 compatible = "qcom,geni-spi"; 1832 reg = <0 0x00a94000 0 0x4000>; 1833 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1834 clock-names = "se"; 1835 pinctrl-names = "default"; 1836 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1837 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 power-domains = <&rpmhpd SC7280_CX>; 1841 operating-points-v2 = <&qup_opp_table>; 1842 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1843 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1844 interconnect-names = "qup-core", "qup-config"; 1845 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1846 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1847 dma-names = "tx", "rx"; 1848 status = "disabled"; 1849 }; 1850 1851 uart13: serial@a94000 { 1852 compatible = "qcom,geni-uart"; 1853 reg = <0 0x00a94000 0 0x4000>; 1854 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1855 clock-names = "se"; 1856 pinctrl-names = "default"; 1857 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1858 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1859 power-domains = <&rpmhpd SC7280_CX>; 1860 operating-points-v2 = <&qup_opp_table>; 1861 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1862 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1863 interconnect-names = "qup-core", "qup-config"; 1864 status = "disabled"; 1865 }; 1866 1867 i2c14: i2c@a98000 { 1868 compatible = "qcom,geni-i2c"; 1869 reg = <0 0x00a98000 0 0x4000>; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1871 clock-names = "se"; 1872 pinctrl-names = "default"; 1873 pinctrl-0 = <&qup_i2c14_data_clk>; 1874 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1878 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1879 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1880 interconnect-names = "qup-core", "qup-config", 1881 "qup-memory"; 1882 power-domains = <&rpmhpd SC7280_CX>; 1883 required-opps = <&rpmhpd_opp_low_svs>; 1884 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1885 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1886 dma-names = "tx", "rx"; 1887 status = "disabled"; 1888 }; 1889 1890 spi14: spi@a98000 { 1891 compatible = "qcom,geni-spi"; 1892 reg = <0 0x00a98000 0 0x4000>; 1893 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1894 clock-names = "se"; 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1897 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 power-domains = <&rpmhpd SC7280_CX>; 1901 operating-points-v2 = <&qup_opp_table>; 1902 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1903 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1904 interconnect-names = "qup-core", "qup-config"; 1905 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1906 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1907 dma-names = "tx", "rx"; 1908 status = "disabled"; 1909 }; 1910 1911 uart14: serial@a98000 { 1912 compatible = "qcom,geni-uart"; 1913 reg = <0 0x00a98000 0 0x4000>; 1914 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1915 clock-names = "se"; 1916 pinctrl-names = "default"; 1917 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1918 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1919 power-domains = <&rpmhpd SC7280_CX>; 1920 operating-points-v2 = <&qup_opp_table>; 1921 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1922 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1923 interconnect-names = "qup-core", "qup-config"; 1924 status = "disabled"; 1925 }; 1926 1927 i2c15: i2c@a9c000 { 1928 compatible = "qcom,geni-i2c"; 1929 reg = <0 0x00a9c000 0 0x4000>; 1930 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1931 clock-names = "se"; 1932 pinctrl-names = "default"; 1933 pinctrl-0 = <&qup_i2c15_data_clk>; 1934 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1938 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1939 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1940 interconnect-names = "qup-core", "qup-config", 1941 "qup-memory"; 1942 power-domains = <&rpmhpd SC7280_CX>; 1943 required-opps = <&rpmhpd_opp_low_svs>; 1944 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1945 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1946 dma-names = "tx", "rx"; 1947 status = "disabled"; 1948 }; 1949 1950 spi15: spi@a9c000 { 1951 compatible = "qcom,geni-spi"; 1952 reg = <0 0x00a9c000 0 0x4000>; 1953 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1954 clock-names = "se"; 1955 pinctrl-names = "default"; 1956 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1957 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1958 #address-cells = <1>; 1959 #size-cells = <0>; 1960 power-domains = <&rpmhpd SC7280_CX>; 1961 operating-points-v2 = <&qup_opp_table>; 1962 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1963 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1964 interconnect-names = "qup-core", "qup-config"; 1965 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1966 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1967 dma-names = "tx", "rx"; 1968 status = "disabled"; 1969 }; 1970 1971 uart15: serial@a9c000 { 1972 compatible = "qcom,geni-uart"; 1973 reg = <0 0x00a9c000 0 0x4000>; 1974 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1975 clock-names = "se"; 1976 pinctrl-names = "default"; 1977 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1978 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1979 power-domains = <&rpmhpd SC7280_CX>; 1980 operating-points-v2 = <&qup_opp_table>; 1981 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1982 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1983 interconnect-names = "qup-core", "qup-config"; 1984 status = "disabled"; 1985 }; 1986 }; 1987 1988 cnoc2: interconnect@1500000 { 1989 reg = <0 0x01500000 0 0x1000>; 1990 compatible = "qcom,sc7280-cnoc2"; 1991 #interconnect-cells = <2>; 1992 qcom,bcm-voters = <&apps_bcm_voter>; 1993 }; 1994 1995 cnoc3: interconnect@1502000 { 1996 reg = <0 0x01502000 0 0x1000>; 1997 compatible = "qcom,sc7280-cnoc3"; 1998 #interconnect-cells = <2>; 1999 qcom,bcm-voters = <&apps_bcm_voter>; 2000 }; 2001 2002 mc_virt: interconnect@1580000 { 2003 reg = <0 0x01580000 0 0x4>; 2004 compatible = "qcom,sc7280-mc-virt"; 2005 #interconnect-cells = <2>; 2006 qcom,bcm-voters = <&apps_bcm_voter>; 2007 }; 2008 2009 system_noc: interconnect@1680000 { 2010 reg = <0 0x01680000 0 0x15480>; 2011 compatible = "qcom,sc7280-system-noc"; 2012 #interconnect-cells = <2>; 2013 qcom,bcm-voters = <&apps_bcm_voter>; 2014 }; 2015 2016 aggre1_noc: interconnect@16e0000 { 2017 compatible = "qcom,sc7280-aggre1-noc"; 2018 reg = <0 0x016e0000 0 0x1c080>; 2019 #interconnect-cells = <2>; 2020 qcom,bcm-voters = <&apps_bcm_voter>; 2021 }; 2022 2023 aggre2_noc: interconnect@1700000 { 2024 reg = <0 0x01700000 0 0x2b080>; 2025 compatible = "qcom,sc7280-aggre2-noc"; 2026 #interconnect-cells = <2>; 2027 qcom,bcm-voters = <&apps_bcm_voter>; 2028 }; 2029 2030 mmss_noc: interconnect@1740000 { 2031 reg = <0 0x01740000 0 0x1e080>; 2032 compatible = "qcom,sc7280-mmss-noc"; 2033 #interconnect-cells = <2>; 2034 qcom,bcm-voters = <&apps_bcm_voter>; 2035 }; 2036 2037 wifi: wifi@17a10040 { 2038 compatible = "qcom,wcn6750-wifi"; 2039 reg = <0 0x17a10040 0 0x0>; 2040 iommus = <&apps_smmu 0x1c00 0x1>; 2041 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2073 qcom,rproc = <&remoteproc_wpss>; 2074 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2075 status = "disabled"; 2076 qcom,smem-states = <&wlan_smp2p_out 0>; 2077 qcom,smem-state-names = "wlan-smp2p-out"; 2078 }; 2079 2080 pcie1: pci@1c08000 { 2081 compatible = "qcom,pcie-sc7280"; 2082 reg = <0 0x01c08000 0 0x3000>, 2083 <0 0x40000000 0 0xf1d>, 2084 <0 0x40000f20 0 0xa8>, 2085 <0 0x40001000 0 0x1000>, 2086 <0 0x40100000 0 0x100000>; 2087 2088 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2089 device_type = "pci"; 2090 linux,pci-domain = <1>; 2091 bus-range = <0x00 0xff>; 2092 num-lanes = <2>; 2093 2094 #address-cells = <3>; 2095 #size-cells = <2>; 2096 2097 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2098 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2099 2100 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2101 interrupt-names = "msi"; 2102 #interrupt-cells = <1>; 2103 interrupt-map-mask = <0 0 0 0x7>; 2104 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2105 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2106 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2107 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2108 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2110 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2111 <&pcie1_lane>, 2112 <&rpmhcc RPMH_CXO_CLK>, 2113 <&gcc GCC_PCIE_1_AUX_CLK>, 2114 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2115 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2116 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2117 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2118 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2119 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2120 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2121 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2122 2123 clock-names = "pipe", 2124 "pipe_mux", 2125 "phy_pipe", 2126 "ref", 2127 "aux", 2128 "cfg", 2129 "bus_master", 2130 "bus_slave", 2131 "slave_q2a", 2132 "tbu", 2133 "ddrss_sf_tbu", 2134 "aggre0", 2135 "aggre1"; 2136 2137 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2138 assigned-clock-rates = <19200000>; 2139 2140 resets = <&gcc GCC_PCIE_1_BCR>; 2141 reset-names = "pci"; 2142 2143 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2144 2145 phys = <&pcie1_lane>; 2146 phy-names = "pciephy"; 2147 2148 pinctrl-names = "default"; 2149 pinctrl-0 = <&pcie1_clkreq_n>; 2150 2151 dma-coherent; 2152 2153 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2154 <0x100 &apps_smmu 0x1c81 0x1>; 2155 2156 status = "disabled"; 2157 }; 2158 2159 pcie1_phy: phy@1c0e000 { 2160 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2161 reg = <0 0x01c0e000 0 0x1c0>; 2162 #address-cells = <2>; 2163 #size-cells = <2>; 2164 ranges; 2165 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2166 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2167 <&gcc GCC_PCIE_CLKREF_EN>, 2168 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2169 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2170 2171 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2172 reset-names = "phy"; 2173 2174 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2175 assigned-clock-rates = <100000000>; 2176 2177 status = "disabled"; 2178 2179 pcie1_lane: phy@1c0e200 { 2180 reg = <0 0x01c0e200 0 0x170>, 2181 <0 0x01c0e400 0 0x200>, 2182 <0 0x01c0ea00 0 0x1f0>, 2183 <0 0x01c0e600 0 0x170>, 2184 <0 0x01c0e800 0 0x200>, 2185 <0 0x01c0ee00 0 0xf4>; 2186 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2187 clock-names = "pipe0"; 2188 2189 #phy-cells = <0>; 2190 #clock-cells = <0>; 2191 clock-output-names = "pcie_1_pipe_clk"; 2192 }; 2193 }; 2194 2195 ipa: ipa@1e40000 { 2196 compatible = "qcom,sc7280-ipa"; 2197 2198 iommus = <&apps_smmu 0x480 0x0>, 2199 <&apps_smmu 0x482 0x0>; 2200 reg = <0 0x01e40000 0 0x8000>, 2201 <0 0x01e50000 0 0x4ad0>, 2202 <0 0x01e04000 0 0x23000>; 2203 reg-names = "ipa-reg", 2204 "ipa-shared", 2205 "gsi"; 2206 2207 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2208 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2209 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2210 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2211 interrupt-names = "ipa", 2212 "gsi", 2213 "ipa-clock-query", 2214 "ipa-setup-ready"; 2215 2216 clocks = <&rpmhcc RPMH_IPA_CLK>; 2217 clock-names = "core"; 2218 2219 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2221 interconnect-names = "memory", 2222 "config"; 2223 2224 qcom,qmp = <&aoss_qmp>; 2225 2226 qcom,smem-states = <&ipa_smp2p_out 0>, 2227 <&ipa_smp2p_out 1>; 2228 qcom,smem-state-names = "ipa-clock-enabled-valid", 2229 "ipa-clock-enabled"; 2230 2231 status = "disabled"; 2232 }; 2233 2234 tcsr_mutex: hwlock@1f40000 { 2235 compatible = "qcom,tcsr-mutex"; 2236 reg = <0 0x01f40000 0 0x20000>; 2237 #hwlock-cells = <1>; 2238 }; 2239 2240 tcsr_1: syscon@1f60000 { 2241 compatible = "qcom,sc7280-tcsr", "syscon"; 2242 reg = <0 0x01f60000 0 0x20000>; 2243 }; 2244 2245 tcsr_2: syscon@1fc0000 { 2246 compatible = "qcom,sc7280-tcsr", "syscon"; 2247 reg = <0 0x01fc0000 0 0x30000>; 2248 }; 2249 2250 lpasscc: lpasscc@3000000 { 2251 compatible = "qcom,sc7280-lpasscc"; 2252 reg = <0 0x03000000 0 0x40>, 2253 <0 0x03c04000 0 0x4>; 2254 reg-names = "qdsp6ss", "top_cc"; 2255 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2256 clock-names = "iface"; 2257 #clock-cells = <1>; 2258 status = "reserved"; /* Owned by ADSP firmware */ 2259 }; 2260 2261 lpass_rx_macro: codec@3200000 { 2262 compatible = "qcom,sc7280-lpass-rx-macro"; 2263 reg = <0 0x03200000 0 0x1000>; 2264 2265 pinctrl-names = "default"; 2266 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2267 2268 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2269 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2270 <&lpass_va_macro>; 2271 clock-names = "mclk", "npl", "fsgen"; 2272 2273 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2274 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2275 power-domain-names = "macro", "dcodec"; 2276 2277 #clock-cells = <0>; 2278 #sound-dai-cells = <1>; 2279 2280 status = "disabled"; 2281 }; 2282 2283 swr0: soundwire@3210000 { 2284 compatible = "qcom,soundwire-v1.6.0"; 2285 reg = <0 0x03210000 0 0x2000>; 2286 2287 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&lpass_rx_macro>; 2289 clock-names = "iface"; 2290 2291 qcom,din-ports = <0>; 2292 qcom,dout-ports = <5>; 2293 2294 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2295 reset-names = "swr_audio_cgcr"; 2296 2297 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2298 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2299 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2300 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2301 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2302 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2303 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2304 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2305 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2306 2307 #sound-dai-cells = <1>; 2308 #address-cells = <2>; 2309 #size-cells = <0>; 2310 2311 status = "disabled"; 2312 }; 2313 2314 lpass_tx_macro: codec@3220000 { 2315 compatible = "qcom,sc7280-lpass-tx-macro"; 2316 reg = <0 0x03220000 0 0x1000>; 2317 2318 pinctrl-names = "default"; 2319 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2320 2321 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2322 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2323 <&lpass_va_macro>; 2324 clock-names = "mclk", "npl", "fsgen"; 2325 2326 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2327 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2328 power-domain-names = "macro", "dcodec"; 2329 2330 #clock-cells = <0>; 2331 #sound-dai-cells = <1>; 2332 2333 status = "disabled"; 2334 }; 2335 2336 swr1: soundwire@3230000 { 2337 compatible = "qcom,soundwire-v1.6.0"; 2338 reg = <0 0x03230000 0 0x2000>; 2339 2340 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2341 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2342 clocks = <&lpass_tx_macro>; 2343 clock-names = "iface"; 2344 2345 qcom,din-ports = <3>; 2346 qcom,dout-ports = <0>; 2347 2348 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2349 reset-names = "swr_audio_cgcr"; 2350 2351 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2352 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2353 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2354 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2355 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2356 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2357 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2358 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2359 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2360 2361 #sound-dai-cells = <1>; 2362 #address-cells = <2>; 2363 #size-cells = <0>; 2364 2365 status = "disabled"; 2366 }; 2367 2368 lpass_audiocc: clock-controller@3300000 { 2369 compatible = "qcom,sc7280-lpassaudiocc"; 2370 reg = <0 0x03300000 0 0x30000>, 2371 <0 0x032a9000 0 0x1000>; 2372 clocks = <&rpmhcc RPMH_CXO_CLK>, 2373 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2374 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2375 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2376 #clock-cells = <1>; 2377 #power-domain-cells = <1>; 2378 #reset-cells = <1>; 2379 }; 2380 2381 lpass_va_macro: codec@3370000 { 2382 compatible = "qcom,sc7280-lpass-va-macro"; 2383 reg = <0 0x03370000 0 0x1000>; 2384 2385 pinctrl-names = "default"; 2386 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2387 2388 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2389 clock-names = "mclk"; 2390 2391 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2392 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2393 power-domain-names = "macro", "dcodec"; 2394 2395 #clock-cells = <0>; 2396 #sound-dai-cells = <1>; 2397 2398 status = "disabled"; 2399 }; 2400 2401 lpass_aon: clock-controller@3380000 { 2402 compatible = "qcom,sc7280-lpassaoncc"; 2403 reg = <0 0x03380000 0 0x30000>; 2404 clocks = <&rpmhcc RPMH_CXO_CLK>, 2405 <&rpmhcc RPMH_CXO_CLK_A>, 2406 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2407 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2408 #clock-cells = <1>; 2409 #power-domain-cells = <1>; 2410 status = "reserved"; /* Owned by ADSP firmware */ 2411 }; 2412 2413 lpass_core: clock-controller@3900000 { 2414 compatible = "qcom,sc7280-lpasscorecc"; 2415 reg = <0 0x03900000 0 0x50000>; 2416 clocks = <&rpmhcc RPMH_CXO_CLK>; 2417 clock-names = "bi_tcxo"; 2418 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2419 #clock-cells = <1>; 2420 #power-domain-cells = <1>; 2421 status = "reserved"; /* Owned by ADSP firmware */ 2422 }; 2423 2424 lpass_cpu: audio@3987000 { 2425 compatible = "qcom,sc7280-lpass-cpu"; 2426 2427 reg = <0 0x03987000 0 0x68000>, 2428 <0 0x03b00000 0 0x29000>, 2429 <0 0x03260000 0 0xc000>, 2430 <0 0x03280000 0 0x29000>, 2431 <0 0x03340000 0 0x29000>, 2432 <0 0x0336c000 0 0x3000>; 2433 reg-names = "lpass-hdmiif", 2434 "lpass-lpaif", 2435 "lpass-rxtx-cdc-dma-lpm", 2436 "lpass-rxtx-lpaif", 2437 "lpass-va-lpaif", 2438 "lpass-va-cdc-dma-lpm"; 2439 2440 iommus = <&apps_smmu 0x1820 0>, 2441 <&apps_smmu 0x1821 0>, 2442 <&apps_smmu 0x1832 0>; 2443 2444 power-domains = <&rpmhpd SC7280_LCX>; 2445 power-domain-names = "lcx"; 2446 required-opps = <&rpmhpd_opp_nom>; 2447 2448 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2449 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2450 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2451 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2452 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2453 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2454 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2455 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2456 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2457 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2458 clock-names = "aon_cc_audio_hm_h", 2459 "audio_cc_ext_mclk0", 2460 "core_cc_sysnoc_mport_core", 2461 "core_cc_ext_if0_ibit", 2462 "core_cc_ext_if1_ibit", 2463 "audio_cc_codec_mem", 2464 "audio_cc_codec_mem0", 2465 "audio_cc_codec_mem1", 2466 "audio_cc_codec_mem2", 2467 "aon_cc_va_mem0"; 2468 2469 #sound-dai-cells = <1>; 2470 #address-cells = <1>; 2471 #size-cells = <0>; 2472 2473 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2477 interrupt-names = "lpass-irq-lpaif", 2478 "lpass-irq-hdmi", 2479 "lpass-irq-vaif", 2480 "lpass-irq-rxtxif"; 2481 2482 status = "disabled"; 2483 }; 2484 2485 lpass_hm: clock-controller@3c00000 { 2486 compatible = "qcom,sc7280-lpasshm"; 2487 reg = <0 0x03c00000 0 0x28>; 2488 clocks = <&rpmhcc RPMH_CXO_CLK>; 2489 clock-names = "bi_tcxo"; 2490 #clock-cells = <1>; 2491 #power-domain-cells = <1>; 2492 status = "reserved"; /* Owned by ADSP firmware */ 2493 }; 2494 2495 lpass_ag_noc: interconnect@3c40000 { 2496 reg = <0 0x03c40000 0 0xf080>; 2497 compatible = "qcom,sc7280-lpass-ag-noc"; 2498 #interconnect-cells = <2>; 2499 qcom,bcm-voters = <&apps_bcm_voter>; 2500 }; 2501 2502 lpass_tlmm: pinctrl@33c0000 { 2503 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2504 reg = <0 0x033c0000 0x0 0x20000>, 2505 <0 0x03550000 0x0 0x10000>; 2506 qcom,adsp-bypass-mode; 2507 gpio-controller; 2508 #gpio-cells = <2>; 2509 gpio-ranges = <&lpass_tlmm 0 0 15>; 2510 2511 lpass_dmic01_clk: dmic01-clk-state { 2512 pins = "gpio6"; 2513 function = "dmic1_clk"; 2514 }; 2515 2516 lpass_dmic01_data: dmic01-data-state { 2517 pins = "gpio7"; 2518 function = "dmic1_data"; 2519 }; 2520 2521 lpass_dmic23_clk: dmic23-clk-state { 2522 pins = "gpio8"; 2523 function = "dmic2_clk"; 2524 }; 2525 2526 lpass_dmic23_data: dmic23-data-state { 2527 pins = "gpio9"; 2528 function = "dmic2_data"; 2529 }; 2530 2531 lpass_rx_swr_clk: rx-swr-clk-state { 2532 pins = "gpio3"; 2533 function = "swr_rx_clk"; 2534 }; 2535 2536 lpass_rx_swr_data: rx-swr-data-state { 2537 pins = "gpio4", "gpio5"; 2538 function = "swr_rx_data"; 2539 }; 2540 2541 lpass_tx_swr_clk: tx-swr-clk-state { 2542 pins = "gpio0"; 2543 function = "swr_tx_clk"; 2544 }; 2545 2546 lpass_tx_swr_data: tx-swr-data-state { 2547 pins = "gpio1", "gpio2", "gpio14"; 2548 function = "swr_tx_data"; 2549 }; 2550 }; 2551 2552 gpu: gpu@3d00000 { 2553 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2554 reg = <0 0x03d00000 0 0x40000>, 2555 <0 0x03d9e000 0 0x1000>, 2556 <0 0x03d61000 0 0x800>; 2557 reg-names = "kgsl_3d0_reg_memory", 2558 "cx_mem", 2559 "cx_dbgc"; 2560 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2561 iommus = <&adreno_smmu 0 0x401>; 2562 operating-points-v2 = <&gpu_opp_table>; 2563 qcom,gmu = <&gmu>; 2564 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2565 interconnect-names = "gfx-mem"; 2566 #cooling-cells = <2>; 2567 2568 nvmem-cells = <&gpu_speed_bin>; 2569 nvmem-cell-names = "speed_bin"; 2570 2571 gpu_opp_table: opp-table { 2572 compatible = "operating-points-v2"; 2573 2574 opp-315000000 { 2575 opp-hz = /bits/ 64 <315000000>; 2576 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2577 opp-peak-kBps = <1804000>; 2578 opp-supported-hw = <0x03>; 2579 }; 2580 2581 opp-450000000 { 2582 opp-hz = /bits/ 64 <450000000>; 2583 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2584 opp-peak-kBps = <4068000>; 2585 opp-supported-hw = <0x03>; 2586 }; 2587 2588 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2589 opp-550000000-0 { 2590 opp-hz = /bits/ 64 <550000000>; 2591 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2592 opp-peak-kBps = <8368000>; 2593 opp-supported-hw = <0x01>; 2594 }; 2595 2596 opp-550000000-1 { 2597 opp-hz = /bits/ 64 <550000000>; 2598 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2599 opp-peak-kBps = <6832000>; 2600 opp-supported-hw = <0x02>; 2601 }; 2602 2603 opp-608000000 { 2604 opp-hz = /bits/ 64 <608000000>; 2605 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2606 opp-peak-kBps = <8368000>; 2607 opp-supported-hw = <0x02>; 2608 }; 2609 2610 opp-700000000 { 2611 opp-hz = /bits/ 64 <700000000>; 2612 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2613 opp-peak-kBps = <8532000>; 2614 opp-supported-hw = <0x02>; 2615 }; 2616 2617 opp-812000000 { 2618 opp-hz = /bits/ 64 <812000000>; 2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2620 opp-peak-kBps = <8532000>; 2621 opp-supported-hw = <0x02>; 2622 }; 2623 2624 opp-840000000 { 2625 opp-hz = /bits/ 64 <840000000>; 2626 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2627 opp-peak-kBps = <8532000>; 2628 opp-supported-hw = <0x02>; 2629 }; 2630 2631 opp-900000000 { 2632 opp-hz = /bits/ 64 <900000000>; 2633 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2634 opp-peak-kBps = <8532000>; 2635 opp-supported-hw = <0x02>; 2636 }; 2637 }; 2638 }; 2639 2640 gmu: gmu@3d6a000 { 2641 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2642 reg = <0 0x03d6a000 0 0x34000>, 2643 <0 0x3de0000 0 0x10000>, 2644 <0 0x0b290000 0 0x10000>; 2645 reg-names = "gmu", "rscc", "gmu_pdc"; 2646 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2647 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2648 interrupt-names = "hfi", "gmu"; 2649 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2650 <&gpucc GPU_CC_CXO_CLK>, 2651 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2652 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2653 <&gpucc GPU_CC_AHB_CLK>, 2654 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2655 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2656 clock-names = "gmu", 2657 "cxo", 2658 "axi", 2659 "memnoc", 2660 "ahb", 2661 "hub", 2662 "smmu_vote"; 2663 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2664 <&gpucc GPU_CC_GX_GDSC>; 2665 power-domain-names = "cx", 2666 "gx"; 2667 iommus = <&adreno_smmu 5 0x400>; 2668 operating-points-v2 = <&gmu_opp_table>; 2669 2670 gmu_opp_table: opp-table { 2671 compatible = "operating-points-v2"; 2672 2673 opp-200000000 { 2674 opp-hz = /bits/ 64 <200000000>; 2675 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2676 }; 2677 }; 2678 }; 2679 2680 gpucc: clock-controller@3d90000 { 2681 compatible = "qcom,sc7280-gpucc"; 2682 reg = <0 0x03d90000 0 0x9000>; 2683 clocks = <&rpmhcc RPMH_CXO_CLK>, 2684 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2685 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2686 clock-names = "bi_tcxo", 2687 "gcc_gpu_gpll0_clk_src", 2688 "gcc_gpu_gpll0_div_clk_src"; 2689 #clock-cells = <1>; 2690 #reset-cells = <1>; 2691 #power-domain-cells = <1>; 2692 }; 2693 2694 dma@117f000 { 2695 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2696 reg = <0x0 0x0117f000 0x0 0x1000>, 2697 <0x0 0x01112000 0x0 0x6000>; 2698 }; 2699 2700 adreno_smmu: iommu@3da0000 { 2701 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2702 "qcom,smmu-500", "arm,mmu-500"; 2703 reg = <0 0x03da0000 0 0x20000>; 2704 #iommu-cells = <2>; 2705 #global-interrupts = <2>; 2706 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2718 2719 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2720 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2721 <&gpucc GPU_CC_AHB_CLK>, 2722 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2723 <&gpucc GPU_CC_CX_GMU_CLK>, 2724 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2725 <&gpucc GPU_CC_HUB_AON_CLK>; 2726 clock-names = "gcc_gpu_memnoc_gfx_clk", 2727 "gcc_gpu_snoc_dvm_gfx_clk", 2728 "gpu_cc_ahb_clk", 2729 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2730 "gpu_cc_cx_gmu_clk", 2731 "gpu_cc_hub_cx_int_clk", 2732 "gpu_cc_hub_aon_clk"; 2733 2734 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2735 }; 2736 2737 remoteproc_mpss: remoteproc@4080000 { 2738 compatible = "qcom,sc7280-mpss-pas"; 2739 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2740 reg-names = "qdsp6", "rmb"; 2741 2742 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2743 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2744 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2745 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2746 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2747 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2748 interrupt-names = "wdog", "fatal", "ready", "handover", 2749 "stop-ack", "shutdown-ack"; 2750 2751 clocks = <&rpmhcc RPMH_CXO_CLK>; 2752 clock-names = "xo"; 2753 2754 power-domains = <&rpmhpd SC7280_CX>, 2755 <&rpmhpd SC7280_MSS>; 2756 power-domain-names = "cx", "mss"; 2757 2758 memory-region = <&mpss_mem>; 2759 2760 qcom,qmp = <&aoss_qmp>; 2761 2762 qcom,smem-states = <&modem_smp2p_out 0>; 2763 qcom,smem-state-names = "stop"; 2764 2765 status = "disabled"; 2766 2767 glink-edge { 2768 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2769 IPCC_MPROC_SIGNAL_GLINK_QMP 2770 IRQ_TYPE_EDGE_RISING>; 2771 mboxes = <&ipcc IPCC_CLIENT_MPSS 2772 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2773 label = "modem"; 2774 qcom,remote-pid = <1>; 2775 }; 2776 }; 2777 2778 stm@6002000 { 2779 compatible = "arm,coresight-stm", "arm,primecell"; 2780 reg = <0 0x06002000 0 0x1000>, 2781 <0 0x16280000 0 0x180000>; 2782 reg-names = "stm-base", "stm-stimulus-base"; 2783 2784 clocks = <&aoss_qmp>; 2785 clock-names = "apb_pclk"; 2786 2787 out-ports { 2788 port { 2789 stm_out: endpoint { 2790 remote-endpoint = <&funnel0_in7>; 2791 }; 2792 }; 2793 }; 2794 }; 2795 2796 funnel@6041000 { 2797 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2798 reg = <0 0x06041000 0 0x1000>; 2799 2800 clocks = <&aoss_qmp>; 2801 clock-names = "apb_pclk"; 2802 2803 out-ports { 2804 port { 2805 funnel0_out: endpoint { 2806 remote-endpoint = <&merge_funnel_in0>; 2807 }; 2808 }; 2809 }; 2810 2811 in-ports { 2812 #address-cells = <1>; 2813 #size-cells = <0>; 2814 2815 port@7 { 2816 reg = <7>; 2817 funnel0_in7: endpoint { 2818 remote-endpoint = <&stm_out>; 2819 }; 2820 }; 2821 }; 2822 }; 2823 2824 funnel@6042000 { 2825 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2826 reg = <0 0x06042000 0 0x1000>; 2827 2828 clocks = <&aoss_qmp>; 2829 clock-names = "apb_pclk"; 2830 2831 out-ports { 2832 port { 2833 funnel1_out: endpoint { 2834 remote-endpoint = <&merge_funnel_in1>; 2835 }; 2836 }; 2837 }; 2838 2839 in-ports { 2840 #address-cells = <1>; 2841 #size-cells = <0>; 2842 2843 port@4 { 2844 reg = <4>; 2845 funnel1_in4: endpoint { 2846 remote-endpoint = <&apss_merge_funnel_out>; 2847 }; 2848 }; 2849 }; 2850 }; 2851 2852 funnel@6045000 { 2853 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2854 reg = <0 0x06045000 0 0x1000>; 2855 2856 clocks = <&aoss_qmp>; 2857 clock-names = "apb_pclk"; 2858 2859 out-ports { 2860 port { 2861 merge_funnel_out: endpoint { 2862 remote-endpoint = <&swao_funnel_in>; 2863 }; 2864 }; 2865 }; 2866 2867 in-ports { 2868 #address-cells = <1>; 2869 #size-cells = <0>; 2870 2871 port@0 { 2872 reg = <0>; 2873 merge_funnel_in0: endpoint { 2874 remote-endpoint = <&funnel0_out>; 2875 }; 2876 }; 2877 2878 port@1 { 2879 reg = <1>; 2880 merge_funnel_in1: endpoint { 2881 remote-endpoint = <&funnel1_out>; 2882 }; 2883 }; 2884 }; 2885 }; 2886 2887 replicator@6046000 { 2888 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2889 reg = <0 0x06046000 0 0x1000>; 2890 2891 clocks = <&aoss_qmp>; 2892 clock-names = "apb_pclk"; 2893 2894 out-ports { 2895 port { 2896 replicator_out: endpoint { 2897 remote-endpoint = <&etr_in>; 2898 }; 2899 }; 2900 }; 2901 2902 in-ports { 2903 port { 2904 replicator_in: endpoint { 2905 remote-endpoint = <&swao_replicator_out>; 2906 }; 2907 }; 2908 }; 2909 }; 2910 2911 etr@6048000 { 2912 compatible = "arm,coresight-tmc", "arm,primecell"; 2913 reg = <0 0x06048000 0 0x1000>; 2914 iommus = <&apps_smmu 0x04c0 0>; 2915 2916 clocks = <&aoss_qmp>; 2917 clock-names = "apb_pclk"; 2918 arm,scatter-gather; 2919 2920 in-ports { 2921 port { 2922 etr_in: endpoint { 2923 remote-endpoint = <&replicator_out>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 2929 funnel@6b04000 { 2930 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2931 reg = <0 0x06b04000 0 0x1000>; 2932 2933 clocks = <&aoss_qmp>; 2934 clock-names = "apb_pclk"; 2935 2936 out-ports { 2937 port { 2938 swao_funnel_out: endpoint { 2939 remote-endpoint = <&etf_in>; 2940 }; 2941 }; 2942 }; 2943 2944 in-ports { 2945 #address-cells = <1>; 2946 #size-cells = <0>; 2947 2948 port@7 { 2949 reg = <7>; 2950 swao_funnel_in: endpoint { 2951 remote-endpoint = <&merge_funnel_out>; 2952 }; 2953 }; 2954 }; 2955 }; 2956 2957 etf@6b05000 { 2958 compatible = "arm,coresight-tmc", "arm,primecell"; 2959 reg = <0 0x06b05000 0 0x1000>; 2960 2961 clocks = <&aoss_qmp>; 2962 clock-names = "apb_pclk"; 2963 2964 out-ports { 2965 port { 2966 etf_out: endpoint { 2967 remote-endpoint = <&swao_replicator_in>; 2968 }; 2969 }; 2970 }; 2971 2972 in-ports { 2973 port { 2974 etf_in: endpoint { 2975 remote-endpoint = <&swao_funnel_out>; 2976 }; 2977 }; 2978 }; 2979 }; 2980 2981 replicator@6b06000 { 2982 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2983 reg = <0 0x06b06000 0 0x1000>; 2984 2985 clocks = <&aoss_qmp>; 2986 clock-names = "apb_pclk"; 2987 qcom,replicator-loses-context; 2988 2989 out-ports { 2990 port { 2991 swao_replicator_out: endpoint { 2992 remote-endpoint = <&replicator_in>; 2993 }; 2994 }; 2995 }; 2996 2997 in-ports { 2998 port { 2999 swao_replicator_in: endpoint { 3000 remote-endpoint = <&etf_out>; 3001 }; 3002 }; 3003 }; 3004 }; 3005 3006 etm@7040000 { 3007 compatible = "arm,coresight-etm4x", "arm,primecell"; 3008 reg = <0 0x07040000 0 0x1000>; 3009 3010 cpu = <&CPU0>; 3011 3012 clocks = <&aoss_qmp>; 3013 clock-names = "apb_pclk"; 3014 arm,coresight-loses-context-with-cpu; 3015 qcom,skip-power-up; 3016 3017 out-ports { 3018 port { 3019 etm0_out: endpoint { 3020 remote-endpoint = <&apss_funnel_in0>; 3021 }; 3022 }; 3023 }; 3024 }; 3025 3026 etm@7140000 { 3027 compatible = "arm,coresight-etm4x", "arm,primecell"; 3028 reg = <0 0x07140000 0 0x1000>; 3029 3030 cpu = <&CPU1>; 3031 3032 clocks = <&aoss_qmp>; 3033 clock-names = "apb_pclk"; 3034 arm,coresight-loses-context-with-cpu; 3035 qcom,skip-power-up; 3036 3037 out-ports { 3038 port { 3039 etm1_out: endpoint { 3040 remote-endpoint = <&apss_funnel_in1>; 3041 }; 3042 }; 3043 }; 3044 }; 3045 3046 etm@7240000 { 3047 compatible = "arm,coresight-etm4x", "arm,primecell"; 3048 reg = <0 0x07240000 0 0x1000>; 3049 3050 cpu = <&CPU2>; 3051 3052 clocks = <&aoss_qmp>; 3053 clock-names = "apb_pclk"; 3054 arm,coresight-loses-context-with-cpu; 3055 qcom,skip-power-up; 3056 3057 out-ports { 3058 port { 3059 etm2_out: endpoint { 3060 remote-endpoint = <&apss_funnel_in2>; 3061 }; 3062 }; 3063 }; 3064 }; 3065 3066 etm@7340000 { 3067 compatible = "arm,coresight-etm4x", "arm,primecell"; 3068 reg = <0 0x07340000 0 0x1000>; 3069 3070 cpu = <&CPU3>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 arm,coresight-loses-context-with-cpu; 3075 qcom,skip-power-up; 3076 3077 out-ports { 3078 port { 3079 etm3_out: endpoint { 3080 remote-endpoint = <&apss_funnel_in3>; 3081 }; 3082 }; 3083 }; 3084 }; 3085 3086 etm@7440000 { 3087 compatible = "arm,coresight-etm4x", "arm,primecell"; 3088 reg = <0 0x07440000 0 0x1000>; 3089 3090 cpu = <&CPU4>; 3091 3092 clocks = <&aoss_qmp>; 3093 clock-names = "apb_pclk"; 3094 arm,coresight-loses-context-with-cpu; 3095 qcom,skip-power-up; 3096 3097 out-ports { 3098 port { 3099 etm4_out: endpoint { 3100 remote-endpoint = <&apss_funnel_in4>; 3101 }; 3102 }; 3103 }; 3104 }; 3105 3106 etm@7540000 { 3107 compatible = "arm,coresight-etm4x", "arm,primecell"; 3108 reg = <0 0x07540000 0 0x1000>; 3109 3110 cpu = <&CPU5>; 3111 3112 clocks = <&aoss_qmp>; 3113 clock-names = "apb_pclk"; 3114 arm,coresight-loses-context-with-cpu; 3115 qcom,skip-power-up; 3116 3117 out-ports { 3118 port { 3119 etm5_out: endpoint { 3120 remote-endpoint = <&apss_funnel_in5>; 3121 }; 3122 }; 3123 }; 3124 }; 3125 3126 etm@7640000 { 3127 compatible = "arm,coresight-etm4x", "arm,primecell"; 3128 reg = <0 0x07640000 0 0x1000>; 3129 3130 cpu = <&CPU6>; 3131 3132 clocks = <&aoss_qmp>; 3133 clock-names = "apb_pclk"; 3134 arm,coresight-loses-context-with-cpu; 3135 qcom,skip-power-up; 3136 3137 out-ports { 3138 port { 3139 etm6_out: endpoint { 3140 remote-endpoint = <&apss_funnel_in6>; 3141 }; 3142 }; 3143 }; 3144 }; 3145 3146 etm@7740000 { 3147 compatible = "arm,coresight-etm4x", "arm,primecell"; 3148 reg = <0 0x07740000 0 0x1000>; 3149 3150 cpu = <&CPU7>; 3151 3152 clocks = <&aoss_qmp>; 3153 clock-names = "apb_pclk"; 3154 arm,coresight-loses-context-with-cpu; 3155 qcom,skip-power-up; 3156 3157 out-ports { 3158 port { 3159 etm7_out: endpoint { 3160 remote-endpoint = <&apss_funnel_in7>; 3161 }; 3162 }; 3163 }; 3164 }; 3165 3166 funnel@7800000 { /* APSS Funnel */ 3167 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3168 reg = <0 0x07800000 0 0x1000>; 3169 3170 clocks = <&aoss_qmp>; 3171 clock-names = "apb_pclk"; 3172 3173 out-ports { 3174 port { 3175 apss_funnel_out: endpoint { 3176 remote-endpoint = <&apss_merge_funnel_in>; 3177 }; 3178 }; 3179 }; 3180 3181 in-ports { 3182 #address-cells = <1>; 3183 #size-cells = <0>; 3184 3185 port@0 { 3186 reg = <0>; 3187 apss_funnel_in0: endpoint { 3188 remote-endpoint = <&etm0_out>; 3189 }; 3190 }; 3191 3192 port@1 { 3193 reg = <1>; 3194 apss_funnel_in1: endpoint { 3195 remote-endpoint = <&etm1_out>; 3196 }; 3197 }; 3198 3199 port@2 { 3200 reg = <2>; 3201 apss_funnel_in2: endpoint { 3202 remote-endpoint = <&etm2_out>; 3203 }; 3204 }; 3205 3206 port@3 { 3207 reg = <3>; 3208 apss_funnel_in3: endpoint { 3209 remote-endpoint = <&etm3_out>; 3210 }; 3211 }; 3212 3213 port@4 { 3214 reg = <4>; 3215 apss_funnel_in4: endpoint { 3216 remote-endpoint = <&etm4_out>; 3217 }; 3218 }; 3219 3220 port@5 { 3221 reg = <5>; 3222 apss_funnel_in5: endpoint { 3223 remote-endpoint = <&etm5_out>; 3224 }; 3225 }; 3226 3227 port@6 { 3228 reg = <6>; 3229 apss_funnel_in6: endpoint { 3230 remote-endpoint = <&etm6_out>; 3231 }; 3232 }; 3233 3234 port@7 { 3235 reg = <7>; 3236 apss_funnel_in7: endpoint { 3237 remote-endpoint = <&etm7_out>; 3238 }; 3239 }; 3240 }; 3241 }; 3242 3243 funnel@7810000 { 3244 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3245 reg = <0 0x07810000 0 0x1000>; 3246 3247 clocks = <&aoss_qmp>; 3248 clock-names = "apb_pclk"; 3249 3250 out-ports { 3251 port { 3252 apss_merge_funnel_out: endpoint { 3253 remote-endpoint = <&funnel1_in4>; 3254 }; 3255 }; 3256 }; 3257 3258 in-ports { 3259 port { 3260 apss_merge_funnel_in: endpoint { 3261 remote-endpoint = <&apss_funnel_out>; 3262 }; 3263 }; 3264 }; 3265 }; 3266 3267 sdhc_2: mmc@8804000 { 3268 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3269 pinctrl-names = "default", "sleep"; 3270 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3271 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3272 status = "disabled"; 3273 3274 reg = <0 0x08804000 0 0x1000>; 3275 3276 iommus = <&apps_smmu 0x100 0x0>; 3277 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3279 interrupt-names = "hc_irq", "pwr_irq"; 3280 3281 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3282 <&gcc GCC_SDCC2_APPS_CLK>, 3283 <&rpmhcc RPMH_CXO_CLK>; 3284 clock-names = "iface", "core", "xo"; 3285 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3286 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3287 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3288 power-domains = <&rpmhpd SC7280_CX>; 3289 operating-points-v2 = <&sdhc2_opp_table>; 3290 3291 bus-width = <4>; 3292 3293 qcom,dll-config = <0x0007642c>; 3294 3295 resets = <&gcc GCC_SDCC2_BCR>; 3296 3297 sdhc2_opp_table: opp-table { 3298 compatible = "operating-points-v2"; 3299 3300 opp-100000000 { 3301 opp-hz = /bits/ 64 <100000000>; 3302 required-opps = <&rpmhpd_opp_low_svs>; 3303 opp-peak-kBps = <1800000 400000>; 3304 opp-avg-kBps = <100000 0>; 3305 }; 3306 3307 opp-202000000 { 3308 opp-hz = /bits/ 64 <202000000>; 3309 required-opps = <&rpmhpd_opp_nom>; 3310 opp-peak-kBps = <5400000 1600000>; 3311 opp-avg-kBps = <200000 0>; 3312 }; 3313 }; 3314 }; 3315 3316 usb_1_hsphy: phy@88e3000 { 3317 compatible = "qcom,sc7280-usb-hs-phy", 3318 "qcom,usb-snps-hs-7nm-phy"; 3319 reg = <0 0x088e3000 0 0x400>; 3320 status = "disabled"; 3321 #phy-cells = <0>; 3322 3323 clocks = <&rpmhcc RPMH_CXO_CLK>; 3324 clock-names = "ref"; 3325 3326 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3327 }; 3328 3329 usb_2_hsphy: phy@88e4000 { 3330 compatible = "qcom,sc7280-usb-hs-phy", 3331 "qcom,usb-snps-hs-7nm-phy"; 3332 reg = <0 0x088e4000 0 0x400>; 3333 status = "disabled"; 3334 #phy-cells = <0>; 3335 3336 clocks = <&rpmhcc RPMH_CXO_CLK>; 3337 clock-names = "ref"; 3338 3339 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3340 }; 3341 3342 usb_1_qmpphy: phy-wrapper@88e9000 { 3343 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3344 "qcom,sm8250-qmp-usb3-dp-phy"; 3345 reg = <0 0x088e9000 0 0x200>, 3346 <0 0x088e8000 0 0x40>, 3347 <0 0x088ea000 0 0x200>; 3348 status = "disabled"; 3349 #address-cells = <2>; 3350 #size-cells = <2>; 3351 ranges; 3352 3353 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3354 <&rpmhcc RPMH_CXO_CLK>, 3355 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3356 clock-names = "aux", "ref_clk_src", "com_aux"; 3357 3358 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3359 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3360 reset-names = "phy", "common"; 3361 3362 usb_1_ssphy: usb3-phy@88e9200 { 3363 reg = <0 0x088e9200 0 0x200>, 3364 <0 0x088e9400 0 0x200>, 3365 <0 0x088e9c00 0 0x400>, 3366 <0 0x088e9600 0 0x200>, 3367 <0 0x088e9800 0 0x200>, 3368 <0 0x088e9a00 0 0x100>; 3369 #clock-cells = <0>; 3370 #phy-cells = <0>; 3371 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3372 clock-names = "pipe0"; 3373 clock-output-names = "usb3_phy_pipe_clk_src"; 3374 }; 3375 3376 dp_phy: dp-phy@88ea200 { 3377 reg = <0 0x088ea200 0 0x200>, 3378 <0 0x088ea400 0 0x200>, 3379 <0 0x088eaa00 0 0x200>, 3380 <0 0x088ea600 0 0x200>, 3381 <0 0x088ea800 0 0x200>; 3382 #phy-cells = <0>; 3383 #clock-cells = <1>; 3384 }; 3385 }; 3386 3387 usb_2: usb@8cf8800 { 3388 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3389 reg = <0 0x08cf8800 0 0x400>; 3390 status = "disabled"; 3391 #address-cells = <2>; 3392 #size-cells = <2>; 3393 ranges; 3394 dma-ranges; 3395 3396 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3397 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3398 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3399 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3400 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3401 clock-names = "cfg_noc", 3402 "core", 3403 "iface", 3404 "sleep", 3405 "mock_utmi"; 3406 3407 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3408 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3409 assigned-clock-rates = <19200000>, <200000000>; 3410 3411 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3412 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3413 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3414 interrupt-names = "hs_phy_irq", 3415 "dp_hs_phy_irq", 3416 "dm_hs_phy_irq"; 3417 3418 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3419 required-opps = <&rpmhpd_opp_nom>; 3420 3421 resets = <&gcc GCC_USB30_SEC_BCR>; 3422 3423 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3424 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3425 interconnect-names = "usb-ddr", "apps-usb"; 3426 3427 usb_2_dwc3: usb@8c00000 { 3428 compatible = "snps,dwc3"; 3429 reg = <0 0x08c00000 0 0xe000>; 3430 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3431 iommus = <&apps_smmu 0xa0 0x0>; 3432 snps,dis_u2_susphy_quirk; 3433 snps,dis_enblslpm_quirk; 3434 phys = <&usb_2_hsphy>; 3435 phy-names = "usb2-phy"; 3436 maximum-speed = "high-speed"; 3437 usb-role-switch; 3438 3439 port { 3440 usb2_role_switch: endpoint { 3441 remote-endpoint = <&eud_ep>; 3442 }; 3443 }; 3444 }; 3445 }; 3446 3447 qspi: spi@88dc000 { 3448 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3449 reg = <0 0x088dc000 0 0x1000>; 3450 iommus = <&apps_smmu 0x20 0x0>; 3451 #address-cells = <1>; 3452 #size-cells = <0>; 3453 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3454 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3455 <&gcc GCC_QSPI_CORE_CLK>; 3456 clock-names = "iface", "core"; 3457 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3458 &cnoc2 SLAVE_QSPI_0 0>; 3459 interconnect-names = "qspi-config"; 3460 power-domains = <&rpmhpd SC7280_CX>; 3461 operating-points-v2 = <&qspi_opp_table>; 3462 status = "disabled"; 3463 }; 3464 3465 remoteproc_wpss: remoteproc@8a00000 { 3466 compatible = "qcom,sc7280-wpss-pil"; 3467 reg = <0 0x08a00000 0 0x10000>; 3468 3469 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3470 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3471 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3472 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3473 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3474 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3475 interrupt-names = "wdog", "fatal", "ready", "handover", 3476 "stop-ack", "shutdown-ack"; 3477 3478 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3479 <&gcc GCC_WPSS_AHB_CLK>, 3480 <&gcc GCC_WPSS_RSCP_CLK>, 3481 <&rpmhcc RPMH_CXO_CLK>; 3482 clock-names = "ahb_bdg", "ahb", 3483 "rscp", "xo"; 3484 3485 power-domains = <&rpmhpd SC7280_CX>, 3486 <&rpmhpd SC7280_MX>; 3487 power-domain-names = "cx", "mx"; 3488 3489 memory-region = <&wpss_mem>; 3490 3491 qcom,qmp = <&aoss_qmp>; 3492 3493 qcom,smem-states = <&wpss_smp2p_out 0>; 3494 qcom,smem-state-names = "stop"; 3495 3496 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3497 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3498 reset-names = "restart", "pdc_sync"; 3499 3500 qcom,halt-regs = <&tcsr_1 0x17000>; 3501 3502 status = "disabled"; 3503 3504 glink-edge { 3505 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3506 IPCC_MPROC_SIGNAL_GLINK_QMP 3507 IRQ_TYPE_EDGE_RISING>; 3508 mboxes = <&ipcc IPCC_CLIENT_WPSS 3509 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3510 3511 label = "wpss"; 3512 qcom,remote-pid = <13>; 3513 }; 3514 }; 3515 3516 pmu@9091000 { 3517 compatible = "qcom,sc7280-llcc-bwmon"; 3518 reg = <0 0x09091000 0 0x1000>; 3519 3520 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3521 3522 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3523 3524 operating-points-v2 = <&llcc_bwmon_opp_table>; 3525 3526 llcc_bwmon_opp_table: opp-table { 3527 compatible = "operating-points-v2"; 3528 3529 opp-0 { 3530 opp-peak-kBps = <800000>; 3531 }; 3532 opp-1 { 3533 opp-peak-kBps = <1804000>; 3534 }; 3535 opp-2 { 3536 opp-peak-kBps = <2188000>; 3537 }; 3538 opp-3 { 3539 opp-peak-kBps = <3072000>; 3540 }; 3541 opp-4 { 3542 opp-peak-kBps = <4068000>; 3543 }; 3544 opp-5 { 3545 opp-peak-kBps = <6220000>; 3546 }; 3547 opp-6 { 3548 opp-peak-kBps = <6832000>; 3549 }; 3550 opp-7 { 3551 opp-peak-kBps = <8532000>; 3552 }; 3553 }; 3554 }; 3555 3556 pmu@90b6400 { 3557 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3558 reg = <0 0x090b6400 0 0x600>; 3559 3560 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3561 3562 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3563 operating-points-v2 = <&cpu_bwmon_opp_table>; 3564 3565 cpu_bwmon_opp_table: opp-table { 3566 compatible = "operating-points-v2"; 3567 3568 opp-0 { 3569 opp-peak-kBps = <2400000>; 3570 }; 3571 opp-1 { 3572 opp-peak-kBps = <4800000>; 3573 }; 3574 opp-2 { 3575 opp-peak-kBps = <7456000>; 3576 }; 3577 opp-3 { 3578 opp-peak-kBps = <9600000>; 3579 }; 3580 opp-4 { 3581 opp-peak-kBps = <12896000>; 3582 }; 3583 opp-5 { 3584 opp-peak-kBps = <14928000>; 3585 }; 3586 opp-6 { 3587 opp-peak-kBps = <17056000>; 3588 }; 3589 }; 3590 }; 3591 3592 dc_noc: interconnect@90e0000 { 3593 reg = <0 0x090e0000 0 0x5080>; 3594 compatible = "qcom,sc7280-dc-noc"; 3595 #interconnect-cells = <2>; 3596 qcom,bcm-voters = <&apps_bcm_voter>; 3597 }; 3598 3599 gem_noc: interconnect@9100000 { 3600 reg = <0 0x09100000 0 0xe2200>; 3601 compatible = "qcom,sc7280-gem-noc"; 3602 #interconnect-cells = <2>; 3603 qcom,bcm-voters = <&apps_bcm_voter>; 3604 }; 3605 3606 system-cache-controller@9200000 { 3607 compatible = "qcom,sc7280-llcc"; 3608 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3609 <0 0x09600000 0 0x58000>; 3610 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3611 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3612 }; 3613 3614 eud: eud@88e0000 { 3615 compatible = "qcom,sc7280-eud", "qcom,eud"; 3616 reg = <0 0x88e0000 0 0x2000>, 3617 <0 0x88e2000 0 0x1000>; 3618 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3619 3620 status = "disabled"; 3621 3622 ports { 3623 #address-cells = <1>; 3624 #size-cells = <0>; 3625 3626 port@0 { 3627 reg = <0>; 3628 eud_ep: endpoint { 3629 remote-endpoint = <&usb2_role_switch>; 3630 }; 3631 }; 3632 }; 3633 }; 3634 3635 nsp_noc: interconnect@a0c0000 { 3636 reg = <0 0x0a0c0000 0 0x10000>; 3637 compatible = "qcom,sc7280-nsp-noc"; 3638 #interconnect-cells = <2>; 3639 qcom,bcm-voters = <&apps_bcm_voter>; 3640 }; 3641 3642 usb_1: usb@a6f8800 { 3643 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3644 reg = <0 0x0a6f8800 0 0x400>; 3645 status = "disabled"; 3646 #address-cells = <2>; 3647 #size-cells = <2>; 3648 ranges; 3649 dma-ranges; 3650 3651 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3652 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3653 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3654 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3655 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3656 clock-names = "cfg_noc", 3657 "core", 3658 "iface", 3659 "sleep", 3660 "mock_utmi"; 3661 3662 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3663 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3664 assigned-clock-rates = <19200000>, <200000000>; 3665 3666 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3667 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3668 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3669 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3670 interrupt-names = "hs_phy_irq", 3671 "dp_hs_phy_irq", 3672 "dm_hs_phy_irq", 3673 "ss_phy_irq"; 3674 3675 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3676 required-opps = <&rpmhpd_opp_nom>; 3677 3678 resets = <&gcc GCC_USB30_PRIM_BCR>; 3679 3680 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3681 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3682 interconnect-names = "usb-ddr", "apps-usb"; 3683 3684 wakeup-source; 3685 3686 usb_1_dwc3: usb@a600000 { 3687 compatible = "snps,dwc3"; 3688 reg = <0 0x0a600000 0 0xe000>; 3689 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3690 iommus = <&apps_smmu 0xe0 0x0>; 3691 snps,dis_u2_susphy_quirk; 3692 snps,dis_enblslpm_quirk; 3693 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3694 phy-names = "usb2-phy", "usb3-phy"; 3695 maximum-speed = "super-speed"; 3696 }; 3697 }; 3698 3699 venus: video-codec@aa00000 { 3700 compatible = "qcom,sc7280-venus"; 3701 reg = <0 0x0aa00000 0 0xd0600>; 3702 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3703 3704 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3705 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3706 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3707 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3708 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3709 clock-names = "core", "bus", "iface", 3710 "vcodec_core", "vcodec_bus"; 3711 3712 power-domains = <&videocc MVSC_GDSC>, 3713 <&videocc MVS0_GDSC>, 3714 <&rpmhpd SC7280_CX>; 3715 power-domain-names = "venus", "vcodec0", "cx"; 3716 operating-points-v2 = <&venus_opp_table>; 3717 3718 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3719 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3720 interconnect-names = "cpu-cfg", "video-mem"; 3721 3722 iommus = <&apps_smmu 0x2180 0x20>, 3723 <&apps_smmu 0x2184 0x20>; 3724 memory-region = <&video_mem>; 3725 3726 video-decoder { 3727 compatible = "venus-decoder"; 3728 }; 3729 3730 video-encoder { 3731 compatible = "venus-encoder"; 3732 }; 3733 3734 video-firmware { 3735 iommus = <&apps_smmu 0x21a2 0x0>; 3736 }; 3737 3738 venus_opp_table: opp-table { 3739 compatible = "operating-points-v2"; 3740 3741 opp-133330000 { 3742 opp-hz = /bits/ 64 <133330000>; 3743 required-opps = <&rpmhpd_opp_low_svs>; 3744 }; 3745 3746 opp-240000000 { 3747 opp-hz = /bits/ 64 <240000000>; 3748 required-opps = <&rpmhpd_opp_svs>; 3749 }; 3750 3751 opp-335000000 { 3752 opp-hz = /bits/ 64 <335000000>; 3753 required-opps = <&rpmhpd_opp_svs_l1>; 3754 }; 3755 3756 opp-424000000 { 3757 opp-hz = /bits/ 64 <424000000>; 3758 required-opps = <&rpmhpd_opp_nom>; 3759 }; 3760 3761 opp-460000048 { 3762 opp-hz = /bits/ 64 <460000048>; 3763 required-opps = <&rpmhpd_opp_turbo>; 3764 }; 3765 }; 3766 }; 3767 3768 videocc: clock-controller@aaf0000 { 3769 compatible = "qcom,sc7280-videocc"; 3770 reg = <0 0x0aaf0000 0 0x10000>; 3771 clocks = <&rpmhcc RPMH_CXO_CLK>, 3772 <&rpmhcc RPMH_CXO_CLK_A>; 3773 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3774 #clock-cells = <1>; 3775 #reset-cells = <1>; 3776 #power-domain-cells = <1>; 3777 }; 3778 3779 camcc: clock-controller@ad00000 { 3780 compatible = "qcom,sc7280-camcc"; 3781 reg = <0 0x0ad00000 0 0x10000>; 3782 clocks = <&rpmhcc RPMH_CXO_CLK>, 3783 <&rpmhcc RPMH_CXO_CLK_A>, 3784 <&sleep_clk>; 3785 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3786 #clock-cells = <1>; 3787 #reset-cells = <1>; 3788 #power-domain-cells = <1>; 3789 }; 3790 3791 dispcc: clock-controller@af00000 { 3792 compatible = "qcom,sc7280-dispcc"; 3793 reg = <0 0x0af00000 0 0x20000>; 3794 clocks = <&rpmhcc RPMH_CXO_CLK>, 3795 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3796 <&mdss_dsi_phy 0>, 3797 <&mdss_dsi_phy 1>, 3798 <&dp_phy 0>, 3799 <&dp_phy 1>, 3800 <&mdss_edp_phy 0>, 3801 <&mdss_edp_phy 1>; 3802 clock-names = "bi_tcxo", 3803 "gcc_disp_gpll0_clk", 3804 "dsi0_phy_pll_out_byteclk", 3805 "dsi0_phy_pll_out_dsiclk", 3806 "dp_phy_pll_link_clk", 3807 "dp_phy_pll_vco_div_clk", 3808 "edp_phy_pll_link_clk", 3809 "edp_phy_pll_vco_div_clk"; 3810 #clock-cells = <1>; 3811 #reset-cells = <1>; 3812 #power-domain-cells = <1>; 3813 }; 3814 3815 mdss: display-subsystem@ae00000 { 3816 compatible = "qcom,sc7280-mdss"; 3817 reg = <0 0x0ae00000 0 0x1000>; 3818 reg-names = "mdss"; 3819 3820 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3821 3822 clocks = <&gcc GCC_DISP_AHB_CLK>, 3823 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3824 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3825 clock-names = "iface", 3826 "ahb", 3827 "core"; 3828 3829 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3830 interrupt-controller; 3831 #interrupt-cells = <1>; 3832 3833 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3834 interconnect-names = "mdp0-mem"; 3835 3836 iommus = <&apps_smmu 0x900 0x402>; 3837 3838 #address-cells = <2>; 3839 #size-cells = <2>; 3840 ranges; 3841 3842 status = "disabled"; 3843 3844 mdss_mdp: display-controller@ae01000 { 3845 compatible = "qcom,sc7280-dpu"; 3846 reg = <0 0x0ae01000 0 0x8f030>, 3847 <0 0x0aeb0000 0 0x2008>; 3848 reg-names = "mdp", "vbif"; 3849 3850 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3851 <&gcc GCC_DISP_SF_AXI_CLK>, 3852 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3853 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3854 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3855 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3856 clock-names = "bus", 3857 "nrt_bus", 3858 "iface", 3859 "lut", 3860 "core", 3861 "vsync"; 3862 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3863 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3864 assigned-clock-rates = <19200000>, 3865 <19200000>; 3866 operating-points-v2 = <&mdp_opp_table>; 3867 power-domains = <&rpmhpd SC7280_CX>; 3868 3869 interrupt-parent = <&mdss>; 3870 interrupts = <0>; 3871 3872 ports { 3873 #address-cells = <1>; 3874 #size-cells = <0>; 3875 3876 port@0 { 3877 reg = <0>; 3878 dpu_intf1_out: endpoint { 3879 remote-endpoint = <&mdss_dsi0_in>; 3880 }; 3881 }; 3882 3883 port@1 { 3884 reg = <1>; 3885 dpu_intf5_out: endpoint { 3886 remote-endpoint = <&edp_in>; 3887 }; 3888 }; 3889 3890 port@2 { 3891 reg = <2>; 3892 dpu_intf0_out: endpoint { 3893 remote-endpoint = <&dp_in>; 3894 }; 3895 }; 3896 }; 3897 3898 mdp_opp_table: opp-table { 3899 compatible = "operating-points-v2"; 3900 3901 opp-200000000 { 3902 opp-hz = /bits/ 64 <200000000>; 3903 required-opps = <&rpmhpd_opp_low_svs>; 3904 }; 3905 3906 opp-300000000 { 3907 opp-hz = /bits/ 64 <300000000>; 3908 required-opps = <&rpmhpd_opp_svs>; 3909 }; 3910 3911 opp-380000000 { 3912 opp-hz = /bits/ 64 <380000000>; 3913 required-opps = <&rpmhpd_opp_svs_l1>; 3914 }; 3915 3916 opp-506666667 { 3917 opp-hz = /bits/ 64 <506666667>; 3918 required-opps = <&rpmhpd_opp_nom>; 3919 }; 3920 }; 3921 }; 3922 3923 mdss_dsi: dsi@ae94000 { 3924 compatible = "qcom,sc7280-dsi-ctrl", 3925 "qcom,mdss-dsi-ctrl"; 3926 reg = <0 0x0ae94000 0 0x400>; 3927 reg-names = "dsi_ctrl"; 3928 3929 interrupt-parent = <&mdss>; 3930 interrupts = <4>; 3931 3932 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3933 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3934 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3935 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3936 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3937 <&gcc GCC_DISP_HF_AXI_CLK>; 3938 clock-names = "byte", 3939 "byte_intf", 3940 "pixel", 3941 "core", 3942 "iface", 3943 "bus"; 3944 3945 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3946 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3947 3948 operating-points-v2 = <&dsi_opp_table>; 3949 power-domains = <&rpmhpd SC7280_CX>; 3950 3951 phys = <&mdss_dsi_phy>; 3952 3953 #address-cells = <1>; 3954 #size-cells = <0>; 3955 3956 status = "disabled"; 3957 3958 ports { 3959 #address-cells = <1>; 3960 #size-cells = <0>; 3961 3962 port@0 { 3963 reg = <0>; 3964 mdss_dsi0_in: endpoint { 3965 remote-endpoint = <&dpu_intf1_out>; 3966 }; 3967 }; 3968 3969 port@1 { 3970 reg = <1>; 3971 mdss_dsi0_out: endpoint { 3972 }; 3973 }; 3974 }; 3975 3976 dsi_opp_table: opp-table { 3977 compatible = "operating-points-v2"; 3978 3979 opp-187500000 { 3980 opp-hz = /bits/ 64 <187500000>; 3981 required-opps = <&rpmhpd_opp_low_svs>; 3982 }; 3983 3984 opp-300000000 { 3985 opp-hz = /bits/ 64 <300000000>; 3986 required-opps = <&rpmhpd_opp_svs>; 3987 }; 3988 3989 opp-358000000 { 3990 opp-hz = /bits/ 64 <358000000>; 3991 required-opps = <&rpmhpd_opp_svs_l1>; 3992 }; 3993 }; 3994 }; 3995 3996 mdss_dsi_phy: phy@ae94400 { 3997 compatible = "qcom,sc7280-dsi-phy-7nm"; 3998 reg = <0 0x0ae94400 0 0x200>, 3999 <0 0x0ae94600 0 0x280>, 4000 <0 0x0ae94900 0 0x280>; 4001 reg-names = "dsi_phy", 4002 "dsi_phy_lane", 4003 "dsi_pll"; 4004 4005 #clock-cells = <1>; 4006 #phy-cells = <0>; 4007 4008 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4009 <&rpmhcc RPMH_CXO_CLK>; 4010 clock-names = "iface", "ref"; 4011 4012 status = "disabled"; 4013 }; 4014 4015 mdss_edp: edp@aea0000 { 4016 compatible = "qcom,sc7280-edp"; 4017 pinctrl-names = "default"; 4018 pinctrl-0 = <&edp_hot_plug_det>; 4019 4020 reg = <0 0x0aea0000 0 0x200>, 4021 <0 0x0aea0200 0 0x200>, 4022 <0 0x0aea0400 0 0xc00>, 4023 <0 0x0aea1000 0 0x400>; 4024 4025 interrupt-parent = <&mdss>; 4026 interrupts = <14>; 4027 4028 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4029 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4030 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4031 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4032 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4033 clock-names = "core_iface", 4034 "core_aux", 4035 "ctrl_link", 4036 "ctrl_link_iface", 4037 "stream_pixel"; 4038 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4039 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4040 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4041 4042 phys = <&mdss_edp_phy>; 4043 phy-names = "dp"; 4044 4045 operating-points-v2 = <&edp_opp_table>; 4046 power-domains = <&rpmhpd SC7280_CX>; 4047 4048 status = "disabled"; 4049 4050 ports { 4051 #address-cells = <1>; 4052 #size-cells = <0>; 4053 4054 port@0 { 4055 reg = <0>; 4056 edp_in: endpoint { 4057 remote-endpoint = <&dpu_intf5_out>; 4058 }; 4059 }; 4060 4061 port@1 { 4062 reg = <1>; 4063 mdss_edp_out: endpoint { }; 4064 }; 4065 }; 4066 4067 edp_opp_table: opp-table { 4068 compatible = "operating-points-v2"; 4069 4070 opp-160000000 { 4071 opp-hz = /bits/ 64 <160000000>; 4072 required-opps = <&rpmhpd_opp_low_svs>; 4073 }; 4074 4075 opp-270000000 { 4076 opp-hz = /bits/ 64 <270000000>; 4077 required-opps = <&rpmhpd_opp_svs>; 4078 }; 4079 4080 opp-540000000 { 4081 opp-hz = /bits/ 64 <540000000>; 4082 required-opps = <&rpmhpd_opp_nom>; 4083 }; 4084 4085 opp-810000000 { 4086 opp-hz = /bits/ 64 <810000000>; 4087 required-opps = <&rpmhpd_opp_nom>; 4088 }; 4089 }; 4090 }; 4091 4092 mdss_edp_phy: phy@aec2a00 { 4093 compatible = "qcom,sc7280-edp-phy"; 4094 4095 reg = <0 0x0aec2a00 0 0x19c>, 4096 <0 0x0aec2200 0 0xa0>, 4097 <0 0x0aec2600 0 0xa0>, 4098 <0 0x0aec2000 0 0x1c0>; 4099 4100 clocks = <&rpmhcc RPMH_CXO_CLK>, 4101 <&gcc GCC_EDP_CLKREF_EN>; 4102 clock-names = "aux", 4103 "cfg_ahb"; 4104 4105 #clock-cells = <1>; 4106 #phy-cells = <0>; 4107 4108 status = "disabled"; 4109 }; 4110 4111 mdss_dp: displayport-controller@ae90000 { 4112 compatible = "qcom,sc7280-dp"; 4113 4114 reg = <0 0x0ae90000 0 0x200>, 4115 <0 0x0ae90200 0 0x200>, 4116 <0 0x0ae90400 0 0xc00>, 4117 <0 0x0ae91000 0 0x400>, 4118 <0 0x0ae91400 0 0x400>; 4119 4120 interrupt-parent = <&mdss>; 4121 interrupts = <12>; 4122 4123 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4124 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4125 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4126 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4127 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4128 clock-names = "core_iface", 4129 "core_aux", 4130 "ctrl_link", 4131 "ctrl_link_iface", 4132 "stream_pixel"; 4133 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4134 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4135 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4136 phys = <&dp_phy>; 4137 phy-names = "dp"; 4138 4139 operating-points-v2 = <&dp_opp_table>; 4140 power-domains = <&rpmhpd SC7280_CX>; 4141 4142 #sound-dai-cells = <0>; 4143 4144 status = "disabled"; 4145 4146 ports { 4147 #address-cells = <1>; 4148 #size-cells = <0>; 4149 4150 port@0 { 4151 reg = <0>; 4152 dp_in: endpoint { 4153 remote-endpoint = <&dpu_intf0_out>; 4154 }; 4155 }; 4156 4157 port@1 { 4158 reg = <1>; 4159 mdss_dp_out: endpoint { }; 4160 }; 4161 }; 4162 4163 dp_opp_table: opp-table { 4164 compatible = "operating-points-v2"; 4165 4166 opp-160000000 { 4167 opp-hz = /bits/ 64 <160000000>; 4168 required-opps = <&rpmhpd_opp_low_svs>; 4169 }; 4170 4171 opp-270000000 { 4172 opp-hz = /bits/ 64 <270000000>; 4173 required-opps = <&rpmhpd_opp_svs>; 4174 }; 4175 4176 opp-540000000 { 4177 opp-hz = /bits/ 64 <540000000>; 4178 required-opps = <&rpmhpd_opp_svs_l1>; 4179 }; 4180 4181 opp-810000000 { 4182 opp-hz = /bits/ 64 <810000000>; 4183 required-opps = <&rpmhpd_opp_nom>; 4184 }; 4185 }; 4186 }; 4187 }; 4188 4189 pdc: interrupt-controller@b220000 { 4190 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4191 reg = <0 0x0b220000 0 0x30000>; 4192 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4193 <55 306 4>, <59 312 3>, <62 374 2>, 4194 <64 434 2>, <66 438 3>, <69 86 1>, 4195 <70 520 54>, <124 609 31>, <155 63 1>, 4196 <156 716 12>; 4197 #interrupt-cells = <2>; 4198 interrupt-parent = <&intc>; 4199 interrupt-controller; 4200 }; 4201 4202 pdc_reset: reset-controller@b5e0000 { 4203 compatible = "qcom,sc7280-pdc-global"; 4204 reg = <0 0x0b5e0000 0 0x20000>; 4205 #reset-cells = <1>; 4206 status = "reserved"; /* Owned by firmware */ 4207 }; 4208 4209 tsens0: thermal-sensor@c263000 { 4210 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4211 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4212 <0 0x0c222000 0 0x1ff>; /* SROT */ 4213 #qcom,sensors = <15>; 4214 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4216 interrupt-names = "uplow","critical"; 4217 #thermal-sensor-cells = <1>; 4218 }; 4219 4220 tsens1: thermal-sensor@c265000 { 4221 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4222 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4223 <0 0x0c223000 0 0x1ff>; /* SROT */ 4224 #qcom,sensors = <12>; 4225 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4227 interrupt-names = "uplow","critical"; 4228 #thermal-sensor-cells = <1>; 4229 }; 4230 4231 aoss_reset: reset-controller@c2a0000 { 4232 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4233 reg = <0 0x0c2a0000 0 0x31000>; 4234 #reset-cells = <1>; 4235 }; 4236 4237 aoss_qmp: power-management@c300000 { 4238 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4239 reg = <0 0x0c300000 0 0x400>; 4240 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4241 IPCC_MPROC_SIGNAL_GLINK_QMP 4242 IRQ_TYPE_EDGE_RISING>; 4243 mboxes = <&ipcc IPCC_CLIENT_AOP 4244 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4245 4246 #clock-cells = <0>; 4247 }; 4248 4249 sram@c3f0000 { 4250 compatible = "qcom,rpmh-stats"; 4251 reg = <0 0x0c3f0000 0 0x400>; 4252 }; 4253 4254 spmi_bus: spmi@c440000 { 4255 compatible = "qcom,spmi-pmic-arb"; 4256 reg = <0 0x0c440000 0 0x1100>, 4257 <0 0x0c600000 0 0x2000000>, 4258 <0 0x0e600000 0 0x100000>, 4259 <0 0x0e700000 0 0xa0000>, 4260 <0 0x0c40a000 0 0x26000>; 4261 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4262 interrupt-names = "periph_irq"; 4263 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4264 qcom,ee = <0>; 4265 qcom,channel = <0>; 4266 #address-cells = <2>; 4267 #size-cells = <0>; 4268 interrupt-controller; 4269 #interrupt-cells = <4>; 4270 }; 4271 4272 tlmm: pinctrl@f100000 { 4273 compatible = "qcom,sc7280-pinctrl"; 4274 reg = <0 0x0f100000 0 0x300000>; 4275 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4276 gpio-controller; 4277 #gpio-cells = <2>; 4278 interrupt-controller; 4279 #interrupt-cells = <2>; 4280 gpio-ranges = <&tlmm 0 0 175>; 4281 wakeup-parent = <&pdc>; 4282 4283 dp_hot_plug_det: dp-hot-plug-det-state { 4284 pins = "gpio47"; 4285 function = "dp_hot"; 4286 }; 4287 4288 edp_hot_plug_det: edp-hot-plug-det-state { 4289 pins = "gpio60"; 4290 function = "edp_hot"; 4291 }; 4292 4293 mi2s0_data0: mi2s0-data0-state { 4294 pins = "gpio98"; 4295 function = "mi2s0_data0"; 4296 }; 4297 4298 mi2s0_data1: mi2s0-data1-state { 4299 pins = "gpio99"; 4300 function = "mi2s0_data1"; 4301 }; 4302 4303 mi2s0_mclk: mi2s0-mclk-state { 4304 pins = "gpio96"; 4305 function = "pri_mi2s"; 4306 }; 4307 4308 mi2s0_sclk: mi2s0-sclk-state { 4309 pins = "gpio97"; 4310 function = "mi2s0_sck"; 4311 }; 4312 4313 mi2s0_ws: mi2s0-ws-state { 4314 pins = "gpio100"; 4315 function = "mi2s0_ws"; 4316 }; 4317 4318 mi2s1_data0: mi2s1-data0-state { 4319 pins = "gpio107"; 4320 function = "mi2s1_data0"; 4321 }; 4322 4323 mi2s1_sclk: mi2s1-sclk-state { 4324 pins = "gpio106"; 4325 function = "mi2s1_sck"; 4326 }; 4327 4328 mi2s1_ws: mi2s1-ws-state { 4329 pins = "gpio108"; 4330 function = "mi2s1_ws"; 4331 }; 4332 4333 pcie1_clkreq_n: pcie1-clkreq-n-state { 4334 pins = "gpio79"; 4335 function = "pcie1_clkreqn"; 4336 }; 4337 4338 qspi_clk: qspi-clk-state { 4339 pins = "gpio14"; 4340 function = "qspi_clk"; 4341 }; 4342 4343 qspi_cs0: qspi-cs0-state { 4344 pins = "gpio15"; 4345 function = "qspi_cs"; 4346 }; 4347 4348 qspi_cs1: qspi-cs1-state { 4349 pins = "gpio19"; 4350 function = "qspi_cs"; 4351 }; 4352 4353 qspi_data0: qspi-data0-state { 4354 pins = "gpio12"; 4355 function = "qspi_data"; 4356 }; 4357 4358 qspi_data1: qspi-data1-state { 4359 pins = "gpio13"; 4360 function = "qspi_data"; 4361 }; 4362 4363 qspi_data23: qspi-data23-state { 4364 pins = "gpio16", "gpio17"; 4365 function = "qspi_data"; 4366 }; 4367 4368 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4369 pins = "gpio0", "gpio1"; 4370 function = "qup00"; 4371 }; 4372 4373 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4374 pins = "gpio4", "gpio5"; 4375 function = "qup01"; 4376 }; 4377 4378 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4379 pins = "gpio8", "gpio9"; 4380 function = "qup02"; 4381 }; 4382 4383 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4384 pins = "gpio12", "gpio13"; 4385 function = "qup03"; 4386 }; 4387 4388 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4389 pins = "gpio16", "gpio17"; 4390 function = "qup04"; 4391 }; 4392 4393 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4394 pins = "gpio20", "gpio21"; 4395 function = "qup05"; 4396 }; 4397 4398 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4399 pins = "gpio24", "gpio25"; 4400 function = "qup06"; 4401 }; 4402 4403 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4404 pins = "gpio28", "gpio29"; 4405 function = "qup07"; 4406 }; 4407 4408 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4409 pins = "gpio32", "gpio33"; 4410 function = "qup10"; 4411 }; 4412 4413 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4414 pins = "gpio36", "gpio37"; 4415 function = "qup11"; 4416 }; 4417 4418 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4419 pins = "gpio40", "gpio41"; 4420 function = "qup12"; 4421 }; 4422 4423 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4424 pins = "gpio44", "gpio45"; 4425 function = "qup13"; 4426 }; 4427 4428 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4429 pins = "gpio48", "gpio49"; 4430 function = "qup14"; 4431 }; 4432 4433 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4434 pins = "gpio52", "gpio53"; 4435 function = "qup15"; 4436 }; 4437 4438 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4439 pins = "gpio56", "gpio57"; 4440 function = "qup16"; 4441 }; 4442 4443 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4444 pins = "gpio60", "gpio61"; 4445 function = "qup17"; 4446 }; 4447 4448 qup_spi0_data_clk: qup-spi0-data-clk-state { 4449 pins = "gpio0", "gpio1", "gpio2"; 4450 function = "qup00"; 4451 }; 4452 4453 qup_spi0_cs: qup-spi0-cs-state { 4454 pins = "gpio3"; 4455 function = "qup00"; 4456 }; 4457 4458 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4459 pins = "gpio3"; 4460 function = "gpio"; 4461 }; 4462 4463 qup_spi1_data_clk: qup-spi1-data-clk-state { 4464 pins = "gpio4", "gpio5", "gpio6"; 4465 function = "qup01"; 4466 }; 4467 4468 qup_spi1_cs: qup-spi1-cs-state { 4469 pins = "gpio7"; 4470 function = "qup01"; 4471 }; 4472 4473 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4474 pins = "gpio7"; 4475 function = "gpio"; 4476 }; 4477 4478 qup_spi2_data_clk: qup-spi2-data-clk-state { 4479 pins = "gpio8", "gpio9", "gpio10"; 4480 function = "qup02"; 4481 }; 4482 4483 qup_spi2_cs: qup-spi2-cs-state { 4484 pins = "gpio11"; 4485 function = "qup02"; 4486 }; 4487 4488 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4489 pins = "gpio11"; 4490 function = "gpio"; 4491 }; 4492 4493 qup_spi3_data_clk: qup-spi3-data-clk-state { 4494 pins = "gpio12", "gpio13", "gpio14"; 4495 function = "qup03"; 4496 }; 4497 4498 qup_spi3_cs: qup-spi3-cs-state { 4499 pins = "gpio15"; 4500 function = "qup03"; 4501 }; 4502 4503 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4504 pins = "gpio15"; 4505 function = "gpio"; 4506 }; 4507 4508 qup_spi4_data_clk: qup-spi4-data-clk-state { 4509 pins = "gpio16", "gpio17", "gpio18"; 4510 function = "qup04"; 4511 }; 4512 4513 qup_spi4_cs: qup-spi4-cs-state { 4514 pins = "gpio19"; 4515 function = "qup04"; 4516 }; 4517 4518 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4519 pins = "gpio19"; 4520 function = "gpio"; 4521 }; 4522 4523 qup_spi5_data_clk: qup-spi5-data-clk-state { 4524 pins = "gpio20", "gpio21", "gpio22"; 4525 function = "qup05"; 4526 }; 4527 4528 qup_spi5_cs: qup-spi5-cs-state { 4529 pins = "gpio23"; 4530 function = "qup05"; 4531 }; 4532 4533 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4534 pins = "gpio23"; 4535 function = "gpio"; 4536 }; 4537 4538 qup_spi6_data_clk: qup-spi6-data-clk-state { 4539 pins = "gpio24", "gpio25", "gpio26"; 4540 function = "qup06"; 4541 }; 4542 4543 qup_spi6_cs: qup-spi6-cs-state { 4544 pins = "gpio27"; 4545 function = "qup06"; 4546 }; 4547 4548 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4549 pins = "gpio27"; 4550 function = "gpio"; 4551 }; 4552 4553 qup_spi7_data_clk: qup-spi7-data-clk-state { 4554 pins = "gpio28", "gpio29", "gpio30"; 4555 function = "qup07"; 4556 }; 4557 4558 qup_spi7_cs: qup-spi7-cs-state { 4559 pins = "gpio31"; 4560 function = "qup07"; 4561 }; 4562 4563 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4564 pins = "gpio31"; 4565 function = "gpio"; 4566 }; 4567 4568 qup_spi8_data_clk: qup-spi8-data-clk-state { 4569 pins = "gpio32", "gpio33", "gpio34"; 4570 function = "qup10"; 4571 }; 4572 4573 qup_spi8_cs: qup-spi8-cs-state { 4574 pins = "gpio35"; 4575 function = "qup10"; 4576 }; 4577 4578 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4579 pins = "gpio35"; 4580 function = "gpio"; 4581 }; 4582 4583 qup_spi9_data_clk: qup-spi9-data-clk-state { 4584 pins = "gpio36", "gpio37", "gpio38"; 4585 function = "qup11"; 4586 }; 4587 4588 qup_spi9_cs: qup-spi9-cs-state { 4589 pins = "gpio39"; 4590 function = "qup11"; 4591 }; 4592 4593 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4594 pins = "gpio39"; 4595 function = "gpio"; 4596 }; 4597 4598 qup_spi10_data_clk: qup-spi10-data-clk-state { 4599 pins = "gpio40", "gpio41", "gpio42"; 4600 function = "qup12"; 4601 }; 4602 4603 qup_spi10_cs: qup-spi10-cs-state { 4604 pins = "gpio43"; 4605 function = "qup12"; 4606 }; 4607 4608 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4609 pins = "gpio43"; 4610 function = "gpio"; 4611 }; 4612 4613 qup_spi11_data_clk: qup-spi11-data-clk-state { 4614 pins = "gpio44", "gpio45", "gpio46"; 4615 function = "qup13"; 4616 }; 4617 4618 qup_spi11_cs: qup-spi11-cs-state { 4619 pins = "gpio47"; 4620 function = "qup13"; 4621 }; 4622 4623 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4624 pins = "gpio47"; 4625 function = "gpio"; 4626 }; 4627 4628 qup_spi12_data_clk: qup-spi12-data-clk-state { 4629 pins = "gpio48", "gpio49", "gpio50"; 4630 function = "qup14"; 4631 }; 4632 4633 qup_spi12_cs: qup-spi12-cs-state { 4634 pins = "gpio51"; 4635 function = "qup14"; 4636 }; 4637 4638 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4639 pins = "gpio51"; 4640 function = "gpio"; 4641 }; 4642 4643 qup_spi13_data_clk: qup-spi13-data-clk-state { 4644 pins = "gpio52", "gpio53", "gpio54"; 4645 function = "qup15"; 4646 }; 4647 4648 qup_spi13_cs: qup-spi13-cs-state { 4649 pins = "gpio55"; 4650 function = "qup15"; 4651 }; 4652 4653 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4654 pins = "gpio55"; 4655 function = "gpio"; 4656 }; 4657 4658 qup_spi14_data_clk: qup-spi14-data-clk-state { 4659 pins = "gpio56", "gpio57", "gpio58"; 4660 function = "qup16"; 4661 }; 4662 4663 qup_spi14_cs: qup-spi14-cs-state { 4664 pins = "gpio59"; 4665 function = "qup16"; 4666 }; 4667 4668 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4669 pins = "gpio59"; 4670 function = "gpio"; 4671 }; 4672 4673 qup_spi15_data_clk: qup-spi15-data-clk-state { 4674 pins = "gpio60", "gpio61", "gpio62"; 4675 function = "qup17"; 4676 }; 4677 4678 qup_spi15_cs: qup-spi15-cs-state { 4679 pins = "gpio63"; 4680 function = "qup17"; 4681 }; 4682 4683 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4684 pins = "gpio63"; 4685 function = "gpio"; 4686 }; 4687 4688 qup_uart0_cts: qup-uart0-cts-state { 4689 pins = "gpio0"; 4690 function = "qup00"; 4691 }; 4692 4693 qup_uart0_rts: qup-uart0-rts-state { 4694 pins = "gpio1"; 4695 function = "qup00"; 4696 }; 4697 4698 qup_uart0_tx: qup-uart0-tx-state { 4699 pins = "gpio2"; 4700 function = "qup00"; 4701 }; 4702 4703 qup_uart0_rx: qup-uart0-rx-state { 4704 pins = "gpio3"; 4705 function = "qup00"; 4706 }; 4707 4708 qup_uart1_cts: qup-uart1-cts-state { 4709 pins = "gpio4"; 4710 function = "qup01"; 4711 }; 4712 4713 qup_uart1_rts: qup-uart1-rts-state { 4714 pins = "gpio5"; 4715 function = "qup01"; 4716 }; 4717 4718 qup_uart1_tx: qup-uart1-tx-state { 4719 pins = "gpio6"; 4720 function = "qup01"; 4721 }; 4722 4723 qup_uart1_rx: qup-uart1-rx-state { 4724 pins = "gpio7"; 4725 function = "qup01"; 4726 }; 4727 4728 qup_uart2_cts: qup-uart2-cts-state { 4729 pins = "gpio8"; 4730 function = "qup02"; 4731 }; 4732 4733 qup_uart2_rts: qup-uart2-rts-state { 4734 pins = "gpio9"; 4735 function = "qup02"; 4736 }; 4737 4738 qup_uart2_tx: qup-uart2-tx-state { 4739 pins = "gpio10"; 4740 function = "qup02"; 4741 }; 4742 4743 qup_uart2_rx: qup-uart2-rx-state { 4744 pins = "gpio11"; 4745 function = "qup02"; 4746 }; 4747 4748 qup_uart3_cts: qup-uart3-cts-state { 4749 pins = "gpio12"; 4750 function = "qup03"; 4751 }; 4752 4753 qup_uart3_rts: qup-uart3-rts-state { 4754 pins = "gpio13"; 4755 function = "qup03"; 4756 }; 4757 4758 qup_uart3_tx: qup-uart3-tx-state { 4759 pins = "gpio14"; 4760 function = "qup03"; 4761 }; 4762 4763 qup_uart3_rx: qup-uart3-rx-state { 4764 pins = "gpio15"; 4765 function = "qup03"; 4766 }; 4767 4768 qup_uart4_cts: qup-uart4-cts-state { 4769 pins = "gpio16"; 4770 function = "qup04"; 4771 }; 4772 4773 qup_uart4_rts: qup-uart4-rts-state { 4774 pins = "gpio17"; 4775 function = "qup04"; 4776 }; 4777 4778 qup_uart4_tx: qup-uart4-tx-state { 4779 pins = "gpio18"; 4780 function = "qup04"; 4781 }; 4782 4783 qup_uart4_rx: qup-uart4-rx-state { 4784 pins = "gpio19"; 4785 function = "qup04"; 4786 }; 4787 4788 qup_uart5_cts: qup-uart5-cts-state { 4789 pins = "gpio20"; 4790 function = "qup05"; 4791 }; 4792 4793 qup_uart5_rts: qup-uart5-rts-state { 4794 pins = "gpio21"; 4795 function = "qup05"; 4796 }; 4797 4798 qup_uart5_tx: qup-uart5-tx-state { 4799 pins = "gpio22"; 4800 function = "qup05"; 4801 }; 4802 4803 qup_uart5_rx: qup-uart5-rx-state { 4804 pins = "gpio23"; 4805 function = "qup05"; 4806 }; 4807 4808 qup_uart6_cts: qup-uart6-cts-state { 4809 pins = "gpio24"; 4810 function = "qup06"; 4811 }; 4812 4813 qup_uart6_rts: qup-uart6-rts-state { 4814 pins = "gpio25"; 4815 function = "qup06"; 4816 }; 4817 4818 qup_uart6_tx: qup-uart6-tx-state { 4819 pins = "gpio26"; 4820 function = "qup06"; 4821 }; 4822 4823 qup_uart6_rx: qup-uart6-rx-state { 4824 pins = "gpio27"; 4825 function = "qup06"; 4826 }; 4827 4828 qup_uart7_cts: qup-uart7-cts-state { 4829 pins = "gpio28"; 4830 function = "qup07"; 4831 }; 4832 4833 qup_uart7_rts: qup-uart7-rts-state { 4834 pins = "gpio29"; 4835 function = "qup07"; 4836 }; 4837 4838 qup_uart7_tx: qup-uart7-tx-state { 4839 pins = "gpio30"; 4840 function = "qup07"; 4841 }; 4842 4843 qup_uart7_rx: qup-uart7-rx-state { 4844 pins = "gpio31"; 4845 function = "qup07"; 4846 }; 4847 4848 qup_uart8_cts: qup-uart8-cts-state { 4849 pins = "gpio32"; 4850 function = "qup10"; 4851 }; 4852 4853 qup_uart8_rts: qup-uart8-rts-state { 4854 pins = "gpio33"; 4855 function = "qup10"; 4856 }; 4857 4858 qup_uart8_tx: qup-uart8-tx-state { 4859 pins = "gpio34"; 4860 function = "qup10"; 4861 }; 4862 4863 qup_uart8_rx: qup-uart8-rx-state { 4864 pins = "gpio35"; 4865 function = "qup10"; 4866 }; 4867 4868 qup_uart9_cts: qup-uart9-cts-state { 4869 pins = "gpio36"; 4870 function = "qup11"; 4871 }; 4872 4873 qup_uart9_rts: qup-uart9-rts-state { 4874 pins = "gpio37"; 4875 function = "qup11"; 4876 }; 4877 4878 qup_uart9_tx: qup-uart9-tx-state { 4879 pins = "gpio38"; 4880 function = "qup11"; 4881 }; 4882 4883 qup_uart9_rx: qup-uart9-rx-state { 4884 pins = "gpio39"; 4885 function = "qup11"; 4886 }; 4887 4888 qup_uart10_cts: qup-uart10-cts-state { 4889 pins = "gpio40"; 4890 function = "qup12"; 4891 }; 4892 4893 qup_uart10_rts: qup-uart10-rts-state { 4894 pins = "gpio41"; 4895 function = "qup12"; 4896 }; 4897 4898 qup_uart10_tx: qup-uart10-tx-state { 4899 pins = "gpio42"; 4900 function = "qup12"; 4901 }; 4902 4903 qup_uart10_rx: qup-uart10-rx-state { 4904 pins = "gpio43"; 4905 function = "qup12"; 4906 }; 4907 4908 qup_uart11_cts: qup-uart11-cts-state { 4909 pins = "gpio44"; 4910 function = "qup13"; 4911 }; 4912 4913 qup_uart11_rts: qup-uart11-rts-state { 4914 pins = "gpio45"; 4915 function = "qup13"; 4916 }; 4917 4918 qup_uart11_tx: qup-uart11-tx-state { 4919 pins = "gpio46"; 4920 function = "qup13"; 4921 }; 4922 4923 qup_uart11_rx: qup-uart11-rx-state { 4924 pins = "gpio47"; 4925 function = "qup13"; 4926 }; 4927 4928 qup_uart12_cts: qup-uart12-cts-state { 4929 pins = "gpio48"; 4930 function = "qup14"; 4931 }; 4932 4933 qup_uart12_rts: qup-uart12-rts-state { 4934 pins = "gpio49"; 4935 function = "qup14"; 4936 }; 4937 4938 qup_uart12_tx: qup-uart12-tx-state { 4939 pins = "gpio50"; 4940 function = "qup14"; 4941 }; 4942 4943 qup_uart12_rx: qup-uart12-rx-state { 4944 pins = "gpio51"; 4945 function = "qup14"; 4946 }; 4947 4948 qup_uart13_cts: qup-uart13-cts-state { 4949 pins = "gpio52"; 4950 function = "qup15"; 4951 }; 4952 4953 qup_uart13_rts: qup-uart13-rts-state { 4954 pins = "gpio53"; 4955 function = "qup15"; 4956 }; 4957 4958 qup_uart13_tx: qup-uart13-tx-state { 4959 pins = "gpio54"; 4960 function = "qup15"; 4961 }; 4962 4963 qup_uart13_rx: qup-uart13-rx-state { 4964 pins = "gpio55"; 4965 function = "qup15"; 4966 }; 4967 4968 qup_uart14_cts: qup-uart14-cts-state { 4969 pins = "gpio56"; 4970 function = "qup16"; 4971 }; 4972 4973 qup_uart14_rts: qup-uart14-rts-state { 4974 pins = "gpio57"; 4975 function = "qup16"; 4976 }; 4977 4978 qup_uart14_tx: qup-uart14-tx-state { 4979 pins = "gpio58"; 4980 function = "qup16"; 4981 }; 4982 4983 qup_uart14_rx: qup-uart14-rx-state { 4984 pins = "gpio59"; 4985 function = "qup16"; 4986 }; 4987 4988 qup_uart15_cts: qup-uart15-cts-state { 4989 pins = "gpio60"; 4990 function = "qup17"; 4991 }; 4992 4993 qup_uart15_rts: qup-uart15-rts-state { 4994 pins = "gpio61"; 4995 function = "qup17"; 4996 }; 4997 4998 qup_uart15_tx: qup-uart15-tx-state { 4999 pins = "gpio62"; 5000 function = "qup17"; 5001 }; 5002 5003 qup_uart15_rx: qup-uart15-rx-state { 5004 pins = "gpio63"; 5005 function = "qup17"; 5006 }; 5007 5008 sdc1_clk: sdc1-clk-state { 5009 pins = "sdc1_clk"; 5010 }; 5011 5012 sdc1_cmd: sdc1-cmd-state { 5013 pins = "sdc1_cmd"; 5014 }; 5015 5016 sdc1_data: sdc1-data-state { 5017 pins = "sdc1_data"; 5018 }; 5019 5020 sdc1_rclk: sdc1-rclk-state { 5021 pins = "sdc1_rclk"; 5022 }; 5023 5024 sdc1_clk_sleep: sdc1-clk-sleep-state { 5025 pins = "sdc1_clk"; 5026 drive-strength = <2>; 5027 bias-bus-hold; 5028 }; 5029 5030 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5031 pins = "sdc1_cmd"; 5032 drive-strength = <2>; 5033 bias-bus-hold; 5034 }; 5035 5036 sdc1_data_sleep: sdc1-data-sleep-state { 5037 pins = "sdc1_data"; 5038 drive-strength = <2>; 5039 bias-bus-hold; 5040 }; 5041 5042 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5043 pins = "sdc1_rclk"; 5044 drive-strength = <2>; 5045 bias-bus-hold; 5046 }; 5047 5048 sdc2_clk: sdc2-clk-state { 5049 pins = "sdc2_clk"; 5050 }; 5051 5052 sdc2_cmd: sdc2-cmd-state { 5053 pins = "sdc2_cmd"; 5054 }; 5055 5056 sdc2_data: sdc2-data-state { 5057 pins = "sdc2_data"; 5058 }; 5059 5060 sdc2_clk_sleep: sdc2-clk-sleep-state { 5061 pins = "sdc2_clk"; 5062 drive-strength = <2>; 5063 bias-bus-hold; 5064 }; 5065 5066 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5067 pins = "sdc2_cmd"; 5068 drive-strength = <2>; 5069 bias-bus-hold; 5070 }; 5071 5072 sdc2_data_sleep: sdc2-data-sleep-state { 5073 pins = "sdc2_data"; 5074 drive-strength = <2>; 5075 bias-bus-hold; 5076 }; 5077 }; 5078 5079 sram@146a5000 { 5080 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5081 reg = <0 0x146a5000 0 0x6000>; 5082 5083 #address-cells = <1>; 5084 #size-cells = <1>; 5085 5086 ranges = <0 0 0x146a5000 0x6000>; 5087 5088 pil-reloc@594c { 5089 compatible = "qcom,pil-reloc-info"; 5090 reg = <0x594c 0xc8>; 5091 }; 5092 }; 5093 5094 apps_smmu: iommu@15000000 { 5095 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5096 reg = <0 0x15000000 0 0x100000>; 5097 #iommu-cells = <2>; 5098 #global-interrupts = <1>; 5099 dma-coherent; 5100 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5181 }; 5182 5183 intc: interrupt-controller@17a00000 { 5184 compatible = "arm,gic-v3"; 5185 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5186 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5187 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5188 #interrupt-cells = <3>; 5189 interrupt-controller; 5190 #address-cells = <2>; 5191 #size-cells = <2>; 5192 ranges; 5193 5194 msi-controller@17a40000 { 5195 compatible = "arm,gic-v3-its"; 5196 reg = <0 0x17a40000 0 0x20000>; 5197 msi-controller; 5198 #msi-cells = <1>; 5199 status = "disabled"; 5200 }; 5201 }; 5202 5203 watchdog: watchdog@17c10000 { 5204 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5205 reg = <0 0x17c10000 0 0x1000>; 5206 clocks = <&sleep_clk>; 5207 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5208 status = "reserved"; /* Owned by Gunyah hyp */ 5209 }; 5210 5211 timer@17c20000 { 5212 #address-cells = <1>; 5213 #size-cells = <1>; 5214 ranges = <0 0 0 0x20000000>; 5215 compatible = "arm,armv7-timer-mem"; 5216 reg = <0 0x17c20000 0 0x1000>; 5217 5218 frame@17c21000 { 5219 frame-number = <0>; 5220 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5221 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5222 reg = <0x17c21000 0x1000>, 5223 <0x17c22000 0x1000>; 5224 }; 5225 5226 frame@17c23000 { 5227 frame-number = <1>; 5228 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5229 reg = <0x17c23000 0x1000>; 5230 status = "disabled"; 5231 }; 5232 5233 frame@17c25000 { 5234 frame-number = <2>; 5235 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5236 reg = <0x17c25000 0x1000>; 5237 status = "disabled"; 5238 }; 5239 5240 frame@17c27000 { 5241 frame-number = <3>; 5242 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5243 reg = <0x17c27000 0x1000>; 5244 status = "disabled"; 5245 }; 5246 5247 frame@17c29000 { 5248 frame-number = <4>; 5249 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5250 reg = <0x17c29000 0x1000>; 5251 status = "disabled"; 5252 }; 5253 5254 frame@17c2b000 { 5255 frame-number = <5>; 5256 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5257 reg = <0x17c2b000 0x1000>; 5258 status = "disabled"; 5259 }; 5260 5261 frame@17c2d000 { 5262 frame-number = <6>; 5263 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5264 reg = <0x17c2d000 0x1000>; 5265 status = "disabled"; 5266 }; 5267 }; 5268 5269 apps_rsc: rsc@18200000 { 5270 compatible = "qcom,rpmh-rsc"; 5271 reg = <0 0x18200000 0 0x10000>, 5272 <0 0x18210000 0 0x10000>, 5273 <0 0x18220000 0 0x10000>; 5274 reg-names = "drv-0", "drv-1", "drv-2"; 5275 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5276 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5277 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5278 qcom,tcs-offset = <0xd00>; 5279 qcom,drv-id = <2>; 5280 qcom,tcs-config = <ACTIVE_TCS 2>, 5281 <SLEEP_TCS 3>, 5282 <WAKE_TCS 3>, 5283 <CONTROL_TCS 1>; 5284 5285 apps_bcm_voter: bcm-voter { 5286 compatible = "qcom,bcm-voter"; 5287 }; 5288 5289 rpmhpd: power-controller { 5290 compatible = "qcom,sc7280-rpmhpd"; 5291 #power-domain-cells = <1>; 5292 operating-points-v2 = <&rpmhpd_opp_table>; 5293 5294 rpmhpd_opp_table: opp-table { 5295 compatible = "operating-points-v2"; 5296 5297 rpmhpd_opp_ret: opp1 { 5298 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5299 }; 5300 5301 rpmhpd_opp_low_svs: opp2 { 5302 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5303 }; 5304 5305 rpmhpd_opp_svs: opp3 { 5306 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5307 }; 5308 5309 rpmhpd_opp_svs_l1: opp4 { 5310 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5311 }; 5312 5313 rpmhpd_opp_svs_l2: opp5 { 5314 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5315 }; 5316 5317 rpmhpd_opp_nom: opp6 { 5318 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5319 }; 5320 5321 rpmhpd_opp_nom_l1: opp7 { 5322 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5323 }; 5324 5325 rpmhpd_opp_turbo: opp8 { 5326 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5327 }; 5328 5329 rpmhpd_opp_turbo_l1: opp9 { 5330 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5331 }; 5332 }; 5333 }; 5334 5335 rpmhcc: clock-controller { 5336 compatible = "qcom,sc7280-rpmh-clk"; 5337 clocks = <&xo_board>; 5338 clock-names = "xo"; 5339 #clock-cells = <1>; 5340 }; 5341 }; 5342 5343 epss_l3: interconnect@18590000 { 5344 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5345 reg = <0 0x18590000 0 0x1000>; 5346 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5347 clock-names = "xo", "alternate"; 5348 #interconnect-cells = <1>; 5349 }; 5350 5351 cpufreq_hw: cpufreq@18591000 { 5352 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5353 reg = <0 0x18591000 0 0x1000>, 5354 <0 0x18592000 0 0x1000>, 5355 <0 0x18593000 0 0x1000>; 5356 5357 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5358 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5359 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5360 interrupt-names = "dcvsh-irq-0", 5361 "dcvsh-irq-1", 5362 "dcvsh-irq-2"; 5363 5364 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5365 clock-names = "xo", "alternate"; 5366 #freq-domain-cells = <1>; 5367 #clock-cells = <1>; 5368 }; 5369 }; 5370 5371 thermal_zones: thermal-zones { 5372 cpu0-thermal { 5373 polling-delay-passive = <250>; 5374 polling-delay = <0>; 5375 5376 thermal-sensors = <&tsens0 1>; 5377 5378 trips { 5379 cpu0_alert0: trip-point0 { 5380 temperature = <90000>; 5381 hysteresis = <2000>; 5382 type = "passive"; 5383 }; 5384 5385 cpu0_alert1: trip-point1 { 5386 temperature = <95000>; 5387 hysteresis = <2000>; 5388 type = "passive"; 5389 }; 5390 5391 cpu0_crit: cpu-crit { 5392 temperature = <110000>; 5393 hysteresis = <0>; 5394 type = "critical"; 5395 }; 5396 }; 5397 5398 cooling-maps { 5399 map0 { 5400 trip = <&cpu0_alert0>; 5401 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5402 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5403 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5405 }; 5406 map1 { 5407 trip = <&cpu0_alert1>; 5408 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5409 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5412 }; 5413 }; 5414 }; 5415 5416 cpu1-thermal { 5417 polling-delay-passive = <250>; 5418 polling-delay = <0>; 5419 5420 thermal-sensors = <&tsens0 2>; 5421 5422 trips { 5423 cpu1_alert0: trip-point0 { 5424 temperature = <90000>; 5425 hysteresis = <2000>; 5426 type = "passive"; 5427 }; 5428 5429 cpu1_alert1: trip-point1 { 5430 temperature = <95000>; 5431 hysteresis = <2000>; 5432 type = "passive"; 5433 }; 5434 5435 cpu1_crit: cpu-crit { 5436 temperature = <110000>; 5437 hysteresis = <0>; 5438 type = "critical"; 5439 }; 5440 }; 5441 5442 cooling-maps { 5443 map0 { 5444 trip = <&cpu1_alert0>; 5445 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5446 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5447 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5449 }; 5450 map1 { 5451 trip = <&cpu1_alert1>; 5452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5456 }; 5457 }; 5458 }; 5459 5460 cpu2-thermal { 5461 polling-delay-passive = <250>; 5462 polling-delay = <0>; 5463 5464 thermal-sensors = <&tsens0 3>; 5465 5466 trips { 5467 cpu2_alert0: trip-point0 { 5468 temperature = <90000>; 5469 hysteresis = <2000>; 5470 type = "passive"; 5471 }; 5472 5473 cpu2_alert1: trip-point1 { 5474 temperature = <95000>; 5475 hysteresis = <2000>; 5476 type = "passive"; 5477 }; 5478 5479 cpu2_crit: cpu-crit { 5480 temperature = <110000>; 5481 hysteresis = <0>; 5482 type = "critical"; 5483 }; 5484 }; 5485 5486 cooling-maps { 5487 map0 { 5488 trip = <&cpu2_alert0>; 5489 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5490 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5491 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5493 }; 5494 map1 { 5495 trip = <&cpu2_alert1>; 5496 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5497 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5500 }; 5501 }; 5502 }; 5503 5504 cpu3-thermal { 5505 polling-delay-passive = <250>; 5506 polling-delay = <0>; 5507 5508 thermal-sensors = <&tsens0 4>; 5509 5510 trips { 5511 cpu3_alert0: trip-point0 { 5512 temperature = <90000>; 5513 hysteresis = <2000>; 5514 type = "passive"; 5515 }; 5516 5517 cpu3_alert1: trip-point1 { 5518 temperature = <95000>; 5519 hysteresis = <2000>; 5520 type = "passive"; 5521 }; 5522 5523 cpu3_crit: cpu-crit { 5524 temperature = <110000>; 5525 hysteresis = <0>; 5526 type = "critical"; 5527 }; 5528 }; 5529 5530 cooling-maps { 5531 map0 { 5532 trip = <&cpu3_alert0>; 5533 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5534 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5537 }; 5538 map1 { 5539 trip = <&cpu3_alert1>; 5540 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5541 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5544 }; 5545 }; 5546 }; 5547 5548 cpu4-thermal { 5549 polling-delay-passive = <250>; 5550 polling-delay = <0>; 5551 5552 thermal-sensors = <&tsens0 7>; 5553 5554 trips { 5555 cpu4_alert0: trip-point0 { 5556 temperature = <90000>; 5557 hysteresis = <2000>; 5558 type = "passive"; 5559 }; 5560 5561 cpu4_alert1: trip-point1 { 5562 temperature = <95000>; 5563 hysteresis = <2000>; 5564 type = "passive"; 5565 }; 5566 5567 cpu4_crit: cpu-crit { 5568 temperature = <110000>; 5569 hysteresis = <0>; 5570 type = "critical"; 5571 }; 5572 }; 5573 5574 cooling-maps { 5575 map0 { 5576 trip = <&cpu4_alert0>; 5577 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5578 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5581 }; 5582 map1 { 5583 trip = <&cpu4_alert1>; 5584 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5585 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5588 }; 5589 }; 5590 }; 5591 5592 cpu5-thermal { 5593 polling-delay-passive = <250>; 5594 polling-delay = <0>; 5595 5596 thermal-sensors = <&tsens0 8>; 5597 5598 trips { 5599 cpu5_alert0: trip-point0 { 5600 temperature = <90000>; 5601 hysteresis = <2000>; 5602 type = "passive"; 5603 }; 5604 5605 cpu5_alert1: trip-point1 { 5606 temperature = <95000>; 5607 hysteresis = <2000>; 5608 type = "passive"; 5609 }; 5610 5611 cpu5_crit: cpu-crit { 5612 temperature = <110000>; 5613 hysteresis = <0>; 5614 type = "critical"; 5615 }; 5616 }; 5617 5618 cooling-maps { 5619 map0 { 5620 trip = <&cpu5_alert0>; 5621 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5622 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5623 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5625 }; 5626 map1 { 5627 trip = <&cpu5_alert1>; 5628 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5629 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5632 }; 5633 }; 5634 }; 5635 5636 cpu6-thermal { 5637 polling-delay-passive = <250>; 5638 polling-delay = <0>; 5639 5640 thermal-sensors = <&tsens0 9>; 5641 5642 trips { 5643 cpu6_alert0: trip-point0 { 5644 temperature = <90000>; 5645 hysteresis = <2000>; 5646 type = "passive"; 5647 }; 5648 5649 cpu6_alert1: trip-point1 { 5650 temperature = <95000>; 5651 hysteresis = <2000>; 5652 type = "passive"; 5653 }; 5654 5655 cpu6_crit: cpu-crit { 5656 temperature = <110000>; 5657 hysteresis = <0>; 5658 type = "critical"; 5659 }; 5660 }; 5661 5662 cooling-maps { 5663 map0 { 5664 trip = <&cpu6_alert0>; 5665 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5666 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5667 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5669 }; 5670 map1 { 5671 trip = <&cpu6_alert1>; 5672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5676 }; 5677 }; 5678 }; 5679 5680 cpu7-thermal { 5681 polling-delay-passive = <250>; 5682 polling-delay = <0>; 5683 5684 thermal-sensors = <&tsens0 10>; 5685 5686 trips { 5687 cpu7_alert0: trip-point0 { 5688 temperature = <90000>; 5689 hysteresis = <2000>; 5690 type = "passive"; 5691 }; 5692 5693 cpu7_alert1: trip-point1 { 5694 temperature = <95000>; 5695 hysteresis = <2000>; 5696 type = "passive"; 5697 }; 5698 5699 cpu7_crit: cpu-crit { 5700 temperature = <110000>; 5701 hysteresis = <0>; 5702 type = "critical"; 5703 }; 5704 }; 5705 5706 cooling-maps { 5707 map0 { 5708 trip = <&cpu7_alert0>; 5709 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5710 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5713 }; 5714 map1 { 5715 trip = <&cpu7_alert1>; 5716 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5720 }; 5721 }; 5722 }; 5723 5724 cpu8-thermal { 5725 polling-delay-passive = <250>; 5726 polling-delay = <0>; 5727 5728 thermal-sensors = <&tsens0 11>; 5729 5730 trips { 5731 cpu8_alert0: trip-point0 { 5732 temperature = <90000>; 5733 hysteresis = <2000>; 5734 type = "passive"; 5735 }; 5736 5737 cpu8_alert1: trip-point1 { 5738 temperature = <95000>; 5739 hysteresis = <2000>; 5740 type = "passive"; 5741 }; 5742 5743 cpu8_crit: cpu-crit { 5744 temperature = <110000>; 5745 hysteresis = <0>; 5746 type = "critical"; 5747 }; 5748 }; 5749 5750 cooling-maps { 5751 map0 { 5752 trip = <&cpu8_alert0>; 5753 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5754 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5757 }; 5758 map1 { 5759 trip = <&cpu8_alert1>; 5760 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5764 }; 5765 }; 5766 }; 5767 5768 cpu9-thermal { 5769 polling-delay-passive = <250>; 5770 polling-delay = <0>; 5771 5772 thermal-sensors = <&tsens0 12>; 5773 5774 trips { 5775 cpu9_alert0: trip-point0 { 5776 temperature = <90000>; 5777 hysteresis = <2000>; 5778 type = "passive"; 5779 }; 5780 5781 cpu9_alert1: trip-point1 { 5782 temperature = <95000>; 5783 hysteresis = <2000>; 5784 type = "passive"; 5785 }; 5786 5787 cpu9_crit: cpu-crit { 5788 temperature = <110000>; 5789 hysteresis = <0>; 5790 type = "critical"; 5791 }; 5792 }; 5793 5794 cooling-maps { 5795 map0 { 5796 trip = <&cpu9_alert0>; 5797 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5801 }; 5802 map1 { 5803 trip = <&cpu9_alert1>; 5804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5808 }; 5809 }; 5810 }; 5811 5812 cpu10-thermal { 5813 polling-delay-passive = <250>; 5814 polling-delay = <0>; 5815 5816 thermal-sensors = <&tsens0 13>; 5817 5818 trips { 5819 cpu10_alert0: trip-point0 { 5820 temperature = <90000>; 5821 hysteresis = <2000>; 5822 type = "passive"; 5823 }; 5824 5825 cpu10_alert1: trip-point1 { 5826 temperature = <95000>; 5827 hysteresis = <2000>; 5828 type = "passive"; 5829 }; 5830 5831 cpu10_crit: cpu-crit { 5832 temperature = <110000>; 5833 hysteresis = <0>; 5834 type = "critical"; 5835 }; 5836 }; 5837 5838 cooling-maps { 5839 map0 { 5840 trip = <&cpu10_alert0>; 5841 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5845 }; 5846 map1 { 5847 trip = <&cpu10_alert1>; 5848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5852 }; 5853 }; 5854 }; 5855 5856 cpu11-thermal { 5857 polling-delay-passive = <250>; 5858 polling-delay = <0>; 5859 5860 thermal-sensors = <&tsens0 14>; 5861 5862 trips { 5863 cpu11_alert0: trip-point0 { 5864 temperature = <90000>; 5865 hysteresis = <2000>; 5866 type = "passive"; 5867 }; 5868 5869 cpu11_alert1: trip-point1 { 5870 temperature = <95000>; 5871 hysteresis = <2000>; 5872 type = "passive"; 5873 }; 5874 5875 cpu11_crit: cpu-crit { 5876 temperature = <110000>; 5877 hysteresis = <0>; 5878 type = "critical"; 5879 }; 5880 }; 5881 5882 cooling-maps { 5883 map0 { 5884 trip = <&cpu11_alert0>; 5885 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5886 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5887 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5888 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5889 }; 5890 map1 { 5891 trip = <&cpu11_alert1>; 5892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5896 }; 5897 }; 5898 }; 5899 5900 aoss0-thermal { 5901 polling-delay-passive = <0>; 5902 polling-delay = <0>; 5903 5904 thermal-sensors = <&tsens0 0>; 5905 5906 trips { 5907 aoss0_alert0: trip-point0 { 5908 temperature = <90000>; 5909 hysteresis = <2000>; 5910 type = "hot"; 5911 }; 5912 5913 aoss0_crit: aoss0-crit { 5914 temperature = <110000>; 5915 hysteresis = <0>; 5916 type = "critical"; 5917 }; 5918 }; 5919 }; 5920 5921 aoss1-thermal { 5922 polling-delay-passive = <0>; 5923 polling-delay = <0>; 5924 5925 thermal-sensors = <&tsens1 0>; 5926 5927 trips { 5928 aoss1_alert0: trip-point0 { 5929 temperature = <90000>; 5930 hysteresis = <2000>; 5931 type = "hot"; 5932 }; 5933 5934 aoss1_crit: aoss1-crit { 5935 temperature = <110000>; 5936 hysteresis = <0>; 5937 type = "critical"; 5938 }; 5939 }; 5940 }; 5941 5942 cpuss0-thermal { 5943 polling-delay-passive = <0>; 5944 polling-delay = <0>; 5945 5946 thermal-sensors = <&tsens0 5>; 5947 5948 trips { 5949 cpuss0_alert0: trip-point0 { 5950 temperature = <90000>; 5951 hysteresis = <2000>; 5952 type = "hot"; 5953 }; 5954 cpuss0_crit: cluster0-crit { 5955 temperature = <110000>; 5956 hysteresis = <0>; 5957 type = "critical"; 5958 }; 5959 }; 5960 }; 5961 5962 cpuss1-thermal { 5963 polling-delay-passive = <0>; 5964 polling-delay = <0>; 5965 5966 thermal-sensors = <&tsens0 6>; 5967 5968 trips { 5969 cpuss1_alert0: trip-point0 { 5970 temperature = <90000>; 5971 hysteresis = <2000>; 5972 type = "hot"; 5973 }; 5974 cpuss1_crit: cluster0-crit { 5975 temperature = <110000>; 5976 hysteresis = <0>; 5977 type = "critical"; 5978 }; 5979 }; 5980 }; 5981 5982 gpuss0-thermal { 5983 polling-delay-passive = <100>; 5984 polling-delay = <0>; 5985 5986 thermal-sensors = <&tsens1 1>; 5987 5988 trips { 5989 gpuss0_alert0: trip-point0 { 5990 temperature = <95000>; 5991 hysteresis = <2000>; 5992 type = "passive"; 5993 }; 5994 5995 gpuss0_crit: gpuss0-crit { 5996 temperature = <110000>; 5997 hysteresis = <0>; 5998 type = "critical"; 5999 }; 6000 }; 6001 6002 cooling-maps { 6003 map0 { 6004 trip = <&gpuss0_alert0>; 6005 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6006 }; 6007 }; 6008 }; 6009 6010 gpuss1-thermal { 6011 polling-delay-passive = <100>; 6012 polling-delay = <0>; 6013 6014 thermal-sensors = <&tsens1 2>; 6015 6016 trips { 6017 gpuss1_alert0: trip-point0 { 6018 temperature = <95000>; 6019 hysteresis = <2000>; 6020 type = "passive"; 6021 }; 6022 6023 gpuss1_crit: gpuss1-crit { 6024 temperature = <110000>; 6025 hysteresis = <0>; 6026 type = "critical"; 6027 }; 6028 }; 6029 6030 cooling-maps { 6031 map0 { 6032 trip = <&gpuss1_alert0>; 6033 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6034 }; 6035 }; 6036 }; 6037 6038 nspss0-thermal { 6039 polling-delay-passive = <0>; 6040 polling-delay = <0>; 6041 6042 thermal-sensors = <&tsens1 3>; 6043 6044 trips { 6045 nspss0_alert0: trip-point0 { 6046 temperature = <90000>; 6047 hysteresis = <2000>; 6048 type = "hot"; 6049 }; 6050 6051 nspss0_crit: nspss0-crit { 6052 temperature = <110000>; 6053 hysteresis = <0>; 6054 type = "critical"; 6055 }; 6056 }; 6057 }; 6058 6059 nspss1-thermal { 6060 polling-delay-passive = <0>; 6061 polling-delay = <0>; 6062 6063 thermal-sensors = <&tsens1 4>; 6064 6065 trips { 6066 nspss1_alert0: trip-point0 { 6067 temperature = <90000>; 6068 hysteresis = <2000>; 6069 type = "hot"; 6070 }; 6071 6072 nspss1_crit: nspss1-crit { 6073 temperature = <110000>; 6074 hysteresis = <0>; 6075 type = "critical"; 6076 }; 6077 }; 6078 }; 6079 6080 video-thermal { 6081 polling-delay-passive = <0>; 6082 polling-delay = <0>; 6083 6084 thermal-sensors = <&tsens1 5>; 6085 6086 trips { 6087 video_alert0: trip-point0 { 6088 temperature = <90000>; 6089 hysteresis = <2000>; 6090 type = "hot"; 6091 }; 6092 6093 video_crit: video-crit { 6094 temperature = <110000>; 6095 hysteresis = <0>; 6096 type = "critical"; 6097 }; 6098 }; 6099 }; 6100 6101 ddr-thermal { 6102 polling-delay-passive = <0>; 6103 polling-delay = <0>; 6104 6105 thermal-sensors = <&tsens1 6>; 6106 6107 trips { 6108 ddr_alert0: trip-point0 { 6109 temperature = <90000>; 6110 hysteresis = <2000>; 6111 type = "hot"; 6112 }; 6113 6114 ddr_crit: ddr-crit { 6115 temperature = <110000>; 6116 hysteresis = <0>; 6117 type = "critical"; 6118 }; 6119 }; 6120 }; 6121 6122 mdmss0-thermal { 6123 polling-delay-passive = <0>; 6124 polling-delay = <0>; 6125 6126 thermal-sensors = <&tsens1 7>; 6127 6128 trips { 6129 mdmss0_alert0: trip-point0 { 6130 temperature = <90000>; 6131 hysteresis = <2000>; 6132 type = "hot"; 6133 }; 6134 6135 mdmss0_crit: mdmss0-crit { 6136 temperature = <110000>; 6137 hysteresis = <0>; 6138 type = "critical"; 6139 }; 6140 }; 6141 }; 6142 6143 mdmss1-thermal { 6144 polling-delay-passive = <0>; 6145 polling-delay = <0>; 6146 6147 thermal-sensors = <&tsens1 8>; 6148 6149 trips { 6150 mdmss1_alert0: trip-point0 { 6151 temperature = <90000>; 6152 hysteresis = <2000>; 6153 type = "hot"; 6154 }; 6155 6156 mdmss1_crit: mdmss1-crit { 6157 temperature = <110000>; 6158 hysteresis = <0>; 6159 type = "critical"; 6160 }; 6161 }; 6162 }; 6163 6164 mdmss2-thermal { 6165 polling-delay-passive = <0>; 6166 polling-delay = <0>; 6167 6168 thermal-sensors = <&tsens1 9>; 6169 6170 trips { 6171 mdmss2_alert0: trip-point0 { 6172 temperature = <90000>; 6173 hysteresis = <2000>; 6174 type = "hot"; 6175 }; 6176 6177 mdmss2_crit: mdmss2-crit { 6178 temperature = <110000>; 6179 hysteresis = <0>; 6180 type = "critical"; 6181 }; 6182 }; 6183 }; 6184 6185 mdmss3-thermal { 6186 polling-delay-passive = <0>; 6187 polling-delay = <0>; 6188 6189 thermal-sensors = <&tsens1 10>; 6190 6191 trips { 6192 mdmss3_alert0: trip-point0 { 6193 temperature = <90000>; 6194 hysteresis = <2000>; 6195 type = "hot"; 6196 }; 6197 6198 mdmss3_crit: mdmss3-crit { 6199 temperature = <110000>; 6200 hysteresis = <0>; 6201 type = "critical"; 6202 }; 6203 }; 6204 }; 6205 6206 camera0-thermal { 6207 polling-delay-passive = <0>; 6208 polling-delay = <0>; 6209 6210 thermal-sensors = <&tsens1 11>; 6211 6212 trips { 6213 camera0_alert0: trip-point0 { 6214 temperature = <90000>; 6215 hysteresis = <2000>; 6216 type = "hot"; 6217 }; 6218 6219 camera0_crit: camera0-crit { 6220 temperature = <110000>; 6221 hysteresis = <0>; 6222 type = "critical"; 6223 }; 6224 }; 6225 }; 6226 }; 6227 6228 timer { 6229 compatible = "arm,armv8-timer"; 6230 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6231 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6232 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6233 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6234 }; 6235}; 6236