1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 756 wlan_smp2p_out: wlan-ap-to-wpss { 757 qcom,entry-name = "wlan"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 wlan_smp2p_in: wlan-wpss-to-ap { 762 qcom,entry-name = "wlan"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 }; 767 768 pmu { 769 compatible = "arm,armv8-pmuv3"; 770 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 771 }; 772 773 psci { 774 compatible = "arm,psci-1.0"; 775 method = "smc"; 776 }; 777 778 qspi_opp_table: opp-table-qspi { 779 compatible = "operating-points-v2"; 780 781 opp-75000000 { 782 opp-hz = /bits/ 64 <75000000>; 783 required-opps = <&rpmhpd_opp_low_svs>; 784 }; 785 786 opp-150000000 { 787 opp-hz = /bits/ 64 <150000000>; 788 required-opps = <&rpmhpd_opp_svs>; 789 }; 790 791 opp-200000000 { 792 opp-hz = /bits/ 64 <200000000>; 793 required-opps = <&rpmhpd_opp_svs_l1>; 794 }; 795 796 opp-300000000 { 797 opp-hz = /bits/ 64 <300000000>; 798 required-opps = <&rpmhpd_opp_nom>; 799 }; 800 }; 801 802 qup_opp_table: opp-table-qup { 803 compatible = "operating-points-v2"; 804 805 opp-75000000 { 806 opp-hz = /bits/ 64 <75000000>; 807 required-opps = <&rpmhpd_opp_low_svs>; 808 }; 809 810 opp-100000000 { 811 opp-hz = /bits/ 64 <100000000>; 812 required-opps = <&rpmhpd_opp_svs>; 813 }; 814 815 opp-128000000 { 816 opp-hz = /bits/ 64 <128000000>; 817 required-opps = <&rpmhpd_opp_nom>; 818 }; 819 }; 820 821 soc: soc@0 { 822 #address-cells = <2>; 823 #size-cells = <2>; 824 ranges = <0 0 0 0 0x10 0>; 825 dma-ranges = <0 0 0 0 0x10 0>; 826 compatible = "simple-bus"; 827 828 gcc: clock-controller@100000 { 829 compatible = "qcom,gcc-sc7280"; 830 reg = <0 0x00100000 0 0x1f0000>; 831 clocks = <&rpmhcc RPMH_CXO_CLK>, 832 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 833 <0>, <&pcie1_lane>, 834 <0>, <0>, <0>, <0>; 835 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 836 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 837 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 838 "ufs_phy_tx_symbol_0_clk", 839 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 840 #clock-cells = <1>; 841 #reset-cells = <1>; 842 #power-domain-cells = <1>; 843 power-domains = <&rpmhpd SC7280_CX>; 844 }; 845 846 ipcc: mailbox@408000 { 847 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 848 reg = <0 0x00408000 0 0x1000>; 849 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-controller; 851 #interrupt-cells = <3>; 852 #mbox-cells = <2>; 853 }; 854 855 qfprom: efuse@784000 { 856 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 857 reg = <0 0x00784000 0 0xa20>, 858 <0 0x00780000 0 0xa20>, 859 <0 0x00782000 0 0x120>, 860 <0 0x00786000 0 0x1fff>; 861 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 862 clock-names = "core"; 863 power-domains = <&rpmhpd SC7280_MX>; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 867 gpu_speed_bin: gpu_speed_bin@1e9 { 868 reg = <0x1e9 0x2>; 869 bits = <5 8>; 870 }; 871 }; 872 873 sdhc_1: mmc@7c4000 { 874 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 875 pinctrl-names = "default", "sleep"; 876 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 877 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 878 status = "disabled"; 879 880 reg = <0 0x007c4000 0 0x1000>, 881 <0 0x007c5000 0 0x1000>; 882 reg-names = "hc", "cqhci"; 883 884 iommus = <&apps_smmu 0xc0 0x0>; 885 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "hc_irq", "pwr_irq"; 888 889 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 890 <&gcc GCC_SDCC1_APPS_CLK>, 891 <&rpmhcc RPMH_CXO_CLK>; 892 clock-names = "iface", "core", "xo"; 893 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 895 interconnect-names = "sdhc-ddr","cpu-sdhc"; 896 power-domains = <&rpmhpd SC7280_CX>; 897 operating-points-v2 = <&sdhc1_opp_table>; 898 899 bus-width = <8>; 900 supports-cqe; 901 902 qcom,dll-config = <0x0007642c>; 903 qcom,ddr-config = <0x80040868>; 904 905 mmc-ddr-1_8v; 906 mmc-hs200-1_8v; 907 mmc-hs400-1_8v; 908 mmc-hs400-enhanced-strobe; 909 910 resets = <&gcc GCC_SDCC1_BCR>; 911 912 sdhc1_opp_table: opp-table { 913 compatible = "operating-points-v2"; 914 915 opp-100000000 { 916 opp-hz = /bits/ 64 <100000000>; 917 required-opps = <&rpmhpd_opp_low_svs>; 918 opp-peak-kBps = <1800000 400000>; 919 opp-avg-kBps = <100000 0>; 920 }; 921 922 opp-384000000 { 923 opp-hz = /bits/ 64 <384000000>; 924 required-opps = <&rpmhpd_opp_nom>; 925 opp-peak-kBps = <5400000 1600000>; 926 opp-avg-kBps = <390000 0>; 927 }; 928 }; 929 930 }; 931 932 gpi_dma0: dma-controller@900000 { 933 #dma-cells = <3>; 934 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 935 reg = <0 0x00900000 0 0x60000>; 936 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 948 dma-channels = <12>; 949 dma-channel-mask = <0x7f>; 950 iommus = <&apps_smmu 0x0136 0x0>; 951 status = "disabled"; 952 }; 953 954 qupv3_id_0: geniqup@9c0000 { 955 compatible = "qcom,geni-se-qup"; 956 reg = <0 0x009c0000 0 0x2000>; 957 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 958 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 959 clock-names = "m-ahb", "s-ahb"; 960 #address-cells = <2>; 961 #size-cells = <2>; 962 ranges; 963 iommus = <&apps_smmu 0x123 0x0>; 964 status = "disabled"; 965 966 i2c0: i2c@980000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0 0x00980000 0 0x4000>; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 970 clock-names = "se"; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c0_data_clk>; 973 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 978 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 979 interconnect-names = "qup-core", "qup-config", 980 "qup-memory"; 981 power-domains = <&rpmhpd SC7280_CX>; 982 required-opps = <&rpmhpd_opp_low_svs>; 983 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 984 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 spi0: spi@980000 { 990 compatible = "qcom,geni-spi"; 991 reg = <0 0x00980000 0 0x4000>; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 993 clock-names = "se"; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 996 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 power-domains = <&rpmhpd SC7280_CX>; 1000 operating-points-v2 = <&qup_opp_table>; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1003 interconnect-names = "qup-core", "qup-config"; 1004 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1005 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1006 dma-names = "tx", "rx"; 1007 status = "disabled"; 1008 }; 1009 1010 uart0: serial@980000 { 1011 compatible = "qcom,geni-uart"; 1012 reg = <0 0x00980000 0 0x4000>; 1013 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1014 clock-names = "se"; 1015 pinctrl-names = "default"; 1016 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1017 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1018 power-domains = <&rpmhpd SC7280_CX>; 1019 operating-points-v2 = <&qup_opp_table>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1021 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1022 interconnect-names = "qup-core", "qup-config"; 1023 status = "disabled"; 1024 }; 1025 1026 i2c1: i2c@984000 { 1027 compatible = "qcom,geni-i2c"; 1028 reg = <0 0x00984000 0 0x4000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1030 clock-names = "se"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_i2c1_data_clk>; 1033 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1038 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1039 interconnect-names = "qup-core", "qup-config", 1040 "qup-memory"; 1041 power-domains = <&rpmhpd SC7280_CX>; 1042 required-opps = <&rpmhpd_opp_low_svs>; 1043 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1044 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 status = "disabled"; 1047 }; 1048 1049 spi1: spi@984000 { 1050 compatible = "qcom,geni-spi"; 1051 reg = <0 0x00984000 0 0x4000>; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1053 clock-names = "se"; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1056 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 power-domains = <&rpmhpd SC7280_CX>; 1060 operating-points-v2 = <&qup_opp_table>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1063 interconnect-names = "qup-core", "qup-config"; 1064 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1065 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 status = "disabled"; 1068 }; 1069 1070 uart1: serial@984000 { 1071 compatible = "qcom,geni-uart"; 1072 reg = <0 0x00984000 0 0x4000>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1074 clock-names = "se"; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1077 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&rpmhpd SC7280_CX>; 1079 operating-points-v2 = <&qup_opp_table>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c2: i2c@988000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x00988000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_i2c2_data_clk>; 1093 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1098 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1099 interconnect-names = "qup-core", "qup-config", 1100 "qup-memory"; 1101 power-domains = <&rpmhpd SC7280_CX>; 1102 required-opps = <&rpmhpd_opp_low_svs>; 1103 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 status = "disabled"; 1107 }; 1108 1109 spi2: spi@988000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x00988000 0 0x4000>; 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1113 clock-names = "se"; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1116 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 power-domains = <&rpmhpd SC7280_CX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1125 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1126 dma-names = "tx", "rx"; 1127 status = "disabled"; 1128 }; 1129 1130 uart2: serial@988000 { 1131 compatible = "qcom,geni-uart"; 1132 reg = <0 0x00988000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1137 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd SC7280_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 status = "disabled"; 1144 }; 1145 1146 i2c3: i2c@98c000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x0098c000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c3_data_clk>; 1153 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1158 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1159 interconnect-names = "qup-core", "qup-config", 1160 "qup-memory"; 1161 power-domains = <&rpmhpd SC7280_CX>; 1162 required-opps = <&rpmhpd_opp_low_svs>; 1163 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 status = "disabled"; 1167 }; 1168 1169 spi3: spi@98c000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x0098c000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1176 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 power-domains = <&rpmhpd SC7280_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1183 interconnect-names = "qup-core", "qup-config"; 1184 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1185 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1186 dma-names = "tx", "rx"; 1187 status = "disabled"; 1188 }; 1189 1190 uart3: serial@98c000 { 1191 compatible = "qcom,geni-uart"; 1192 reg = <0 0x0098c000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1194 clock-names = "se"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1197 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1198 power-domains = <&rpmhpd SC7280_CX>; 1199 operating-points-v2 = <&qup_opp_table>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 status = "disabled"; 1204 }; 1205 1206 i2c4: i2c@990000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x00990000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c4_data_clk>; 1213 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1218 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1219 interconnect-names = "qup-core", "qup-config", 1220 "qup-memory"; 1221 power-domains = <&rpmhpd SC7280_CX>; 1222 required-opps = <&rpmhpd_opp_low_svs>; 1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1224 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1225 dma-names = "tx", "rx"; 1226 status = "disabled"; 1227 }; 1228 1229 spi4: spi@990000 { 1230 compatible = "qcom,geni-spi"; 1231 reg = <0 0x00990000 0 0x4000>; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1233 clock-names = "se"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1236 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 power-domains = <&rpmhpd SC7280_CX>; 1240 operating-points-v2 = <&qup_opp_table>; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1242 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1243 interconnect-names = "qup-core", "qup-config"; 1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1245 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1246 dma-names = "tx", "rx"; 1247 status = "disabled"; 1248 }; 1249 1250 uart4: serial@990000 { 1251 compatible = "qcom,geni-uart"; 1252 reg = <0 0x00990000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1254 clock-names = "se"; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1257 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1258 power-domains = <&rpmhpd SC7280_CX>; 1259 operating-points-v2 = <&qup_opp_table>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 status = "disabled"; 1264 }; 1265 1266 i2c5: i2c@994000 { 1267 compatible = "qcom,geni-i2c"; 1268 reg = <0 0x00994000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_i2c5_data_clk>; 1273 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1278 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1279 interconnect-names = "qup-core", "qup-config", 1280 "qup-memory"; 1281 power-domains = <&rpmhpd SC7280_CX>; 1282 required-opps = <&rpmhpd_opp_low_svs>; 1283 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1284 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1285 dma-names = "tx", "rx"; 1286 status = "disabled"; 1287 }; 1288 1289 spi5: spi@994000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00994000 0 0x4000>; 1292 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1293 clock-names = "se"; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1296 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 power-domains = <&rpmhpd SC7280_CX>; 1300 operating-points-v2 = <&qup_opp_table>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1303 interconnect-names = "qup-core", "qup-config"; 1304 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1305 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1306 dma-names = "tx", "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 uart5: serial@994000 { 1311 compatible = "qcom,geni-uart"; 1312 reg = <0 0x00994000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1314 clock-names = "se"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1317 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1318 power-domains = <&rpmhpd SC7280_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1322 interconnect-names = "qup-core", "qup-config"; 1323 status = "disabled"; 1324 }; 1325 1326 i2c6: i2c@998000 { 1327 compatible = "qcom,geni-i2c"; 1328 reg = <0 0x00998000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_i2c6_data_clk>; 1333 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", 1340 "qup-memory"; 1341 power-domains = <&rpmhpd SC7280_CX>; 1342 required-opps = <&rpmhpd_opp_low_svs>; 1343 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1344 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 status = "disabled"; 1347 }; 1348 1349 spi6: spi@998000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00998000 0 0x4000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1353 clock-names = "se"; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1356 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 power-domains = <&rpmhpd SC7280_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1365 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1366 dma-names = "tx", "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 uart6: serial@998000 { 1371 compatible = "qcom,geni-uart"; 1372 reg = <0 0x00998000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd SC7280_CX>; 1379 operating-points-v2 = <&qup_opp_table>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1382 interconnect-names = "qup-core", "qup-config"; 1383 status = "disabled"; 1384 }; 1385 1386 i2c7: i2c@99c000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x0099c000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c7_data_clk>; 1393 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1398 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1399 interconnect-names = "qup-core", "qup-config", 1400 "qup-memory"; 1401 power-domains = <&rpmhpd SC7280_CX>; 1402 required-opps = <&rpmhpd_opp_low_svs>; 1403 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1404 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1405 dma-names = "tx", "rx"; 1406 status = "disabled"; 1407 }; 1408 1409 spi7: spi@99c000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0 0x0099c000 0 0x4000>; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1413 clock-names = "se"; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1416 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 power-domains = <&rpmhpd SC7280_CX>; 1420 operating-points-v2 = <&qup_opp_table>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1425 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 uart7: serial@99c000 { 1431 compatible = "qcom,geni-uart"; 1432 reg = <0 0x0099c000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1437 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1438 power-domains = <&rpmhpd SC7280_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 status = "disabled"; 1444 }; 1445 }; 1446 1447 gpi_dma1: dma-controller@a00000 { 1448 #dma-cells = <3>; 1449 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1450 reg = <0 0x00a00000 0 0x60000>; 1451 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1463 dma-channels = <12>; 1464 dma-channel-mask = <0x1e>; 1465 iommus = <&apps_smmu 0x56 0x0>; 1466 status = "disabled"; 1467 }; 1468 1469 qupv3_id_1: geniqup@ac0000 { 1470 compatible = "qcom,geni-se-qup"; 1471 reg = <0 0x00ac0000 0 0x2000>; 1472 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1473 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1474 clock-names = "m-ahb", "s-ahb"; 1475 #address-cells = <2>; 1476 #size-cells = <2>; 1477 ranges; 1478 iommus = <&apps_smmu 0x43 0x0>; 1479 status = "disabled"; 1480 1481 i2c8: i2c@a80000 { 1482 compatible = "qcom,geni-i2c"; 1483 reg = <0 0x00a80000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1485 clock-names = "se"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_i2c8_data_clk>; 1488 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1492 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1493 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1494 interconnect-names = "qup-core", "qup-config", 1495 "qup-memory"; 1496 power-domains = <&rpmhpd SC7280_CX>; 1497 required-opps = <&rpmhpd_opp_low_svs>; 1498 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1499 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1500 dma-names = "tx", "rx"; 1501 status = "disabled"; 1502 }; 1503 1504 spi8: spi@a80000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0 0x00a80000 0 0x4000>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1508 clock-names = "se"; 1509 pinctrl-names = "default"; 1510 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1511 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 power-domains = <&rpmhpd SC7280_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1518 interconnect-names = "qup-core", "qup-config"; 1519 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1520 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1521 dma-names = "tx", "rx"; 1522 status = "disabled"; 1523 }; 1524 1525 uart8: serial@a80000 { 1526 compatible = "qcom,geni-uart"; 1527 reg = <0 0x00a80000 0 0x4000>; 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1529 clock-names = "se"; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1532 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1533 power-domains = <&rpmhpd SC7280_CX>; 1534 operating-points-v2 = <&qup_opp_table>; 1535 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1536 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1537 interconnect-names = "qup-core", "qup-config"; 1538 status = "disabled"; 1539 }; 1540 1541 i2c9: i2c@a84000 { 1542 compatible = "qcom,geni-i2c"; 1543 reg = <0 0x00a84000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_i2c9_data_clk>; 1548 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1552 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1553 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1554 interconnect-names = "qup-core", "qup-config", 1555 "qup-memory"; 1556 power-domains = <&rpmhpd SC7280_CX>; 1557 required-opps = <&rpmhpd_opp_low_svs>; 1558 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1559 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1560 dma-names = "tx", "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 spi9: spi@a84000 { 1565 compatible = "qcom,geni-spi"; 1566 reg = <0 0x00a84000 0 0x4000>; 1567 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1568 clock-names = "se"; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1571 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 power-domains = <&rpmhpd SC7280_CX>; 1575 operating-points-v2 = <&qup_opp_table>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1577 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1578 interconnect-names = "qup-core", "qup-config"; 1579 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1580 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1581 dma-names = "tx", "rx"; 1582 status = "disabled"; 1583 }; 1584 1585 uart9: serial@a84000 { 1586 compatible = "qcom,geni-uart"; 1587 reg = <0 0x00a84000 0 0x4000>; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1589 clock-names = "se"; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1592 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1593 power-domains = <&rpmhpd SC7280_CX>; 1594 operating-points-v2 = <&qup_opp_table>; 1595 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1596 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1597 interconnect-names = "qup-core", "qup-config"; 1598 status = "disabled"; 1599 }; 1600 1601 i2c10: i2c@a88000 { 1602 compatible = "qcom,geni-i2c"; 1603 reg = <0 0x00a88000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1605 clock-names = "se"; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_i2c10_data_clk>; 1608 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1612 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1613 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1614 interconnect-names = "qup-core", "qup-config", 1615 "qup-memory"; 1616 power-domains = <&rpmhpd SC7280_CX>; 1617 required-opps = <&rpmhpd_opp_low_svs>; 1618 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1619 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1620 dma-names = "tx", "rx"; 1621 status = "disabled"; 1622 }; 1623 1624 spi10: spi@a88000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a88000 0 0x4000>; 1627 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1628 clock-names = "se"; 1629 pinctrl-names = "default"; 1630 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1631 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 power-domains = <&rpmhpd SC7280_CX>; 1635 operating-points-v2 = <&qup_opp_table>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1638 interconnect-names = "qup-core", "qup-config"; 1639 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1640 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1641 dma-names = "tx", "rx"; 1642 status = "disabled"; 1643 }; 1644 1645 uart10: serial@a88000 { 1646 compatible = "qcom,geni-uart"; 1647 reg = <0 0x00a88000 0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1649 clock-names = "se"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1652 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1653 power-domains = <&rpmhpd SC7280_CX>; 1654 operating-points-v2 = <&qup_opp_table>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1657 interconnect-names = "qup-core", "qup-config"; 1658 status = "disabled"; 1659 }; 1660 1661 i2c11: i2c@a8c000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0 0x00a8c000 0 0x4000>; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1665 clock-names = "se"; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_i2c11_data_clk>; 1668 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", 1675 "qup-memory"; 1676 power-domains = <&rpmhpd SC7280_CX>; 1677 required-opps = <&rpmhpd_opp_low_svs>; 1678 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1679 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1680 dma-names = "tx", "rx"; 1681 status = "disabled"; 1682 }; 1683 1684 spi11: spi@a8c000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0 0x00a8c000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1691 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 power-domains = <&rpmhpd SC7280_CX>; 1695 operating-points-v2 = <&qup_opp_table>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1698 interconnect-names = "qup-core", "qup-config"; 1699 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1700 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 uart11: serial@a8c000 { 1706 compatible = "qcom,geni-uart"; 1707 reg = <0 0x00a8c000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1713 power-domains = <&rpmhpd SC7280_CX>; 1714 operating-points-v2 = <&qup_opp_table>; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1716 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1717 interconnect-names = "qup-core", "qup-config"; 1718 status = "disabled"; 1719 }; 1720 1721 i2c12: i2c@a90000 { 1722 compatible = "qcom,geni-i2c"; 1723 reg = <0 0x00a90000 0 0x4000>; 1724 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1725 clock-names = "se"; 1726 pinctrl-names = "default"; 1727 pinctrl-0 = <&qup_i2c12_data_clk>; 1728 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1732 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1733 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1734 interconnect-names = "qup-core", "qup-config", 1735 "qup-memory"; 1736 power-domains = <&rpmhpd SC7280_CX>; 1737 required-opps = <&rpmhpd_opp_low_svs>; 1738 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1739 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1740 dma-names = "tx", "rx"; 1741 status = "disabled"; 1742 }; 1743 1744 spi12: spi@a90000 { 1745 compatible = "qcom,geni-spi"; 1746 reg = <0 0x00a90000 0 0x4000>; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1748 clock-names = "se"; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1751 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 power-domains = <&rpmhpd SC7280_CX>; 1755 operating-points-v2 = <&qup_opp_table>; 1756 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1758 interconnect-names = "qup-core", "qup-config"; 1759 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1760 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 uart12: serial@a90000 { 1766 compatible = "qcom,geni-uart"; 1767 reg = <0 0x00a90000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 status = "disabled"; 1779 }; 1780 1781 i2c13: i2c@a94000 { 1782 compatible = "qcom,geni-i2c"; 1783 reg = <0 0x00a94000 0 0x4000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1785 clock-names = "se"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_i2c13_data_clk>; 1788 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1792 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1793 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1794 interconnect-names = "qup-core", "qup-config", 1795 "qup-memory"; 1796 power-domains = <&rpmhpd SC7280_CX>; 1797 required-opps = <&rpmhpd_opp_low_svs>; 1798 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1800 dma-names = "tx", "rx"; 1801 status = "disabled"; 1802 }; 1803 1804 spi13: spi@a94000 { 1805 compatible = "qcom,geni-spi"; 1806 reg = <0 0x00a94000 0 0x4000>; 1807 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1808 clock-names = "se"; 1809 pinctrl-names = "default"; 1810 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1811 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 power-domains = <&rpmhpd SC7280_CX>; 1815 operating-points-v2 = <&qup_opp_table>; 1816 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1818 interconnect-names = "qup-core", "qup-config"; 1819 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1820 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1821 dma-names = "tx", "rx"; 1822 status = "disabled"; 1823 }; 1824 1825 uart13: serial@a94000 { 1826 compatible = "qcom,geni-uart"; 1827 reg = <0 0x00a94000 0 0x4000>; 1828 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1829 clock-names = "se"; 1830 pinctrl-names = "default"; 1831 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1832 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 operating-points-v2 = <&qup_opp_table>; 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1837 interconnect-names = "qup-core", "qup-config"; 1838 status = "disabled"; 1839 }; 1840 1841 i2c14: i2c@a98000 { 1842 compatible = "qcom,geni-i2c"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1845 clock-names = "se"; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_i2c14_data_clk>; 1848 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1852 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1853 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1854 interconnect-names = "qup-core", "qup-config", 1855 "qup-memory"; 1856 power-domains = <&rpmhpd SC7280_CX>; 1857 required-opps = <&rpmhpd_opp_low_svs>; 1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1859 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1860 dma-names = "tx", "rx"; 1861 status = "disabled"; 1862 }; 1863 1864 spi14: spi@a98000 { 1865 compatible = "qcom,geni-spi"; 1866 reg = <0 0x00a98000 0 0x4000>; 1867 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1868 clock-names = "se"; 1869 pinctrl-names = "default"; 1870 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1871 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 power-domains = <&rpmhpd SC7280_CX>; 1875 operating-points-v2 = <&qup_opp_table>; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1878 interconnect-names = "qup-core", "qup-config"; 1879 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1880 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1881 dma-names = "tx", "rx"; 1882 status = "disabled"; 1883 }; 1884 1885 uart14: serial@a98000 { 1886 compatible = "qcom,geni-uart"; 1887 reg = <0 0x00a98000 0 0x4000>; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1889 clock-names = "se"; 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1892 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1893 power-domains = <&rpmhpd SC7280_CX>; 1894 operating-points-v2 = <&qup_opp_table>; 1895 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1896 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1897 interconnect-names = "qup-core", "qup-config"; 1898 status = "disabled"; 1899 }; 1900 1901 i2c15: i2c@a9c000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0 0x00a9c000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_i2c15_data_clk>; 1908 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1909 #address-cells = <1>; 1910 #size-cells = <0>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1913 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1914 interconnect-names = "qup-core", "qup-config", 1915 "qup-memory"; 1916 power-domains = <&rpmhpd SC7280_CX>; 1917 required-opps = <&rpmhpd_opp_low_svs>; 1918 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1919 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1920 dma-names = "tx", "rx"; 1921 status = "disabled"; 1922 }; 1923 1924 spi15: spi@a9c000 { 1925 compatible = "qcom,geni-spi"; 1926 reg = <0 0x00a9c000 0 0x4000>; 1927 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1928 clock-names = "se"; 1929 pinctrl-names = "default"; 1930 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1931 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1932 #address-cells = <1>; 1933 #size-cells = <0>; 1934 power-domains = <&rpmhpd SC7280_CX>; 1935 operating-points-v2 = <&qup_opp_table>; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1938 interconnect-names = "qup-core", "qup-config"; 1939 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1940 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1941 dma-names = "tx", "rx"; 1942 status = "disabled"; 1943 }; 1944 1945 uart15: serial@a9c000 { 1946 compatible = "qcom,geni-uart"; 1947 reg = <0 0x00a9c000 0 0x4000>; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1949 clock-names = "se"; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1952 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1953 power-domains = <&rpmhpd SC7280_CX>; 1954 operating-points-v2 = <&qup_opp_table>; 1955 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1956 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1957 interconnect-names = "qup-core", "qup-config"; 1958 status = "disabled"; 1959 }; 1960 }; 1961 1962 cnoc2: interconnect@1500000 { 1963 reg = <0 0x01500000 0 0x1000>; 1964 compatible = "qcom,sc7280-cnoc2"; 1965 #interconnect-cells = <2>; 1966 qcom,bcm-voters = <&apps_bcm_voter>; 1967 }; 1968 1969 cnoc3: interconnect@1502000 { 1970 reg = <0 0x01502000 0 0x1000>; 1971 compatible = "qcom,sc7280-cnoc3"; 1972 #interconnect-cells = <2>; 1973 qcom,bcm-voters = <&apps_bcm_voter>; 1974 }; 1975 1976 mc_virt: interconnect@1580000 { 1977 reg = <0 0x01580000 0 0x4>; 1978 compatible = "qcom,sc7280-mc-virt"; 1979 #interconnect-cells = <2>; 1980 qcom,bcm-voters = <&apps_bcm_voter>; 1981 }; 1982 1983 system_noc: interconnect@1680000 { 1984 reg = <0 0x01680000 0 0x15480>; 1985 compatible = "qcom,sc7280-system-noc"; 1986 #interconnect-cells = <2>; 1987 qcom,bcm-voters = <&apps_bcm_voter>; 1988 }; 1989 1990 aggre1_noc: interconnect@16e0000 { 1991 compatible = "qcom,sc7280-aggre1-noc"; 1992 reg = <0 0x016e0000 0 0x1c080>; 1993 #interconnect-cells = <2>; 1994 qcom,bcm-voters = <&apps_bcm_voter>; 1995 }; 1996 1997 aggre2_noc: interconnect@1700000 { 1998 reg = <0 0x01700000 0 0x2b080>; 1999 compatible = "qcom,sc7280-aggre2-noc"; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 }; 2003 2004 mmss_noc: interconnect@1740000 { 2005 reg = <0 0x01740000 0 0x1e080>; 2006 compatible = "qcom,sc7280-mmss-noc"; 2007 #interconnect-cells = <2>; 2008 qcom,bcm-voters = <&apps_bcm_voter>; 2009 }; 2010 2011 wifi: wifi@17a10040 { 2012 compatible = "qcom,wcn6750-wifi"; 2013 reg = <0 0x17a10040 0 0x0>; 2014 iommus = <&apps_smmu 0x1c00 0x1>; 2015 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2016 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2017 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2018 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2019 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2020 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2021 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2022 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2023 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2024 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2025 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2026 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2027 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2028 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2029 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2030 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2031 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2047 qcom,rproc = <&remoteproc_wpss>; 2048 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2049 status = "disabled"; 2050 qcom,smem-states = <&wlan_smp2p_out 0>; 2051 qcom,smem-state-names = "wlan-smp2p-out"; 2052 }; 2053 2054 pcie1: pci@1c08000 { 2055 compatible = "qcom,pcie-sc7280"; 2056 reg = <0 0x01c08000 0 0x3000>, 2057 <0 0x40000000 0 0xf1d>, 2058 <0 0x40000f20 0 0xa8>, 2059 <0 0x40001000 0 0x1000>, 2060 <0 0x40100000 0 0x100000>; 2061 2062 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2063 device_type = "pci"; 2064 linux,pci-domain = <1>; 2065 bus-range = <0x00 0xff>; 2066 num-lanes = <2>; 2067 2068 #address-cells = <3>; 2069 #size-cells = <2>; 2070 2071 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2072 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2073 2074 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2075 interrupt-names = "msi"; 2076 #interrupt-cells = <1>; 2077 interrupt-map-mask = <0 0 0 0x7>; 2078 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2079 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2080 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2081 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2082 2083 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2084 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2085 <&pcie1_lane>, 2086 <&rpmhcc RPMH_CXO_CLK>, 2087 <&gcc GCC_PCIE_1_AUX_CLK>, 2088 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2089 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2090 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2091 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2092 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2093 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2094 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2095 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2096 2097 clock-names = "pipe", 2098 "pipe_mux", 2099 "phy_pipe", 2100 "ref", 2101 "aux", 2102 "cfg", 2103 "bus_master", 2104 "bus_slave", 2105 "slave_q2a", 2106 "tbu", 2107 "ddrss_sf_tbu", 2108 "aggre0", 2109 "aggre1"; 2110 2111 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2112 assigned-clock-rates = <19200000>; 2113 2114 resets = <&gcc GCC_PCIE_1_BCR>; 2115 reset-names = "pci"; 2116 2117 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2118 2119 phys = <&pcie1_lane>; 2120 phy-names = "pciephy"; 2121 2122 pinctrl-names = "default"; 2123 pinctrl-0 = <&pcie1_clkreq_n>; 2124 2125 iommus = <&apps_smmu 0x1c80 0x1>; 2126 2127 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2128 <0x100 &apps_smmu 0x1c81 0x1>; 2129 2130 status = "disabled"; 2131 }; 2132 2133 pcie1_phy: phy@1c0e000 { 2134 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2135 reg = <0 0x01c0e000 0 0x1c0>; 2136 #address-cells = <2>; 2137 #size-cells = <2>; 2138 ranges; 2139 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2140 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2141 <&gcc GCC_PCIE_CLKREF_EN>, 2142 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2143 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2144 2145 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2146 reset-names = "phy"; 2147 2148 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2149 assigned-clock-rates = <100000000>; 2150 2151 status = "disabled"; 2152 2153 pcie1_lane: phy@1c0e200 { 2154 reg = <0 0x01c0e200 0 0x170>, 2155 <0 0x01c0e400 0 0x200>, 2156 <0 0x01c0ea00 0 0x1f0>, 2157 <0 0x01c0e600 0 0x170>, 2158 <0 0x01c0e800 0 0x200>, 2159 <0 0x01c0ee00 0 0xf4>; 2160 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2161 clock-names = "pipe0"; 2162 2163 #phy-cells = <0>; 2164 #clock-cells = <0>; 2165 clock-output-names = "pcie_1_pipe_clk"; 2166 }; 2167 }; 2168 2169 ipa: ipa@1e40000 { 2170 compatible = "qcom,sc7280-ipa"; 2171 2172 iommus = <&apps_smmu 0x480 0x0>, 2173 <&apps_smmu 0x482 0x0>; 2174 reg = <0 0x1e40000 0 0x8000>, 2175 <0 0x1e50000 0 0x4ad0>, 2176 <0 0x1e04000 0 0x23000>; 2177 reg-names = "ipa-reg", 2178 "ipa-shared", 2179 "gsi"; 2180 2181 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2182 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2183 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2184 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2185 interrupt-names = "ipa", 2186 "gsi", 2187 "ipa-clock-query", 2188 "ipa-setup-ready"; 2189 2190 clocks = <&rpmhcc RPMH_IPA_CLK>; 2191 clock-names = "core"; 2192 2193 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2195 interconnect-names = "memory", 2196 "config"; 2197 2198 qcom,qmp = <&aoss_qmp>; 2199 2200 qcom,smem-states = <&ipa_smp2p_out 0>, 2201 <&ipa_smp2p_out 1>; 2202 qcom,smem-state-names = "ipa-clock-enabled-valid", 2203 "ipa-clock-enabled"; 2204 2205 status = "disabled"; 2206 }; 2207 2208 tcsr_mutex: hwlock@1f40000 { 2209 compatible = "qcom,tcsr-mutex"; 2210 reg = <0 0x01f40000 0 0x20000>; 2211 #hwlock-cells = <1>; 2212 }; 2213 2214 tcsr_1: syscon@1f60000 { 2215 compatible = "qcom,sc7280-tcsr", "syscon"; 2216 reg = <0 0x01f60000 0 0x20000>; 2217 }; 2218 2219 tcsr_2: syscon@1fc0000 { 2220 compatible = "qcom,sc7280-tcsr", "syscon"; 2221 reg = <0 0x01fc0000 0 0x30000>; 2222 }; 2223 2224 lpasscc: lpasscc@3000000 { 2225 compatible = "qcom,sc7280-lpasscc"; 2226 reg = <0 0x03000000 0 0x40>, 2227 <0 0x03c04000 0 0x4>; 2228 reg-names = "qdsp6ss", "top_cc"; 2229 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2230 clock-names = "iface"; 2231 #clock-cells = <1>; 2232 }; 2233 2234 lpass_rx_macro: codec@3200000 { 2235 compatible = "qcom,sc7280-lpass-rx-macro"; 2236 reg = <0 0x03200000 0 0x1000>; 2237 2238 pinctrl-names = "default"; 2239 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2240 2241 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2242 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2243 <&lpass_va_macro>; 2244 clock-names = "mclk", "npl", "fsgen"; 2245 2246 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2247 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2248 power-domain-names = "macro", "dcodec"; 2249 2250 #clock-cells = <0>; 2251 #sound-dai-cells = <1>; 2252 2253 status = "disabled"; 2254 }; 2255 2256 swr0: soundwire@3210000 { 2257 compatible = "qcom,soundwire-v1.6.0"; 2258 reg = <0 0x03210000 0 0x2000>; 2259 2260 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2261 clocks = <&lpass_rx_macro>; 2262 clock-names = "iface"; 2263 2264 qcom,din-ports = <0>; 2265 qcom,dout-ports = <5>; 2266 2267 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2268 reset-names = "swr_audio_cgcr"; 2269 2270 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2271 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2272 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2273 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2274 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2275 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2276 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2277 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2279 2280 #sound-dai-cells = <1>; 2281 #address-cells = <2>; 2282 #size-cells = <0>; 2283 2284 status = "disabled"; 2285 }; 2286 2287 lpass_tx_macro: codec@3220000 { 2288 compatible = "qcom,sc7280-lpass-tx-macro"; 2289 reg = <0 0x03220000 0 0x1000>; 2290 2291 pinctrl-names = "default"; 2292 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2293 2294 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2295 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2296 <&lpass_va_macro>; 2297 clock-names = "mclk", "npl", "fsgen"; 2298 2299 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2300 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2301 power-domain-names = "macro", "dcodec"; 2302 2303 #clock-cells = <0>; 2304 #sound-dai-cells = <1>; 2305 2306 status = "disabled"; 2307 }; 2308 2309 swr1: soundwire@3230000 { 2310 compatible = "qcom,soundwire-v1.6.0"; 2311 reg = <0 0x03230000 0 0x2000>; 2312 2313 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2314 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2315 clocks = <&lpass_tx_macro>; 2316 clock-names = "iface"; 2317 2318 qcom,din-ports = <3>; 2319 qcom,dout-ports = <0>; 2320 2321 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2322 reset-names = "swr_audio_cgcr"; 2323 2324 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2325 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2326 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2327 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2328 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2329 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2330 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2331 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2332 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2333 2334 #sound-dai-cells = <1>; 2335 #address-cells = <2>; 2336 #size-cells = <0>; 2337 2338 status = "disabled"; 2339 }; 2340 2341 lpass_audiocc: clock-controller@3300000 { 2342 compatible = "qcom,sc7280-lpassaudiocc"; 2343 reg = <0 0x03300000 0 0x30000>, 2344 <0 0x032a9000 0 0x1000>; 2345 clocks = <&rpmhcc RPMH_CXO_CLK>, 2346 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2347 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2348 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2349 #clock-cells = <1>; 2350 #power-domain-cells = <1>; 2351 #reset-cells = <1>; 2352 }; 2353 2354 lpass_va_macro: codec@3370000 { 2355 compatible = "qcom,sc7280-lpass-va-macro"; 2356 reg = <0 0x03370000 0 0x1000>; 2357 2358 pinctrl-names = "default"; 2359 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2360 2361 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2362 clock-names = "mclk"; 2363 2364 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2365 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2366 power-domain-names = "macro", "dcodec"; 2367 2368 #clock-cells = <0>; 2369 #sound-dai-cells = <1>; 2370 2371 status = "disabled"; 2372 }; 2373 2374 lpass_aon: clock-controller@3380000 { 2375 compatible = "qcom,sc7280-lpassaoncc"; 2376 reg = <0 0x03380000 0 0x30000>; 2377 clocks = <&rpmhcc RPMH_CXO_CLK>, 2378 <&rpmhcc RPMH_CXO_CLK_A>, 2379 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2380 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2381 #clock-cells = <1>; 2382 #power-domain-cells = <1>; 2383 }; 2384 2385 lpass_core: clock-controller@3900000 { 2386 compatible = "qcom,sc7280-lpasscorecc"; 2387 reg = <0 0x03900000 0 0x50000>; 2388 clocks = <&rpmhcc RPMH_CXO_CLK>; 2389 clock-names = "bi_tcxo"; 2390 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2391 #clock-cells = <1>; 2392 #power-domain-cells = <1>; 2393 }; 2394 2395 lpass_cpu: audio@3987000 { 2396 compatible = "qcom,sc7280-lpass-cpu"; 2397 2398 reg = <0 0x03987000 0 0x68000>, 2399 <0 0x03b00000 0 0x29000>, 2400 <0 0x03260000 0 0xc000>, 2401 <0 0x03280000 0 0x29000>, 2402 <0 0x03340000 0 0x29000>, 2403 <0 0x0336c000 0 0x3000>; 2404 reg-names = "lpass-hdmiif", 2405 "lpass-lpaif", 2406 "lpass-rxtx-cdc-dma-lpm", 2407 "lpass-rxtx-lpaif", 2408 "lpass-va-lpaif", 2409 "lpass-va-cdc-dma-lpm"; 2410 2411 iommus = <&apps_smmu 0x1820 0>, 2412 <&apps_smmu 0x1821 0>, 2413 <&apps_smmu 0x1832 0>; 2414 2415 power-domains = <&rpmhpd SC7280_LCX>; 2416 power-domain-names = "lcx"; 2417 required-opps = <&rpmhpd_opp_nom>; 2418 2419 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2420 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2421 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2422 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2423 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2424 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2425 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2426 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2427 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2428 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2429 clock-names = "aon_cc_audio_hm_h", 2430 "audio_cc_ext_mclk0", 2431 "core_cc_sysnoc_mport_core", 2432 "core_cc_ext_if0_ibit", 2433 "core_cc_ext_if1_ibit", 2434 "audio_cc_codec_mem", 2435 "audio_cc_codec_mem0", 2436 "audio_cc_codec_mem1", 2437 "audio_cc_codec_mem2", 2438 "aon_cc_va_mem0"; 2439 2440 #sound-dai-cells = <1>; 2441 #address-cells = <1>; 2442 #size-cells = <0>; 2443 2444 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2448 interrupt-names = "lpass-irq-lpaif", 2449 "lpass-irq-hdmi", 2450 "lpass-irq-vaif", 2451 "lpass-irq-rxtxif"; 2452 2453 status = "disabled"; 2454 }; 2455 2456 lpass_hm: clock-controller@3c00000 { 2457 compatible = "qcom,sc7280-lpasshm"; 2458 reg = <0 0x3c00000 0 0x28>; 2459 clocks = <&rpmhcc RPMH_CXO_CLK>; 2460 clock-names = "bi_tcxo"; 2461 #clock-cells = <1>; 2462 #power-domain-cells = <1>; 2463 }; 2464 2465 lpass_ag_noc: interconnect@3c40000 { 2466 reg = <0 0x03c40000 0 0xf080>; 2467 compatible = "qcom,sc7280-lpass-ag-noc"; 2468 #interconnect-cells = <2>; 2469 qcom,bcm-voters = <&apps_bcm_voter>; 2470 }; 2471 2472 lpass_tlmm: pinctrl@33c0000 { 2473 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2474 reg = <0 0x033c0000 0x0 0x20000>, 2475 <0 0x03550000 0x0 0x10000>; 2476 qcom,adsp-bypass-mode; 2477 gpio-controller; 2478 #gpio-cells = <2>; 2479 gpio-ranges = <&lpass_tlmm 0 0 15>; 2480 2481 lpass_dmic01_clk: dmic01-clk-state { 2482 pins = "gpio6"; 2483 function = "dmic1_clk"; 2484 }; 2485 2486 lpass_dmic01_data: dmic01-data-state { 2487 pins = "gpio7"; 2488 function = "dmic1_data"; 2489 }; 2490 2491 lpass_dmic23_clk: dmic23-clk-state { 2492 pins = "gpio8"; 2493 function = "dmic2_clk"; 2494 }; 2495 2496 lpass_dmic23_data: dmic23-data-state { 2497 pins = "gpio9"; 2498 function = "dmic2_data"; 2499 }; 2500 2501 lpass_rx_swr_clk: rx-swr-clk-state { 2502 pins = "gpio3"; 2503 function = "swr_rx_clk"; 2504 }; 2505 2506 lpass_rx_swr_data: rx-swr-data-state { 2507 pins = "gpio4", "gpio5"; 2508 function = "swr_rx_data"; 2509 }; 2510 2511 lpass_tx_swr_clk: tx-swr-clk-state { 2512 pins = "gpio0"; 2513 function = "swr_tx_clk"; 2514 }; 2515 2516 lpass_tx_swr_data: tx-swr-data-state { 2517 pins = "gpio1", "gpio2", "gpio14"; 2518 function = "swr_tx_data"; 2519 }; 2520 }; 2521 2522 gpu: gpu@3d00000 { 2523 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2524 reg = <0 0x03d00000 0 0x40000>, 2525 <0 0x03d9e000 0 0x1000>, 2526 <0 0x03d61000 0 0x800>; 2527 reg-names = "kgsl_3d0_reg_memory", 2528 "cx_mem", 2529 "cx_dbgc"; 2530 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2531 iommus = <&adreno_smmu 0 0x401>; 2532 operating-points-v2 = <&gpu_opp_table>; 2533 qcom,gmu = <&gmu>; 2534 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2535 interconnect-names = "gfx-mem"; 2536 #cooling-cells = <2>; 2537 2538 nvmem-cells = <&gpu_speed_bin>; 2539 nvmem-cell-names = "speed_bin"; 2540 2541 gpu_opp_table: opp-table { 2542 compatible = "operating-points-v2"; 2543 2544 opp-315000000 { 2545 opp-hz = /bits/ 64 <315000000>; 2546 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2547 opp-peak-kBps = <1804000>; 2548 opp-supported-hw = <0x03>; 2549 }; 2550 2551 opp-450000000 { 2552 opp-hz = /bits/ 64 <450000000>; 2553 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2554 opp-peak-kBps = <4068000>; 2555 opp-supported-hw = <0x03>; 2556 }; 2557 2558 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2559 opp-550000000-0 { 2560 opp-hz = /bits/ 64 <550000000>; 2561 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2562 opp-peak-kBps = <8368000>; 2563 opp-supported-hw = <0x01>; 2564 }; 2565 2566 opp-550000000-1 { 2567 opp-hz = /bits/ 64 <550000000>; 2568 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2569 opp-peak-kBps = <6832000>; 2570 opp-supported-hw = <0x02>; 2571 }; 2572 2573 opp-608000000 { 2574 opp-hz = /bits/ 64 <608000000>; 2575 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2576 opp-peak-kBps = <8368000>; 2577 opp-supported-hw = <0x02>; 2578 }; 2579 2580 opp-700000000 { 2581 opp-hz = /bits/ 64 <700000000>; 2582 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2583 opp-peak-kBps = <8532000>; 2584 opp-supported-hw = <0x02>; 2585 }; 2586 2587 opp-812000000 { 2588 opp-hz = /bits/ 64 <812000000>; 2589 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2590 opp-peak-kBps = <8532000>; 2591 opp-supported-hw = <0x02>; 2592 }; 2593 2594 opp-840000000 { 2595 opp-hz = /bits/ 64 <840000000>; 2596 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2597 opp-peak-kBps = <8532000>; 2598 opp-supported-hw = <0x02>; 2599 }; 2600 2601 opp-900000000 { 2602 opp-hz = /bits/ 64 <900000000>; 2603 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2604 opp-peak-kBps = <8532000>; 2605 opp-supported-hw = <0x02>; 2606 }; 2607 }; 2608 }; 2609 2610 gmu: gmu@3d6a000 { 2611 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2612 reg = <0 0x03d6a000 0 0x34000>, 2613 <0 0x3de0000 0 0x10000>, 2614 <0 0x0b290000 0 0x10000>; 2615 reg-names = "gmu", "rscc", "gmu_pdc"; 2616 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2618 interrupt-names = "hfi", "gmu"; 2619 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2620 <&gpucc GPU_CC_CXO_CLK>, 2621 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2622 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2623 <&gpucc GPU_CC_AHB_CLK>, 2624 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2625 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2626 clock-names = "gmu", 2627 "cxo", 2628 "axi", 2629 "memnoc", 2630 "ahb", 2631 "hub", 2632 "smmu_vote"; 2633 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2634 <&gpucc GPU_CC_GX_GDSC>; 2635 power-domain-names = "cx", 2636 "gx"; 2637 iommus = <&adreno_smmu 5 0x400>; 2638 operating-points-v2 = <&gmu_opp_table>; 2639 2640 gmu_opp_table: opp-table { 2641 compatible = "operating-points-v2"; 2642 2643 opp-200000000 { 2644 opp-hz = /bits/ 64 <200000000>; 2645 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2646 }; 2647 }; 2648 }; 2649 2650 gpucc: clock-controller@3d90000 { 2651 compatible = "qcom,sc7280-gpucc"; 2652 reg = <0 0x03d90000 0 0x9000>; 2653 clocks = <&rpmhcc RPMH_CXO_CLK>, 2654 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2655 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2656 clock-names = "bi_tcxo", 2657 "gcc_gpu_gpll0_clk_src", 2658 "gcc_gpu_gpll0_div_clk_src"; 2659 #clock-cells = <1>; 2660 #reset-cells = <1>; 2661 #power-domain-cells = <1>; 2662 }; 2663 2664 adreno_smmu: iommu@3da0000 { 2665 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2666 reg = <0 0x03da0000 0 0x20000>; 2667 #iommu-cells = <2>; 2668 #global-interrupts = <2>; 2669 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2676 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2678 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2679 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2680 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2681 2682 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2683 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2684 <&gpucc GPU_CC_AHB_CLK>, 2685 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2686 <&gpucc GPU_CC_CX_GMU_CLK>, 2687 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2688 <&gpucc GPU_CC_HUB_AON_CLK>; 2689 clock-names = "gcc_gpu_memnoc_gfx_clk", 2690 "gcc_gpu_snoc_dvm_gfx_clk", 2691 "gpu_cc_ahb_clk", 2692 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2693 "gpu_cc_cx_gmu_clk", 2694 "gpu_cc_hub_cx_int_clk", 2695 "gpu_cc_hub_aon_clk"; 2696 2697 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2698 }; 2699 2700 remoteproc_mpss: remoteproc@4080000 { 2701 compatible = "qcom,sc7280-mpss-pas"; 2702 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2703 reg-names = "qdsp6", "rmb"; 2704 2705 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2706 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2707 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2708 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2709 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2710 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2711 interrupt-names = "wdog", "fatal", "ready", "handover", 2712 "stop-ack", "shutdown-ack"; 2713 2714 clocks = <&rpmhcc RPMH_CXO_CLK>; 2715 clock-names = "xo"; 2716 2717 power-domains = <&rpmhpd SC7280_CX>, 2718 <&rpmhpd SC7280_MSS>; 2719 power-domain-names = "cx", "mss"; 2720 2721 memory-region = <&mpss_mem>; 2722 2723 qcom,qmp = <&aoss_qmp>; 2724 2725 qcom,smem-states = <&modem_smp2p_out 0>; 2726 qcom,smem-state-names = "stop"; 2727 2728 status = "disabled"; 2729 2730 glink-edge { 2731 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2732 IPCC_MPROC_SIGNAL_GLINK_QMP 2733 IRQ_TYPE_EDGE_RISING>; 2734 mboxes = <&ipcc IPCC_CLIENT_MPSS 2735 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2736 label = "modem"; 2737 qcom,remote-pid = <1>; 2738 }; 2739 }; 2740 2741 stm@6002000 { 2742 compatible = "arm,coresight-stm", "arm,primecell"; 2743 reg = <0 0x06002000 0 0x1000>, 2744 <0 0x16280000 0 0x180000>; 2745 reg-names = "stm-base", "stm-stimulus-base"; 2746 2747 clocks = <&aoss_qmp>; 2748 clock-names = "apb_pclk"; 2749 2750 out-ports { 2751 port { 2752 stm_out: endpoint { 2753 remote-endpoint = <&funnel0_in7>; 2754 }; 2755 }; 2756 }; 2757 }; 2758 2759 funnel@6041000 { 2760 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2761 reg = <0 0x06041000 0 0x1000>; 2762 2763 clocks = <&aoss_qmp>; 2764 clock-names = "apb_pclk"; 2765 2766 out-ports { 2767 port { 2768 funnel0_out: endpoint { 2769 remote-endpoint = <&merge_funnel_in0>; 2770 }; 2771 }; 2772 }; 2773 2774 in-ports { 2775 #address-cells = <1>; 2776 #size-cells = <0>; 2777 2778 port@7 { 2779 reg = <7>; 2780 funnel0_in7: endpoint { 2781 remote-endpoint = <&stm_out>; 2782 }; 2783 }; 2784 }; 2785 }; 2786 2787 funnel@6042000 { 2788 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2789 reg = <0 0x06042000 0 0x1000>; 2790 2791 clocks = <&aoss_qmp>; 2792 clock-names = "apb_pclk"; 2793 2794 out-ports { 2795 port { 2796 funnel1_out: endpoint { 2797 remote-endpoint = <&merge_funnel_in1>; 2798 }; 2799 }; 2800 }; 2801 2802 in-ports { 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 2806 port@4 { 2807 reg = <4>; 2808 funnel1_in4: endpoint { 2809 remote-endpoint = <&apss_merge_funnel_out>; 2810 }; 2811 }; 2812 }; 2813 }; 2814 2815 funnel@6045000 { 2816 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2817 reg = <0 0x06045000 0 0x1000>; 2818 2819 clocks = <&aoss_qmp>; 2820 clock-names = "apb_pclk"; 2821 2822 out-ports { 2823 port { 2824 merge_funnel_out: endpoint { 2825 remote-endpoint = <&swao_funnel_in>; 2826 }; 2827 }; 2828 }; 2829 2830 in-ports { 2831 #address-cells = <1>; 2832 #size-cells = <0>; 2833 2834 port@0 { 2835 reg = <0>; 2836 merge_funnel_in0: endpoint { 2837 remote-endpoint = <&funnel0_out>; 2838 }; 2839 }; 2840 2841 port@1 { 2842 reg = <1>; 2843 merge_funnel_in1: endpoint { 2844 remote-endpoint = <&funnel1_out>; 2845 }; 2846 }; 2847 }; 2848 }; 2849 2850 replicator@6046000 { 2851 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2852 reg = <0 0x06046000 0 0x1000>; 2853 2854 clocks = <&aoss_qmp>; 2855 clock-names = "apb_pclk"; 2856 2857 out-ports { 2858 port { 2859 replicator_out: endpoint { 2860 remote-endpoint = <&etr_in>; 2861 }; 2862 }; 2863 }; 2864 2865 in-ports { 2866 port { 2867 replicator_in: endpoint { 2868 remote-endpoint = <&swao_replicator_out>; 2869 }; 2870 }; 2871 }; 2872 }; 2873 2874 etr@6048000 { 2875 compatible = "arm,coresight-tmc", "arm,primecell"; 2876 reg = <0 0x06048000 0 0x1000>; 2877 iommus = <&apps_smmu 0x04c0 0>; 2878 2879 clocks = <&aoss_qmp>; 2880 clock-names = "apb_pclk"; 2881 arm,scatter-gather; 2882 2883 in-ports { 2884 port { 2885 etr_in: endpoint { 2886 remote-endpoint = <&replicator_out>; 2887 }; 2888 }; 2889 }; 2890 }; 2891 2892 funnel@6b04000 { 2893 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2894 reg = <0 0x06b04000 0 0x1000>; 2895 2896 clocks = <&aoss_qmp>; 2897 clock-names = "apb_pclk"; 2898 2899 out-ports { 2900 port { 2901 swao_funnel_out: endpoint { 2902 remote-endpoint = <&etf_in>; 2903 }; 2904 }; 2905 }; 2906 2907 in-ports { 2908 #address-cells = <1>; 2909 #size-cells = <0>; 2910 2911 port@7 { 2912 reg = <7>; 2913 swao_funnel_in: endpoint { 2914 remote-endpoint = <&merge_funnel_out>; 2915 }; 2916 }; 2917 }; 2918 }; 2919 2920 etf@6b05000 { 2921 compatible = "arm,coresight-tmc", "arm,primecell"; 2922 reg = <0 0x06b05000 0 0x1000>; 2923 2924 clocks = <&aoss_qmp>; 2925 clock-names = "apb_pclk"; 2926 2927 out-ports { 2928 port { 2929 etf_out: endpoint { 2930 remote-endpoint = <&swao_replicator_in>; 2931 }; 2932 }; 2933 }; 2934 2935 in-ports { 2936 port { 2937 etf_in: endpoint { 2938 remote-endpoint = <&swao_funnel_out>; 2939 }; 2940 }; 2941 }; 2942 }; 2943 2944 replicator@6b06000 { 2945 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2946 reg = <0 0x06b06000 0 0x1000>; 2947 2948 clocks = <&aoss_qmp>; 2949 clock-names = "apb_pclk"; 2950 qcom,replicator-loses-context; 2951 2952 out-ports { 2953 port { 2954 swao_replicator_out: endpoint { 2955 remote-endpoint = <&replicator_in>; 2956 }; 2957 }; 2958 }; 2959 2960 in-ports { 2961 port { 2962 swao_replicator_in: endpoint { 2963 remote-endpoint = <&etf_out>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 etm@7040000 { 2970 compatible = "arm,coresight-etm4x", "arm,primecell"; 2971 reg = <0 0x07040000 0 0x1000>; 2972 2973 cpu = <&CPU0>; 2974 2975 clocks = <&aoss_qmp>; 2976 clock-names = "apb_pclk"; 2977 arm,coresight-loses-context-with-cpu; 2978 qcom,skip-power-up; 2979 2980 out-ports { 2981 port { 2982 etm0_out: endpoint { 2983 remote-endpoint = <&apss_funnel_in0>; 2984 }; 2985 }; 2986 }; 2987 }; 2988 2989 etm@7140000 { 2990 compatible = "arm,coresight-etm4x", "arm,primecell"; 2991 reg = <0 0x07140000 0 0x1000>; 2992 2993 cpu = <&CPU1>; 2994 2995 clocks = <&aoss_qmp>; 2996 clock-names = "apb_pclk"; 2997 arm,coresight-loses-context-with-cpu; 2998 qcom,skip-power-up; 2999 3000 out-ports { 3001 port { 3002 etm1_out: endpoint { 3003 remote-endpoint = <&apss_funnel_in1>; 3004 }; 3005 }; 3006 }; 3007 }; 3008 3009 etm@7240000 { 3010 compatible = "arm,coresight-etm4x", "arm,primecell"; 3011 reg = <0 0x07240000 0 0x1000>; 3012 3013 cpu = <&CPU2>; 3014 3015 clocks = <&aoss_qmp>; 3016 clock-names = "apb_pclk"; 3017 arm,coresight-loses-context-with-cpu; 3018 qcom,skip-power-up; 3019 3020 out-ports { 3021 port { 3022 etm2_out: endpoint { 3023 remote-endpoint = <&apss_funnel_in2>; 3024 }; 3025 }; 3026 }; 3027 }; 3028 3029 etm@7340000 { 3030 compatible = "arm,coresight-etm4x", "arm,primecell"; 3031 reg = <0 0x07340000 0 0x1000>; 3032 3033 cpu = <&CPU3>; 3034 3035 clocks = <&aoss_qmp>; 3036 clock-names = "apb_pclk"; 3037 arm,coresight-loses-context-with-cpu; 3038 qcom,skip-power-up; 3039 3040 out-ports { 3041 port { 3042 etm3_out: endpoint { 3043 remote-endpoint = <&apss_funnel_in3>; 3044 }; 3045 }; 3046 }; 3047 }; 3048 3049 etm@7440000 { 3050 compatible = "arm,coresight-etm4x", "arm,primecell"; 3051 reg = <0 0x07440000 0 0x1000>; 3052 3053 cpu = <&CPU4>; 3054 3055 clocks = <&aoss_qmp>; 3056 clock-names = "apb_pclk"; 3057 arm,coresight-loses-context-with-cpu; 3058 qcom,skip-power-up; 3059 3060 out-ports { 3061 port { 3062 etm4_out: endpoint { 3063 remote-endpoint = <&apss_funnel_in4>; 3064 }; 3065 }; 3066 }; 3067 }; 3068 3069 etm@7540000 { 3070 compatible = "arm,coresight-etm4x", "arm,primecell"; 3071 reg = <0 0x07540000 0 0x1000>; 3072 3073 cpu = <&CPU5>; 3074 3075 clocks = <&aoss_qmp>; 3076 clock-names = "apb_pclk"; 3077 arm,coresight-loses-context-with-cpu; 3078 qcom,skip-power-up; 3079 3080 out-ports { 3081 port { 3082 etm5_out: endpoint { 3083 remote-endpoint = <&apss_funnel_in5>; 3084 }; 3085 }; 3086 }; 3087 }; 3088 3089 etm@7640000 { 3090 compatible = "arm,coresight-etm4x", "arm,primecell"; 3091 reg = <0 0x07640000 0 0x1000>; 3092 3093 cpu = <&CPU6>; 3094 3095 clocks = <&aoss_qmp>; 3096 clock-names = "apb_pclk"; 3097 arm,coresight-loses-context-with-cpu; 3098 qcom,skip-power-up; 3099 3100 out-ports { 3101 port { 3102 etm6_out: endpoint { 3103 remote-endpoint = <&apss_funnel_in6>; 3104 }; 3105 }; 3106 }; 3107 }; 3108 3109 etm@7740000 { 3110 compatible = "arm,coresight-etm4x", "arm,primecell"; 3111 reg = <0 0x07740000 0 0x1000>; 3112 3113 cpu = <&CPU7>; 3114 3115 clocks = <&aoss_qmp>; 3116 clock-names = "apb_pclk"; 3117 arm,coresight-loses-context-with-cpu; 3118 qcom,skip-power-up; 3119 3120 out-ports { 3121 port { 3122 etm7_out: endpoint { 3123 remote-endpoint = <&apss_funnel_in7>; 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 funnel@7800000 { /* APSS Funnel */ 3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3131 reg = <0 0x07800000 0 0x1000>; 3132 3133 clocks = <&aoss_qmp>; 3134 clock-names = "apb_pclk"; 3135 3136 out-ports { 3137 port { 3138 apss_funnel_out: endpoint { 3139 remote-endpoint = <&apss_merge_funnel_in>; 3140 }; 3141 }; 3142 }; 3143 3144 in-ports { 3145 #address-cells = <1>; 3146 #size-cells = <0>; 3147 3148 port@0 { 3149 reg = <0>; 3150 apss_funnel_in0: endpoint { 3151 remote-endpoint = <&etm0_out>; 3152 }; 3153 }; 3154 3155 port@1 { 3156 reg = <1>; 3157 apss_funnel_in1: endpoint { 3158 remote-endpoint = <&etm1_out>; 3159 }; 3160 }; 3161 3162 port@2 { 3163 reg = <2>; 3164 apss_funnel_in2: endpoint { 3165 remote-endpoint = <&etm2_out>; 3166 }; 3167 }; 3168 3169 port@3 { 3170 reg = <3>; 3171 apss_funnel_in3: endpoint { 3172 remote-endpoint = <&etm3_out>; 3173 }; 3174 }; 3175 3176 port@4 { 3177 reg = <4>; 3178 apss_funnel_in4: endpoint { 3179 remote-endpoint = <&etm4_out>; 3180 }; 3181 }; 3182 3183 port@5 { 3184 reg = <5>; 3185 apss_funnel_in5: endpoint { 3186 remote-endpoint = <&etm5_out>; 3187 }; 3188 }; 3189 3190 port@6 { 3191 reg = <6>; 3192 apss_funnel_in6: endpoint { 3193 remote-endpoint = <&etm6_out>; 3194 }; 3195 }; 3196 3197 port@7 { 3198 reg = <7>; 3199 apss_funnel_in7: endpoint { 3200 remote-endpoint = <&etm7_out>; 3201 }; 3202 }; 3203 }; 3204 }; 3205 3206 funnel@7810000 { 3207 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3208 reg = <0 0x07810000 0 0x1000>; 3209 3210 clocks = <&aoss_qmp>; 3211 clock-names = "apb_pclk"; 3212 3213 out-ports { 3214 port { 3215 apss_merge_funnel_out: endpoint { 3216 remote-endpoint = <&funnel1_in4>; 3217 }; 3218 }; 3219 }; 3220 3221 in-ports { 3222 port { 3223 apss_merge_funnel_in: endpoint { 3224 remote-endpoint = <&apss_funnel_out>; 3225 }; 3226 }; 3227 }; 3228 }; 3229 3230 sdhc_2: mmc@8804000 { 3231 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3232 pinctrl-names = "default", "sleep"; 3233 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3234 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3235 status = "disabled"; 3236 3237 reg = <0 0x08804000 0 0x1000>; 3238 3239 iommus = <&apps_smmu 0x100 0x0>; 3240 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3242 interrupt-names = "hc_irq", "pwr_irq"; 3243 3244 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3245 <&gcc GCC_SDCC2_APPS_CLK>, 3246 <&rpmhcc RPMH_CXO_CLK>; 3247 clock-names = "iface", "core", "xo"; 3248 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3249 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3250 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3251 power-domains = <&rpmhpd SC7280_CX>; 3252 operating-points-v2 = <&sdhc2_opp_table>; 3253 3254 bus-width = <4>; 3255 3256 qcom,dll-config = <0x0007642c>; 3257 3258 resets = <&gcc GCC_SDCC2_BCR>; 3259 3260 sdhc2_opp_table: opp-table { 3261 compatible = "operating-points-v2"; 3262 3263 opp-100000000 { 3264 opp-hz = /bits/ 64 <100000000>; 3265 required-opps = <&rpmhpd_opp_low_svs>; 3266 opp-peak-kBps = <1800000 400000>; 3267 opp-avg-kBps = <100000 0>; 3268 }; 3269 3270 opp-202000000 { 3271 opp-hz = /bits/ 64 <202000000>; 3272 required-opps = <&rpmhpd_opp_nom>; 3273 opp-peak-kBps = <5400000 1600000>; 3274 opp-avg-kBps = <200000 0>; 3275 }; 3276 }; 3277 3278 }; 3279 3280 usb_1_hsphy: phy@88e3000 { 3281 compatible = "qcom,sc7280-usb-hs-phy", 3282 "qcom,usb-snps-hs-7nm-phy"; 3283 reg = <0 0x088e3000 0 0x400>; 3284 status = "disabled"; 3285 #phy-cells = <0>; 3286 3287 clocks = <&rpmhcc RPMH_CXO_CLK>; 3288 clock-names = "ref"; 3289 3290 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3291 }; 3292 3293 usb_2_hsphy: phy@88e4000 { 3294 compatible = "qcom,sc7280-usb-hs-phy", 3295 "qcom,usb-snps-hs-7nm-phy"; 3296 reg = <0 0x088e4000 0 0x400>; 3297 status = "disabled"; 3298 #phy-cells = <0>; 3299 3300 clocks = <&rpmhcc RPMH_CXO_CLK>; 3301 clock-names = "ref"; 3302 3303 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3304 }; 3305 3306 usb_1_qmpphy: phy-wrapper@88e9000 { 3307 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3308 "qcom,sm8250-qmp-usb3-dp-phy"; 3309 reg = <0 0x088e9000 0 0x200>, 3310 <0 0x088e8000 0 0x40>, 3311 <0 0x088ea000 0 0x200>; 3312 status = "disabled"; 3313 #address-cells = <2>; 3314 #size-cells = <2>; 3315 ranges; 3316 3317 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3318 <&rpmhcc RPMH_CXO_CLK>, 3319 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3320 clock-names = "aux", "ref_clk_src", "com_aux"; 3321 3322 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3323 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3324 reset-names = "phy", "common"; 3325 3326 usb_1_ssphy: usb3-phy@88e9200 { 3327 reg = <0 0x088e9200 0 0x200>, 3328 <0 0x088e9400 0 0x200>, 3329 <0 0x088e9c00 0 0x400>, 3330 <0 0x088e9600 0 0x200>, 3331 <0 0x088e9800 0 0x200>, 3332 <0 0x088e9a00 0 0x100>; 3333 #clock-cells = <0>; 3334 #phy-cells = <0>; 3335 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3336 clock-names = "pipe0"; 3337 clock-output-names = "usb3_phy_pipe_clk_src"; 3338 }; 3339 3340 dp_phy: dp-phy@88ea200 { 3341 reg = <0 0x088ea200 0 0x200>, 3342 <0 0x088ea400 0 0x200>, 3343 <0 0x088eaa00 0 0x200>, 3344 <0 0x088ea600 0 0x200>, 3345 <0 0x088ea800 0 0x200>; 3346 #phy-cells = <0>; 3347 #clock-cells = <1>; 3348 }; 3349 }; 3350 3351 usb_2: usb@8cf8800 { 3352 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3353 reg = <0 0x08cf8800 0 0x400>; 3354 status = "disabled"; 3355 #address-cells = <2>; 3356 #size-cells = <2>; 3357 ranges; 3358 dma-ranges; 3359 3360 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3361 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3362 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3363 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3364 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3365 clock-names = "cfg_noc", 3366 "core", 3367 "iface", 3368 "sleep", 3369 "mock_utmi"; 3370 3371 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3372 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3373 assigned-clock-rates = <19200000>, <200000000>; 3374 3375 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3376 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3377 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3378 interrupt-names = "hs_phy_irq", 3379 "dp_hs_phy_irq", 3380 "dm_hs_phy_irq"; 3381 3382 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3383 required-opps = <&rpmhpd_opp_nom>; 3384 3385 resets = <&gcc GCC_USB30_SEC_BCR>; 3386 3387 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3388 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3389 interconnect-names = "usb-ddr", "apps-usb"; 3390 3391 usb_2_dwc3: usb@8c00000 { 3392 compatible = "snps,dwc3"; 3393 reg = <0 0x08c00000 0 0xe000>; 3394 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3395 iommus = <&apps_smmu 0xa0 0x0>; 3396 snps,dis_u2_susphy_quirk; 3397 snps,dis_enblslpm_quirk; 3398 phys = <&usb_2_hsphy>; 3399 phy-names = "usb2-phy"; 3400 maximum-speed = "high-speed"; 3401 usb-role-switch; 3402 port { 3403 usb2_role_switch: endpoint { 3404 remote-endpoint = <&eud_ep>; 3405 }; 3406 }; 3407 }; 3408 }; 3409 3410 qspi: spi@88dc000 { 3411 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3412 reg = <0 0x088dc000 0 0x1000>; 3413 #address-cells = <1>; 3414 #size-cells = <0>; 3415 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3416 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3417 <&gcc GCC_QSPI_CORE_CLK>; 3418 clock-names = "iface", "core"; 3419 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3420 &cnoc2 SLAVE_QSPI_0 0>; 3421 interconnect-names = "qspi-config"; 3422 power-domains = <&rpmhpd SC7280_CX>; 3423 operating-points-v2 = <&qspi_opp_table>; 3424 status = "disabled"; 3425 }; 3426 3427 remoteproc_wpss: remoteproc@8a00000 { 3428 compatible = "qcom,sc7280-wpss-pil"; 3429 reg = <0 0x08a00000 0 0x10000>; 3430 3431 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3432 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3433 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3434 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3435 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3436 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3437 interrupt-names = "wdog", "fatal", "ready", "handover", 3438 "stop-ack", "shutdown-ack"; 3439 3440 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3441 <&gcc GCC_WPSS_AHB_CLK>, 3442 <&gcc GCC_WPSS_RSCP_CLK>, 3443 <&rpmhcc RPMH_CXO_CLK>; 3444 clock-names = "ahb_bdg", "ahb", 3445 "rscp", "xo"; 3446 3447 power-domains = <&rpmhpd SC7280_CX>, 3448 <&rpmhpd SC7280_MX>; 3449 power-domain-names = "cx", "mx"; 3450 3451 memory-region = <&wpss_mem>; 3452 3453 qcom,qmp = <&aoss_qmp>; 3454 3455 qcom,smem-states = <&wpss_smp2p_out 0>; 3456 qcom,smem-state-names = "stop"; 3457 3458 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3459 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3460 reset-names = "restart", "pdc_sync"; 3461 3462 qcom,halt-regs = <&tcsr_1 0x17000>; 3463 3464 status = "disabled"; 3465 3466 glink-edge { 3467 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3468 IPCC_MPROC_SIGNAL_GLINK_QMP 3469 IRQ_TYPE_EDGE_RISING>; 3470 mboxes = <&ipcc IPCC_CLIENT_WPSS 3471 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3472 3473 label = "wpss"; 3474 qcom,remote-pid = <13>; 3475 }; 3476 }; 3477 3478 pmu@9091000 { 3479 compatible = "qcom,sc7280-llcc-bwmon"; 3480 reg = <0 0x9091000 0 0x1000>; 3481 3482 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3483 3484 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3485 3486 operating-points-v2 = <&llcc_bwmon_opp_table>; 3487 3488 llcc_bwmon_opp_table: opp-table { 3489 compatible = "operating-points-v2"; 3490 3491 opp-0 { 3492 opp-peak-kBps = <800000>; 3493 }; 3494 opp-1 { 3495 opp-peak-kBps = <1804000>; 3496 }; 3497 opp-2 { 3498 opp-peak-kBps = <2188000>; 3499 }; 3500 opp-3 { 3501 opp-peak-kBps = <3072000>; 3502 }; 3503 opp-4 { 3504 opp-peak-kBps = <4068000>; 3505 }; 3506 opp-5 { 3507 opp-peak-kBps = <6220000>; 3508 }; 3509 opp-6 { 3510 opp-peak-kBps = <6832000>; 3511 }; 3512 opp-7 { 3513 opp-peak-kBps = <8532000>; 3514 }; 3515 }; 3516 }; 3517 3518 pmu@90b6400 { 3519 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3520 reg = <0 0x090b6400 0 0x600>; 3521 3522 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3523 3524 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3525 operating-points-v2 = <&cpu_bwmon_opp_table>; 3526 3527 cpu_bwmon_opp_table: opp-table { 3528 compatible = "operating-points-v2"; 3529 3530 opp-0 { 3531 opp-peak-kBps = <2400000>; 3532 }; 3533 opp-1 { 3534 opp-peak-kBps = <4800000>; 3535 }; 3536 opp-2 { 3537 opp-peak-kBps = <7456000>; 3538 }; 3539 opp-3 { 3540 opp-peak-kBps = <9600000>; 3541 }; 3542 opp-4 { 3543 opp-peak-kBps = <12896000>; 3544 }; 3545 opp-5 { 3546 opp-peak-kBps = <14928000>; 3547 }; 3548 opp-6 { 3549 opp-peak-kBps = <17056000>; 3550 }; 3551 }; 3552 }; 3553 3554 dc_noc: interconnect@90e0000 { 3555 reg = <0 0x090e0000 0 0x5080>; 3556 compatible = "qcom,sc7280-dc-noc"; 3557 #interconnect-cells = <2>; 3558 qcom,bcm-voters = <&apps_bcm_voter>; 3559 }; 3560 3561 gem_noc: interconnect@9100000 { 3562 reg = <0 0x9100000 0 0xe2200>; 3563 compatible = "qcom,sc7280-gem-noc"; 3564 #interconnect-cells = <2>; 3565 qcom,bcm-voters = <&apps_bcm_voter>; 3566 }; 3567 3568 system-cache-controller@9200000 { 3569 compatible = "qcom,sc7280-llcc"; 3570 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3571 reg-names = "llcc_base", "llcc_broadcast_base"; 3572 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3573 }; 3574 3575 eud: eud@88e0000 { 3576 compatible = "qcom,sc7280-eud","qcom,eud"; 3577 reg = <0 0x88e0000 0 0x2000>, 3578 <0 0x88e2000 0 0x1000>; 3579 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3580 ports { 3581 port@0 { 3582 eud_ep: endpoint { 3583 remote-endpoint = <&usb2_role_switch>; 3584 }; 3585 }; 3586 port@1 { 3587 eud_con: endpoint { 3588 remote-endpoint = <&con_eud>; 3589 }; 3590 }; 3591 }; 3592 }; 3593 3594 eud_typec: connector { 3595 compatible = "usb-c-connector"; 3596 ports { 3597 port@0 { 3598 con_eud: endpoint { 3599 remote-endpoint = <&eud_con>; 3600 }; 3601 }; 3602 }; 3603 }; 3604 3605 nsp_noc: interconnect@a0c0000 { 3606 reg = <0 0x0a0c0000 0 0x10000>; 3607 compatible = "qcom,sc7280-nsp-noc"; 3608 #interconnect-cells = <2>; 3609 qcom,bcm-voters = <&apps_bcm_voter>; 3610 }; 3611 3612 usb_1: usb@a6f8800 { 3613 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3614 reg = <0 0x0a6f8800 0 0x400>; 3615 status = "disabled"; 3616 #address-cells = <2>; 3617 #size-cells = <2>; 3618 ranges; 3619 dma-ranges; 3620 3621 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3622 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3623 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3624 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3625 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3626 clock-names = "cfg_noc", 3627 "core", 3628 "iface", 3629 "sleep", 3630 "mock_utmi"; 3631 3632 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3633 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3634 assigned-clock-rates = <19200000>, <200000000>; 3635 3636 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3637 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3638 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3639 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3640 interrupt-names = "hs_phy_irq", 3641 "dp_hs_phy_irq", 3642 "dm_hs_phy_irq", 3643 "ss_phy_irq"; 3644 3645 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3646 required-opps = <&rpmhpd_opp_nom>; 3647 3648 resets = <&gcc GCC_USB30_PRIM_BCR>; 3649 3650 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3651 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3652 interconnect-names = "usb-ddr", "apps-usb"; 3653 3654 wakeup-source; 3655 3656 usb_1_dwc3: usb@a600000 { 3657 compatible = "snps,dwc3"; 3658 reg = <0 0x0a600000 0 0xe000>; 3659 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3660 iommus = <&apps_smmu 0xe0 0x0>; 3661 snps,dis_u2_susphy_quirk; 3662 snps,dis_enblslpm_quirk; 3663 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3664 phy-names = "usb2-phy", "usb3-phy"; 3665 maximum-speed = "super-speed"; 3666 }; 3667 }; 3668 3669 venus: video-codec@aa00000 { 3670 compatible = "qcom,sc7280-venus"; 3671 reg = <0 0x0aa00000 0 0xd0600>; 3672 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3673 3674 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3675 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3676 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3677 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3678 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3679 clock-names = "core", "bus", "iface", 3680 "vcodec_core", "vcodec_bus"; 3681 3682 power-domains = <&videocc MVSC_GDSC>, 3683 <&videocc MVS0_GDSC>, 3684 <&rpmhpd SC7280_CX>; 3685 power-domain-names = "venus", "vcodec0", "cx"; 3686 operating-points-v2 = <&venus_opp_table>; 3687 3688 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3689 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3690 interconnect-names = "cpu-cfg", "video-mem"; 3691 3692 iommus = <&apps_smmu 0x2180 0x20>, 3693 <&apps_smmu 0x2184 0x20>; 3694 memory-region = <&video_mem>; 3695 3696 video-decoder { 3697 compatible = "venus-decoder"; 3698 }; 3699 3700 video-encoder { 3701 compatible = "venus-encoder"; 3702 }; 3703 3704 video-firmware { 3705 iommus = <&apps_smmu 0x21a2 0x0>; 3706 }; 3707 3708 venus_opp_table: opp-table { 3709 compatible = "operating-points-v2"; 3710 3711 opp-133330000 { 3712 opp-hz = /bits/ 64 <133330000>; 3713 required-opps = <&rpmhpd_opp_low_svs>; 3714 }; 3715 3716 opp-240000000 { 3717 opp-hz = /bits/ 64 <240000000>; 3718 required-opps = <&rpmhpd_opp_svs>; 3719 }; 3720 3721 opp-335000000 { 3722 opp-hz = /bits/ 64 <335000000>; 3723 required-opps = <&rpmhpd_opp_svs_l1>; 3724 }; 3725 3726 opp-424000000 { 3727 opp-hz = /bits/ 64 <424000000>; 3728 required-opps = <&rpmhpd_opp_nom>; 3729 }; 3730 3731 opp-460000048 { 3732 opp-hz = /bits/ 64 <460000048>; 3733 required-opps = <&rpmhpd_opp_turbo>; 3734 }; 3735 }; 3736 3737 }; 3738 3739 videocc: clock-controller@aaf0000 { 3740 compatible = "qcom,sc7280-videocc"; 3741 reg = <0 0xaaf0000 0 0x10000>; 3742 clocks = <&rpmhcc RPMH_CXO_CLK>, 3743 <&rpmhcc RPMH_CXO_CLK_A>; 3744 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3745 #clock-cells = <1>; 3746 #reset-cells = <1>; 3747 #power-domain-cells = <1>; 3748 }; 3749 3750 camcc: clock-controller@ad00000 { 3751 compatible = "qcom,sc7280-camcc"; 3752 reg = <0 0x0ad00000 0 0x10000>; 3753 clocks = <&rpmhcc RPMH_CXO_CLK>, 3754 <&rpmhcc RPMH_CXO_CLK_A>, 3755 <&sleep_clk>; 3756 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3757 #clock-cells = <1>; 3758 #reset-cells = <1>; 3759 #power-domain-cells = <1>; 3760 }; 3761 3762 dispcc: clock-controller@af00000 { 3763 compatible = "qcom,sc7280-dispcc"; 3764 reg = <0 0xaf00000 0 0x20000>; 3765 clocks = <&rpmhcc RPMH_CXO_CLK>, 3766 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3767 <&mdss_dsi_phy 0>, 3768 <&mdss_dsi_phy 1>, 3769 <&dp_phy 0>, 3770 <&dp_phy 1>, 3771 <&mdss_edp_phy 0>, 3772 <&mdss_edp_phy 1>; 3773 clock-names = "bi_tcxo", 3774 "gcc_disp_gpll0_clk", 3775 "dsi0_phy_pll_out_byteclk", 3776 "dsi0_phy_pll_out_dsiclk", 3777 "dp_phy_pll_link_clk", 3778 "dp_phy_pll_vco_div_clk", 3779 "edp_phy_pll_link_clk", 3780 "edp_phy_pll_vco_div_clk"; 3781 #clock-cells = <1>; 3782 #reset-cells = <1>; 3783 #power-domain-cells = <1>; 3784 }; 3785 3786 mdss: display-subsystem@ae00000 { 3787 compatible = "qcom,sc7280-mdss"; 3788 reg = <0 0x0ae00000 0 0x1000>; 3789 reg-names = "mdss"; 3790 3791 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3792 3793 clocks = <&gcc GCC_DISP_AHB_CLK>, 3794 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3795 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3796 clock-names = "iface", 3797 "ahb", 3798 "core"; 3799 3800 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3801 interrupt-controller; 3802 #interrupt-cells = <1>; 3803 3804 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3805 interconnect-names = "mdp0-mem"; 3806 3807 iommus = <&apps_smmu 0x900 0x402>; 3808 3809 #address-cells = <2>; 3810 #size-cells = <2>; 3811 ranges; 3812 3813 status = "disabled"; 3814 3815 mdss_mdp: display-controller@ae01000 { 3816 compatible = "qcom,sc7280-dpu"; 3817 reg = <0 0x0ae01000 0 0x8f030>, 3818 <0 0x0aeb0000 0 0x2008>; 3819 reg-names = "mdp", "vbif"; 3820 3821 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3822 <&gcc GCC_DISP_SF_AXI_CLK>, 3823 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3824 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3825 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3826 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3827 clock-names = "bus", 3828 "nrt_bus", 3829 "iface", 3830 "lut", 3831 "core", 3832 "vsync"; 3833 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3834 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3835 assigned-clock-rates = <19200000>, 3836 <19200000>; 3837 operating-points-v2 = <&mdp_opp_table>; 3838 power-domains = <&rpmhpd SC7280_CX>; 3839 3840 interrupt-parent = <&mdss>; 3841 interrupts = <0>; 3842 3843 status = "disabled"; 3844 3845 ports { 3846 #address-cells = <1>; 3847 #size-cells = <0>; 3848 3849 port@0 { 3850 reg = <0>; 3851 dpu_intf1_out: endpoint { 3852 remote-endpoint = <&dsi0_in>; 3853 }; 3854 }; 3855 3856 port@1 { 3857 reg = <1>; 3858 dpu_intf5_out: endpoint { 3859 remote-endpoint = <&edp_in>; 3860 }; 3861 }; 3862 3863 port@2 { 3864 reg = <2>; 3865 dpu_intf0_out: endpoint { 3866 remote-endpoint = <&dp_in>; 3867 }; 3868 }; 3869 }; 3870 3871 mdp_opp_table: opp-table { 3872 compatible = "operating-points-v2"; 3873 3874 opp-200000000 { 3875 opp-hz = /bits/ 64 <200000000>; 3876 required-opps = <&rpmhpd_opp_low_svs>; 3877 }; 3878 3879 opp-300000000 { 3880 opp-hz = /bits/ 64 <300000000>; 3881 required-opps = <&rpmhpd_opp_svs>; 3882 }; 3883 3884 opp-380000000 { 3885 opp-hz = /bits/ 64 <380000000>; 3886 required-opps = <&rpmhpd_opp_svs_l1>; 3887 }; 3888 3889 opp-506666667 { 3890 opp-hz = /bits/ 64 <506666667>; 3891 required-opps = <&rpmhpd_opp_nom>; 3892 }; 3893 }; 3894 }; 3895 3896 mdss_dsi: dsi@ae94000 { 3897 compatible = "qcom,mdss-dsi-ctrl"; 3898 reg = <0 0x0ae94000 0 0x400>; 3899 reg-names = "dsi_ctrl"; 3900 3901 interrupt-parent = <&mdss>; 3902 interrupts = <4>; 3903 3904 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3905 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3906 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3907 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3908 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3909 <&gcc GCC_DISP_HF_AXI_CLK>; 3910 clock-names = "byte", 3911 "byte_intf", 3912 "pixel", 3913 "core", 3914 "iface", 3915 "bus"; 3916 3917 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3918 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3919 3920 operating-points-v2 = <&dsi_opp_table>; 3921 power-domains = <&rpmhpd SC7280_CX>; 3922 3923 phys = <&mdss_dsi_phy>; 3924 3925 #address-cells = <1>; 3926 #size-cells = <0>; 3927 3928 status = "disabled"; 3929 3930 ports { 3931 #address-cells = <1>; 3932 #size-cells = <0>; 3933 3934 port@0 { 3935 reg = <0>; 3936 dsi0_in: endpoint { 3937 remote-endpoint = <&dpu_intf1_out>; 3938 }; 3939 }; 3940 3941 port@1 { 3942 reg = <1>; 3943 dsi0_out: endpoint { 3944 }; 3945 }; 3946 }; 3947 3948 dsi_opp_table: opp-table { 3949 compatible = "operating-points-v2"; 3950 3951 opp-187500000 { 3952 opp-hz = /bits/ 64 <187500000>; 3953 required-opps = <&rpmhpd_opp_low_svs>; 3954 }; 3955 3956 opp-300000000 { 3957 opp-hz = /bits/ 64 <300000000>; 3958 required-opps = <&rpmhpd_opp_svs>; 3959 }; 3960 3961 opp-358000000 { 3962 opp-hz = /bits/ 64 <358000000>; 3963 required-opps = <&rpmhpd_opp_svs_l1>; 3964 }; 3965 }; 3966 }; 3967 3968 mdss_dsi_phy: phy@ae94400 { 3969 compatible = "qcom,sc7280-dsi-phy-7nm"; 3970 reg = <0 0x0ae94400 0 0x200>, 3971 <0 0x0ae94600 0 0x280>, 3972 <0 0x0ae94900 0 0x280>; 3973 reg-names = "dsi_phy", 3974 "dsi_phy_lane", 3975 "dsi_pll"; 3976 3977 #clock-cells = <1>; 3978 #phy-cells = <0>; 3979 3980 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3981 <&rpmhcc RPMH_CXO_CLK>; 3982 clock-names = "iface", "ref"; 3983 3984 status = "disabled"; 3985 }; 3986 3987 mdss_edp: edp@aea0000 { 3988 compatible = "qcom,sc7280-edp"; 3989 pinctrl-names = "default"; 3990 pinctrl-0 = <&edp_hot_plug_det>; 3991 3992 reg = <0 0xaea0000 0 0x200>, 3993 <0 0xaea0200 0 0x200>, 3994 <0 0xaea0400 0 0xc00>, 3995 <0 0xaea1000 0 0x400>; 3996 3997 interrupt-parent = <&mdss>; 3998 interrupts = <14>; 3999 4000 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4001 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4002 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4003 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4004 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4005 clock-names = "core_iface", 4006 "core_aux", 4007 "ctrl_link", 4008 "ctrl_link_iface", 4009 "stream_pixel"; 4010 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4011 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4012 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4013 4014 phys = <&mdss_edp_phy>; 4015 phy-names = "dp"; 4016 4017 operating-points-v2 = <&edp_opp_table>; 4018 power-domains = <&rpmhpd SC7280_CX>; 4019 4020 status = "disabled"; 4021 4022 ports { 4023 #address-cells = <1>; 4024 #size-cells = <0>; 4025 4026 port@0 { 4027 reg = <0>; 4028 edp_in: endpoint { 4029 remote-endpoint = <&dpu_intf5_out>; 4030 }; 4031 }; 4032 4033 port@1 { 4034 reg = <1>; 4035 mdss_edp_out: endpoint { }; 4036 }; 4037 }; 4038 4039 edp_opp_table: opp-table { 4040 compatible = "operating-points-v2"; 4041 4042 opp-160000000 { 4043 opp-hz = /bits/ 64 <160000000>; 4044 required-opps = <&rpmhpd_opp_low_svs>; 4045 }; 4046 4047 opp-270000000 { 4048 opp-hz = /bits/ 64 <270000000>; 4049 required-opps = <&rpmhpd_opp_svs>; 4050 }; 4051 4052 opp-540000000 { 4053 opp-hz = /bits/ 64 <540000000>; 4054 required-opps = <&rpmhpd_opp_nom>; 4055 }; 4056 4057 opp-810000000 { 4058 opp-hz = /bits/ 64 <810000000>; 4059 required-opps = <&rpmhpd_opp_nom>; 4060 }; 4061 }; 4062 }; 4063 4064 mdss_edp_phy: phy@aec2a00 { 4065 compatible = "qcom,sc7280-edp-phy"; 4066 4067 reg = <0 0xaec2a00 0 0x19c>, 4068 <0 0xaec2200 0 0xa0>, 4069 <0 0xaec2600 0 0xa0>, 4070 <0 0xaec2000 0 0x1c0>; 4071 4072 clocks = <&rpmhcc RPMH_CXO_CLK>, 4073 <&gcc GCC_EDP_CLKREF_EN>; 4074 clock-names = "aux", 4075 "cfg_ahb"; 4076 4077 #clock-cells = <1>; 4078 #phy-cells = <0>; 4079 4080 status = "disabled"; 4081 }; 4082 4083 mdss_dp: displayport-controller@ae90000 { 4084 compatible = "qcom,sc7280-dp"; 4085 4086 reg = <0 0xae90000 0 0x200>, 4087 <0 0xae90200 0 0x200>, 4088 <0 0xae90400 0 0xc00>, 4089 <0 0xae91000 0 0x400>, 4090 <0 0xae91400 0 0x400>; 4091 4092 interrupt-parent = <&mdss>; 4093 interrupts = <12>; 4094 4095 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4096 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4097 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4098 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4099 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4100 clock-names = "core_iface", 4101 "core_aux", 4102 "ctrl_link", 4103 "ctrl_link_iface", 4104 "stream_pixel"; 4105 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4106 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4107 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4108 phys = <&dp_phy>; 4109 phy-names = "dp"; 4110 4111 operating-points-v2 = <&dp_opp_table>; 4112 power-domains = <&rpmhpd SC7280_CX>; 4113 4114 #sound-dai-cells = <0>; 4115 4116 status = "disabled"; 4117 4118 ports { 4119 #address-cells = <1>; 4120 #size-cells = <0>; 4121 4122 port@0 { 4123 reg = <0>; 4124 dp_in: endpoint { 4125 remote-endpoint = <&dpu_intf0_out>; 4126 }; 4127 }; 4128 4129 port@1 { 4130 reg = <1>; 4131 dp_out: endpoint { }; 4132 }; 4133 }; 4134 4135 dp_opp_table: opp-table { 4136 compatible = "operating-points-v2"; 4137 4138 opp-160000000 { 4139 opp-hz = /bits/ 64 <160000000>; 4140 required-opps = <&rpmhpd_opp_low_svs>; 4141 }; 4142 4143 opp-270000000 { 4144 opp-hz = /bits/ 64 <270000000>; 4145 required-opps = <&rpmhpd_opp_svs>; 4146 }; 4147 4148 opp-540000000 { 4149 opp-hz = /bits/ 64 <540000000>; 4150 required-opps = <&rpmhpd_opp_svs_l1>; 4151 }; 4152 4153 opp-810000000 { 4154 opp-hz = /bits/ 64 <810000000>; 4155 required-opps = <&rpmhpd_opp_nom>; 4156 }; 4157 }; 4158 }; 4159 }; 4160 4161 pdc: interrupt-controller@b220000 { 4162 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4163 reg = <0 0x0b220000 0 0x30000>; 4164 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4165 <55 306 4>, <59 312 3>, <62 374 2>, 4166 <64 434 2>, <66 438 3>, <69 86 1>, 4167 <70 520 54>, <124 609 31>, <155 63 1>, 4168 <156 716 12>; 4169 #interrupt-cells = <2>; 4170 interrupt-parent = <&intc>; 4171 interrupt-controller; 4172 }; 4173 4174 pdc_reset: reset-controller@b5e0000 { 4175 compatible = "qcom,sc7280-pdc-global"; 4176 reg = <0 0x0b5e0000 0 0x20000>; 4177 #reset-cells = <1>; 4178 }; 4179 4180 tsens0: thermal-sensor@c263000 { 4181 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4182 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4183 <0 0x0c222000 0 0x1ff>; /* SROT */ 4184 #qcom,sensors = <15>; 4185 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4187 interrupt-names = "uplow","critical"; 4188 #thermal-sensor-cells = <1>; 4189 }; 4190 4191 tsens1: thermal-sensor@c265000 { 4192 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4193 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4194 <0 0x0c223000 0 0x1ff>; /* SROT */ 4195 #qcom,sensors = <12>; 4196 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4198 interrupt-names = "uplow","critical"; 4199 #thermal-sensor-cells = <1>; 4200 }; 4201 4202 aoss_reset: reset-controller@c2a0000 { 4203 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4204 reg = <0 0x0c2a0000 0 0x31000>; 4205 #reset-cells = <1>; 4206 }; 4207 4208 aoss_qmp: power-controller@c300000 { 4209 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4210 reg = <0 0x0c300000 0 0x400>; 4211 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4212 IPCC_MPROC_SIGNAL_GLINK_QMP 4213 IRQ_TYPE_EDGE_RISING>; 4214 mboxes = <&ipcc IPCC_CLIENT_AOP 4215 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4216 4217 #clock-cells = <0>; 4218 }; 4219 4220 sram@c3f0000 { 4221 compatible = "qcom,rpmh-stats"; 4222 reg = <0 0x0c3f0000 0 0x400>; 4223 }; 4224 4225 spmi_bus: spmi@c440000 { 4226 compatible = "qcom,spmi-pmic-arb"; 4227 reg = <0 0x0c440000 0 0x1100>, 4228 <0 0x0c600000 0 0x2000000>, 4229 <0 0x0e600000 0 0x100000>, 4230 <0 0x0e700000 0 0xa0000>, 4231 <0 0x0c40a000 0 0x26000>; 4232 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4233 interrupt-names = "periph_irq"; 4234 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4235 qcom,ee = <0>; 4236 qcom,channel = <0>; 4237 #address-cells = <1>; 4238 #size-cells = <1>; 4239 interrupt-controller; 4240 #interrupt-cells = <4>; 4241 }; 4242 4243 tlmm: pinctrl@f100000 { 4244 compatible = "qcom,sc7280-pinctrl"; 4245 reg = <0 0x0f100000 0 0x300000>; 4246 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4247 gpio-controller; 4248 #gpio-cells = <2>; 4249 interrupt-controller; 4250 #interrupt-cells = <2>; 4251 gpio-ranges = <&tlmm 0 0 175>; 4252 wakeup-parent = <&pdc>; 4253 4254 dp_hot_plug_det: dp-hot-plug-det-state { 4255 pins = "gpio47"; 4256 function = "dp_hot"; 4257 }; 4258 4259 edp_hot_plug_det: edp-hot-plug-det-state { 4260 pins = "gpio60"; 4261 function = "edp_hot"; 4262 }; 4263 4264 mi2s0_data0: mi2s0-data0-state { 4265 pins = "gpio98"; 4266 function = "mi2s0_data0"; 4267 }; 4268 4269 mi2s0_data1: mi2s0-data1-state { 4270 pins = "gpio99"; 4271 function = "mi2s0_data1"; 4272 }; 4273 4274 mi2s0_mclk: mi2s0-mclk-state { 4275 pins = "gpio96"; 4276 function = "pri_mi2s"; 4277 }; 4278 4279 mi2s0_sclk: mi2s0-sclk-state { 4280 pins = "gpio97"; 4281 function = "mi2s0_sck"; 4282 }; 4283 4284 mi2s0_ws: mi2s0-ws-state { 4285 pins = "gpio100"; 4286 function = "mi2s0_ws"; 4287 }; 4288 4289 mi2s1_data0: mi2s1-data0-state { 4290 pins = "gpio107"; 4291 function = "mi2s1_data0"; 4292 }; 4293 4294 mi2s1_sclk: mi2s1-sclk-state { 4295 pins = "gpio106"; 4296 function = "mi2s1_sck"; 4297 }; 4298 4299 mi2s1_ws: mi2s1-ws-state { 4300 pins = "gpio108"; 4301 function = "mi2s1_ws"; 4302 }; 4303 4304 pcie1_clkreq_n: pcie1-clkreq-n-state { 4305 pins = "gpio79"; 4306 function = "pcie1_clkreqn"; 4307 }; 4308 4309 qspi_clk: qspi-clk-state { 4310 pins = "gpio14"; 4311 function = "qspi_clk"; 4312 }; 4313 4314 qspi_cs0: qspi-cs0-state { 4315 pins = "gpio15"; 4316 function = "qspi_cs"; 4317 }; 4318 4319 qspi_cs1: qspi-cs1-state { 4320 pins = "gpio19"; 4321 function = "qspi_cs"; 4322 }; 4323 4324 qspi_data01: qspi-data01-state { 4325 pins = "gpio12", "gpio13"; 4326 function = "qspi_data"; 4327 }; 4328 4329 qspi_data12: qspi-data12-state { 4330 pins = "gpio16", "gpio17"; 4331 function = "qspi_data"; 4332 }; 4333 4334 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4335 pins = "gpio0", "gpio1"; 4336 function = "qup00"; 4337 }; 4338 4339 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4340 pins = "gpio4", "gpio5"; 4341 function = "qup01"; 4342 }; 4343 4344 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4345 pins = "gpio8", "gpio9"; 4346 function = "qup02"; 4347 }; 4348 4349 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4350 pins = "gpio12", "gpio13"; 4351 function = "qup03"; 4352 }; 4353 4354 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4355 pins = "gpio16", "gpio17"; 4356 function = "qup04"; 4357 }; 4358 4359 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4360 pins = "gpio20", "gpio21"; 4361 function = "qup05"; 4362 }; 4363 4364 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4365 pins = "gpio24", "gpio25"; 4366 function = "qup06"; 4367 }; 4368 4369 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4370 pins = "gpio28", "gpio29"; 4371 function = "qup07"; 4372 }; 4373 4374 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4375 pins = "gpio32", "gpio33"; 4376 function = "qup10"; 4377 }; 4378 4379 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4380 pins = "gpio36", "gpio37"; 4381 function = "qup11"; 4382 }; 4383 4384 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4385 pins = "gpio40", "gpio41"; 4386 function = "qup12"; 4387 }; 4388 4389 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4390 pins = "gpio44", "gpio45"; 4391 function = "qup13"; 4392 }; 4393 4394 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4395 pins = "gpio48", "gpio49"; 4396 function = "qup14"; 4397 }; 4398 4399 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4400 pins = "gpio52", "gpio53"; 4401 function = "qup15"; 4402 }; 4403 4404 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4405 pins = "gpio56", "gpio57"; 4406 function = "qup16"; 4407 }; 4408 4409 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4410 pins = "gpio60", "gpio61"; 4411 function = "qup17"; 4412 }; 4413 4414 qup_spi0_data_clk: qup-spi0-data-clk-state { 4415 pins = "gpio0", "gpio1", "gpio2"; 4416 function = "qup00"; 4417 }; 4418 4419 qup_spi0_cs: qup-spi0-cs-state { 4420 pins = "gpio3"; 4421 function = "qup00"; 4422 }; 4423 4424 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4425 pins = "gpio3"; 4426 function = "gpio"; 4427 }; 4428 4429 qup_spi1_data_clk: qup-spi1-data-clk-state { 4430 pins = "gpio4", "gpio5", "gpio6"; 4431 function = "qup01"; 4432 }; 4433 4434 qup_spi1_cs: qup-spi1-cs-state { 4435 pins = "gpio7"; 4436 function = "qup01"; 4437 }; 4438 4439 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4440 pins = "gpio7"; 4441 function = "gpio"; 4442 }; 4443 4444 qup_spi2_data_clk: qup-spi2-data-clk-state { 4445 pins = "gpio8", "gpio9", "gpio10"; 4446 function = "qup02"; 4447 }; 4448 4449 qup_spi2_cs: qup-spi2-cs-state { 4450 pins = "gpio11"; 4451 function = "qup02"; 4452 }; 4453 4454 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4455 pins = "gpio11"; 4456 function = "gpio"; 4457 }; 4458 4459 qup_spi3_data_clk: qup-spi3-data-clk-state { 4460 pins = "gpio12", "gpio13", "gpio14"; 4461 function = "qup03"; 4462 }; 4463 4464 qup_spi3_cs: qup-spi3-cs-state { 4465 pins = "gpio15"; 4466 function = "qup03"; 4467 }; 4468 4469 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4470 pins = "gpio15"; 4471 function = "gpio"; 4472 }; 4473 4474 qup_spi4_data_clk: qup-spi4-data-clk-state { 4475 pins = "gpio16", "gpio17", "gpio18"; 4476 function = "qup04"; 4477 }; 4478 4479 qup_spi4_cs: qup-spi4-cs-state { 4480 pins = "gpio19"; 4481 function = "qup04"; 4482 }; 4483 4484 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4485 pins = "gpio19"; 4486 function = "gpio"; 4487 }; 4488 4489 qup_spi5_data_clk: qup-spi5-data-clk-state { 4490 pins = "gpio20", "gpio21", "gpio22"; 4491 function = "qup05"; 4492 }; 4493 4494 qup_spi5_cs: qup-spi5-cs-state { 4495 pins = "gpio23"; 4496 function = "qup05"; 4497 }; 4498 4499 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4500 pins = "gpio23"; 4501 function = "gpio"; 4502 }; 4503 4504 qup_spi6_data_clk: qup-spi6-data-clk-state { 4505 pins = "gpio24", "gpio25", "gpio26"; 4506 function = "qup06"; 4507 }; 4508 4509 qup_spi6_cs: qup-spi6-cs-state { 4510 pins = "gpio27"; 4511 function = "qup06"; 4512 }; 4513 4514 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4515 pins = "gpio27"; 4516 function = "gpio"; 4517 }; 4518 4519 qup_spi7_data_clk: qup-spi7-data-clk-state { 4520 pins = "gpio28", "gpio29", "gpio30"; 4521 function = "qup07"; 4522 }; 4523 4524 qup_spi7_cs: qup-spi7-cs-state { 4525 pins = "gpio31"; 4526 function = "qup07"; 4527 }; 4528 4529 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4530 pins = "gpio31"; 4531 function = "gpio"; 4532 }; 4533 4534 qup_spi8_data_clk: qup-spi8-data-clk-state { 4535 pins = "gpio32", "gpio33", "gpio34"; 4536 function = "qup10"; 4537 }; 4538 4539 qup_spi8_cs: qup-spi8-cs-state { 4540 pins = "gpio35"; 4541 function = "qup10"; 4542 }; 4543 4544 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4545 pins = "gpio35"; 4546 function = "gpio"; 4547 }; 4548 4549 qup_spi9_data_clk: qup-spi9-data-clk-state { 4550 pins = "gpio36", "gpio37", "gpio38"; 4551 function = "qup11"; 4552 }; 4553 4554 qup_spi9_cs: qup-spi9-cs-state { 4555 pins = "gpio39"; 4556 function = "qup11"; 4557 }; 4558 4559 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4560 pins = "gpio39"; 4561 function = "gpio"; 4562 }; 4563 4564 qup_spi10_data_clk: qup-spi10-data-clk-state { 4565 pins = "gpio40", "gpio41", "gpio42"; 4566 function = "qup12"; 4567 }; 4568 4569 qup_spi10_cs: qup-spi10-cs-state { 4570 pins = "gpio43"; 4571 function = "qup12"; 4572 }; 4573 4574 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4575 pins = "gpio43"; 4576 function = "gpio"; 4577 }; 4578 4579 qup_spi11_data_clk: qup-spi11-data-clk-state { 4580 pins = "gpio44", "gpio45", "gpio46"; 4581 function = "qup13"; 4582 }; 4583 4584 qup_spi11_cs: qup-spi11-cs-state { 4585 pins = "gpio47"; 4586 function = "qup13"; 4587 }; 4588 4589 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4590 pins = "gpio47"; 4591 function = "gpio"; 4592 }; 4593 4594 qup_spi12_data_clk: qup-spi12-data-clk-state { 4595 pins = "gpio48", "gpio49", "gpio50"; 4596 function = "qup14"; 4597 }; 4598 4599 qup_spi12_cs: qup-spi12-cs-state { 4600 pins = "gpio51"; 4601 function = "qup14"; 4602 }; 4603 4604 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4605 pins = "gpio51"; 4606 function = "gpio"; 4607 }; 4608 4609 qup_spi13_data_clk: qup-spi13-data-clk-state { 4610 pins = "gpio52", "gpio53", "gpio54"; 4611 function = "qup15"; 4612 }; 4613 4614 qup_spi13_cs: qup-spi13-cs-state { 4615 pins = "gpio55"; 4616 function = "qup15"; 4617 }; 4618 4619 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4620 pins = "gpio55"; 4621 function = "gpio"; 4622 }; 4623 4624 qup_spi14_data_clk: qup-spi14-data-clk-state { 4625 pins = "gpio56", "gpio57", "gpio58"; 4626 function = "qup16"; 4627 }; 4628 4629 qup_spi14_cs: qup-spi14-cs-state { 4630 pins = "gpio59"; 4631 function = "qup16"; 4632 }; 4633 4634 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4635 pins = "gpio59"; 4636 function = "gpio"; 4637 }; 4638 4639 qup_spi15_data_clk: qup-spi15-data-clk-state { 4640 pins = "gpio60", "gpio61", "gpio62"; 4641 function = "qup17"; 4642 }; 4643 4644 qup_spi15_cs: qup-spi15-cs-state { 4645 pins = "gpio63"; 4646 function = "qup17"; 4647 }; 4648 4649 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4650 pins = "gpio63"; 4651 function = "gpio"; 4652 }; 4653 4654 qup_uart0_cts: qup-uart0-cts-state { 4655 pins = "gpio0"; 4656 function = "qup00"; 4657 }; 4658 4659 qup_uart0_rts: qup-uart0-rts-state { 4660 pins = "gpio1"; 4661 function = "qup00"; 4662 }; 4663 4664 qup_uart0_tx: qup-uart0-tx-state { 4665 pins = "gpio2"; 4666 function = "qup00"; 4667 }; 4668 4669 qup_uart0_rx: qup-uart0-rx-state { 4670 pins = "gpio3"; 4671 function = "qup00"; 4672 }; 4673 4674 qup_uart1_cts: qup-uart1-cts-state { 4675 pins = "gpio4"; 4676 function = "qup01"; 4677 }; 4678 4679 qup_uart1_rts: qup-uart1-rts-state { 4680 pins = "gpio5"; 4681 function = "qup01"; 4682 }; 4683 4684 qup_uart1_tx: qup-uart1-tx-state { 4685 pins = "gpio6"; 4686 function = "qup01"; 4687 }; 4688 4689 qup_uart1_rx: qup-uart1-rx-state { 4690 pins = "gpio7"; 4691 function = "qup01"; 4692 }; 4693 4694 qup_uart2_cts: qup-uart2-cts-state { 4695 pins = "gpio8"; 4696 function = "qup02"; 4697 }; 4698 4699 qup_uart2_rts: qup-uart2-rts-state { 4700 pins = "gpio9"; 4701 function = "qup02"; 4702 }; 4703 4704 qup_uart2_tx: qup-uart2-tx-state { 4705 pins = "gpio10"; 4706 function = "qup02"; 4707 }; 4708 4709 qup_uart2_rx: qup-uart2-rx-state { 4710 pins = "gpio11"; 4711 function = "qup02"; 4712 }; 4713 4714 qup_uart3_cts: qup-uart3-cts-state { 4715 pins = "gpio12"; 4716 function = "qup03"; 4717 }; 4718 4719 qup_uart3_rts: qup-uart3-rts-state { 4720 pins = "gpio13"; 4721 function = "qup03"; 4722 }; 4723 4724 qup_uart3_tx: qup-uart3-tx-state { 4725 pins = "gpio14"; 4726 function = "qup03"; 4727 }; 4728 4729 qup_uart3_rx: qup-uart3-rx-state { 4730 pins = "gpio15"; 4731 function = "qup03"; 4732 }; 4733 4734 qup_uart4_cts: qup-uart4-cts-state { 4735 pins = "gpio16"; 4736 function = "qup04"; 4737 }; 4738 4739 qup_uart4_rts: qup-uart4-rts-state { 4740 pins = "gpio17"; 4741 function = "qup04"; 4742 }; 4743 4744 qup_uart4_tx: qup-uart4-tx-state { 4745 pins = "gpio18"; 4746 function = "qup04"; 4747 }; 4748 4749 qup_uart4_rx: qup-uart4-rx-state { 4750 pins = "gpio19"; 4751 function = "qup04"; 4752 }; 4753 4754 qup_uart5_cts: qup-uart5-cts-state { 4755 pins = "gpio20"; 4756 function = "qup05"; 4757 }; 4758 4759 qup_uart5_rts: qup-uart5-rts-state { 4760 pins = "gpio21"; 4761 function = "qup05"; 4762 }; 4763 4764 qup_uart5_tx: qup-uart5-tx-state { 4765 pins = "gpio22"; 4766 function = "qup05"; 4767 }; 4768 4769 qup_uart5_rx: qup-uart5-rx-state { 4770 pins = "gpio23"; 4771 function = "qup05"; 4772 }; 4773 4774 qup_uart6_cts: qup-uart6-cts-state { 4775 pins = "gpio24"; 4776 function = "qup06"; 4777 }; 4778 4779 qup_uart6_rts: qup-uart6-rts-state { 4780 pins = "gpio25"; 4781 function = "qup06"; 4782 }; 4783 4784 qup_uart6_tx: qup-uart6-tx-state { 4785 pins = "gpio26"; 4786 function = "qup06"; 4787 }; 4788 4789 qup_uart6_rx: qup-uart6-rx-state { 4790 pins = "gpio27"; 4791 function = "qup06"; 4792 }; 4793 4794 qup_uart7_cts: qup-uart7-cts-state { 4795 pins = "gpio28"; 4796 function = "qup07"; 4797 }; 4798 4799 qup_uart7_rts: qup-uart7-rts-state { 4800 pins = "gpio29"; 4801 function = "qup07"; 4802 }; 4803 4804 qup_uart7_tx: qup-uart7-tx-state { 4805 pins = "gpio30"; 4806 function = "qup07"; 4807 }; 4808 4809 qup_uart7_rx: qup-uart7-rx-state { 4810 pins = "gpio31"; 4811 function = "qup07"; 4812 }; 4813 4814 qup_uart8_cts: qup-uart8-cts-state { 4815 pins = "gpio32"; 4816 function = "qup10"; 4817 }; 4818 4819 qup_uart8_rts: qup-uart8-rts-state { 4820 pins = "gpio33"; 4821 function = "qup10"; 4822 }; 4823 4824 qup_uart8_tx: qup-uart8-tx-state { 4825 pins = "gpio34"; 4826 function = "qup10"; 4827 }; 4828 4829 qup_uart8_rx: qup-uart8-rx-state { 4830 pins = "gpio35"; 4831 function = "qup10"; 4832 }; 4833 4834 qup_uart9_cts: qup-uart9-cts-state { 4835 pins = "gpio36"; 4836 function = "qup11"; 4837 }; 4838 4839 qup_uart9_rts: qup-uart9-rts-state { 4840 pins = "gpio37"; 4841 function = "qup11"; 4842 }; 4843 4844 qup_uart9_tx: qup-uart9-tx-state { 4845 pins = "gpio38"; 4846 function = "qup11"; 4847 }; 4848 4849 qup_uart9_rx: qup-uart9-rx-state { 4850 pins = "gpio39"; 4851 function = "qup11"; 4852 }; 4853 4854 qup_uart10_cts: qup-uart10-cts-state { 4855 pins = "gpio40"; 4856 function = "qup12"; 4857 }; 4858 4859 qup_uart10_rts: qup-uart10-rts-state { 4860 pins = "gpio41"; 4861 function = "qup12"; 4862 }; 4863 4864 qup_uart10_tx: qup-uart10-tx-state { 4865 pins = "gpio42"; 4866 function = "qup12"; 4867 }; 4868 4869 qup_uart10_rx: qup-uart10-rx-state { 4870 pins = "gpio43"; 4871 function = "qup12"; 4872 }; 4873 4874 qup_uart11_cts: qup-uart11-cts-state { 4875 pins = "gpio44"; 4876 function = "qup13"; 4877 }; 4878 4879 qup_uart11_rts: qup-uart11-rts-state { 4880 pins = "gpio45"; 4881 function = "qup13"; 4882 }; 4883 4884 qup_uart11_tx: qup-uart11-tx-state { 4885 pins = "gpio46"; 4886 function = "qup13"; 4887 }; 4888 4889 qup_uart11_rx: qup-uart11-rx-state { 4890 pins = "gpio47"; 4891 function = "qup13"; 4892 }; 4893 4894 qup_uart12_cts: qup-uart12-cts-state { 4895 pins = "gpio48"; 4896 function = "qup14"; 4897 }; 4898 4899 qup_uart12_rts: qup-uart12-rts-state { 4900 pins = "gpio49"; 4901 function = "qup14"; 4902 }; 4903 4904 qup_uart12_tx: qup-uart12-tx-state { 4905 pins = "gpio50"; 4906 function = "qup14"; 4907 }; 4908 4909 qup_uart12_rx: qup-uart12-rx-state { 4910 pins = "gpio51"; 4911 function = "qup14"; 4912 }; 4913 4914 qup_uart13_cts: qup-uart13-cts-state { 4915 pins = "gpio52"; 4916 function = "qup15"; 4917 }; 4918 4919 qup_uart13_rts: qup-uart13-rts-state { 4920 pins = "gpio53"; 4921 function = "qup15"; 4922 }; 4923 4924 qup_uart13_tx: qup-uart13-tx-state { 4925 pins = "gpio54"; 4926 function = "qup15"; 4927 }; 4928 4929 qup_uart13_rx: qup-uart13-rx-state { 4930 pins = "gpio55"; 4931 function = "qup15"; 4932 }; 4933 4934 qup_uart14_cts: qup-uart14-cts-state { 4935 pins = "gpio56"; 4936 function = "qup16"; 4937 }; 4938 4939 qup_uart14_rts: qup-uart14-rts-state { 4940 pins = "gpio57"; 4941 function = "qup16"; 4942 }; 4943 4944 qup_uart14_tx: qup-uart14-tx-state { 4945 pins = "gpio58"; 4946 function = "qup16"; 4947 }; 4948 4949 qup_uart14_rx: qup-uart14-rx-state { 4950 pins = "gpio59"; 4951 function = "qup16"; 4952 }; 4953 4954 qup_uart15_cts: qup-uart15-cts-state { 4955 pins = "gpio60"; 4956 function = "qup17"; 4957 }; 4958 4959 qup_uart15_rts: qup-uart15-rts-state { 4960 pins = "gpio61"; 4961 function = "qup17"; 4962 }; 4963 4964 qup_uart15_tx: qup-uart15-tx-state { 4965 pins = "gpio62"; 4966 function = "qup17"; 4967 }; 4968 4969 qup_uart15_rx: qup-uart15-rx-state { 4970 pins = "gpio63"; 4971 function = "qup17"; 4972 }; 4973 4974 sdc1_clk: sdc1-clk-state { 4975 pins = "sdc1_clk"; 4976 }; 4977 4978 sdc1_cmd: sdc1-cmd-state { 4979 pins = "sdc1_cmd"; 4980 }; 4981 4982 sdc1_data: sdc1-data-state { 4983 pins = "sdc1_data"; 4984 }; 4985 4986 sdc1_rclk: sdc1-rclk-state { 4987 pins = "sdc1_rclk"; 4988 }; 4989 4990 sdc1_clk_sleep: sdc1-clk-sleep-state { 4991 pins = "sdc1_clk"; 4992 drive-strength = <2>; 4993 bias-bus-hold; 4994 }; 4995 4996 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 4997 pins = "sdc1_cmd"; 4998 drive-strength = <2>; 4999 bias-bus-hold; 5000 }; 5001 5002 sdc1_data_sleep: sdc1-data-sleep-state { 5003 pins = "sdc1_data"; 5004 drive-strength = <2>; 5005 bias-bus-hold; 5006 }; 5007 5008 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5009 pins = "sdc1_rclk"; 5010 drive-strength = <2>; 5011 bias-bus-hold; 5012 }; 5013 5014 sdc2_clk: sdc2-clk-state { 5015 pins = "sdc2_clk"; 5016 }; 5017 5018 sdc2_cmd: sdc2-cmd-state { 5019 pins = "sdc2_cmd"; 5020 }; 5021 5022 sdc2_data: sdc2-data-state { 5023 pins = "sdc2_data"; 5024 }; 5025 5026 sdc2_clk_sleep: sdc2-clk-sleep-state { 5027 pins = "sdc2_clk"; 5028 drive-strength = <2>; 5029 bias-bus-hold; 5030 }; 5031 5032 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5033 pins = "sdc2_cmd"; 5034 drive-strength = <2>; 5035 bias-bus-hold; 5036 }; 5037 5038 sdc2_data_sleep: sdc2-data-sleep-state { 5039 pins = "sdc2_data"; 5040 drive-strength = <2>; 5041 bias-bus-hold; 5042 }; 5043 }; 5044 5045 sram@146a5000 { 5046 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5047 reg = <0 0x146a5000 0 0x6000>; 5048 5049 #address-cells = <1>; 5050 #size-cells = <1>; 5051 5052 ranges = <0 0 0x146a5000 0x6000>; 5053 5054 pil-reloc@594c { 5055 compatible = "qcom,pil-reloc-info"; 5056 reg = <0x594c 0xc8>; 5057 }; 5058 }; 5059 5060 apps_smmu: iommu@15000000 { 5061 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5062 reg = <0 0x15000000 0 0x100000>; 5063 #iommu-cells = <2>; 5064 #global-interrupts = <1>; 5065 dma-coherent; 5066 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5147 }; 5148 5149 intc: interrupt-controller@17a00000 { 5150 compatible = "arm,gic-v3"; 5151 #address-cells = <2>; 5152 #size-cells = <2>; 5153 ranges; 5154 #interrupt-cells = <3>; 5155 interrupt-controller; 5156 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5157 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5158 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5159 5160 gic-its@17a40000 { 5161 compatible = "arm,gic-v3-its"; 5162 msi-controller; 5163 #msi-cells = <1>; 5164 reg = <0 0x17a40000 0 0x20000>; 5165 status = "disabled"; 5166 }; 5167 }; 5168 5169 watchdog@17c10000 { 5170 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5171 reg = <0 0x17c10000 0 0x1000>; 5172 clocks = <&sleep_clk>; 5173 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5174 }; 5175 5176 timer@17c20000 { 5177 #address-cells = <1>; 5178 #size-cells = <1>; 5179 ranges = <0 0 0 0x20000000>; 5180 compatible = "arm,armv7-timer-mem"; 5181 reg = <0 0x17c20000 0 0x1000>; 5182 5183 frame@17c21000 { 5184 frame-number = <0>; 5185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5187 reg = <0x17c21000 0x1000>, 5188 <0x17c22000 0x1000>; 5189 }; 5190 5191 frame@17c23000 { 5192 frame-number = <1>; 5193 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5194 reg = <0x17c23000 0x1000>; 5195 status = "disabled"; 5196 }; 5197 5198 frame@17c25000 { 5199 frame-number = <2>; 5200 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5201 reg = <0x17c25000 0x1000>; 5202 status = "disabled"; 5203 }; 5204 5205 frame@17c27000 { 5206 frame-number = <3>; 5207 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5208 reg = <0x17c27000 0x1000>; 5209 status = "disabled"; 5210 }; 5211 5212 frame@17c29000 { 5213 frame-number = <4>; 5214 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5215 reg = <0x17c29000 0x1000>; 5216 status = "disabled"; 5217 }; 5218 5219 frame@17c2b000 { 5220 frame-number = <5>; 5221 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5222 reg = <0x17c2b000 0x1000>; 5223 status = "disabled"; 5224 }; 5225 5226 frame@17c2d000 { 5227 frame-number = <6>; 5228 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5229 reg = <0x17c2d000 0x1000>; 5230 status = "disabled"; 5231 }; 5232 }; 5233 5234 apps_rsc: rsc@18200000 { 5235 compatible = "qcom,rpmh-rsc"; 5236 reg = <0 0x18200000 0 0x10000>, 5237 <0 0x18210000 0 0x10000>, 5238 <0 0x18220000 0 0x10000>; 5239 reg-names = "drv-0", "drv-1", "drv-2"; 5240 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5241 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5242 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5243 qcom,tcs-offset = <0xd00>; 5244 qcom,drv-id = <2>; 5245 qcom,tcs-config = <ACTIVE_TCS 2>, 5246 <SLEEP_TCS 3>, 5247 <WAKE_TCS 3>, 5248 <CONTROL_TCS 1>; 5249 5250 apps_bcm_voter: bcm-voter { 5251 compatible = "qcom,bcm-voter"; 5252 }; 5253 5254 rpmhpd: power-controller { 5255 compatible = "qcom,sc7280-rpmhpd"; 5256 #power-domain-cells = <1>; 5257 operating-points-v2 = <&rpmhpd_opp_table>; 5258 5259 rpmhpd_opp_table: opp-table { 5260 compatible = "operating-points-v2"; 5261 5262 rpmhpd_opp_ret: opp1 { 5263 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5264 }; 5265 5266 rpmhpd_opp_low_svs: opp2 { 5267 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5268 }; 5269 5270 rpmhpd_opp_svs: opp3 { 5271 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5272 }; 5273 5274 rpmhpd_opp_svs_l1: opp4 { 5275 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5276 }; 5277 5278 rpmhpd_opp_svs_l2: opp5 { 5279 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5280 }; 5281 5282 rpmhpd_opp_nom: opp6 { 5283 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5284 }; 5285 5286 rpmhpd_opp_nom_l1: opp7 { 5287 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5288 }; 5289 5290 rpmhpd_opp_turbo: opp8 { 5291 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5292 }; 5293 5294 rpmhpd_opp_turbo_l1: opp9 { 5295 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5296 }; 5297 }; 5298 }; 5299 5300 rpmhcc: clock-controller { 5301 compatible = "qcom,sc7280-rpmh-clk"; 5302 clocks = <&xo_board>; 5303 clock-names = "xo"; 5304 #clock-cells = <1>; 5305 }; 5306 }; 5307 5308 epss_l3: interconnect@18590000 { 5309 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5310 reg = <0 0x18590000 0 0x1000>; 5311 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5312 clock-names = "xo", "alternate"; 5313 #interconnect-cells = <1>; 5314 }; 5315 5316 cpufreq_hw: cpufreq@18591000 { 5317 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5318 reg = <0 0x18591000 0 0x1000>, 5319 <0 0x18592000 0 0x1000>, 5320 <0 0x18593000 0 0x1000>; 5321 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5322 clock-names = "xo", "alternate"; 5323 #freq-domain-cells = <1>; 5324 }; 5325 }; 5326 5327 thermal_zones: thermal-zones { 5328 cpu0-thermal { 5329 polling-delay-passive = <250>; 5330 polling-delay = <0>; 5331 5332 thermal-sensors = <&tsens0 1>; 5333 5334 trips { 5335 cpu0_alert0: trip-point0 { 5336 temperature = <90000>; 5337 hysteresis = <2000>; 5338 type = "passive"; 5339 }; 5340 5341 cpu0_alert1: trip-point1 { 5342 temperature = <95000>; 5343 hysteresis = <2000>; 5344 type = "passive"; 5345 }; 5346 5347 cpu0_crit: cpu-crit { 5348 temperature = <110000>; 5349 hysteresis = <0>; 5350 type = "critical"; 5351 }; 5352 }; 5353 5354 cooling-maps { 5355 map0 { 5356 trip = <&cpu0_alert0>; 5357 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5358 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5359 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5360 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5361 }; 5362 map1 { 5363 trip = <&cpu0_alert1>; 5364 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5365 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5366 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5367 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5368 }; 5369 }; 5370 }; 5371 5372 cpu1-thermal { 5373 polling-delay-passive = <250>; 5374 polling-delay = <0>; 5375 5376 thermal-sensors = <&tsens0 2>; 5377 5378 trips { 5379 cpu1_alert0: trip-point0 { 5380 temperature = <90000>; 5381 hysteresis = <2000>; 5382 type = "passive"; 5383 }; 5384 5385 cpu1_alert1: trip-point1 { 5386 temperature = <95000>; 5387 hysteresis = <2000>; 5388 type = "passive"; 5389 }; 5390 5391 cpu1_crit: cpu-crit { 5392 temperature = <110000>; 5393 hysteresis = <0>; 5394 type = "critical"; 5395 }; 5396 }; 5397 5398 cooling-maps { 5399 map0 { 5400 trip = <&cpu1_alert0>; 5401 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5402 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5403 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5404 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5405 }; 5406 map1 { 5407 trip = <&cpu1_alert1>; 5408 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5409 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5412 }; 5413 }; 5414 }; 5415 5416 cpu2-thermal { 5417 polling-delay-passive = <250>; 5418 polling-delay = <0>; 5419 5420 thermal-sensors = <&tsens0 3>; 5421 5422 trips { 5423 cpu2_alert0: trip-point0 { 5424 temperature = <90000>; 5425 hysteresis = <2000>; 5426 type = "passive"; 5427 }; 5428 5429 cpu2_alert1: trip-point1 { 5430 temperature = <95000>; 5431 hysteresis = <2000>; 5432 type = "passive"; 5433 }; 5434 5435 cpu2_crit: cpu-crit { 5436 temperature = <110000>; 5437 hysteresis = <0>; 5438 type = "critical"; 5439 }; 5440 }; 5441 5442 cooling-maps { 5443 map0 { 5444 trip = <&cpu2_alert0>; 5445 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5446 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5447 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5448 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5449 }; 5450 map1 { 5451 trip = <&cpu2_alert1>; 5452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5456 }; 5457 }; 5458 }; 5459 5460 cpu3-thermal { 5461 polling-delay-passive = <250>; 5462 polling-delay = <0>; 5463 5464 thermal-sensors = <&tsens0 4>; 5465 5466 trips { 5467 cpu3_alert0: trip-point0 { 5468 temperature = <90000>; 5469 hysteresis = <2000>; 5470 type = "passive"; 5471 }; 5472 5473 cpu3_alert1: trip-point1 { 5474 temperature = <95000>; 5475 hysteresis = <2000>; 5476 type = "passive"; 5477 }; 5478 5479 cpu3_crit: cpu-crit { 5480 temperature = <110000>; 5481 hysteresis = <0>; 5482 type = "critical"; 5483 }; 5484 }; 5485 5486 cooling-maps { 5487 map0 { 5488 trip = <&cpu3_alert0>; 5489 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5490 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5491 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5492 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5493 }; 5494 map1 { 5495 trip = <&cpu3_alert1>; 5496 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5497 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5500 }; 5501 }; 5502 }; 5503 5504 cpu4-thermal { 5505 polling-delay-passive = <250>; 5506 polling-delay = <0>; 5507 5508 thermal-sensors = <&tsens0 7>; 5509 5510 trips { 5511 cpu4_alert0: trip-point0 { 5512 temperature = <90000>; 5513 hysteresis = <2000>; 5514 type = "passive"; 5515 }; 5516 5517 cpu4_alert1: trip-point1 { 5518 temperature = <95000>; 5519 hysteresis = <2000>; 5520 type = "passive"; 5521 }; 5522 5523 cpu4_crit: cpu-crit { 5524 temperature = <110000>; 5525 hysteresis = <0>; 5526 type = "critical"; 5527 }; 5528 }; 5529 5530 cooling-maps { 5531 map0 { 5532 trip = <&cpu4_alert0>; 5533 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5534 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5536 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5537 }; 5538 map1 { 5539 trip = <&cpu4_alert1>; 5540 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5541 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5544 }; 5545 }; 5546 }; 5547 5548 cpu5-thermal { 5549 polling-delay-passive = <250>; 5550 polling-delay = <0>; 5551 5552 thermal-sensors = <&tsens0 8>; 5553 5554 trips { 5555 cpu5_alert0: trip-point0 { 5556 temperature = <90000>; 5557 hysteresis = <2000>; 5558 type = "passive"; 5559 }; 5560 5561 cpu5_alert1: trip-point1 { 5562 temperature = <95000>; 5563 hysteresis = <2000>; 5564 type = "passive"; 5565 }; 5566 5567 cpu5_crit: cpu-crit { 5568 temperature = <110000>; 5569 hysteresis = <0>; 5570 type = "critical"; 5571 }; 5572 }; 5573 5574 cooling-maps { 5575 map0 { 5576 trip = <&cpu5_alert0>; 5577 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5578 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5580 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5581 }; 5582 map1 { 5583 trip = <&cpu5_alert1>; 5584 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5585 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5588 }; 5589 }; 5590 }; 5591 5592 cpu6-thermal { 5593 polling-delay-passive = <250>; 5594 polling-delay = <0>; 5595 5596 thermal-sensors = <&tsens0 9>; 5597 5598 trips { 5599 cpu6_alert0: trip-point0 { 5600 temperature = <90000>; 5601 hysteresis = <2000>; 5602 type = "passive"; 5603 }; 5604 5605 cpu6_alert1: trip-point1 { 5606 temperature = <95000>; 5607 hysteresis = <2000>; 5608 type = "passive"; 5609 }; 5610 5611 cpu6_crit: cpu-crit { 5612 temperature = <110000>; 5613 hysteresis = <0>; 5614 type = "critical"; 5615 }; 5616 }; 5617 5618 cooling-maps { 5619 map0 { 5620 trip = <&cpu6_alert0>; 5621 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5622 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5623 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5624 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5625 }; 5626 map1 { 5627 trip = <&cpu6_alert1>; 5628 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5629 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5632 }; 5633 }; 5634 }; 5635 5636 cpu7-thermal { 5637 polling-delay-passive = <250>; 5638 polling-delay = <0>; 5639 5640 thermal-sensors = <&tsens0 10>; 5641 5642 trips { 5643 cpu7_alert0: trip-point0 { 5644 temperature = <90000>; 5645 hysteresis = <2000>; 5646 type = "passive"; 5647 }; 5648 5649 cpu7_alert1: trip-point1 { 5650 temperature = <95000>; 5651 hysteresis = <2000>; 5652 type = "passive"; 5653 }; 5654 5655 cpu7_crit: cpu-crit { 5656 temperature = <110000>; 5657 hysteresis = <0>; 5658 type = "critical"; 5659 }; 5660 }; 5661 5662 cooling-maps { 5663 map0 { 5664 trip = <&cpu7_alert0>; 5665 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5666 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5667 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5668 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5669 }; 5670 map1 { 5671 trip = <&cpu7_alert1>; 5672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5676 }; 5677 }; 5678 }; 5679 5680 cpu8-thermal { 5681 polling-delay-passive = <250>; 5682 polling-delay = <0>; 5683 5684 thermal-sensors = <&tsens0 11>; 5685 5686 trips { 5687 cpu8_alert0: trip-point0 { 5688 temperature = <90000>; 5689 hysteresis = <2000>; 5690 type = "passive"; 5691 }; 5692 5693 cpu8_alert1: trip-point1 { 5694 temperature = <95000>; 5695 hysteresis = <2000>; 5696 type = "passive"; 5697 }; 5698 5699 cpu8_crit: cpu-crit { 5700 temperature = <110000>; 5701 hysteresis = <0>; 5702 type = "critical"; 5703 }; 5704 }; 5705 5706 cooling-maps { 5707 map0 { 5708 trip = <&cpu8_alert0>; 5709 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5710 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5712 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5713 }; 5714 map1 { 5715 trip = <&cpu8_alert1>; 5716 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5720 }; 5721 }; 5722 }; 5723 5724 cpu9-thermal { 5725 polling-delay-passive = <250>; 5726 polling-delay = <0>; 5727 5728 thermal-sensors = <&tsens0 12>; 5729 5730 trips { 5731 cpu9_alert0: trip-point0 { 5732 temperature = <90000>; 5733 hysteresis = <2000>; 5734 type = "passive"; 5735 }; 5736 5737 cpu9_alert1: trip-point1 { 5738 temperature = <95000>; 5739 hysteresis = <2000>; 5740 type = "passive"; 5741 }; 5742 5743 cpu9_crit: cpu-crit { 5744 temperature = <110000>; 5745 hysteresis = <0>; 5746 type = "critical"; 5747 }; 5748 }; 5749 5750 cooling-maps { 5751 map0 { 5752 trip = <&cpu9_alert0>; 5753 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5754 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5756 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5757 }; 5758 map1 { 5759 trip = <&cpu9_alert1>; 5760 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5764 }; 5765 }; 5766 }; 5767 5768 cpu10-thermal { 5769 polling-delay-passive = <250>; 5770 polling-delay = <0>; 5771 5772 thermal-sensors = <&tsens0 13>; 5773 5774 trips { 5775 cpu10_alert0: trip-point0 { 5776 temperature = <90000>; 5777 hysteresis = <2000>; 5778 type = "passive"; 5779 }; 5780 5781 cpu10_alert1: trip-point1 { 5782 temperature = <95000>; 5783 hysteresis = <2000>; 5784 type = "passive"; 5785 }; 5786 5787 cpu10_crit: cpu-crit { 5788 temperature = <110000>; 5789 hysteresis = <0>; 5790 type = "critical"; 5791 }; 5792 }; 5793 5794 cooling-maps { 5795 map0 { 5796 trip = <&cpu10_alert0>; 5797 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5800 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5801 }; 5802 map1 { 5803 trip = <&cpu10_alert1>; 5804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5808 }; 5809 }; 5810 }; 5811 5812 cpu11-thermal { 5813 polling-delay-passive = <250>; 5814 polling-delay = <0>; 5815 5816 thermal-sensors = <&tsens0 14>; 5817 5818 trips { 5819 cpu11_alert0: trip-point0 { 5820 temperature = <90000>; 5821 hysteresis = <2000>; 5822 type = "passive"; 5823 }; 5824 5825 cpu11_alert1: trip-point1 { 5826 temperature = <95000>; 5827 hysteresis = <2000>; 5828 type = "passive"; 5829 }; 5830 5831 cpu11_crit: cpu-crit { 5832 temperature = <110000>; 5833 hysteresis = <0>; 5834 type = "critical"; 5835 }; 5836 }; 5837 5838 cooling-maps { 5839 map0 { 5840 trip = <&cpu11_alert0>; 5841 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5844 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5845 }; 5846 map1 { 5847 trip = <&cpu11_alert1>; 5848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5852 }; 5853 }; 5854 }; 5855 5856 aoss0-thermal { 5857 polling-delay-passive = <0>; 5858 polling-delay = <0>; 5859 5860 thermal-sensors = <&tsens0 0>; 5861 5862 trips { 5863 aoss0_alert0: trip-point0 { 5864 temperature = <90000>; 5865 hysteresis = <2000>; 5866 type = "hot"; 5867 }; 5868 5869 aoss0_crit: aoss0-crit { 5870 temperature = <110000>; 5871 hysteresis = <0>; 5872 type = "critical"; 5873 }; 5874 }; 5875 }; 5876 5877 aoss1-thermal { 5878 polling-delay-passive = <0>; 5879 polling-delay = <0>; 5880 5881 thermal-sensors = <&tsens1 0>; 5882 5883 trips { 5884 aoss1_alert0: trip-point0 { 5885 temperature = <90000>; 5886 hysteresis = <2000>; 5887 type = "hot"; 5888 }; 5889 5890 aoss1_crit: aoss1-crit { 5891 temperature = <110000>; 5892 hysteresis = <0>; 5893 type = "critical"; 5894 }; 5895 }; 5896 }; 5897 5898 cpuss0-thermal { 5899 polling-delay-passive = <0>; 5900 polling-delay = <0>; 5901 5902 thermal-sensors = <&tsens0 5>; 5903 5904 trips { 5905 cpuss0_alert0: trip-point0 { 5906 temperature = <90000>; 5907 hysteresis = <2000>; 5908 type = "hot"; 5909 }; 5910 cpuss0_crit: cluster0-crit { 5911 temperature = <110000>; 5912 hysteresis = <0>; 5913 type = "critical"; 5914 }; 5915 }; 5916 }; 5917 5918 cpuss1-thermal { 5919 polling-delay-passive = <0>; 5920 polling-delay = <0>; 5921 5922 thermal-sensors = <&tsens0 6>; 5923 5924 trips { 5925 cpuss1_alert0: trip-point0 { 5926 temperature = <90000>; 5927 hysteresis = <2000>; 5928 type = "hot"; 5929 }; 5930 cpuss1_crit: cluster0-crit { 5931 temperature = <110000>; 5932 hysteresis = <0>; 5933 type = "critical"; 5934 }; 5935 }; 5936 }; 5937 5938 gpuss0-thermal { 5939 polling-delay-passive = <100>; 5940 polling-delay = <0>; 5941 5942 thermal-sensors = <&tsens1 1>; 5943 5944 trips { 5945 gpuss0_alert0: trip-point0 { 5946 temperature = <95000>; 5947 hysteresis = <2000>; 5948 type = "passive"; 5949 }; 5950 5951 gpuss0_crit: gpuss0-crit { 5952 temperature = <110000>; 5953 hysteresis = <0>; 5954 type = "critical"; 5955 }; 5956 }; 5957 5958 cooling-maps { 5959 map0 { 5960 trip = <&gpuss0_alert0>; 5961 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5962 }; 5963 }; 5964 }; 5965 5966 gpuss1-thermal { 5967 polling-delay-passive = <100>; 5968 polling-delay = <0>; 5969 5970 thermal-sensors = <&tsens1 2>; 5971 5972 trips { 5973 gpuss1_alert0: trip-point0 { 5974 temperature = <95000>; 5975 hysteresis = <2000>; 5976 type = "passive"; 5977 }; 5978 5979 gpuss1_crit: gpuss1-crit { 5980 temperature = <110000>; 5981 hysteresis = <0>; 5982 type = "critical"; 5983 }; 5984 }; 5985 5986 cooling-maps { 5987 map0 { 5988 trip = <&gpuss1_alert0>; 5989 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5990 }; 5991 }; 5992 }; 5993 5994 nspss0-thermal { 5995 polling-delay-passive = <0>; 5996 polling-delay = <0>; 5997 5998 thermal-sensors = <&tsens1 3>; 5999 6000 trips { 6001 nspss0_alert0: trip-point0 { 6002 temperature = <90000>; 6003 hysteresis = <2000>; 6004 type = "hot"; 6005 }; 6006 6007 nspss0_crit: nspss0-crit { 6008 temperature = <110000>; 6009 hysteresis = <0>; 6010 type = "critical"; 6011 }; 6012 }; 6013 }; 6014 6015 nspss1-thermal { 6016 polling-delay-passive = <0>; 6017 polling-delay = <0>; 6018 6019 thermal-sensors = <&tsens1 4>; 6020 6021 trips { 6022 nspss1_alert0: trip-point0 { 6023 temperature = <90000>; 6024 hysteresis = <2000>; 6025 type = "hot"; 6026 }; 6027 6028 nspss1_crit: nspss1-crit { 6029 temperature = <110000>; 6030 hysteresis = <0>; 6031 type = "critical"; 6032 }; 6033 }; 6034 }; 6035 6036 video-thermal { 6037 polling-delay-passive = <0>; 6038 polling-delay = <0>; 6039 6040 thermal-sensors = <&tsens1 5>; 6041 6042 trips { 6043 video_alert0: trip-point0 { 6044 temperature = <90000>; 6045 hysteresis = <2000>; 6046 type = "hot"; 6047 }; 6048 6049 video_crit: video-crit { 6050 temperature = <110000>; 6051 hysteresis = <0>; 6052 type = "critical"; 6053 }; 6054 }; 6055 }; 6056 6057 ddr-thermal { 6058 polling-delay-passive = <0>; 6059 polling-delay = <0>; 6060 6061 thermal-sensors = <&tsens1 6>; 6062 6063 trips { 6064 ddr_alert0: trip-point0 { 6065 temperature = <90000>; 6066 hysteresis = <2000>; 6067 type = "hot"; 6068 }; 6069 6070 ddr_crit: ddr-crit { 6071 temperature = <110000>; 6072 hysteresis = <0>; 6073 type = "critical"; 6074 }; 6075 }; 6076 }; 6077 6078 mdmss0-thermal { 6079 polling-delay-passive = <0>; 6080 polling-delay = <0>; 6081 6082 thermal-sensors = <&tsens1 7>; 6083 6084 trips { 6085 mdmss0_alert0: trip-point0 { 6086 temperature = <90000>; 6087 hysteresis = <2000>; 6088 type = "hot"; 6089 }; 6090 6091 mdmss0_crit: mdmss0-crit { 6092 temperature = <110000>; 6093 hysteresis = <0>; 6094 type = "critical"; 6095 }; 6096 }; 6097 }; 6098 6099 mdmss1-thermal { 6100 polling-delay-passive = <0>; 6101 polling-delay = <0>; 6102 6103 thermal-sensors = <&tsens1 8>; 6104 6105 trips { 6106 mdmss1_alert0: trip-point0 { 6107 temperature = <90000>; 6108 hysteresis = <2000>; 6109 type = "hot"; 6110 }; 6111 6112 mdmss1_crit: mdmss1-crit { 6113 temperature = <110000>; 6114 hysteresis = <0>; 6115 type = "critical"; 6116 }; 6117 }; 6118 }; 6119 6120 mdmss2-thermal { 6121 polling-delay-passive = <0>; 6122 polling-delay = <0>; 6123 6124 thermal-sensors = <&tsens1 9>; 6125 6126 trips { 6127 mdmss2_alert0: trip-point0 { 6128 temperature = <90000>; 6129 hysteresis = <2000>; 6130 type = "hot"; 6131 }; 6132 6133 mdmss2_crit: mdmss2-crit { 6134 temperature = <110000>; 6135 hysteresis = <0>; 6136 type = "critical"; 6137 }; 6138 }; 6139 }; 6140 6141 mdmss3-thermal { 6142 polling-delay-passive = <0>; 6143 polling-delay = <0>; 6144 6145 thermal-sensors = <&tsens1 10>; 6146 6147 trips { 6148 mdmss3_alert0: trip-point0 { 6149 temperature = <90000>; 6150 hysteresis = <2000>; 6151 type = "hot"; 6152 }; 6153 6154 mdmss3_crit: mdmss3-crit { 6155 temperature = <110000>; 6156 hysteresis = <0>; 6157 type = "critical"; 6158 }; 6159 }; 6160 }; 6161 6162 camera0-thermal { 6163 polling-delay-passive = <0>; 6164 polling-delay = <0>; 6165 6166 thermal-sensors = <&tsens1 11>; 6167 6168 trips { 6169 camera0_alert0: trip-point0 { 6170 temperature = <90000>; 6171 hysteresis = <2000>; 6172 type = "hot"; 6173 }; 6174 6175 camera0_crit: camera0-crit { 6176 temperature = <110000>; 6177 hysteresis = <0>; 6178 type = "critical"; 6179 }; 6180 }; 6181 }; 6182 }; 6183 6184 timer { 6185 compatible = "arm,armv8-timer"; 6186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6190 }; 6191}; 6192