1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-aoss-qmp.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/reset/qcom,sdm845-aoss.h> 15#include <dt-bindings/reset/qcom,sdm845-pdc.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 clock-frequency = <76800000>; 31 #clock-cells = <0>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32000>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 reserved-memory { 42 #address-cells = <2>; 43 #size-cells = <2>; 44 ranges; 45 46 aop_mem: memory@80800000 { 47 reg = <0x0 0x80800000 0x0 0x60000>; 48 no-map; 49 }; 50 51 aop_cmd_db_mem: memory@80860000 { 52 reg = <0x0 0x80860000 0x0 0x20000>; 53 compatible = "qcom,cmd-db"; 54 no-map; 55 }; 56 57 smem_mem: memory@80900000 { 58 reg = <0x0 0x80900000 0x0 0x200000>; 59 no-map; 60 }; 61 62 cpucp_mem: memory@80b00000 { 63 no-map; 64 reg = <0x0 0x80b00000 0x0 0x100000>; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <2>; 70 #size-cells = <0>; 71 72 CPU0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,kryo"; 75 reg = <0x0 0x0>; 76 enable-method = "psci"; 77 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 78 &LITTLE_CPU_SLEEP_1 79 &CLUSTER_SLEEP_0>; 80 next-level-cache = <&L2_0>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 L2_0: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 L3_0: l3-cache { 87 compatible = "cache"; 88 }; 89 }; 90 }; 91 92 CPU1: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,kryo"; 95 reg = <0x0 0x100>; 96 enable-method = "psci"; 97 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 98 &LITTLE_CPU_SLEEP_1 99 &CLUSTER_SLEEP_0>; 100 next-level-cache = <&L2_100>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 #cooling-cells = <2>; 103 L2_100: l2-cache { 104 compatible = "cache"; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU2: cpu@200 { 110 device_type = "cpu"; 111 compatible = "arm,kryo"; 112 reg = <0x0 0x200>; 113 enable-method = "psci"; 114 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 115 &LITTLE_CPU_SLEEP_1 116 &CLUSTER_SLEEP_0>; 117 next-level-cache = <&L2_200>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 #cooling-cells = <2>; 120 L2_200: l2-cache { 121 compatible = "cache"; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "arm,kryo"; 129 reg = <0x0 0x300>; 130 enable-method = "psci"; 131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 132 &LITTLE_CPU_SLEEP_1 133 &CLUSTER_SLEEP_0>; 134 next-level-cache = <&L2_300>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 #cooling-cells = <2>; 137 L2_300: l2-cache { 138 compatible = "cache"; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU4: cpu@400 { 144 device_type = "cpu"; 145 compatible = "arm,kryo"; 146 reg = <0x0 0x400>; 147 enable-method = "psci"; 148 cpu-idle-states = <&BIG_CPU_SLEEP_0 149 &BIG_CPU_SLEEP_1 150 &CLUSTER_SLEEP_0>; 151 next-level-cache = <&L2_400>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 #cooling-cells = <2>; 154 L2_400: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 160 CPU5: cpu@500 { 161 device_type = "cpu"; 162 compatible = "arm,kryo"; 163 reg = <0x0 0x500>; 164 enable-method = "psci"; 165 cpu-idle-states = <&BIG_CPU_SLEEP_0 166 &BIG_CPU_SLEEP_1 167 &CLUSTER_SLEEP_0>; 168 next-level-cache = <&L2_500>; 169 qcom,freq-domain = <&cpufreq_hw 1>; 170 #cooling-cells = <2>; 171 L2_500: l2-cache { 172 compatible = "cache"; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU6: cpu@600 { 178 device_type = "cpu"; 179 compatible = "arm,kryo"; 180 reg = <0x0 0x600>; 181 enable-method = "psci"; 182 cpu-idle-states = <&BIG_CPU_SLEEP_0 183 &BIG_CPU_SLEEP_1 184 &CLUSTER_SLEEP_0>; 185 next-level-cache = <&L2_600>; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 #cooling-cells = <2>; 188 L2_600: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "arm,kryo"; 197 reg = <0x0 0x700>; 198 enable-method = "psci"; 199 cpu-idle-states = <&BIG_CPU_SLEEP_0 200 &BIG_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 next-level-cache = <&L2_700>; 203 qcom,freq-domain = <&cpufreq_hw 1>; 204 #cooling-cells = <2>; 205 L2_700: l2-cache { 206 compatible = "cache"; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 215 compatible = "arm,idle-state"; 216 idle-state-name = "little-power-down"; 217 arm,psci-suspend-param = <0x40000003>; 218 entry-latency-us = <549>; 219 exit-latency-us = <901>; 220 min-residency-us = <1774>; 221 local-timer-stop; 222 }; 223 224 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 225 compatible = "arm,idle-state"; 226 idle-state-name = "little-rail-power-down"; 227 arm,psci-suspend-param = <0x40000004>; 228 entry-latency-us = <702>; 229 exit-latency-us = <915>; 230 min-residency-us = <4001>; 231 local-timer-stop; 232 }; 233 234 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 235 compatible = "arm,idle-state"; 236 idle-state-name = "big-power-down"; 237 arm,psci-suspend-param = <0x40000003>; 238 entry-latency-us = <523>; 239 exit-latency-us = <1244>; 240 min-residency-us = <2207>; 241 local-timer-stop; 242 }; 243 244 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 245 compatible = "arm,idle-state"; 246 idle-state-name = "big-rail-power-down"; 247 arm,psci-suspend-param = <0x40000004>; 248 entry-latency-us = <526>; 249 exit-latency-us = <1854>; 250 min-residency-us = <5555>; 251 local-timer-stop; 252 }; 253 254 CLUSTER_SLEEP_0: cluster-sleep-0 { 255 compatible = "arm,idle-state"; 256 idle-state-name = "cluster-power-down"; 257 arm,psci-suspend-param = <0x40003444>; 258 entry-latency-us = <3263>; 259 exit-latency-us = <6562>; 260 min-residency-us = <9926>; 261 local-timer-stop; 262 }; 263 }; 264 }; 265 266 memory@80000000 { 267 device_type = "memory"; 268 /* We expect the bootloader to fill in the size */ 269 reg = <0 0x80000000 0 0>; 270 }; 271 272 firmware { 273 scm { 274 compatible = "qcom,scm-sc7280", "qcom,scm"; 275 }; 276 }; 277 278 clk_virt: interconnect { 279 compatible = "qcom,sc7280-clk-virt"; 280 #interconnect-cells = <2>; 281 qcom,bcm-voters = <&apps_bcm_voter>; 282 }; 283 284 smem { 285 compatible = "qcom,smem"; 286 memory-region = <&smem_mem>; 287 hwlocks = <&tcsr_mutex 3>; 288 }; 289 290 smp2p-adsp { 291 compatible = "qcom,smp2p"; 292 qcom,smem = <443>, <429>; 293 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 294 IPCC_MPROC_SIGNAL_SMP2P 295 IRQ_TYPE_EDGE_RISING>; 296 mboxes = <&ipcc IPCC_CLIENT_LPASS 297 IPCC_MPROC_SIGNAL_SMP2P>; 298 299 qcom,local-pid = <0>; 300 qcom,remote-pid = <2>; 301 302 adsp_smp2p_out: master-kernel { 303 qcom,entry-name = "master-kernel"; 304 #qcom,smem-state-cells = <1>; 305 }; 306 307 adsp_smp2p_in: slave-kernel { 308 qcom,entry-name = "slave-kernel"; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 }; 312 }; 313 314 smp2p-cdsp { 315 compatible = "qcom,smp2p"; 316 qcom,smem = <94>, <432>; 317 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 318 IPCC_MPROC_SIGNAL_SMP2P 319 IRQ_TYPE_EDGE_RISING>; 320 mboxes = <&ipcc IPCC_CLIENT_CDSP 321 IPCC_MPROC_SIGNAL_SMP2P>; 322 323 qcom,local-pid = <0>; 324 qcom,remote-pid = <5>; 325 326 cdsp_smp2p_out: master-kernel { 327 qcom,entry-name = "master-kernel"; 328 #qcom,smem-state-cells = <1>; 329 }; 330 331 cdsp_smp2p_in: slave-kernel { 332 qcom,entry-name = "slave-kernel"; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 }; 336 }; 337 338 smp2p-mpss { 339 compatible = "qcom,smp2p"; 340 qcom,smem = <435>, <428>; 341 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 342 IPCC_MPROC_SIGNAL_SMP2P 343 IRQ_TYPE_EDGE_RISING>; 344 mboxes = <&ipcc IPCC_CLIENT_MPSS 345 IPCC_MPROC_SIGNAL_SMP2P>; 346 347 qcom,local-pid = <0>; 348 qcom,remote-pid = <1>; 349 350 modem_smp2p_out: master-kernel { 351 qcom,entry-name = "master-kernel"; 352 #qcom,smem-state-cells = <1>; 353 }; 354 355 modem_smp2p_in: slave-kernel { 356 qcom,entry-name = "slave-kernel"; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 ipa_smp2p_out: ipa-ap-to-modem { 362 qcom,entry-name = "ipa"; 363 #qcom,smem-state-cells = <1>; 364 }; 365 366 ipa_smp2p_in: ipa-modem-to-ap { 367 qcom,entry-name = "ipa"; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 }; 372 373 smp2p-wpss { 374 compatible = "qcom,smp2p"; 375 qcom,smem = <617>, <616>; 376 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 377 IPCC_MPROC_SIGNAL_SMP2P 378 IRQ_TYPE_EDGE_RISING>; 379 mboxes = <&ipcc IPCC_CLIENT_WPSS 380 IPCC_MPROC_SIGNAL_SMP2P>; 381 382 qcom,local-pid = <0>; 383 qcom,remote-pid = <13>; 384 385 wpss_smp2p_out: master-kernel { 386 qcom,entry-name = "master-kernel"; 387 #qcom,smem-state-cells = <1>; 388 }; 389 390 wpss_smp2p_in: slave-kernel { 391 qcom,entry-name = "slave-kernel"; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 }; 395 }; 396 397 pmu { 398 compatible = "arm,armv8-pmuv3"; 399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 400 }; 401 402 psci { 403 compatible = "arm,psci-1.0"; 404 method = "smc"; 405 }; 406 407 soc: soc@0 { 408 #address-cells = <2>; 409 #size-cells = <2>; 410 ranges = <0 0 0 0 0x10 0>; 411 dma-ranges = <0 0 0 0 0x10 0>; 412 compatible = "simple-bus"; 413 414 gcc: clock-controller@100000 { 415 compatible = "qcom,gcc-sc7280"; 416 reg = <0 0x00100000 0 0x1f0000>; 417 clocks = <&rpmhcc RPMH_CXO_CLK>, 418 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 419 <0>, <0>, <0>, <0>, <0>, <0>; 420 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 421 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 422 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 423 "ufs_phy_tx_symbol_0_clk", 424 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 425 #clock-cells = <1>; 426 #reset-cells = <1>; 427 #power-domain-cells = <1>; 428 }; 429 430 ipcc: mailbox@408000 { 431 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 432 reg = <0 0x00408000 0 0x1000>; 433 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-controller; 435 #interrupt-cells = <3>; 436 #mbox-cells = <2>; 437 }; 438 439 qupv3_id_0: geniqup@9c0000 { 440 compatible = "qcom,geni-se-qup"; 441 reg = <0 0x009c0000 0 0x2000>; 442 clock-names = "m-ahb", "s-ahb"; 443 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 444 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 445 #address-cells = <2>; 446 #size-cells = <2>; 447 ranges; 448 status = "disabled"; 449 450 uart5: serial@994000 { 451 compatible = "qcom,geni-debug-uart"; 452 reg = <0 0x00994000 0 0x4000>; 453 clock-names = "se"; 454 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&qup_uart5_default>; 457 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 458 status = "disabled"; 459 }; 460 }; 461 462 cnoc2: interconnect@1500000 { 463 reg = <0 0x01500000 0 0x1000>; 464 compatible = "qcom,sc7280-cnoc2"; 465 #interconnect-cells = <2>; 466 qcom,bcm-voters = <&apps_bcm_voter>; 467 }; 468 469 cnoc3: interconnect@1502000 { 470 reg = <0 0x01502000 0 0x1000>; 471 compatible = "qcom,sc7280-cnoc3"; 472 #interconnect-cells = <2>; 473 qcom,bcm-voters = <&apps_bcm_voter>; 474 }; 475 476 mc_virt: interconnect@1580000 { 477 reg = <0 0x01580000 0 0x4>; 478 compatible = "qcom,sc7280-mc-virt"; 479 #interconnect-cells = <2>; 480 qcom,bcm-voters = <&apps_bcm_voter>; 481 }; 482 483 system_noc: interconnect@1680000 { 484 reg = <0 0x01680000 0 0x15480>; 485 compatible = "qcom,sc7280-system-noc"; 486 #interconnect-cells = <2>; 487 qcom,bcm-voters = <&apps_bcm_voter>; 488 }; 489 490 aggre1_noc: interconnect@16e0000 { 491 compatible = "qcom,sc7280-aggre1-noc"; 492 reg = <0 0x016e0000 0 0x1c080>; 493 #interconnect-cells = <2>; 494 qcom,bcm-voters = <&apps_bcm_voter>; 495 }; 496 497 aggre2_noc: interconnect@1700000 { 498 reg = <0 0x01700000 0 0x2b080>; 499 compatible = "qcom,sc7280-aggre2-noc"; 500 #interconnect-cells = <2>; 501 qcom,bcm-voters = <&apps_bcm_voter>; 502 }; 503 504 mmss_noc: interconnect@1740000 { 505 reg = <0 0x01740000 0 0x1e080>; 506 compatible = "qcom,sc7280-mmss-noc"; 507 #interconnect-cells = <2>; 508 qcom,bcm-voters = <&apps_bcm_voter>; 509 }; 510 511 tcsr_mutex: hwlock@1f40000 { 512 compatible = "qcom,tcsr-mutex", "syscon"; 513 reg = <0 0x01f40000 0 0x40000>; 514 #hwlock-cells = <1>; 515 }; 516 517 lpasscc: lpasscc@3000000 { 518 compatible = "qcom,sc7280-lpasscc"; 519 reg = <0 0x03000000 0 0x40>, 520 <0 0x03c04000 0 0x4>, 521 <0 0x03389000 0 0x24>; 522 reg-names = "qdsp6ss", "top_cc", "cc"; 523 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 524 clock-names = "iface"; 525 #clock-cells = <1>; 526 }; 527 528 lpass_ag_noc: interconnect@3c40000 { 529 reg = <0 0x03c40000 0 0xf080>; 530 compatible = "qcom,sc7280-lpass-ag-noc"; 531 #interconnect-cells = <2>; 532 qcom,bcm-voters = <&apps_bcm_voter>; 533 }; 534 535 gpucc: clock-controller@3d90000 { 536 compatible = "qcom,sc7280-gpucc"; 537 reg = <0 0x03d90000 0 0x9000>; 538 clocks = <&rpmhcc RPMH_CXO_CLK>, 539 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 540 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 541 clock-names = "bi_tcxo", 542 "gcc_gpu_gpll0_clk_src", 543 "gcc_gpu_gpll0_div_clk_src"; 544 #clock-cells = <1>; 545 #reset-cells = <1>; 546 #power-domain-cells = <1>; 547 }; 548 549 stm@6002000 { 550 compatible = "arm,coresight-stm", "arm,primecell"; 551 reg = <0 0x06002000 0 0x1000>, 552 <0 0x16280000 0 0x180000>; 553 reg-names = "stm-base", "stm-stimulus-base"; 554 555 clocks = <&aoss_qmp>; 556 clock-names = "apb_pclk"; 557 558 out-ports { 559 port { 560 stm_out: endpoint { 561 remote-endpoint = <&funnel0_in7>; 562 }; 563 }; 564 }; 565 }; 566 567 funnel@6041000 { 568 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 569 reg = <0 0x06041000 0 0x1000>; 570 571 clocks = <&aoss_qmp>; 572 clock-names = "apb_pclk"; 573 574 out-ports { 575 port { 576 funnel0_out: endpoint { 577 remote-endpoint = <&merge_funnel_in0>; 578 }; 579 }; 580 }; 581 582 in-ports { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 586 port@7 { 587 reg = <7>; 588 funnel0_in7: endpoint { 589 remote-endpoint = <&stm_out>; 590 }; 591 }; 592 }; 593 }; 594 595 funnel@6042000 { 596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 597 reg = <0 0x06042000 0 0x1000>; 598 599 clocks = <&aoss_qmp>; 600 clock-names = "apb_pclk"; 601 602 out-ports { 603 port { 604 funnel1_out: endpoint { 605 remote-endpoint = <&merge_funnel_in1>; 606 }; 607 }; 608 }; 609 610 in-ports { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 614 port@4 { 615 reg = <4>; 616 funnel1_in4: endpoint { 617 remote-endpoint = <&apss_merge_funnel_out>; 618 }; 619 }; 620 }; 621 }; 622 623 funnel@6045000 { 624 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 625 reg = <0 0x06045000 0 0x1000>; 626 627 clocks = <&aoss_qmp>; 628 clock-names = "apb_pclk"; 629 630 out-ports { 631 port { 632 merge_funnel_out: endpoint { 633 remote-endpoint = <&swao_funnel_in>; 634 }; 635 }; 636 }; 637 638 in-ports { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 port@0 { 643 reg = <0>; 644 merge_funnel_in0: endpoint { 645 remote-endpoint = <&funnel0_out>; 646 }; 647 }; 648 649 port@1 { 650 reg = <1>; 651 merge_funnel_in1: endpoint { 652 remote-endpoint = <&funnel1_out>; 653 }; 654 }; 655 }; 656 }; 657 658 replicator@6046000 { 659 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 660 reg = <0 0x06046000 0 0x1000>; 661 662 clocks = <&aoss_qmp>; 663 clock-names = "apb_pclk"; 664 665 out-ports { 666 port { 667 replicator_out: endpoint { 668 remote-endpoint = <&etr_in>; 669 }; 670 }; 671 }; 672 673 in-ports { 674 port { 675 replicator_in: endpoint { 676 remote-endpoint = <&swao_replicator_out>; 677 }; 678 }; 679 }; 680 }; 681 682 etr@6048000 { 683 compatible = "arm,coresight-tmc", "arm,primecell"; 684 reg = <0 0x06048000 0 0x1000>; 685 iommus = <&apps_smmu 0x04c0 0>; 686 687 clocks = <&aoss_qmp>; 688 clock-names = "apb_pclk"; 689 arm,scatter-gather; 690 691 in-ports { 692 port { 693 etr_in: endpoint { 694 remote-endpoint = <&replicator_out>; 695 }; 696 }; 697 }; 698 }; 699 700 funnel@6b04000 { 701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 702 reg = <0 0x06b04000 0 0x1000>; 703 704 clocks = <&aoss_qmp>; 705 clock-names = "apb_pclk"; 706 707 out-ports { 708 port { 709 swao_funnel_out: endpoint { 710 remote-endpoint = <&etf_in>; 711 }; 712 }; 713 }; 714 715 in-ports { 716 #address-cells = <1>; 717 #size-cells = <0>; 718 719 port@7 { 720 reg = <7>; 721 swao_funnel_in: endpoint { 722 remote-endpoint = <&merge_funnel_out>; 723 }; 724 }; 725 }; 726 }; 727 728 etf@6b05000 { 729 compatible = "arm,coresight-tmc", "arm,primecell"; 730 reg = <0 0x06b05000 0 0x1000>; 731 732 clocks = <&aoss_qmp>; 733 clock-names = "apb_pclk"; 734 735 out-ports { 736 port { 737 etf_out: endpoint { 738 remote-endpoint = <&swao_replicator_in>; 739 }; 740 }; 741 }; 742 743 in-ports { 744 port { 745 etf_in: endpoint { 746 remote-endpoint = <&swao_funnel_out>; 747 }; 748 }; 749 }; 750 }; 751 752 replicator@6b06000 { 753 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 754 reg = <0 0x06b06000 0 0x1000>; 755 756 clocks = <&aoss_qmp>; 757 clock-names = "apb_pclk"; 758 qcom,replicator-loses-context; 759 760 out-ports { 761 port { 762 swao_replicator_out: endpoint { 763 remote-endpoint = <&replicator_in>; 764 }; 765 }; 766 }; 767 768 in-ports { 769 port { 770 swao_replicator_in: endpoint { 771 remote-endpoint = <&etf_out>; 772 }; 773 }; 774 }; 775 }; 776 777 etm@7040000 { 778 compatible = "arm,coresight-etm4x", "arm,primecell"; 779 reg = <0 0x07040000 0 0x1000>; 780 781 cpu = <&CPU0>; 782 783 clocks = <&aoss_qmp>; 784 clock-names = "apb_pclk"; 785 arm,coresight-loses-context-with-cpu; 786 qcom,skip-power-up; 787 788 out-ports { 789 port { 790 etm0_out: endpoint { 791 remote-endpoint = <&apss_funnel_in0>; 792 }; 793 }; 794 }; 795 }; 796 797 etm@7140000 { 798 compatible = "arm,coresight-etm4x", "arm,primecell"; 799 reg = <0 0x07140000 0 0x1000>; 800 801 cpu = <&CPU1>; 802 803 clocks = <&aoss_qmp>; 804 clock-names = "apb_pclk"; 805 arm,coresight-loses-context-with-cpu; 806 qcom,skip-power-up; 807 808 out-ports { 809 port { 810 etm1_out: endpoint { 811 remote-endpoint = <&apss_funnel_in1>; 812 }; 813 }; 814 }; 815 }; 816 817 etm@7240000 { 818 compatible = "arm,coresight-etm4x", "arm,primecell"; 819 reg = <0 0x07240000 0 0x1000>; 820 821 cpu = <&CPU2>; 822 823 clocks = <&aoss_qmp>; 824 clock-names = "apb_pclk"; 825 arm,coresight-loses-context-with-cpu; 826 qcom,skip-power-up; 827 828 out-ports { 829 port { 830 etm2_out: endpoint { 831 remote-endpoint = <&apss_funnel_in2>; 832 }; 833 }; 834 }; 835 }; 836 837 etm@7340000 { 838 compatible = "arm,coresight-etm4x", "arm,primecell"; 839 reg = <0 0x07340000 0 0x1000>; 840 841 cpu = <&CPU3>; 842 843 clocks = <&aoss_qmp>; 844 clock-names = "apb_pclk"; 845 arm,coresight-loses-context-with-cpu; 846 qcom,skip-power-up; 847 848 out-ports { 849 port { 850 etm3_out: endpoint { 851 remote-endpoint = <&apss_funnel_in3>; 852 }; 853 }; 854 }; 855 }; 856 857 etm@7440000 { 858 compatible = "arm,coresight-etm4x", "arm,primecell"; 859 reg = <0 0x07440000 0 0x1000>; 860 861 cpu = <&CPU4>; 862 863 clocks = <&aoss_qmp>; 864 clock-names = "apb_pclk"; 865 arm,coresight-loses-context-with-cpu; 866 qcom,skip-power-up; 867 868 out-ports { 869 port { 870 etm4_out: endpoint { 871 remote-endpoint = <&apss_funnel_in4>; 872 }; 873 }; 874 }; 875 }; 876 877 etm@7540000 { 878 compatible = "arm,coresight-etm4x", "arm,primecell"; 879 reg = <0 0x07540000 0 0x1000>; 880 881 cpu = <&CPU5>; 882 883 clocks = <&aoss_qmp>; 884 clock-names = "apb_pclk"; 885 arm,coresight-loses-context-with-cpu; 886 qcom,skip-power-up; 887 888 out-ports { 889 port { 890 etm5_out: endpoint { 891 remote-endpoint = <&apss_funnel_in5>; 892 }; 893 }; 894 }; 895 }; 896 897 etm@7640000 { 898 compatible = "arm,coresight-etm4x", "arm,primecell"; 899 reg = <0 0x07640000 0 0x1000>; 900 901 cpu = <&CPU6>; 902 903 clocks = <&aoss_qmp>; 904 clock-names = "apb_pclk"; 905 arm,coresight-loses-context-with-cpu; 906 qcom,skip-power-up; 907 908 out-ports { 909 port { 910 etm6_out: endpoint { 911 remote-endpoint = <&apss_funnel_in6>; 912 }; 913 }; 914 }; 915 }; 916 917 etm@7740000 { 918 compatible = "arm,coresight-etm4x", "arm,primecell"; 919 reg = <0 0x07740000 0 0x1000>; 920 921 cpu = <&CPU7>; 922 923 clocks = <&aoss_qmp>; 924 clock-names = "apb_pclk"; 925 arm,coresight-loses-context-with-cpu; 926 qcom,skip-power-up; 927 928 out-ports { 929 port { 930 etm7_out: endpoint { 931 remote-endpoint = <&apss_funnel_in7>; 932 }; 933 }; 934 }; 935 }; 936 937 funnel@7800000 { /* APSS Funnel */ 938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 939 reg = <0 0x07800000 0 0x1000>; 940 941 clocks = <&aoss_qmp>; 942 clock-names = "apb_pclk"; 943 944 out-ports { 945 port { 946 apss_funnel_out: endpoint { 947 remote-endpoint = <&apss_merge_funnel_in>; 948 }; 949 }; 950 }; 951 952 in-ports { 953 #address-cells = <1>; 954 #size-cells = <0>; 955 956 port@0 { 957 reg = <0>; 958 apss_funnel_in0: endpoint { 959 remote-endpoint = <&etm0_out>; 960 }; 961 }; 962 963 port@1 { 964 reg = <1>; 965 apss_funnel_in1: endpoint { 966 remote-endpoint = <&etm1_out>; 967 }; 968 }; 969 970 port@2 { 971 reg = <2>; 972 apss_funnel_in2: endpoint { 973 remote-endpoint = <&etm2_out>; 974 }; 975 }; 976 977 port@3 { 978 reg = <3>; 979 apss_funnel_in3: endpoint { 980 remote-endpoint = <&etm3_out>; 981 }; 982 }; 983 984 port@4 { 985 reg = <4>; 986 apss_funnel_in4: endpoint { 987 remote-endpoint = <&etm4_out>; 988 }; 989 }; 990 991 port@5 { 992 reg = <5>; 993 apss_funnel_in5: endpoint { 994 remote-endpoint = <&etm5_out>; 995 }; 996 }; 997 998 port@6 { 999 reg = <6>; 1000 apss_funnel_in6: endpoint { 1001 remote-endpoint = <&etm6_out>; 1002 }; 1003 }; 1004 1005 port@7 { 1006 reg = <7>; 1007 apss_funnel_in7: endpoint { 1008 remote-endpoint = <&etm7_out>; 1009 }; 1010 }; 1011 }; 1012 }; 1013 1014 funnel@7810000 { 1015 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1016 reg = <0 0x07810000 0 0x1000>; 1017 1018 clocks = <&aoss_qmp>; 1019 clock-names = "apb_pclk"; 1020 1021 out-ports { 1022 port { 1023 apss_merge_funnel_out: endpoint { 1024 remote-endpoint = <&funnel1_in4>; 1025 }; 1026 }; 1027 }; 1028 1029 in-ports { 1030 port { 1031 apss_merge_funnel_in: endpoint { 1032 remote-endpoint = <&apss_funnel_out>; 1033 }; 1034 }; 1035 }; 1036 }; 1037 1038 dc_noc: interconnect@90e0000 { 1039 reg = <0 0x090e0000 0 0x5080>; 1040 compatible = "qcom,sc7280-dc-noc"; 1041 #interconnect-cells = <2>; 1042 qcom,bcm-voters = <&apps_bcm_voter>; 1043 }; 1044 1045 gem_noc: interconnect@9100000 { 1046 reg = <0 0x9100000 0 0xe2200>; 1047 compatible = "qcom,sc7280-gem-noc"; 1048 #interconnect-cells = <2>; 1049 qcom,bcm-voters = <&apps_bcm_voter>; 1050 }; 1051 1052 system-cache-controller@9200000 { 1053 compatible = "qcom,sc7280-llcc"; 1054 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1055 reg-names = "llcc_base", "llcc_broadcast_base"; 1056 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1057 }; 1058 1059 nsp_noc: interconnect@a0c0000 { 1060 reg = <0 0x0a0c0000 0 0x10000>; 1061 compatible = "qcom,sc7280-nsp-noc"; 1062 #interconnect-cells = <2>; 1063 qcom,bcm-voters = <&apps_bcm_voter>; 1064 }; 1065 1066 videocc: clock-controller@aaf0000 { 1067 compatible = "qcom,sc7280-videocc"; 1068 reg = <0 0xaaf0000 0 0x10000>; 1069 clocks = <&rpmhcc RPMH_CXO_CLK>, 1070 <&rpmhcc RPMH_CXO_CLK_A>; 1071 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1072 #clock-cells = <1>; 1073 #reset-cells = <1>; 1074 #power-domain-cells = <1>; 1075 }; 1076 1077 dispcc: clock-controller@af00000 { 1078 compatible = "qcom,sc7280-dispcc"; 1079 reg = <0 0xaf00000 0 0x20000>; 1080 clocks = <&rpmhcc RPMH_CXO_CLK>, 1081 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1082 <0>, <0>, <0>, <0>, <0>, <0>; 1083 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1084 "dsi0_phy_pll_out_byteclk", 1085 "dsi0_phy_pll_out_dsiclk", 1086 "dp_phy_pll_link_clk", 1087 "dp_phy_pll_vco_div_clk", 1088 "edp_phy_pll_link_clk", 1089 "edp_phy_pll_vco_div_clk"; 1090 #clock-cells = <1>; 1091 #reset-cells = <1>; 1092 #power-domain-cells = <1>; 1093 }; 1094 1095 pdc: interrupt-controller@b220000 { 1096 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1097 reg = <0 0x0b220000 0 0x30000>; 1098 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1099 <55 306 4>, <59 312 3>, <62 374 2>, 1100 <64 434 2>, <66 438 3>, <69 86 1>, 1101 <70 520 54>, <124 609 31>, <155 63 1>, 1102 <156 716 12>; 1103 #interrupt-cells = <2>; 1104 interrupt-parent = <&intc>; 1105 interrupt-controller; 1106 }; 1107 1108 pdc_reset: reset-controller@b5e0000 { 1109 compatible = "qcom,sc7280-pdc-global"; 1110 reg = <0 0x0b5e0000 0 0x20000>; 1111 #reset-cells = <1>; 1112 }; 1113 1114 tsens0: thermal-sensor@c263000 { 1115 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1116 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1117 <0 0x0c222000 0 0x1ff>; /* SROT */ 1118 #qcom,sensors = <15>; 1119 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1121 interrupt-names = "uplow","critical"; 1122 #thermal-sensor-cells = <1>; 1123 }; 1124 1125 tsens1: thermal-sensor@c265000 { 1126 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1127 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1128 <0 0x0c223000 0 0x1ff>; /* SROT */ 1129 #qcom,sensors = <12>; 1130 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1132 interrupt-names = "uplow","critical"; 1133 #thermal-sensor-cells = <1>; 1134 }; 1135 1136 aoss_reset: reset-controller@c2a0000 { 1137 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1138 reg = <0 0x0c2a0000 0 0x31000>; 1139 #reset-cells = <1>; 1140 }; 1141 1142 aoss_qmp: power-controller@c300000 { 1143 compatible = "qcom,sc7280-aoss-qmp"; 1144 reg = <0 0x0c300000 0 0x100000>; 1145 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1146 IPCC_MPROC_SIGNAL_GLINK_QMP 1147 IRQ_TYPE_EDGE_RISING>; 1148 mboxes = <&ipcc IPCC_CLIENT_AOP 1149 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1150 1151 #clock-cells = <0>; 1152 #power-domain-cells = <1>; 1153 }; 1154 1155 spmi_bus: spmi@c440000 { 1156 compatible = "qcom,spmi-pmic-arb"; 1157 reg = <0 0x0c440000 0 0x1100>, 1158 <0 0x0c600000 0 0x2000000>, 1159 <0 0x0e600000 0 0x100000>, 1160 <0 0x0e700000 0 0xa0000>, 1161 <0 0x0c40a000 0 0x26000>; 1162 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1163 interrupt-names = "periph_irq"; 1164 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1165 qcom,ee = <0>; 1166 qcom,channel = <0>; 1167 #address-cells = <1>; 1168 #size-cells = <1>; 1169 interrupt-controller; 1170 #interrupt-cells = <4>; 1171 }; 1172 1173 tlmm: pinctrl@f100000 { 1174 compatible = "qcom,sc7280-pinctrl"; 1175 reg = <0 0x0f100000 0 0x300000>; 1176 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1177 gpio-controller; 1178 #gpio-cells = <2>; 1179 interrupt-controller; 1180 #interrupt-cells = <2>; 1181 gpio-ranges = <&tlmm 0 0 175>; 1182 wakeup-parent = <&pdc>; 1183 1184 qup_uart5_default: qup-uart5-default { 1185 pins = "gpio46", "gpio47"; 1186 function = "qup13"; 1187 }; 1188 }; 1189 1190 apps_smmu: iommu@15000000 { 1191 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1192 reg = <0 0x15000000 0 0x100000>; 1193 #iommu-cells = <2>; 1194 #global-interrupts = <1>; 1195 dma-coherent; 1196 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1277 }; 1278 1279 intc: interrupt-controller@17a00000 { 1280 compatible = "arm,gic-v3"; 1281 #address-cells = <2>; 1282 #size-cells = <2>; 1283 ranges; 1284 #interrupt-cells = <3>; 1285 interrupt-controller; 1286 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1287 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1288 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1289 1290 gic-its@17a40000 { 1291 compatible = "arm,gic-v3-its"; 1292 msi-controller; 1293 #msi-cells = <1>; 1294 reg = <0 0x17a40000 0 0x20000>; 1295 status = "disabled"; 1296 }; 1297 }; 1298 1299 watchdog@17c10000 { 1300 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1301 reg = <0 0x17c10000 0 0x1000>; 1302 clocks = <&sleep_clk>; 1303 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1304 }; 1305 1306 timer@17c20000 { 1307 #address-cells = <2>; 1308 #size-cells = <2>; 1309 ranges; 1310 compatible = "arm,armv7-timer-mem"; 1311 reg = <0 0x17c20000 0 0x1000>; 1312 1313 frame@17c21000 { 1314 frame-number = <0>; 1315 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1317 reg = <0 0x17c21000 0 0x1000>, 1318 <0 0x17c22000 0 0x1000>; 1319 }; 1320 1321 frame@17c23000 { 1322 frame-number = <1>; 1323 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1324 reg = <0 0x17c23000 0 0x1000>; 1325 status = "disabled"; 1326 }; 1327 1328 frame@17c25000 { 1329 frame-number = <2>; 1330 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1331 reg = <0 0x17c25000 0 0x1000>; 1332 status = "disabled"; 1333 }; 1334 1335 frame@17c27000 { 1336 frame-number = <3>; 1337 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1338 reg = <0 0x17c27000 0 0x1000>; 1339 status = "disabled"; 1340 }; 1341 1342 frame@17c29000 { 1343 frame-number = <4>; 1344 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1345 reg = <0 0x17c29000 0 0x1000>; 1346 status = "disabled"; 1347 }; 1348 1349 frame@17c2b000 { 1350 frame-number = <5>; 1351 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1352 reg = <0 0x17c2b000 0 0x1000>; 1353 status = "disabled"; 1354 }; 1355 1356 frame@17c2d000 { 1357 frame-number = <6>; 1358 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1359 reg = <0 0x17c2d000 0 0x1000>; 1360 status = "disabled"; 1361 }; 1362 }; 1363 1364 apps_rsc: rsc@18200000 { 1365 compatible = "qcom,rpmh-rsc"; 1366 reg = <0 0x18200000 0 0x10000>, 1367 <0 0x18210000 0 0x10000>, 1368 <0 0x18220000 0 0x10000>; 1369 reg-names = "drv-0", "drv-1", "drv-2"; 1370 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1373 qcom,tcs-offset = <0xd00>; 1374 qcom,drv-id = <2>; 1375 qcom,tcs-config = <ACTIVE_TCS 2>, 1376 <SLEEP_TCS 3>, 1377 <WAKE_TCS 3>, 1378 <CONTROL_TCS 1>; 1379 1380 apps_bcm_voter: bcm-voter { 1381 compatible = "qcom,bcm-voter"; 1382 }; 1383 1384 rpmhpd: power-controller { 1385 compatible = "qcom,sc7280-rpmhpd"; 1386 #power-domain-cells = <1>; 1387 operating-points-v2 = <&rpmhpd_opp_table>; 1388 1389 rpmhpd_opp_table: opp-table { 1390 compatible = "operating-points-v2"; 1391 1392 rpmhpd_opp_ret: opp1 { 1393 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1394 }; 1395 1396 rpmhpd_opp_low_svs: opp2 { 1397 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1398 }; 1399 1400 rpmhpd_opp_svs: opp3 { 1401 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1402 }; 1403 1404 rpmhpd_opp_svs_l1: opp4 { 1405 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1406 }; 1407 1408 rpmhpd_opp_svs_l2: opp5 { 1409 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1410 }; 1411 1412 rpmhpd_opp_nom: opp6 { 1413 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1414 }; 1415 1416 rpmhpd_opp_nom_l1: opp7 { 1417 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1418 }; 1419 1420 rpmhpd_opp_turbo: opp8 { 1421 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1422 }; 1423 1424 rpmhpd_opp_turbo_l1: opp9 { 1425 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1426 }; 1427 }; 1428 }; 1429 1430 rpmhcc: clock-controller { 1431 compatible = "qcom,sc7280-rpmh-clk"; 1432 clocks = <&xo_board>; 1433 clock-names = "xo"; 1434 #clock-cells = <1>; 1435 }; 1436 }; 1437 1438 cpufreq_hw: cpufreq@18591000 { 1439 compatible = "qcom,cpufreq-epss"; 1440 reg = <0 0x18591000 0 0x1000>, 1441 <0 0x18592000 0 0x1000>, 1442 <0 0x18593000 0 0x1000>; 1443 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1444 clock-names = "xo", "alternate"; 1445 #freq-domain-cells = <1>; 1446 }; 1447 }; 1448 1449 thermal_zones: thermal-zones { 1450 cpu0-thermal { 1451 polling-delay-passive = <250>; 1452 polling-delay = <0>; 1453 1454 thermal-sensors = <&tsens0 1>; 1455 1456 trips { 1457 cpu0_alert0: trip-point0 { 1458 temperature = <90000>; 1459 hysteresis = <2000>; 1460 type = "passive"; 1461 }; 1462 1463 cpu0_alert1: trip-point1 { 1464 temperature = <95000>; 1465 hysteresis = <2000>; 1466 type = "passive"; 1467 }; 1468 1469 cpu0_crit: cpu-crit { 1470 temperature = <110000>; 1471 hysteresis = <0>; 1472 type = "critical"; 1473 }; 1474 }; 1475 1476 cooling-maps { 1477 map0 { 1478 trip = <&cpu0_alert0>; 1479 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1480 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1481 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1482 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1483 }; 1484 map1 { 1485 trip = <&cpu0_alert1>; 1486 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1487 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1488 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1489 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1490 }; 1491 }; 1492 }; 1493 1494 cpu1-thermal { 1495 polling-delay-passive = <250>; 1496 polling-delay = <0>; 1497 1498 thermal-sensors = <&tsens0 2>; 1499 1500 trips { 1501 cpu1_alert0: trip-point0 { 1502 temperature = <90000>; 1503 hysteresis = <2000>; 1504 type = "passive"; 1505 }; 1506 1507 cpu1_alert1: trip-point1 { 1508 temperature = <95000>; 1509 hysteresis = <2000>; 1510 type = "passive"; 1511 }; 1512 1513 cpu1_crit: cpu-crit { 1514 temperature = <110000>; 1515 hysteresis = <0>; 1516 type = "critical"; 1517 }; 1518 }; 1519 1520 cooling-maps { 1521 map0 { 1522 trip = <&cpu1_alert0>; 1523 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1524 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1525 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1526 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1527 }; 1528 map1 { 1529 trip = <&cpu1_alert1>; 1530 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1531 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1532 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1533 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1534 }; 1535 }; 1536 }; 1537 1538 cpu2-thermal { 1539 polling-delay-passive = <250>; 1540 polling-delay = <0>; 1541 1542 thermal-sensors = <&tsens0 3>; 1543 1544 trips { 1545 cpu2_alert0: trip-point0 { 1546 temperature = <90000>; 1547 hysteresis = <2000>; 1548 type = "passive"; 1549 }; 1550 1551 cpu2_alert1: trip-point1 { 1552 temperature = <95000>; 1553 hysteresis = <2000>; 1554 type = "passive"; 1555 }; 1556 1557 cpu2_crit: cpu-crit { 1558 temperature = <110000>; 1559 hysteresis = <0>; 1560 type = "critical"; 1561 }; 1562 }; 1563 1564 cooling-maps { 1565 map0 { 1566 trip = <&cpu2_alert0>; 1567 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1568 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1569 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1570 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1571 }; 1572 map1 { 1573 trip = <&cpu2_alert1>; 1574 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1575 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1576 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1577 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1578 }; 1579 }; 1580 }; 1581 1582 cpu3-thermal { 1583 polling-delay-passive = <250>; 1584 polling-delay = <0>; 1585 1586 thermal-sensors = <&tsens0 4>; 1587 1588 trips { 1589 cpu3_alert0: trip-point0 { 1590 temperature = <90000>; 1591 hysteresis = <2000>; 1592 type = "passive"; 1593 }; 1594 1595 cpu3_alert1: trip-point1 { 1596 temperature = <95000>; 1597 hysteresis = <2000>; 1598 type = "passive"; 1599 }; 1600 1601 cpu3_crit: cpu-crit { 1602 temperature = <110000>; 1603 hysteresis = <0>; 1604 type = "critical"; 1605 }; 1606 }; 1607 1608 cooling-maps { 1609 map0 { 1610 trip = <&cpu3_alert0>; 1611 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1612 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1613 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1614 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1615 }; 1616 map1 { 1617 trip = <&cpu3_alert1>; 1618 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1619 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1620 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1621 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1622 }; 1623 }; 1624 }; 1625 1626 cpu4-thermal { 1627 polling-delay-passive = <250>; 1628 polling-delay = <0>; 1629 1630 thermal-sensors = <&tsens0 7>; 1631 1632 trips { 1633 cpu4_alert0: trip-point0 { 1634 temperature = <90000>; 1635 hysteresis = <2000>; 1636 type = "passive"; 1637 }; 1638 1639 cpu4_alert1: trip-point1 { 1640 temperature = <95000>; 1641 hysteresis = <2000>; 1642 type = "passive"; 1643 }; 1644 1645 cpu4_crit: cpu-crit { 1646 temperature = <110000>; 1647 hysteresis = <0>; 1648 type = "critical"; 1649 }; 1650 }; 1651 1652 cooling-maps { 1653 map0 { 1654 trip = <&cpu4_alert0>; 1655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1659 }; 1660 map1 { 1661 trip = <&cpu4_alert1>; 1662 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1663 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1664 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1665 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1666 }; 1667 }; 1668 }; 1669 1670 cpu5-thermal { 1671 polling-delay-passive = <250>; 1672 polling-delay = <0>; 1673 1674 thermal-sensors = <&tsens0 8>; 1675 1676 trips { 1677 cpu5_alert0: trip-point0 { 1678 temperature = <90000>; 1679 hysteresis = <2000>; 1680 type = "passive"; 1681 }; 1682 1683 cpu5_alert1: trip-point1 { 1684 temperature = <95000>; 1685 hysteresis = <2000>; 1686 type = "passive"; 1687 }; 1688 1689 cpu5_crit: cpu-crit { 1690 temperature = <110000>; 1691 hysteresis = <0>; 1692 type = "critical"; 1693 }; 1694 }; 1695 1696 cooling-maps { 1697 map0 { 1698 trip = <&cpu5_alert0>; 1699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1703 }; 1704 map1 { 1705 trip = <&cpu5_alert1>; 1706 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1707 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1708 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1709 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1710 }; 1711 }; 1712 }; 1713 1714 cpu6-thermal { 1715 polling-delay-passive = <250>; 1716 polling-delay = <0>; 1717 1718 thermal-sensors = <&tsens0 9>; 1719 1720 trips { 1721 cpu6_alert0: trip-point0 { 1722 temperature = <90000>; 1723 hysteresis = <2000>; 1724 type = "passive"; 1725 }; 1726 1727 cpu6_alert1: trip-point1 { 1728 temperature = <95000>; 1729 hysteresis = <2000>; 1730 type = "passive"; 1731 }; 1732 1733 cpu6_crit: cpu-crit { 1734 temperature = <110000>; 1735 hysteresis = <0>; 1736 type = "critical"; 1737 }; 1738 }; 1739 1740 cooling-maps { 1741 map0 { 1742 trip = <&cpu6_alert0>; 1743 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1744 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1745 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1746 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1747 }; 1748 map1 { 1749 trip = <&cpu6_alert1>; 1750 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1751 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1752 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1753 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1754 }; 1755 }; 1756 }; 1757 1758 cpu7-thermal { 1759 polling-delay-passive = <250>; 1760 polling-delay = <0>; 1761 1762 thermal-sensors = <&tsens0 10>; 1763 1764 trips { 1765 cpu7_alert0: trip-point0 { 1766 temperature = <90000>; 1767 hysteresis = <2000>; 1768 type = "passive"; 1769 }; 1770 1771 cpu7_alert1: trip-point1 { 1772 temperature = <95000>; 1773 hysteresis = <2000>; 1774 type = "passive"; 1775 }; 1776 1777 cpu7_crit: cpu-crit { 1778 temperature = <110000>; 1779 hysteresis = <0>; 1780 type = "critical"; 1781 }; 1782 }; 1783 1784 cooling-maps { 1785 map0 { 1786 trip = <&cpu7_alert0>; 1787 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1788 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1789 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1790 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1791 }; 1792 map1 { 1793 trip = <&cpu7_alert1>; 1794 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1795 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1796 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1797 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1798 }; 1799 }; 1800 }; 1801 1802 cpu8-thermal { 1803 polling-delay-passive = <250>; 1804 polling-delay = <0>; 1805 1806 thermal-sensors = <&tsens0 11>; 1807 1808 trips { 1809 cpu8_alert0: trip-point0 { 1810 temperature = <90000>; 1811 hysteresis = <2000>; 1812 type = "passive"; 1813 }; 1814 1815 cpu8_alert1: trip-point1 { 1816 temperature = <95000>; 1817 hysteresis = <2000>; 1818 type = "passive"; 1819 }; 1820 1821 cpu8_crit: cpu-crit { 1822 temperature = <110000>; 1823 hysteresis = <0>; 1824 type = "critical"; 1825 }; 1826 }; 1827 1828 cooling-maps { 1829 map0 { 1830 trip = <&cpu8_alert0>; 1831 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1832 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1833 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1834 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1835 }; 1836 map1 { 1837 trip = <&cpu8_alert1>; 1838 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1839 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1840 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1841 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1842 }; 1843 }; 1844 }; 1845 1846 cpu9-thermal { 1847 polling-delay-passive = <250>; 1848 polling-delay = <0>; 1849 1850 thermal-sensors = <&tsens0 12>; 1851 1852 trips { 1853 cpu9_alert0: trip-point0 { 1854 temperature = <90000>; 1855 hysteresis = <2000>; 1856 type = "passive"; 1857 }; 1858 1859 cpu9_alert1: trip-point1 { 1860 temperature = <95000>; 1861 hysteresis = <2000>; 1862 type = "passive"; 1863 }; 1864 1865 cpu9_crit: cpu-crit { 1866 temperature = <110000>; 1867 hysteresis = <0>; 1868 type = "critical"; 1869 }; 1870 }; 1871 1872 cooling-maps { 1873 map0 { 1874 trip = <&cpu9_alert0>; 1875 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1877 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1878 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1879 }; 1880 map1 { 1881 trip = <&cpu9_alert1>; 1882 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1883 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1884 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1885 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1886 }; 1887 }; 1888 }; 1889 1890 cpu10-thermal { 1891 polling-delay-passive = <250>; 1892 polling-delay = <0>; 1893 1894 thermal-sensors = <&tsens0 13>; 1895 1896 trips { 1897 cpu10_alert0: trip-point0 { 1898 temperature = <90000>; 1899 hysteresis = <2000>; 1900 type = "passive"; 1901 }; 1902 1903 cpu10_alert1: trip-point1 { 1904 temperature = <95000>; 1905 hysteresis = <2000>; 1906 type = "passive"; 1907 }; 1908 1909 cpu10_crit: cpu-crit { 1910 temperature = <110000>; 1911 hysteresis = <0>; 1912 type = "critical"; 1913 }; 1914 }; 1915 1916 cooling-maps { 1917 map0 { 1918 trip = <&cpu10_alert0>; 1919 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1920 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1921 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1922 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1923 }; 1924 map1 { 1925 trip = <&cpu10_alert1>; 1926 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1927 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1928 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1929 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1930 }; 1931 }; 1932 }; 1933 1934 cpu11-thermal { 1935 polling-delay-passive = <250>; 1936 polling-delay = <0>; 1937 1938 thermal-sensors = <&tsens0 14>; 1939 1940 trips { 1941 cpu11_alert0: trip-point0 { 1942 temperature = <90000>; 1943 hysteresis = <2000>; 1944 type = "passive"; 1945 }; 1946 1947 cpu11_alert1: trip-point1 { 1948 temperature = <95000>; 1949 hysteresis = <2000>; 1950 type = "passive"; 1951 }; 1952 1953 cpu11_crit: cpu-crit { 1954 temperature = <110000>; 1955 hysteresis = <0>; 1956 type = "critical"; 1957 }; 1958 }; 1959 1960 cooling-maps { 1961 map0 { 1962 trip = <&cpu11_alert0>; 1963 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1964 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1965 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1966 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1967 }; 1968 map1 { 1969 trip = <&cpu11_alert1>; 1970 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1971 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1972 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1973 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1974 }; 1975 }; 1976 }; 1977 1978 aoss0-thermal { 1979 polling-delay-passive = <0>; 1980 polling-delay = <0>; 1981 1982 thermal-sensors = <&tsens0 0>; 1983 1984 trips { 1985 aoss0_alert0: trip-point0 { 1986 temperature = <90000>; 1987 hysteresis = <2000>; 1988 type = "hot"; 1989 }; 1990 1991 aoss0_crit: aoss0-crit { 1992 temperature = <110000>; 1993 hysteresis = <0>; 1994 type = "critical"; 1995 }; 1996 }; 1997 }; 1998 1999 aoss1-thermal { 2000 polling-delay-passive = <0>; 2001 polling-delay = <0>; 2002 2003 thermal-sensors = <&tsens1 0>; 2004 2005 trips { 2006 aoss1_alert0: trip-point0 { 2007 temperature = <90000>; 2008 hysteresis = <2000>; 2009 type = "hot"; 2010 }; 2011 2012 aoss1_crit: aoss1-crit { 2013 temperature = <110000>; 2014 hysteresis = <0>; 2015 type = "critical"; 2016 }; 2017 }; 2018 }; 2019 2020 cpuss0-thermal { 2021 polling-delay-passive = <0>; 2022 polling-delay = <0>; 2023 2024 thermal-sensors = <&tsens0 5>; 2025 2026 trips { 2027 cpuss0_alert0: trip-point0 { 2028 temperature = <90000>; 2029 hysteresis = <2000>; 2030 type = "hot"; 2031 }; 2032 cpuss0_crit: cluster0-crit { 2033 temperature = <110000>; 2034 hysteresis = <0>; 2035 type = "critical"; 2036 }; 2037 }; 2038 }; 2039 2040 cpuss1-thermal { 2041 polling-delay-passive = <0>; 2042 polling-delay = <0>; 2043 2044 thermal-sensors = <&tsens0 6>; 2045 2046 trips { 2047 cpuss1_alert0: trip-point0 { 2048 temperature = <90000>; 2049 hysteresis = <2000>; 2050 type = "hot"; 2051 }; 2052 cpuss1_crit: cluster0-crit { 2053 temperature = <110000>; 2054 hysteresis = <0>; 2055 type = "critical"; 2056 }; 2057 }; 2058 }; 2059 2060 gpuss0-thermal { 2061 polling-delay-passive = <0>; 2062 polling-delay = <0>; 2063 2064 thermal-sensors = <&tsens1 1>; 2065 2066 trips { 2067 gpuss0_alert0: trip-point0 { 2068 temperature = <90000>; 2069 hysteresis = <2000>; 2070 type = "hot"; 2071 }; 2072 2073 gpuss0_crit: gpuss0-crit { 2074 temperature = <110000>; 2075 hysteresis = <0>; 2076 type = "critical"; 2077 }; 2078 }; 2079 }; 2080 2081 gpuss1-thermal { 2082 polling-delay-passive = <0>; 2083 polling-delay = <0>; 2084 2085 thermal-sensors = <&tsens1 2>; 2086 2087 trips { 2088 gpuss1_alert0: trip-point0 { 2089 temperature = <90000>; 2090 hysteresis = <2000>; 2091 type = "hot"; 2092 }; 2093 2094 gpuss1_crit: gpuss1-crit { 2095 temperature = <110000>; 2096 hysteresis = <0>; 2097 type = "critical"; 2098 }; 2099 }; 2100 }; 2101 2102 nspss0-thermal { 2103 polling-delay-passive = <0>; 2104 polling-delay = <0>; 2105 2106 thermal-sensors = <&tsens1 3>; 2107 2108 trips { 2109 nspss0_alert0: trip-point0 { 2110 temperature = <90000>; 2111 hysteresis = <2000>; 2112 type = "hot"; 2113 }; 2114 2115 nspss0_crit: nspss0-crit { 2116 temperature = <110000>; 2117 hysteresis = <0>; 2118 type = "critical"; 2119 }; 2120 }; 2121 }; 2122 2123 nspss1-thermal { 2124 polling-delay-passive = <0>; 2125 polling-delay = <0>; 2126 2127 thermal-sensors = <&tsens1 4>; 2128 2129 trips { 2130 nspss1_alert0: trip-point0 { 2131 temperature = <90000>; 2132 hysteresis = <2000>; 2133 type = "hot"; 2134 }; 2135 2136 nspss1_crit: nspss1-crit { 2137 temperature = <110000>; 2138 hysteresis = <0>; 2139 type = "critical"; 2140 }; 2141 }; 2142 }; 2143 2144 video-thermal { 2145 polling-delay-passive = <0>; 2146 polling-delay = <0>; 2147 2148 thermal-sensors = <&tsens1 5>; 2149 2150 trips { 2151 video_alert0: trip-point0 { 2152 temperature = <90000>; 2153 hysteresis = <2000>; 2154 type = "hot"; 2155 }; 2156 2157 video_crit: video-crit { 2158 temperature = <110000>; 2159 hysteresis = <0>; 2160 type = "critical"; 2161 }; 2162 }; 2163 }; 2164 2165 ddr-thermal { 2166 polling-delay-passive = <0>; 2167 polling-delay = <0>; 2168 2169 thermal-sensors = <&tsens1 6>; 2170 2171 trips { 2172 ddr_alert0: trip-point0 { 2173 temperature = <90000>; 2174 hysteresis = <2000>; 2175 type = "hot"; 2176 }; 2177 2178 ddr_crit: ddr-crit { 2179 temperature = <110000>; 2180 hysteresis = <0>; 2181 type = "critical"; 2182 }; 2183 }; 2184 }; 2185 2186 mdmss0-thermal { 2187 polling-delay-passive = <0>; 2188 polling-delay = <0>; 2189 2190 thermal-sensors = <&tsens1 7>; 2191 2192 trips { 2193 mdmss0_alert0: trip-point0 { 2194 temperature = <90000>; 2195 hysteresis = <2000>; 2196 type = "hot"; 2197 }; 2198 2199 mdmss0_crit: mdmss0-crit { 2200 temperature = <110000>; 2201 hysteresis = <0>; 2202 type = "critical"; 2203 }; 2204 }; 2205 }; 2206 2207 mdmss1-thermal { 2208 polling-delay-passive = <0>; 2209 polling-delay = <0>; 2210 2211 thermal-sensors = <&tsens1 8>; 2212 2213 trips { 2214 mdmss1_alert0: trip-point0 { 2215 temperature = <90000>; 2216 hysteresis = <2000>; 2217 type = "hot"; 2218 }; 2219 2220 mdmss1_crit: mdmss1-crit { 2221 temperature = <110000>; 2222 hysteresis = <0>; 2223 type = "critical"; 2224 }; 2225 }; 2226 }; 2227 2228 mdmss2-thermal { 2229 polling-delay-passive = <0>; 2230 polling-delay = <0>; 2231 2232 thermal-sensors = <&tsens1 9>; 2233 2234 trips { 2235 mdmss2_alert0: trip-point0 { 2236 temperature = <90000>; 2237 hysteresis = <2000>; 2238 type = "hot"; 2239 }; 2240 2241 mdmss2_crit: mdmss2-crit { 2242 temperature = <110000>; 2243 hysteresis = <0>; 2244 type = "critical"; 2245 }; 2246 }; 2247 }; 2248 2249 mdmss3-thermal { 2250 polling-delay-passive = <0>; 2251 polling-delay = <0>; 2252 2253 thermal-sensors = <&tsens1 10>; 2254 2255 trips { 2256 mdmss3_alert0: trip-point0 { 2257 temperature = <90000>; 2258 hysteresis = <2000>; 2259 type = "hot"; 2260 }; 2261 2262 mdmss3_crit: mdmss3-crit { 2263 temperature = <110000>; 2264 hysteresis = <0>; 2265 type = "critical"; 2266 }; 2267 }; 2268 }; 2269 2270 camera0-thermal { 2271 polling-delay-passive = <0>; 2272 polling-delay = <0>; 2273 2274 thermal-sensors = <&tsens1 11>; 2275 2276 trips { 2277 camera0_alert0: trip-point0 { 2278 temperature = <90000>; 2279 hysteresis = <2000>; 2280 type = "hot"; 2281 }; 2282 2283 camera0_crit: camera0-crit { 2284 temperature = <110000>; 2285 hysteresis = <0>; 2286 type = "critical"; 2287 }; 2288 }; 2289 }; 2290 }; 2291 2292 timer { 2293 compatible = "arm,armv8-timer"; 2294 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2295 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2296 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2297 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2298 }; 2299}; 2300