1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 next-level-cache = <&L3_0>; 185 L3_0: l3-cache { 186 compatible = "cache"; 187 cache-level = <3>; 188 }; 189 }; 190 }; 191 192 CPU1: cpu@100 { 193 device_type = "cpu"; 194 compatible = "qcom,kryo"; 195 reg = <0x0 0x100>; 196 enable-method = "psci"; 197 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 198 &LITTLE_CPU_SLEEP_1 199 &CLUSTER_SLEEP_0>; 200 next-level-cache = <&L2_100>; 201 operating-points-v2 = <&cpu0_opp_table>; 202 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 203 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 204 qcom,freq-domain = <&cpufreq_hw 0>; 205 #cooling-cells = <2>; 206 L2_100: l2-cache { 207 compatible = "cache"; 208 cache-level = <2>; 209 next-level-cache = <&L3_0>; 210 }; 211 }; 212 213 CPU2: cpu@200 { 214 device_type = "cpu"; 215 compatible = "qcom,kryo"; 216 reg = <0x0 0x200>; 217 enable-method = "psci"; 218 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 219 &LITTLE_CPU_SLEEP_1 220 &CLUSTER_SLEEP_0>; 221 next-level-cache = <&L2_200>; 222 operating-points-v2 = <&cpu0_opp_table>; 223 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 224 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 225 qcom,freq-domain = <&cpufreq_hw 0>; 226 #cooling-cells = <2>; 227 L2_200: l2-cache { 228 compatible = "cache"; 229 cache-level = <2>; 230 next-level-cache = <&L3_0>; 231 }; 232 }; 233 234 CPU3: cpu@300 { 235 device_type = "cpu"; 236 compatible = "qcom,kryo"; 237 reg = <0x0 0x300>; 238 enable-method = "psci"; 239 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 240 &LITTLE_CPU_SLEEP_1 241 &CLUSTER_SLEEP_0>; 242 next-level-cache = <&L2_300>; 243 operating-points-v2 = <&cpu0_opp_table>; 244 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 245 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 246 qcom,freq-domain = <&cpufreq_hw 0>; 247 #cooling-cells = <2>; 248 L2_300: l2-cache { 249 compatible = "cache"; 250 cache-level = <2>; 251 next-level-cache = <&L3_0>; 252 }; 253 }; 254 255 CPU4: cpu@400 { 256 device_type = "cpu"; 257 compatible = "qcom,kryo"; 258 reg = <0x0 0x400>; 259 enable-method = "psci"; 260 cpu-idle-states = <&BIG_CPU_SLEEP_0 261 &BIG_CPU_SLEEP_1 262 &CLUSTER_SLEEP_0>; 263 next-level-cache = <&L2_400>; 264 operating-points-v2 = <&cpu4_opp_table>; 265 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 266 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 267 qcom,freq-domain = <&cpufreq_hw 1>; 268 #cooling-cells = <2>; 269 L2_400: l2-cache { 270 compatible = "cache"; 271 cache-level = <2>; 272 next-level-cache = <&L3_0>; 273 }; 274 }; 275 276 CPU5: cpu@500 { 277 device_type = "cpu"; 278 compatible = "qcom,kryo"; 279 reg = <0x0 0x500>; 280 enable-method = "psci"; 281 cpu-idle-states = <&BIG_CPU_SLEEP_0 282 &BIG_CPU_SLEEP_1 283 &CLUSTER_SLEEP_0>; 284 next-level-cache = <&L2_500>; 285 operating-points-v2 = <&cpu4_opp_table>; 286 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 287 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 288 qcom,freq-domain = <&cpufreq_hw 1>; 289 #cooling-cells = <2>; 290 L2_500: l2-cache { 291 compatible = "cache"; 292 cache-level = <2>; 293 next-level-cache = <&L3_0>; 294 }; 295 }; 296 297 CPU6: cpu@600 { 298 device_type = "cpu"; 299 compatible = "qcom,kryo"; 300 reg = <0x0 0x600>; 301 enable-method = "psci"; 302 cpu-idle-states = <&BIG_CPU_SLEEP_0 303 &BIG_CPU_SLEEP_1 304 &CLUSTER_SLEEP_0>; 305 next-level-cache = <&L2_600>; 306 operating-points-v2 = <&cpu4_opp_table>; 307 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 308 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 309 qcom,freq-domain = <&cpufreq_hw 1>; 310 #cooling-cells = <2>; 311 L2_600: l2-cache { 312 compatible = "cache"; 313 cache-level = <2>; 314 next-level-cache = <&L3_0>; 315 }; 316 }; 317 318 CPU7: cpu@700 { 319 device_type = "cpu"; 320 compatible = "qcom,kryo"; 321 reg = <0x0 0x700>; 322 enable-method = "psci"; 323 cpu-idle-states = <&BIG_CPU_SLEEP_0 324 &BIG_CPU_SLEEP_1 325 &CLUSTER_SLEEP_0>; 326 next-level-cache = <&L2_700>; 327 operating-points-v2 = <&cpu7_opp_table>; 328 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 329 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 330 qcom,freq-domain = <&cpufreq_hw 2>; 331 #cooling-cells = <2>; 332 L2_700: l2-cache { 333 compatible = "cache"; 334 cache-level = <2>; 335 next-level-cache = <&L3_0>; 336 }; 337 }; 338 339 cpu-map { 340 cluster0 { 341 core0 { 342 cpu = <&CPU0>; 343 }; 344 345 core1 { 346 cpu = <&CPU1>; 347 }; 348 349 core2 { 350 cpu = <&CPU2>; 351 }; 352 353 core3 { 354 cpu = <&CPU3>; 355 }; 356 357 core4 { 358 cpu = <&CPU4>; 359 }; 360 361 core5 { 362 cpu = <&CPU5>; 363 }; 364 365 core6 { 366 cpu = <&CPU6>; 367 }; 368 369 core7 { 370 cpu = <&CPU7>; 371 }; 372 }; 373 }; 374 375 idle-states { 376 entry-method = "psci"; 377 378 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 379 compatible = "arm,idle-state"; 380 idle-state-name = "little-power-down"; 381 arm,psci-suspend-param = <0x40000003>; 382 entry-latency-us = <549>; 383 exit-latency-us = <901>; 384 min-residency-us = <1774>; 385 local-timer-stop; 386 }; 387 388 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 389 compatible = "arm,idle-state"; 390 idle-state-name = "little-rail-power-down"; 391 arm,psci-suspend-param = <0x40000004>; 392 entry-latency-us = <702>; 393 exit-latency-us = <915>; 394 min-residency-us = <4001>; 395 local-timer-stop; 396 }; 397 398 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 399 compatible = "arm,idle-state"; 400 idle-state-name = "big-power-down"; 401 arm,psci-suspend-param = <0x40000003>; 402 entry-latency-us = <523>; 403 exit-latency-us = <1244>; 404 min-residency-us = <2207>; 405 local-timer-stop; 406 }; 407 408 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 409 compatible = "arm,idle-state"; 410 idle-state-name = "big-rail-power-down"; 411 arm,psci-suspend-param = <0x40000004>; 412 entry-latency-us = <526>; 413 exit-latency-us = <1854>; 414 min-residency-us = <5555>; 415 local-timer-stop; 416 }; 417 418 CLUSTER_SLEEP_0: cluster-sleep-0 { 419 compatible = "arm,idle-state"; 420 idle-state-name = "cluster-power-down"; 421 arm,psci-suspend-param = <0x40003444>; 422 entry-latency-us = <3263>; 423 exit-latency-us = <6562>; 424 min-residency-us = <9926>; 425 local-timer-stop; 426 }; 427 }; 428 }; 429 430 cpu0_opp_table: opp-table-cpu0 { 431 compatible = "operating-points-v2"; 432 opp-shared; 433 434 cpu0_opp_300mhz: opp-300000000 { 435 opp-hz = /bits/ 64 <300000000>; 436 opp-peak-kBps = <800000 9600000>; 437 }; 438 439 cpu0_opp_691mhz: opp-691200000 { 440 opp-hz = /bits/ 64 <691200000>; 441 opp-peak-kBps = <800000 17817600>; 442 }; 443 444 cpu0_opp_806mhz: opp-806400000 { 445 opp-hz = /bits/ 64 <806400000>; 446 opp-peak-kBps = <800000 20889600>; 447 }; 448 449 cpu0_opp_941mhz: opp-940800000 { 450 opp-hz = /bits/ 64 <940800000>; 451 opp-peak-kBps = <1804000 24576000>; 452 }; 453 454 cpu0_opp_1152mhz: opp-1152000000 { 455 opp-hz = /bits/ 64 <1152000000>; 456 opp-peak-kBps = <2188000 27033600>; 457 }; 458 459 cpu0_opp_1325mhz: opp-1324800000 { 460 opp-hz = /bits/ 64 <1324800000>; 461 opp-peak-kBps = <2188000 33792000>; 462 }; 463 464 cpu0_opp_1517mhz: opp-1516800000 { 465 opp-hz = /bits/ 64 <1516800000>; 466 opp-peak-kBps = <3072000 38092800>; 467 }; 468 469 cpu0_opp_1651mhz: opp-1651200000 { 470 opp-hz = /bits/ 64 <1651200000>; 471 opp-peak-kBps = <3072000 41779200>; 472 }; 473 474 cpu0_opp_1805mhz: opp-1804800000 { 475 opp-hz = /bits/ 64 <1804800000>; 476 opp-peak-kBps = <4068000 48537600>; 477 }; 478 479 cpu0_opp_1958mhz: opp-1958400000 { 480 opp-hz = /bits/ 64 <1958400000>; 481 opp-peak-kBps = <4068000 48537600>; 482 }; 483 484 cpu0_opp_2016mhz: opp-2016000000 { 485 opp-hz = /bits/ 64 <2016000000>; 486 opp-peak-kBps = <6220000 48537600>; 487 }; 488 }; 489 490 cpu4_opp_table: opp-table-cpu4 { 491 compatible = "operating-points-v2"; 492 opp-shared; 493 494 cpu4_opp_691mhz: opp-691200000 { 495 opp-hz = /bits/ 64 <691200000>; 496 opp-peak-kBps = <1804000 9600000>; 497 }; 498 499 cpu4_opp_941mhz: opp-940800000 { 500 opp-hz = /bits/ 64 <940800000>; 501 opp-peak-kBps = <2188000 17817600>; 502 }; 503 504 cpu4_opp_1229mhz: opp-1228800000 { 505 opp-hz = /bits/ 64 <1228800000>; 506 opp-peak-kBps = <4068000 24576000>; 507 }; 508 509 cpu4_opp_1344mhz: opp-1344000000 { 510 opp-hz = /bits/ 64 <1344000000>; 511 opp-peak-kBps = <4068000 24576000>; 512 }; 513 514 cpu4_opp_1517mhz: opp-1516800000 { 515 opp-hz = /bits/ 64 <1516800000>; 516 opp-peak-kBps = <4068000 24576000>; 517 }; 518 519 cpu4_opp_1651mhz: opp-1651200000 { 520 opp-hz = /bits/ 64 <1651200000>; 521 opp-peak-kBps = <6220000 38092800>; 522 }; 523 524 cpu4_opp_1901mhz: opp-1900800000 { 525 opp-hz = /bits/ 64 <1900800000>; 526 opp-peak-kBps = <6220000 44851200>; 527 }; 528 529 cpu4_opp_2054mhz: opp-2054400000 { 530 opp-hz = /bits/ 64 <2054400000>; 531 opp-peak-kBps = <6220000 44851200>; 532 }; 533 534 cpu4_opp_2112mhz: opp-2112000000 { 535 opp-hz = /bits/ 64 <2112000000>; 536 opp-peak-kBps = <6220000 44851200>; 537 }; 538 539 cpu4_opp_2131mhz: opp-2131200000 { 540 opp-hz = /bits/ 64 <2131200000>; 541 opp-peak-kBps = <6220000 44851200>; 542 }; 543 544 cpu4_opp_2208mhz: opp-2208000000 { 545 opp-hz = /bits/ 64 <2208000000>; 546 opp-peak-kBps = <6220000 44851200>; 547 }; 548 549 cpu4_opp_2400mhz: opp-2400000000 { 550 opp-hz = /bits/ 64 <2400000000>; 551 opp-peak-kBps = <8532000 48537600>; 552 }; 553 554 cpu4_opp_2611mhz: opp-2611200000 { 555 opp-hz = /bits/ 64 <2611200000>; 556 opp-peak-kBps = <8532000 48537600>; 557 }; 558 }; 559 560 cpu7_opp_table: opp-table-cpu7 { 561 compatible = "operating-points-v2"; 562 opp-shared; 563 564 cpu7_opp_806mhz: opp-806400000 { 565 opp-hz = /bits/ 64 <806400000>; 566 opp-peak-kBps = <1804000 9600000>; 567 }; 568 569 cpu7_opp_1056mhz: opp-1056000000 { 570 opp-hz = /bits/ 64 <1056000000>; 571 opp-peak-kBps = <2188000 17817600>; 572 }; 573 574 cpu7_opp_1325mhz: opp-1324800000 { 575 opp-hz = /bits/ 64 <1324800000>; 576 opp-peak-kBps = <4068000 24576000>; 577 }; 578 579 cpu7_opp_1517mhz: opp-1516800000 { 580 opp-hz = /bits/ 64 <1516800000>; 581 opp-peak-kBps = <4068000 24576000>; 582 }; 583 584 cpu7_opp_1766mhz: opp-1766400000 { 585 opp-hz = /bits/ 64 <1766400000>; 586 opp-peak-kBps = <6220000 38092800>; 587 }; 588 589 cpu7_opp_1862mhz: opp-1862400000 { 590 opp-hz = /bits/ 64 <1862400000>; 591 opp-peak-kBps = <6220000 38092800>; 592 }; 593 594 cpu7_opp_2035mhz: opp-2035200000 { 595 opp-hz = /bits/ 64 <2035200000>; 596 opp-peak-kBps = <6220000 38092800>; 597 }; 598 599 cpu7_opp_2112mhz: opp-2112000000 { 600 opp-hz = /bits/ 64 <2112000000>; 601 opp-peak-kBps = <6220000 44851200>; 602 }; 603 604 cpu7_opp_2208mhz: opp-2208000000 { 605 opp-hz = /bits/ 64 <2208000000>; 606 opp-peak-kBps = <6220000 44851200>; 607 }; 608 609 cpu7_opp_2381mhz: opp-2380800000 { 610 opp-hz = /bits/ 64 <2380800000>; 611 opp-peak-kBps = <6832000 44851200>; 612 }; 613 614 cpu7_opp_2400mhz: opp-2400000000 { 615 opp-hz = /bits/ 64 <2400000000>; 616 opp-peak-kBps = <8532000 48537600>; 617 }; 618 619 cpu7_opp_2515mhz: opp-2515200000 { 620 opp-hz = /bits/ 64 <2515200000>; 621 opp-peak-kBps = <8532000 48537600>; 622 }; 623 624 cpu7_opp_2707mhz: opp-2707200000 { 625 opp-hz = /bits/ 64 <2707200000>; 626 opp-peak-kBps = <8532000 48537600>; 627 }; 628 629 cpu7_opp_3014mhz: opp-3014400000 { 630 opp-hz = /bits/ 64 <3014400000>; 631 opp-peak-kBps = <8532000 48537600>; 632 }; 633 }; 634 635 memory@80000000 { 636 device_type = "memory"; 637 /* We expect the bootloader to fill in the size */ 638 reg = <0 0x80000000 0 0>; 639 }; 640 641 firmware { 642 scm { 643 compatible = "qcom,scm-sc7280", "qcom,scm"; 644 }; 645 }; 646 647 clk_virt: interconnect { 648 compatible = "qcom,sc7280-clk-virt"; 649 #interconnect-cells = <2>; 650 qcom,bcm-voters = <&apps_bcm_voter>; 651 }; 652 653 smem { 654 compatible = "qcom,smem"; 655 memory-region = <&smem_mem>; 656 hwlocks = <&tcsr_mutex 3>; 657 }; 658 659 smp2p-adsp { 660 compatible = "qcom,smp2p"; 661 qcom,smem = <443>, <429>; 662 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 663 IPCC_MPROC_SIGNAL_SMP2P 664 IRQ_TYPE_EDGE_RISING>; 665 mboxes = <&ipcc IPCC_CLIENT_LPASS 666 IPCC_MPROC_SIGNAL_SMP2P>; 667 668 qcom,local-pid = <0>; 669 qcom,remote-pid = <2>; 670 671 adsp_smp2p_out: master-kernel { 672 qcom,entry-name = "master-kernel"; 673 #qcom,smem-state-cells = <1>; 674 }; 675 676 adsp_smp2p_in: slave-kernel { 677 qcom,entry-name = "slave-kernel"; 678 interrupt-controller; 679 #interrupt-cells = <2>; 680 }; 681 }; 682 683 smp2p-cdsp { 684 compatible = "qcom,smp2p"; 685 qcom,smem = <94>, <432>; 686 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 687 IPCC_MPROC_SIGNAL_SMP2P 688 IRQ_TYPE_EDGE_RISING>; 689 mboxes = <&ipcc IPCC_CLIENT_CDSP 690 IPCC_MPROC_SIGNAL_SMP2P>; 691 692 qcom,local-pid = <0>; 693 qcom,remote-pid = <5>; 694 695 cdsp_smp2p_out: master-kernel { 696 qcom,entry-name = "master-kernel"; 697 #qcom,smem-state-cells = <1>; 698 }; 699 700 cdsp_smp2p_in: slave-kernel { 701 qcom,entry-name = "slave-kernel"; 702 interrupt-controller; 703 #interrupt-cells = <2>; 704 }; 705 }; 706 707 smp2p-mpss { 708 compatible = "qcom,smp2p"; 709 qcom,smem = <435>, <428>; 710 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 711 IPCC_MPROC_SIGNAL_SMP2P 712 IRQ_TYPE_EDGE_RISING>; 713 mboxes = <&ipcc IPCC_CLIENT_MPSS 714 IPCC_MPROC_SIGNAL_SMP2P>; 715 716 qcom,local-pid = <0>; 717 qcom,remote-pid = <1>; 718 719 modem_smp2p_out: master-kernel { 720 qcom,entry-name = "master-kernel"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 modem_smp2p_in: slave-kernel { 725 qcom,entry-name = "slave-kernel"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 730 ipa_smp2p_out: ipa-ap-to-modem { 731 qcom,entry-name = "ipa"; 732 #qcom,smem-state-cells = <1>; 733 }; 734 735 ipa_smp2p_in: ipa-modem-to-ap { 736 qcom,entry-name = "ipa"; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 }; 740 }; 741 742 smp2p-wpss { 743 compatible = "qcom,smp2p"; 744 qcom,smem = <617>, <616>; 745 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 746 IPCC_MPROC_SIGNAL_SMP2P 747 IRQ_TYPE_EDGE_RISING>; 748 mboxes = <&ipcc IPCC_CLIENT_WPSS 749 IPCC_MPROC_SIGNAL_SMP2P>; 750 751 qcom,local-pid = <0>; 752 qcom,remote-pid = <13>; 753 754 wpss_smp2p_out: master-kernel { 755 qcom,entry-name = "master-kernel"; 756 #qcom,smem-state-cells = <1>; 757 }; 758 759 wpss_smp2p_in: slave-kernel { 760 qcom,entry-name = "slave-kernel"; 761 interrupt-controller; 762 #interrupt-cells = <2>; 763 }; 764 765 wlan_smp2p_out: wlan-ap-to-wpss { 766 qcom,entry-name = "wlan"; 767 #qcom,smem-state-cells = <1>; 768 }; 769 770 wlan_smp2p_in: wlan-wpss-to-ap { 771 qcom,entry-name = "wlan"; 772 interrupt-controller; 773 #interrupt-cells = <2>; 774 }; 775 }; 776 777 pmu { 778 compatible = "arm,armv8-pmuv3"; 779 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 780 }; 781 782 psci { 783 compatible = "arm,psci-1.0"; 784 method = "smc"; 785 }; 786 787 qspi_opp_table: opp-table-qspi { 788 compatible = "operating-points-v2"; 789 790 opp-75000000 { 791 opp-hz = /bits/ 64 <75000000>; 792 required-opps = <&rpmhpd_opp_low_svs>; 793 }; 794 795 opp-150000000 { 796 opp-hz = /bits/ 64 <150000000>; 797 required-opps = <&rpmhpd_opp_svs>; 798 }; 799 800 opp-200000000 { 801 opp-hz = /bits/ 64 <200000000>; 802 required-opps = <&rpmhpd_opp_svs_l1>; 803 }; 804 805 opp-300000000 { 806 opp-hz = /bits/ 64 <300000000>; 807 required-opps = <&rpmhpd_opp_nom>; 808 }; 809 }; 810 811 qup_opp_table: opp-table-qup { 812 compatible = "operating-points-v2"; 813 814 opp-75000000 { 815 opp-hz = /bits/ 64 <75000000>; 816 required-opps = <&rpmhpd_opp_low_svs>; 817 }; 818 819 opp-100000000 { 820 opp-hz = /bits/ 64 <100000000>; 821 required-opps = <&rpmhpd_opp_svs>; 822 }; 823 824 opp-128000000 { 825 opp-hz = /bits/ 64 <128000000>; 826 required-opps = <&rpmhpd_opp_nom>; 827 }; 828 }; 829 830 soc: soc@0 { 831 #address-cells = <2>; 832 #size-cells = <2>; 833 ranges = <0 0 0 0 0x10 0>; 834 dma-ranges = <0 0 0 0 0x10 0>; 835 compatible = "simple-bus"; 836 837 gcc: clock-controller@100000 { 838 compatible = "qcom,gcc-sc7280"; 839 reg = <0 0x00100000 0 0x1f0000>; 840 clocks = <&rpmhcc RPMH_CXO_CLK>, 841 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 842 <0>, <&pcie1_lane>, 843 <0>, <0>, <0>, <0>; 844 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 845 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 846 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 847 "ufs_phy_tx_symbol_0_clk", 848 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 849 #clock-cells = <1>; 850 #reset-cells = <1>; 851 #power-domain-cells = <1>; 852 power-domains = <&rpmhpd SC7280_CX>; 853 }; 854 855 ipcc: mailbox@408000 { 856 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 857 reg = <0 0x00408000 0 0x1000>; 858 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-controller; 860 #interrupt-cells = <3>; 861 #mbox-cells = <2>; 862 }; 863 864 qfprom: efuse@784000 { 865 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 866 reg = <0 0x00784000 0 0xa20>, 867 <0 0x00780000 0 0xa20>, 868 <0 0x00782000 0 0x120>, 869 <0 0x00786000 0 0x1fff>; 870 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 871 clock-names = "core"; 872 power-domains = <&rpmhpd SC7280_MX>; 873 #address-cells = <1>; 874 #size-cells = <1>; 875 876 gpu_speed_bin: gpu_speed_bin@1e9 { 877 reg = <0x1e9 0x2>; 878 bits = <5 8>; 879 }; 880 }; 881 882 sdhc_1: mmc@7c4000 { 883 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 884 pinctrl-names = "default", "sleep"; 885 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 886 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 887 status = "disabled"; 888 889 reg = <0 0x007c4000 0 0x1000>, 890 <0 0x007c5000 0 0x1000>; 891 reg-names = "hc", "cqhci"; 892 893 iommus = <&apps_smmu 0xc0 0x0>; 894 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 896 interrupt-names = "hc_irq", "pwr_irq"; 897 898 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 899 <&gcc GCC_SDCC1_APPS_CLK>, 900 <&rpmhcc RPMH_CXO_CLK>; 901 clock-names = "iface", "core", "xo"; 902 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 903 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 904 interconnect-names = "sdhc-ddr","cpu-sdhc"; 905 power-domains = <&rpmhpd SC7280_CX>; 906 operating-points-v2 = <&sdhc1_opp_table>; 907 908 bus-width = <8>; 909 supports-cqe; 910 911 qcom,dll-config = <0x0007642c>; 912 qcom,ddr-config = <0x80040868>; 913 914 mmc-ddr-1_8v; 915 mmc-hs200-1_8v; 916 mmc-hs400-1_8v; 917 mmc-hs400-enhanced-strobe; 918 919 resets = <&gcc GCC_SDCC1_BCR>; 920 921 sdhc1_opp_table: opp-table { 922 compatible = "operating-points-v2"; 923 924 opp-100000000 { 925 opp-hz = /bits/ 64 <100000000>; 926 required-opps = <&rpmhpd_opp_low_svs>; 927 opp-peak-kBps = <1800000 400000>; 928 opp-avg-kBps = <100000 0>; 929 }; 930 931 opp-384000000 { 932 opp-hz = /bits/ 64 <384000000>; 933 required-opps = <&rpmhpd_opp_nom>; 934 opp-peak-kBps = <5400000 1600000>; 935 opp-avg-kBps = <390000 0>; 936 }; 937 }; 938 939 }; 940 941 gpi_dma0: dma-controller@900000 { 942 #dma-cells = <3>; 943 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 944 reg = <0 0x00900000 0 0x60000>; 945 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 957 dma-channels = <12>; 958 dma-channel-mask = <0x7f>; 959 iommus = <&apps_smmu 0x0136 0x0>; 960 status = "disabled"; 961 }; 962 963 qupv3_id_0: geniqup@9c0000 { 964 compatible = "qcom,geni-se-qup"; 965 reg = <0 0x009c0000 0 0x2000>; 966 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 967 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 968 clock-names = "m-ahb", "s-ahb"; 969 #address-cells = <2>; 970 #size-cells = <2>; 971 ranges; 972 iommus = <&apps_smmu 0x123 0x0>; 973 status = "disabled"; 974 975 i2c0: i2c@980000 { 976 compatible = "qcom,geni-i2c"; 977 reg = <0 0x00980000 0 0x4000>; 978 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 979 clock-names = "se"; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&qup_i2c0_data_clk>; 982 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 986 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 987 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 988 interconnect-names = "qup-core", "qup-config", 989 "qup-memory"; 990 power-domains = <&rpmhpd SC7280_CX>; 991 required-opps = <&rpmhpd_opp_low_svs>; 992 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 993 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 994 dma-names = "tx", "rx"; 995 status = "disabled"; 996 }; 997 998 spi0: spi@980000 { 999 compatible = "qcom,geni-spi"; 1000 reg = <0 0x00980000 0 0x4000>; 1001 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1002 clock-names = "se"; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1005 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 power-domains = <&rpmhpd SC7280_CX>; 1009 operating-points-v2 = <&qup_opp_table>; 1010 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1011 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1012 interconnect-names = "qup-core", "qup-config"; 1013 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1014 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1015 dma-names = "tx", "rx"; 1016 status = "disabled"; 1017 }; 1018 1019 uart0: serial@980000 { 1020 compatible = "qcom,geni-uart"; 1021 reg = <0 0x00980000 0 0x4000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1023 clock-names = "se"; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1026 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&rpmhpd SC7280_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 status = "disabled"; 1033 }; 1034 1035 i2c1: i2c@984000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x00984000 0 0x4000>; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1039 clock-names = "se"; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c1_data_clk>; 1042 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1047 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", 1049 "qup-memory"; 1050 power-domains = <&rpmhpd SC7280_CX>; 1051 required-opps = <&rpmhpd_opp_low_svs>; 1052 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1053 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1054 dma-names = "tx", "rx"; 1055 status = "disabled"; 1056 }; 1057 1058 spi1: spi@984000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x00984000 0 0x4000>; 1061 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1062 clock-names = "se"; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1065 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 power-domains = <&rpmhpd SC7280_CX>; 1069 operating-points-v2 = <&qup_opp_table>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1071 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1072 interconnect-names = "qup-core", "qup-config"; 1073 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1074 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1075 dma-names = "tx", "rx"; 1076 status = "disabled"; 1077 }; 1078 1079 uart1: serial@984000 { 1080 compatible = "qcom,geni-uart"; 1081 reg = <0 0x00984000 0 0x4000>; 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1083 clock-names = "se"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1086 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1087 power-domains = <&rpmhpd SC7280_CX>; 1088 operating-points-v2 = <&qup_opp_table>; 1089 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1091 interconnect-names = "qup-core", "qup-config"; 1092 status = "disabled"; 1093 }; 1094 1095 i2c2: i2c@988000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x00988000 0 0x4000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1099 clock-names = "se"; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_i2c2_data_clk>; 1102 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1106 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1107 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1108 interconnect-names = "qup-core", "qup-config", 1109 "qup-memory"; 1110 power-domains = <&rpmhpd SC7280_CX>; 1111 required-opps = <&rpmhpd_opp_low_svs>; 1112 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1113 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1114 dma-names = "tx", "rx"; 1115 status = "disabled"; 1116 }; 1117 1118 spi2: spi@988000 { 1119 compatible = "qcom,geni-spi"; 1120 reg = <0 0x00988000 0 0x4000>; 1121 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1122 clock-names = "se"; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1125 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 operating-points-v2 = <&qup_opp_table>; 1130 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1132 interconnect-names = "qup-core", "qup-config"; 1133 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1134 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1135 dma-names = "tx", "rx"; 1136 status = "disabled"; 1137 }; 1138 1139 uart2: serial@988000 { 1140 compatible = "qcom,geni-uart"; 1141 reg = <0 0x00988000 0 0x4000>; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1143 clock-names = "se"; 1144 pinctrl-names = "default"; 1145 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1146 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1147 power-domains = <&rpmhpd SC7280_CX>; 1148 operating-points-v2 = <&qup_opp_table>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1151 interconnect-names = "qup-core", "qup-config"; 1152 status = "disabled"; 1153 }; 1154 1155 i2c3: i2c@98c000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0 0x0098c000 0 0x4000>; 1158 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1159 clock-names = "se"; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&qup_i2c3_data_clk>; 1162 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1166 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1167 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1168 interconnect-names = "qup-core", "qup-config", 1169 "qup-memory"; 1170 power-domains = <&rpmhpd SC7280_CX>; 1171 required-opps = <&rpmhpd_opp_low_svs>; 1172 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1173 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1174 dma-names = "tx", "rx"; 1175 status = "disabled"; 1176 }; 1177 1178 spi3: spi@98c000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0 0x0098c000 0 0x4000>; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1182 clock-names = "se"; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1185 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 power-domains = <&rpmhpd SC7280_CX>; 1189 operating-points-v2 = <&qup_opp_table>; 1190 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1191 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1192 interconnect-names = "qup-core", "qup-config"; 1193 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1194 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1195 dma-names = "tx", "rx"; 1196 status = "disabled"; 1197 }; 1198 1199 uart3: serial@98c000 { 1200 compatible = "qcom,geni-uart"; 1201 reg = <0 0x0098c000 0 0x4000>; 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1203 clock-names = "se"; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1206 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1207 power-domains = <&rpmhpd SC7280_CX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 status = "disabled"; 1213 }; 1214 1215 i2c4: i2c@990000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x00990000 0 0x4000>; 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1219 clock-names = "se"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_i2c4_data_clk>; 1222 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1226 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1227 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1228 interconnect-names = "qup-core", "qup-config", 1229 "qup-memory"; 1230 power-domains = <&rpmhpd SC7280_CX>; 1231 required-opps = <&rpmhpd_opp_low_svs>; 1232 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1233 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1234 dma-names = "tx", "rx"; 1235 status = "disabled"; 1236 }; 1237 1238 spi4: spi@990000 { 1239 compatible = "qcom,geni-spi"; 1240 reg = <0 0x00990000 0 0x4000>; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1242 clock-names = "se"; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1245 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 operating-points-v2 = <&qup_opp_table>; 1250 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1251 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1252 interconnect-names = "qup-core", "qup-config"; 1253 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1254 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1255 dma-names = "tx", "rx"; 1256 status = "disabled"; 1257 }; 1258 1259 uart4: serial@990000 { 1260 compatible = "qcom,geni-uart"; 1261 reg = <0 0x00990000 0 0x4000>; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1263 clock-names = "se"; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1266 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1267 power-domains = <&rpmhpd SC7280_CX>; 1268 operating-points-v2 = <&qup_opp_table>; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1270 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1271 interconnect-names = "qup-core", "qup-config"; 1272 status = "disabled"; 1273 }; 1274 1275 i2c5: i2c@994000 { 1276 compatible = "qcom,geni-i2c"; 1277 reg = <0 0x00994000 0 0x4000>; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1279 clock-names = "se"; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_i2c5_data_clk>; 1282 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1286 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1287 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1288 interconnect-names = "qup-core", "qup-config", 1289 "qup-memory"; 1290 power-domains = <&rpmhpd SC7280_CX>; 1291 required-opps = <&rpmhpd_opp_low_svs>; 1292 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1293 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1294 dma-names = "tx", "rx"; 1295 status = "disabled"; 1296 }; 1297 1298 spi5: spi@994000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00994000 0 0x4000>; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1302 clock-names = "se"; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1305 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 power-domains = <&rpmhpd SC7280_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1311 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1312 interconnect-names = "qup-core", "qup-config"; 1313 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1314 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1315 dma-names = "tx", "rx"; 1316 status = "disabled"; 1317 }; 1318 1319 uart5: serial@994000 { 1320 compatible = "qcom,geni-uart"; 1321 reg = <0 0x00994000 0 0x4000>; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1323 clock-names = "se"; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1326 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1327 power-domains = <&rpmhpd SC7280_CX>; 1328 operating-points-v2 = <&qup_opp_table>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1331 interconnect-names = "qup-core", "qup-config"; 1332 status = "disabled"; 1333 }; 1334 1335 i2c6: i2c@998000 { 1336 compatible = "qcom,geni-i2c"; 1337 reg = <0 0x00998000 0 0x4000>; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1339 clock-names = "se"; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_i2c6_data_clk>; 1342 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1347 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1348 interconnect-names = "qup-core", "qup-config", 1349 "qup-memory"; 1350 power-domains = <&rpmhpd SC7280_CX>; 1351 required-opps = <&rpmhpd_opp_low_svs>; 1352 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1353 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1354 dma-names = "tx", "rx"; 1355 status = "disabled"; 1356 }; 1357 1358 spi6: spi@998000 { 1359 compatible = "qcom,geni-spi"; 1360 reg = <0 0x00998000 0 0x4000>; 1361 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1362 clock-names = "se"; 1363 pinctrl-names = "default"; 1364 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1365 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 power-domains = <&rpmhpd SC7280_CX>; 1369 operating-points-v2 = <&qup_opp_table>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1372 interconnect-names = "qup-core", "qup-config"; 1373 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1374 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1375 dma-names = "tx", "rx"; 1376 status = "disabled"; 1377 }; 1378 1379 uart6: serial@998000 { 1380 compatible = "qcom,geni-uart"; 1381 reg = <0 0x00998000 0 0x4000>; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1383 clock-names = "se"; 1384 pinctrl-names = "default"; 1385 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1386 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1387 power-domains = <&rpmhpd SC7280_CX>; 1388 operating-points-v2 = <&qup_opp_table>; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1390 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1391 interconnect-names = "qup-core", "qup-config"; 1392 status = "disabled"; 1393 }; 1394 1395 i2c7: i2c@99c000 { 1396 compatible = "qcom,geni-i2c"; 1397 reg = <0 0x0099c000 0 0x4000>; 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1399 clock-names = "se"; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_i2c7_data_clk>; 1402 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1406 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1407 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1408 interconnect-names = "qup-core", "qup-config", 1409 "qup-memory"; 1410 power-domains = <&rpmhpd SC7280_CX>; 1411 required-opps = <&rpmhpd_opp_low_svs>; 1412 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1413 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1414 dma-names = "tx", "rx"; 1415 status = "disabled"; 1416 }; 1417 1418 spi7: spi@99c000 { 1419 compatible = "qcom,geni-spi"; 1420 reg = <0 0x0099c000 0 0x4000>; 1421 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1422 clock-names = "se"; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1425 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 power-domains = <&rpmhpd SC7280_CX>; 1429 operating-points-v2 = <&qup_opp_table>; 1430 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1431 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1432 interconnect-names = "qup-core", "qup-config"; 1433 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1434 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1435 dma-names = "tx", "rx"; 1436 status = "disabled"; 1437 }; 1438 1439 uart7: serial@99c000 { 1440 compatible = "qcom,geni-uart"; 1441 reg = <0 0x0099c000 0 0x4000>; 1442 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1443 clock-names = "se"; 1444 pinctrl-names = "default"; 1445 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1446 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1447 power-domains = <&rpmhpd SC7280_CX>; 1448 operating-points-v2 = <&qup_opp_table>; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1451 interconnect-names = "qup-core", "qup-config"; 1452 status = "disabled"; 1453 }; 1454 }; 1455 1456 gpi_dma1: dma-controller@a00000 { 1457 #dma-cells = <3>; 1458 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1459 reg = <0 0x00a00000 0 0x60000>; 1460 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1472 dma-channels = <12>; 1473 dma-channel-mask = <0x1e>; 1474 iommus = <&apps_smmu 0x56 0x0>; 1475 status = "disabled"; 1476 }; 1477 1478 qupv3_id_1: geniqup@ac0000 { 1479 compatible = "qcom,geni-se-qup"; 1480 reg = <0 0x00ac0000 0 0x2000>; 1481 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1482 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1483 clock-names = "m-ahb", "s-ahb"; 1484 #address-cells = <2>; 1485 #size-cells = <2>; 1486 ranges; 1487 iommus = <&apps_smmu 0x43 0x0>; 1488 status = "disabled"; 1489 1490 i2c8: i2c@a80000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0 0x00a80000 0 0x4000>; 1493 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1494 clock-names = "se"; 1495 pinctrl-names = "default"; 1496 pinctrl-0 = <&qup_i2c8_data_clk>; 1497 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1501 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1503 interconnect-names = "qup-core", "qup-config", 1504 "qup-memory"; 1505 power-domains = <&rpmhpd SC7280_CX>; 1506 required-opps = <&rpmhpd_opp_low_svs>; 1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1508 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1509 dma-names = "tx", "rx"; 1510 status = "disabled"; 1511 }; 1512 1513 spi8: spi@a80000 { 1514 compatible = "qcom,geni-spi"; 1515 reg = <0 0x00a80000 0 0x4000>; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1517 clock-names = "se"; 1518 pinctrl-names = "default"; 1519 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1520 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 power-domains = <&rpmhpd SC7280_CX>; 1524 operating-points-v2 = <&qup_opp_table>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1527 interconnect-names = "qup-core", "qup-config"; 1528 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1529 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1530 dma-names = "tx", "rx"; 1531 status = "disabled"; 1532 }; 1533 1534 uart8: serial@a80000 { 1535 compatible = "qcom,geni-uart"; 1536 reg = <0 0x00a80000 0 0x4000>; 1537 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1538 clock-names = "se"; 1539 pinctrl-names = "default"; 1540 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1541 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1542 power-domains = <&rpmhpd SC7280_CX>; 1543 operating-points-v2 = <&qup_opp_table>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1546 interconnect-names = "qup-core", "qup-config"; 1547 status = "disabled"; 1548 }; 1549 1550 i2c9: i2c@a84000 { 1551 compatible = "qcom,geni-i2c"; 1552 reg = <0 0x00a84000 0 0x4000>; 1553 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1554 clock-names = "se"; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&qup_i2c9_data_clk>; 1557 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1561 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1562 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1563 interconnect-names = "qup-core", "qup-config", 1564 "qup-memory"; 1565 power-domains = <&rpmhpd SC7280_CX>; 1566 required-opps = <&rpmhpd_opp_low_svs>; 1567 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1568 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1569 dma-names = "tx", "rx"; 1570 status = "disabled"; 1571 }; 1572 1573 spi9: spi@a84000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0 0x00a84000 0 0x4000>; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1577 clock-names = "se"; 1578 pinctrl-names = "default"; 1579 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1580 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 power-domains = <&rpmhpd SC7280_CX>; 1584 operating-points-v2 = <&qup_opp_table>; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1586 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1587 interconnect-names = "qup-core", "qup-config"; 1588 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1589 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1590 dma-names = "tx", "rx"; 1591 status = "disabled"; 1592 }; 1593 1594 uart9: serial@a84000 { 1595 compatible = "qcom,geni-uart"; 1596 reg = <0 0x00a84000 0 0x4000>; 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1598 clock-names = "se"; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1601 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1602 power-domains = <&rpmhpd SC7280_CX>; 1603 operating-points-v2 = <&qup_opp_table>; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1606 interconnect-names = "qup-core", "qup-config"; 1607 status = "disabled"; 1608 }; 1609 1610 i2c10: i2c@a88000 { 1611 compatible = "qcom,geni-i2c"; 1612 reg = <0 0x00a88000 0 0x4000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1614 clock-names = "se"; 1615 pinctrl-names = "default"; 1616 pinctrl-0 = <&qup_i2c10_data_clk>; 1617 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1623 interconnect-names = "qup-core", "qup-config", 1624 "qup-memory"; 1625 power-domains = <&rpmhpd SC7280_CX>; 1626 required-opps = <&rpmhpd_opp_low_svs>; 1627 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1628 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1629 dma-names = "tx", "rx"; 1630 status = "disabled"; 1631 }; 1632 1633 spi10: spi@a88000 { 1634 compatible = "qcom,geni-spi"; 1635 reg = <0 0x00a88000 0 0x4000>; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1637 clock-names = "se"; 1638 pinctrl-names = "default"; 1639 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1640 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 power-domains = <&rpmhpd SC7280_CX>; 1644 operating-points-v2 = <&qup_opp_table>; 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1646 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1647 interconnect-names = "qup-core", "qup-config"; 1648 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1649 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1650 dma-names = "tx", "rx"; 1651 status = "disabled"; 1652 }; 1653 1654 uart10: serial@a88000 { 1655 compatible = "qcom,geni-uart"; 1656 reg = <0 0x00a88000 0 0x4000>; 1657 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1658 clock-names = "se"; 1659 pinctrl-names = "default"; 1660 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1661 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1662 power-domains = <&rpmhpd SC7280_CX>; 1663 operating-points-v2 = <&qup_opp_table>; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1665 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1666 interconnect-names = "qup-core", "qup-config"; 1667 status = "disabled"; 1668 }; 1669 1670 i2c11: i2c@a8c000 { 1671 compatible = "qcom,geni-i2c"; 1672 reg = <0 0x00a8c000 0 0x4000>; 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1674 clock-names = "se"; 1675 pinctrl-names = "default"; 1676 pinctrl-0 = <&qup_i2c11_data_clk>; 1677 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1683 interconnect-names = "qup-core", "qup-config", 1684 "qup-memory"; 1685 power-domains = <&rpmhpd SC7280_CX>; 1686 required-opps = <&rpmhpd_opp_low_svs>; 1687 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1688 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 status = "disabled"; 1691 }; 1692 1693 spi11: spi@a8c000 { 1694 compatible = "qcom,geni-spi"; 1695 reg = <0 0x00a8c000 0 0x4000>; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1697 clock-names = "se"; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1700 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 power-domains = <&rpmhpd SC7280_CX>; 1704 operating-points-v2 = <&qup_opp_table>; 1705 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1706 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1707 interconnect-names = "qup-core", "qup-config"; 1708 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1709 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1710 dma-names = "tx", "rx"; 1711 status = "disabled"; 1712 }; 1713 1714 uart11: serial@a8c000 { 1715 compatible = "qcom,geni-uart"; 1716 reg = <0 0x00a8c000 0 0x4000>; 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1718 clock-names = "se"; 1719 pinctrl-names = "default"; 1720 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1721 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1722 power-domains = <&rpmhpd SC7280_CX>; 1723 operating-points-v2 = <&qup_opp_table>; 1724 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1725 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1726 interconnect-names = "qup-core", "qup-config"; 1727 status = "disabled"; 1728 }; 1729 1730 i2c12: i2c@a90000 { 1731 compatible = "qcom,geni-i2c"; 1732 reg = <0 0x00a90000 0 0x4000>; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1734 clock-names = "se"; 1735 pinctrl-names = "default"; 1736 pinctrl-0 = <&qup_i2c12_data_clk>; 1737 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1741 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1742 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1743 interconnect-names = "qup-core", "qup-config", 1744 "qup-memory"; 1745 power-domains = <&rpmhpd SC7280_CX>; 1746 required-opps = <&rpmhpd_opp_low_svs>; 1747 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1748 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1749 dma-names = "tx", "rx"; 1750 status = "disabled"; 1751 }; 1752 1753 spi12: spi@a90000 { 1754 compatible = "qcom,geni-spi"; 1755 reg = <0 0x00a90000 0 0x4000>; 1756 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1757 clock-names = "se"; 1758 pinctrl-names = "default"; 1759 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1760 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 power-domains = <&rpmhpd SC7280_CX>; 1764 operating-points-v2 = <&qup_opp_table>; 1765 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1766 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1767 interconnect-names = "qup-core", "qup-config"; 1768 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1769 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1770 dma-names = "tx", "rx"; 1771 status = "disabled"; 1772 }; 1773 1774 uart12: serial@a90000 { 1775 compatible = "qcom,geni-uart"; 1776 reg = <0 0x00a90000 0 0x4000>; 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1778 clock-names = "se"; 1779 pinctrl-names = "default"; 1780 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1781 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1782 power-domains = <&rpmhpd SC7280_CX>; 1783 operating-points-v2 = <&qup_opp_table>; 1784 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1785 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1786 interconnect-names = "qup-core", "qup-config"; 1787 status = "disabled"; 1788 }; 1789 1790 i2c13: i2c@a94000 { 1791 compatible = "qcom,geni-i2c"; 1792 reg = <0 0x00a94000 0 0x4000>; 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1794 clock-names = "se"; 1795 pinctrl-names = "default"; 1796 pinctrl-0 = <&qup_i2c13_data_clk>; 1797 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1801 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1802 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1803 interconnect-names = "qup-core", "qup-config", 1804 "qup-memory"; 1805 power-domains = <&rpmhpd SC7280_CX>; 1806 required-opps = <&rpmhpd_opp_low_svs>; 1807 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1808 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1809 dma-names = "tx", "rx"; 1810 status = "disabled"; 1811 }; 1812 1813 spi13: spi@a94000 { 1814 compatible = "qcom,geni-spi"; 1815 reg = <0 0x00a94000 0 0x4000>; 1816 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1817 clock-names = "se"; 1818 pinctrl-names = "default"; 1819 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1820 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 power-domains = <&rpmhpd SC7280_CX>; 1824 operating-points-v2 = <&qup_opp_table>; 1825 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1826 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1827 interconnect-names = "qup-core", "qup-config"; 1828 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1829 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1830 dma-names = "tx", "rx"; 1831 status = "disabled"; 1832 }; 1833 1834 uart13: serial@a94000 { 1835 compatible = "qcom,geni-uart"; 1836 reg = <0 0x00a94000 0 0x4000>; 1837 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1838 clock-names = "se"; 1839 pinctrl-names = "default"; 1840 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1841 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1842 power-domains = <&rpmhpd SC7280_CX>; 1843 operating-points-v2 = <&qup_opp_table>; 1844 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1845 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1846 interconnect-names = "qup-core", "qup-config"; 1847 status = "disabled"; 1848 }; 1849 1850 i2c14: i2c@a98000 { 1851 compatible = "qcom,geni-i2c"; 1852 reg = <0 0x00a98000 0 0x4000>; 1853 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1854 clock-names = "se"; 1855 pinctrl-names = "default"; 1856 pinctrl-0 = <&qup_i2c14_data_clk>; 1857 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1861 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1862 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1863 interconnect-names = "qup-core", "qup-config", 1864 "qup-memory"; 1865 power-domains = <&rpmhpd SC7280_CX>; 1866 required-opps = <&rpmhpd_opp_low_svs>; 1867 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1868 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1869 dma-names = "tx", "rx"; 1870 status = "disabled"; 1871 }; 1872 1873 spi14: spi@a98000 { 1874 compatible = "qcom,geni-spi"; 1875 reg = <0 0x00a98000 0 0x4000>; 1876 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1877 clock-names = "se"; 1878 pinctrl-names = "default"; 1879 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1880 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1881 #address-cells = <1>; 1882 #size-cells = <0>; 1883 power-domains = <&rpmhpd SC7280_CX>; 1884 operating-points-v2 = <&qup_opp_table>; 1885 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1886 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1887 interconnect-names = "qup-core", "qup-config"; 1888 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1889 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1890 dma-names = "tx", "rx"; 1891 status = "disabled"; 1892 }; 1893 1894 uart14: serial@a98000 { 1895 compatible = "qcom,geni-uart"; 1896 reg = <0 0x00a98000 0 0x4000>; 1897 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1898 clock-names = "se"; 1899 pinctrl-names = "default"; 1900 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1901 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1902 power-domains = <&rpmhpd SC7280_CX>; 1903 operating-points-v2 = <&qup_opp_table>; 1904 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1905 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1906 interconnect-names = "qup-core", "qup-config"; 1907 status = "disabled"; 1908 }; 1909 1910 i2c15: i2c@a9c000 { 1911 compatible = "qcom,geni-i2c"; 1912 reg = <0 0x00a9c000 0 0x4000>; 1913 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1914 clock-names = "se"; 1915 pinctrl-names = "default"; 1916 pinctrl-0 = <&qup_i2c15_data_clk>; 1917 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1922 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1923 interconnect-names = "qup-core", "qup-config", 1924 "qup-memory"; 1925 power-domains = <&rpmhpd SC7280_CX>; 1926 required-opps = <&rpmhpd_opp_low_svs>; 1927 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1928 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1929 dma-names = "tx", "rx"; 1930 status = "disabled"; 1931 }; 1932 1933 spi15: spi@a9c000 { 1934 compatible = "qcom,geni-spi"; 1935 reg = <0 0x00a9c000 0 0x4000>; 1936 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1937 clock-names = "se"; 1938 pinctrl-names = "default"; 1939 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1940 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 power-domains = <&rpmhpd SC7280_CX>; 1944 operating-points-v2 = <&qup_opp_table>; 1945 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1946 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1947 interconnect-names = "qup-core", "qup-config"; 1948 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1949 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1950 dma-names = "tx", "rx"; 1951 status = "disabled"; 1952 }; 1953 1954 uart15: serial@a9c000 { 1955 compatible = "qcom,geni-uart"; 1956 reg = <0 0x00a9c000 0 0x4000>; 1957 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1958 clock-names = "se"; 1959 pinctrl-names = "default"; 1960 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1961 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1962 power-domains = <&rpmhpd SC7280_CX>; 1963 operating-points-v2 = <&qup_opp_table>; 1964 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1966 interconnect-names = "qup-core", "qup-config"; 1967 status = "disabled"; 1968 }; 1969 }; 1970 1971 cnoc2: interconnect@1500000 { 1972 reg = <0 0x01500000 0 0x1000>; 1973 compatible = "qcom,sc7280-cnoc2"; 1974 #interconnect-cells = <2>; 1975 qcom,bcm-voters = <&apps_bcm_voter>; 1976 }; 1977 1978 cnoc3: interconnect@1502000 { 1979 reg = <0 0x01502000 0 0x1000>; 1980 compatible = "qcom,sc7280-cnoc3"; 1981 #interconnect-cells = <2>; 1982 qcom,bcm-voters = <&apps_bcm_voter>; 1983 }; 1984 1985 mc_virt: interconnect@1580000 { 1986 reg = <0 0x01580000 0 0x4>; 1987 compatible = "qcom,sc7280-mc-virt"; 1988 #interconnect-cells = <2>; 1989 qcom,bcm-voters = <&apps_bcm_voter>; 1990 }; 1991 1992 system_noc: interconnect@1680000 { 1993 reg = <0 0x01680000 0 0x15480>; 1994 compatible = "qcom,sc7280-system-noc"; 1995 #interconnect-cells = <2>; 1996 qcom,bcm-voters = <&apps_bcm_voter>; 1997 }; 1998 1999 aggre1_noc: interconnect@16e0000 { 2000 compatible = "qcom,sc7280-aggre1-noc"; 2001 reg = <0 0x016e0000 0 0x1c080>; 2002 #interconnect-cells = <2>; 2003 qcom,bcm-voters = <&apps_bcm_voter>; 2004 }; 2005 2006 aggre2_noc: interconnect@1700000 { 2007 reg = <0 0x01700000 0 0x2b080>; 2008 compatible = "qcom,sc7280-aggre2-noc"; 2009 #interconnect-cells = <2>; 2010 qcom,bcm-voters = <&apps_bcm_voter>; 2011 }; 2012 2013 mmss_noc: interconnect@1740000 { 2014 reg = <0 0x01740000 0 0x1e080>; 2015 compatible = "qcom,sc7280-mmss-noc"; 2016 #interconnect-cells = <2>; 2017 qcom,bcm-voters = <&apps_bcm_voter>; 2018 }; 2019 2020 wifi: wifi@17a10040 { 2021 compatible = "qcom,wcn6750-wifi"; 2022 reg = <0 0x17a10040 0 0x0>; 2023 iommus = <&apps_smmu 0x1c00 0x1>; 2024 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2025 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2026 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2027 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2028 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2029 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2030 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2031 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2056 qcom,rproc = <&remoteproc_wpss>; 2057 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2058 status = "disabled"; 2059 qcom,smem-states = <&wlan_smp2p_out 0>; 2060 qcom,smem-state-names = "wlan-smp2p-out"; 2061 }; 2062 2063 pcie1: pci@1c08000 { 2064 compatible = "qcom,pcie-sc7280"; 2065 reg = <0 0x01c08000 0 0x3000>, 2066 <0 0x40000000 0 0xf1d>, 2067 <0 0x40000f20 0 0xa8>, 2068 <0 0x40001000 0 0x1000>, 2069 <0 0x40100000 0 0x100000>; 2070 2071 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2072 device_type = "pci"; 2073 linux,pci-domain = <1>; 2074 bus-range = <0x00 0xff>; 2075 num-lanes = <2>; 2076 2077 #address-cells = <3>; 2078 #size-cells = <2>; 2079 2080 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2081 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2082 2083 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2084 interrupt-names = "msi"; 2085 #interrupt-cells = <1>; 2086 interrupt-map-mask = <0 0 0 0x7>; 2087 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2088 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2089 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2090 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2091 2092 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2093 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2094 <&pcie1_lane>, 2095 <&rpmhcc RPMH_CXO_CLK>, 2096 <&gcc GCC_PCIE_1_AUX_CLK>, 2097 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2098 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2099 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2100 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2101 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2102 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2103 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2104 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2105 2106 clock-names = "pipe", 2107 "pipe_mux", 2108 "phy_pipe", 2109 "ref", 2110 "aux", 2111 "cfg", 2112 "bus_master", 2113 "bus_slave", 2114 "slave_q2a", 2115 "tbu", 2116 "ddrss_sf_tbu", 2117 "aggre0", 2118 "aggre1"; 2119 2120 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2121 assigned-clock-rates = <19200000>; 2122 2123 resets = <&gcc GCC_PCIE_1_BCR>; 2124 reset-names = "pci"; 2125 2126 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2127 2128 phys = <&pcie1_lane>; 2129 phy-names = "pciephy"; 2130 2131 pinctrl-names = "default"; 2132 pinctrl-0 = <&pcie1_clkreq_n>; 2133 2134 dma-coherent; 2135 2136 iommus = <&apps_smmu 0x1c80 0x1>; 2137 2138 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2139 <0x100 &apps_smmu 0x1c81 0x1>; 2140 2141 status = "disabled"; 2142 }; 2143 2144 pcie1_phy: phy@1c0e000 { 2145 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2146 reg = <0 0x01c0e000 0 0x1c0>; 2147 #address-cells = <2>; 2148 #size-cells = <2>; 2149 ranges; 2150 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2151 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2152 <&gcc GCC_PCIE_CLKREF_EN>, 2153 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2154 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2155 2156 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2157 reset-names = "phy"; 2158 2159 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2160 assigned-clock-rates = <100000000>; 2161 2162 status = "disabled"; 2163 2164 pcie1_lane: phy@1c0e200 { 2165 reg = <0 0x01c0e200 0 0x170>, 2166 <0 0x01c0e400 0 0x200>, 2167 <0 0x01c0ea00 0 0x1f0>, 2168 <0 0x01c0e600 0 0x170>, 2169 <0 0x01c0e800 0 0x200>, 2170 <0 0x01c0ee00 0 0xf4>; 2171 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2172 clock-names = "pipe0"; 2173 2174 #phy-cells = <0>; 2175 #clock-cells = <0>; 2176 clock-output-names = "pcie_1_pipe_clk"; 2177 }; 2178 }; 2179 2180 ipa: ipa@1e40000 { 2181 compatible = "qcom,sc7280-ipa"; 2182 2183 iommus = <&apps_smmu 0x480 0x0>, 2184 <&apps_smmu 0x482 0x0>; 2185 reg = <0 0x01e40000 0 0x8000>, 2186 <0 0x01e50000 0 0x4ad0>, 2187 <0 0x01e04000 0 0x23000>; 2188 reg-names = "ipa-reg", 2189 "ipa-shared", 2190 "gsi"; 2191 2192 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2193 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2194 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2195 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2196 interrupt-names = "ipa", 2197 "gsi", 2198 "ipa-clock-query", 2199 "ipa-setup-ready"; 2200 2201 clocks = <&rpmhcc RPMH_IPA_CLK>; 2202 clock-names = "core"; 2203 2204 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2205 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2206 interconnect-names = "memory", 2207 "config"; 2208 2209 qcom,qmp = <&aoss_qmp>; 2210 2211 qcom,smem-states = <&ipa_smp2p_out 0>, 2212 <&ipa_smp2p_out 1>; 2213 qcom,smem-state-names = "ipa-clock-enabled-valid", 2214 "ipa-clock-enabled"; 2215 2216 status = "disabled"; 2217 }; 2218 2219 tcsr_mutex: hwlock@1f40000 { 2220 compatible = "qcom,tcsr-mutex"; 2221 reg = <0 0x01f40000 0 0x20000>; 2222 #hwlock-cells = <1>; 2223 }; 2224 2225 tcsr_1: syscon@1f60000 { 2226 compatible = "qcom,sc7280-tcsr", "syscon"; 2227 reg = <0 0x01f60000 0 0x20000>; 2228 }; 2229 2230 tcsr_2: syscon@1fc0000 { 2231 compatible = "qcom,sc7280-tcsr", "syscon"; 2232 reg = <0 0x01fc0000 0 0x30000>; 2233 }; 2234 2235 lpasscc: lpasscc@3000000 { 2236 compatible = "qcom,sc7280-lpasscc"; 2237 reg = <0 0x03000000 0 0x40>, 2238 <0 0x03c04000 0 0x4>; 2239 reg-names = "qdsp6ss", "top_cc"; 2240 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2241 clock-names = "iface"; 2242 #clock-cells = <1>; 2243 }; 2244 2245 lpass_rx_macro: codec@3200000 { 2246 compatible = "qcom,sc7280-lpass-rx-macro"; 2247 reg = <0 0x03200000 0 0x1000>; 2248 2249 pinctrl-names = "default"; 2250 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2251 2252 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2253 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2254 <&lpass_va_macro>; 2255 clock-names = "mclk", "npl", "fsgen"; 2256 2257 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2258 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2259 power-domain-names = "macro", "dcodec"; 2260 2261 #clock-cells = <0>; 2262 #sound-dai-cells = <1>; 2263 2264 status = "disabled"; 2265 }; 2266 2267 swr0: soundwire@3210000 { 2268 compatible = "qcom,soundwire-v1.6.0"; 2269 reg = <0 0x03210000 0 0x2000>; 2270 2271 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2272 clocks = <&lpass_rx_macro>; 2273 clock-names = "iface"; 2274 2275 qcom,din-ports = <0>; 2276 qcom,dout-ports = <5>; 2277 2278 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2279 reset-names = "swr_audio_cgcr"; 2280 2281 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2282 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2283 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2284 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2285 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2286 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2287 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2288 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2289 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2290 2291 #sound-dai-cells = <1>; 2292 #address-cells = <2>; 2293 #size-cells = <0>; 2294 2295 status = "disabled"; 2296 }; 2297 2298 lpass_tx_macro: codec@3220000 { 2299 compatible = "qcom,sc7280-lpass-tx-macro"; 2300 reg = <0 0x03220000 0 0x1000>; 2301 2302 pinctrl-names = "default"; 2303 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2304 2305 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2306 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2307 <&lpass_va_macro>; 2308 clock-names = "mclk", "npl", "fsgen"; 2309 2310 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2311 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2312 power-domain-names = "macro", "dcodec"; 2313 2314 #clock-cells = <0>; 2315 #sound-dai-cells = <1>; 2316 2317 status = "disabled"; 2318 }; 2319 2320 swr1: soundwire@3230000 { 2321 compatible = "qcom,soundwire-v1.6.0"; 2322 reg = <0 0x03230000 0 0x2000>; 2323 2324 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2325 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2326 clocks = <&lpass_tx_macro>; 2327 clock-names = "iface"; 2328 2329 qcom,din-ports = <3>; 2330 qcom,dout-ports = <0>; 2331 2332 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2333 reset-names = "swr_audio_cgcr"; 2334 2335 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2336 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2337 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2338 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2339 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2340 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2341 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2342 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2343 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2344 2345 #sound-dai-cells = <1>; 2346 #address-cells = <2>; 2347 #size-cells = <0>; 2348 2349 status = "disabled"; 2350 }; 2351 2352 lpass_audiocc: clock-controller@3300000 { 2353 compatible = "qcom,sc7280-lpassaudiocc"; 2354 reg = <0 0x03300000 0 0x30000>, 2355 <0 0x032a9000 0 0x1000>; 2356 clocks = <&rpmhcc RPMH_CXO_CLK>, 2357 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2358 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2359 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2360 #clock-cells = <1>; 2361 #power-domain-cells = <1>; 2362 #reset-cells = <1>; 2363 }; 2364 2365 lpass_va_macro: codec@3370000 { 2366 compatible = "qcom,sc7280-lpass-va-macro"; 2367 reg = <0 0x03370000 0 0x1000>; 2368 2369 pinctrl-names = "default"; 2370 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2371 2372 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2373 clock-names = "mclk"; 2374 2375 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2376 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2377 power-domain-names = "macro", "dcodec"; 2378 2379 #clock-cells = <0>; 2380 #sound-dai-cells = <1>; 2381 2382 status = "disabled"; 2383 }; 2384 2385 lpass_aon: clock-controller@3380000 { 2386 compatible = "qcom,sc7280-lpassaoncc"; 2387 reg = <0 0x03380000 0 0x30000>; 2388 clocks = <&rpmhcc RPMH_CXO_CLK>, 2389 <&rpmhcc RPMH_CXO_CLK_A>, 2390 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2391 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2392 #clock-cells = <1>; 2393 #power-domain-cells = <1>; 2394 }; 2395 2396 lpass_core: clock-controller@3900000 { 2397 compatible = "qcom,sc7280-lpasscorecc"; 2398 reg = <0 0x03900000 0 0x50000>; 2399 clocks = <&rpmhcc RPMH_CXO_CLK>; 2400 clock-names = "bi_tcxo"; 2401 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2402 #clock-cells = <1>; 2403 #power-domain-cells = <1>; 2404 }; 2405 2406 lpass_cpu: audio@3987000 { 2407 compatible = "qcom,sc7280-lpass-cpu"; 2408 2409 reg = <0 0x03987000 0 0x68000>, 2410 <0 0x03b00000 0 0x29000>, 2411 <0 0x03260000 0 0xc000>, 2412 <0 0x03280000 0 0x29000>, 2413 <0 0x03340000 0 0x29000>, 2414 <0 0x0336c000 0 0x3000>; 2415 reg-names = "lpass-hdmiif", 2416 "lpass-lpaif", 2417 "lpass-rxtx-cdc-dma-lpm", 2418 "lpass-rxtx-lpaif", 2419 "lpass-va-lpaif", 2420 "lpass-va-cdc-dma-lpm"; 2421 2422 iommus = <&apps_smmu 0x1820 0>, 2423 <&apps_smmu 0x1821 0>, 2424 <&apps_smmu 0x1832 0>; 2425 2426 power-domains = <&rpmhpd SC7280_LCX>; 2427 power-domain-names = "lcx"; 2428 required-opps = <&rpmhpd_opp_nom>; 2429 2430 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2431 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2432 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2433 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2434 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2435 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2436 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2437 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2438 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2439 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2440 clock-names = "aon_cc_audio_hm_h", 2441 "audio_cc_ext_mclk0", 2442 "core_cc_sysnoc_mport_core", 2443 "core_cc_ext_if0_ibit", 2444 "core_cc_ext_if1_ibit", 2445 "audio_cc_codec_mem", 2446 "audio_cc_codec_mem0", 2447 "audio_cc_codec_mem1", 2448 "audio_cc_codec_mem2", 2449 "aon_cc_va_mem0"; 2450 2451 #sound-dai-cells = <1>; 2452 #address-cells = <1>; 2453 #size-cells = <0>; 2454 2455 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2459 interrupt-names = "lpass-irq-lpaif", 2460 "lpass-irq-hdmi", 2461 "lpass-irq-vaif", 2462 "lpass-irq-rxtxif"; 2463 2464 status = "disabled"; 2465 }; 2466 2467 lpass_hm: clock-controller@3c00000 { 2468 compatible = "qcom,sc7280-lpasshm"; 2469 reg = <0 0x03c00000 0 0x28>; 2470 clocks = <&rpmhcc RPMH_CXO_CLK>; 2471 clock-names = "bi_tcxo"; 2472 #clock-cells = <1>; 2473 #power-domain-cells = <1>; 2474 }; 2475 2476 lpass_ag_noc: interconnect@3c40000 { 2477 reg = <0 0x03c40000 0 0xf080>; 2478 compatible = "qcom,sc7280-lpass-ag-noc"; 2479 #interconnect-cells = <2>; 2480 qcom,bcm-voters = <&apps_bcm_voter>; 2481 }; 2482 2483 lpass_tlmm: pinctrl@33c0000 { 2484 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2485 reg = <0 0x033c0000 0x0 0x20000>, 2486 <0 0x03550000 0x0 0x10000>; 2487 qcom,adsp-bypass-mode; 2488 gpio-controller; 2489 #gpio-cells = <2>; 2490 gpio-ranges = <&lpass_tlmm 0 0 15>; 2491 2492 lpass_dmic01_clk: dmic01-clk-state { 2493 pins = "gpio6"; 2494 function = "dmic1_clk"; 2495 }; 2496 2497 lpass_dmic01_data: dmic01-data-state { 2498 pins = "gpio7"; 2499 function = "dmic1_data"; 2500 }; 2501 2502 lpass_dmic23_clk: dmic23-clk-state { 2503 pins = "gpio8"; 2504 function = "dmic2_clk"; 2505 }; 2506 2507 lpass_dmic23_data: dmic23-data-state { 2508 pins = "gpio9"; 2509 function = "dmic2_data"; 2510 }; 2511 2512 lpass_rx_swr_clk: rx-swr-clk-state { 2513 pins = "gpio3"; 2514 function = "swr_rx_clk"; 2515 }; 2516 2517 lpass_rx_swr_data: rx-swr-data-state { 2518 pins = "gpio4", "gpio5"; 2519 function = "swr_rx_data"; 2520 }; 2521 2522 lpass_tx_swr_clk: tx-swr-clk-state { 2523 pins = "gpio0"; 2524 function = "swr_tx_clk"; 2525 }; 2526 2527 lpass_tx_swr_data: tx-swr-data-state { 2528 pins = "gpio1", "gpio2", "gpio14"; 2529 function = "swr_tx_data"; 2530 }; 2531 }; 2532 2533 gpu: gpu@3d00000 { 2534 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2535 reg = <0 0x03d00000 0 0x40000>, 2536 <0 0x03d9e000 0 0x1000>, 2537 <0 0x03d61000 0 0x800>; 2538 reg-names = "kgsl_3d0_reg_memory", 2539 "cx_mem", 2540 "cx_dbgc"; 2541 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2542 iommus = <&adreno_smmu 0 0x401>; 2543 operating-points-v2 = <&gpu_opp_table>; 2544 qcom,gmu = <&gmu>; 2545 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2546 interconnect-names = "gfx-mem"; 2547 #cooling-cells = <2>; 2548 2549 nvmem-cells = <&gpu_speed_bin>; 2550 nvmem-cell-names = "speed_bin"; 2551 2552 gpu_opp_table: opp-table { 2553 compatible = "operating-points-v2"; 2554 2555 opp-315000000 { 2556 opp-hz = /bits/ 64 <315000000>; 2557 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2558 opp-peak-kBps = <1804000>; 2559 opp-supported-hw = <0x03>; 2560 }; 2561 2562 opp-450000000 { 2563 opp-hz = /bits/ 64 <450000000>; 2564 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2565 opp-peak-kBps = <4068000>; 2566 opp-supported-hw = <0x03>; 2567 }; 2568 2569 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2570 opp-550000000-0 { 2571 opp-hz = /bits/ 64 <550000000>; 2572 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2573 opp-peak-kBps = <8368000>; 2574 opp-supported-hw = <0x01>; 2575 }; 2576 2577 opp-550000000-1 { 2578 opp-hz = /bits/ 64 <550000000>; 2579 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2580 opp-peak-kBps = <6832000>; 2581 opp-supported-hw = <0x02>; 2582 }; 2583 2584 opp-608000000 { 2585 opp-hz = /bits/ 64 <608000000>; 2586 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2587 opp-peak-kBps = <8368000>; 2588 opp-supported-hw = <0x02>; 2589 }; 2590 2591 opp-700000000 { 2592 opp-hz = /bits/ 64 <700000000>; 2593 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2594 opp-peak-kBps = <8532000>; 2595 opp-supported-hw = <0x02>; 2596 }; 2597 2598 opp-812000000 { 2599 opp-hz = /bits/ 64 <812000000>; 2600 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2601 opp-peak-kBps = <8532000>; 2602 opp-supported-hw = <0x02>; 2603 }; 2604 2605 opp-840000000 { 2606 opp-hz = /bits/ 64 <840000000>; 2607 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2608 opp-peak-kBps = <8532000>; 2609 opp-supported-hw = <0x02>; 2610 }; 2611 2612 opp-900000000 { 2613 opp-hz = /bits/ 64 <900000000>; 2614 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2615 opp-peak-kBps = <8532000>; 2616 opp-supported-hw = <0x02>; 2617 }; 2618 }; 2619 }; 2620 2621 gmu: gmu@3d6a000 { 2622 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2623 reg = <0 0x03d6a000 0 0x34000>, 2624 <0 0x3de0000 0 0x10000>, 2625 <0 0x0b290000 0 0x10000>; 2626 reg-names = "gmu", "rscc", "gmu_pdc"; 2627 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2629 interrupt-names = "hfi", "gmu"; 2630 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2631 <&gpucc GPU_CC_CXO_CLK>, 2632 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2633 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2634 <&gpucc GPU_CC_AHB_CLK>, 2635 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2636 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2637 clock-names = "gmu", 2638 "cxo", 2639 "axi", 2640 "memnoc", 2641 "ahb", 2642 "hub", 2643 "smmu_vote"; 2644 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2645 <&gpucc GPU_CC_GX_GDSC>; 2646 power-domain-names = "cx", 2647 "gx"; 2648 iommus = <&adreno_smmu 5 0x400>; 2649 operating-points-v2 = <&gmu_opp_table>; 2650 2651 gmu_opp_table: opp-table { 2652 compatible = "operating-points-v2"; 2653 2654 opp-200000000 { 2655 opp-hz = /bits/ 64 <200000000>; 2656 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2657 }; 2658 }; 2659 }; 2660 2661 gpucc: clock-controller@3d90000 { 2662 compatible = "qcom,sc7280-gpucc"; 2663 reg = <0 0x03d90000 0 0x9000>; 2664 clocks = <&rpmhcc RPMH_CXO_CLK>, 2665 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2666 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2667 clock-names = "bi_tcxo", 2668 "gcc_gpu_gpll0_clk_src", 2669 "gcc_gpu_gpll0_div_clk_src"; 2670 #clock-cells = <1>; 2671 #reset-cells = <1>; 2672 #power-domain-cells = <1>; 2673 }; 2674 2675 dma@117f000 { 2676 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2677 reg = <0x0 0x0117f000 0x0 0x1000>, 2678 <0x0 0x01112000 0x0 0x6000>; 2679 }; 2680 2681 adreno_smmu: iommu@3da0000 { 2682 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2683 reg = <0 0x03da0000 0 0x20000>; 2684 #iommu-cells = <2>; 2685 #global-interrupts = <2>; 2686 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2687 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2688 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2689 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2690 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2691 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2698 2699 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2700 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2701 <&gpucc GPU_CC_AHB_CLK>, 2702 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2703 <&gpucc GPU_CC_CX_GMU_CLK>, 2704 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2705 <&gpucc GPU_CC_HUB_AON_CLK>; 2706 clock-names = "gcc_gpu_memnoc_gfx_clk", 2707 "gcc_gpu_snoc_dvm_gfx_clk", 2708 "gpu_cc_ahb_clk", 2709 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2710 "gpu_cc_cx_gmu_clk", 2711 "gpu_cc_hub_cx_int_clk", 2712 "gpu_cc_hub_aon_clk"; 2713 2714 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2715 }; 2716 2717 remoteproc_mpss: remoteproc@4080000 { 2718 compatible = "qcom,sc7280-mpss-pas"; 2719 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2720 reg-names = "qdsp6", "rmb"; 2721 2722 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2723 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2724 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2725 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2726 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2727 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2728 interrupt-names = "wdog", "fatal", "ready", "handover", 2729 "stop-ack", "shutdown-ack"; 2730 2731 clocks = <&rpmhcc RPMH_CXO_CLK>; 2732 clock-names = "xo"; 2733 2734 power-domains = <&rpmhpd SC7280_CX>, 2735 <&rpmhpd SC7280_MSS>; 2736 power-domain-names = "cx", "mss"; 2737 2738 memory-region = <&mpss_mem>; 2739 2740 qcom,qmp = <&aoss_qmp>; 2741 2742 qcom,smem-states = <&modem_smp2p_out 0>; 2743 qcom,smem-state-names = "stop"; 2744 2745 status = "disabled"; 2746 2747 glink-edge { 2748 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2749 IPCC_MPROC_SIGNAL_GLINK_QMP 2750 IRQ_TYPE_EDGE_RISING>; 2751 mboxes = <&ipcc IPCC_CLIENT_MPSS 2752 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2753 label = "modem"; 2754 qcom,remote-pid = <1>; 2755 }; 2756 }; 2757 2758 stm@6002000 { 2759 compatible = "arm,coresight-stm", "arm,primecell"; 2760 reg = <0 0x06002000 0 0x1000>, 2761 <0 0x16280000 0 0x180000>; 2762 reg-names = "stm-base", "stm-stimulus-base"; 2763 2764 clocks = <&aoss_qmp>; 2765 clock-names = "apb_pclk"; 2766 2767 out-ports { 2768 port { 2769 stm_out: endpoint { 2770 remote-endpoint = <&funnel0_in7>; 2771 }; 2772 }; 2773 }; 2774 }; 2775 2776 funnel@6041000 { 2777 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2778 reg = <0 0x06041000 0 0x1000>; 2779 2780 clocks = <&aoss_qmp>; 2781 clock-names = "apb_pclk"; 2782 2783 out-ports { 2784 port { 2785 funnel0_out: endpoint { 2786 remote-endpoint = <&merge_funnel_in0>; 2787 }; 2788 }; 2789 }; 2790 2791 in-ports { 2792 #address-cells = <1>; 2793 #size-cells = <0>; 2794 2795 port@7 { 2796 reg = <7>; 2797 funnel0_in7: endpoint { 2798 remote-endpoint = <&stm_out>; 2799 }; 2800 }; 2801 }; 2802 }; 2803 2804 funnel@6042000 { 2805 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2806 reg = <0 0x06042000 0 0x1000>; 2807 2808 clocks = <&aoss_qmp>; 2809 clock-names = "apb_pclk"; 2810 2811 out-ports { 2812 port { 2813 funnel1_out: endpoint { 2814 remote-endpoint = <&merge_funnel_in1>; 2815 }; 2816 }; 2817 }; 2818 2819 in-ports { 2820 #address-cells = <1>; 2821 #size-cells = <0>; 2822 2823 port@4 { 2824 reg = <4>; 2825 funnel1_in4: endpoint { 2826 remote-endpoint = <&apss_merge_funnel_out>; 2827 }; 2828 }; 2829 }; 2830 }; 2831 2832 funnel@6045000 { 2833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2834 reg = <0 0x06045000 0 0x1000>; 2835 2836 clocks = <&aoss_qmp>; 2837 clock-names = "apb_pclk"; 2838 2839 out-ports { 2840 port { 2841 merge_funnel_out: endpoint { 2842 remote-endpoint = <&swao_funnel_in>; 2843 }; 2844 }; 2845 }; 2846 2847 in-ports { 2848 #address-cells = <1>; 2849 #size-cells = <0>; 2850 2851 port@0 { 2852 reg = <0>; 2853 merge_funnel_in0: endpoint { 2854 remote-endpoint = <&funnel0_out>; 2855 }; 2856 }; 2857 2858 port@1 { 2859 reg = <1>; 2860 merge_funnel_in1: endpoint { 2861 remote-endpoint = <&funnel1_out>; 2862 }; 2863 }; 2864 }; 2865 }; 2866 2867 replicator@6046000 { 2868 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2869 reg = <0 0x06046000 0 0x1000>; 2870 2871 clocks = <&aoss_qmp>; 2872 clock-names = "apb_pclk"; 2873 2874 out-ports { 2875 port { 2876 replicator_out: endpoint { 2877 remote-endpoint = <&etr_in>; 2878 }; 2879 }; 2880 }; 2881 2882 in-ports { 2883 port { 2884 replicator_in: endpoint { 2885 remote-endpoint = <&swao_replicator_out>; 2886 }; 2887 }; 2888 }; 2889 }; 2890 2891 etr@6048000 { 2892 compatible = "arm,coresight-tmc", "arm,primecell"; 2893 reg = <0 0x06048000 0 0x1000>; 2894 iommus = <&apps_smmu 0x04c0 0>; 2895 2896 clocks = <&aoss_qmp>; 2897 clock-names = "apb_pclk"; 2898 arm,scatter-gather; 2899 2900 in-ports { 2901 port { 2902 etr_in: endpoint { 2903 remote-endpoint = <&replicator_out>; 2904 }; 2905 }; 2906 }; 2907 }; 2908 2909 funnel@6b04000 { 2910 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2911 reg = <0 0x06b04000 0 0x1000>; 2912 2913 clocks = <&aoss_qmp>; 2914 clock-names = "apb_pclk"; 2915 2916 out-ports { 2917 port { 2918 swao_funnel_out: endpoint { 2919 remote-endpoint = <&etf_in>; 2920 }; 2921 }; 2922 }; 2923 2924 in-ports { 2925 #address-cells = <1>; 2926 #size-cells = <0>; 2927 2928 port@7 { 2929 reg = <7>; 2930 swao_funnel_in: endpoint { 2931 remote-endpoint = <&merge_funnel_out>; 2932 }; 2933 }; 2934 }; 2935 }; 2936 2937 etf@6b05000 { 2938 compatible = "arm,coresight-tmc", "arm,primecell"; 2939 reg = <0 0x06b05000 0 0x1000>; 2940 2941 clocks = <&aoss_qmp>; 2942 clock-names = "apb_pclk"; 2943 2944 out-ports { 2945 port { 2946 etf_out: endpoint { 2947 remote-endpoint = <&swao_replicator_in>; 2948 }; 2949 }; 2950 }; 2951 2952 in-ports { 2953 port { 2954 etf_in: endpoint { 2955 remote-endpoint = <&swao_funnel_out>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 replicator@6b06000 { 2962 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2963 reg = <0 0x06b06000 0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 qcom,replicator-loses-context; 2968 2969 out-ports { 2970 port { 2971 swao_replicator_out: endpoint { 2972 remote-endpoint = <&replicator_in>; 2973 }; 2974 }; 2975 }; 2976 2977 in-ports { 2978 port { 2979 swao_replicator_in: endpoint { 2980 remote-endpoint = <&etf_out>; 2981 }; 2982 }; 2983 }; 2984 }; 2985 2986 etm@7040000 { 2987 compatible = "arm,coresight-etm4x", "arm,primecell"; 2988 reg = <0 0x07040000 0 0x1000>; 2989 2990 cpu = <&CPU0>; 2991 2992 clocks = <&aoss_qmp>; 2993 clock-names = "apb_pclk"; 2994 arm,coresight-loses-context-with-cpu; 2995 qcom,skip-power-up; 2996 2997 out-ports { 2998 port { 2999 etm0_out: endpoint { 3000 remote-endpoint = <&apss_funnel_in0>; 3001 }; 3002 }; 3003 }; 3004 }; 3005 3006 etm@7140000 { 3007 compatible = "arm,coresight-etm4x", "arm,primecell"; 3008 reg = <0 0x07140000 0 0x1000>; 3009 3010 cpu = <&CPU1>; 3011 3012 clocks = <&aoss_qmp>; 3013 clock-names = "apb_pclk"; 3014 arm,coresight-loses-context-with-cpu; 3015 qcom,skip-power-up; 3016 3017 out-ports { 3018 port { 3019 etm1_out: endpoint { 3020 remote-endpoint = <&apss_funnel_in1>; 3021 }; 3022 }; 3023 }; 3024 }; 3025 3026 etm@7240000 { 3027 compatible = "arm,coresight-etm4x", "arm,primecell"; 3028 reg = <0 0x07240000 0 0x1000>; 3029 3030 cpu = <&CPU2>; 3031 3032 clocks = <&aoss_qmp>; 3033 clock-names = "apb_pclk"; 3034 arm,coresight-loses-context-with-cpu; 3035 qcom,skip-power-up; 3036 3037 out-ports { 3038 port { 3039 etm2_out: endpoint { 3040 remote-endpoint = <&apss_funnel_in2>; 3041 }; 3042 }; 3043 }; 3044 }; 3045 3046 etm@7340000 { 3047 compatible = "arm,coresight-etm4x", "arm,primecell"; 3048 reg = <0 0x07340000 0 0x1000>; 3049 3050 cpu = <&CPU3>; 3051 3052 clocks = <&aoss_qmp>; 3053 clock-names = "apb_pclk"; 3054 arm,coresight-loses-context-with-cpu; 3055 qcom,skip-power-up; 3056 3057 out-ports { 3058 port { 3059 etm3_out: endpoint { 3060 remote-endpoint = <&apss_funnel_in3>; 3061 }; 3062 }; 3063 }; 3064 }; 3065 3066 etm@7440000 { 3067 compatible = "arm,coresight-etm4x", "arm,primecell"; 3068 reg = <0 0x07440000 0 0x1000>; 3069 3070 cpu = <&CPU4>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 arm,coresight-loses-context-with-cpu; 3075 qcom,skip-power-up; 3076 3077 out-ports { 3078 port { 3079 etm4_out: endpoint { 3080 remote-endpoint = <&apss_funnel_in4>; 3081 }; 3082 }; 3083 }; 3084 }; 3085 3086 etm@7540000 { 3087 compatible = "arm,coresight-etm4x", "arm,primecell"; 3088 reg = <0 0x07540000 0 0x1000>; 3089 3090 cpu = <&CPU5>; 3091 3092 clocks = <&aoss_qmp>; 3093 clock-names = "apb_pclk"; 3094 arm,coresight-loses-context-with-cpu; 3095 qcom,skip-power-up; 3096 3097 out-ports { 3098 port { 3099 etm5_out: endpoint { 3100 remote-endpoint = <&apss_funnel_in5>; 3101 }; 3102 }; 3103 }; 3104 }; 3105 3106 etm@7640000 { 3107 compatible = "arm,coresight-etm4x", "arm,primecell"; 3108 reg = <0 0x07640000 0 0x1000>; 3109 3110 cpu = <&CPU6>; 3111 3112 clocks = <&aoss_qmp>; 3113 clock-names = "apb_pclk"; 3114 arm,coresight-loses-context-with-cpu; 3115 qcom,skip-power-up; 3116 3117 out-ports { 3118 port { 3119 etm6_out: endpoint { 3120 remote-endpoint = <&apss_funnel_in6>; 3121 }; 3122 }; 3123 }; 3124 }; 3125 3126 etm@7740000 { 3127 compatible = "arm,coresight-etm4x", "arm,primecell"; 3128 reg = <0 0x07740000 0 0x1000>; 3129 3130 cpu = <&CPU7>; 3131 3132 clocks = <&aoss_qmp>; 3133 clock-names = "apb_pclk"; 3134 arm,coresight-loses-context-with-cpu; 3135 qcom,skip-power-up; 3136 3137 out-ports { 3138 port { 3139 etm7_out: endpoint { 3140 remote-endpoint = <&apss_funnel_in7>; 3141 }; 3142 }; 3143 }; 3144 }; 3145 3146 funnel@7800000 { /* APSS Funnel */ 3147 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3148 reg = <0 0x07800000 0 0x1000>; 3149 3150 clocks = <&aoss_qmp>; 3151 clock-names = "apb_pclk"; 3152 3153 out-ports { 3154 port { 3155 apss_funnel_out: endpoint { 3156 remote-endpoint = <&apss_merge_funnel_in>; 3157 }; 3158 }; 3159 }; 3160 3161 in-ports { 3162 #address-cells = <1>; 3163 #size-cells = <0>; 3164 3165 port@0 { 3166 reg = <0>; 3167 apss_funnel_in0: endpoint { 3168 remote-endpoint = <&etm0_out>; 3169 }; 3170 }; 3171 3172 port@1 { 3173 reg = <1>; 3174 apss_funnel_in1: endpoint { 3175 remote-endpoint = <&etm1_out>; 3176 }; 3177 }; 3178 3179 port@2 { 3180 reg = <2>; 3181 apss_funnel_in2: endpoint { 3182 remote-endpoint = <&etm2_out>; 3183 }; 3184 }; 3185 3186 port@3 { 3187 reg = <3>; 3188 apss_funnel_in3: endpoint { 3189 remote-endpoint = <&etm3_out>; 3190 }; 3191 }; 3192 3193 port@4 { 3194 reg = <4>; 3195 apss_funnel_in4: endpoint { 3196 remote-endpoint = <&etm4_out>; 3197 }; 3198 }; 3199 3200 port@5 { 3201 reg = <5>; 3202 apss_funnel_in5: endpoint { 3203 remote-endpoint = <&etm5_out>; 3204 }; 3205 }; 3206 3207 port@6 { 3208 reg = <6>; 3209 apss_funnel_in6: endpoint { 3210 remote-endpoint = <&etm6_out>; 3211 }; 3212 }; 3213 3214 port@7 { 3215 reg = <7>; 3216 apss_funnel_in7: endpoint { 3217 remote-endpoint = <&etm7_out>; 3218 }; 3219 }; 3220 }; 3221 }; 3222 3223 funnel@7810000 { 3224 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3225 reg = <0 0x07810000 0 0x1000>; 3226 3227 clocks = <&aoss_qmp>; 3228 clock-names = "apb_pclk"; 3229 3230 out-ports { 3231 port { 3232 apss_merge_funnel_out: endpoint { 3233 remote-endpoint = <&funnel1_in4>; 3234 }; 3235 }; 3236 }; 3237 3238 in-ports { 3239 port { 3240 apss_merge_funnel_in: endpoint { 3241 remote-endpoint = <&apss_funnel_out>; 3242 }; 3243 }; 3244 }; 3245 }; 3246 3247 sdhc_2: mmc@8804000 { 3248 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3249 pinctrl-names = "default", "sleep"; 3250 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3251 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3252 status = "disabled"; 3253 3254 reg = <0 0x08804000 0 0x1000>; 3255 3256 iommus = <&apps_smmu 0x100 0x0>; 3257 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3259 interrupt-names = "hc_irq", "pwr_irq"; 3260 3261 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3262 <&gcc GCC_SDCC2_APPS_CLK>, 3263 <&rpmhcc RPMH_CXO_CLK>; 3264 clock-names = "iface", "core", "xo"; 3265 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3266 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3267 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3268 power-domains = <&rpmhpd SC7280_CX>; 3269 operating-points-v2 = <&sdhc2_opp_table>; 3270 3271 bus-width = <4>; 3272 3273 qcom,dll-config = <0x0007642c>; 3274 3275 resets = <&gcc GCC_SDCC2_BCR>; 3276 3277 sdhc2_opp_table: opp-table { 3278 compatible = "operating-points-v2"; 3279 3280 opp-100000000 { 3281 opp-hz = /bits/ 64 <100000000>; 3282 required-opps = <&rpmhpd_opp_low_svs>; 3283 opp-peak-kBps = <1800000 400000>; 3284 opp-avg-kBps = <100000 0>; 3285 }; 3286 3287 opp-202000000 { 3288 opp-hz = /bits/ 64 <202000000>; 3289 required-opps = <&rpmhpd_opp_nom>; 3290 opp-peak-kBps = <5400000 1600000>; 3291 opp-avg-kBps = <200000 0>; 3292 }; 3293 }; 3294 3295 }; 3296 3297 usb_1_hsphy: phy@88e3000 { 3298 compatible = "qcom,sc7280-usb-hs-phy", 3299 "qcom,usb-snps-hs-7nm-phy"; 3300 reg = <0 0x088e3000 0 0x400>; 3301 status = "disabled"; 3302 #phy-cells = <0>; 3303 3304 clocks = <&rpmhcc RPMH_CXO_CLK>; 3305 clock-names = "ref"; 3306 3307 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3308 }; 3309 3310 usb_2_hsphy: phy@88e4000 { 3311 compatible = "qcom,sc7280-usb-hs-phy", 3312 "qcom,usb-snps-hs-7nm-phy"; 3313 reg = <0 0x088e4000 0 0x400>; 3314 status = "disabled"; 3315 #phy-cells = <0>; 3316 3317 clocks = <&rpmhcc RPMH_CXO_CLK>; 3318 clock-names = "ref"; 3319 3320 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3321 }; 3322 3323 usb_1_qmpphy: phy-wrapper@88e9000 { 3324 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3325 "qcom,sm8250-qmp-usb3-dp-phy"; 3326 reg = <0 0x088e9000 0 0x200>, 3327 <0 0x088e8000 0 0x40>, 3328 <0 0x088ea000 0 0x200>; 3329 status = "disabled"; 3330 #address-cells = <2>; 3331 #size-cells = <2>; 3332 ranges; 3333 3334 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3335 <&rpmhcc RPMH_CXO_CLK>, 3336 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3337 clock-names = "aux", "ref_clk_src", "com_aux"; 3338 3339 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3340 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3341 reset-names = "phy", "common"; 3342 3343 usb_1_ssphy: usb3-phy@88e9200 { 3344 reg = <0 0x088e9200 0 0x200>, 3345 <0 0x088e9400 0 0x200>, 3346 <0 0x088e9c00 0 0x400>, 3347 <0 0x088e9600 0 0x200>, 3348 <0 0x088e9800 0 0x200>, 3349 <0 0x088e9a00 0 0x100>; 3350 #clock-cells = <0>; 3351 #phy-cells = <0>; 3352 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3353 clock-names = "pipe0"; 3354 clock-output-names = "usb3_phy_pipe_clk_src"; 3355 }; 3356 3357 dp_phy: dp-phy@88ea200 { 3358 reg = <0 0x088ea200 0 0x200>, 3359 <0 0x088ea400 0 0x200>, 3360 <0 0x088eaa00 0 0x200>, 3361 <0 0x088ea600 0 0x200>, 3362 <0 0x088ea800 0 0x200>; 3363 #phy-cells = <0>; 3364 #clock-cells = <1>; 3365 }; 3366 }; 3367 3368 usb_2: usb@8cf8800 { 3369 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3370 reg = <0 0x08cf8800 0 0x400>; 3371 status = "disabled"; 3372 #address-cells = <2>; 3373 #size-cells = <2>; 3374 ranges; 3375 dma-ranges; 3376 3377 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3378 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3379 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3380 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3381 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3382 clock-names = "cfg_noc", 3383 "core", 3384 "iface", 3385 "sleep", 3386 "mock_utmi"; 3387 3388 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3389 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3390 assigned-clock-rates = <19200000>, <200000000>; 3391 3392 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3393 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3394 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3395 interrupt-names = "hs_phy_irq", 3396 "dp_hs_phy_irq", 3397 "dm_hs_phy_irq"; 3398 3399 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3400 required-opps = <&rpmhpd_opp_nom>; 3401 3402 resets = <&gcc GCC_USB30_SEC_BCR>; 3403 3404 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3405 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3406 interconnect-names = "usb-ddr", "apps-usb"; 3407 3408 usb_2_dwc3: usb@8c00000 { 3409 compatible = "snps,dwc3"; 3410 reg = <0 0x08c00000 0 0xe000>; 3411 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3412 iommus = <&apps_smmu 0xa0 0x0>; 3413 snps,dis_u2_susphy_quirk; 3414 snps,dis_enblslpm_quirk; 3415 phys = <&usb_2_hsphy>; 3416 phy-names = "usb2-phy"; 3417 maximum-speed = "high-speed"; 3418 usb-role-switch; 3419 port { 3420 usb2_role_switch: endpoint { 3421 remote-endpoint = <&eud_ep>; 3422 }; 3423 }; 3424 }; 3425 }; 3426 3427 qspi: spi@88dc000 { 3428 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3429 reg = <0 0x088dc000 0 0x1000>; 3430 #address-cells = <1>; 3431 #size-cells = <0>; 3432 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3433 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3434 <&gcc GCC_QSPI_CORE_CLK>; 3435 clock-names = "iface", "core"; 3436 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3437 &cnoc2 SLAVE_QSPI_0 0>; 3438 interconnect-names = "qspi-config"; 3439 power-domains = <&rpmhpd SC7280_CX>; 3440 operating-points-v2 = <&qspi_opp_table>; 3441 status = "disabled"; 3442 }; 3443 3444 remoteproc_wpss: remoteproc@8a00000 { 3445 compatible = "qcom,sc7280-wpss-pil"; 3446 reg = <0 0x08a00000 0 0x10000>; 3447 3448 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3449 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3450 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3451 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3452 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3453 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3454 interrupt-names = "wdog", "fatal", "ready", "handover", 3455 "stop-ack", "shutdown-ack"; 3456 3457 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3458 <&gcc GCC_WPSS_AHB_CLK>, 3459 <&gcc GCC_WPSS_RSCP_CLK>, 3460 <&rpmhcc RPMH_CXO_CLK>; 3461 clock-names = "ahb_bdg", "ahb", 3462 "rscp", "xo"; 3463 3464 power-domains = <&rpmhpd SC7280_CX>, 3465 <&rpmhpd SC7280_MX>; 3466 power-domain-names = "cx", "mx"; 3467 3468 memory-region = <&wpss_mem>; 3469 3470 qcom,qmp = <&aoss_qmp>; 3471 3472 qcom,smem-states = <&wpss_smp2p_out 0>; 3473 qcom,smem-state-names = "stop"; 3474 3475 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3476 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3477 reset-names = "restart", "pdc_sync"; 3478 3479 qcom,halt-regs = <&tcsr_1 0x17000>; 3480 3481 status = "disabled"; 3482 3483 glink-edge { 3484 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3485 IPCC_MPROC_SIGNAL_GLINK_QMP 3486 IRQ_TYPE_EDGE_RISING>; 3487 mboxes = <&ipcc IPCC_CLIENT_WPSS 3488 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3489 3490 label = "wpss"; 3491 qcom,remote-pid = <13>; 3492 }; 3493 }; 3494 3495 pmu@9091000 { 3496 compatible = "qcom,sc7280-llcc-bwmon"; 3497 reg = <0 0x09091000 0 0x1000>; 3498 3499 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3500 3501 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3502 3503 operating-points-v2 = <&llcc_bwmon_opp_table>; 3504 3505 llcc_bwmon_opp_table: opp-table { 3506 compatible = "operating-points-v2"; 3507 3508 opp-0 { 3509 opp-peak-kBps = <800000>; 3510 }; 3511 opp-1 { 3512 opp-peak-kBps = <1804000>; 3513 }; 3514 opp-2 { 3515 opp-peak-kBps = <2188000>; 3516 }; 3517 opp-3 { 3518 opp-peak-kBps = <3072000>; 3519 }; 3520 opp-4 { 3521 opp-peak-kBps = <4068000>; 3522 }; 3523 opp-5 { 3524 opp-peak-kBps = <6220000>; 3525 }; 3526 opp-6 { 3527 opp-peak-kBps = <6832000>; 3528 }; 3529 opp-7 { 3530 opp-peak-kBps = <8532000>; 3531 }; 3532 }; 3533 }; 3534 3535 pmu@90b6400 { 3536 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3537 reg = <0 0x090b6400 0 0x600>; 3538 3539 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3540 3541 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3542 operating-points-v2 = <&cpu_bwmon_opp_table>; 3543 3544 cpu_bwmon_opp_table: opp-table { 3545 compatible = "operating-points-v2"; 3546 3547 opp-0 { 3548 opp-peak-kBps = <2400000>; 3549 }; 3550 opp-1 { 3551 opp-peak-kBps = <4800000>; 3552 }; 3553 opp-2 { 3554 opp-peak-kBps = <7456000>; 3555 }; 3556 opp-3 { 3557 opp-peak-kBps = <9600000>; 3558 }; 3559 opp-4 { 3560 opp-peak-kBps = <12896000>; 3561 }; 3562 opp-5 { 3563 opp-peak-kBps = <14928000>; 3564 }; 3565 opp-6 { 3566 opp-peak-kBps = <17056000>; 3567 }; 3568 }; 3569 }; 3570 3571 dc_noc: interconnect@90e0000 { 3572 reg = <0 0x090e0000 0 0x5080>; 3573 compatible = "qcom,sc7280-dc-noc"; 3574 #interconnect-cells = <2>; 3575 qcom,bcm-voters = <&apps_bcm_voter>; 3576 }; 3577 3578 gem_noc: interconnect@9100000 { 3579 reg = <0 0x09100000 0 0xe2200>; 3580 compatible = "qcom,sc7280-gem-noc"; 3581 #interconnect-cells = <2>; 3582 qcom,bcm-voters = <&apps_bcm_voter>; 3583 }; 3584 3585 system-cache-controller@9200000 { 3586 compatible = "qcom,sc7280-llcc"; 3587 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3588 reg-names = "llcc_base", "llcc_broadcast_base"; 3589 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3590 }; 3591 3592 eud: eud@88e0000 { 3593 compatible = "qcom,sc7280-eud","qcom,eud"; 3594 reg = <0 0x088e0000 0 0x2000>, 3595 <0 0x088e2000 0 0x1000>; 3596 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3597 ports { 3598 port@0 { 3599 eud_ep: endpoint { 3600 remote-endpoint = <&usb2_role_switch>; 3601 }; 3602 }; 3603 port@1 { 3604 eud_con: endpoint { 3605 remote-endpoint = <&con_eud>; 3606 }; 3607 }; 3608 }; 3609 }; 3610 3611 eud_typec: connector { 3612 compatible = "usb-c-connector"; 3613 ports { 3614 port@0 { 3615 con_eud: endpoint { 3616 remote-endpoint = <&eud_con>; 3617 }; 3618 }; 3619 }; 3620 }; 3621 3622 nsp_noc: interconnect@a0c0000 { 3623 reg = <0 0x0a0c0000 0 0x10000>; 3624 compatible = "qcom,sc7280-nsp-noc"; 3625 #interconnect-cells = <2>; 3626 qcom,bcm-voters = <&apps_bcm_voter>; 3627 }; 3628 3629 usb_1: usb@a6f8800 { 3630 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3631 reg = <0 0x0a6f8800 0 0x400>; 3632 status = "disabled"; 3633 #address-cells = <2>; 3634 #size-cells = <2>; 3635 ranges; 3636 dma-ranges; 3637 3638 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3639 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3640 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3641 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3642 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3643 clock-names = "cfg_noc", 3644 "core", 3645 "iface", 3646 "sleep", 3647 "mock_utmi"; 3648 3649 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3650 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3651 assigned-clock-rates = <19200000>, <200000000>; 3652 3653 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3654 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3655 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3656 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3657 interrupt-names = "hs_phy_irq", 3658 "dp_hs_phy_irq", 3659 "dm_hs_phy_irq", 3660 "ss_phy_irq"; 3661 3662 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3663 required-opps = <&rpmhpd_opp_nom>; 3664 3665 resets = <&gcc GCC_USB30_PRIM_BCR>; 3666 3667 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3668 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3669 interconnect-names = "usb-ddr", "apps-usb"; 3670 3671 wakeup-source; 3672 3673 usb_1_dwc3: usb@a600000 { 3674 compatible = "snps,dwc3"; 3675 reg = <0 0x0a600000 0 0xe000>; 3676 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3677 iommus = <&apps_smmu 0xe0 0x0>; 3678 snps,dis_u2_susphy_quirk; 3679 snps,dis_enblslpm_quirk; 3680 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3681 phy-names = "usb2-phy", "usb3-phy"; 3682 maximum-speed = "super-speed"; 3683 }; 3684 }; 3685 3686 venus: video-codec@aa00000 { 3687 compatible = "qcom,sc7280-venus"; 3688 reg = <0 0x0aa00000 0 0xd0600>; 3689 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3690 3691 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3692 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3693 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3694 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3695 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3696 clock-names = "core", "bus", "iface", 3697 "vcodec_core", "vcodec_bus"; 3698 3699 power-domains = <&videocc MVSC_GDSC>, 3700 <&videocc MVS0_GDSC>, 3701 <&rpmhpd SC7280_CX>; 3702 power-domain-names = "venus", "vcodec0", "cx"; 3703 operating-points-v2 = <&venus_opp_table>; 3704 3705 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3706 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3707 interconnect-names = "cpu-cfg", "video-mem"; 3708 3709 iommus = <&apps_smmu 0x2180 0x20>, 3710 <&apps_smmu 0x2184 0x20>; 3711 memory-region = <&video_mem>; 3712 3713 video-decoder { 3714 compatible = "venus-decoder"; 3715 }; 3716 3717 video-encoder { 3718 compatible = "venus-encoder"; 3719 }; 3720 3721 video-firmware { 3722 iommus = <&apps_smmu 0x21a2 0x0>; 3723 }; 3724 3725 venus_opp_table: opp-table { 3726 compatible = "operating-points-v2"; 3727 3728 opp-133330000 { 3729 opp-hz = /bits/ 64 <133330000>; 3730 required-opps = <&rpmhpd_opp_low_svs>; 3731 }; 3732 3733 opp-240000000 { 3734 opp-hz = /bits/ 64 <240000000>; 3735 required-opps = <&rpmhpd_opp_svs>; 3736 }; 3737 3738 opp-335000000 { 3739 opp-hz = /bits/ 64 <335000000>; 3740 required-opps = <&rpmhpd_opp_svs_l1>; 3741 }; 3742 3743 opp-424000000 { 3744 opp-hz = /bits/ 64 <424000000>; 3745 required-opps = <&rpmhpd_opp_nom>; 3746 }; 3747 3748 opp-460000048 { 3749 opp-hz = /bits/ 64 <460000048>; 3750 required-opps = <&rpmhpd_opp_turbo>; 3751 }; 3752 }; 3753 3754 }; 3755 3756 videocc: clock-controller@aaf0000 { 3757 compatible = "qcom,sc7280-videocc"; 3758 reg = <0 0x0aaf0000 0 0x10000>; 3759 clocks = <&rpmhcc RPMH_CXO_CLK>, 3760 <&rpmhcc RPMH_CXO_CLK_A>; 3761 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3762 #clock-cells = <1>; 3763 #reset-cells = <1>; 3764 #power-domain-cells = <1>; 3765 }; 3766 3767 camcc: clock-controller@ad00000 { 3768 compatible = "qcom,sc7280-camcc"; 3769 reg = <0 0x0ad00000 0 0x10000>; 3770 clocks = <&rpmhcc RPMH_CXO_CLK>, 3771 <&rpmhcc RPMH_CXO_CLK_A>, 3772 <&sleep_clk>; 3773 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3774 #clock-cells = <1>; 3775 #reset-cells = <1>; 3776 #power-domain-cells = <1>; 3777 }; 3778 3779 dispcc: clock-controller@af00000 { 3780 compatible = "qcom,sc7280-dispcc"; 3781 reg = <0 0x0af00000 0 0x20000>; 3782 clocks = <&rpmhcc RPMH_CXO_CLK>, 3783 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3784 <&mdss_dsi_phy 0>, 3785 <&mdss_dsi_phy 1>, 3786 <&dp_phy 0>, 3787 <&dp_phy 1>, 3788 <&mdss_edp_phy 0>, 3789 <&mdss_edp_phy 1>; 3790 clock-names = "bi_tcxo", 3791 "gcc_disp_gpll0_clk", 3792 "dsi0_phy_pll_out_byteclk", 3793 "dsi0_phy_pll_out_dsiclk", 3794 "dp_phy_pll_link_clk", 3795 "dp_phy_pll_vco_div_clk", 3796 "edp_phy_pll_link_clk", 3797 "edp_phy_pll_vco_div_clk"; 3798 #clock-cells = <1>; 3799 #reset-cells = <1>; 3800 #power-domain-cells = <1>; 3801 }; 3802 3803 mdss: display-subsystem@ae00000 { 3804 compatible = "qcom,sc7280-mdss"; 3805 reg = <0 0x0ae00000 0 0x1000>; 3806 reg-names = "mdss"; 3807 3808 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3809 3810 clocks = <&gcc GCC_DISP_AHB_CLK>, 3811 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3812 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3813 clock-names = "iface", 3814 "ahb", 3815 "core"; 3816 3817 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3818 interrupt-controller; 3819 #interrupt-cells = <1>; 3820 3821 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3822 interconnect-names = "mdp0-mem"; 3823 3824 iommus = <&apps_smmu 0x900 0x402>; 3825 3826 #address-cells = <2>; 3827 #size-cells = <2>; 3828 ranges; 3829 3830 status = "disabled"; 3831 3832 mdss_mdp: display-controller@ae01000 { 3833 compatible = "qcom,sc7280-dpu"; 3834 reg = <0 0x0ae01000 0 0x8f030>, 3835 <0 0x0aeb0000 0 0x2008>; 3836 reg-names = "mdp", "vbif"; 3837 3838 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3839 <&gcc GCC_DISP_SF_AXI_CLK>, 3840 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3841 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3842 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3843 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3844 clock-names = "bus", 3845 "nrt_bus", 3846 "iface", 3847 "lut", 3848 "core", 3849 "vsync"; 3850 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3851 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3852 assigned-clock-rates = <19200000>, 3853 <19200000>; 3854 operating-points-v2 = <&mdp_opp_table>; 3855 power-domains = <&rpmhpd SC7280_CX>; 3856 3857 interrupt-parent = <&mdss>; 3858 interrupts = <0>; 3859 3860 status = "disabled"; 3861 3862 ports { 3863 #address-cells = <1>; 3864 #size-cells = <0>; 3865 3866 port@0 { 3867 reg = <0>; 3868 dpu_intf1_out: endpoint { 3869 remote-endpoint = <&dsi0_in>; 3870 }; 3871 }; 3872 3873 port@1 { 3874 reg = <1>; 3875 dpu_intf5_out: endpoint { 3876 remote-endpoint = <&edp_in>; 3877 }; 3878 }; 3879 3880 port@2 { 3881 reg = <2>; 3882 dpu_intf0_out: endpoint { 3883 remote-endpoint = <&dp_in>; 3884 }; 3885 }; 3886 }; 3887 3888 mdp_opp_table: opp-table { 3889 compatible = "operating-points-v2"; 3890 3891 opp-200000000 { 3892 opp-hz = /bits/ 64 <200000000>; 3893 required-opps = <&rpmhpd_opp_low_svs>; 3894 }; 3895 3896 opp-300000000 { 3897 opp-hz = /bits/ 64 <300000000>; 3898 required-opps = <&rpmhpd_opp_svs>; 3899 }; 3900 3901 opp-380000000 { 3902 opp-hz = /bits/ 64 <380000000>; 3903 required-opps = <&rpmhpd_opp_svs_l1>; 3904 }; 3905 3906 opp-506666667 { 3907 opp-hz = /bits/ 64 <506666667>; 3908 required-opps = <&rpmhpd_opp_nom>; 3909 }; 3910 }; 3911 }; 3912 3913 mdss_dsi: dsi@ae94000 { 3914 compatible = "qcom,sc7280-dsi-ctrl", 3915 "qcom,mdss-dsi-ctrl"; 3916 reg = <0 0x0ae94000 0 0x400>; 3917 reg-names = "dsi_ctrl"; 3918 3919 interrupt-parent = <&mdss>; 3920 interrupts = <4>; 3921 3922 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3923 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3924 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3925 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3926 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3927 <&gcc GCC_DISP_HF_AXI_CLK>; 3928 clock-names = "byte", 3929 "byte_intf", 3930 "pixel", 3931 "core", 3932 "iface", 3933 "bus"; 3934 3935 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3936 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3937 3938 operating-points-v2 = <&dsi_opp_table>; 3939 power-domains = <&rpmhpd SC7280_CX>; 3940 3941 phys = <&mdss_dsi_phy>; 3942 3943 #address-cells = <1>; 3944 #size-cells = <0>; 3945 3946 status = "disabled"; 3947 3948 ports { 3949 #address-cells = <1>; 3950 #size-cells = <0>; 3951 3952 port@0 { 3953 reg = <0>; 3954 dsi0_in: endpoint { 3955 remote-endpoint = <&dpu_intf1_out>; 3956 }; 3957 }; 3958 3959 port@1 { 3960 reg = <1>; 3961 dsi0_out: endpoint { 3962 }; 3963 }; 3964 }; 3965 3966 dsi_opp_table: opp-table { 3967 compatible = "operating-points-v2"; 3968 3969 opp-187500000 { 3970 opp-hz = /bits/ 64 <187500000>; 3971 required-opps = <&rpmhpd_opp_low_svs>; 3972 }; 3973 3974 opp-300000000 { 3975 opp-hz = /bits/ 64 <300000000>; 3976 required-opps = <&rpmhpd_opp_svs>; 3977 }; 3978 3979 opp-358000000 { 3980 opp-hz = /bits/ 64 <358000000>; 3981 required-opps = <&rpmhpd_opp_svs_l1>; 3982 }; 3983 }; 3984 }; 3985 3986 mdss_dsi_phy: phy@ae94400 { 3987 compatible = "qcom,sc7280-dsi-phy-7nm"; 3988 reg = <0 0x0ae94400 0 0x200>, 3989 <0 0x0ae94600 0 0x280>, 3990 <0 0x0ae94900 0 0x280>; 3991 reg-names = "dsi_phy", 3992 "dsi_phy_lane", 3993 "dsi_pll"; 3994 3995 #clock-cells = <1>; 3996 #phy-cells = <0>; 3997 3998 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3999 <&rpmhcc RPMH_CXO_CLK>; 4000 clock-names = "iface", "ref"; 4001 4002 status = "disabled"; 4003 }; 4004 4005 mdss_edp: edp@aea0000 { 4006 compatible = "qcom,sc7280-edp"; 4007 pinctrl-names = "default"; 4008 pinctrl-0 = <&edp_hot_plug_det>; 4009 4010 reg = <0 0x0aea0000 0 0x200>, 4011 <0 0x0aea0200 0 0x200>, 4012 <0 0x0aea0400 0 0xc00>, 4013 <0 0x0aea1000 0 0x400>; 4014 4015 interrupt-parent = <&mdss>; 4016 interrupts = <14>; 4017 4018 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4019 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4020 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4021 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4022 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4023 clock-names = "core_iface", 4024 "core_aux", 4025 "ctrl_link", 4026 "ctrl_link_iface", 4027 "stream_pixel"; 4028 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4029 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4030 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4031 4032 phys = <&mdss_edp_phy>; 4033 phy-names = "dp"; 4034 4035 operating-points-v2 = <&edp_opp_table>; 4036 power-domains = <&rpmhpd SC7280_CX>; 4037 4038 status = "disabled"; 4039 4040 ports { 4041 #address-cells = <1>; 4042 #size-cells = <0>; 4043 4044 port@0 { 4045 reg = <0>; 4046 edp_in: endpoint { 4047 remote-endpoint = <&dpu_intf5_out>; 4048 }; 4049 }; 4050 4051 port@1 { 4052 reg = <1>; 4053 mdss_edp_out: endpoint { }; 4054 }; 4055 }; 4056 4057 edp_opp_table: opp-table { 4058 compatible = "operating-points-v2"; 4059 4060 opp-160000000 { 4061 opp-hz = /bits/ 64 <160000000>; 4062 required-opps = <&rpmhpd_opp_low_svs>; 4063 }; 4064 4065 opp-270000000 { 4066 opp-hz = /bits/ 64 <270000000>; 4067 required-opps = <&rpmhpd_opp_svs>; 4068 }; 4069 4070 opp-540000000 { 4071 opp-hz = /bits/ 64 <540000000>; 4072 required-opps = <&rpmhpd_opp_nom>; 4073 }; 4074 4075 opp-810000000 { 4076 opp-hz = /bits/ 64 <810000000>; 4077 required-opps = <&rpmhpd_opp_nom>; 4078 }; 4079 }; 4080 }; 4081 4082 mdss_edp_phy: phy@aec2a00 { 4083 compatible = "qcom,sc7280-edp-phy"; 4084 4085 reg = <0 0x0aec2a00 0 0x19c>, 4086 <0 0x0aec2200 0 0xa0>, 4087 <0 0x0aec2600 0 0xa0>, 4088 <0 0x0aec2000 0 0x1c0>; 4089 4090 clocks = <&rpmhcc RPMH_CXO_CLK>, 4091 <&gcc GCC_EDP_CLKREF_EN>; 4092 clock-names = "aux", 4093 "cfg_ahb"; 4094 4095 #clock-cells = <1>; 4096 #phy-cells = <0>; 4097 4098 status = "disabled"; 4099 }; 4100 4101 mdss_dp: displayport-controller@ae90000 { 4102 compatible = "qcom,sc7280-dp"; 4103 4104 reg = <0 0x0ae90000 0 0x200>, 4105 <0 0x0ae90200 0 0x200>, 4106 <0 0x0ae90400 0 0xc00>, 4107 <0 0x0ae91000 0 0x400>, 4108 <0 0x0ae91400 0 0x400>; 4109 4110 interrupt-parent = <&mdss>; 4111 interrupts = <12>; 4112 4113 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4114 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4115 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4116 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4117 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4118 clock-names = "core_iface", 4119 "core_aux", 4120 "ctrl_link", 4121 "ctrl_link_iface", 4122 "stream_pixel"; 4123 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4124 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4125 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4126 phys = <&dp_phy>; 4127 phy-names = "dp"; 4128 4129 operating-points-v2 = <&dp_opp_table>; 4130 power-domains = <&rpmhpd SC7280_CX>; 4131 4132 #sound-dai-cells = <0>; 4133 4134 status = "disabled"; 4135 4136 ports { 4137 #address-cells = <1>; 4138 #size-cells = <0>; 4139 4140 port@0 { 4141 reg = <0>; 4142 dp_in: endpoint { 4143 remote-endpoint = <&dpu_intf0_out>; 4144 }; 4145 }; 4146 4147 port@1 { 4148 reg = <1>; 4149 mdss_dp_out: endpoint { }; 4150 }; 4151 }; 4152 4153 dp_opp_table: opp-table { 4154 compatible = "operating-points-v2"; 4155 4156 opp-160000000 { 4157 opp-hz = /bits/ 64 <160000000>; 4158 required-opps = <&rpmhpd_opp_low_svs>; 4159 }; 4160 4161 opp-270000000 { 4162 opp-hz = /bits/ 64 <270000000>; 4163 required-opps = <&rpmhpd_opp_svs>; 4164 }; 4165 4166 opp-540000000 { 4167 opp-hz = /bits/ 64 <540000000>; 4168 required-opps = <&rpmhpd_opp_svs_l1>; 4169 }; 4170 4171 opp-810000000 { 4172 opp-hz = /bits/ 64 <810000000>; 4173 required-opps = <&rpmhpd_opp_nom>; 4174 }; 4175 }; 4176 }; 4177 }; 4178 4179 pdc: interrupt-controller@b220000 { 4180 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4181 reg = <0 0x0b220000 0 0x30000>; 4182 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4183 <55 306 4>, <59 312 3>, <62 374 2>, 4184 <64 434 2>, <66 438 3>, <69 86 1>, 4185 <70 520 54>, <124 609 31>, <155 63 1>, 4186 <156 716 12>; 4187 #interrupt-cells = <2>; 4188 interrupt-parent = <&intc>; 4189 interrupt-controller; 4190 }; 4191 4192 pdc_reset: reset-controller@b5e0000 { 4193 compatible = "qcom,sc7280-pdc-global"; 4194 reg = <0 0x0b5e0000 0 0x20000>; 4195 #reset-cells = <1>; 4196 }; 4197 4198 tsens0: thermal-sensor@c263000 { 4199 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4200 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4201 <0 0x0c222000 0 0x1ff>; /* SROT */ 4202 #qcom,sensors = <15>; 4203 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4205 interrupt-names = "uplow","critical"; 4206 #thermal-sensor-cells = <1>; 4207 }; 4208 4209 tsens1: thermal-sensor@c265000 { 4210 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4211 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4212 <0 0x0c223000 0 0x1ff>; /* SROT */ 4213 #qcom,sensors = <12>; 4214 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4216 interrupt-names = "uplow","critical"; 4217 #thermal-sensor-cells = <1>; 4218 }; 4219 4220 aoss_reset: reset-controller@c2a0000 { 4221 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4222 reg = <0 0x0c2a0000 0 0x31000>; 4223 #reset-cells = <1>; 4224 }; 4225 4226 aoss_qmp: power-management@c300000 { 4227 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4228 reg = <0 0x0c300000 0 0x400>; 4229 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4230 IPCC_MPROC_SIGNAL_GLINK_QMP 4231 IRQ_TYPE_EDGE_RISING>; 4232 mboxes = <&ipcc IPCC_CLIENT_AOP 4233 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4234 4235 #clock-cells = <0>; 4236 }; 4237 4238 sram@c3f0000 { 4239 compatible = "qcom,rpmh-stats"; 4240 reg = <0 0x0c3f0000 0 0x400>; 4241 }; 4242 4243 spmi_bus: spmi@c440000 { 4244 compatible = "qcom,spmi-pmic-arb"; 4245 reg = <0 0x0c440000 0 0x1100>, 4246 <0 0x0c600000 0 0x2000000>, 4247 <0 0x0e600000 0 0x100000>, 4248 <0 0x0e700000 0 0xa0000>, 4249 <0 0x0c40a000 0 0x26000>; 4250 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4251 interrupt-names = "periph_irq"; 4252 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4253 qcom,ee = <0>; 4254 qcom,channel = <0>; 4255 #address-cells = <2>; 4256 #size-cells = <0>; 4257 interrupt-controller; 4258 #interrupt-cells = <4>; 4259 }; 4260 4261 tlmm: pinctrl@f100000 { 4262 compatible = "qcom,sc7280-pinctrl"; 4263 reg = <0 0x0f100000 0 0x300000>; 4264 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4265 gpio-controller; 4266 #gpio-cells = <2>; 4267 interrupt-controller; 4268 #interrupt-cells = <2>; 4269 gpio-ranges = <&tlmm 0 0 175>; 4270 wakeup-parent = <&pdc>; 4271 4272 dp_hot_plug_det: dp-hot-plug-det-state { 4273 pins = "gpio47"; 4274 function = "dp_hot"; 4275 }; 4276 4277 edp_hot_plug_det: edp-hot-plug-det-state { 4278 pins = "gpio60"; 4279 function = "edp_hot"; 4280 }; 4281 4282 mi2s0_data0: mi2s0-data0-state { 4283 pins = "gpio98"; 4284 function = "mi2s0_data0"; 4285 }; 4286 4287 mi2s0_data1: mi2s0-data1-state { 4288 pins = "gpio99"; 4289 function = "mi2s0_data1"; 4290 }; 4291 4292 mi2s0_mclk: mi2s0-mclk-state { 4293 pins = "gpio96"; 4294 function = "pri_mi2s"; 4295 }; 4296 4297 mi2s0_sclk: mi2s0-sclk-state { 4298 pins = "gpio97"; 4299 function = "mi2s0_sck"; 4300 }; 4301 4302 mi2s0_ws: mi2s0-ws-state { 4303 pins = "gpio100"; 4304 function = "mi2s0_ws"; 4305 }; 4306 4307 mi2s1_data0: mi2s1-data0-state { 4308 pins = "gpio107"; 4309 function = "mi2s1_data0"; 4310 }; 4311 4312 mi2s1_sclk: mi2s1-sclk-state { 4313 pins = "gpio106"; 4314 function = "mi2s1_sck"; 4315 }; 4316 4317 mi2s1_ws: mi2s1-ws-state { 4318 pins = "gpio108"; 4319 function = "mi2s1_ws"; 4320 }; 4321 4322 pcie1_clkreq_n: pcie1-clkreq-n-state { 4323 pins = "gpio79"; 4324 function = "pcie1_clkreqn"; 4325 }; 4326 4327 qspi_clk: qspi-clk-state { 4328 pins = "gpio14"; 4329 function = "qspi_clk"; 4330 }; 4331 4332 qspi_cs0: qspi-cs0-state { 4333 pins = "gpio15"; 4334 function = "qspi_cs"; 4335 }; 4336 4337 qspi_cs1: qspi-cs1-state { 4338 pins = "gpio19"; 4339 function = "qspi_cs"; 4340 }; 4341 4342 qspi_data01: qspi-data01-state { 4343 pins = "gpio12", "gpio13"; 4344 function = "qspi_data"; 4345 }; 4346 4347 qspi_data12: qspi-data12-state { 4348 pins = "gpio16", "gpio17"; 4349 function = "qspi_data"; 4350 }; 4351 4352 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4353 pins = "gpio0", "gpio1"; 4354 function = "qup00"; 4355 }; 4356 4357 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4358 pins = "gpio4", "gpio5"; 4359 function = "qup01"; 4360 }; 4361 4362 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4363 pins = "gpio8", "gpio9"; 4364 function = "qup02"; 4365 }; 4366 4367 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4368 pins = "gpio12", "gpio13"; 4369 function = "qup03"; 4370 }; 4371 4372 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4373 pins = "gpio16", "gpio17"; 4374 function = "qup04"; 4375 }; 4376 4377 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4378 pins = "gpio20", "gpio21"; 4379 function = "qup05"; 4380 }; 4381 4382 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4383 pins = "gpio24", "gpio25"; 4384 function = "qup06"; 4385 }; 4386 4387 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4388 pins = "gpio28", "gpio29"; 4389 function = "qup07"; 4390 }; 4391 4392 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4393 pins = "gpio32", "gpio33"; 4394 function = "qup10"; 4395 }; 4396 4397 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4398 pins = "gpio36", "gpio37"; 4399 function = "qup11"; 4400 }; 4401 4402 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4403 pins = "gpio40", "gpio41"; 4404 function = "qup12"; 4405 }; 4406 4407 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4408 pins = "gpio44", "gpio45"; 4409 function = "qup13"; 4410 }; 4411 4412 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4413 pins = "gpio48", "gpio49"; 4414 function = "qup14"; 4415 }; 4416 4417 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4418 pins = "gpio52", "gpio53"; 4419 function = "qup15"; 4420 }; 4421 4422 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4423 pins = "gpio56", "gpio57"; 4424 function = "qup16"; 4425 }; 4426 4427 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4428 pins = "gpio60", "gpio61"; 4429 function = "qup17"; 4430 }; 4431 4432 qup_spi0_data_clk: qup-spi0-data-clk-state { 4433 pins = "gpio0", "gpio1", "gpio2"; 4434 function = "qup00"; 4435 }; 4436 4437 qup_spi0_cs: qup-spi0-cs-state { 4438 pins = "gpio3"; 4439 function = "qup00"; 4440 }; 4441 4442 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4443 pins = "gpio3"; 4444 function = "gpio"; 4445 }; 4446 4447 qup_spi1_data_clk: qup-spi1-data-clk-state { 4448 pins = "gpio4", "gpio5", "gpio6"; 4449 function = "qup01"; 4450 }; 4451 4452 qup_spi1_cs: qup-spi1-cs-state { 4453 pins = "gpio7"; 4454 function = "qup01"; 4455 }; 4456 4457 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4458 pins = "gpio7"; 4459 function = "gpio"; 4460 }; 4461 4462 qup_spi2_data_clk: qup-spi2-data-clk-state { 4463 pins = "gpio8", "gpio9", "gpio10"; 4464 function = "qup02"; 4465 }; 4466 4467 qup_spi2_cs: qup-spi2-cs-state { 4468 pins = "gpio11"; 4469 function = "qup02"; 4470 }; 4471 4472 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4473 pins = "gpio11"; 4474 function = "gpio"; 4475 }; 4476 4477 qup_spi3_data_clk: qup-spi3-data-clk-state { 4478 pins = "gpio12", "gpio13", "gpio14"; 4479 function = "qup03"; 4480 }; 4481 4482 qup_spi3_cs: qup-spi3-cs-state { 4483 pins = "gpio15"; 4484 function = "qup03"; 4485 }; 4486 4487 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4488 pins = "gpio15"; 4489 function = "gpio"; 4490 }; 4491 4492 qup_spi4_data_clk: qup-spi4-data-clk-state { 4493 pins = "gpio16", "gpio17", "gpio18"; 4494 function = "qup04"; 4495 }; 4496 4497 qup_spi4_cs: qup-spi4-cs-state { 4498 pins = "gpio19"; 4499 function = "qup04"; 4500 }; 4501 4502 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4503 pins = "gpio19"; 4504 function = "gpio"; 4505 }; 4506 4507 qup_spi5_data_clk: qup-spi5-data-clk-state { 4508 pins = "gpio20", "gpio21", "gpio22"; 4509 function = "qup05"; 4510 }; 4511 4512 qup_spi5_cs: qup-spi5-cs-state { 4513 pins = "gpio23"; 4514 function = "qup05"; 4515 }; 4516 4517 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4518 pins = "gpio23"; 4519 function = "gpio"; 4520 }; 4521 4522 qup_spi6_data_clk: qup-spi6-data-clk-state { 4523 pins = "gpio24", "gpio25", "gpio26"; 4524 function = "qup06"; 4525 }; 4526 4527 qup_spi6_cs: qup-spi6-cs-state { 4528 pins = "gpio27"; 4529 function = "qup06"; 4530 }; 4531 4532 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4533 pins = "gpio27"; 4534 function = "gpio"; 4535 }; 4536 4537 qup_spi7_data_clk: qup-spi7-data-clk-state { 4538 pins = "gpio28", "gpio29", "gpio30"; 4539 function = "qup07"; 4540 }; 4541 4542 qup_spi7_cs: qup-spi7-cs-state { 4543 pins = "gpio31"; 4544 function = "qup07"; 4545 }; 4546 4547 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4548 pins = "gpio31"; 4549 function = "gpio"; 4550 }; 4551 4552 qup_spi8_data_clk: qup-spi8-data-clk-state { 4553 pins = "gpio32", "gpio33", "gpio34"; 4554 function = "qup10"; 4555 }; 4556 4557 qup_spi8_cs: qup-spi8-cs-state { 4558 pins = "gpio35"; 4559 function = "qup10"; 4560 }; 4561 4562 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4563 pins = "gpio35"; 4564 function = "gpio"; 4565 }; 4566 4567 qup_spi9_data_clk: qup-spi9-data-clk-state { 4568 pins = "gpio36", "gpio37", "gpio38"; 4569 function = "qup11"; 4570 }; 4571 4572 qup_spi9_cs: qup-spi9-cs-state { 4573 pins = "gpio39"; 4574 function = "qup11"; 4575 }; 4576 4577 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4578 pins = "gpio39"; 4579 function = "gpio"; 4580 }; 4581 4582 qup_spi10_data_clk: qup-spi10-data-clk-state { 4583 pins = "gpio40", "gpio41", "gpio42"; 4584 function = "qup12"; 4585 }; 4586 4587 qup_spi10_cs: qup-spi10-cs-state { 4588 pins = "gpio43"; 4589 function = "qup12"; 4590 }; 4591 4592 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4593 pins = "gpio43"; 4594 function = "gpio"; 4595 }; 4596 4597 qup_spi11_data_clk: qup-spi11-data-clk-state { 4598 pins = "gpio44", "gpio45", "gpio46"; 4599 function = "qup13"; 4600 }; 4601 4602 qup_spi11_cs: qup-spi11-cs-state { 4603 pins = "gpio47"; 4604 function = "qup13"; 4605 }; 4606 4607 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4608 pins = "gpio47"; 4609 function = "gpio"; 4610 }; 4611 4612 qup_spi12_data_clk: qup-spi12-data-clk-state { 4613 pins = "gpio48", "gpio49", "gpio50"; 4614 function = "qup14"; 4615 }; 4616 4617 qup_spi12_cs: qup-spi12-cs-state { 4618 pins = "gpio51"; 4619 function = "qup14"; 4620 }; 4621 4622 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4623 pins = "gpio51"; 4624 function = "gpio"; 4625 }; 4626 4627 qup_spi13_data_clk: qup-spi13-data-clk-state { 4628 pins = "gpio52", "gpio53", "gpio54"; 4629 function = "qup15"; 4630 }; 4631 4632 qup_spi13_cs: qup-spi13-cs-state { 4633 pins = "gpio55"; 4634 function = "qup15"; 4635 }; 4636 4637 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4638 pins = "gpio55"; 4639 function = "gpio"; 4640 }; 4641 4642 qup_spi14_data_clk: qup-spi14-data-clk-state { 4643 pins = "gpio56", "gpio57", "gpio58"; 4644 function = "qup16"; 4645 }; 4646 4647 qup_spi14_cs: qup-spi14-cs-state { 4648 pins = "gpio59"; 4649 function = "qup16"; 4650 }; 4651 4652 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4653 pins = "gpio59"; 4654 function = "gpio"; 4655 }; 4656 4657 qup_spi15_data_clk: qup-spi15-data-clk-state { 4658 pins = "gpio60", "gpio61", "gpio62"; 4659 function = "qup17"; 4660 }; 4661 4662 qup_spi15_cs: qup-spi15-cs-state { 4663 pins = "gpio63"; 4664 function = "qup17"; 4665 }; 4666 4667 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4668 pins = "gpio63"; 4669 function = "gpio"; 4670 }; 4671 4672 qup_uart0_cts: qup-uart0-cts-state { 4673 pins = "gpio0"; 4674 function = "qup00"; 4675 }; 4676 4677 qup_uart0_rts: qup-uart0-rts-state { 4678 pins = "gpio1"; 4679 function = "qup00"; 4680 }; 4681 4682 qup_uart0_tx: qup-uart0-tx-state { 4683 pins = "gpio2"; 4684 function = "qup00"; 4685 }; 4686 4687 qup_uart0_rx: qup-uart0-rx-state { 4688 pins = "gpio3"; 4689 function = "qup00"; 4690 }; 4691 4692 qup_uart1_cts: qup-uart1-cts-state { 4693 pins = "gpio4"; 4694 function = "qup01"; 4695 }; 4696 4697 qup_uart1_rts: qup-uart1-rts-state { 4698 pins = "gpio5"; 4699 function = "qup01"; 4700 }; 4701 4702 qup_uart1_tx: qup-uart1-tx-state { 4703 pins = "gpio6"; 4704 function = "qup01"; 4705 }; 4706 4707 qup_uart1_rx: qup-uart1-rx-state { 4708 pins = "gpio7"; 4709 function = "qup01"; 4710 }; 4711 4712 qup_uart2_cts: qup-uart2-cts-state { 4713 pins = "gpio8"; 4714 function = "qup02"; 4715 }; 4716 4717 qup_uart2_rts: qup-uart2-rts-state { 4718 pins = "gpio9"; 4719 function = "qup02"; 4720 }; 4721 4722 qup_uart2_tx: qup-uart2-tx-state { 4723 pins = "gpio10"; 4724 function = "qup02"; 4725 }; 4726 4727 qup_uart2_rx: qup-uart2-rx-state { 4728 pins = "gpio11"; 4729 function = "qup02"; 4730 }; 4731 4732 qup_uart3_cts: qup-uart3-cts-state { 4733 pins = "gpio12"; 4734 function = "qup03"; 4735 }; 4736 4737 qup_uart3_rts: qup-uart3-rts-state { 4738 pins = "gpio13"; 4739 function = "qup03"; 4740 }; 4741 4742 qup_uart3_tx: qup-uart3-tx-state { 4743 pins = "gpio14"; 4744 function = "qup03"; 4745 }; 4746 4747 qup_uart3_rx: qup-uart3-rx-state { 4748 pins = "gpio15"; 4749 function = "qup03"; 4750 }; 4751 4752 qup_uart4_cts: qup-uart4-cts-state { 4753 pins = "gpio16"; 4754 function = "qup04"; 4755 }; 4756 4757 qup_uart4_rts: qup-uart4-rts-state { 4758 pins = "gpio17"; 4759 function = "qup04"; 4760 }; 4761 4762 qup_uart4_tx: qup-uart4-tx-state { 4763 pins = "gpio18"; 4764 function = "qup04"; 4765 }; 4766 4767 qup_uart4_rx: qup-uart4-rx-state { 4768 pins = "gpio19"; 4769 function = "qup04"; 4770 }; 4771 4772 qup_uart5_cts: qup-uart5-cts-state { 4773 pins = "gpio20"; 4774 function = "qup05"; 4775 }; 4776 4777 qup_uart5_rts: qup-uart5-rts-state { 4778 pins = "gpio21"; 4779 function = "qup05"; 4780 }; 4781 4782 qup_uart5_tx: qup-uart5-tx-state { 4783 pins = "gpio22"; 4784 function = "qup05"; 4785 }; 4786 4787 qup_uart5_rx: qup-uart5-rx-state { 4788 pins = "gpio23"; 4789 function = "qup05"; 4790 }; 4791 4792 qup_uart6_cts: qup-uart6-cts-state { 4793 pins = "gpio24"; 4794 function = "qup06"; 4795 }; 4796 4797 qup_uart6_rts: qup-uart6-rts-state { 4798 pins = "gpio25"; 4799 function = "qup06"; 4800 }; 4801 4802 qup_uart6_tx: qup-uart6-tx-state { 4803 pins = "gpio26"; 4804 function = "qup06"; 4805 }; 4806 4807 qup_uart6_rx: qup-uart6-rx-state { 4808 pins = "gpio27"; 4809 function = "qup06"; 4810 }; 4811 4812 qup_uart7_cts: qup-uart7-cts-state { 4813 pins = "gpio28"; 4814 function = "qup07"; 4815 }; 4816 4817 qup_uart7_rts: qup-uart7-rts-state { 4818 pins = "gpio29"; 4819 function = "qup07"; 4820 }; 4821 4822 qup_uart7_tx: qup-uart7-tx-state { 4823 pins = "gpio30"; 4824 function = "qup07"; 4825 }; 4826 4827 qup_uart7_rx: qup-uart7-rx-state { 4828 pins = "gpio31"; 4829 function = "qup07"; 4830 }; 4831 4832 qup_uart8_cts: qup-uart8-cts-state { 4833 pins = "gpio32"; 4834 function = "qup10"; 4835 }; 4836 4837 qup_uart8_rts: qup-uart8-rts-state { 4838 pins = "gpio33"; 4839 function = "qup10"; 4840 }; 4841 4842 qup_uart8_tx: qup-uart8-tx-state { 4843 pins = "gpio34"; 4844 function = "qup10"; 4845 }; 4846 4847 qup_uart8_rx: qup-uart8-rx-state { 4848 pins = "gpio35"; 4849 function = "qup10"; 4850 }; 4851 4852 qup_uart9_cts: qup-uart9-cts-state { 4853 pins = "gpio36"; 4854 function = "qup11"; 4855 }; 4856 4857 qup_uart9_rts: qup-uart9-rts-state { 4858 pins = "gpio37"; 4859 function = "qup11"; 4860 }; 4861 4862 qup_uart9_tx: qup-uart9-tx-state { 4863 pins = "gpio38"; 4864 function = "qup11"; 4865 }; 4866 4867 qup_uart9_rx: qup-uart9-rx-state { 4868 pins = "gpio39"; 4869 function = "qup11"; 4870 }; 4871 4872 qup_uart10_cts: qup-uart10-cts-state { 4873 pins = "gpio40"; 4874 function = "qup12"; 4875 }; 4876 4877 qup_uart10_rts: qup-uart10-rts-state { 4878 pins = "gpio41"; 4879 function = "qup12"; 4880 }; 4881 4882 qup_uart10_tx: qup-uart10-tx-state { 4883 pins = "gpio42"; 4884 function = "qup12"; 4885 }; 4886 4887 qup_uart10_rx: qup-uart10-rx-state { 4888 pins = "gpio43"; 4889 function = "qup12"; 4890 }; 4891 4892 qup_uart11_cts: qup-uart11-cts-state { 4893 pins = "gpio44"; 4894 function = "qup13"; 4895 }; 4896 4897 qup_uart11_rts: qup-uart11-rts-state { 4898 pins = "gpio45"; 4899 function = "qup13"; 4900 }; 4901 4902 qup_uart11_tx: qup-uart11-tx-state { 4903 pins = "gpio46"; 4904 function = "qup13"; 4905 }; 4906 4907 qup_uart11_rx: qup-uart11-rx-state { 4908 pins = "gpio47"; 4909 function = "qup13"; 4910 }; 4911 4912 qup_uart12_cts: qup-uart12-cts-state { 4913 pins = "gpio48"; 4914 function = "qup14"; 4915 }; 4916 4917 qup_uart12_rts: qup-uart12-rts-state { 4918 pins = "gpio49"; 4919 function = "qup14"; 4920 }; 4921 4922 qup_uart12_tx: qup-uart12-tx-state { 4923 pins = "gpio50"; 4924 function = "qup14"; 4925 }; 4926 4927 qup_uart12_rx: qup-uart12-rx-state { 4928 pins = "gpio51"; 4929 function = "qup14"; 4930 }; 4931 4932 qup_uart13_cts: qup-uart13-cts-state { 4933 pins = "gpio52"; 4934 function = "qup15"; 4935 }; 4936 4937 qup_uart13_rts: qup-uart13-rts-state { 4938 pins = "gpio53"; 4939 function = "qup15"; 4940 }; 4941 4942 qup_uart13_tx: qup-uart13-tx-state { 4943 pins = "gpio54"; 4944 function = "qup15"; 4945 }; 4946 4947 qup_uart13_rx: qup-uart13-rx-state { 4948 pins = "gpio55"; 4949 function = "qup15"; 4950 }; 4951 4952 qup_uart14_cts: qup-uart14-cts-state { 4953 pins = "gpio56"; 4954 function = "qup16"; 4955 }; 4956 4957 qup_uart14_rts: qup-uart14-rts-state { 4958 pins = "gpio57"; 4959 function = "qup16"; 4960 }; 4961 4962 qup_uart14_tx: qup-uart14-tx-state { 4963 pins = "gpio58"; 4964 function = "qup16"; 4965 }; 4966 4967 qup_uart14_rx: qup-uart14-rx-state { 4968 pins = "gpio59"; 4969 function = "qup16"; 4970 }; 4971 4972 qup_uart15_cts: qup-uart15-cts-state { 4973 pins = "gpio60"; 4974 function = "qup17"; 4975 }; 4976 4977 qup_uart15_rts: qup-uart15-rts-state { 4978 pins = "gpio61"; 4979 function = "qup17"; 4980 }; 4981 4982 qup_uart15_tx: qup-uart15-tx-state { 4983 pins = "gpio62"; 4984 function = "qup17"; 4985 }; 4986 4987 qup_uart15_rx: qup-uart15-rx-state { 4988 pins = "gpio63"; 4989 function = "qup17"; 4990 }; 4991 4992 sdc1_clk: sdc1-clk-state { 4993 pins = "sdc1_clk"; 4994 }; 4995 4996 sdc1_cmd: sdc1-cmd-state { 4997 pins = "sdc1_cmd"; 4998 }; 4999 5000 sdc1_data: sdc1-data-state { 5001 pins = "sdc1_data"; 5002 }; 5003 5004 sdc1_rclk: sdc1-rclk-state { 5005 pins = "sdc1_rclk"; 5006 }; 5007 5008 sdc1_clk_sleep: sdc1-clk-sleep-state { 5009 pins = "sdc1_clk"; 5010 drive-strength = <2>; 5011 bias-bus-hold; 5012 }; 5013 5014 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5015 pins = "sdc1_cmd"; 5016 drive-strength = <2>; 5017 bias-bus-hold; 5018 }; 5019 5020 sdc1_data_sleep: sdc1-data-sleep-state { 5021 pins = "sdc1_data"; 5022 drive-strength = <2>; 5023 bias-bus-hold; 5024 }; 5025 5026 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5027 pins = "sdc1_rclk"; 5028 drive-strength = <2>; 5029 bias-bus-hold; 5030 }; 5031 5032 sdc2_clk: sdc2-clk-state { 5033 pins = "sdc2_clk"; 5034 }; 5035 5036 sdc2_cmd: sdc2-cmd-state { 5037 pins = "sdc2_cmd"; 5038 }; 5039 5040 sdc2_data: sdc2-data-state { 5041 pins = "sdc2_data"; 5042 }; 5043 5044 sdc2_clk_sleep: sdc2-clk-sleep-state { 5045 pins = "sdc2_clk"; 5046 drive-strength = <2>; 5047 bias-bus-hold; 5048 }; 5049 5050 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5051 pins = "sdc2_cmd"; 5052 drive-strength = <2>; 5053 bias-bus-hold; 5054 }; 5055 5056 sdc2_data_sleep: sdc2-data-sleep-state { 5057 pins = "sdc2_data"; 5058 drive-strength = <2>; 5059 bias-bus-hold; 5060 }; 5061 }; 5062 5063 sram@146a5000 { 5064 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5065 reg = <0 0x146a5000 0 0x6000>; 5066 5067 #address-cells = <1>; 5068 #size-cells = <1>; 5069 5070 ranges = <0 0 0x146a5000 0x6000>; 5071 5072 pil-reloc@594c { 5073 compatible = "qcom,pil-reloc-info"; 5074 reg = <0x594c 0xc8>; 5075 }; 5076 }; 5077 5078 apps_smmu: iommu@15000000 { 5079 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5080 reg = <0 0x15000000 0 0x100000>; 5081 #iommu-cells = <2>; 5082 #global-interrupts = <1>; 5083 dma-coherent; 5084 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5165 }; 5166 5167 intc: interrupt-controller@17a00000 { 5168 compatible = "arm,gic-v3"; 5169 #address-cells = <2>; 5170 #size-cells = <2>; 5171 ranges; 5172 #interrupt-cells = <3>; 5173 interrupt-controller; 5174 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5175 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5176 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5177 5178 gic-its@17a40000 { 5179 compatible = "arm,gic-v3-its"; 5180 msi-controller; 5181 #msi-cells = <1>; 5182 reg = <0 0x17a40000 0 0x20000>; 5183 status = "disabled"; 5184 }; 5185 }; 5186 5187 watchdog@17c10000 { 5188 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5189 reg = <0 0x17c10000 0 0x1000>; 5190 clocks = <&sleep_clk>; 5191 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5192 }; 5193 5194 timer@17c20000 { 5195 #address-cells = <1>; 5196 #size-cells = <1>; 5197 ranges = <0 0 0 0x20000000>; 5198 compatible = "arm,armv7-timer-mem"; 5199 reg = <0 0x17c20000 0 0x1000>; 5200 5201 frame@17c21000 { 5202 frame-number = <0>; 5203 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5204 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5205 reg = <0x17c21000 0x1000>, 5206 <0x17c22000 0x1000>; 5207 }; 5208 5209 frame@17c23000 { 5210 frame-number = <1>; 5211 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5212 reg = <0x17c23000 0x1000>; 5213 status = "disabled"; 5214 }; 5215 5216 frame@17c25000 { 5217 frame-number = <2>; 5218 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5219 reg = <0x17c25000 0x1000>; 5220 status = "disabled"; 5221 }; 5222 5223 frame@17c27000 { 5224 frame-number = <3>; 5225 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5226 reg = <0x17c27000 0x1000>; 5227 status = "disabled"; 5228 }; 5229 5230 frame@17c29000 { 5231 frame-number = <4>; 5232 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5233 reg = <0x17c29000 0x1000>; 5234 status = "disabled"; 5235 }; 5236 5237 frame@17c2b000 { 5238 frame-number = <5>; 5239 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5240 reg = <0x17c2b000 0x1000>; 5241 status = "disabled"; 5242 }; 5243 5244 frame@17c2d000 { 5245 frame-number = <6>; 5246 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5247 reg = <0x17c2d000 0x1000>; 5248 status = "disabled"; 5249 }; 5250 }; 5251 5252 apps_rsc: rsc@18200000 { 5253 compatible = "qcom,rpmh-rsc"; 5254 reg = <0 0x18200000 0 0x10000>, 5255 <0 0x18210000 0 0x10000>, 5256 <0 0x18220000 0 0x10000>; 5257 reg-names = "drv-0", "drv-1", "drv-2"; 5258 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5259 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5260 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5261 qcom,tcs-offset = <0xd00>; 5262 qcom,drv-id = <2>; 5263 qcom,tcs-config = <ACTIVE_TCS 2>, 5264 <SLEEP_TCS 3>, 5265 <WAKE_TCS 3>, 5266 <CONTROL_TCS 1>; 5267 5268 apps_bcm_voter: bcm-voter { 5269 compatible = "qcom,bcm-voter"; 5270 }; 5271 5272 rpmhpd: power-controller { 5273 compatible = "qcom,sc7280-rpmhpd"; 5274 #power-domain-cells = <1>; 5275 operating-points-v2 = <&rpmhpd_opp_table>; 5276 5277 rpmhpd_opp_table: opp-table { 5278 compatible = "operating-points-v2"; 5279 5280 rpmhpd_opp_ret: opp1 { 5281 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5282 }; 5283 5284 rpmhpd_opp_low_svs: opp2 { 5285 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5286 }; 5287 5288 rpmhpd_opp_svs: opp3 { 5289 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5290 }; 5291 5292 rpmhpd_opp_svs_l1: opp4 { 5293 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5294 }; 5295 5296 rpmhpd_opp_svs_l2: opp5 { 5297 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5298 }; 5299 5300 rpmhpd_opp_nom: opp6 { 5301 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5302 }; 5303 5304 rpmhpd_opp_nom_l1: opp7 { 5305 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5306 }; 5307 5308 rpmhpd_opp_turbo: opp8 { 5309 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5310 }; 5311 5312 rpmhpd_opp_turbo_l1: opp9 { 5313 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5314 }; 5315 }; 5316 }; 5317 5318 rpmhcc: clock-controller { 5319 compatible = "qcom,sc7280-rpmh-clk"; 5320 clocks = <&xo_board>; 5321 clock-names = "xo"; 5322 #clock-cells = <1>; 5323 }; 5324 }; 5325 5326 epss_l3: interconnect@18590000 { 5327 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5328 reg = <0 0x18590000 0 0x1000>; 5329 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5330 clock-names = "xo", "alternate"; 5331 #interconnect-cells = <1>; 5332 }; 5333 5334 cpufreq_hw: cpufreq@18591000 { 5335 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5336 reg = <0 0x18591000 0 0x1000>, 5337 <0 0x18592000 0 0x1000>, 5338 <0 0x18593000 0 0x1000>; 5339 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5340 clock-names = "xo", "alternate"; 5341 #freq-domain-cells = <1>; 5342 }; 5343 }; 5344 5345 thermal_zones: thermal-zones { 5346 cpu0-thermal { 5347 polling-delay-passive = <250>; 5348 polling-delay = <0>; 5349 5350 thermal-sensors = <&tsens0 1>; 5351 5352 trips { 5353 cpu0_alert0: trip-point0 { 5354 temperature = <90000>; 5355 hysteresis = <2000>; 5356 type = "passive"; 5357 }; 5358 5359 cpu0_alert1: trip-point1 { 5360 temperature = <95000>; 5361 hysteresis = <2000>; 5362 type = "passive"; 5363 }; 5364 5365 cpu0_crit: cpu-crit { 5366 temperature = <110000>; 5367 hysteresis = <0>; 5368 type = "critical"; 5369 }; 5370 }; 5371 5372 cooling-maps { 5373 map0 { 5374 trip = <&cpu0_alert0>; 5375 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5376 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5377 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5378 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5379 }; 5380 map1 { 5381 trip = <&cpu0_alert1>; 5382 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5383 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5384 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5385 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5386 }; 5387 }; 5388 }; 5389 5390 cpu1-thermal { 5391 polling-delay-passive = <250>; 5392 polling-delay = <0>; 5393 5394 thermal-sensors = <&tsens0 2>; 5395 5396 trips { 5397 cpu1_alert0: trip-point0 { 5398 temperature = <90000>; 5399 hysteresis = <2000>; 5400 type = "passive"; 5401 }; 5402 5403 cpu1_alert1: trip-point1 { 5404 temperature = <95000>; 5405 hysteresis = <2000>; 5406 type = "passive"; 5407 }; 5408 5409 cpu1_crit: cpu-crit { 5410 temperature = <110000>; 5411 hysteresis = <0>; 5412 type = "critical"; 5413 }; 5414 }; 5415 5416 cooling-maps { 5417 map0 { 5418 trip = <&cpu1_alert0>; 5419 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5420 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5421 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5422 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5423 }; 5424 map1 { 5425 trip = <&cpu1_alert1>; 5426 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5427 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5428 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5429 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5430 }; 5431 }; 5432 }; 5433 5434 cpu2-thermal { 5435 polling-delay-passive = <250>; 5436 polling-delay = <0>; 5437 5438 thermal-sensors = <&tsens0 3>; 5439 5440 trips { 5441 cpu2_alert0: trip-point0 { 5442 temperature = <90000>; 5443 hysteresis = <2000>; 5444 type = "passive"; 5445 }; 5446 5447 cpu2_alert1: trip-point1 { 5448 temperature = <95000>; 5449 hysteresis = <2000>; 5450 type = "passive"; 5451 }; 5452 5453 cpu2_crit: cpu-crit { 5454 temperature = <110000>; 5455 hysteresis = <0>; 5456 type = "critical"; 5457 }; 5458 }; 5459 5460 cooling-maps { 5461 map0 { 5462 trip = <&cpu2_alert0>; 5463 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5464 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5465 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5466 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5467 }; 5468 map1 { 5469 trip = <&cpu2_alert1>; 5470 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5471 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5472 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5473 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5474 }; 5475 }; 5476 }; 5477 5478 cpu3-thermal { 5479 polling-delay-passive = <250>; 5480 polling-delay = <0>; 5481 5482 thermal-sensors = <&tsens0 4>; 5483 5484 trips { 5485 cpu3_alert0: trip-point0 { 5486 temperature = <90000>; 5487 hysteresis = <2000>; 5488 type = "passive"; 5489 }; 5490 5491 cpu3_alert1: trip-point1 { 5492 temperature = <95000>; 5493 hysteresis = <2000>; 5494 type = "passive"; 5495 }; 5496 5497 cpu3_crit: cpu-crit { 5498 temperature = <110000>; 5499 hysteresis = <0>; 5500 type = "critical"; 5501 }; 5502 }; 5503 5504 cooling-maps { 5505 map0 { 5506 trip = <&cpu3_alert0>; 5507 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5508 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5509 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5510 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5511 }; 5512 map1 { 5513 trip = <&cpu3_alert1>; 5514 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5515 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5516 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5517 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5518 }; 5519 }; 5520 }; 5521 5522 cpu4-thermal { 5523 polling-delay-passive = <250>; 5524 polling-delay = <0>; 5525 5526 thermal-sensors = <&tsens0 7>; 5527 5528 trips { 5529 cpu4_alert0: trip-point0 { 5530 temperature = <90000>; 5531 hysteresis = <2000>; 5532 type = "passive"; 5533 }; 5534 5535 cpu4_alert1: trip-point1 { 5536 temperature = <95000>; 5537 hysteresis = <2000>; 5538 type = "passive"; 5539 }; 5540 5541 cpu4_crit: cpu-crit { 5542 temperature = <110000>; 5543 hysteresis = <0>; 5544 type = "critical"; 5545 }; 5546 }; 5547 5548 cooling-maps { 5549 map0 { 5550 trip = <&cpu4_alert0>; 5551 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5552 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5553 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5554 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5555 }; 5556 map1 { 5557 trip = <&cpu4_alert1>; 5558 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5559 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5560 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5561 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5562 }; 5563 }; 5564 }; 5565 5566 cpu5-thermal { 5567 polling-delay-passive = <250>; 5568 polling-delay = <0>; 5569 5570 thermal-sensors = <&tsens0 8>; 5571 5572 trips { 5573 cpu5_alert0: trip-point0 { 5574 temperature = <90000>; 5575 hysteresis = <2000>; 5576 type = "passive"; 5577 }; 5578 5579 cpu5_alert1: trip-point1 { 5580 temperature = <95000>; 5581 hysteresis = <2000>; 5582 type = "passive"; 5583 }; 5584 5585 cpu5_crit: cpu-crit { 5586 temperature = <110000>; 5587 hysteresis = <0>; 5588 type = "critical"; 5589 }; 5590 }; 5591 5592 cooling-maps { 5593 map0 { 5594 trip = <&cpu5_alert0>; 5595 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5596 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5597 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5598 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5599 }; 5600 map1 { 5601 trip = <&cpu5_alert1>; 5602 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5603 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5604 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5605 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5606 }; 5607 }; 5608 }; 5609 5610 cpu6-thermal { 5611 polling-delay-passive = <250>; 5612 polling-delay = <0>; 5613 5614 thermal-sensors = <&tsens0 9>; 5615 5616 trips { 5617 cpu6_alert0: trip-point0 { 5618 temperature = <90000>; 5619 hysteresis = <2000>; 5620 type = "passive"; 5621 }; 5622 5623 cpu6_alert1: trip-point1 { 5624 temperature = <95000>; 5625 hysteresis = <2000>; 5626 type = "passive"; 5627 }; 5628 5629 cpu6_crit: cpu-crit { 5630 temperature = <110000>; 5631 hysteresis = <0>; 5632 type = "critical"; 5633 }; 5634 }; 5635 5636 cooling-maps { 5637 map0 { 5638 trip = <&cpu6_alert0>; 5639 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5640 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5641 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5642 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5643 }; 5644 map1 { 5645 trip = <&cpu6_alert1>; 5646 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5647 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5648 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5649 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5650 }; 5651 }; 5652 }; 5653 5654 cpu7-thermal { 5655 polling-delay-passive = <250>; 5656 polling-delay = <0>; 5657 5658 thermal-sensors = <&tsens0 10>; 5659 5660 trips { 5661 cpu7_alert0: trip-point0 { 5662 temperature = <90000>; 5663 hysteresis = <2000>; 5664 type = "passive"; 5665 }; 5666 5667 cpu7_alert1: trip-point1 { 5668 temperature = <95000>; 5669 hysteresis = <2000>; 5670 type = "passive"; 5671 }; 5672 5673 cpu7_crit: cpu-crit { 5674 temperature = <110000>; 5675 hysteresis = <0>; 5676 type = "critical"; 5677 }; 5678 }; 5679 5680 cooling-maps { 5681 map0 { 5682 trip = <&cpu7_alert0>; 5683 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5684 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5685 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5686 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5687 }; 5688 map1 { 5689 trip = <&cpu7_alert1>; 5690 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5691 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5692 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5693 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5694 }; 5695 }; 5696 }; 5697 5698 cpu8-thermal { 5699 polling-delay-passive = <250>; 5700 polling-delay = <0>; 5701 5702 thermal-sensors = <&tsens0 11>; 5703 5704 trips { 5705 cpu8_alert0: trip-point0 { 5706 temperature = <90000>; 5707 hysteresis = <2000>; 5708 type = "passive"; 5709 }; 5710 5711 cpu8_alert1: trip-point1 { 5712 temperature = <95000>; 5713 hysteresis = <2000>; 5714 type = "passive"; 5715 }; 5716 5717 cpu8_crit: cpu-crit { 5718 temperature = <110000>; 5719 hysteresis = <0>; 5720 type = "critical"; 5721 }; 5722 }; 5723 5724 cooling-maps { 5725 map0 { 5726 trip = <&cpu8_alert0>; 5727 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5728 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5729 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5730 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5731 }; 5732 map1 { 5733 trip = <&cpu8_alert1>; 5734 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5735 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5736 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5737 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5738 }; 5739 }; 5740 }; 5741 5742 cpu9-thermal { 5743 polling-delay-passive = <250>; 5744 polling-delay = <0>; 5745 5746 thermal-sensors = <&tsens0 12>; 5747 5748 trips { 5749 cpu9_alert0: trip-point0 { 5750 temperature = <90000>; 5751 hysteresis = <2000>; 5752 type = "passive"; 5753 }; 5754 5755 cpu9_alert1: trip-point1 { 5756 temperature = <95000>; 5757 hysteresis = <2000>; 5758 type = "passive"; 5759 }; 5760 5761 cpu9_crit: cpu-crit { 5762 temperature = <110000>; 5763 hysteresis = <0>; 5764 type = "critical"; 5765 }; 5766 }; 5767 5768 cooling-maps { 5769 map0 { 5770 trip = <&cpu9_alert0>; 5771 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5772 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5773 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5774 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5775 }; 5776 map1 { 5777 trip = <&cpu9_alert1>; 5778 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5779 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5780 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5781 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5782 }; 5783 }; 5784 }; 5785 5786 cpu10-thermal { 5787 polling-delay-passive = <250>; 5788 polling-delay = <0>; 5789 5790 thermal-sensors = <&tsens0 13>; 5791 5792 trips { 5793 cpu10_alert0: trip-point0 { 5794 temperature = <90000>; 5795 hysteresis = <2000>; 5796 type = "passive"; 5797 }; 5798 5799 cpu10_alert1: trip-point1 { 5800 temperature = <95000>; 5801 hysteresis = <2000>; 5802 type = "passive"; 5803 }; 5804 5805 cpu10_crit: cpu-crit { 5806 temperature = <110000>; 5807 hysteresis = <0>; 5808 type = "critical"; 5809 }; 5810 }; 5811 5812 cooling-maps { 5813 map0 { 5814 trip = <&cpu10_alert0>; 5815 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5816 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5817 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5818 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5819 }; 5820 map1 { 5821 trip = <&cpu10_alert1>; 5822 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5823 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5824 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5825 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5826 }; 5827 }; 5828 }; 5829 5830 cpu11-thermal { 5831 polling-delay-passive = <250>; 5832 polling-delay = <0>; 5833 5834 thermal-sensors = <&tsens0 14>; 5835 5836 trips { 5837 cpu11_alert0: trip-point0 { 5838 temperature = <90000>; 5839 hysteresis = <2000>; 5840 type = "passive"; 5841 }; 5842 5843 cpu11_alert1: trip-point1 { 5844 temperature = <95000>; 5845 hysteresis = <2000>; 5846 type = "passive"; 5847 }; 5848 5849 cpu11_crit: cpu-crit { 5850 temperature = <110000>; 5851 hysteresis = <0>; 5852 type = "critical"; 5853 }; 5854 }; 5855 5856 cooling-maps { 5857 map0 { 5858 trip = <&cpu11_alert0>; 5859 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5860 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5861 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5862 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5863 }; 5864 map1 { 5865 trip = <&cpu11_alert1>; 5866 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5867 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5868 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5869 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5870 }; 5871 }; 5872 }; 5873 5874 aoss0-thermal { 5875 polling-delay-passive = <0>; 5876 polling-delay = <0>; 5877 5878 thermal-sensors = <&tsens0 0>; 5879 5880 trips { 5881 aoss0_alert0: trip-point0 { 5882 temperature = <90000>; 5883 hysteresis = <2000>; 5884 type = "hot"; 5885 }; 5886 5887 aoss0_crit: aoss0-crit { 5888 temperature = <110000>; 5889 hysteresis = <0>; 5890 type = "critical"; 5891 }; 5892 }; 5893 }; 5894 5895 aoss1-thermal { 5896 polling-delay-passive = <0>; 5897 polling-delay = <0>; 5898 5899 thermal-sensors = <&tsens1 0>; 5900 5901 trips { 5902 aoss1_alert0: trip-point0 { 5903 temperature = <90000>; 5904 hysteresis = <2000>; 5905 type = "hot"; 5906 }; 5907 5908 aoss1_crit: aoss1-crit { 5909 temperature = <110000>; 5910 hysteresis = <0>; 5911 type = "critical"; 5912 }; 5913 }; 5914 }; 5915 5916 cpuss0-thermal { 5917 polling-delay-passive = <0>; 5918 polling-delay = <0>; 5919 5920 thermal-sensors = <&tsens0 5>; 5921 5922 trips { 5923 cpuss0_alert0: trip-point0 { 5924 temperature = <90000>; 5925 hysteresis = <2000>; 5926 type = "hot"; 5927 }; 5928 cpuss0_crit: cluster0-crit { 5929 temperature = <110000>; 5930 hysteresis = <0>; 5931 type = "critical"; 5932 }; 5933 }; 5934 }; 5935 5936 cpuss1-thermal { 5937 polling-delay-passive = <0>; 5938 polling-delay = <0>; 5939 5940 thermal-sensors = <&tsens0 6>; 5941 5942 trips { 5943 cpuss1_alert0: trip-point0 { 5944 temperature = <90000>; 5945 hysteresis = <2000>; 5946 type = "hot"; 5947 }; 5948 cpuss1_crit: cluster0-crit { 5949 temperature = <110000>; 5950 hysteresis = <0>; 5951 type = "critical"; 5952 }; 5953 }; 5954 }; 5955 5956 gpuss0-thermal { 5957 polling-delay-passive = <100>; 5958 polling-delay = <0>; 5959 5960 thermal-sensors = <&tsens1 1>; 5961 5962 trips { 5963 gpuss0_alert0: trip-point0 { 5964 temperature = <95000>; 5965 hysteresis = <2000>; 5966 type = "passive"; 5967 }; 5968 5969 gpuss0_crit: gpuss0-crit { 5970 temperature = <110000>; 5971 hysteresis = <0>; 5972 type = "critical"; 5973 }; 5974 }; 5975 5976 cooling-maps { 5977 map0 { 5978 trip = <&gpuss0_alert0>; 5979 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5980 }; 5981 }; 5982 }; 5983 5984 gpuss1-thermal { 5985 polling-delay-passive = <100>; 5986 polling-delay = <0>; 5987 5988 thermal-sensors = <&tsens1 2>; 5989 5990 trips { 5991 gpuss1_alert0: trip-point0 { 5992 temperature = <95000>; 5993 hysteresis = <2000>; 5994 type = "passive"; 5995 }; 5996 5997 gpuss1_crit: gpuss1-crit { 5998 temperature = <110000>; 5999 hysteresis = <0>; 6000 type = "critical"; 6001 }; 6002 }; 6003 6004 cooling-maps { 6005 map0 { 6006 trip = <&gpuss1_alert0>; 6007 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6008 }; 6009 }; 6010 }; 6011 6012 nspss0-thermal { 6013 polling-delay-passive = <0>; 6014 polling-delay = <0>; 6015 6016 thermal-sensors = <&tsens1 3>; 6017 6018 trips { 6019 nspss0_alert0: trip-point0 { 6020 temperature = <90000>; 6021 hysteresis = <2000>; 6022 type = "hot"; 6023 }; 6024 6025 nspss0_crit: nspss0-crit { 6026 temperature = <110000>; 6027 hysteresis = <0>; 6028 type = "critical"; 6029 }; 6030 }; 6031 }; 6032 6033 nspss1-thermal { 6034 polling-delay-passive = <0>; 6035 polling-delay = <0>; 6036 6037 thermal-sensors = <&tsens1 4>; 6038 6039 trips { 6040 nspss1_alert0: trip-point0 { 6041 temperature = <90000>; 6042 hysteresis = <2000>; 6043 type = "hot"; 6044 }; 6045 6046 nspss1_crit: nspss1-crit { 6047 temperature = <110000>; 6048 hysteresis = <0>; 6049 type = "critical"; 6050 }; 6051 }; 6052 }; 6053 6054 video-thermal { 6055 polling-delay-passive = <0>; 6056 polling-delay = <0>; 6057 6058 thermal-sensors = <&tsens1 5>; 6059 6060 trips { 6061 video_alert0: trip-point0 { 6062 temperature = <90000>; 6063 hysteresis = <2000>; 6064 type = "hot"; 6065 }; 6066 6067 video_crit: video-crit { 6068 temperature = <110000>; 6069 hysteresis = <0>; 6070 type = "critical"; 6071 }; 6072 }; 6073 }; 6074 6075 ddr-thermal { 6076 polling-delay-passive = <0>; 6077 polling-delay = <0>; 6078 6079 thermal-sensors = <&tsens1 6>; 6080 6081 trips { 6082 ddr_alert0: trip-point0 { 6083 temperature = <90000>; 6084 hysteresis = <2000>; 6085 type = "hot"; 6086 }; 6087 6088 ddr_crit: ddr-crit { 6089 temperature = <110000>; 6090 hysteresis = <0>; 6091 type = "critical"; 6092 }; 6093 }; 6094 }; 6095 6096 mdmss0-thermal { 6097 polling-delay-passive = <0>; 6098 polling-delay = <0>; 6099 6100 thermal-sensors = <&tsens1 7>; 6101 6102 trips { 6103 mdmss0_alert0: trip-point0 { 6104 temperature = <90000>; 6105 hysteresis = <2000>; 6106 type = "hot"; 6107 }; 6108 6109 mdmss0_crit: mdmss0-crit { 6110 temperature = <110000>; 6111 hysteresis = <0>; 6112 type = "critical"; 6113 }; 6114 }; 6115 }; 6116 6117 mdmss1-thermal { 6118 polling-delay-passive = <0>; 6119 polling-delay = <0>; 6120 6121 thermal-sensors = <&tsens1 8>; 6122 6123 trips { 6124 mdmss1_alert0: trip-point0 { 6125 temperature = <90000>; 6126 hysteresis = <2000>; 6127 type = "hot"; 6128 }; 6129 6130 mdmss1_crit: mdmss1-crit { 6131 temperature = <110000>; 6132 hysteresis = <0>; 6133 type = "critical"; 6134 }; 6135 }; 6136 }; 6137 6138 mdmss2-thermal { 6139 polling-delay-passive = <0>; 6140 polling-delay = <0>; 6141 6142 thermal-sensors = <&tsens1 9>; 6143 6144 trips { 6145 mdmss2_alert0: trip-point0 { 6146 temperature = <90000>; 6147 hysteresis = <2000>; 6148 type = "hot"; 6149 }; 6150 6151 mdmss2_crit: mdmss2-crit { 6152 temperature = <110000>; 6153 hysteresis = <0>; 6154 type = "critical"; 6155 }; 6156 }; 6157 }; 6158 6159 mdmss3-thermal { 6160 polling-delay-passive = <0>; 6161 polling-delay = <0>; 6162 6163 thermal-sensors = <&tsens1 10>; 6164 6165 trips { 6166 mdmss3_alert0: trip-point0 { 6167 temperature = <90000>; 6168 hysteresis = <2000>; 6169 type = "hot"; 6170 }; 6171 6172 mdmss3_crit: mdmss3-crit { 6173 temperature = <110000>; 6174 hysteresis = <0>; 6175 type = "critical"; 6176 }; 6177 }; 6178 }; 6179 6180 camera0-thermal { 6181 polling-delay-passive = <0>; 6182 polling-delay = <0>; 6183 6184 thermal-sensors = <&tsens1 11>; 6185 6186 trips { 6187 camera0_alert0: trip-point0 { 6188 temperature = <90000>; 6189 hysteresis = <2000>; 6190 type = "hot"; 6191 }; 6192 6193 camera0_crit: camera0-crit { 6194 temperature = <110000>; 6195 hysteresis = <0>; 6196 type = "critical"; 6197 }; 6198 }; 6199 }; 6200 }; 6201 6202 timer { 6203 compatible = "arm,armv8-timer"; 6204 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6205 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6206 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6207 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6208 }; 6209}; 6210