1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 clock-frequency = <76800000>; 23 #clock-cells = <0>; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 clock-frequency = <32000>; 29 #clock-cells = <0>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,kryo"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&L2_0>; 43 L2_0: l2-cache { 44 compatible = "cache"; 45 next-level-cache = <&L3_0>; 46 L3_0: l3-cache { 47 compatible = "cache"; 48 }; 49 }; 50 }; 51 52 CPU1: cpu@100 { 53 device_type = "cpu"; 54 compatible = "arm,kryo"; 55 reg = <0x0 0x100>; 56 enable-method = "psci"; 57 next-level-cache = <&L2_100>; 58 L2_100: l2-cache { 59 compatible = "cache"; 60 next-level-cache = <&L3_0>; 61 }; 62 }; 63 64 CPU2: cpu@200 { 65 device_type = "cpu"; 66 compatible = "arm,kryo"; 67 reg = <0x0 0x200>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_200>; 70 L2_200: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 }; 74 }; 75 76 CPU3: cpu@300 { 77 device_type = "cpu"; 78 compatible = "arm,kryo"; 79 reg = <0x0 0x300>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_300>; 82 L2_300: l2-cache { 83 compatible = "cache"; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU4: cpu@400 { 89 device_type = "cpu"; 90 compatible = "arm,kryo"; 91 reg = <0x0 0x400>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_400>; 94 L2_400: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU5: cpu@500 { 101 device_type = "cpu"; 102 compatible = "arm,kryo"; 103 reg = <0x0 0x500>; 104 enable-method = "psci"; 105 next-level-cache = <&L2_500>; 106 L2_500: l2-cache { 107 compatible = "cache"; 108 next-level-cache = <&L3_0>; 109 }; 110 }; 111 112 CPU6: cpu@600 { 113 device_type = "cpu"; 114 compatible = "arm,kryo"; 115 reg = <0x0 0x600>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_600>; 118 L2_600: l2-cache { 119 compatible = "cache"; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU7: cpu@700 { 125 device_type = "cpu"; 126 compatible = "arm,kryo"; 127 reg = <0x0 0x700>; 128 enable-method = "psci"; 129 next-level-cache = <&L2_700>; 130 L2_700: l2-cache { 131 compatible = "cache"; 132 next-level-cache = <&L3_0>; 133 }; 134 }; 135 }; 136 137 memory@80000000 { 138 device_type = "memory"; 139 /* We expect the bootloader to fill in the size */ 140 reg = <0 0x80000000 0 0>; 141 }; 142 143 firmware { 144 scm { 145 compatible = "qcom,scm-sc7280", "qcom,scm"; 146 }; 147 }; 148 149 pmu { 150 compatible = "arm,armv8-pmuv3"; 151 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 152 }; 153 154 psci { 155 compatible = "arm,psci-1.0"; 156 method = "smc"; 157 }; 158 159 soc: soc@0 { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 ranges = <0 0 0 0 0x10 0>; 163 dma-ranges = <0 0 0 0 0x10 0>; 164 compatible = "simple-bus"; 165 166 gcc: clock-controller@100000 { 167 compatible = "qcom,gcc-sc7280"; 168 reg = <0 0x00100000 0 0x1f0000>; 169 #clock-cells = <1>; 170 #reset-cells = <1>; 171 #power-domain-cells = <1>; 172 }; 173 174 qupv3_id_0: geniqup@9c0000 { 175 compatible = "qcom,geni-se-qup"; 176 reg = <0 0x009c0000 0 0x2000>; 177 clock-names = "m-ahb", "s-ahb"; 178 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 179 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 status = "disabled"; 184 185 uart5: serial@994000 { 186 compatible = "qcom,geni-debug-uart"; 187 reg = <0 0x00994000 0 0x4000>; 188 clock-names = "se"; 189 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&qup_uart5_default>; 192 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 193 status = "disabled"; 194 }; 195 }; 196 197 tlmm: pinctrl@f100000 { 198 compatible = "qcom,sc7280-pinctrl"; 199 reg = <0 0x0f100000 0 0x300000>; 200 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 201 gpio-controller; 202 #gpio-cells = <2>; 203 interrupt-controller; 204 #interrupt-cells = <2>; 205 gpio-ranges = <&tlmm 0 0 175>; 206 207 qup_uart5_default: qup-uart5-default { 208 pins = "gpio46", "gpio47"; 209 function = "qup13"; 210 }; 211 }; 212 213 intc: interrupt-controller@17a00000 { 214 compatible = "arm,gic-v3"; 215 #address-cells = <2>; 216 #size-cells = <2>; 217 ranges; 218 #interrupt-cells = <3>; 219 interrupt-controller; 220 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 221 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 222 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 223 224 gic-its@17a40000 { 225 compatible = "arm,gic-v3-its"; 226 msi-controller; 227 #msi-cells = <1>; 228 reg = <0 0x17a40000 0 0x20000>; 229 status = "disabled"; 230 }; 231 }; 232 233 timer@17c20000 { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 compatible = "arm,armv7-timer-mem"; 238 reg = <0 0x17c20000 0 0x1000>; 239 240 frame@17c21000 { 241 frame-number = <0>; 242 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 244 reg = <0 0x17c21000 0 0x1000>, 245 <0 0x17c22000 0 0x1000>; 246 }; 247 248 frame@17c23000 { 249 frame-number = <1>; 250 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 251 reg = <0 0x17c23000 0 0x1000>; 252 status = "disabled"; 253 }; 254 255 frame@17c25000 { 256 frame-number = <2>; 257 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 258 reg = <0 0x17c25000 0 0x1000>; 259 status = "disabled"; 260 }; 261 262 frame@17c27000 { 263 frame-number = <3>; 264 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 265 reg = <0 0x17c27000 0 0x1000>; 266 status = "disabled"; 267 }; 268 269 frame@17c29000 { 270 frame-number = <4>; 271 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 272 reg = <0 0x17c29000 0 0x1000>; 273 status = "disabled"; 274 }; 275 276 frame@17c2b000 { 277 frame-number = <5>; 278 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 279 reg = <0 0x17c2b000 0 0x1000>; 280 status = "disabled"; 281 }; 282 283 frame@17c2d000 { 284 frame-number = <6>; 285 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 286 reg = <0 0x17c2d000 0 0x1000>; 287 status = "disabled"; 288 }; 289 }; 290 }; 291 292 timer { 293 compatible = "arm,armv8-timer"; 294 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 295 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 296 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 297 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 298 }; 299}; 300