1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 756 wlan_smp2p_out: wlan-ap-to-wpss { 757 qcom,entry-name = "wlan"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 wlan_smp2p_in: wlan-wpss-to-ap { 762 qcom,entry-name = "wlan"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 }; 767 768 pmu { 769 compatible = "arm,armv8-pmuv3"; 770 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 771 }; 772 773 psci { 774 compatible = "arm,psci-1.0"; 775 method = "smc"; 776 }; 777 778 qspi_opp_table: opp-table-qspi { 779 compatible = "operating-points-v2"; 780 781 opp-75000000 { 782 opp-hz = /bits/ 64 <75000000>; 783 required-opps = <&rpmhpd_opp_low_svs>; 784 }; 785 786 opp-150000000 { 787 opp-hz = /bits/ 64 <150000000>; 788 required-opps = <&rpmhpd_opp_svs>; 789 }; 790 791 opp-200000000 { 792 opp-hz = /bits/ 64 <200000000>; 793 required-opps = <&rpmhpd_opp_svs_l1>; 794 }; 795 796 opp-300000000 { 797 opp-hz = /bits/ 64 <300000000>; 798 required-opps = <&rpmhpd_opp_nom>; 799 }; 800 }; 801 802 qup_opp_table: opp-table-qup { 803 compatible = "operating-points-v2"; 804 805 opp-75000000 { 806 opp-hz = /bits/ 64 <75000000>; 807 required-opps = <&rpmhpd_opp_low_svs>; 808 }; 809 810 opp-100000000 { 811 opp-hz = /bits/ 64 <100000000>; 812 required-opps = <&rpmhpd_opp_svs>; 813 }; 814 815 opp-128000000 { 816 opp-hz = /bits/ 64 <128000000>; 817 required-opps = <&rpmhpd_opp_nom>; 818 }; 819 }; 820 821 soc: soc@0 { 822 #address-cells = <2>; 823 #size-cells = <2>; 824 ranges = <0 0 0 0 0x10 0>; 825 dma-ranges = <0 0 0 0 0x10 0>; 826 compatible = "simple-bus"; 827 828 gcc: clock-controller@100000 { 829 compatible = "qcom,gcc-sc7280"; 830 reg = <0 0x00100000 0 0x1f0000>; 831 clocks = <&rpmhcc RPMH_CXO_CLK>, 832 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 833 <0>, <&pcie1_lane>, 834 <0>, <0>, <0>, <0>; 835 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 836 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 837 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 838 "ufs_phy_tx_symbol_0_clk", 839 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 840 #clock-cells = <1>; 841 #reset-cells = <1>; 842 #power-domain-cells = <1>; 843 power-domains = <&rpmhpd SC7280_CX>; 844 }; 845 846 ipcc: mailbox@408000 { 847 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 848 reg = <0 0x00408000 0 0x1000>; 849 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-controller; 851 #interrupt-cells = <3>; 852 #mbox-cells = <2>; 853 }; 854 855 qfprom: efuse@784000 { 856 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 857 reg = <0 0x00784000 0 0xa20>, 858 <0 0x00780000 0 0xa20>, 859 <0 0x00782000 0 0x120>, 860 <0 0x00786000 0 0x1fff>; 861 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 862 clock-names = "core"; 863 power-domains = <&rpmhpd SC7280_MX>; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 867 gpu_speed_bin: gpu_speed_bin@1e9 { 868 reg = <0x1e9 0x2>; 869 bits = <5 8>; 870 }; 871 }; 872 873 sdhc_1: mmc@7c4000 { 874 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 875 pinctrl-names = "default", "sleep"; 876 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 877 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 878 status = "disabled"; 879 880 reg = <0 0x007c4000 0 0x1000>, 881 <0 0x007c5000 0 0x1000>; 882 reg-names = "hc", "cqhci"; 883 884 iommus = <&apps_smmu 0xc0 0x0>; 885 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "hc_irq", "pwr_irq"; 888 889 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 890 <&gcc GCC_SDCC1_APPS_CLK>, 891 <&rpmhcc RPMH_CXO_CLK>; 892 clock-names = "iface", "core", "xo"; 893 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 895 interconnect-names = "sdhc-ddr","cpu-sdhc"; 896 power-domains = <&rpmhpd SC7280_CX>; 897 operating-points-v2 = <&sdhc1_opp_table>; 898 899 bus-width = <8>; 900 supports-cqe; 901 902 qcom,dll-config = <0x0007642c>; 903 qcom,ddr-config = <0x80040868>; 904 905 mmc-ddr-1_8v; 906 mmc-hs200-1_8v; 907 mmc-hs400-1_8v; 908 mmc-hs400-enhanced-strobe; 909 910 resets = <&gcc GCC_SDCC1_BCR>; 911 912 sdhc1_opp_table: opp-table { 913 compatible = "operating-points-v2"; 914 915 opp-100000000 { 916 opp-hz = /bits/ 64 <100000000>; 917 required-opps = <&rpmhpd_opp_low_svs>; 918 opp-peak-kBps = <1800000 400000>; 919 opp-avg-kBps = <100000 0>; 920 }; 921 922 opp-384000000 { 923 opp-hz = /bits/ 64 <384000000>; 924 required-opps = <&rpmhpd_opp_nom>; 925 opp-peak-kBps = <5400000 1600000>; 926 opp-avg-kBps = <390000 0>; 927 }; 928 }; 929 930 }; 931 932 gpi_dma0: dma-controller@900000 { 933 #dma-cells = <3>; 934 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 935 reg = <0 0x00900000 0 0x60000>; 936 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 948 dma-channels = <12>; 949 dma-channel-mask = <0x7f>; 950 iommus = <&apps_smmu 0x0136 0x0>; 951 status = "disabled"; 952 }; 953 954 qupv3_id_0: geniqup@9c0000 { 955 compatible = "qcom,geni-se-qup"; 956 reg = <0 0x009c0000 0 0x2000>; 957 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 958 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 959 clock-names = "m-ahb", "s-ahb"; 960 #address-cells = <2>; 961 #size-cells = <2>; 962 ranges; 963 iommus = <&apps_smmu 0x123 0x0>; 964 status = "disabled"; 965 966 i2c0: i2c@980000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0 0x00980000 0 0x4000>; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 970 clock-names = "se"; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c0_data_clk>; 973 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 978 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 979 interconnect-names = "qup-core", "qup-config", 980 "qup-memory"; 981 power-domains = <&rpmhpd SC7280_CX>; 982 required-opps = <&rpmhpd_opp_low_svs>; 983 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 984 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 spi0: spi@980000 { 990 compatible = "qcom,geni-spi"; 991 reg = <0 0x00980000 0 0x4000>; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 993 clock-names = "se"; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 996 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 power-domains = <&rpmhpd SC7280_CX>; 1000 operating-points-v2 = <&qup_opp_table>; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1003 interconnect-names = "qup-core", "qup-config"; 1004 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1005 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1006 dma-names = "tx", "rx"; 1007 status = "disabled"; 1008 }; 1009 1010 uart0: serial@980000 { 1011 compatible = "qcom,geni-uart"; 1012 reg = <0 0x00980000 0 0x4000>; 1013 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1014 clock-names = "se"; 1015 pinctrl-names = "default"; 1016 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1017 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1018 power-domains = <&rpmhpd SC7280_CX>; 1019 operating-points-v2 = <&qup_opp_table>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1021 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1022 interconnect-names = "qup-core", "qup-config"; 1023 status = "disabled"; 1024 }; 1025 1026 i2c1: i2c@984000 { 1027 compatible = "qcom,geni-i2c"; 1028 reg = <0 0x00984000 0 0x4000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1030 clock-names = "se"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_i2c1_data_clk>; 1033 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1038 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1039 interconnect-names = "qup-core", "qup-config", 1040 "qup-memory"; 1041 power-domains = <&rpmhpd SC7280_CX>; 1042 required-opps = <&rpmhpd_opp_low_svs>; 1043 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1044 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 status = "disabled"; 1047 }; 1048 1049 spi1: spi@984000 { 1050 compatible = "qcom,geni-spi"; 1051 reg = <0 0x00984000 0 0x4000>; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1053 clock-names = "se"; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1056 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 power-domains = <&rpmhpd SC7280_CX>; 1060 operating-points-v2 = <&qup_opp_table>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1063 interconnect-names = "qup-core", "qup-config"; 1064 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1065 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 status = "disabled"; 1068 }; 1069 1070 uart1: serial@984000 { 1071 compatible = "qcom,geni-uart"; 1072 reg = <0 0x00984000 0 0x4000>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1074 clock-names = "se"; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1077 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&rpmhpd SC7280_CX>; 1079 operating-points-v2 = <&qup_opp_table>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c2: i2c@988000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x00988000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_i2c2_data_clk>; 1093 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1098 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1099 interconnect-names = "qup-core", "qup-config", 1100 "qup-memory"; 1101 power-domains = <&rpmhpd SC7280_CX>; 1102 required-opps = <&rpmhpd_opp_low_svs>; 1103 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 status = "disabled"; 1107 }; 1108 1109 spi2: spi@988000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x00988000 0 0x4000>; 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1113 clock-names = "se"; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1116 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 power-domains = <&rpmhpd SC7280_CX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1125 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1126 dma-names = "tx", "rx"; 1127 status = "disabled"; 1128 }; 1129 1130 uart2: serial@988000 { 1131 compatible = "qcom,geni-uart"; 1132 reg = <0 0x00988000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1137 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd SC7280_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 status = "disabled"; 1144 }; 1145 1146 i2c3: i2c@98c000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x0098c000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c3_data_clk>; 1153 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1158 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1159 interconnect-names = "qup-core", "qup-config", 1160 "qup-memory"; 1161 power-domains = <&rpmhpd SC7280_CX>; 1162 required-opps = <&rpmhpd_opp_low_svs>; 1163 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 status = "disabled"; 1167 }; 1168 1169 spi3: spi@98c000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x0098c000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1176 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 power-domains = <&rpmhpd SC7280_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1183 interconnect-names = "qup-core", "qup-config"; 1184 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1185 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1186 dma-names = "tx", "rx"; 1187 status = "disabled"; 1188 }; 1189 1190 uart3: serial@98c000 { 1191 compatible = "qcom,geni-uart"; 1192 reg = <0 0x0098c000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1194 clock-names = "se"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1197 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1198 power-domains = <&rpmhpd SC7280_CX>; 1199 operating-points-v2 = <&qup_opp_table>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 status = "disabled"; 1204 }; 1205 1206 i2c4: i2c@990000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x00990000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c4_data_clk>; 1213 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1218 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1219 interconnect-names = "qup-core", "qup-config", 1220 "qup-memory"; 1221 power-domains = <&rpmhpd SC7280_CX>; 1222 required-opps = <&rpmhpd_opp_low_svs>; 1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1224 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1225 dma-names = "tx", "rx"; 1226 status = "disabled"; 1227 }; 1228 1229 spi4: spi@990000 { 1230 compatible = "qcom,geni-spi"; 1231 reg = <0 0x00990000 0 0x4000>; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1233 clock-names = "se"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1236 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 power-domains = <&rpmhpd SC7280_CX>; 1240 operating-points-v2 = <&qup_opp_table>; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1242 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1243 interconnect-names = "qup-core", "qup-config"; 1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1245 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1246 dma-names = "tx", "rx"; 1247 status = "disabled"; 1248 }; 1249 1250 uart4: serial@990000 { 1251 compatible = "qcom,geni-uart"; 1252 reg = <0 0x00990000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1254 clock-names = "se"; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1257 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1258 power-domains = <&rpmhpd SC7280_CX>; 1259 operating-points-v2 = <&qup_opp_table>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 status = "disabled"; 1264 }; 1265 1266 i2c5: i2c@994000 { 1267 compatible = "qcom,geni-i2c"; 1268 reg = <0 0x00994000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_i2c5_data_clk>; 1273 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1278 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1279 interconnect-names = "qup-core", "qup-config", 1280 "qup-memory"; 1281 power-domains = <&rpmhpd SC7280_CX>; 1282 required-opps = <&rpmhpd_opp_low_svs>; 1283 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1284 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1285 dma-names = "tx", "rx"; 1286 status = "disabled"; 1287 }; 1288 1289 spi5: spi@994000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00994000 0 0x4000>; 1292 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1293 clock-names = "se"; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1296 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 power-domains = <&rpmhpd SC7280_CX>; 1300 operating-points-v2 = <&qup_opp_table>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1303 interconnect-names = "qup-core", "qup-config"; 1304 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1305 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1306 dma-names = "tx", "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 uart5: serial@994000 { 1311 compatible = "qcom,geni-uart"; 1312 reg = <0 0x00994000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1314 clock-names = "se"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1317 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1318 power-domains = <&rpmhpd SC7280_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1322 interconnect-names = "qup-core", "qup-config"; 1323 status = "disabled"; 1324 }; 1325 1326 i2c6: i2c@998000 { 1327 compatible = "qcom,geni-i2c"; 1328 reg = <0 0x00998000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_i2c6_data_clk>; 1333 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", 1340 "qup-memory"; 1341 power-domains = <&rpmhpd SC7280_CX>; 1342 required-opps = <&rpmhpd_opp_low_svs>; 1343 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1344 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 status = "disabled"; 1347 }; 1348 1349 spi6: spi@998000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00998000 0 0x4000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1353 clock-names = "se"; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1356 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 power-domains = <&rpmhpd SC7280_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1365 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1366 dma-names = "tx", "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 uart6: serial@998000 { 1371 compatible = "qcom,geni-uart"; 1372 reg = <0 0x00998000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd SC7280_CX>; 1379 operating-points-v2 = <&qup_opp_table>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1382 interconnect-names = "qup-core", "qup-config"; 1383 status = "disabled"; 1384 }; 1385 1386 i2c7: i2c@99c000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x0099c000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c7_data_clk>; 1393 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1398 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1399 interconnect-names = "qup-core", "qup-config", 1400 "qup-memory"; 1401 power-domains = <&rpmhpd SC7280_CX>; 1402 required-opps = <&rpmhpd_opp_low_svs>; 1403 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1404 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1405 dma-names = "tx", "rx"; 1406 status = "disabled"; 1407 }; 1408 1409 spi7: spi@99c000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0 0x0099c000 0 0x4000>; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1413 clock-names = "se"; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1416 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 power-domains = <&rpmhpd SC7280_CX>; 1420 operating-points-v2 = <&qup_opp_table>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1425 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 uart7: serial@99c000 { 1431 compatible = "qcom,geni-uart"; 1432 reg = <0 0x0099c000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1437 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1438 power-domains = <&rpmhpd SC7280_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 status = "disabled"; 1444 }; 1445 }; 1446 1447 gpi_dma1: dma-controller@a00000 { 1448 #dma-cells = <3>; 1449 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1450 reg = <0 0x00a00000 0 0x60000>; 1451 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1463 dma-channels = <12>; 1464 dma-channel-mask = <0x1e>; 1465 iommus = <&apps_smmu 0x56 0x0>; 1466 status = "disabled"; 1467 }; 1468 1469 qupv3_id_1: geniqup@ac0000 { 1470 compatible = "qcom,geni-se-qup"; 1471 reg = <0 0x00ac0000 0 0x2000>; 1472 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1473 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1474 clock-names = "m-ahb", "s-ahb"; 1475 #address-cells = <2>; 1476 #size-cells = <2>; 1477 ranges; 1478 iommus = <&apps_smmu 0x43 0x0>; 1479 status = "disabled"; 1480 1481 i2c8: i2c@a80000 { 1482 compatible = "qcom,geni-i2c"; 1483 reg = <0 0x00a80000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1485 clock-names = "se"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_i2c8_data_clk>; 1488 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1492 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1493 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1494 interconnect-names = "qup-core", "qup-config", 1495 "qup-memory"; 1496 power-domains = <&rpmhpd SC7280_CX>; 1497 required-opps = <&rpmhpd_opp_low_svs>; 1498 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1499 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1500 dma-names = "tx", "rx"; 1501 status = "disabled"; 1502 }; 1503 1504 spi8: spi@a80000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0 0x00a80000 0 0x4000>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1508 clock-names = "se"; 1509 pinctrl-names = "default"; 1510 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1511 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 power-domains = <&rpmhpd SC7280_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1518 interconnect-names = "qup-core", "qup-config"; 1519 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1520 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1521 dma-names = "tx", "rx"; 1522 status = "disabled"; 1523 }; 1524 1525 uart8: serial@a80000 { 1526 compatible = "qcom,geni-uart"; 1527 reg = <0 0x00a80000 0 0x4000>; 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1529 clock-names = "se"; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1532 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1533 power-domains = <&rpmhpd SC7280_CX>; 1534 operating-points-v2 = <&qup_opp_table>; 1535 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1536 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1537 interconnect-names = "qup-core", "qup-config"; 1538 status = "disabled"; 1539 }; 1540 1541 i2c9: i2c@a84000 { 1542 compatible = "qcom,geni-i2c"; 1543 reg = <0 0x00a84000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_i2c9_data_clk>; 1548 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1552 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1553 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1554 interconnect-names = "qup-core", "qup-config", 1555 "qup-memory"; 1556 power-domains = <&rpmhpd SC7280_CX>; 1557 required-opps = <&rpmhpd_opp_low_svs>; 1558 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1559 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1560 dma-names = "tx", "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 spi9: spi@a84000 { 1565 compatible = "qcom,geni-spi"; 1566 reg = <0 0x00a84000 0 0x4000>; 1567 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1568 clock-names = "se"; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1571 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 power-domains = <&rpmhpd SC7280_CX>; 1575 operating-points-v2 = <&qup_opp_table>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1577 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1578 interconnect-names = "qup-core", "qup-config"; 1579 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1580 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1581 dma-names = "tx", "rx"; 1582 status = "disabled"; 1583 }; 1584 1585 uart9: serial@a84000 { 1586 compatible = "qcom,geni-uart"; 1587 reg = <0 0x00a84000 0 0x4000>; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1589 clock-names = "se"; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1592 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1593 power-domains = <&rpmhpd SC7280_CX>; 1594 operating-points-v2 = <&qup_opp_table>; 1595 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1596 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1597 interconnect-names = "qup-core", "qup-config"; 1598 status = "disabled"; 1599 }; 1600 1601 i2c10: i2c@a88000 { 1602 compatible = "qcom,geni-i2c"; 1603 reg = <0 0x00a88000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1605 clock-names = "se"; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_i2c10_data_clk>; 1608 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1612 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1613 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1614 interconnect-names = "qup-core", "qup-config", 1615 "qup-memory"; 1616 power-domains = <&rpmhpd SC7280_CX>; 1617 required-opps = <&rpmhpd_opp_low_svs>; 1618 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1619 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1620 dma-names = "tx", "rx"; 1621 status = "disabled"; 1622 }; 1623 1624 spi10: spi@a88000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a88000 0 0x4000>; 1627 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1628 clock-names = "se"; 1629 pinctrl-names = "default"; 1630 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1631 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 power-domains = <&rpmhpd SC7280_CX>; 1635 operating-points-v2 = <&qup_opp_table>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1638 interconnect-names = "qup-core", "qup-config"; 1639 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1640 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1641 dma-names = "tx", "rx"; 1642 status = "disabled"; 1643 }; 1644 1645 uart10: serial@a88000 { 1646 compatible = "qcom,geni-uart"; 1647 reg = <0 0x00a88000 0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1649 clock-names = "se"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1652 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1653 power-domains = <&rpmhpd SC7280_CX>; 1654 operating-points-v2 = <&qup_opp_table>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1657 interconnect-names = "qup-core", "qup-config"; 1658 status = "disabled"; 1659 }; 1660 1661 i2c11: i2c@a8c000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0 0x00a8c000 0 0x4000>; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1665 clock-names = "se"; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_i2c11_data_clk>; 1668 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", 1675 "qup-memory"; 1676 power-domains = <&rpmhpd SC7280_CX>; 1677 required-opps = <&rpmhpd_opp_low_svs>; 1678 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1679 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1680 dma-names = "tx", "rx"; 1681 status = "disabled"; 1682 }; 1683 1684 spi11: spi@a8c000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0 0x00a8c000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1691 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 power-domains = <&rpmhpd SC7280_CX>; 1695 operating-points-v2 = <&qup_opp_table>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1698 interconnect-names = "qup-core", "qup-config"; 1699 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1700 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 uart11: serial@a8c000 { 1706 compatible = "qcom,geni-uart"; 1707 reg = <0 0x00a8c000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1713 power-domains = <&rpmhpd SC7280_CX>; 1714 operating-points-v2 = <&qup_opp_table>; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1716 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1717 interconnect-names = "qup-core", "qup-config"; 1718 status = "disabled"; 1719 }; 1720 1721 i2c12: i2c@a90000 { 1722 compatible = "qcom,geni-i2c"; 1723 reg = <0 0x00a90000 0 0x4000>; 1724 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1725 clock-names = "se"; 1726 pinctrl-names = "default"; 1727 pinctrl-0 = <&qup_i2c12_data_clk>; 1728 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1732 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1733 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1734 interconnect-names = "qup-core", "qup-config", 1735 "qup-memory"; 1736 power-domains = <&rpmhpd SC7280_CX>; 1737 required-opps = <&rpmhpd_opp_low_svs>; 1738 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1739 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1740 dma-names = "tx", "rx"; 1741 status = "disabled"; 1742 }; 1743 1744 spi12: spi@a90000 { 1745 compatible = "qcom,geni-spi"; 1746 reg = <0 0x00a90000 0 0x4000>; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1748 clock-names = "se"; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1751 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 power-domains = <&rpmhpd SC7280_CX>; 1755 operating-points-v2 = <&qup_opp_table>; 1756 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1758 interconnect-names = "qup-core", "qup-config"; 1759 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1760 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 uart12: serial@a90000 { 1766 compatible = "qcom,geni-uart"; 1767 reg = <0 0x00a90000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 status = "disabled"; 1779 }; 1780 1781 i2c13: i2c@a94000 { 1782 compatible = "qcom,geni-i2c"; 1783 reg = <0 0x00a94000 0 0x4000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1785 clock-names = "se"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_i2c13_data_clk>; 1788 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1792 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1793 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1794 interconnect-names = "qup-core", "qup-config", 1795 "qup-memory"; 1796 power-domains = <&rpmhpd SC7280_CX>; 1797 required-opps = <&rpmhpd_opp_low_svs>; 1798 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1800 dma-names = "tx", "rx"; 1801 status = "disabled"; 1802 }; 1803 1804 spi13: spi@a94000 { 1805 compatible = "qcom,geni-spi"; 1806 reg = <0 0x00a94000 0 0x4000>; 1807 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1808 clock-names = "se"; 1809 pinctrl-names = "default"; 1810 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1811 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 power-domains = <&rpmhpd SC7280_CX>; 1815 operating-points-v2 = <&qup_opp_table>; 1816 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1818 interconnect-names = "qup-core", "qup-config"; 1819 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1820 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1821 dma-names = "tx", "rx"; 1822 status = "disabled"; 1823 }; 1824 1825 uart13: serial@a94000 { 1826 compatible = "qcom,geni-uart"; 1827 reg = <0 0x00a94000 0 0x4000>; 1828 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1829 clock-names = "se"; 1830 pinctrl-names = "default"; 1831 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1832 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 operating-points-v2 = <&qup_opp_table>; 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1837 interconnect-names = "qup-core", "qup-config"; 1838 status = "disabled"; 1839 }; 1840 1841 i2c14: i2c@a98000 { 1842 compatible = "qcom,geni-i2c"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1845 clock-names = "se"; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_i2c14_data_clk>; 1848 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1852 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1853 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1854 interconnect-names = "qup-core", "qup-config", 1855 "qup-memory"; 1856 power-domains = <&rpmhpd SC7280_CX>; 1857 required-opps = <&rpmhpd_opp_low_svs>; 1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1859 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1860 dma-names = "tx", "rx"; 1861 status = "disabled"; 1862 }; 1863 1864 spi14: spi@a98000 { 1865 compatible = "qcom,geni-spi"; 1866 reg = <0 0x00a98000 0 0x4000>; 1867 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1868 clock-names = "se"; 1869 pinctrl-names = "default"; 1870 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1871 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 power-domains = <&rpmhpd SC7280_CX>; 1875 operating-points-v2 = <&qup_opp_table>; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1878 interconnect-names = "qup-core", "qup-config"; 1879 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1880 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1881 dma-names = "tx", "rx"; 1882 status = "disabled"; 1883 }; 1884 1885 uart14: serial@a98000 { 1886 compatible = "qcom,geni-uart"; 1887 reg = <0 0x00a98000 0 0x4000>; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1889 clock-names = "se"; 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1892 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1893 power-domains = <&rpmhpd SC7280_CX>; 1894 operating-points-v2 = <&qup_opp_table>; 1895 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1896 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1897 interconnect-names = "qup-core", "qup-config"; 1898 status = "disabled"; 1899 }; 1900 1901 i2c15: i2c@a9c000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0 0x00a9c000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_i2c15_data_clk>; 1908 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1909 #address-cells = <1>; 1910 #size-cells = <0>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1913 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1914 interconnect-names = "qup-core", "qup-config", 1915 "qup-memory"; 1916 power-domains = <&rpmhpd SC7280_CX>; 1917 required-opps = <&rpmhpd_opp_low_svs>; 1918 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1919 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1920 dma-names = "tx", "rx"; 1921 status = "disabled"; 1922 }; 1923 1924 spi15: spi@a9c000 { 1925 compatible = "qcom,geni-spi"; 1926 reg = <0 0x00a9c000 0 0x4000>; 1927 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1928 clock-names = "se"; 1929 pinctrl-names = "default"; 1930 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1931 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1932 #address-cells = <1>; 1933 #size-cells = <0>; 1934 power-domains = <&rpmhpd SC7280_CX>; 1935 operating-points-v2 = <&qup_opp_table>; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1938 interconnect-names = "qup-core", "qup-config"; 1939 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1940 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1941 dma-names = "tx", "rx"; 1942 status = "disabled"; 1943 }; 1944 1945 uart15: serial@a9c000 { 1946 compatible = "qcom,geni-uart"; 1947 reg = <0 0x00a9c000 0 0x4000>; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1949 clock-names = "se"; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1952 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1953 power-domains = <&rpmhpd SC7280_CX>; 1954 operating-points-v2 = <&qup_opp_table>; 1955 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1956 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1957 interconnect-names = "qup-core", "qup-config"; 1958 status = "disabled"; 1959 }; 1960 }; 1961 1962 cnoc2: interconnect@1500000 { 1963 reg = <0 0x01500000 0 0x1000>; 1964 compatible = "qcom,sc7280-cnoc2"; 1965 #interconnect-cells = <2>; 1966 qcom,bcm-voters = <&apps_bcm_voter>; 1967 }; 1968 1969 cnoc3: interconnect@1502000 { 1970 reg = <0 0x01502000 0 0x1000>; 1971 compatible = "qcom,sc7280-cnoc3"; 1972 #interconnect-cells = <2>; 1973 qcom,bcm-voters = <&apps_bcm_voter>; 1974 }; 1975 1976 mc_virt: interconnect@1580000 { 1977 reg = <0 0x01580000 0 0x4>; 1978 compatible = "qcom,sc7280-mc-virt"; 1979 #interconnect-cells = <2>; 1980 qcom,bcm-voters = <&apps_bcm_voter>; 1981 }; 1982 1983 system_noc: interconnect@1680000 { 1984 reg = <0 0x01680000 0 0x15480>; 1985 compatible = "qcom,sc7280-system-noc"; 1986 #interconnect-cells = <2>; 1987 qcom,bcm-voters = <&apps_bcm_voter>; 1988 }; 1989 1990 aggre1_noc: interconnect@16e0000 { 1991 compatible = "qcom,sc7280-aggre1-noc"; 1992 reg = <0 0x016e0000 0 0x1c080>; 1993 #interconnect-cells = <2>; 1994 qcom,bcm-voters = <&apps_bcm_voter>; 1995 }; 1996 1997 aggre2_noc: interconnect@1700000 { 1998 reg = <0 0x01700000 0 0x2b080>; 1999 compatible = "qcom,sc7280-aggre2-noc"; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 }; 2003 2004 mmss_noc: interconnect@1740000 { 2005 reg = <0 0x01740000 0 0x1e080>; 2006 compatible = "qcom,sc7280-mmss-noc"; 2007 #interconnect-cells = <2>; 2008 qcom,bcm-voters = <&apps_bcm_voter>; 2009 }; 2010 2011 wifi: wifi@17a10040 { 2012 compatible = "qcom,wcn6750-wifi"; 2013 reg = <0 0x17a10040 0 0x0>; 2014 iommus = <&apps_smmu 0x1c00 0x1>; 2015 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2016 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2017 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2018 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2019 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2020 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2021 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2022 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2023 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2024 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2025 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2026 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2027 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2028 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2029 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2030 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2031 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2047 qcom,rproc = <&remoteproc_wpss>; 2048 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2049 status = "disabled"; 2050 qcom,smem-states = <&wlan_smp2p_out 0>; 2051 qcom,smem-state-names = "wlan-smp2p-out"; 2052 }; 2053 2054 pcie1: pci@1c08000 { 2055 compatible = "qcom,pcie-sc7280"; 2056 reg = <0 0x01c08000 0 0x3000>, 2057 <0 0x40000000 0 0xf1d>, 2058 <0 0x40000f20 0 0xa8>, 2059 <0 0x40001000 0 0x1000>, 2060 <0 0x40100000 0 0x100000>; 2061 2062 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2063 device_type = "pci"; 2064 linux,pci-domain = <1>; 2065 bus-range = <0x00 0xff>; 2066 num-lanes = <2>; 2067 2068 #address-cells = <3>; 2069 #size-cells = <2>; 2070 2071 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2072 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2073 2074 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2075 interrupt-names = "msi"; 2076 #interrupt-cells = <1>; 2077 interrupt-map-mask = <0 0 0 0x7>; 2078 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2079 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2080 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2081 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2082 2083 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2084 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2085 <&pcie1_lane>, 2086 <&rpmhcc RPMH_CXO_CLK>, 2087 <&gcc GCC_PCIE_1_AUX_CLK>, 2088 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2089 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2090 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2091 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2092 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2093 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2094 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2095 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2096 2097 clock-names = "pipe", 2098 "pipe_mux", 2099 "phy_pipe", 2100 "ref", 2101 "aux", 2102 "cfg", 2103 "bus_master", 2104 "bus_slave", 2105 "slave_q2a", 2106 "tbu", 2107 "ddrss_sf_tbu", 2108 "aggre0", 2109 "aggre1"; 2110 2111 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2112 assigned-clock-rates = <19200000>; 2113 2114 resets = <&gcc GCC_PCIE_1_BCR>; 2115 reset-names = "pci"; 2116 2117 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2118 2119 phys = <&pcie1_lane>; 2120 phy-names = "pciephy"; 2121 2122 pinctrl-names = "default"; 2123 pinctrl-0 = <&pcie1_clkreq_n>; 2124 2125 iommus = <&apps_smmu 0x1c80 0x1>; 2126 2127 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2128 <0x100 &apps_smmu 0x1c81 0x1>; 2129 2130 status = "disabled"; 2131 }; 2132 2133 pcie1_phy: phy@1c0e000 { 2134 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2135 reg = <0 0x01c0e000 0 0x1c0>; 2136 #address-cells = <2>; 2137 #size-cells = <2>; 2138 ranges; 2139 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2140 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2141 <&gcc GCC_PCIE_CLKREF_EN>, 2142 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2143 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2144 2145 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2146 reset-names = "phy"; 2147 2148 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2149 assigned-clock-rates = <100000000>; 2150 2151 status = "disabled"; 2152 2153 pcie1_lane: phy@1c0e200 { 2154 reg = <0 0x01c0e200 0 0x170>, 2155 <0 0x01c0e400 0 0x200>, 2156 <0 0x01c0ea00 0 0x1f0>, 2157 <0 0x01c0e600 0 0x170>, 2158 <0 0x01c0e800 0 0x200>, 2159 <0 0x01c0ee00 0 0xf4>; 2160 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2161 clock-names = "pipe0"; 2162 2163 #phy-cells = <0>; 2164 #clock-cells = <0>; 2165 clock-output-names = "pcie_1_pipe_clk"; 2166 }; 2167 }; 2168 2169 ipa: ipa@1e40000 { 2170 compatible = "qcom,sc7280-ipa"; 2171 2172 iommus = <&apps_smmu 0x480 0x0>, 2173 <&apps_smmu 0x482 0x0>; 2174 reg = <0 0x1e40000 0 0x8000>, 2175 <0 0x1e50000 0 0x4ad0>, 2176 <0 0x1e04000 0 0x23000>; 2177 reg-names = "ipa-reg", 2178 "ipa-shared", 2179 "gsi"; 2180 2181 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2182 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2183 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2184 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2185 interrupt-names = "ipa", 2186 "gsi", 2187 "ipa-clock-query", 2188 "ipa-setup-ready"; 2189 2190 clocks = <&rpmhcc RPMH_IPA_CLK>; 2191 clock-names = "core"; 2192 2193 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2195 interconnect-names = "memory", 2196 "config"; 2197 2198 qcom,qmp = <&aoss_qmp>; 2199 2200 qcom,smem-states = <&ipa_smp2p_out 0>, 2201 <&ipa_smp2p_out 1>; 2202 qcom,smem-state-names = "ipa-clock-enabled-valid", 2203 "ipa-clock-enabled"; 2204 2205 status = "disabled"; 2206 }; 2207 2208 tcsr_mutex: hwlock@1f40000 { 2209 compatible = "qcom,tcsr-mutex"; 2210 reg = <0 0x01f40000 0 0x20000>; 2211 #hwlock-cells = <1>; 2212 }; 2213 2214 tcsr_1: syscon@1f60000 { 2215 compatible = "qcom,sc7280-tcsr", "syscon"; 2216 reg = <0 0x01f60000 0 0x20000>; 2217 }; 2218 2219 tcsr_2: syscon@1fc0000 { 2220 compatible = "qcom,sc7280-tcsr", "syscon"; 2221 reg = <0 0x01fc0000 0 0x30000>; 2222 }; 2223 2224 lpasscc: lpasscc@3000000 { 2225 compatible = "qcom,sc7280-lpasscc"; 2226 reg = <0 0x03000000 0 0x40>, 2227 <0 0x03c04000 0 0x4>; 2228 reg-names = "qdsp6ss", "top_cc"; 2229 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2230 clock-names = "iface"; 2231 #clock-cells = <1>; 2232 }; 2233 2234 lpass_rx_macro: codec@3200000 { 2235 compatible = "qcom,sc7280-lpass-rx-macro"; 2236 reg = <0 0x03200000 0 0x1000>; 2237 2238 pinctrl-names = "default"; 2239 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2240 2241 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2242 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2243 <&lpass_va_macro>; 2244 clock-names = "mclk", "npl", "fsgen"; 2245 2246 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2247 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2248 power-domain-names = "macro", "dcodec"; 2249 2250 #clock-cells = <0>; 2251 #sound-dai-cells = <1>; 2252 2253 status = "disabled"; 2254 }; 2255 2256 swr0: soundwire@3210000 { 2257 compatible = "qcom,soundwire-v1.6.0"; 2258 reg = <0 0x03210000 0 0x2000>; 2259 2260 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2261 clocks = <&lpass_rx_macro>; 2262 clock-names = "iface"; 2263 2264 qcom,din-ports = <0>; 2265 qcom,dout-ports = <5>; 2266 2267 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2268 reset-names = "swr_audio_cgcr"; 2269 2270 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2271 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2272 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2273 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2274 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2275 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2276 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2277 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2279 2280 #sound-dai-cells = <1>; 2281 #address-cells = <2>; 2282 #size-cells = <0>; 2283 2284 status = "disabled"; 2285 }; 2286 2287 lpass_tx_macro: codec@3220000 { 2288 compatible = "qcom,sc7280-lpass-tx-macro"; 2289 reg = <0 0x03220000 0 0x1000>; 2290 2291 pinctrl-names = "default"; 2292 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2293 2294 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2295 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2296 <&lpass_va_macro>; 2297 clock-names = "mclk", "npl", "fsgen"; 2298 2299 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2300 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2301 power-domain-names = "macro", "dcodec"; 2302 2303 #clock-cells = <0>; 2304 #sound-dai-cells = <1>; 2305 2306 status = "disabled"; 2307 }; 2308 2309 swr1: soundwire@3230000 { 2310 compatible = "qcom,soundwire-v1.6.0"; 2311 reg = <0 0x03230000 0 0x2000>; 2312 2313 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2314 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2315 clocks = <&lpass_tx_macro>; 2316 clock-names = "iface"; 2317 2318 qcom,din-ports = <3>; 2319 qcom,dout-ports = <0>; 2320 2321 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2322 reset-names = "swr_audio_cgcr"; 2323 2324 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2325 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2326 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2327 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2328 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2329 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2330 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2331 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2332 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2333 2334 #sound-dai-cells = <1>; 2335 #address-cells = <2>; 2336 #size-cells = <0>; 2337 2338 status = "disabled"; 2339 }; 2340 2341 lpass_audiocc: clock-controller@3300000 { 2342 compatible = "qcom,sc7280-lpassaudiocc"; 2343 reg = <0 0x03300000 0 0x30000>; 2344 clocks = <&rpmhcc RPMH_CXO_CLK>, 2345 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2346 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2347 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2348 #clock-cells = <1>; 2349 #power-domain-cells = <1>; 2350 #reset-cells = <1>; 2351 }; 2352 2353 lpass_va_macro: codec@3370000 { 2354 compatible = "qcom,sc7280-lpass-va-macro"; 2355 reg = <0 0x03370000 0 0x1000>; 2356 2357 pinctrl-names = "default"; 2358 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2359 2360 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2361 clock-names = "mclk"; 2362 2363 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2364 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2365 power-domain-names = "macro", "dcodec"; 2366 2367 #clock-cells = <0>; 2368 #sound-dai-cells = <1>; 2369 2370 status = "disabled"; 2371 }; 2372 2373 lpass_aon: clock-controller@3380000 { 2374 compatible = "qcom,sc7280-lpassaoncc"; 2375 reg = <0 0x03380000 0 0x30000>; 2376 clocks = <&rpmhcc RPMH_CXO_CLK>, 2377 <&rpmhcc RPMH_CXO_CLK_A>, 2378 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2379 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2380 #clock-cells = <1>; 2381 #power-domain-cells = <1>; 2382 }; 2383 2384 lpass_core: clock-controller@3900000 { 2385 compatible = "qcom,sc7280-lpasscorecc"; 2386 reg = <0 0x03900000 0 0x50000>; 2387 clocks = <&rpmhcc RPMH_CXO_CLK>; 2388 clock-names = "bi_tcxo"; 2389 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2390 #clock-cells = <1>; 2391 #power-domain-cells = <1>; 2392 }; 2393 2394 lpass_cpu: audio@3987000 { 2395 compatible = "qcom,sc7280-lpass-cpu"; 2396 2397 reg = <0 0x03987000 0 0x68000>, 2398 <0 0x03b00000 0 0x29000>, 2399 <0 0x03260000 0 0xc000>, 2400 <0 0x03280000 0 0x29000>, 2401 <0 0x03340000 0 0x29000>, 2402 <0 0x0336c000 0 0x3000>; 2403 reg-names = "lpass-hdmiif", 2404 "lpass-lpaif", 2405 "lpass-rxtx-cdc-dma-lpm", 2406 "lpass-rxtx-lpaif", 2407 "lpass-va-lpaif", 2408 "lpass-va-cdc-dma-lpm"; 2409 2410 iommus = <&apps_smmu 0x1820 0>, 2411 <&apps_smmu 0x1821 0>, 2412 <&apps_smmu 0x1832 0>; 2413 2414 power-domains = <&rpmhpd SC7280_LCX>; 2415 power-domain-names = "lcx"; 2416 required-opps = <&rpmhpd_opp_nom>; 2417 2418 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2419 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2420 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2421 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2422 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2423 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2424 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2425 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2426 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2427 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2428 clock-names = "aon_cc_audio_hm_h", 2429 "audio_cc_ext_mclk0", 2430 "core_cc_sysnoc_mport_core", 2431 "core_cc_ext_if0_ibit", 2432 "core_cc_ext_if1_ibit", 2433 "audio_cc_codec_mem", 2434 "audio_cc_codec_mem0", 2435 "audio_cc_codec_mem1", 2436 "audio_cc_codec_mem2", 2437 "aon_cc_va_mem0"; 2438 2439 #sound-dai-cells = <1>; 2440 #address-cells = <1>; 2441 #size-cells = <0>; 2442 2443 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2447 interrupt-names = "lpass-irq-lpaif", 2448 "lpass-irq-hdmi", 2449 "lpass-irq-vaif", 2450 "lpass-irq-rxtxif"; 2451 2452 status = "disabled"; 2453 }; 2454 2455 lpass_hm: clock-controller@3c00000 { 2456 compatible = "qcom,sc7280-lpasshm"; 2457 reg = <0 0x3c00000 0 0x28>; 2458 clocks = <&rpmhcc RPMH_CXO_CLK>; 2459 clock-names = "bi_tcxo"; 2460 #clock-cells = <1>; 2461 #power-domain-cells = <1>; 2462 }; 2463 2464 lpass_ag_noc: interconnect@3c40000 { 2465 reg = <0 0x03c40000 0 0xf080>; 2466 compatible = "qcom,sc7280-lpass-ag-noc"; 2467 #interconnect-cells = <2>; 2468 qcom,bcm-voters = <&apps_bcm_voter>; 2469 }; 2470 2471 lpass_tlmm: pinctrl@33c0000 { 2472 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2473 reg = <0 0x033c0000 0x0 0x20000>, 2474 <0 0x03550000 0x0 0x10000>; 2475 qcom,adsp-bypass-mode; 2476 gpio-controller; 2477 #gpio-cells = <2>; 2478 gpio-ranges = <&lpass_tlmm 0 0 15>; 2479 2480 lpass_dmic01_clk: dmic01-clk-state { 2481 pins = "gpio6"; 2482 function = "dmic1_clk"; 2483 }; 2484 2485 lpass_dmic01_clk_sleep: dmic01-clk-sleep-state { 2486 pins = "gpio6"; 2487 function = "dmic1_clk"; 2488 }; 2489 2490 lpass_dmic01_data: dmic01-data-state { 2491 pins = "gpio7"; 2492 function = "dmic1_data"; 2493 }; 2494 2495 lpass_dmic01_data_sleep: dmic01-data-sleep-state { 2496 pins = "gpio7"; 2497 function = "dmic1_data"; 2498 }; 2499 2500 lpass_dmic23_clk: dmic23-clk-state { 2501 pins = "gpio8"; 2502 function = "dmic2_clk"; 2503 }; 2504 2505 lpass_dmic23_clk_sleep: dmic23-clk-sleep-state { 2506 pins = "gpio8"; 2507 function = "dmic2_clk"; 2508 }; 2509 2510 lpass_dmic23_data: dmic23-data-state { 2511 pins = "gpio9"; 2512 function = "dmic2_data"; 2513 }; 2514 2515 lpass_dmic23_data_sleep: dmic23-data-sleep-state { 2516 pins = "gpio9"; 2517 function = "dmic2_data"; 2518 }; 2519 2520 lpass_rx_swr_clk: rx-swr-clk-state { 2521 pins = "gpio3"; 2522 function = "swr_rx_clk"; 2523 }; 2524 2525 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep-state { 2526 pins = "gpio3"; 2527 function = "swr_rx_clk"; 2528 }; 2529 2530 lpass_rx_swr_data: rx-swr-data-state { 2531 pins = "gpio4", "gpio5"; 2532 function = "swr_rx_data"; 2533 }; 2534 2535 lpass_rx_swr_data_sleep: rx-swr-data-sleep-state { 2536 pins = "gpio4", "gpio5"; 2537 function = "swr_rx_data"; 2538 }; 2539 2540 lpass_tx_swr_clk: tx-swr-clk-state { 2541 pins = "gpio0"; 2542 function = "swr_tx_clk"; 2543 }; 2544 2545 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep-state { 2546 pins = "gpio0"; 2547 function = "swr_tx_clk"; 2548 }; 2549 2550 lpass_tx_swr_data: tx-swr-data-state { 2551 pins = "gpio1", "gpio2", "gpio14"; 2552 function = "swr_tx_data"; 2553 }; 2554 2555 lpass_tx_swr_data_sleep: tx-swr-data-sleep-state { 2556 pins = "gpio1", "gpio2", "gpio14"; 2557 function = "swr_tx_data"; 2558 }; 2559 }; 2560 2561 gpu: gpu@3d00000 { 2562 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2563 reg = <0 0x03d00000 0 0x40000>, 2564 <0 0x03d9e000 0 0x1000>, 2565 <0 0x03d61000 0 0x800>; 2566 reg-names = "kgsl_3d0_reg_memory", 2567 "cx_mem", 2568 "cx_dbgc"; 2569 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2570 iommus = <&adreno_smmu 0 0x401>; 2571 operating-points-v2 = <&gpu_opp_table>; 2572 qcom,gmu = <&gmu>; 2573 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2574 interconnect-names = "gfx-mem"; 2575 #cooling-cells = <2>; 2576 2577 nvmem-cells = <&gpu_speed_bin>; 2578 nvmem-cell-names = "speed_bin"; 2579 2580 gpu_opp_table: opp-table { 2581 compatible = "operating-points-v2"; 2582 2583 opp-315000000 { 2584 opp-hz = /bits/ 64 <315000000>; 2585 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2586 opp-peak-kBps = <1804000>; 2587 opp-supported-hw = <0x03>; 2588 }; 2589 2590 opp-450000000 { 2591 opp-hz = /bits/ 64 <450000000>; 2592 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2593 opp-peak-kBps = <4068000>; 2594 opp-supported-hw = <0x03>; 2595 }; 2596 2597 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2598 opp-550000000-0 { 2599 opp-hz = /bits/ 64 <550000000>; 2600 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2601 opp-peak-kBps = <8368000>; 2602 opp-supported-hw = <0x01>; 2603 }; 2604 2605 opp-550000000-1 { 2606 opp-hz = /bits/ 64 <550000000>; 2607 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2608 opp-peak-kBps = <6832000>; 2609 opp-supported-hw = <0x02>; 2610 }; 2611 2612 opp-608000000 { 2613 opp-hz = /bits/ 64 <608000000>; 2614 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2615 opp-peak-kBps = <8368000>; 2616 opp-supported-hw = <0x02>; 2617 }; 2618 2619 opp-700000000 { 2620 opp-hz = /bits/ 64 <700000000>; 2621 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2622 opp-peak-kBps = <8532000>; 2623 opp-supported-hw = <0x02>; 2624 }; 2625 2626 opp-812000000 { 2627 opp-hz = /bits/ 64 <812000000>; 2628 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2629 opp-peak-kBps = <8532000>; 2630 opp-supported-hw = <0x02>; 2631 }; 2632 2633 opp-840000000 { 2634 opp-hz = /bits/ 64 <840000000>; 2635 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2636 opp-peak-kBps = <8532000>; 2637 opp-supported-hw = <0x02>; 2638 }; 2639 2640 opp-900000000 { 2641 opp-hz = /bits/ 64 <900000000>; 2642 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2643 opp-peak-kBps = <8532000>; 2644 opp-supported-hw = <0x02>; 2645 }; 2646 }; 2647 }; 2648 2649 gmu: gmu@3d6a000 { 2650 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2651 reg = <0 0x03d6a000 0 0x34000>, 2652 <0 0x3de0000 0 0x10000>, 2653 <0 0x0b290000 0 0x10000>; 2654 reg-names = "gmu", "rscc", "gmu_pdc"; 2655 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2656 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2657 interrupt-names = "hfi", "gmu"; 2658 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2659 <&gpucc GPU_CC_CXO_CLK>, 2660 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2661 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2662 <&gpucc GPU_CC_AHB_CLK>, 2663 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2664 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2665 clock-names = "gmu", 2666 "cxo", 2667 "axi", 2668 "memnoc", 2669 "ahb", 2670 "hub", 2671 "smmu_vote"; 2672 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2673 <&gpucc GPU_CC_GX_GDSC>; 2674 power-domain-names = "cx", 2675 "gx"; 2676 iommus = <&adreno_smmu 5 0x400>; 2677 operating-points-v2 = <&gmu_opp_table>; 2678 2679 gmu_opp_table: opp-table { 2680 compatible = "operating-points-v2"; 2681 2682 opp-200000000 { 2683 opp-hz = /bits/ 64 <200000000>; 2684 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2685 }; 2686 }; 2687 }; 2688 2689 gpucc: clock-controller@3d90000 { 2690 compatible = "qcom,sc7280-gpucc"; 2691 reg = <0 0x03d90000 0 0x9000>; 2692 clocks = <&rpmhcc RPMH_CXO_CLK>, 2693 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2694 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2695 clock-names = "bi_tcxo", 2696 "gcc_gpu_gpll0_clk_src", 2697 "gcc_gpu_gpll0_div_clk_src"; 2698 #clock-cells = <1>; 2699 #reset-cells = <1>; 2700 #power-domain-cells = <1>; 2701 }; 2702 2703 adreno_smmu: iommu@3da0000 { 2704 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2705 reg = <0 0x03da0000 0 0x20000>; 2706 #iommu-cells = <2>; 2707 #global-interrupts = <2>; 2708 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2720 2721 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2722 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2723 <&gpucc GPU_CC_AHB_CLK>, 2724 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2725 <&gpucc GPU_CC_CX_GMU_CLK>, 2726 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2727 <&gpucc GPU_CC_HUB_AON_CLK>; 2728 clock-names = "gcc_gpu_memnoc_gfx_clk", 2729 "gcc_gpu_snoc_dvm_gfx_clk", 2730 "gpu_cc_ahb_clk", 2731 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2732 "gpu_cc_cx_gmu_clk", 2733 "gpu_cc_hub_cx_int_clk", 2734 "gpu_cc_hub_aon_clk"; 2735 2736 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2737 }; 2738 2739 remoteproc_mpss: remoteproc@4080000 { 2740 compatible = "qcom,sc7280-mpss-pas"; 2741 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2742 reg-names = "qdsp6", "rmb"; 2743 2744 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2745 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2746 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2747 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2748 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2749 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2750 interrupt-names = "wdog", "fatal", "ready", "handover", 2751 "stop-ack", "shutdown-ack"; 2752 2753 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2754 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2755 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2756 <&rpmhcc RPMH_PKA_CLK>, 2757 <&rpmhcc RPMH_CXO_CLK>; 2758 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2759 2760 power-domains = <&rpmhpd SC7280_CX>, 2761 <&rpmhpd SC7280_MSS>; 2762 power-domain-names = "cx", "mss"; 2763 2764 memory-region = <&mpss_mem>; 2765 2766 qcom,qmp = <&aoss_qmp>; 2767 2768 qcom,smem-states = <&modem_smp2p_out 0>; 2769 qcom,smem-state-names = "stop"; 2770 2771 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2772 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2773 reset-names = "mss_restart", "pdc_reset"; 2774 2775 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2776 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2777 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2778 2779 status = "disabled"; 2780 2781 glink-edge { 2782 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2783 IPCC_MPROC_SIGNAL_GLINK_QMP 2784 IRQ_TYPE_EDGE_RISING>; 2785 mboxes = <&ipcc IPCC_CLIENT_MPSS 2786 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2787 label = "modem"; 2788 qcom,remote-pid = <1>; 2789 }; 2790 }; 2791 2792 stm@6002000 { 2793 compatible = "arm,coresight-stm", "arm,primecell"; 2794 reg = <0 0x06002000 0 0x1000>, 2795 <0 0x16280000 0 0x180000>; 2796 reg-names = "stm-base", "stm-stimulus-base"; 2797 2798 clocks = <&aoss_qmp>; 2799 clock-names = "apb_pclk"; 2800 2801 out-ports { 2802 port { 2803 stm_out: endpoint { 2804 remote-endpoint = <&funnel0_in7>; 2805 }; 2806 }; 2807 }; 2808 }; 2809 2810 funnel@6041000 { 2811 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2812 reg = <0 0x06041000 0 0x1000>; 2813 2814 clocks = <&aoss_qmp>; 2815 clock-names = "apb_pclk"; 2816 2817 out-ports { 2818 port { 2819 funnel0_out: endpoint { 2820 remote-endpoint = <&merge_funnel_in0>; 2821 }; 2822 }; 2823 }; 2824 2825 in-ports { 2826 #address-cells = <1>; 2827 #size-cells = <0>; 2828 2829 port@7 { 2830 reg = <7>; 2831 funnel0_in7: endpoint { 2832 remote-endpoint = <&stm_out>; 2833 }; 2834 }; 2835 }; 2836 }; 2837 2838 funnel@6042000 { 2839 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2840 reg = <0 0x06042000 0 0x1000>; 2841 2842 clocks = <&aoss_qmp>; 2843 clock-names = "apb_pclk"; 2844 2845 out-ports { 2846 port { 2847 funnel1_out: endpoint { 2848 remote-endpoint = <&merge_funnel_in1>; 2849 }; 2850 }; 2851 }; 2852 2853 in-ports { 2854 #address-cells = <1>; 2855 #size-cells = <0>; 2856 2857 port@4 { 2858 reg = <4>; 2859 funnel1_in4: endpoint { 2860 remote-endpoint = <&apss_merge_funnel_out>; 2861 }; 2862 }; 2863 }; 2864 }; 2865 2866 funnel@6045000 { 2867 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2868 reg = <0 0x06045000 0 0x1000>; 2869 2870 clocks = <&aoss_qmp>; 2871 clock-names = "apb_pclk"; 2872 2873 out-ports { 2874 port { 2875 merge_funnel_out: endpoint { 2876 remote-endpoint = <&swao_funnel_in>; 2877 }; 2878 }; 2879 }; 2880 2881 in-ports { 2882 #address-cells = <1>; 2883 #size-cells = <0>; 2884 2885 port@0 { 2886 reg = <0>; 2887 merge_funnel_in0: endpoint { 2888 remote-endpoint = <&funnel0_out>; 2889 }; 2890 }; 2891 2892 port@1 { 2893 reg = <1>; 2894 merge_funnel_in1: endpoint { 2895 remote-endpoint = <&funnel1_out>; 2896 }; 2897 }; 2898 }; 2899 }; 2900 2901 replicator@6046000 { 2902 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2903 reg = <0 0x06046000 0 0x1000>; 2904 2905 clocks = <&aoss_qmp>; 2906 clock-names = "apb_pclk"; 2907 2908 out-ports { 2909 port { 2910 replicator_out: endpoint { 2911 remote-endpoint = <&etr_in>; 2912 }; 2913 }; 2914 }; 2915 2916 in-ports { 2917 port { 2918 replicator_in: endpoint { 2919 remote-endpoint = <&swao_replicator_out>; 2920 }; 2921 }; 2922 }; 2923 }; 2924 2925 etr@6048000 { 2926 compatible = "arm,coresight-tmc", "arm,primecell"; 2927 reg = <0 0x06048000 0 0x1000>; 2928 iommus = <&apps_smmu 0x04c0 0>; 2929 2930 clocks = <&aoss_qmp>; 2931 clock-names = "apb_pclk"; 2932 arm,scatter-gather; 2933 2934 in-ports { 2935 port { 2936 etr_in: endpoint { 2937 remote-endpoint = <&replicator_out>; 2938 }; 2939 }; 2940 }; 2941 }; 2942 2943 funnel@6b04000 { 2944 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2945 reg = <0 0x06b04000 0 0x1000>; 2946 2947 clocks = <&aoss_qmp>; 2948 clock-names = "apb_pclk"; 2949 2950 out-ports { 2951 port { 2952 swao_funnel_out: endpoint { 2953 remote-endpoint = <&etf_in>; 2954 }; 2955 }; 2956 }; 2957 2958 in-ports { 2959 #address-cells = <1>; 2960 #size-cells = <0>; 2961 2962 port@7 { 2963 reg = <7>; 2964 swao_funnel_in: endpoint { 2965 remote-endpoint = <&merge_funnel_out>; 2966 }; 2967 }; 2968 }; 2969 }; 2970 2971 etf@6b05000 { 2972 compatible = "arm,coresight-tmc", "arm,primecell"; 2973 reg = <0 0x06b05000 0 0x1000>; 2974 2975 clocks = <&aoss_qmp>; 2976 clock-names = "apb_pclk"; 2977 2978 out-ports { 2979 port { 2980 etf_out: endpoint { 2981 remote-endpoint = <&swao_replicator_in>; 2982 }; 2983 }; 2984 }; 2985 2986 in-ports { 2987 port { 2988 etf_in: endpoint { 2989 remote-endpoint = <&swao_funnel_out>; 2990 }; 2991 }; 2992 }; 2993 }; 2994 2995 replicator@6b06000 { 2996 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2997 reg = <0 0x06b06000 0 0x1000>; 2998 2999 clocks = <&aoss_qmp>; 3000 clock-names = "apb_pclk"; 3001 qcom,replicator-loses-context; 3002 3003 out-ports { 3004 port { 3005 swao_replicator_out: endpoint { 3006 remote-endpoint = <&replicator_in>; 3007 }; 3008 }; 3009 }; 3010 3011 in-ports { 3012 port { 3013 swao_replicator_in: endpoint { 3014 remote-endpoint = <&etf_out>; 3015 }; 3016 }; 3017 }; 3018 }; 3019 3020 etm@7040000 { 3021 compatible = "arm,coresight-etm4x", "arm,primecell"; 3022 reg = <0 0x07040000 0 0x1000>; 3023 3024 cpu = <&CPU0>; 3025 3026 clocks = <&aoss_qmp>; 3027 clock-names = "apb_pclk"; 3028 arm,coresight-loses-context-with-cpu; 3029 qcom,skip-power-up; 3030 3031 out-ports { 3032 port { 3033 etm0_out: endpoint { 3034 remote-endpoint = <&apss_funnel_in0>; 3035 }; 3036 }; 3037 }; 3038 }; 3039 3040 etm@7140000 { 3041 compatible = "arm,coresight-etm4x", "arm,primecell"; 3042 reg = <0 0x07140000 0 0x1000>; 3043 3044 cpu = <&CPU1>; 3045 3046 clocks = <&aoss_qmp>; 3047 clock-names = "apb_pclk"; 3048 arm,coresight-loses-context-with-cpu; 3049 qcom,skip-power-up; 3050 3051 out-ports { 3052 port { 3053 etm1_out: endpoint { 3054 remote-endpoint = <&apss_funnel_in1>; 3055 }; 3056 }; 3057 }; 3058 }; 3059 3060 etm@7240000 { 3061 compatible = "arm,coresight-etm4x", "arm,primecell"; 3062 reg = <0 0x07240000 0 0x1000>; 3063 3064 cpu = <&CPU2>; 3065 3066 clocks = <&aoss_qmp>; 3067 clock-names = "apb_pclk"; 3068 arm,coresight-loses-context-with-cpu; 3069 qcom,skip-power-up; 3070 3071 out-ports { 3072 port { 3073 etm2_out: endpoint { 3074 remote-endpoint = <&apss_funnel_in2>; 3075 }; 3076 }; 3077 }; 3078 }; 3079 3080 etm@7340000 { 3081 compatible = "arm,coresight-etm4x", "arm,primecell"; 3082 reg = <0 0x07340000 0 0x1000>; 3083 3084 cpu = <&CPU3>; 3085 3086 clocks = <&aoss_qmp>; 3087 clock-names = "apb_pclk"; 3088 arm,coresight-loses-context-with-cpu; 3089 qcom,skip-power-up; 3090 3091 out-ports { 3092 port { 3093 etm3_out: endpoint { 3094 remote-endpoint = <&apss_funnel_in3>; 3095 }; 3096 }; 3097 }; 3098 }; 3099 3100 etm@7440000 { 3101 compatible = "arm,coresight-etm4x", "arm,primecell"; 3102 reg = <0 0x07440000 0 0x1000>; 3103 3104 cpu = <&CPU4>; 3105 3106 clocks = <&aoss_qmp>; 3107 clock-names = "apb_pclk"; 3108 arm,coresight-loses-context-with-cpu; 3109 qcom,skip-power-up; 3110 3111 out-ports { 3112 port { 3113 etm4_out: endpoint { 3114 remote-endpoint = <&apss_funnel_in4>; 3115 }; 3116 }; 3117 }; 3118 }; 3119 3120 etm@7540000 { 3121 compatible = "arm,coresight-etm4x", "arm,primecell"; 3122 reg = <0 0x07540000 0 0x1000>; 3123 3124 cpu = <&CPU5>; 3125 3126 clocks = <&aoss_qmp>; 3127 clock-names = "apb_pclk"; 3128 arm,coresight-loses-context-with-cpu; 3129 qcom,skip-power-up; 3130 3131 out-ports { 3132 port { 3133 etm5_out: endpoint { 3134 remote-endpoint = <&apss_funnel_in5>; 3135 }; 3136 }; 3137 }; 3138 }; 3139 3140 etm@7640000 { 3141 compatible = "arm,coresight-etm4x", "arm,primecell"; 3142 reg = <0 0x07640000 0 0x1000>; 3143 3144 cpu = <&CPU6>; 3145 3146 clocks = <&aoss_qmp>; 3147 clock-names = "apb_pclk"; 3148 arm,coresight-loses-context-with-cpu; 3149 qcom,skip-power-up; 3150 3151 out-ports { 3152 port { 3153 etm6_out: endpoint { 3154 remote-endpoint = <&apss_funnel_in6>; 3155 }; 3156 }; 3157 }; 3158 }; 3159 3160 etm@7740000 { 3161 compatible = "arm,coresight-etm4x", "arm,primecell"; 3162 reg = <0 0x07740000 0 0x1000>; 3163 3164 cpu = <&CPU7>; 3165 3166 clocks = <&aoss_qmp>; 3167 clock-names = "apb_pclk"; 3168 arm,coresight-loses-context-with-cpu; 3169 qcom,skip-power-up; 3170 3171 out-ports { 3172 port { 3173 etm7_out: endpoint { 3174 remote-endpoint = <&apss_funnel_in7>; 3175 }; 3176 }; 3177 }; 3178 }; 3179 3180 funnel@7800000 { /* APSS Funnel */ 3181 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3182 reg = <0 0x07800000 0 0x1000>; 3183 3184 clocks = <&aoss_qmp>; 3185 clock-names = "apb_pclk"; 3186 3187 out-ports { 3188 port { 3189 apss_funnel_out: endpoint { 3190 remote-endpoint = <&apss_merge_funnel_in>; 3191 }; 3192 }; 3193 }; 3194 3195 in-ports { 3196 #address-cells = <1>; 3197 #size-cells = <0>; 3198 3199 port@0 { 3200 reg = <0>; 3201 apss_funnel_in0: endpoint { 3202 remote-endpoint = <&etm0_out>; 3203 }; 3204 }; 3205 3206 port@1 { 3207 reg = <1>; 3208 apss_funnel_in1: endpoint { 3209 remote-endpoint = <&etm1_out>; 3210 }; 3211 }; 3212 3213 port@2 { 3214 reg = <2>; 3215 apss_funnel_in2: endpoint { 3216 remote-endpoint = <&etm2_out>; 3217 }; 3218 }; 3219 3220 port@3 { 3221 reg = <3>; 3222 apss_funnel_in3: endpoint { 3223 remote-endpoint = <&etm3_out>; 3224 }; 3225 }; 3226 3227 port@4 { 3228 reg = <4>; 3229 apss_funnel_in4: endpoint { 3230 remote-endpoint = <&etm4_out>; 3231 }; 3232 }; 3233 3234 port@5 { 3235 reg = <5>; 3236 apss_funnel_in5: endpoint { 3237 remote-endpoint = <&etm5_out>; 3238 }; 3239 }; 3240 3241 port@6 { 3242 reg = <6>; 3243 apss_funnel_in6: endpoint { 3244 remote-endpoint = <&etm6_out>; 3245 }; 3246 }; 3247 3248 port@7 { 3249 reg = <7>; 3250 apss_funnel_in7: endpoint { 3251 remote-endpoint = <&etm7_out>; 3252 }; 3253 }; 3254 }; 3255 }; 3256 3257 funnel@7810000 { 3258 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3259 reg = <0 0x07810000 0 0x1000>; 3260 3261 clocks = <&aoss_qmp>; 3262 clock-names = "apb_pclk"; 3263 3264 out-ports { 3265 port { 3266 apss_merge_funnel_out: endpoint { 3267 remote-endpoint = <&funnel1_in4>; 3268 }; 3269 }; 3270 }; 3271 3272 in-ports { 3273 port { 3274 apss_merge_funnel_in: endpoint { 3275 remote-endpoint = <&apss_funnel_out>; 3276 }; 3277 }; 3278 }; 3279 }; 3280 3281 sdhc_2: mmc@8804000 { 3282 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3283 pinctrl-names = "default", "sleep"; 3284 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3285 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3286 status = "disabled"; 3287 3288 reg = <0 0x08804000 0 0x1000>; 3289 3290 iommus = <&apps_smmu 0x100 0x0>; 3291 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3293 interrupt-names = "hc_irq", "pwr_irq"; 3294 3295 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3296 <&gcc GCC_SDCC2_APPS_CLK>, 3297 <&rpmhcc RPMH_CXO_CLK>; 3298 clock-names = "iface", "core", "xo"; 3299 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3300 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3301 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3302 power-domains = <&rpmhpd SC7280_CX>; 3303 operating-points-v2 = <&sdhc2_opp_table>; 3304 3305 bus-width = <4>; 3306 3307 qcom,dll-config = <0x0007642c>; 3308 3309 resets = <&gcc GCC_SDCC2_BCR>; 3310 3311 sdhc2_opp_table: opp-table { 3312 compatible = "operating-points-v2"; 3313 3314 opp-100000000 { 3315 opp-hz = /bits/ 64 <100000000>; 3316 required-opps = <&rpmhpd_opp_low_svs>; 3317 opp-peak-kBps = <1800000 400000>; 3318 opp-avg-kBps = <100000 0>; 3319 }; 3320 3321 opp-202000000 { 3322 opp-hz = /bits/ 64 <202000000>; 3323 required-opps = <&rpmhpd_opp_nom>; 3324 opp-peak-kBps = <5400000 1600000>; 3325 opp-avg-kBps = <200000 0>; 3326 }; 3327 }; 3328 3329 }; 3330 3331 usb_1_hsphy: phy@88e3000 { 3332 compatible = "qcom,sc7280-usb-hs-phy", 3333 "qcom,usb-snps-hs-7nm-phy"; 3334 reg = <0 0x088e3000 0 0x400>; 3335 status = "disabled"; 3336 #phy-cells = <0>; 3337 3338 clocks = <&rpmhcc RPMH_CXO_CLK>; 3339 clock-names = "ref"; 3340 3341 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3342 }; 3343 3344 usb_2_hsphy: phy@88e4000 { 3345 compatible = "qcom,sc7280-usb-hs-phy", 3346 "qcom,usb-snps-hs-7nm-phy"; 3347 reg = <0 0x088e4000 0 0x400>; 3348 status = "disabled"; 3349 #phy-cells = <0>; 3350 3351 clocks = <&rpmhcc RPMH_CXO_CLK>; 3352 clock-names = "ref"; 3353 3354 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3355 }; 3356 3357 usb_1_qmpphy: phy-wrapper@88e9000 { 3358 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3359 "qcom,sm8250-qmp-usb3-dp-phy"; 3360 reg = <0 0x088e9000 0 0x200>, 3361 <0 0x088e8000 0 0x40>, 3362 <0 0x088ea000 0 0x200>; 3363 status = "disabled"; 3364 #address-cells = <2>; 3365 #size-cells = <2>; 3366 ranges; 3367 3368 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3369 <&rpmhcc RPMH_CXO_CLK>, 3370 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3371 clock-names = "aux", "ref_clk_src", "com_aux"; 3372 3373 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3374 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3375 reset-names = "phy", "common"; 3376 3377 usb_1_ssphy: usb3-phy@88e9200 { 3378 reg = <0 0x088e9200 0 0x200>, 3379 <0 0x088e9400 0 0x200>, 3380 <0 0x088e9c00 0 0x400>, 3381 <0 0x088e9600 0 0x200>, 3382 <0 0x088e9800 0 0x200>, 3383 <0 0x088e9a00 0 0x100>; 3384 #clock-cells = <0>; 3385 #phy-cells = <0>; 3386 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3387 clock-names = "pipe0"; 3388 clock-output-names = "usb3_phy_pipe_clk_src"; 3389 }; 3390 3391 dp_phy: dp-phy@88ea200 { 3392 reg = <0 0x088ea200 0 0x200>, 3393 <0 0x088ea400 0 0x200>, 3394 <0 0x088eaa00 0 0x200>, 3395 <0 0x088ea600 0 0x200>, 3396 <0 0x088ea800 0 0x200>; 3397 #phy-cells = <0>; 3398 #clock-cells = <1>; 3399 }; 3400 }; 3401 3402 usb_2: usb@8cf8800 { 3403 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3404 reg = <0 0x08cf8800 0 0x400>; 3405 status = "disabled"; 3406 #address-cells = <2>; 3407 #size-cells = <2>; 3408 ranges; 3409 dma-ranges; 3410 3411 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3412 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3413 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3414 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3415 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3416 clock-names = "cfg_noc", 3417 "core", 3418 "iface", 3419 "sleep", 3420 "mock_utmi"; 3421 3422 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3423 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3424 assigned-clock-rates = <19200000>, <200000000>; 3425 3426 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3427 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3428 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3429 interrupt-names = "hs_phy_irq", 3430 "dp_hs_phy_irq", 3431 "dm_hs_phy_irq"; 3432 3433 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3434 required-opps = <&rpmhpd_opp_nom>; 3435 3436 resets = <&gcc GCC_USB30_SEC_BCR>; 3437 3438 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3439 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3440 interconnect-names = "usb-ddr", "apps-usb"; 3441 3442 usb_2_dwc3: usb@8c00000 { 3443 compatible = "snps,dwc3"; 3444 reg = <0 0x08c00000 0 0xe000>; 3445 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3446 iommus = <&apps_smmu 0xa0 0x0>; 3447 snps,dis_u2_susphy_quirk; 3448 snps,dis_enblslpm_quirk; 3449 phys = <&usb_2_hsphy>; 3450 phy-names = "usb2-phy"; 3451 maximum-speed = "high-speed"; 3452 usb-role-switch; 3453 port { 3454 usb2_role_switch: endpoint { 3455 remote-endpoint = <&eud_ep>; 3456 }; 3457 }; 3458 }; 3459 }; 3460 3461 qspi: spi@88dc000 { 3462 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3463 reg = <0 0x088dc000 0 0x1000>; 3464 #address-cells = <1>; 3465 #size-cells = <0>; 3466 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3467 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3468 <&gcc GCC_QSPI_CORE_CLK>; 3469 clock-names = "iface", "core"; 3470 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3471 &cnoc2 SLAVE_QSPI_0 0>; 3472 interconnect-names = "qspi-config"; 3473 power-domains = <&rpmhpd SC7280_CX>; 3474 operating-points-v2 = <&qspi_opp_table>; 3475 status = "disabled"; 3476 }; 3477 3478 remoteproc_wpss: remoteproc@8a00000 { 3479 compatible = "qcom,sc7280-wpss-pil"; 3480 reg = <0 0x08a00000 0 0x10000>; 3481 3482 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3483 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3484 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3485 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3486 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3487 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3488 interrupt-names = "wdog", "fatal", "ready", "handover", 3489 "stop-ack", "shutdown-ack"; 3490 3491 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3492 <&gcc GCC_WPSS_AHB_CLK>, 3493 <&gcc GCC_WPSS_RSCP_CLK>, 3494 <&rpmhcc RPMH_CXO_CLK>; 3495 clock-names = "ahb_bdg", "ahb", 3496 "rscp", "xo"; 3497 3498 power-domains = <&rpmhpd SC7280_CX>, 3499 <&rpmhpd SC7280_MX>; 3500 power-domain-names = "cx", "mx"; 3501 3502 memory-region = <&wpss_mem>; 3503 3504 qcom,qmp = <&aoss_qmp>; 3505 3506 qcom,smem-states = <&wpss_smp2p_out 0>; 3507 qcom,smem-state-names = "stop"; 3508 3509 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3510 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3511 reset-names = "restart", "pdc_sync"; 3512 3513 qcom,halt-regs = <&tcsr_1 0x17000>; 3514 3515 status = "disabled"; 3516 3517 glink-edge { 3518 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3519 IPCC_MPROC_SIGNAL_GLINK_QMP 3520 IRQ_TYPE_EDGE_RISING>; 3521 mboxes = <&ipcc IPCC_CLIENT_WPSS 3522 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3523 3524 label = "wpss"; 3525 qcom,remote-pid = <13>; 3526 }; 3527 }; 3528 3529 pmu@9091000 { 3530 compatible = "qcom,sc7280-llcc-bwmon"; 3531 reg = <0 0x9091000 0 0x1000>; 3532 3533 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3534 3535 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3536 3537 operating-points-v2 = <&llcc_bwmon_opp_table>; 3538 3539 llcc_bwmon_opp_table: opp-table { 3540 compatible = "operating-points-v2"; 3541 3542 opp-0 { 3543 opp-peak-kBps = <800000>; 3544 }; 3545 opp-1 { 3546 opp-peak-kBps = <1804000>; 3547 }; 3548 opp-2 { 3549 opp-peak-kBps = <2188000>; 3550 }; 3551 opp-3 { 3552 opp-peak-kBps = <3072000>; 3553 }; 3554 opp-4 { 3555 opp-peak-kBps = <4068000>; 3556 }; 3557 opp-5 { 3558 opp-peak-kBps = <6220000>; 3559 }; 3560 opp-6 { 3561 opp-peak-kBps = <6832000>; 3562 }; 3563 opp-7 { 3564 opp-peak-kBps = <8532000>; 3565 }; 3566 }; 3567 }; 3568 3569 pmu@90b6400 { 3570 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3571 reg = <0 0x090b6400 0 0x600>; 3572 3573 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3574 3575 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3576 operating-points-v2 = <&cpu_bwmon_opp_table>; 3577 3578 cpu_bwmon_opp_table: opp-table { 3579 compatible = "operating-points-v2"; 3580 3581 opp-0 { 3582 opp-peak-kBps = <2400000>; 3583 }; 3584 opp-1 { 3585 opp-peak-kBps = <4800000>; 3586 }; 3587 opp-2 { 3588 opp-peak-kBps = <7456000>; 3589 }; 3590 opp-3 { 3591 opp-peak-kBps = <9600000>; 3592 }; 3593 opp-4 { 3594 opp-peak-kBps = <12896000>; 3595 }; 3596 opp-5 { 3597 opp-peak-kBps = <14928000>; 3598 }; 3599 opp-6 { 3600 opp-peak-kBps = <17056000>; 3601 }; 3602 }; 3603 }; 3604 3605 dc_noc: interconnect@90e0000 { 3606 reg = <0 0x090e0000 0 0x5080>; 3607 compatible = "qcom,sc7280-dc-noc"; 3608 #interconnect-cells = <2>; 3609 qcom,bcm-voters = <&apps_bcm_voter>; 3610 }; 3611 3612 gem_noc: interconnect@9100000 { 3613 reg = <0 0x9100000 0 0xe2200>; 3614 compatible = "qcom,sc7280-gem-noc"; 3615 #interconnect-cells = <2>; 3616 qcom,bcm-voters = <&apps_bcm_voter>; 3617 }; 3618 3619 system-cache-controller@9200000 { 3620 compatible = "qcom,sc7280-llcc"; 3621 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3622 reg-names = "llcc_base", "llcc_broadcast_base"; 3623 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3624 }; 3625 3626 eud: eud@88e0000 { 3627 compatible = "qcom,sc7280-eud","qcom,eud"; 3628 reg = <0 0x88e0000 0 0x2000>, 3629 <0 0x88e2000 0 0x1000>; 3630 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3631 ports { 3632 port@0 { 3633 eud_ep: endpoint { 3634 remote-endpoint = <&usb2_role_switch>; 3635 }; 3636 }; 3637 port@1 { 3638 eud_con: endpoint { 3639 remote-endpoint = <&con_eud>; 3640 }; 3641 }; 3642 }; 3643 }; 3644 3645 eud_typec: connector { 3646 compatible = "usb-c-connector"; 3647 ports { 3648 port@0 { 3649 con_eud: endpoint { 3650 remote-endpoint = <&eud_con>; 3651 }; 3652 }; 3653 }; 3654 }; 3655 3656 nsp_noc: interconnect@a0c0000 { 3657 reg = <0 0x0a0c0000 0 0x10000>; 3658 compatible = "qcom,sc7280-nsp-noc"; 3659 #interconnect-cells = <2>; 3660 qcom,bcm-voters = <&apps_bcm_voter>; 3661 }; 3662 3663 usb_1: usb@a6f8800 { 3664 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3665 reg = <0 0x0a6f8800 0 0x400>; 3666 status = "disabled"; 3667 #address-cells = <2>; 3668 #size-cells = <2>; 3669 ranges; 3670 dma-ranges; 3671 3672 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3673 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3674 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3675 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3676 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3677 clock-names = "cfg_noc", 3678 "core", 3679 "iface", 3680 "sleep", 3681 "mock_utmi"; 3682 3683 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3684 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3685 assigned-clock-rates = <19200000>, <200000000>; 3686 3687 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3688 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3689 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3690 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3691 interrupt-names = "hs_phy_irq", 3692 "dp_hs_phy_irq", 3693 "dm_hs_phy_irq", 3694 "ss_phy_irq"; 3695 3696 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3697 required-opps = <&rpmhpd_opp_nom>; 3698 3699 resets = <&gcc GCC_USB30_PRIM_BCR>; 3700 3701 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3702 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3703 interconnect-names = "usb-ddr", "apps-usb"; 3704 3705 wakeup-source; 3706 3707 usb_1_dwc3: usb@a600000 { 3708 compatible = "snps,dwc3"; 3709 reg = <0 0x0a600000 0 0xe000>; 3710 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3711 iommus = <&apps_smmu 0xe0 0x0>; 3712 snps,dis_u2_susphy_quirk; 3713 snps,dis_enblslpm_quirk; 3714 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3715 phy-names = "usb2-phy", "usb3-phy"; 3716 maximum-speed = "super-speed"; 3717 }; 3718 }; 3719 3720 venus: video-codec@aa00000 { 3721 compatible = "qcom,sc7280-venus"; 3722 reg = <0 0x0aa00000 0 0xd0600>; 3723 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3724 3725 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3726 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3727 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3728 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3729 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3730 clock-names = "core", "bus", "iface", 3731 "vcodec_core", "vcodec_bus"; 3732 3733 power-domains = <&videocc MVSC_GDSC>, 3734 <&videocc MVS0_GDSC>, 3735 <&rpmhpd SC7280_CX>; 3736 power-domain-names = "venus", "vcodec0", "cx"; 3737 operating-points-v2 = <&venus_opp_table>; 3738 3739 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3740 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3741 interconnect-names = "cpu-cfg", "video-mem"; 3742 3743 iommus = <&apps_smmu 0x2180 0x20>, 3744 <&apps_smmu 0x2184 0x20>; 3745 memory-region = <&video_mem>; 3746 3747 video-decoder { 3748 compatible = "venus-decoder"; 3749 }; 3750 3751 video-encoder { 3752 compatible = "venus-encoder"; 3753 }; 3754 3755 video-firmware { 3756 iommus = <&apps_smmu 0x21a2 0x0>; 3757 }; 3758 3759 venus_opp_table: opp-table { 3760 compatible = "operating-points-v2"; 3761 3762 opp-133330000 { 3763 opp-hz = /bits/ 64 <133330000>; 3764 required-opps = <&rpmhpd_opp_low_svs>; 3765 }; 3766 3767 opp-240000000 { 3768 opp-hz = /bits/ 64 <240000000>; 3769 required-opps = <&rpmhpd_opp_svs>; 3770 }; 3771 3772 opp-335000000 { 3773 opp-hz = /bits/ 64 <335000000>; 3774 required-opps = <&rpmhpd_opp_svs_l1>; 3775 }; 3776 3777 opp-424000000 { 3778 opp-hz = /bits/ 64 <424000000>; 3779 required-opps = <&rpmhpd_opp_nom>; 3780 }; 3781 3782 opp-460000048 { 3783 opp-hz = /bits/ 64 <460000048>; 3784 required-opps = <&rpmhpd_opp_turbo>; 3785 }; 3786 }; 3787 3788 }; 3789 3790 videocc: clock-controller@aaf0000 { 3791 compatible = "qcom,sc7280-videocc"; 3792 reg = <0 0xaaf0000 0 0x10000>; 3793 clocks = <&rpmhcc RPMH_CXO_CLK>, 3794 <&rpmhcc RPMH_CXO_CLK_A>; 3795 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3796 #clock-cells = <1>; 3797 #reset-cells = <1>; 3798 #power-domain-cells = <1>; 3799 }; 3800 3801 camcc: clock-controller@ad00000 { 3802 compatible = "qcom,sc7280-camcc"; 3803 reg = <0 0x0ad00000 0 0x10000>; 3804 clocks = <&rpmhcc RPMH_CXO_CLK>, 3805 <&rpmhcc RPMH_CXO_CLK_A>, 3806 <&sleep_clk>; 3807 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3808 #clock-cells = <1>; 3809 #reset-cells = <1>; 3810 #power-domain-cells = <1>; 3811 }; 3812 3813 dispcc: clock-controller@af00000 { 3814 compatible = "qcom,sc7280-dispcc"; 3815 reg = <0 0xaf00000 0 0x20000>; 3816 clocks = <&rpmhcc RPMH_CXO_CLK>, 3817 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3818 <&mdss_dsi_phy 0>, 3819 <&mdss_dsi_phy 1>, 3820 <&dp_phy 0>, 3821 <&dp_phy 1>, 3822 <&mdss_edp_phy 0>, 3823 <&mdss_edp_phy 1>; 3824 clock-names = "bi_tcxo", 3825 "gcc_disp_gpll0_clk", 3826 "dsi0_phy_pll_out_byteclk", 3827 "dsi0_phy_pll_out_dsiclk", 3828 "dp_phy_pll_link_clk", 3829 "dp_phy_pll_vco_div_clk", 3830 "edp_phy_pll_link_clk", 3831 "edp_phy_pll_vco_div_clk"; 3832 #clock-cells = <1>; 3833 #reset-cells = <1>; 3834 #power-domain-cells = <1>; 3835 }; 3836 3837 mdss: display-subsystem@ae00000 { 3838 compatible = "qcom,sc7280-mdss"; 3839 reg = <0 0x0ae00000 0 0x1000>; 3840 reg-names = "mdss"; 3841 3842 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3843 3844 clocks = <&gcc GCC_DISP_AHB_CLK>, 3845 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3846 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3847 clock-names = "iface", 3848 "ahb", 3849 "core"; 3850 3851 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3852 interrupt-controller; 3853 #interrupt-cells = <1>; 3854 3855 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3856 interconnect-names = "mdp0-mem"; 3857 3858 iommus = <&apps_smmu 0x900 0x402>; 3859 3860 #address-cells = <2>; 3861 #size-cells = <2>; 3862 ranges; 3863 3864 status = "disabled"; 3865 3866 mdss_mdp: display-controller@ae01000 { 3867 compatible = "qcom,sc7280-dpu"; 3868 reg = <0 0x0ae01000 0 0x8f030>, 3869 <0 0x0aeb0000 0 0x2008>; 3870 reg-names = "mdp", "vbif"; 3871 3872 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3873 <&gcc GCC_DISP_SF_AXI_CLK>, 3874 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3875 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3876 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3877 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3878 clock-names = "bus", 3879 "nrt_bus", 3880 "iface", 3881 "lut", 3882 "core", 3883 "vsync"; 3884 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3885 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3886 assigned-clock-rates = <19200000>, 3887 <19200000>; 3888 operating-points-v2 = <&mdp_opp_table>; 3889 power-domains = <&rpmhpd SC7280_CX>; 3890 3891 interrupt-parent = <&mdss>; 3892 interrupts = <0>; 3893 3894 status = "disabled"; 3895 3896 ports { 3897 #address-cells = <1>; 3898 #size-cells = <0>; 3899 3900 port@0 { 3901 reg = <0>; 3902 dpu_intf1_out: endpoint { 3903 remote-endpoint = <&dsi0_in>; 3904 }; 3905 }; 3906 3907 port@1 { 3908 reg = <1>; 3909 dpu_intf5_out: endpoint { 3910 remote-endpoint = <&edp_in>; 3911 }; 3912 }; 3913 3914 port@2 { 3915 reg = <2>; 3916 dpu_intf0_out: endpoint { 3917 remote-endpoint = <&dp_in>; 3918 }; 3919 }; 3920 }; 3921 3922 mdp_opp_table: opp-table { 3923 compatible = "operating-points-v2"; 3924 3925 opp-200000000 { 3926 opp-hz = /bits/ 64 <200000000>; 3927 required-opps = <&rpmhpd_opp_low_svs>; 3928 }; 3929 3930 opp-300000000 { 3931 opp-hz = /bits/ 64 <300000000>; 3932 required-opps = <&rpmhpd_opp_svs>; 3933 }; 3934 3935 opp-380000000 { 3936 opp-hz = /bits/ 64 <380000000>; 3937 required-opps = <&rpmhpd_opp_svs_l1>; 3938 }; 3939 3940 opp-506666667 { 3941 opp-hz = /bits/ 64 <506666667>; 3942 required-opps = <&rpmhpd_opp_nom>; 3943 }; 3944 }; 3945 }; 3946 3947 mdss_dsi: dsi@ae94000 { 3948 compatible = "qcom,mdss-dsi-ctrl"; 3949 reg = <0 0x0ae94000 0 0x400>; 3950 reg-names = "dsi_ctrl"; 3951 3952 interrupt-parent = <&mdss>; 3953 interrupts = <4>; 3954 3955 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3956 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3957 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3958 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3959 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3960 <&gcc GCC_DISP_HF_AXI_CLK>; 3961 clock-names = "byte", 3962 "byte_intf", 3963 "pixel", 3964 "core", 3965 "iface", 3966 "bus"; 3967 3968 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3969 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3970 3971 operating-points-v2 = <&dsi_opp_table>; 3972 power-domains = <&rpmhpd SC7280_CX>; 3973 3974 phys = <&mdss_dsi_phy>; 3975 3976 #address-cells = <1>; 3977 #size-cells = <0>; 3978 3979 status = "disabled"; 3980 3981 ports { 3982 #address-cells = <1>; 3983 #size-cells = <0>; 3984 3985 port@0 { 3986 reg = <0>; 3987 dsi0_in: endpoint { 3988 remote-endpoint = <&dpu_intf1_out>; 3989 }; 3990 }; 3991 3992 port@1 { 3993 reg = <1>; 3994 dsi0_out: endpoint { 3995 }; 3996 }; 3997 }; 3998 3999 dsi_opp_table: opp-table { 4000 compatible = "operating-points-v2"; 4001 4002 opp-187500000 { 4003 opp-hz = /bits/ 64 <187500000>; 4004 required-opps = <&rpmhpd_opp_low_svs>; 4005 }; 4006 4007 opp-300000000 { 4008 opp-hz = /bits/ 64 <300000000>; 4009 required-opps = <&rpmhpd_opp_svs>; 4010 }; 4011 4012 opp-358000000 { 4013 opp-hz = /bits/ 64 <358000000>; 4014 required-opps = <&rpmhpd_opp_svs_l1>; 4015 }; 4016 }; 4017 }; 4018 4019 mdss_dsi_phy: phy@ae94400 { 4020 compatible = "qcom,sc7280-dsi-phy-7nm"; 4021 reg = <0 0x0ae94400 0 0x200>, 4022 <0 0x0ae94600 0 0x280>, 4023 <0 0x0ae94900 0 0x280>; 4024 reg-names = "dsi_phy", 4025 "dsi_phy_lane", 4026 "dsi_pll"; 4027 4028 #clock-cells = <1>; 4029 #phy-cells = <0>; 4030 4031 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4032 <&rpmhcc RPMH_CXO_CLK>; 4033 clock-names = "iface", "ref"; 4034 4035 status = "disabled"; 4036 }; 4037 4038 mdss_edp: edp@aea0000 { 4039 compatible = "qcom,sc7280-edp"; 4040 pinctrl-names = "default"; 4041 pinctrl-0 = <&edp_hot_plug_det>; 4042 4043 reg = <0 0xaea0000 0 0x200>, 4044 <0 0xaea0200 0 0x200>, 4045 <0 0xaea0400 0 0xc00>, 4046 <0 0xaea1000 0 0x400>; 4047 4048 interrupt-parent = <&mdss>; 4049 interrupts = <14>; 4050 4051 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4052 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4053 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4054 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4055 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4056 clock-names = "core_iface", 4057 "core_aux", 4058 "ctrl_link", 4059 "ctrl_link_iface", 4060 "stream_pixel"; 4061 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4062 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4063 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4064 4065 phys = <&mdss_edp_phy>; 4066 phy-names = "dp"; 4067 4068 operating-points-v2 = <&edp_opp_table>; 4069 power-domains = <&rpmhpd SC7280_CX>; 4070 4071 status = "disabled"; 4072 4073 ports { 4074 #address-cells = <1>; 4075 #size-cells = <0>; 4076 4077 port@0 { 4078 reg = <0>; 4079 edp_in: endpoint { 4080 remote-endpoint = <&dpu_intf5_out>; 4081 }; 4082 }; 4083 4084 port@1 { 4085 reg = <1>; 4086 mdss_edp_out: endpoint { }; 4087 }; 4088 }; 4089 4090 edp_opp_table: opp-table { 4091 compatible = "operating-points-v2"; 4092 4093 opp-160000000 { 4094 opp-hz = /bits/ 64 <160000000>; 4095 required-opps = <&rpmhpd_opp_low_svs>; 4096 }; 4097 4098 opp-270000000 { 4099 opp-hz = /bits/ 64 <270000000>; 4100 required-opps = <&rpmhpd_opp_svs>; 4101 }; 4102 4103 opp-540000000 { 4104 opp-hz = /bits/ 64 <540000000>; 4105 required-opps = <&rpmhpd_opp_nom>; 4106 }; 4107 4108 opp-810000000 { 4109 opp-hz = /bits/ 64 <810000000>; 4110 required-opps = <&rpmhpd_opp_nom>; 4111 }; 4112 }; 4113 }; 4114 4115 mdss_edp_phy: phy@aec2a00 { 4116 compatible = "qcom,sc7280-edp-phy"; 4117 4118 reg = <0 0xaec2a00 0 0x19c>, 4119 <0 0xaec2200 0 0xa0>, 4120 <0 0xaec2600 0 0xa0>, 4121 <0 0xaec2000 0 0x1c0>; 4122 4123 clocks = <&rpmhcc RPMH_CXO_CLK>, 4124 <&gcc GCC_EDP_CLKREF_EN>; 4125 clock-names = "aux", 4126 "cfg_ahb"; 4127 4128 #clock-cells = <1>; 4129 #phy-cells = <0>; 4130 4131 status = "disabled"; 4132 }; 4133 4134 mdss_dp: displayport-controller@ae90000 { 4135 compatible = "qcom,sc7280-dp"; 4136 4137 reg = <0 0xae90000 0 0x200>, 4138 <0 0xae90200 0 0x200>, 4139 <0 0xae90400 0 0xc00>, 4140 <0 0xae91000 0 0x400>, 4141 <0 0xae91400 0 0x400>; 4142 4143 interrupt-parent = <&mdss>; 4144 interrupts = <12>; 4145 4146 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4147 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4148 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4149 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4150 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4151 clock-names = "core_iface", 4152 "core_aux", 4153 "ctrl_link", 4154 "ctrl_link_iface", 4155 "stream_pixel"; 4156 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4157 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4158 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4159 phys = <&dp_phy>; 4160 phy-names = "dp"; 4161 4162 operating-points-v2 = <&dp_opp_table>; 4163 power-domains = <&rpmhpd SC7280_CX>; 4164 4165 #sound-dai-cells = <0>; 4166 4167 status = "disabled"; 4168 4169 ports { 4170 #address-cells = <1>; 4171 #size-cells = <0>; 4172 4173 port@0 { 4174 reg = <0>; 4175 dp_in: endpoint { 4176 remote-endpoint = <&dpu_intf0_out>; 4177 }; 4178 }; 4179 4180 port@1 { 4181 reg = <1>; 4182 dp_out: endpoint { }; 4183 }; 4184 }; 4185 4186 dp_opp_table: opp-table { 4187 compatible = "operating-points-v2"; 4188 4189 opp-160000000 { 4190 opp-hz = /bits/ 64 <160000000>; 4191 required-opps = <&rpmhpd_opp_low_svs>; 4192 }; 4193 4194 opp-270000000 { 4195 opp-hz = /bits/ 64 <270000000>; 4196 required-opps = <&rpmhpd_opp_svs>; 4197 }; 4198 4199 opp-540000000 { 4200 opp-hz = /bits/ 64 <540000000>; 4201 required-opps = <&rpmhpd_opp_svs_l1>; 4202 }; 4203 4204 opp-810000000 { 4205 opp-hz = /bits/ 64 <810000000>; 4206 required-opps = <&rpmhpd_opp_nom>; 4207 }; 4208 }; 4209 }; 4210 }; 4211 4212 pdc: interrupt-controller@b220000 { 4213 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4214 reg = <0 0x0b220000 0 0x30000>; 4215 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4216 <55 306 4>, <59 312 3>, <62 374 2>, 4217 <64 434 2>, <66 438 3>, <69 86 1>, 4218 <70 520 54>, <124 609 31>, <155 63 1>, 4219 <156 716 12>; 4220 #interrupt-cells = <2>; 4221 interrupt-parent = <&intc>; 4222 interrupt-controller; 4223 }; 4224 4225 pdc_reset: reset-controller@b5e0000 { 4226 compatible = "qcom,sc7280-pdc-global"; 4227 reg = <0 0x0b5e0000 0 0x20000>; 4228 #reset-cells = <1>; 4229 }; 4230 4231 tsens0: thermal-sensor@c263000 { 4232 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4233 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4234 <0 0x0c222000 0 0x1ff>; /* SROT */ 4235 #qcom,sensors = <15>; 4236 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4238 interrupt-names = "uplow","critical"; 4239 #thermal-sensor-cells = <1>; 4240 }; 4241 4242 tsens1: thermal-sensor@c265000 { 4243 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4244 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4245 <0 0x0c223000 0 0x1ff>; /* SROT */ 4246 #qcom,sensors = <12>; 4247 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4249 interrupt-names = "uplow","critical"; 4250 #thermal-sensor-cells = <1>; 4251 }; 4252 4253 aoss_reset: reset-controller@c2a0000 { 4254 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4255 reg = <0 0x0c2a0000 0 0x31000>; 4256 #reset-cells = <1>; 4257 }; 4258 4259 aoss_qmp: power-controller@c300000 { 4260 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4261 reg = <0 0x0c300000 0 0x400>; 4262 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4263 IPCC_MPROC_SIGNAL_GLINK_QMP 4264 IRQ_TYPE_EDGE_RISING>; 4265 mboxes = <&ipcc IPCC_CLIENT_AOP 4266 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4267 4268 #clock-cells = <0>; 4269 }; 4270 4271 sram@c3f0000 { 4272 compatible = "qcom,rpmh-stats"; 4273 reg = <0 0x0c3f0000 0 0x400>; 4274 }; 4275 4276 spmi_bus: spmi@c440000 { 4277 compatible = "qcom,spmi-pmic-arb"; 4278 reg = <0 0x0c440000 0 0x1100>, 4279 <0 0x0c600000 0 0x2000000>, 4280 <0 0x0e600000 0 0x100000>, 4281 <0 0x0e700000 0 0xa0000>, 4282 <0 0x0c40a000 0 0x26000>; 4283 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4284 interrupt-names = "periph_irq"; 4285 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4286 qcom,ee = <0>; 4287 qcom,channel = <0>; 4288 #address-cells = <1>; 4289 #size-cells = <1>; 4290 interrupt-controller; 4291 #interrupt-cells = <4>; 4292 }; 4293 4294 tlmm: pinctrl@f100000 { 4295 compatible = "qcom,sc7280-pinctrl"; 4296 reg = <0 0x0f100000 0 0x300000>; 4297 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4298 gpio-controller; 4299 #gpio-cells = <2>; 4300 interrupt-controller; 4301 #interrupt-cells = <2>; 4302 gpio-ranges = <&tlmm 0 0 175>; 4303 wakeup-parent = <&pdc>; 4304 4305 dp_hot_plug_det: dp-hot-plug-det-state { 4306 pins = "gpio47"; 4307 function = "dp_hot"; 4308 }; 4309 4310 edp_hot_plug_det: edp-hot-plug-det-state { 4311 pins = "gpio60"; 4312 function = "edp_hot"; 4313 }; 4314 4315 mi2s0_data0: mi2s0-data0-state { 4316 pins = "gpio98"; 4317 function = "mi2s0_data0"; 4318 }; 4319 4320 mi2s0_data1: mi2s0-data1-state { 4321 pins = "gpio99"; 4322 function = "mi2s0_data1"; 4323 }; 4324 4325 mi2s0_mclk: mi2s0-mclk-state { 4326 pins = "gpio96"; 4327 function = "pri_mi2s"; 4328 }; 4329 4330 mi2s0_sclk: mi2s0-sclk-state { 4331 pins = "gpio97"; 4332 function = "mi2s0_sck"; 4333 }; 4334 4335 mi2s0_ws: mi2s0-ws-state { 4336 pins = "gpio100"; 4337 function = "mi2s0_ws"; 4338 }; 4339 4340 mi2s1_data0: mi2s1-data0-state { 4341 pins = "gpio107"; 4342 function = "mi2s1_data0"; 4343 }; 4344 4345 mi2s1_sclk: mi2s1-sclk-state { 4346 pins = "gpio106"; 4347 function = "mi2s1_sck"; 4348 }; 4349 4350 mi2s1_ws: mi2s1-ws-state { 4351 pins = "gpio108"; 4352 function = "mi2s1_ws"; 4353 }; 4354 4355 pcie1_clkreq_n: pcie1-clkreq-n-state { 4356 pins = "gpio79"; 4357 function = "pcie1_clkreqn"; 4358 }; 4359 4360 qspi_clk: qspi-clk-state { 4361 pins = "gpio14"; 4362 function = "qspi_clk"; 4363 }; 4364 4365 qspi_cs0: qspi-cs0-state { 4366 pins = "gpio15"; 4367 function = "qspi_cs"; 4368 }; 4369 4370 qspi_cs1: qspi-cs1-state { 4371 pins = "gpio19"; 4372 function = "qspi_cs"; 4373 }; 4374 4375 qspi_data01: qspi-data01-state { 4376 pins = "gpio12", "gpio13"; 4377 function = "qspi_data"; 4378 }; 4379 4380 qspi_data12: qspi-data12-state { 4381 pins = "gpio16", "gpio17"; 4382 function = "qspi_data"; 4383 }; 4384 4385 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4386 pins = "gpio0", "gpio1"; 4387 function = "qup00"; 4388 }; 4389 4390 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4391 pins = "gpio4", "gpio5"; 4392 function = "qup01"; 4393 }; 4394 4395 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4396 pins = "gpio8", "gpio9"; 4397 function = "qup02"; 4398 }; 4399 4400 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4401 pins = "gpio12", "gpio13"; 4402 function = "qup03"; 4403 }; 4404 4405 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4406 pins = "gpio16", "gpio17"; 4407 function = "qup04"; 4408 }; 4409 4410 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4411 pins = "gpio20", "gpio21"; 4412 function = "qup05"; 4413 }; 4414 4415 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4416 pins = "gpio24", "gpio25"; 4417 function = "qup06"; 4418 }; 4419 4420 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4421 pins = "gpio28", "gpio29"; 4422 function = "qup07"; 4423 }; 4424 4425 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4426 pins = "gpio32", "gpio33"; 4427 function = "qup10"; 4428 }; 4429 4430 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4431 pins = "gpio36", "gpio37"; 4432 function = "qup11"; 4433 }; 4434 4435 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4436 pins = "gpio40", "gpio41"; 4437 function = "qup12"; 4438 }; 4439 4440 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4441 pins = "gpio44", "gpio45"; 4442 function = "qup13"; 4443 }; 4444 4445 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4446 pins = "gpio48", "gpio49"; 4447 function = "qup14"; 4448 }; 4449 4450 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4451 pins = "gpio52", "gpio53"; 4452 function = "qup15"; 4453 }; 4454 4455 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4456 pins = "gpio56", "gpio57"; 4457 function = "qup16"; 4458 }; 4459 4460 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4461 pins = "gpio60", "gpio61"; 4462 function = "qup17"; 4463 }; 4464 4465 qup_spi0_data_clk: qup-spi0-data-clk-state { 4466 pins = "gpio0", "gpio1", "gpio2"; 4467 function = "qup00"; 4468 }; 4469 4470 qup_spi0_cs: qup-spi0-cs-state { 4471 pins = "gpio3"; 4472 function = "qup00"; 4473 }; 4474 4475 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4476 pins = "gpio3"; 4477 function = "gpio"; 4478 }; 4479 4480 qup_spi1_data_clk: qup-spi1-data-clk-state { 4481 pins = "gpio4", "gpio5", "gpio6"; 4482 function = "qup01"; 4483 }; 4484 4485 qup_spi1_cs: qup-spi1-cs-state { 4486 pins = "gpio7"; 4487 function = "qup01"; 4488 }; 4489 4490 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4491 pins = "gpio7"; 4492 function = "gpio"; 4493 }; 4494 4495 qup_spi2_data_clk: qup-spi2-data-clk-state { 4496 pins = "gpio8", "gpio9", "gpio10"; 4497 function = "qup02"; 4498 }; 4499 4500 qup_spi2_cs: qup-spi2-cs-state { 4501 pins = "gpio11"; 4502 function = "qup02"; 4503 }; 4504 4505 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4506 pins = "gpio11"; 4507 function = "gpio"; 4508 }; 4509 4510 qup_spi3_data_clk: qup-spi3-data-clk-state { 4511 pins = "gpio12", "gpio13", "gpio14"; 4512 function = "qup03"; 4513 }; 4514 4515 qup_spi3_cs: qup-spi3-cs-state { 4516 pins = "gpio15"; 4517 function = "qup03"; 4518 }; 4519 4520 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4521 pins = "gpio15"; 4522 function = "gpio"; 4523 }; 4524 4525 qup_spi4_data_clk: qup-spi4-data-clk-state { 4526 pins = "gpio16", "gpio17", "gpio18"; 4527 function = "qup04"; 4528 }; 4529 4530 qup_spi4_cs: qup-spi4-cs-state { 4531 pins = "gpio19"; 4532 function = "qup04"; 4533 }; 4534 4535 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4536 pins = "gpio19"; 4537 function = "gpio"; 4538 }; 4539 4540 qup_spi5_data_clk: qup-spi5-data-clk-state { 4541 pins = "gpio20", "gpio21", "gpio22"; 4542 function = "qup05"; 4543 }; 4544 4545 qup_spi5_cs: qup-spi5-cs-state { 4546 pins = "gpio23"; 4547 function = "qup05"; 4548 }; 4549 4550 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4551 pins = "gpio23"; 4552 function = "gpio"; 4553 }; 4554 4555 qup_spi6_data_clk: qup-spi6-data-clk-state { 4556 pins = "gpio24", "gpio25", "gpio26"; 4557 function = "qup06"; 4558 }; 4559 4560 qup_spi6_cs: qup-spi6-cs-state { 4561 pins = "gpio27"; 4562 function = "qup06"; 4563 }; 4564 4565 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4566 pins = "gpio27"; 4567 function = "gpio"; 4568 }; 4569 4570 qup_spi7_data_clk: qup-spi7-data-clk-state { 4571 pins = "gpio28", "gpio29", "gpio30"; 4572 function = "qup07"; 4573 }; 4574 4575 qup_spi7_cs: qup-spi7-cs-state { 4576 pins = "gpio31"; 4577 function = "qup07"; 4578 }; 4579 4580 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4581 pins = "gpio31"; 4582 function = "gpio"; 4583 }; 4584 4585 qup_spi8_data_clk: qup-spi8-data-clk-state { 4586 pins = "gpio32", "gpio33", "gpio34"; 4587 function = "qup10"; 4588 }; 4589 4590 qup_spi8_cs: qup-spi8-cs-state { 4591 pins = "gpio35"; 4592 function = "qup10"; 4593 }; 4594 4595 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4596 pins = "gpio35"; 4597 function = "gpio"; 4598 }; 4599 4600 qup_spi9_data_clk: qup-spi9-data-clk-state { 4601 pins = "gpio36", "gpio37", "gpio38"; 4602 function = "qup11"; 4603 }; 4604 4605 qup_spi9_cs: qup-spi9-cs-state { 4606 pins = "gpio39"; 4607 function = "qup11"; 4608 }; 4609 4610 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4611 pins = "gpio39"; 4612 function = "gpio"; 4613 }; 4614 4615 qup_spi10_data_clk: qup-spi10-data-clk-state { 4616 pins = "gpio40", "gpio41", "gpio42"; 4617 function = "qup12"; 4618 }; 4619 4620 qup_spi10_cs: qup-spi10-cs-state { 4621 pins = "gpio43"; 4622 function = "qup12"; 4623 }; 4624 4625 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4626 pins = "gpio43"; 4627 function = "gpio"; 4628 }; 4629 4630 qup_spi11_data_clk: qup-spi11-data-clk-state { 4631 pins = "gpio44", "gpio45", "gpio46"; 4632 function = "qup13"; 4633 }; 4634 4635 qup_spi11_cs: qup-spi11-cs-state { 4636 pins = "gpio47"; 4637 function = "qup13"; 4638 }; 4639 4640 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4641 pins = "gpio47"; 4642 function = "gpio"; 4643 }; 4644 4645 qup_spi12_data_clk: qup-spi12-data-clk-state { 4646 pins = "gpio48", "gpio49", "gpio50"; 4647 function = "qup14"; 4648 }; 4649 4650 qup_spi12_cs: qup-spi12-cs-state { 4651 pins = "gpio51"; 4652 function = "qup14"; 4653 }; 4654 4655 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4656 pins = "gpio51"; 4657 function = "gpio"; 4658 }; 4659 4660 qup_spi13_data_clk: qup-spi13-data-clk-state { 4661 pins = "gpio52", "gpio53", "gpio54"; 4662 function = "qup15"; 4663 }; 4664 4665 qup_spi13_cs: qup-spi13-cs-state { 4666 pins = "gpio55"; 4667 function = "qup15"; 4668 }; 4669 4670 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4671 pins = "gpio55"; 4672 function = "gpio"; 4673 }; 4674 4675 qup_spi14_data_clk: qup-spi14-data-clk-state { 4676 pins = "gpio56", "gpio57", "gpio58"; 4677 function = "qup16"; 4678 }; 4679 4680 qup_spi14_cs: qup-spi14-cs-state { 4681 pins = "gpio59"; 4682 function = "qup16"; 4683 }; 4684 4685 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4686 pins = "gpio59"; 4687 function = "gpio"; 4688 }; 4689 4690 qup_spi15_data_clk: qup-spi15-data-clk-state { 4691 pins = "gpio60", "gpio61", "gpio62"; 4692 function = "qup17"; 4693 }; 4694 4695 qup_spi15_cs: qup-spi15-cs-state { 4696 pins = "gpio63"; 4697 function = "qup17"; 4698 }; 4699 4700 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4701 pins = "gpio63"; 4702 function = "gpio"; 4703 }; 4704 4705 qup_uart0_cts: qup-uart0-cts-state { 4706 pins = "gpio0"; 4707 function = "qup00"; 4708 }; 4709 4710 qup_uart0_rts: qup-uart0-rts-state { 4711 pins = "gpio1"; 4712 function = "qup00"; 4713 }; 4714 4715 qup_uart0_tx: qup-uart0-tx-state { 4716 pins = "gpio2"; 4717 function = "qup00"; 4718 }; 4719 4720 qup_uart0_rx: qup-uart0-rx-state { 4721 pins = "gpio3"; 4722 function = "qup00"; 4723 }; 4724 4725 qup_uart1_cts: qup-uart1-cts-state { 4726 pins = "gpio4"; 4727 function = "qup01"; 4728 }; 4729 4730 qup_uart1_rts: qup-uart1-rts-state { 4731 pins = "gpio5"; 4732 function = "qup01"; 4733 }; 4734 4735 qup_uart1_tx: qup-uart1-tx-state { 4736 pins = "gpio6"; 4737 function = "qup01"; 4738 }; 4739 4740 qup_uart1_rx: qup-uart1-rx-state { 4741 pins = "gpio7"; 4742 function = "qup01"; 4743 }; 4744 4745 qup_uart2_cts: qup-uart2-cts-state { 4746 pins = "gpio8"; 4747 function = "qup02"; 4748 }; 4749 4750 qup_uart2_rts: qup-uart2-rts-state { 4751 pins = "gpio9"; 4752 function = "qup02"; 4753 }; 4754 4755 qup_uart2_tx: qup-uart2-tx-state { 4756 pins = "gpio10"; 4757 function = "qup02"; 4758 }; 4759 4760 qup_uart2_rx: qup-uart2-rx-state { 4761 pins = "gpio11"; 4762 function = "qup02"; 4763 }; 4764 4765 qup_uart3_cts: qup-uart3-cts-state { 4766 pins = "gpio12"; 4767 function = "qup03"; 4768 }; 4769 4770 qup_uart3_rts: qup-uart3-rts-state { 4771 pins = "gpio13"; 4772 function = "qup03"; 4773 }; 4774 4775 qup_uart3_tx: qup-uart3-tx-state { 4776 pins = "gpio14"; 4777 function = "qup03"; 4778 }; 4779 4780 qup_uart3_rx: qup-uart3-rx-state { 4781 pins = "gpio15"; 4782 function = "qup03"; 4783 }; 4784 4785 qup_uart4_cts: qup-uart4-cts-state { 4786 pins = "gpio16"; 4787 function = "qup04"; 4788 }; 4789 4790 qup_uart4_rts: qup-uart4-rts-state { 4791 pins = "gpio17"; 4792 function = "qup04"; 4793 }; 4794 4795 qup_uart4_tx: qup-uart4-tx-state { 4796 pins = "gpio18"; 4797 function = "qup04"; 4798 }; 4799 4800 qup_uart4_rx: qup-uart4-rx-state { 4801 pins = "gpio19"; 4802 function = "qup04"; 4803 }; 4804 4805 qup_uart5_cts: qup-uart5-cts-state { 4806 pins = "gpio20"; 4807 function = "qup05"; 4808 }; 4809 4810 qup_uart5_rts: qup-uart5-rts-state { 4811 pins = "gpio21"; 4812 function = "qup05"; 4813 }; 4814 4815 qup_uart5_tx: qup-uart5-tx-state { 4816 pins = "gpio22"; 4817 function = "qup05"; 4818 }; 4819 4820 qup_uart5_rx: qup-uart5-rx-state { 4821 pins = "gpio23"; 4822 function = "qup05"; 4823 }; 4824 4825 qup_uart6_cts: qup-uart6-cts-state { 4826 pins = "gpio24"; 4827 function = "qup06"; 4828 }; 4829 4830 qup_uart6_rts: qup-uart6-rts-state { 4831 pins = "gpio25"; 4832 function = "qup06"; 4833 }; 4834 4835 qup_uart6_tx: qup-uart6-tx-state { 4836 pins = "gpio26"; 4837 function = "qup06"; 4838 }; 4839 4840 qup_uart6_rx: qup-uart6-rx-state { 4841 pins = "gpio27"; 4842 function = "qup06"; 4843 }; 4844 4845 qup_uart7_cts: qup-uart7-cts-state { 4846 pins = "gpio28"; 4847 function = "qup07"; 4848 }; 4849 4850 qup_uart7_rts: qup-uart7-rts-state { 4851 pins = "gpio29"; 4852 function = "qup07"; 4853 }; 4854 4855 qup_uart7_tx: qup-uart7-tx-state { 4856 pins = "gpio30"; 4857 function = "qup07"; 4858 }; 4859 4860 qup_uart7_rx: qup-uart7-rx-state { 4861 pins = "gpio31"; 4862 function = "qup07"; 4863 }; 4864 4865 qup_uart8_cts: qup-uart8-cts-state { 4866 pins = "gpio32"; 4867 function = "qup10"; 4868 }; 4869 4870 qup_uart8_rts: qup-uart8-rts-state { 4871 pins = "gpio33"; 4872 function = "qup10"; 4873 }; 4874 4875 qup_uart8_tx: qup-uart8-tx-state { 4876 pins = "gpio34"; 4877 function = "qup10"; 4878 }; 4879 4880 qup_uart8_rx: qup-uart8-rx-state { 4881 pins = "gpio35"; 4882 function = "qup10"; 4883 }; 4884 4885 qup_uart9_cts: qup-uart9-cts-state { 4886 pins = "gpio36"; 4887 function = "qup11"; 4888 }; 4889 4890 qup_uart9_rts: qup-uart9-rts-state { 4891 pins = "gpio37"; 4892 function = "qup11"; 4893 }; 4894 4895 qup_uart9_tx: qup-uart9-tx-state { 4896 pins = "gpio38"; 4897 function = "qup11"; 4898 }; 4899 4900 qup_uart9_rx: qup-uart9-rx-state { 4901 pins = "gpio39"; 4902 function = "qup11"; 4903 }; 4904 4905 qup_uart10_cts: qup-uart10-cts-state { 4906 pins = "gpio40"; 4907 function = "qup12"; 4908 }; 4909 4910 qup_uart10_rts: qup-uart10-rts-state { 4911 pins = "gpio41"; 4912 function = "qup12"; 4913 }; 4914 4915 qup_uart10_tx: qup-uart10-tx-state { 4916 pins = "gpio42"; 4917 function = "qup12"; 4918 }; 4919 4920 qup_uart10_rx: qup-uart10-rx-state { 4921 pins = "gpio43"; 4922 function = "qup12"; 4923 }; 4924 4925 qup_uart11_cts: qup-uart11-cts-state { 4926 pins = "gpio44"; 4927 function = "qup13"; 4928 }; 4929 4930 qup_uart11_rts: qup-uart11-rts-state { 4931 pins = "gpio45"; 4932 function = "qup13"; 4933 }; 4934 4935 qup_uart11_tx: qup-uart11-tx-state { 4936 pins = "gpio46"; 4937 function = "qup13"; 4938 }; 4939 4940 qup_uart11_rx: qup-uart11-rx-state { 4941 pins = "gpio47"; 4942 function = "qup13"; 4943 }; 4944 4945 qup_uart12_cts: qup-uart12-cts-state { 4946 pins = "gpio48"; 4947 function = "qup14"; 4948 }; 4949 4950 qup_uart12_rts: qup-uart12-rts-state { 4951 pins = "gpio49"; 4952 function = "qup14"; 4953 }; 4954 4955 qup_uart12_tx: qup-uart12-tx-state { 4956 pins = "gpio50"; 4957 function = "qup14"; 4958 }; 4959 4960 qup_uart12_rx: qup-uart12-rx-state { 4961 pins = "gpio51"; 4962 function = "qup14"; 4963 }; 4964 4965 qup_uart13_cts: qup-uart13-cts-state { 4966 pins = "gpio52"; 4967 function = "qup15"; 4968 }; 4969 4970 qup_uart13_rts: qup-uart13-rts-state { 4971 pins = "gpio53"; 4972 function = "qup15"; 4973 }; 4974 4975 qup_uart13_tx: qup-uart13-tx-state { 4976 pins = "gpio54"; 4977 function = "qup15"; 4978 }; 4979 4980 qup_uart13_rx: qup-uart13-rx-state { 4981 pins = "gpio55"; 4982 function = "qup15"; 4983 }; 4984 4985 qup_uart14_cts: qup-uart14-cts-state { 4986 pins = "gpio56"; 4987 function = "qup16"; 4988 }; 4989 4990 qup_uart14_rts: qup-uart14-rts-state { 4991 pins = "gpio57"; 4992 function = "qup16"; 4993 }; 4994 4995 qup_uart14_tx: qup-uart14-tx-state { 4996 pins = "gpio58"; 4997 function = "qup16"; 4998 }; 4999 5000 qup_uart14_rx: qup-uart14-rx-state { 5001 pins = "gpio59"; 5002 function = "qup16"; 5003 }; 5004 5005 qup_uart15_cts: qup-uart15-cts-state { 5006 pins = "gpio60"; 5007 function = "qup17"; 5008 }; 5009 5010 qup_uart15_rts: qup-uart15-rts-state { 5011 pins = "gpio61"; 5012 function = "qup17"; 5013 }; 5014 5015 qup_uart15_tx: qup-uart15-tx-state { 5016 pins = "gpio62"; 5017 function = "qup17"; 5018 }; 5019 5020 qup_uart15_rx: qup-uart15-rx-state { 5021 pins = "gpio63"; 5022 function = "qup17"; 5023 }; 5024 5025 sdc1_clk: sdc1-clk-state { 5026 pins = "sdc1_clk"; 5027 }; 5028 5029 sdc1_cmd: sdc1-cmd-state { 5030 pins = "sdc1_cmd"; 5031 }; 5032 5033 sdc1_data: sdc1-data-state { 5034 pins = "sdc1_data"; 5035 }; 5036 5037 sdc1_rclk: sdc1-rclk-state { 5038 pins = "sdc1_rclk"; 5039 }; 5040 5041 sdc1_clk_sleep: sdc1-clk-sleep-state { 5042 pins = "sdc1_clk"; 5043 drive-strength = <2>; 5044 bias-bus-hold; 5045 }; 5046 5047 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5048 pins = "sdc1_cmd"; 5049 drive-strength = <2>; 5050 bias-bus-hold; 5051 }; 5052 5053 sdc1_data_sleep: sdc1-data-sleep-state { 5054 pins = "sdc1_data"; 5055 drive-strength = <2>; 5056 bias-bus-hold; 5057 }; 5058 5059 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5060 pins = "sdc1_rclk"; 5061 drive-strength = <2>; 5062 bias-bus-hold; 5063 }; 5064 5065 sdc2_clk: sdc2-clk-state { 5066 pins = "sdc2_clk"; 5067 }; 5068 5069 sdc2_cmd: sdc2-cmd-state { 5070 pins = "sdc2_cmd"; 5071 }; 5072 5073 sdc2_data: sdc2-data-state { 5074 pins = "sdc2_data"; 5075 }; 5076 5077 sdc2_clk_sleep: sdc2-clk-sleep-state { 5078 pins = "sdc2_clk"; 5079 drive-strength = <2>; 5080 bias-bus-hold; 5081 }; 5082 5083 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5084 pins = "sdc2_cmd"; 5085 drive-strength = <2>; 5086 bias-bus-hold; 5087 }; 5088 5089 sdc2_data_sleep: sdc2-data-sleep-state { 5090 pins = "sdc2_data"; 5091 drive-strength = <2>; 5092 bias-bus-hold; 5093 }; 5094 }; 5095 5096 sram@146a5000 { 5097 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5098 reg = <0 0x146a5000 0 0x6000>; 5099 5100 #address-cells = <1>; 5101 #size-cells = <1>; 5102 5103 ranges = <0 0 0x146a5000 0x6000>; 5104 5105 pil-reloc@594c { 5106 compatible = "qcom,pil-reloc-info"; 5107 reg = <0x594c 0xc8>; 5108 }; 5109 }; 5110 5111 apps_smmu: iommu@15000000 { 5112 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5113 reg = <0 0x15000000 0 0x100000>; 5114 #iommu-cells = <2>; 5115 #global-interrupts = <1>; 5116 dma-coherent; 5117 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5196 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5197 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5198 }; 5199 5200 intc: interrupt-controller@17a00000 { 5201 compatible = "arm,gic-v3"; 5202 #address-cells = <2>; 5203 #size-cells = <2>; 5204 ranges; 5205 #interrupt-cells = <3>; 5206 interrupt-controller; 5207 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5208 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5209 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5210 5211 gic-its@17a40000 { 5212 compatible = "arm,gic-v3-its"; 5213 msi-controller; 5214 #msi-cells = <1>; 5215 reg = <0 0x17a40000 0 0x20000>; 5216 status = "disabled"; 5217 }; 5218 }; 5219 5220 watchdog@17c10000 { 5221 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5222 reg = <0 0x17c10000 0 0x1000>; 5223 clocks = <&sleep_clk>; 5224 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5225 }; 5226 5227 timer@17c20000 { 5228 #address-cells = <1>; 5229 #size-cells = <1>; 5230 ranges = <0 0 0 0x20000000>; 5231 compatible = "arm,armv7-timer-mem"; 5232 reg = <0 0x17c20000 0 0x1000>; 5233 5234 frame@17c21000 { 5235 frame-number = <0>; 5236 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5237 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5238 reg = <0x17c21000 0x1000>, 5239 <0x17c22000 0x1000>; 5240 }; 5241 5242 frame@17c23000 { 5243 frame-number = <1>; 5244 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5245 reg = <0x17c23000 0x1000>; 5246 status = "disabled"; 5247 }; 5248 5249 frame@17c25000 { 5250 frame-number = <2>; 5251 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5252 reg = <0x17c25000 0x1000>; 5253 status = "disabled"; 5254 }; 5255 5256 frame@17c27000 { 5257 frame-number = <3>; 5258 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5259 reg = <0x17c27000 0x1000>; 5260 status = "disabled"; 5261 }; 5262 5263 frame@17c29000 { 5264 frame-number = <4>; 5265 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5266 reg = <0x17c29000 0x1000>; 5267 status = "disabled"; 5268 }; 5269 5270 frame@17c2b000 { 5271 frame-number = <5>; 5272 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5273 reg = <0x17c2b000 0x1000>; 5274 status = "disabled"; 5275 }; 5276 5277 frame@17c2d000 { 5278 frame-number = <6>; 5279 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5280 reg = <0x17c2d000 0x1000>; 5281 status = "disabled"; 5282 }; 5283 }; 5284 5285 apps_rsc: rsc@18200000 { 5286 compatible = "qcom,rpmh-rsc"; 5287 reg = <0 0x18200000 0 0x10000>, 5288 <0 0x18210000 0 0x10000>, 5289 <0 0x18220000 0 0x10000>; 5290 reg-names = "drv-0", "drv-1", "drv-2"; 5291 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5292 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5293 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5294 qcom,tcs-offset = <0xd00>; 5295 qcom,drv-id = <2>; 5296 qcom,tcs-config = <ACTIVE_TCS 2>, 5297 <SLEEP_TCS 3>, 5298 <WAKE_TCS 3>, 5299 <CONTROL_TCS 1>; 5300 5301 apps_bcm_voter: bcm-voter { 5302 compatible = "qcom,bcm-voter"; 5303 }; 5304 5305 rpmhpd: power-controller { 5306 compatible = "qcom,sc7280-rpmhpd"; 5307 #power-domain-cells = <1>; 5308 operating-points-v2 = <&rpmhpd_opp_table>; 5309 5310 rpmhpd_opp_table: opp-table { 5311 compatible = "operating-points-v2"; 5312 5313 rpmhpd_opp_ret: opp1 { 5314 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5315 }; 5316 5317 rpmhpd_opp_low_svs: opp2 { 5318 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5319 }; 5320 5321 rpmhpd_opp_svs: opp3 { 5322 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5323 }; 5324 5325 rpmhpd_opp_svs_l1: opp4 { 5326 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5327 }; 5328 5329 rpmhpd_opp_svs_l2: opp5 { 5330 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5331 }; 5332 5333 rpmhpd_opp_nom: opp6 { 5334 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5335 }; 5336 5337 rpmhpd_opp_nom_l1: opp7 { 5338 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5339 }; 5340 5341 rpmhpd_opp_turbo: opp8 { 5342 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5343 }; 5344 5345 rpmhpd_opp_turbo_l1: opp9 { 5346 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5347 }; 5348 }; 5349 }; 5350 5351 rpmhcc: clock-controller { 5352 compatible = "qcom,sc7280-rpmh-clk"; 5353 clocks = <&xo_board>; 5354 clock-names = "xo"; 5355 #clock-cells = <1>; 5356 }; 5357 }; 5358 5359 epss_l3: interconnect@18590000 { 5360 compatible = "qcom,sc7280-epss-l3"; 5361 reg = <0 0x18590000 0 0x1000>; 5362 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5363 clock-names = "xo", "alternate"; 5364 #interconnect-cells = <1>; 5365 }; 5366 5367 cpufreq_hw: cpufreq@18591000 { 5368 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5369 reg = <0 0x18591000 0 0x1000>, 5370 <0 0x18592000 0 0x1000>, 5371 <0 0x18593000 0 0x1000>; 5372 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5373 clock-names = "xo", "alternate"; 5374 #freq-domain-cells = <1>; 5375 }; 5376 }; 5377 5378 thermal_zones: thermal-zones { 5379 cpu0-thermal { 5380 polling-delay-passive = <250>; 5381 polling-delay = <0>; 5382 5383 thermal-sensors = <&tsens0 1>; 5384 5385 trips { 5386 cpu0_alert0: trip-point0 { 5387 temperature = <90000>; 5388 hysteresis = <2000>; 5389 type = "passive"; 5390 }; 5391 5392 cpu0_alert1: trip-point1 { 5393 temperature = <95000>; 5394 hysteresis = <2000>; 5395 type = "passive"; 5396 }; 5397 5398 cpu0_crit: cpu-crit { 5399 temperature = <110000>; 5400 hysteresis = <0>; 5401 type = "critical"; 5402 }; 5403 }; 5404 5405 cooling-maps { 5406 map0 { 5407 trip = <&cpu0_alert0>; 5408 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5409 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5412 }; 5413 map1 { 5414 trip = <&cpu0_alert1>; 5415 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5416 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5417 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5418 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5419 }; 5420 }; 5421 }; 5422 5423 cpu1-thermal { 5424 polling-delay-passive = <250>; 5425 polling-delay = <0>; 5426 5427 thermal-sensors = <&tsens0 2>; 5428 5429 trips { 5430 cpu1_alert0: trip-point0 { 5431 temperature = <90000>; 5432 hysteresis = <2000>; 5433 type = "passive"; 5434 }; 5435 5436 cpu1_alert1: trip-point1 { 5437 temperature = <95000>; 5438 hysteresis = <2000>; 5439 type = "passive"; 5440 }; 5441 5442 cpu1_crit: cpu-crit { 5443 temperature = <110000>; 5444 hysteresis = <0>; 5445 type = "critical"; 5446 }; 5447 }; 5448 5449 cooling-maps { 5450 map0 { 5451 trip = <&cpu1_alert0>; 5452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5456 }; 5457 map1 { 5458 trip = <&cpu1_alert1>; 5459 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5460 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5461 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5462 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5463 }; 5464 }; 5465 }; 5466 5467 cpu2-thermal { 5468 polling-delay-passive = <250>; 5469 polling-delay = <0>; 5470 5471 thermal-sensors = <&tsens0 3>; 5472 5473 trips { 5474 cpu2_alert0: trip-point0 { 5475 temperature = <90000>; 5476 hysteresis = <2000>; 5477 type = "passive"; 5478 }; 5479 5480 cpu2_alert1: trip-point1 { 5481 temperature = <95000>; 5482 hysteresis = <2000>; 5483 type = "passive"; 5484 }; 5485 5486 cpu2_crit: cpu-crit { 5487 temperature = <110000>; 5488 hysteresis = <0>; 5489 type = "critical"; 5490 }; 5491 }; 5492 5493 cooling-maps { 5494 map0 { 5495 trip = <&cpu2_alert0>; 5496 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5497 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5500 }; 5501 map1 { 5502 trip = <&cpu2_alert1>; 5503 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5504 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5505 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5506 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5507 }; 5508 }; 5509 }; 5510 5511 cpu3-thermal { 5512 polling-delay-passive = <250>; 5513 polling-delay = <0>; 5514 5515 thermal-sensors = <&tsens0 4>; 5516 5517 trips { 5518 cpu3_alert0: trip-point0 { 5519 temperature = <90000>; 5520 hysteresis = <2000>; 5521 type = "passive"; 5522 }; 5523 5524 cpu3_alert1: trip-point1 { 5525 temperature = <95000>; 5526 hysteresis = <2000>; 5527 type = "passive"; 5528 }; 5529 5530 cpu3_crit: cpu-crit { 5531 temperature = <110000>; 5532 hysteresis = <0>; 5533 type = "critical"; 5534 }; 5535 }; 5536 5537 cooling-maps { 5538 map0 { 5539 trip = <&cpu3_alert0>; 5540 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5541 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5544 }; 5545 map1 { 5546 trip = <&cpu3_alert1>; 5547 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5548 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5549 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5550 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5551 }; 5552 }; 5553 }; 5554 5555 cpu4-thermal { 5556 polling-delay-passive = <250>; 5557 polling-delay = <0>; 5558 5559 thermal-sensors = <&tsens0 7>; 5560 5561 trips { 5562 cpu4_alert0: trip-point0 { 5563 temperature = <90000>; 5564 hysteresis = <2000>; 5565 type = "passive"; 5566 }; 5567 5568 cpu4_alert1: trip-point1 { 5569 temperature = <95000>; 5570 hysteresis = <2000>; 5571 type = "passive"; 5572 }; 5573 5574 cpu4_crit: cpu-crit { 5575 temperature = <110000>; 5576 hysteresis = <0>; 5577 type = "critical"; 5578 }; 5579 }; 5580 5581 cooling-maps { 5582 map0 { 5583 trip = <&cpu4_alert0>; 5584 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5585 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5588 }; 5589 map1 { 5590 trip = <&cpu4_alert1>; 5591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5595 }; 5596 }; 5597 }; 5598 5599 cpu5-thermal { 5600 polling-delay-passive = <250>; 5601 polling-delay = <0>; 5602 5603 thermal-sensors = <&tsens0 8>; 5604 5605 trips { 5606 cpu5_alert0: trip-point0 { 5607 temperature = <90000>; 5608 hysteresis = <2000>; 5609 type = "passive"; 5610 }; 5611 5612 cpu5_alert1: trip-point1 { 5613 temperature = <95000>; 5614 hysteresis = <2000>; 5615 type = "passive"; 5616 }; 5617 5618 cpu5_crit: cpu-crit { 5619 temperature = <110000>; 5620 hysteresis = <0>; 5621 type = "critical"; 5622 }; 5623 }; 5624 5625 cooling-maps { 5626 map0 { 5627 trip = <&cpu5_alert0>; 5628 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5629 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5632 }; 5633 map1 { 5634 trip = <&cpu5_alert1>; 5635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5639 }; 5640 }; 5641 }; 5642 5643 cpu6-thermal { 5644 polling-delay-passive = <250>; 5645 polling-delay = <0>; 5646 5647 thermal-sensors = <&tsens0 9>; 5648 5649 trips { 5650 cpu6_alert0: trip-point0 { 5651 temperature = <90000>; 5652 hysteresis = <2000>; 5653 type = "passive"; 5654 }; 5655 5656 cpu6_alert1: trip-point1 { 5657 temperature = <95000>; 5658 hysteresis = <2000>; 5659 type = "passive"; 5660 }; 5661 5662 cpu6_crit: cpu-crit { 5663 temperature = <110000>; 5664 hysteresis = <0>; 5665 type = "critical"; 5666 }; 5667 }; 5668 5669 cooling-maps { 5670 map0 { 5671 trip = <&cpu6_alert0>; 5672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5676 }; 5677 map1 { 5678 trip = <&cpu6_alert1>; 5679 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5680 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5681 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5682 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5683 }; 5684 }; 5685 }; 5686 5687 cpu7-thermal { 5688 polling-delay-passive = <250>; 5689 polling-delay = <0>; 5690 5691 thermal-sensors = <&tsens0 10>; 5692 5693 trips { 5694 cpu7_alert0: trip-point0 { 5695 temperature = <90000>; 5696 hysteresis = <2000>; 5697 type = "passive"; 5698 }; 5699 5700 cpu7_alert1: trip-point1 { 5701 temperature = <95000>; 5702 hysteresis = <2000>; 5703 type = "passive"; 5704 }; 5705 5706 cpu7_crit: cpu-crit { 5707 temperature = <110000>; 5708 hysteresis = <0>; 5709 type = "critical"; 5710 }; 5711 }; 5712 5713 cooling-maps { 5714 map0 { 5715 trip = <&cpu7_alert0>; 5716 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5720 }; 5721 map1 { 5722 trip = <&cpu7_alert1>; 5723 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5724 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5725 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5726 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5727 }; 5728 }; 5729 }; 5730 5731 cpu8-thermal { 5732 polling-delay-passive = <250>; 5733 polling-delay = <0>; 5734 5735 thermal-sensors = <&tsens0 11>; 5736 5737 trips { 5738 cpu8_alert0: trip-point0 { 5739 temperature = <90000>; 5740 hysteresis = <2000>; 5741 type = "passive"; 5742 }; 5743 5744 cpu8_alert1: trip-point1 { 5745 temperature = <95000>; 5746 hysteresis = <2000>; 5747 type = "passive"; 5748 }; 5749 5750 cpu8_crit: cpu-crit { 5751 temperature = <110000>; 5752 hysteresis = <0>; 5753 type = "critical"; 5754 }; 5755 }; 5756 5757 cooling-maps { 5758 map0 { 5759 trip = <&cpu8_alert0>; 5760 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5764 }; 5765 map1 { 5766 trip = <&cpu8_alert1>; 5767 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5768 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5769 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5770 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5771 }; 5772 }; 5773 }; 5774 5775 cpu9-thermal { 5776 polling-delay-passive = <250>; 5777 polling-delay = <0>; 5778 5779 thermal-sensors = <&tsens0 12>; 5780 5781 trips { 5782 cpu9_alert0: trip-point0 { 5783 temperature = <90000>; 5784 hysteresis = <2000>; 5785 type = "passive"; 5786 }; 5787 5788 cpu9_alert1: trip-point1 { 5789 temperature = <95000>; 5790 hysteresis = <2000>; 5791 type = "passive"; 5792 }; 5793 5794 cpu9_crit: cpu-crit { 5795 temperature = <110000>; 5796 hysteresis = <0>; 5797 type = "critical"; 5798 }; 5799 }; 5800 5801 cooling-maps { 5802 map0 { 5803 trip = <&cpu9_alert0>; 5804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5808 }; 5809 map1 { 5810 trip = <&cpu9_alert1>; 5811 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5812 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5813 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5815 }; 5816 }; 5817 }; 5818 5819 cpu10-thermal { 5820 polling-delay-passive = <250>; 5821 polling-delay = <0>; 5822 5823 thermal-sensors = <&tsens0 13>; 5824 5825 trips { 5826 cpu10_alert0: trip-point0 { 5827 temperature = <90000>; 5828 hysteresis = <2000>; 5829 type = "passive"; 5830 }; 5831 5832 cpu10_alert1: trip-point1 { 5833 temperature = <95000>; 5834 hysteresis = <2000>; 5835 type = "passive"; 5836 }; 5837 5838 cpu10_crit: cpu-crit { 5839 temperature = <110000>; 5840 hysteresis = <0>; 5841 type = "critical"; 5842 }; 5843 }; 5844 5845 cooling-maps { 5846 map0 { 5847 trip = <&cpu10_alert0>; 5848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5852 }; 5853 map1 { 5854 trip = <&cpu10_alert1>; 5855 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5857 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5858 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5859 }; 5860 }; 5861 }; 5862 5863 cpu11-thermal { 5864 polling-delay-passive = <250>; 5865 polling-delay = <0>; 5866 5867 thermal-sensors = <&tsens0 14>; 5868 5869 trips { 5870 cpu11_alert0: trip-point0 { 5871 temperature = <90000>; 5872 hysteresis = <2000>; 5873 type = "passive"; 5874 }; 5875 5876 cpu11_alert1: trip-point1 { 5877 temperature = <95000>; 5878 hysteresis = <2000>; 5879 type = "passive"; 5880 }; 5881 5882 cpu11_crit: cpu-crit { 5883 temperature = <110000>; 5884 hysteresis = <0>; 5885 type = "critical"; 5886 }; 5887 }; 5888 5889 cooling-maps { 5890 map0 { 5891 trip = <&cpu11_alert0>; 5892 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5893 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5894 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5895 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5896 }; 5897 map1 { 5898 trip = <&cpu11_alert1>; 5899 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5900 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5901 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5902 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5903 }; 5904 }; 5905 }; 5906 5907 aoss0-thermal { 5908 polling-delay-passive = <0>; 5909 polling-delay = <0>; 5910 5911 thermal-sensors = <&tsens0 0>; 5912 5913 trips { 5914 aoss0_alert0: trip-point0 { 5915 temperature = <90000>; 5916 hysteresis = <2000>; 5917 type = "hot"; 5918 }; 5919 5920 aoss0_crit: aoss0-crit { 5921 temperature = <110000>; 5922 hysteresis = <0>; 5923 type = "critical"; 5924 }; 5925 }; 5926 }; 5927 5928 aoss1-thermal { 5929 polling-delay-passive = <0>; 5930 polling-delay = <0>; 5931 5932 thermal-sensors = <&tsens1 0>; 5933 5934 trips { 5935 aoss1_alert0: trip-point0 { 5936 temperature = <90000>; 5937 hysteresis = <2000>; 5938 type = "hot"; 5939 }; 5940 5941 aoss1_crit: aoss1-crit { 5942 temperature = <110000>; 5943 hysteresis = <0>; 5944 type = "critical"; 5945 }; 5946 }; 5947 }; 5948 5949 cpuss0-thermal { 5950 polling-delay-passive = <0>; 5951 polling-delay = <0>; 5952 5953 thermal-sensors = <&tsens0 5>; 5954 5955 trips { 5956 cpuss0_alert0: trip-point0 { 5957 temperature = <90000>; 5958 hysteresis = <2000>; 5959 type = "hot"; 5960 }; 5961 cpuss0_crit: cluster0-crit { 5962 temperature = <110000>; 5963 hysteresis = <0>; 5964 type = "critical"; 5965 }; 5966 }; 5967 }; 5968 5969 cpuss1-thermal { 5970 polling-delay-passive = <0>; 5971 polling-delay = <0>; 5972 5973 thermal-sensors = <&tsens0 6>; 5974 5975 trips { 5976 cpuss1_alert0: trip-point0 { 5977 temperature = <90000>; 5978 hysteresis = <2000>; 5979 type = "hot"; 5980 }; 5981 cpuss1_crit: cluster0-crit { 5982 temperature = <110000>; 5983 hysteresis = <0>; 5984 type = "critical"; 5985 }; 5986 }; 5987 }; 5988 5989 gpuss0-thermal { 5990 polling-delay-passive = <100>; 5991 polling-delay = <0>; 5992 5993 thermal-sensors = <&tsens1 1>; 5994 5995 trips { 5996 gpuss0_alert0: trip-point0 { 5997 temperature = <95000>; 5998 hysteresis = <2000>; 5999 type = "passive"; 6000 }; 6001 6002 gpuss0_crit: gpuss0-crit { 6003 temperature = <110000>; 6004 hysteresis = <0>; 6005 type = "critical"; 6006 }; 6007 }; 6008 6009 cooling-maps { 6010 map0 { 6011 trip = <&gpuss0_alert0>; 6012 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6013 }; 6014 }; 6015 }; 6016 6017 gpuss1-thermal { 6018 polling-delay-passive = <100>; 6019 polling-delay = <0>; 6020 6021 thermal-sensors = <&tsens1 2>; 6022 6023 trips { 6024 gpuss1_alert0: trip-point0 { 6025 temperature = <95000>; 6026 hysteresis = <2000>; 6027 type = "passive"; 6028 }; 6029 6030 gpuss1_crit: gpuss1-crit { 6031 temperature = <110000>; 6032 hysteresis = <0>; 6033 type = "critical"; 6034 }; 6035 }; 6036 6037 cooling-maps { 6038 map0 { 6039 trip = <&gpuss1_alert0>; 6040 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6041 }; 6042 }; 6043 }; 6044 6045 nspss0-thermal { 6046 polling-delay-passive = <0>; 6047 polling-delay = <0>; 6048 6049 thermal-sensors = <&tsens1 3>; 6050 6051 trips { 6052 nspss0_alert0: trip-point0 { 6053 temperature = <90000>; 6054 hysteresis = <2000>; 6055 type = "hot"; 6056 }; 6057 6058 nspss0_crit: nspss0-crit { 6059 temperature = <110000>; 6060 hysteresis = <0>; 6061 type = "critical"; 6062 }; 6063 }; 6064 }; 6065 6066 nspss1-thermal { 6067 polling-delay-passive = <0>; 6068 polling-delay = <0>; 6069 6070 thermal-sensors = <&tsens1 4>; 6071 6072 trips { 6073 nspss1_alert0: trip-point0 { 6074 temperature = <90000>; 6075 hysteresis = <2000>; 6076 type = "hot"; 6077 }; 6078 6079 nspss1_crit: nspss1-crit { 6080 temperature = <110000>; 6081 hysteresis = <0>; 6082 type = "critical"; 6083 }; 6084 }; 6085 }; 6086 6087 video-thermal { 6088 polling-delay-passive = <0>; 6089 polling-delay = <0>; 6090 6091 thermal-sensors = <&tsens1 5>; 6092 6093 trips { 6094 video_alert0: trip-point0 { 6095 temperature = <90000>; 6096 hysteresis = <2000>; 6097 type = "hot"; 6098 }; 6099 6100 video_crit: video-crit { 6101 temperature = <110000>; 6102 hysteresis = <0>; 6103 type = "critical"; 6104 }; 6105 }; 6106 }; 6107 6108 ddr-thermal { 6109 polling-delay-passive = <0>; 6110 polling-delay = <0>; 6111 6112 thermal-sensors = <&tsens1 6>; 6113 6114 trips { 6115 ddr_alert0: trip-point0 { 6116 temperature = <90000>; 6117 hysteresis = <2000>; 6118 type = "hot"; 6119 }; 6120 6121 ddr_crit: ddr-crit { 6122 temperature = <110000>; 6123 hysteresis = <0>; 6124 type = "critical"; 6125 }; 6126 }; 6127 }; 6128 6129 mdmss0-thermal { 6130 polling-delay-passive = <0>; 6131 polling-delay = <0>; 6132 6133 thermal-sensors = <&tsens1 7>; 6134 6135 trips { 6136 mdmss0_alert0: trip-point0 { 6137 temperature = <90000>; 6138 hysteresis = <2000>; 6139 type = "hot"; 6140 }; 6141 6142 mdmss0_crit: mdmss0-crit { 6143 temperature = <110000>; 6144 hysteresis = <0>; 6145 type = "critical"; 6146 }; 6147 }; 6148 }; 6149 6150 mdmss1-thermal { 6151 polling-delay-passive = <0>; 6152 polling-delay = <0>; 6153 6154 thermal-sensors = <&tsens1 8>; 6155 6156 trips { 6157 mdmss1_alert0: trip-point0 { 6158 temperature = <90000>; 6159 hysteresis = <2000>; 6160 type = "hot"; 6161 }; 6162 6163 mdmss1_crit: mdmss1-crit { 6164 temperature = <110000>; 6165 hysteresis = <0>; 6166 type = "critical"; 6167 }; 6168 }; 6169 }; 6170 6171 mdmss2-thermal { 6172 polling-delay-passive = <0>; 6173 polling-delay = <0>; 6174 6175 thermal-sensors = <&tsens1 9>; 6176 6177 trips { 6178 mdmss2_alert0: trip-point0 { 6179 temperature = <90000>; 6180 hysteresis = <2000>; 6181 type = "hot"; 6182 }; 6183 6184 mdmss2_crit: mdmss2-crit { 6185 temperature = <110000>; 6186 hysteresis = <0>; 6187 type = "critical"; 6188 }; 6189 }; 6190 }; 6191 6192 mdmss3-thermal { 6193 polling-delay-passive = <0>; 6194 polling-delay = <0>; 6195 6196 thermal-sensors = <&tsens1 10>; 6197 6198 trips { 6199 mdmss3_alert0: trip-point0 { 6200 temperature = <90000>; 6201 hysteresis = <2000>; 6202 type = "hot"; 6203 }; 6204 6205 mdmss3_crit: mdmss3-crit { 6206 temperature = <110000>; 6207 hysteresis = <0>; 6208 type = "critical"; 6209 }; 6210 }; 6211 }; 6212 6213 camera0-thermal { 6214 polling-delay-passive = <0>; 6215 polling-delay = <0>; 6216 6217 thermal-sensors = <&tsens1 11>; 6218 6219 trips { 6220 camera0_alert0: trip-point0 { 6221 temperature = <90000>; 6222 hysteresis = <2000>; 6223 type = "hot"; 6224 }; 6225 6226 camera0_crit: camera0-crit { 6227 temperature = <110000>; 6228 hysteresis = <0>; 6229 type = "critical"; 6230 }; 6231 }; 6232 }; 6233 }; 6234 6235 timer { 6236 compatible = "arm,armv8-timer"; 6237 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6238 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6239 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6240 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6241 }; 6242}; 6243