1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 clock-frequency = <76800000>; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 aop_mem: memory@80800000 { 56 reg = <0x0 0x80800000 0x0 0x60000>; 57 no-map; 58 }; 59 60 aop_cmd_db_mem: memory@80860000 { 61 reg = <0x0 0x80860000 0x0 0x20000>; 62 compatible = "qcom,cmd-db"; 63 no-map; 64 }; 65 66 smem_mem: memory@80900000 { 67 reg = <0x0 0x80900000 0x0 0x200000>; 68 no-map; 69 }; 70 71 cpucp_mem: memory@80b00000 { 72 no-map; 73 reg = <0x0 0x80b00000 0x0 0x100000>; 74 }; 75 76 ipa_fw_mem: memory@8b700000 { 77 reg = <0 0x8b700000 0 0x10000>; 78 no-map; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <2>; 84 #size-cells = <0>; 85 86 CPU0: cpu@0 { 87 device_type = "cpu"; 88 compatible = "arm,kryo"; 89 reg = <0x0 0x0>; 90 enable-method = "psci"; 91 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 92 &LITTLE_CPU_SLEEP_1 93 &CLUSTER_SLEEP_0>; 94 next-level-cache = <&L2_0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 L2_0: l2-cache { 98 compatible = "cache"; 99 next-level-cache = <&L3_0>; 100 L3_0: l3-cache { 101 compatible = "cache"; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,kryo"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 next-level-cache = <&L2_100>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 #cooling-cells = <2>; 117 L2_100: l2-cache { 118 compatible = "cache"; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU2: cpu@200 { 124 device_type = "cpu"; 125 compatible = "arm,kryo"; 126 reg = <0x0 0x200>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 next-level-cache = <&L2_200>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_200: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,kryo"; 143 reg = <0x0 0x300>; 144 enable-method = "psci"; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 146 &LITTLE_CPU_SLEEP_1 147 &CLUSTER_SLEEP_0>; 148 next-level-cache = <&L2_300>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,kryo"; 160 reg = <0x0 0x400>; 161 enable-method = "psci"; 162 cpu-idle-states = <&BIG_CPU_SLEEP_0 163 &BIG_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 next-level-cache = <&L2_400>; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "arm,kryo"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 cpu-idle-states = <&BIG_CPU_SLEEP_0 180 &BIG_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,kryo"; 194 reg = <0x0 0x600>; 195 enable-method = "psci"; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 197 &BIG_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,kryo"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 cpu-idle-states = <&BIG_CPU_SLEEP_0 214 &BIG_CPU_SLEEP_1 215 &CLUSTER_SLEEP_0>; 216 next-level-cache = <&L2_700>; 217 qcom,freq-domain = <&cpufreq_hw 2>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-power-down"; 267 arm,psci-suspend-param = <0x40000003>; 268 entry-latency-us = <549>; 269 exit-latency-us = <901>; 270 min-residency-us = <1774>; 271 local-timer-stop; 272 }; 273 274 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "little-rail-power-down"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <702>; 279 exit-latency-us = <915>; 280 min-residency-us = <4001>; 281 local-timer-stop; 282 }; 283 284 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "big-power-down"; 287 arm,psci-suspend-param = <0x40000003>; 288 entry-latency-us = <523>; 289 exit-latency-us = <1244>; 290 min-residency-us = <2207>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "big-rail-power-down"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <526>; 299 exit-latency-us = <1854>; 300 min-residency-us = <5555>; 301 local-timer-stop; 302 }; 303 304 CLUSTER_SLEEP_0: cluster-sleep-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "cluster-power-down"; 307 arm,psci-suspend-param = <0x40003444>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9926>; 311 local-timer-stop; 312 }; 313 }; 314 }; 315 316 memory@80000000 { 317 device_type = "memory"; 318 /* We expect the bootloader to fill in the size */ 319 reg = <0 0x80000000 0 0>; 320 }; 321 322 firmware { 323 scm { 324 compatible = "qcom,scm-sc7280", "qcom,scm"; 325 }; 326 }; 327 328 clk_virt: interconnect { 329 compatible = "qcom,sc7280-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 smem { 335 compatible = "qcom,smem"; 336 memory-region = <&smem_mem>; 337 hwlocks = <&tcsr_mutex 3>; 338 }; 339 340 smp2p-adsp { 341 compatible = "qcom,smp2p"; 342 qcom,smem = <443>, <429>; 343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 344 IPCC_MPROC_SIGNAL_SMP2P 345 IRQ_TYPE_EDGE_RISING>; 346 mboxes = <&ipcc IPCC_CLIENT_LPASS 347 IPCC_MPROC_SIGNAL_SMP2P>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <2>; 351 352 adsp_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 #qcom,smem-state-cells = <1>; 355 }; 356 357 adsp_smp2p_in: slave-kernel { 358 qcom,entry-name = "slave-kernel"; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 }; 362 }; 363 364 smp2p-cdsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <94>, <432>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_CDSP 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <5>; 375 376 cdsp_smp2p_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 cdsp_smp2p_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-mpss { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <435>, <428>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_MPSS 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <1>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 modem_smp2p_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 411 ipa_smp2p_out: ipa-ap-to-modem { 412 qcom,entry-name = "ipa"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 ipa_smp2p_in: ipa-modem-to-ap { 417 qcom,entry-name = "ipa"; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 smp2p-wpss { 424 compatible = "qcom,smp2p"; 425 qcom,smem = <617>, <616>; 426 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 427 IPCC_MPROC_SIGNAL_SMP2P 428 IRQ_TYPE_EDGE_RISING>; 429 mboxes = <&ipcc IPCC_CLIENT_WPSS 430 IPCC_MPROC_SIGNAL_SMP2P>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <13>; 434 435 wpss_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 wpss_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 }; 446 447 pmu { 448 compatible = "arm,armv8-pmuv3"; 449 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 450 }; 451 452 psci { 453 compatible = "arm,psci-1.0"; 454 method = "smc"; 455 }; 456 457 qspi_opp_table: qspi-opp-table { 458 compatible = "operating-points-v2"; 459 460 opp-75000000 { 461 opp-hz = /bits/ 64 <75000000>; 462 required-opps = <&rpmhpd_opp_low_svs>; 463 }; 464 465 opp-150000000 { 466 opp-hz = /bits/ 64 <150000000>; 467 required-opps = <&rpmhpd_opp_svs>; 468 }; 469 470 opp-300000000 { 471 opp-hz = /bits/ 64 <300000000>; 472 required-opps = <&rpmhpd_opp_nom>; 473 }; 474 }; 475 476 soc: soc@0 { 477 #address-cells = <2>; 478 #size-cells = <2>; 479 ranges = <0 0 0 0 0x10 0>; 480 dma-ranges = <0 0 0 0 0x10 0>; 481 compatible = "simple-bus"; 482 483 gcc: clock-controller@100000 { 484 compatible = "qcom,gcc-sc7280"; 485 reg = <0 0x00100000 0 0x1f0000>; 486 clocks = <&rpmhcc RPMH_CXO_CLK>, 487 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 488 <0>, <0>, <0>, <0>, <0>, <0>; 489 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 490 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 491 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 492 "ufs_phy_tx_symbol_0_clk", 493 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 494 #clock-cells = <1>; 495 #reset-cells = <1>; 496 #power-domain-cells = <1>; 497 }; 498 499 ipcc: mailbox@408000 { 500 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 501 reg = <0 0x00408000 0 0x1000>; 502 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-controller; 504 #interrupt-cells = <3>; 505 #mbox-cells = <2>; 506 }; 507 508 qfprom: efuse@784000 { 509 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 510 reg = <0 0x00784000 0 0xa20>, 511 <0 0x00780000 0 0xa20>, 512 <0 0x00782000 0 0x120>, 513 <0 0x00786000 0 0x1fff>; 514 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 515 clock-names = "core"; 516 power-domains = <&rpmhpd SC7280_MX>; 517 #address-cells = <1>; 518 #size-cells = <1>; 519 }; 520 521 sdhc_1: sdhci@7c4000 { 522 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 523 status = "disabled"; 524 525 reg = <0 0x007c4000 0 0x1000>, 526 <0 0x007c5000 0 0x1000>; 527 reg-names = "hc", "cqhci"; 528 529 iommus = <&apps_smmu 0xc0 0x0>; 530 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 532 interrupt-names = "hc_irq", "pwr_irq"; 533 534 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 535 <&gcc GCC_SDCC1_AHB_CLK>, 536 <&rpmhcc RPMH_CXO_CLK>; 537 clock-names = "core", "iface", "xo"; 538 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 539 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 540 interconnect-names = "sdhc-ddr","cpu-sdhc"; 541 power-domains = <&rpmhpd SC7280_CX>; 542 operating-points-v2 = <&sdhc1_opp_table>; 543 544 bus-width = <8>; 545 supports-cqe; 546 547 qcom,dll-config = <0x0007642c>; 548 qcom,ddr-config = <0x80040868>; 549 550 mmc-ddr-1_8v; 551 mmc-hs200-1_8v; 552 mmc-hs400-1_8v; 553 mmc-hs400-enhanced-strobe; 554 555 sdhc1_opp_table: opp-table { 556 compatible = "operating-points-v2"; 557 558 opp-100000000 { 559 opp-hz = /bits/ 64 <100000000>; 560 required-opps = <&rpmhpd_opp_low_svs>; 561 opp-peak-kBps = <1800000 400000>; 562 opp-avg-kBps = <100000 0>; 563 }; 564 565 opp-384000000 { 566 opp-hz = /bits/ 64 <384000000>; 567 required-opps = <&rpmhpd_opp_nom>; 568 opp-peak-kBps = <5400000 1600000>; 569 opp-avg-kBps = <390000 0>; 570 }; 571 }; 572 573 }; 574 575 qupv3_id_0: geniqup@9c0000 { 576 compatible = "qcom,geni-se-qup"; 577 reg = <0 0x009c0000 0 0x2000>; 578 clock-names = "m-ahb", "s-ahb"; 579 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 580 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 581 #address-cells = <2>; 582 #size-cells = <2>; 583 ranges; 584 status = "disabled"; 585 586 uart5: serial@994000 { 587 compatible = "qcom,geni-debug-uart"; 588 reg = <0 0x00994000 0 0x4000>; 589 clock-names = "se"; 590 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&qup_uart5_default>; 593 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 594 status = "disabled"; 595 }; 596 }; 597 598 cnoc2: interconnect@1500000 { 599 reg = <0 0x01500000 0 0x1000>; 600 compatible = "qcom,sc7280-cnoc2"; 601 #interconnect-cells = <2>; 602 qcom,bcm-voters = <&apps_bcm_voter>; 603 }; 604 605 cnoc3: interconnect@1502000 { 606 reg = <0 0x01502000 0 0x1000>; 607 compatible = "qcom,sc7280-cnoc3"; 608 #interconnect-cells = <2>; 609 qcom,bcm-voters = <&apps_bcm_voter>; 610 }; 611 612 mc_virt: interconnect@1580000 { 613 reg = <0 0x01580000 0 0x4>; 614 compatible = "qcom,sc7280-mc-virt"; 615 #interconnect-cells = <2>; 616 qcom,bcm-voters = <&apps_bcm_voter>; 617 }; 618 619 system_noc: interconnect@1680000 { 620 reg = <0 0x01680000 0 0x15480>; 621 compatible = "qcom,sc7280-system-noc"; 622 #interconnect-cells = <2>; 623 qcom,bcm-voters = <&apps_bcm_voter>; 624 }; 625 626 aggre1_noc: interconnect@16e0000 { 627 compatible = "qcom,sc7280-aggre1-noc"; 628 reg = <0 0x016e0000 0 0x1c080>; 629 #interconnect-cells = <2>; 630 qcom,bcm-voters = <&apps_bcm_voter>; 631 }; 632 633 aggre2_noc: interconnect@1700000 { 634 reg = <0 0x01700000 0 0x2b080>; 635 compatible = "qcom,sc7280-aggre2-noc"; 636 #interconnect-cells = <2>; 637 qcom,bcm-voters = <&apps_bcm_voter>; 638 }; 639 640 mmss_noc: interconnect@1740000 { 641 reg = <0 0x01740000 0 0x1e080>; 642 compatible = "qcom,sc7280-mmss-noc"; 643 #interconnect-cells = <2>; 644 qcom,bcm-voters = <&apps_bcm_voter>; 645 }; 646 647 ipa: ipa@1e40000 { 648 compatible = "qcom,sc7280-ipa"; 649 650 iommus = <&apps_smmu 0x480 0x0>, 651 <&apps_smmu 0x482 0x0>; 652 reg = <0 0x1e40000 0 0x8000>, 653 <0 0x1e50000 0 0x4ad0>, 654 <0 0x1e04000 0 0x23000>; 655 reg-names = "ipa-reg", 656 "ipa-shared", 657 "gsi"; 658 659 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 660 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 661 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 662 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 663 interrupt-names = "ipa", 664 "gsi", 665 "ipa-clock-query", 666 "ipa-setup-ready"; 667 668 clocks = <&rpmhcc RPMH_IPA_CLK>; 669 clock-names = "core"; 670 671 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 672 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 673 interconnect-names = "memory", 674 "config"; 675 676 qcom,smem-states = <&ipa_smp2p_out 0>, 677 <&ipa_smp2p_out 1>; 678 qcom,smem-state-names = "ipa-clock-enabled-valid", 679 "ipa-clock-enabled"; 680 681 status = "disabled"; 682 }; 683 684 tcsr_mutex: hwlock@1f40000 { 685 compatible = "qcom,tcsr-mutex", "syscon"; 686 reg = <0 0x01f40000 0 0x40000>; 687 #hwlock-cells = <1>; 688 }; 689 690 lpasscc: lpasscc@3000000 { 691 compatible = "qcom,sc7280-lpasscc"; 692 reg = <0 0x03000000 0 0x40>, 693 <0 0x03c04000 0 0x4>, 694 <0 0x03389000 0 0x24>; 695 reg-names = "qdsp6ss", "top_cc", "cc"; 696 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 697 clock-names = "iface"; 698 #clock-cells = <1>; 699 }; 700 701 lpass_ag_noc: interconnect@3c40000 { 702 reg = <0 0x03c40000 0 0xf080>; 703 compatible = "qcom,sc7280-lpass-ag-noc"; 704 #interconnect-cells = <2>; 705 qcom,bcm-voters = <&apps_bcm_voter>; 706 }; 707 708 gpu: gpu@3d00000 { 709 compatible = "qcom,adreno-635.0", "qcom,adreno"; 710 #stream-id-cells = <16>; 711 reg = <0 0x03d00000 0 0x40000>, 712 <0 0x03d9e000 0 0x1000>, 713 <0 0x03d61000 0 0x800>; 714 reg-names = "kgsl_3d0_reg_memory", 715 "cx_mem", 716 "cx_dbgc"; 717 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 718 iommus = <&adreno_smmu 0 0x401>; 719 operating-points-v2 = <&gpu_opp_table>; 720 qcom,gmu = <&gmu>; 721 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 722 interconnect-names = "gfx-mem"; 723 #cooling-cells = <2>; 724 725 gpu_opp_table: opp-table { 726 compatible = "operating-points-v2"; 727 728 opp-315000000 { 729 opp-hz = /bits/ 64 <315000000>; 730 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 731 opp-peak-kBps = <1804000>; 732 }; 733 734 opp-450000000 { 735 opp-hz = /bits/ 64 <450000000>; 736 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 737 opp-peak-kBps = <4068000>; 738 }; 739 740 opp-550000000 { 741 opp-hz = /bits/ 64 <550000000>; 742 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 743 opp-peak-kBps = <6832000>; 744 }; 745 }; 746 }; 747 748 gmu: gmu@3d69000 { 749 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 750 reg = <0 0x03d6a000 0 0x34000>, 751 <0 0x3de0000 0 0x10000>, 752 <0 0x0b290000 0 0x10000>; 753 reg-names = "gmu", "rscc", "gmu_pdc"; 754 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "hfi", "gmu"; 757 clocks = <&gpucc 5>, 758 <&gpucc 8>, 759 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 760 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 761 <&gpucc 2>, 762 <&gpucc 15>, 763 <&gpucc 11>; 764 clock-names = "gmu", 765 "cxo", 766 "axi", 767 "memnoc", 768 "ahb", 769 "hub", 770 "smmu_vote"; 771 power-domains = <&gpucc 0>, 772 <&gpucc 1>; 773 power-domain-names = "cx", 774 "gx"; 775 iommus = <&adreno_smmu 5 0x400>; 776 operating-points-v2 = <&gmu_opp_table>; 777 778 gmu_opp_table: opp-table { 779 compatible = "operating-points-v2"; 780 781 opp-200000000 { 782 opp-hz = /bits/ 64 <200000000>; 783 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 784 }; 785 }; 786 }; 787 788 gpucc: clock-controller@3d90000 { 789 compatible = "qcom,sc7280-gpucc"; 790 reg = <0 0x03d90000 0 0x9000>; 791 clocks = <&rpmhcc RPMH_CXO_CLK>, 792 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 793 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 794 clock-names = "bi_tcxo", 795 "gcc_gpu_gpll0_clk_src", 796 "gcc_gpu_gpll0_div_clk_src"; 797 #clock-cells = <1>; 798 #reset-cells = <1>; 799 #power-domain-cells = <1>; 800 }; 801 802 adreno_smmu: iommu@3da0000 { 803 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 804 reg = <0 0x03da0000 0 0x20000>; 805 #iommu-cells = <2>; 806 #global-interrupts = <2>; 807 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 819 820 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 821 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 822 <&gpucc 2>, 823 <&gpucc 11>, 824 <&gpucc 5>, 825 <&gpucc 15>, 826 <&gpucc 13>; 827 clock-names = "gcc_gpu_memnoc_gfx_clk", 828 "gcc_gpu_snoc_dvm_gfx_clk", 829 "gpu_cc_ahb_clk", 830 "gpu_cc_hlos1_vote_gpu_smmu_clk", 831 "gpu_cc_cx_gmu_clk", 832 "gpu_cc_hub_cx_int_clk", 833 "gpu_cc_hub_aon_clk"; 834 835 power-domains = <&gpucc 0>; 836 }; 837 838 stm@6002000 { 839 compatible = "arm,coresight-stm", "arm,primecell"; 840 reg = <0 0x06002000 0 0x1000>, 841 <0 0x16280000 0 0x180000>; 842 reg-names = "stm-base", "stm-stimulus-base"; 843 844 clocks = <&aoss_qmp>; 845 clock-names = "apb_pclk"; 846 847 out-ports { 848 port { 849 stm_out: endpoint { 850 remote-endpoint = <&funnel0_in7>; 851 }; 852 }; 853 }; 854 }; 855 856 funnel@6041000 { 857 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 858 reg = <0 0x06041000 0 0x1000>; 859 860 clocks = <&aoss_qmp>; 861 clock-names = "apb_pclk"; 862 863 out-ports { 864 port { 865 funnel0_out: endpoint { 866 remote-endpoint = <&merge_funnel_in0>; 867 }; 868 }; 869 }; 870 871 in-ports { 872 #address-cells = <1>; 873 #size-cells = <0>; 874 875 port@7 { 876 reg = <7>; 877 funnel0_in7: endpoint { 878 remote-endpoint = <&stm_out>; 879 }; 880 }; 881 }; 882 }; 883 884 funnel@6042000 { 885 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 886 reg = <0 0x06042000 0 0x1000>; 887 888 clocks = <&aoss_qmp>; 889 clock-names = "apb_pclk"; 890 891 out-ports { 892 port { 893 funnel1_out: endpoint { 894 remote-endpoint = <&merge_funnel_in1>; 895 }; 896 }; 897 }; 898 899 in-ports { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 port@4 { 904 reg = <4>; 905 funnel1_in4: endpoint { 906 remote-endpoint = <&apss_merge_funnel_out>; 907 }; 908 }; 909 }; 910 }; 911 912 funnel@6045000 { 913 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 914 reg = <0 0x06045000 0 0x1000>; 915 916 clocks = <&aoss_qmp>; 917 clock-names = "apb_pclk"; 918 919 out-ports { 920 port { 921 merge_funnel_out: endpoint { 922 remote-endpoint = <&swao_funnel_in>; 923 }; 924 }; 925 }; 926 927 in-ports { 928 #address-cells = <1>; 929 #size-cells = <0>; 930 931 port@0 { 932 reg = <0>; 933 merge_funnel_in0: endpoint { 934 remote-endpoint = <&funnel0_out>; 935 }; 936 }; 937 938 port@1 { 939 reg = <1>; 940 merge_funnel_in1: endpoint { 941 remote-endpoint = <&funnel1_out>; 942 }; 943 }; 944 }; 945 }; 946 947 replicator@6046000 { 948 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 949 reg = <0 0x06046000 0 0x1000>; 950 951 clocks = <&aoss_qmp>; 952 clock-names = "apb_pclk"; 953 954 out-ports { 955 port { 956 replicator_out: endpoint { 957 remote-endpoint = <&etr_in>; 958 }; 959 }; 960 }; 961 962 in-ports { 963 port { 964 replicator_in: endpoint { 965 remote-endpoint = <&swao_replicator_out>; 966 }; 967 }; 968 }; 969 }; 970 971 etr@6048000 { 972 compatible = "arm,coresight-tmc", "arm,primecell"; 973 reg = <0 0x06048000 0 0x1000>; 974 iommus = <&apps_smmu 0x04c0 0>; 975 976 clocks = <&aoss_qmp>; 977 clock-names = "apb_pclk"; 978 arm,scatter-gather; 979 980 in-ports { 981 port { 982 etr_in: endpoint { 983 remote-endpoint = <&replicator_out>; 984 }; 985 }; 986 }; 987 }; 988 989 funnel@6b04000 { 990 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 991 reg = <0 0x06b04000 0 0x1000>; 992 993 clocks = <&aoss_qmp>; 994 clock-names = "apb_pclk"; 995 996 out-ports { 997 port { 998 swao_funnel_out: endpoint { 999 remote-endpoint = <&etf_in>; 1000 }; 1001 }; 1002 }; 1003 1004 in-ports { 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 1008 port@7 { 1009 reg = <7>; 1010 swao_funnel_in: endpoint { 1011 remote-endpoint = <&merge_funnel_out>; 1012 }; 1013 }; 1014 }; 1015 }; 1016 1017 etf@6b05000 { 1018 compatible = "arm,coresight-tmc", "arm,primecell"; 1019 reg = <0 0x06b05000 0 0x1000>; 1020 1021 clocks = <&aoss_qmp>; 1022 clock-names = "apb_pclk"; 1023 1024 out-ports { 1025 port { 1026 etf_out: endpoint { 1027 remote-endpoint = <&swao_replicator_in>; 1028 }; 1029 }; 1030 }; 1031 1032 in-ports { 1033 port { 1034 etf_in: endpoint { 1035 remote-endpoint = <&swao_funnel_out>; 1036 }; 1037 }; 1038 }; 1039 }; 1040 1041 replicator@6b06000 { 1042 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1043 reg = <0 0x06b06000 0 0x1000>; 1044 1045 clocks = <&aoss_qmp>; 1046 clock-names = "apb_pclk"; 1047 qcom,replicator-loses-context; 1048 1049 out-ports { 1050 port { 1051 swao_replicator_out: endpoint { 1052 remote-endpoint = <&replicator_in>; 1053 }; 1054 }; 1055 }; 1056 1057 in-ports { 1058 port { 1059 swao_replicator_in: endpoint { 1060 remote-endpoint = <&etf_out>; 1061 }; 1062 }; 1063 }; 1064 }; 1065 1066 etm@7040000 { 1067 compatible = "arm,coresight-etm4x", "arm,primecell"; 1068 reg = <0 0x07040000 0 0x1000>; 1069 1070 cpu = <&CPU0>; 1071 1072 clocks = <&aoss_qmp>; 1073 clock-names = "apb_pclk"; 1074 arm,coresight-loses-context-with-cpu; 1075 qcom,skip-power-up; 1076 1077 out-ports { 1078 port { 1079 etm0_out: endpoint { 1080 remote-endpoint = <&apss_funnel_in0>; 1081 }; 1082 }; 1083 }; 1084 }; 1085 1086 etm@7140000 { 1087 compatible = "arm,coresight-etm4x", "arm,primecell"; 1088 reg = <0 0x07140000 0 0x1000>; 1089 1090 cpu = <&CPU1>; 1091 1092 clocks = <&aoss_qmp>; 1093 clock-names = "apb_pclk"; 1094 arm,coresight-loses-context-with-cpu; 1095 qcom,skip-power-up; 1096 1097 out-ports { 1098 port { 1099 etm1_out: endpoint { 1100 remote-endpoint = <&apss_funnel_in1>; 1101 }; 1102 }; 1103 }; 1104 }; 1105 1106 etm@7240000 { 1107 compatible = "arm,coresight-etm4x", "arm,primecell"; 1108 reg = <0 0x07240000 0 0x1000>; 1109 1110 cpu = <&CPU2>; 1111 1112 clocks = <&aoss_qmp>; 1113 clock-names = "apb_pclk"; 1114 arm,coresight-loses-context-with-cpu; 1115 qcom,skip-power-up; 1116 1117 out-ports { 1118 port { 1119 etm2_out: endpoint { 1120 remote-endpoint = <&apss_funnel_in2>; 1121 }; 1122 }; 1123 }; 1124 }; 1125 1126 etm@7340000 { 1127 compatible = "arm,coresight-etm4x", "arm,primecell"; 1128 reg = <0 0x07340000 0 0x1000>; 1129 1130 cpu = <&CPU3>; 1131 1132 clocks = <&aoss_qmp>; 1133 clock-names = "apb_pclk"; 1134 arm,coresight-loses-context-with-cpu; 1135 qcom,skip-power-up; 1136 1137 out-ports { 1138 port { 1139 etm3_out: endpoint { 1140 remote-endpoint = <&apss_funnel_in3>; 1141 }; 1142 }; 1143 }; 1144 }; 1145 1146 etm@7440000 { 1147 compatible = "arm,coresight-etm4x", "arm,primecell"; 1148 reg = <0 0x07440000 0 0x1000>; 1149 1150 cpu = <&CPU4>; 1151 1152 clocks = <&aoss_qmp>; 1153 clock-names = "apb_pclk"; 1154 arm,coresight-loses-context-with-cpu; 1155 qcom,skip-power-up; 1156 1157 out-ports { 1158 port { 1159 etm4_out: endpoint { 1160 remote-endpoint = <&apss_funnel_in4>; 1161 }; 1162 }; 1163 }; 1164 }; 1165 1166 etm@7540000 { 1167 compatible = "arm,coresight-etm4x", "arm,primecell"; 1168 reg = <0 0x07540000 0 0x1000>; 1169 1170 cpu = <&CPU5>; 1171 1172 clocks = <&aoss_qmp>; 1173 clock-names = "apb_pclk"; 1174 arm,coresight-loses-context-with-cpu; 1175 qcom,skip-power-up; 1176 1177 out-ports { 1178 port { 1179 etm5_out: endpoint { 1180 remote-endpoint = <&apss_funnel_in5>; 1181 }; 1182 }; 1183 }; 1184 }; 1185 1186 etm@7640000 { 1187 compatible = "arm,coresight-etm4x", "arm,primecell"; 1188 reg = <0 0x07640000 0 0x1000>; 1189 1190 cpu = <&CPU6>; 1191 1192 clocks = <&aoss_qmp>; 1193 clock-names = "apb_pclk"; 1194 arm,coresight-loses-context-with-cpu; 1195 qcom,skip-power-up; 1196 1197 out-ports { 1198 port { 1199 etm6_out: endpoint { 1200 remote-endpoint = <&apss_funnel_in6>; 1201 }; 1202 }; 1203 }; 1204 }; 1205 1206 etm@7740000 { 1207 compatible = "arm,coresight-etm4x", "arm,primecell"; 1208 reg = <0 0x07740000 0 0x1000>; 1209 1210 cpu = <&CPU7>; 1211 1212 clocks = <&aoss_qmp>; 1213 clock-names = "apb_pclk"; 1214 arm,coresight-loses-context-with-cpu; 1215 qcom,skip-power-up; 1216 1217 out-ports { 1218 port { 1219 etm7_out: endpoint { 1220 remote-endpoint = <&apss_funnel_in7>; 1221 }; 1222 }; 1223 }; 1224 }; 1225 1226 funnel@7800000 { /* APSS Funnel */ 1227 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1228 reg = <0 0x07800000 0 0x1000>; 1229 1230 clocks = <&aoss_qmp>; 1231 clock-names = "apb_pclk"; 1232 1233 out-ports { 1234 port { 1235 apss_funnel_out: endpoint { 1236 remote-endpoint = <&apss_merge_funnel_in>; 1237 }; 1238 }; 1239 }; 1240 1241 in-ports { 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 1245 port@0 { 1246 reg = <0>; 1247 apss_funnel_in0: endpoint { 1248 remote-endpoint = <&etm0_out>; 1249 }; 1250 }; 1251 1252 port@1 { 1253 reg = <1>; 1254 apss_funnel_in1: endpoint { 1255 remote-endpoint = <&etm1_out>; 1256 }; 1257 }; 1258 1259 port@2 { 1260 reg = <2>; 1261 apss_funnel_in2: endpoint { 1262 remote-endpoint = <&etm2_out>; 1263 }; 1264 }; 1265 1266 port@3 { 1267 reg = <3>; 1268 apss_funnel_in3: endpoint { 1269 remote-endpoint = <&etm3_out>; 1270 }; 1271 }; 1272 1273 port@4 { 1274 reg = <4>; 1275 apss_funnel_in4: endpoint { 1276 remote-endpoint = <&etm4_out>; 1277 }; 1278 }; 1279 1280 port@5 { 1281 reg = <5>; 1282 apss_funnel_in5: endpoint { 1283 remote-endpoint = <&etm5_out>; 1284 }; 1285 }; 1286 1287 port@6 { 1288 reg = <6>; 1289 apss_funnel_in6: endpoint { 1290 remote-endpoint = <&etm6_out>; 1291 }; 1292 }; 1293 1294 port@7 { 1295 reg = <7>; 1296 apss_funnel_in7: endpoint { 1297 remote-endpoint = <&etm7_out>; 1298 }; 1299 }; 1300 }; 1301 }; 1302 1303 funnel@7810000 { 1304 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1305 reg = <0 0x07810000 0 0x1000>; 1306 1307 clocks = <&aoss_qmp>; 1308 clock-names = "apb_pclk"; 1309 1310 out-ports { 1311 port { 1312 apss_merge_funnel_out: endpoint { 1313 remote-endpoint = <&funnel1_in4>; 1314 }; 1315 }; 1316 }; 1317 1318 in-ports { 1319 port { 1320 apss_merge_funnel_in: endpoint { 1321 remote-endpoint = <&apss_funnel_out>; 1322 }; 1323 }; 1324 }; 1325 }; 1326 1327 sdhc_2: sdhci@8804000 { 1328 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1329 status = "disabled"; 1330 1331 reg = <0 0x08804000 0 0x1000>; 1332 1333 iommus = <&apps_smmu 0x100 0x0>; 1334 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1336 interrupt-names = "hc_irq", "pwr_irq"; 1337 1338 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1339 <&gcc GCC_SDCC2_AHB_CLK>, 1340 <&rpmhcc RPMH_CXO_CLK>; 1341 clock-names = "core", "iface", "xo"; 1342 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1343 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1344 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1345 power-domains = <&rpmhpd SC7280_CX>; 1346 operating-points-v2 = <&sdhc2_opp_table>; 1347 1348 bus-width = <4>; 1349 1350 qcom,dll-config = <0x0007642c>; 1351 1352 sdhc2_opp_table: opp-table { 1353 compatible = "operating-points-v2"; 1354 1355 opp-100000000 { 1356 opp-hz = /bits/ 64 <100000000>; 1357 required-opps = <&rpmhpd_opp_low_svs>; 1358 opp-peak-kBps = <1800000 400000>; 1359 opp-avg-kBps = <100000 0>; 1360 }; 1361 1362 opp-202000000 { 1363 opp-hz = /bits/ 64 <202000000>; 1364 required-opps = <&rpmhpd_opp_nom>; 1365 opp-peak-kBps = <5400000 1600000>; 1366 opp-avg-kBps = <200000 0>; 1367 }; 1368 }; 1369 1370 }; 1371 1372 usb_1_hsphy: phy@88e3000 { 1373 compatible = "qcom,sc7280-usb-hs-phy", 1374 "qcom,usb-snps-hs-7nm-phy"; 1375 reg = <0 0x088e3000 0 0x400>; 1376 status = "disabled"; 1377 #phy-cells = <0>; 1378 1379 clocks = <&rpmhcc RPMH_CXO_CLK>; 1380 clock-names = "ref"; 1381 1382 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1383 }; 1384 1385 usb_2_hsphy: phy@88e4000 { 1386 compatible = "qcom,sc7280-usb-hs-phy", 1387 "qcom,usb-snps-hs-7nm-phy"; 1388 reg = <0 0x088e4000 0 0x400>; 1389 status = "disabled"; 1390 #phy-cells = <0>; 1391 1392 clocks = <&rpmhcc RPMH_CXO_CLK>; 1393 clock-names = "ref"; 1394 1395 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1396 }; 1397 1398 usb_1_qmpphy: phy-wrapper@88e9000 { 1399 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1400 "qcom,sm8250-qmp-usb3-dp-phy"; 1401 reg = <0 0x088e9000 0 0x200>, 1402 <0 0x088e8000 0 0x40>, 1403 <0 0x088ea000 0 0x200>; 1404 status = "disabled"; 1405 #address-cells = <2>; 1406 #size-cells = <2>; 1407 ranges; 1408 1409 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1410 <&rpmhcc RPMH_CXO_CLK>, 1411 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1412 clock-names = "aux", "ref_clk_src", "com_aux"; 1413 1414 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1415 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1416 reset-names = "phy", "common"; 1417 1418 usb_1_ssphy: usb3-phy@88e9200 { 1419 reg = <0 0x088e9200 0 0x200>, 1420 <0 0x088e9400 0 0x200>, 1421 <0 0x088e9c00 0 0x400>, 1422 <0 0x088e9600 0 0x200>, 1423 <0 0x088e9800 0 0x200>, 1424 <0 0x088e9a00 0 0x100>; 1425 #clock-cells = <0>; 1426 #phy-cells = <0>; 1427 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1428 clock-names = "pipe0"; 1429 clock-output-names = "usb3_phy_pipe_clk_src"; 1430 }; 1431 1432 dp_phy: dp-phy@88ea200 { 1433 reg = <0 0x088ea200 0 0x200>, 1434 <0 0x088ea400 0 0x200>, 1435 <0 0x088eaa00 0 0x200>, 1436 <0 0x088ea600 0 0x200>, 1437 <0 0x088ea800 0 0x200>; 1438 #phy-cells = <0>; 1439 #clock-cells = <1>; 1440 }; 1441 }; 1442 1443 usb_2: usb@8cf8800 { 1444 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1445 reg = <0 0x08cf8800 0 0x400>; 1446 status = "disabled"; 1447 #address-cells = <2>; 1448 #size-cells = <2>; 1449 ranges; 1450 dma-ranges; 1451 1452 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1453 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1454 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1455 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1456 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1457 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1458 "sleep"; 1459 1460 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1461 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1462 assigned-clock-rates = <19200000>, <200000000>; 1463 1464 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1465 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 1466 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 1467 interrupt-names = "hs_phy_irq", 1468 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1469 1470 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1471 1472 resets = <&gcc GCC_USB30_SEC_BCR>; 1473 1474 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1475 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1476 interconnect-names = "usb-ddr", "apps-usb"; 1477 1478 usb_2_dwc3: usb@8c00000 { 1479 compatible = "snps,dwc3"; 1480 reg = <0 0x08c00000 0 0xe000>; 1481 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1482 iommus = <&apps_smmu 0xa0 0x0>; 1483 snps,dis_u2_susphy_quirk; 1484 snps,dis_enblslpm_quirk; 1485 phys = <&usb_2_hsphy>; 1486 phy-names = "usb2-phy"; 1487 maximum-speed = "high-speed"; 1488 }; 1489 }; 1490 1491 qspi: spi@88dc000 { 1492 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 1493 reg = <0 0x088dc000 0 0x1000>; 1494 #address-cells = <1>; 1495 #size-cells = <0>; 1496 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 1498 <&gcc GCC_QSPI_CORE_CLK>; 1499 clock-names = "iface", "core"; 1500 interconnects = <&gem_noc MASTER_APPSS_PROC 0 1501 &cnoc2 SLAVE_QSPI_0 0>; 1502 interconnect-names = "qspi-config"; 1503 power-domains = <&rpmhpd SC7280_CX>; 1504 operating-points-v2 = <&qspi_opp_table>; 1505 status = "disabled"; 1506 }; 1507 1508 dc_noc: interconnect@90e0000 { 1509 reg = <0 0x090e0000 0 0x5080>; 1510 compatible = "qcom,sc7280-dc-noc"; 1511 #interconnect-cells = <2>; 1512 qcom,bcm-voters = <&apps_bcm_voter>; 1513 }; 1514 1515 gem_noc: interconnect@9100000 { 1516 reg = <0 0x9100000 0 0xe2200>; 1517 compatible = "qcom,sc7280-gem-noc"; 1518 #interconnect-cells = <2>; 1519 qcom,bcm-voters = <&apps_bcm_voter>; 1520 }; 1521 1522 system-cache-controller@9200000 { 1523 compatible = "qcom,sc7280-llcc"; 1524 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1525 reg-names = "llcc_base", "llcc_broadcast_base"; 1526 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1527 }; 1528 1529 nsp_noc: interconnect@a0c0000 { 1530 reg = <0 0x0a0c0000 0 0x10000>; 1531 compatible = "qcom,sc7280-nsp-noc"; 1532 #interconnect-cells = <2>; 1533 qcom,bcm-voters = <&apps_bcm_voter>; 1534 }; 1535 1536 usb_1: usb@a6f8800 { 1537 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1538 reg = <0 0x0a6f8800 0 0x400>; 1539 status = "disabled"; 1540 #address-cells = <2>; 1541 #size-cells = <2>; 1542 ranges; 1543 dma-ranges; 1544 1545 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1546 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1547 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1548 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1549 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1550 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1551 "sleep"; 1552 1553 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1554 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1555 assigned-clock-rates = <19200000>, <200000000>; 1556 1557 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1558 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1559 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1560 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1561 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1562 "dm_hs_phy_irq", "ss_phy_irq"; 1563 1564 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1565 1566 resets = <&gcc GCC_USB30_PRIM_BCR>; 1567 1568 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1570 interconnect-names = "usb-ddr", "apps-usb"; 1571 1572 usb_1_dwc3: usb@a600000 { 1573 compatible = "snps,dwc3"; 1574 reg = <0 0x0a600000 0 0xe000>; 1575 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1576 iommus = <&apps_smmu 0xe0 0x0>; 1577 snps,dis_u2_susphy_quirk; 1578 snps,dis_enblslpm_quirk; 1579 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1580 phy-names = "usb2-phy", "usb3-phy"; 1581 maximum-speed = "super-speed"; 1582 }; 1583 }; 1584 1585 videocc: clock-controller@aaf0000 { 1586 compatible = "qcom,sc7280-videocc"; 1587 reg = <0 0xaaf0000 0 0x10000>; 1588 clocks = <&rpmhcc RPMH_CXO_CLK>, 1589 <&rpmhcc RPMH_CXO_CLK_A>; 1590 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1591 #clock-cells = <1>; 1592 #reset-cells = <1>; 1593 #power-domain-cells = <1>; 1594 }; 1595 1596 dispcc: clock-controller@af00000 { 1597 compatible = "qcom,sc7280-dispcc"; 1598 reg = <0 0xaf00000 0 0x20000>; 1599 clocks = <&rpmhcc RPMH_CXO_CLK>, 1600 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1601 <0>, <0>, <0>, <0>, <0>, <0>; 1602 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1603 "dsi0_phy_pll_out_byteclk", 1604 "dsi0_phy_pll_out_dsiclk", 1605 "dp_phy_pll_link_clk", 1606 "dp_phy_pll_vco_div_clk", 1607 "edp_phy_pll_link_clk", 1608 "edp_phy_pll_vco_div_clk"; 1609 #clock-cells = <1>; 1610 #reset-cells = <1>; 1611 #power-domain-cells = <1>; 1612 }; 1613 1614 pdc: interrupt-controller@b220000 { 1615 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1616 reg = <0 0x0b220000 0 0x30000>; 1617 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1618 <55 306 4>, <59 312 3>, <62 374 2>, 1619 <64 434 2>, <66 438 3>, <69 86 1>, 1620 <70 520 54>, <124 609 31>, <155 63 1>, 1621 <156 716 12>; 1622 #interrupt-cells = <2>; 1623 interrupt-parent = <&intc>; 1624 interrupt-controller; 1625 }; 1626 1627 pdc_reset: reset-controller@b5e0000 { 1628 compatible = "qcom,sc7280-pdc-global"; 1629 reg = <0 0x0b5e0000 0 0x20000>; 1630 #reset-cells = <1>; 1631 }; 1632 1633 tsens0: thermal-sensor@c263000 { 1634 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1635 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1636 <0 0x0c222000 0 0x1ff>; /* SROT */ 1637 #qcom,sensors = <15>; 1638 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1640 interrupt-names = "uplow","critical"; 1641 #thermal-sensor-cells = <1>; 1642 }; 1643 1644 tsens1: thermal-sensor@c265000 { 1645 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1646 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1647 <0 0x0c223000 0 0x1ff>; /* SROT */ 1648 #qcom,sensors = <12>; 1649 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1651 interrupt-names = "uplow","critical"; 1652 #thermal-sensor-cells = <1>; 1653 }; 1654 1655 aoss_reset: reset-controller@c2a0000 { 1656 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1657 reg = <0 0x0c2a0000 0 0x31000>; 1658 #reset-cells = <1>; 1659 }; 1660 1661 aoss_qmp: power-controller@c300000 { 1662 compatible = "qcom,sc7280-aoss-qmp"; 1663 reg = <0 0x0c300000 0 0x100000>; 1664 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1665 IPCC_MPROC_SIGNAL_GLINK_QMP 1666 IRQ_TYPE_EDGE_RISING>; 1667 mboxes = <&ipcc IPCC_CLIENT_AOP 1668 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1669 1670 #clock-cells = <0>; 1671 #power-domain-cells = <1>; 1672 }; 1673 1674 spmi_bus: spmi@c440000 { 1675 compatible = "qcom,spmi-pmic-arb"; 1676 reg = <0 0x0c440000 0 0x1100>, 1677 <0 0x0c600000 0 0x2000000>, 1678 <0 0x0e600000 0 0x100000>, 1679 <0 0x0e700000 0 0xa0000>, 1680 <0 0x0c40a000 0 0x26000>; 1681 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1682 interrupt-names = "periph_irq"; 1683 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1684 qcom,ee = <0>; 1685 qcom,channel = <0>; 1686 #address-cells = <1>; 1687 #size-cells = <1>; 1688 interrupt-controller; 1689 #interrupt-cells = <4>; 1690 }; 1691 1692 tlmm: pinctrl@f100000 { 1693 compatible = "qcom,sc7280-pinctrl"; 1694 reg = <0 0x0f100000 0 0x300000>; 1695 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1696 gpio-controller; 1697 #gpio-cells = <2>; 1698 interrupt-controller; 1699 #interrupt-cells = <2>; 1700 gpio-ranges = <&tlmm 0 0 175>; 1701 wakeup-parent = <&pdc>; 1702 1703 qspi_clk: qspi-clk { 1704 pins = "gpio14"; 1705 function = "qspi_clk"; 1706 }; 1707 1708 qspi_cs0: qspi-cs0 { 1709 pins = "gpio15"; 1710 function = "qspi_cs"; 1711 }; 1712 1713 qspi_cs1: qspi-cs1 { 1714 pins = "gpio19"; 1715 function = "qspi_cs"; 1716 }; 1717 1718 qspi_data01: qspi-data01 { 1719 pins = "gpio12", "gpio13"; 1720 function = "qspi_data"; 1721 }; 1722 1723 qspi_data12: qspi-data12 { 1724 pins = "gpio16", "gpio17"; 1725 function = "qspi_data"; 1726 }; 1727 1728 qup_uart5_default: qup-uart5-default { 1729 pins = "gpio46", "gpio47"; 1730 function = "qup13"; 1731 }; 1732 1733 sdc1_on: sdc1-on { 1734 clk { 1735 pins = "sdc1_clk"; 1736 }; 1737 1738 cmd { 1739 pins = "sdc1_cmd"; 1740 }; 1741 1742 data { 1743 pins = "sdc1_data"; 1744 }; 1745 1746 rclk { 1747 pins = "sdc1_rclk"; 1748 }; 1749 }; 1750 1751 sdc1_off: sdc1-off { 1752 clk { 1753 pins = "sdc1_clk"; 1754 drive-strength = <2>; 1755 bias-bus-hold; 1756 }; 1757 1758 cmd { 1759 pins = "sdc1_cmd"; 1760 drive-strength = <2>; 1761 bias-bus-hold; 1762 }; 1763 1764 data { 1765 pins = "sdc1_data"; 1766 drive-strength = <2>; 1767 bias-bus-hold; 1768 }; 1769 1770 rclk { 1771 pins = "sdc1_rclk"; 1772 bias-bus-hold; 1773 }; 1774 }; 1775 1776 sdc2_on: sdc2-on { 1777 clk { 1778 pins = "sdc2_clk"; 1779 }; 1780 1781 cmd { 1782 pins = "sdc2_cmd"; 1783 }; 1784 1785 data { 1786 pins = "sdc2_data"; 1787 }; 1788 }; 1789 1790 sdc2_off: sdc2-off { 1791 clk { 1792 pins = "sdc2_clk"; 1793 drive-strength = <2>; 1794 bias-bus-hold; 1795 }; 1796 1797 cmd { 1798 pins ="sdc2_cmd"; 1799 drive-strength = <2>; 1800 bias-bus-hold; 1801 }; 1802 1803 data { 1804 pins ="sdc2_data"; 1805 drive-strength = <2>; 1806 bias-bus-hold; 1807 }; 1808 }; 1809 }; 1810 1811 apps_smmu: iommu@15000000 { 1812 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1813 reg = <0 0x15000000 0 0x100000>; 1814 #iommu-cells = <2>; 1815 #global-interrupts = <1>; 1816 dma-coherent; 1817 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1898 }; 1899 1900 intc: interrupt-controller@17a00000 { 1901 compatible = "arm,gic-v3"; 1902 #address-cells = <2>; 1903 #size-cells = <2>; 1904 ranges; 1905 #interrupt-cells = <3>; 1906 interrupt-controller; 1907 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1908 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1909 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1910 1911 gic-its@17a40000 { 1912 compatible = "arm,gic-v3-its"; 1913 msi-controller; 1914 #msi-cells = <1>; 1915 reg = <0 0x17a40000 0 0x20000>; 1916 status = "disabled"; 1917 }; 1918 }; 1919 1920 watchdog@17c10000 { 1921 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1922 reg = <0 0x17c10000 0 0x1000>; 1923 clocks = <&sleep_clk>; 1924 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1925 }; 1926 1927 timer@17c20000 { 1928 #address-cells = <2>; 1929 #size-cells = <2>; 1930 ranges; 1931 compatible = "arm,armv7-timer-mem"; 1932 reg = <0 0x17c20000 0 0x1000>; 1933 1934 frame@17c21000 { 1935 frame-number = <0>; 1936 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1938 reg = <0 0x17c21000 0 0x1000>, 1939 <0 0x17c22000 0 0x1000>; 1940 }; 1941 1942 frame@17c23000 { 1943 frame-number = <1>; 1944 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1945 reg = <0 0x17c23000 0 0x1000>; 1946 status = "disabled"; 1947 }; 1948 1949 frame@17c25000 { 1950 frame-number = <2>; 1951 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1952 reg = <0 0x17c25000 0 0x1000>; 1953 status = "disabled"; 1954 }; 1955 1956 frame@17c27000 { 1957 frame-number = <3>; 1958 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1959 reg = <0 0x17c27000 0 0x1000>; 1960 status = "disabled"; 1961 }; 1962 1963 frame@17c29000 { 1964 frame-number = <4>; 1965 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1966 reg = <0 0x17c29000 0 0x1000>; 1967 status = "disabled"; 1968 }; 1969 1970 frame@17c2b000 { 1971 frame-number = <5>; 1972 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1973 reg = <0 0x17c2b000 0 0x1000>; 1974 status = "disabled"; 1975 }; 1976 1977 frame@17c2d000 { 1978 frame-number = <6>; 1979 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1980 reg = <0 0x17c2d000 0 0x1000>; 1981 status = "disabled"; 1982 }; 1983 }; 1984 1985 apps_rsc: rsc@18200000 { 1986 compatible = "qcom,rpmh-rsc"; 1987 reg = <0 0x18200000 0 0x10000>, 1988 <0 0x18210000 0 0x10000>, 1989 <0 0x18220000 0 0x10000>; 1990 reg-names = "drv-0", "drv-1", "drv-2"; 1991 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1993 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1994 qcom,tcs-offset = <0xd00>; 1995 qcom,drv-id = <2>; 1996 qcom,tcs-config = <ACTIVE_TCS 2>, 1997 <SLEEP_TCS 3>, 1998 <WAKE_TCS 3>, 1999 <CONTROL_TCS 1>; 2000 2001 apps_bcm_voter: bcm-voter { 2002 compatible = "qcom,bcm-voter"; 2003 }; 2004 2005 rpmhpd: power-controller { 2006 compatible = "qcom,sc7280-rpmhpd"; 2007 #power-domain-cells = <1>; 2008 operating-points-v2 = <&rpmhpd_opp_table>; 2009 2010 rpmhpd_opp_table: opp-table { 2011 compatible = "operating-points-v2"; 2012 2013 rpmhpd_opp_ret: opp1 { 2014 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2015 }; 2016 2017 rpmhpd_opp_low_svs: opp2 { 2018 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2019 }; 2020 2021 rpmhpd_opp_svs: opp3 { 2022 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2023 }; 2024 2025 rpmhpd_opp_svs_l1: opp4 { 2026 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2027 }; 2028 2029 rpmhpd_opp_svs_l2: opp5 { 2030 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2031 }; 2032 2033 rpmhpd_opp_nom: opp6 { 2034 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2035 }; 2036 2037 rpmhpd_opp_nom_l1: opp7 { 2038 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2039 }; 2040 2041 rpmhpd_opp_turbo: opp8 { 2042 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2043 }; 2044 2045 rpmhpd_opp_turbo_l1: opp9 { 2046 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2047 }; 2048 }; 2049 }; 2050 2051 rpmhcc: clock-controller { 2052 compatible = "qcom,sc7280-rpmh-clk"; 2053 clocks = <&xo_board>; 2054 clock-names = "xo"; 2055 #clock-cells = <1>; 2056 }; 2057 }; 2058 2059 cpufreq_hw: cpufreq@18591000 { 2060 compatible = "qcom,cpufreq-epss"; 2061 reg = <0 0x18591100 0 0x900>, 2062 <0 0x18592100 0 0x900>, 2063 <0 0x18593100 0 0x900>; 2064 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2065 clock-names = "xo", "alternate"; 2066 #freq-domain-cells = <1>; 2067 }; 2068 }; 2069 2070 thermal_zones: thermal-zones { 2071 cpu0-thermal { 2072 polling-delay-passive = <250>; 2073 polling-delay = <0>; 2074 2075 thermal-sensors = <&tsens0 1>; 2076 2077 trips { 2078 cpu0_alert0: trip-point0 { 2079 temperature = <90000>; 2080 hysteresis = <2000>; 2081 type = "passive"; 2082 }; 2083 2084 cpu0_alert1: trip-point1 { 2085 temperature = <95000>; 2086 hysteresis = <2000>; 2087 type = "passive"; 2088 }; 2089 2090 cpu0_crit: cpu-crit { 2091 temperature = <110000>; 2092 hysteresis = <0>; 2093 type = "critical"; 2094 }; 2095 }; 2096 2097 cooling-maps { 2098 map0 { 2099 trip = <&cpu0_alert0>; 2100 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2101 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2102 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2103 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2104 }; 2105 map1 { 2106 trip = <&cpu0_alert1>; 2107 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2108 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2109 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2110 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2111 }; 2112 }; 2113 }; 2114 2115 cpu1-thermal { 2116 polling-delay-passive = <250>; 2117 polling-delay = <0>; 2118 2119 thermal-sensors = <&tsens0 2>; 2120 2121 trips { 2122 cpu1_alert0: trip-point0 { 2123 temperature = <90000>; 2124 hysteresis = <2000>; 2125 type = "passive"; 2126 }; 2127 2128 cpu1_alert1: trip-point1 { 2129 temperature = <95000>; 2130 hysteresis = <2000>; 2131 type = "passive"; 2132 }; 2133 2134 cpu1_crit: cpu-crit { 2135 temperature = <110000>; 2136 hysteresis = <0>; 2137 type = "critical"; 2138 }; 2139 }; 2140 2141 cooling-maps { 2142 map0 { 2143 trip = <&cpu1_alert0>; 2144 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2145 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2146 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2147 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2148 }; 2149 map1 { 2150 trip = <&cpu1_alert1>; 2151 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2152 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2153 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2154 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2155 }; 2156 }; 2157 }; 2158 2159 cpu2-thermal { 2160 polling-delay-passive = <250>; 2161 polling-delay = <0>; 2162 2163 thermal-sensors = <&tsens0 3>; 2164 2165 trips { 2166 cpu2_alert0: trip-point0 { 2167 temperature = <90000>; 2168 hysteresis = <2000>; 2169 type = "passive"; 2170 }; 2171 2172 cpu2_alert1: trip-point1 { 2173 temperature = <95000>; 2174 hysteresis = <2000>; 2175 type = "passive"; 2176 }; 2177 2178 cpu2_crit: cpu-crit { 2179 temperature = <110000>; 2180 hysteresis = <0>; 2181 type = "critical"; 2182 }; 2183 }; 2184 2185 cooling-maps { 2186 map0 { 2187 trip = <&cpu2_alert0>; 2188 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2189 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2190 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2191 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2192 }; 2193 map1 { 2194 trip = <&cpu2_alert1>; 2195 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2196 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2197 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2198 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2199 }; 2200 }; 2201 }; 2202 2203 cpu3-thermal { 2204 polling-delay-passive = <250>; 2205 polling-delay = <0>; 2206 2207 thermal-sensors = <&tsens0 4>; 2208 2209 trips { 2210 cpu3_alert0: trip-point0 { 2211 temperature = <90000>; 2212 hysteresis = <2000>; 2213 type = "passive"; 2214 }; 2215 2216 cpu3_alert1: trip-point1 { 2217 temperature = <95000>; 2218 hysteresis = <2000>; 2219 type = "passive"; 2220 }; 2221 2222 cpu3_crit: cpu-crit { 2223 temperature = <110000>; 2224 hysteresis = <0>; 2225 type = "critical"; 2226 }; 2227 }; 2228 2229 cooling-maps { 2230 map0 { 2231 trip = <&cpu3_alert0>; 2232 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2233 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2234 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2235 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2236 }; 2237 map1 { 2238 trip = <&cpu3_alert1>; 2239 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2240 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2241 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2242 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2243 }; 2244 }; 2245 }; 2246 2247 cpu4-thermal { 2248 polling-delay-passive = <250>; 2249 polling-delay = <0>; 2250 2251 thermal-sensors = <&tsens0 7>; 2252 2253 trips { 2254 cpu4_alert0: trip-point0 { 2255 temperature = <90000>; 2256 hysteresis = <2000>; 2257 type = "passive"; 2258 }; 2259 2260 cpu4_alert1: trip-point1 { 2261 temperature = <95000>; 2262 hysteresis = <2000>; 2263 type = "passive"; 2264 }; 2265 2266 cpu4_crit: cpu-crit { 2267 temperature = <110000>; 2268 hysteresis = <0>; 2269 type = "critical"; 2270 }; 2271 }; 2272 2273 cooling-maps { 2274 map0 { 2275 trip = <&cpu4_alert0>; 2276 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2277 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2278 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2279 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2280 }; 2281 map1 { 2282 trip = <&cpu4_alert1>; 2283 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2284 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2285 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2286 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2287 }; 2288 }; 2289 }; 2290 2291 cpu5-thermal { 2292 polling-delay-passive = <250>; 2293 polling-delay = <0>; 2294 2295 thermal-sensors = <&tsens0 8>; 2296 2297 trips { 2298 cpu5_alert0: trip-point0 { 2299 temperature = <90000>; 2300 hysteresis = <2000>; 2301 type = "passive"; 2302 }; 2303 2304 cpu5_alert1: trip-point1 { 2305 temperature = <95000>; 2306 hysteresis = <2000>; 2307 type = "passive"; 2308 }; 2309 2310 cpu5_crit: cpu-crit { 2311 temperature = <110000>; 2312 hysteresis = <0>; 2313 type = "critical"; 2314 }; 2315 }; 2316 2317 cooling-maps { 2318 map0 { 2319 trip = <&cpu5_alert0>; 2320 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2321 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2322 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2323 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2324 }; 2325 map1 { 2326 trip = <&cpu5_alert1>; 2327 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2328 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2329 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2330 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2331 }; 2332 }; 2333 }; 2334 2335 cpu6-thermal { 2336 polling-delay-passive = <250>; 2337 polling-delay = <0>; 2338 2339 thermal-sensors = <&tsens0 9>; 2340 2341 trips { 2342 cpu6_alert0: trip-point0 { 2343 temperature = <90000>; 2344 hysteresis = <2000>; 2345 type = "passive"; 2346 }; 2347 2348 cpu6_alert1: trip-point1 { 2349 temperature = <95000>; 2350 hysteresis = <2000>; 2351 type = "passive"; 2352 }; 2353 2354 cpu6_crit: cpu-crit { 2355 temperature = <110000>; 2356 hysteresis = <0>; 2357 type = "critical"; 2358 }; 2359 }; 2360 2361 cooling-maps { 2362 map0 { 2363 trip = <&cpu6_alert0>; 2364 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2365 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2366 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2367 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2368 }; 2369 map1 { 2370 trip = <&cpu6_alert1>; 2371 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2372 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2373 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2374 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2375 }; 2376 }; 2377 }; 2378 2379 cpu7-thermal { 2380 polling-delay-passive = <250>; 2381 polling-delay = <0>; 2382 2383 thermal-sensors = <&tsens0 10>; 2384 2385 trips { 2386 cpu7_alert0: trip-point0 { 2387 temperature = <90000>; 2388 hysteresis = <2000>; 2389 type = "passive"; 2390 }; 2391 2392 cpu7_alert1: trip-point1 { 2393 temperature = <95000>; 2394 hysteresis = <2000>; 2395 type = "passive"; 2396 }; 2397 2398 cpu7_crit: cpu-crit { 2399 temperature = <110000>; 2400 hysteresis = <0>; 2401 type = "critical"; 2402 }; 2403 }; 2404 2405 cooling-maps { 2406 map0 { 2407 trip = <&cpu7_alert0>; 2408 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2409 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2410 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2411 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2412 }; 2413 map1 { 2414 trip = <&cpu7_alert1>; 2415 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2416 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2417 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2418 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2419 }; 2420 }; 2421 }; 2422 2423 cpu8-thermal { 2424 polling-delay-passive = <250>; 2425 polling-delay = <0>; 2426 2427 thermal-sensors = <&tsens0 11>; 2428 2429 trips { 2430 cpu8_alert0: trip-point0 { 2431 temperature = <90000>; 2432 hysteresis = <2000>; 2433 type = "passive"; 2434 }; 2435 2436 cpu8_alert1: trip-point1 { 2437 temperature = <95000>; 2438 hysteresis = <2000>; 2439 type = "passive"; 2440 }; 2441 2442 cpu8_crit: cpu-crit { 2443 temperature = <110000>; 2444 hysteresis = <0>; 2445 type = "critical"; 2446 }; 2447 }; 2448 2449 cooling-maps { 2450 map0 { 2451 trip = <&cpu8_alert0>; 2452 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2453 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2454 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2455 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2456 }; 2457 map1 { 2458 trip = <&cpu8_alert1>; 2459 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2460 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2461 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2462 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2463 }; 2464 }; 2465 }; 2466 2467 cpu9-thermal { 2468 polling-delay-passive = <250>; 2469 polling-delay = <0>; 2470 2471 thermal-sensors = <&tsens0 12>; 2472 2473 trips { 2474 cpu9_alert0: trip-point0 { 2475 temperature = <90000>; 2476 hysteresis = <2000>; 2477 type = "passive"; 2478 }; 2479 2480 cpu9_alert1: trip-point1 { 2481 temperature = <95000>; 2482 hysteresis = <2000>; 2483 type = "passive"; 2484 }; 2485 2486 cpu9_crit: cpu-crit { 2487 temperature = <110000>; 2488 hysteresis = <0>; 2489 type = "critical"; 2490 }; 2491 }; 2492 2493 cooling-maps { 2494 map0 { 2495 trip = <&cpu9_alert0>; 2496 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2497 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2498 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2499 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2500 }; 2501 map1 { 2502 trip = <&cpu9_alert1>; 2503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2504 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2505 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2506 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2507 }; 2508 }; 2509 }; 2510 2511 cpu10-thermal { 2512 polling-delay-passive = <250>; 2513 polling-delay = <0>; 2514 2515 thermal-sensors = <&tsens0 13>; 2516 2517 trips { 2518 cpu10_alert0: trip-point0 { 2519 temperature = <90000>; 2520 hysteresis = <2000>; 2521 type = "passive"; 2522 }; 2523 2524 cpu10_alert1: trip-point1 { 2525 temperature = <95000>; 2526 hysteresis = <2000>; 2527 type = "passive"; 2528 }; 2529 2530 cpu10_crit: cpu-crit { 2531 temperature = <110000>; 2532 hysteresis = <0>; 2533 type = "critical"; 2534 }; 2535 }; 2536 2537 cooling-maps { 2538 map0 { 2539 trip = <&cpu10_alert0>; 2540 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2541 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2542 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2543 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2544 }; 2545 map1 { 2546 trip = <&cpu10_alert1>; 2547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2551 }; 2552 }; 2553 }; 2554 2555 cpu11-thermal { 2556 polling-delay-passive = <250>; 2557 polling-delay = <0>; 2558 2559 thermal-sensors = <&tsens0 14>; 2560 2561 trips { 2562 cpu11_alert0: trip-point0 { 2563 temperature = <90000>; 2564 hysteresis = <2000>; 2565 type = "passive"; 2566 }; 2567 2568 cpu11_alert1: trip-point1 { 2569 temperature = <95000>; 2570 hysteresis = <2000>; 2571 type = "passive"; 2572 }; 2573 2574 cpu11_crit: cpu-crit { 2575 temperature = <110000>; 2576 hysteresis = <0>; 2577 type = "critical"; 2578 }; 2579 }; 2580 2581 cooling-maps { 2582 map0 { 2583 trip = <&cpu11_alert0>; 2584 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2585 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2586 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2587 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2588 }; 2589 map1 { 2590 trip = <&cpu11_alert1>; 2591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2595 }; 2596 }; 2597 }; 2598 2599 aoss0-thermal { 2600 polling-delay-passive = <0>; 2601 polling-delay = <0>; 2602 2603 thermal-sensors = <&tsens0 0>; 2604 2605 trips { 2606 aoss0_alert0: trip-point0 { 2607 temperature = <90000>; 2608 hysteresis = <2000>; 2609 type = "hot"; 2610 }; 2611 2612 aoss0_crit: aoss0-crit { 2613 temperature = <110000>; 2614 hysteresis = <0>; 2615 type = "critical"; 2616 }; 2617 }; 2618 }; 2619 2620 aoss1-thermal { 2621 polling-delay-passive = <0>; 2622 polling-delay = <0>; 2623 2624 thermal-sensors = <&tsens1 0>; 2625 2626 trips { 2627 aoss1_alert0: trip-point0 { 2628 temperature = <90000>; 2629 hysteresis = <2000>; 2630 type = "hot"; 2631 }; 2632 2633 aoss1_crit: aoss1-crit { 2634 temperature = <110000>; 2635 hysteresis = <0>; 2636 type = "critical"; 2637 }; 2638 }; 2639 }; 2640 2641 cpuss0-thermal { 2642 polling-delay-passive = <0>; 2643 polling-delay = <0>; 2644 2645 thermal-sensors = <&tsens0 5>; 2646 2647 trips { 2648 cpuss0_alert0: trip-point0 { 2649 temperature = <90000>; 2650 hysteresis = <2000>; 2651 type = "hot"; 2652 }; 2653 cpuss0_crit: cluster0-crit { 2654 temperature = <110000>; 2655 hysteresis = <0>; 2656 type = "critical"; 2657 }; 2658 }; 2659 }; 2660 2661 cpuss1-thermal { 2662 polling-delay-passive = <0>; 2663 polling-delay = <0>; 2664 2665 thermal-sensors = <&tsens0 6>; 2666 2667 trips { 2668 cpuss1_alert0: trip-point0 { 2669 temperature = <90000>; 2670 hysteresis = <2000>; 2671 type = "hot"; 2672 }; 2673 cpuss1_crit: cluster0-crit { 2674 temperature = <110000>; 2675 hysteresis = <0>; 2676 type = "critical"; 2677 }; 2678 }; 2679 }; 2680 2681 gpuss0-thermal { 2682 polling-delay-passive = <100>; 2683 polling-delay = <0>; 2684 2685 thermal-sensors = <&tsens1 1>; 2686 2687 trips { 2688 gpuss0_alert0: trip-point0 { 2689 temperature = <95000>; 2690 hysteresis = <2000>; 2691 type = "passive"; 2692 }; 2693 2694 gpuss0_crit: gpuss0-crit { 2695 temperature = <110000>; 2696 hysteresis = <0>; 2697 type = "critical"; 2698 }; 2699 }; 2700 2701 cooling-maps { 2702 map0 { 2703 trip = <&gpuss0_alert0>; 2704 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2705 }; 2706 }; 2707 }; 2708 2709 gpuss1-thermal { 2710 polling-delay-passive = <100>; 2711 polling-delay = <0>; 2712 2713 thermal-sensors = <&tsens1 2>; 2714 2715 trips { 2716 gpuss1_alert0: trip-point0 { 2717 temperature = <95000>; 2718 hysteresis = <2000>; 2719 type = "passive"; 2720 }; 2721 2722 gpuss1_crit: gpuss1-crit { 2723 temperature = <110000>; 2724 hysteresis = <0>; 2725 type = "critical"; 2726 }; 2727 }; 2728 2729 cooling-maps { 2730 map0 { 2731 trip = <&gpuss1_alert0>; 2732 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2733 }; 2734 }; 2735 }; 2736 2737 nspss0-thermal { 2738 polling-delay-passive = <0>; 2739 polling-delay = <0>; 2740 2741 thermal-sensors = <&tsens1 3>; 2742 2743 trips { 2744 nspss0_alert0: trip-point0 { 2745 temperature = <90000>; 2746 hysteresis = <2000>; 2747 type = "hot"; 2748 }; 2749 2750 nspss0_crit: nspss0-crit { 2751 temperature = <110000>; 2752 hysteresis = <0>; 2753 type = "critical"; 2754 }; 2755 }; 2756 }; 2757 2758 nspss1-thermal { 2759 polling-delay-passive = <0>; 2760 polling-delay = <0>; 2761 2762 thermal-sensors = <&tsens1 4>; 2763 2764 trips { 2765 nspss1_alert0: trip-point0 { 2766 temperature = <90000>; 2767 hysteresis = <2000>; 2768 type = "hot"; 2769 }; 2770 2771 nspss1_crit: nspss1-crit { 2772 temperature = <110000>; 2773 hysteresis = <0>; 2774 type = "critical"; 2775 }; 2776 }; 2777 }; 2778 2779 video-thermal { 2780 polling-delay-passive = <0>; 2781 polling-delay = <0>; 2782 2783 thermal-sensors = <&tsens1 5>; 2784 2785 trips { 2786 video_alert0: trip-point0 { 2787 temperature = <90000>; 2788 hysteresis = <2000>; 2789 type = "hot"; 2790 }; 2791 2792 video_crit: video-crit { 2793 temperature = <110000>; 2794 hysteresis = <0>; 2795 type = "critical"; 2796 }; 2797 }; 2798 }; 2799 2800 ddr-thermal { 2801 polling-delay-passive = <0>; 2802 polling-delay = <0>; 2803 2804 thermal-sensors = <&tsens1 6>; 2805 2806 trips { 2807 ddr_alert0: trip-point0 { 2808 temperature = <90000>; 2809 hysteresis = <2000>; 2810 type = "hot"; 2811 }; 2812 2813 ddr_crit: ddr-crit { 2814 temperature = <110000>; 2815 hysteresis = <0>; 2816 type = "critical"; 2817 }; 2818 }; 2819 }; 2820 2821 mdmss0-thermal { 2822 polling-delay-passive = <0>; 2823 polling-delay = <0>; 2824 2825 thermal-sensors = <&tsens1 7>; 2826 2827 trips { 2828 mdmss0_alert0: trip-point0 { 2829 temperature = <90000>; 2830 hysteresis = <2000>; 2831 type = "hot"; 2832 }; 2833 2834 mdmss0_crit: mdmss0-crit { 2835 temperature = <110000>; 2836 hysteresis = <0>; 2837 type = "critical"; 2838 }; 2839 }; 2840 }; 2841 2842 mdmss1-thermal { 2843 polling-delay-passive = <0>; 2844 polling-delay = <0>; 2845 2846 thermal-sensors = <&tsens1 8>; 2847 2848 trips { 2849 mdmss1_alert0: trip-point0 { 2850 temperature = <90000>; 2851 hysteresis = <2000>; 2852 type = "hot"; 2853 }; 2854 2855 mdmss1_crit: mdmss1-crit { 2856 temperature = <110000>; 2857 hysteresis = <0>; 2858 type = "critical"; 2859 }; 2860 }; 2861 }; 2862 2863 mdmss2-thermal { 2864 polling-delay-passive = <0>; 2865 polling-delay = <0>; 2866 2867 thermal-sensors = <&tsens1 9>; 2868 2869 trips { 2870 mdmss2_alert0: trip-point0 { 2871 temperature = <90000>; 2872 hysteresis = <2000>; 2873 type = "hot"; 2874 }; 2875 2876 mdmss2_crit: mdmss2-crit { 2877 temperature = <110000>; 2878 hysteresis = <0>; 2879 type = "critical"; 2880 }; 2881 }; 2882 }; 2883 2884 mdmss3-thermal { 2885 polling-delay-passive = <0>; 2886 polling-delay = <0>; 2887 2888 thermal-sensors = <&tsens1 10>; 2889 2890 trips { 2891 mdmss3_alert0: trip-point0 { 2892 temperature = <90000>; 2893 hysteresis = <2000>; 2894 type = "hot"; 2895 }; 2896 2897 mdmss3_crit: mdmss3-crit { 2898 temperature = <110000>; 2899 hysteresis = <0>; 2900 type = "critical"; 2901 }; 2902 }; 2903 }; 2904 2905 camera0-thermal { 2906 polling-delay-passive = <0>; 2907 polling-delay = <0>; 2908 2909 thermal-sensors = <&tsens1 11>; 2910 2911 trips { 2912 camera0_alert0: trip-point0 { 2913 temperature = <90000>; 2914 hysteresis = <2000>; 2915 type = "hot"; 2916 }; 2917 2918 camera0_crit: camera0-crit { 2919 temperature = <110000>; 2920 hysteresis = <0>; 2921 type = "critical"; 2922 }; 2923 }; 2924 }; 2925 }; 2926 2927 timer { 2928 compatible = "arm,armv8-timer"; 2929 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2930 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2931 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2932 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2933 }; 2934}; 2935