1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7280.h> 13#include <dt-bindings/interconnect/qcom,sc7280.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/reset/qcom,sdm845-aoss.h> 18#include <dt-bindings/reset/qcom,sdm845-pdc.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 mmc1 = &sdhc_1; 48 mmc2 = &sdhc_2; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 }; 66 67 clocks { 68 xo_board: xo-board { 69 compatible = "fixed-clock"; 70 clock-frequency = <76800000>; 71 #clock-cells = <0>; 72 }; 73 74 sleep_clk: sleep-clk { 75 compatible = "fixed-clock"; 76 clock-frequency = <32000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 reserved-memory { 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 hyp_mem: memory@80000000 { 87 reg = <0x0 0x80000000 0x0 0x600000>; 88 no-map; 89 }; 90 91 xbl_mem: memory@80600000 { 92 reg = <0x0 0x80600000 0x0 0x200000>; 93 no-map; 94 }; 95 96 aop_mem: memory@80800000 { 97 reg = <0x0 0x80800000 0x0 0x60000>; 98 no-map; 99 }; 100 101 aop_cmd_db_mem: memory@80860000 { 102 reg = <0x0 0x80860000 0x0 0x20000>; 103 compatible = "qcom,cmd-db"; 104 no-map; 105 }; 106 107 reserved_xbl_uefi_log: memory@80880000 { 108 reg = <0x0 0x80884000 0x0 0x10000>; 109 no-map; 110 }; 111 112 sec_apps_mem: memory@808ff000 { 113 reg = <0x0 0x808ff000 0x0 0x1000>; 114 no-map; 115 }; 116 117 smem_mem: memory@80900000 { 118 reg = <0x0 0x80900000 0x0 0x200000>; 119 no-map; 120 }; 121 122 cpucp_mem: memory@80b00000 { 123 no-map; 124 reg = <0x0 0x80b00000 0x0 0x100000>; 125 }; 126 127 wlan_fw_mem: memory@80c00000 { 128 reg = <0x0 0x80c00000 0x0 0xc00000>; 129 no-map; 130 }; 131 132 ipa_fw_mem: memory@8b700000 { 133 reg = <0 0x8b700000 0 0x10000>; 134 no-map; 135 }; 136 137 rmtfs_mem: memory@9c900000 { 138 compatible = "qcom,rmtfs-mem"; 139 reg = <0x0 0x9c900000 0x0 0x280000>; 140 no-map; 141 142 qcom,client-id = <1>; 143 qcom,vmid = <15>; 144 }; 145 }; 146 147 cpus { 148 #address-cells = <2>; 149 #size-cells = <0>; 150 151 CPU0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,kryo"; 154 reg = <0x0 0x0>; 155 enable-method = "psci"; 156 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 157 &LITTLE_CPU_SLEEP_1 158 &CLUSTER_SLEEP_0>; 159 next-level-cache = <&L2_0>; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 #cooling-cells = <2>; 162 L2_0: l2-cache { 163 compatible = "cache"; 164 next-level-cache = <&L3_0>; 165 L3_0: l3-cache { 166 compatible = "cache"; 167 }; 168 }; 169 }; 170 171 CPU1: cpu@100 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x100>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_100>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_100: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU2: cpu@200 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x200>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_200>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 #cooling-cells = <2>; 199 L2_200: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU3: cpu@300 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x300>; 209 enable-method = "psci"; 210 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 211 &LITTLE_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_300>; 214 qcom,freq-domain = <&cpufreq_hw 0>; 215 #cooling-cells = <2>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "arm,kryo"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&BIG_CPU_SLEEP_0 228 &BIG_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 next-level-cache = <&L2_400>; 231 qcom,freq-domain = <&cpufreq_hw 1>; 232 #cooling-cells = <2>; 233 L2_400: l2-cache { 234 compatible = "cache"; 235 next-level-cache = <&L3_0>; 236 }; 237 }; 238 239 CPU5: cpu@500 { 240 device_type = "cpu"; 241 compatible = "arm,kryo"; 242 reg = <0x0 0x500>; 243 enable-method = "psci"; 244 cpu-idle-states = <&BIG_CPU_SLEEP_0 245 &BIG_CPU_SLEEP_1 246 &CLUSTER_SLEEP_0>; 247 next-level-cache = <&L2_500>; 248 qcom,freq-domain = <&cpufreq_hw 1>; 249 #cooling-cells = <2>; 250 L2_500: l2-cache { 251 compatible = "cache"; 252 next-level-cache = <&L3_0>; 253 }; 254 }; 255 256 CPU6: cpu@600 { 257 device_type = "cpu"; 258 compatible = "arm,kryo"; 259 reg = <0x0 0x600>; 260 enable-method = "psci"; 261 cpu-idle-states = <&BIG_CPU_SLEEP_0 262 &BIG_CPU_SLEEP_1 263 &CLUSTER_SLEEP_0>; 264 next-level-cache = <&L2_600>; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 #cooling-cells = <2>; 267 L2_600: l2-cache { 268 compatible = "cache"; 269 next-level-cache = <&L3_0>; 270 }; 271 }; 272 273 CPU7: cpu@700 { 274 device_type = "cpu"; 275 compatible = "arm,kryo"; 276 reg = <0x0 0x700>; 277 enable-method = "psci"; 278 cpu-idle-states = <&BIG_CPU_SLEEP_0 279 &BIG_CPU_SLEEP_1 280 &CLUSTER_SLEEP_0>; 281 next-level-cache = <&L2_700>; 282 qcom,freq-domain = <&cpufreq_hw 2>; 283 #cooling-cells = <2>; 284 L2_700: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 cpu-map { 291 cluster0 { 292 core0 { 293 cpu = <&CPU0>; 294 }; 295 296 core1 { 297 cpu = <&CPU1>; 298 }; 299 300 core2 { 301 cpu = <&CPU2>; 302 }; 303 304 core3 { 305 cpu = <&CPU3>; 306 }; 307 308 core4 { 309 cpu = <&CPU4>; 310 }; 311 312 core5 { 313 cpu = <&CPU5>; 314 }; 315 316 core6 { 317 cpu = <&CPU6>; 318 }; 319 320 core7 { 321 cpu = <&CPU7>; 322 }; 323 }; 324 }; 325 326 idle-states { 327 entry-method = "psci"; 328 329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-power-down"; 332 arm,psci-suspend-param = <0x40000003>; 333 entry-latency-us = <549>; 334 exit-latency-us = <901>; 335 min-residency-us = <1774>; 336 local-timer-stop; 337 }; 338 339 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "little-rail-power-down"; 342 arm,psci-suspend-param = <0x40000004>; 343 entry-latency-us = <702>; 344 exit-latency-us = <915>; 345 min-residency-us = <4001>; 346 local-timer-stop; 347 }; 348 349 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "big-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <523>; 354 exit-latency-us = <1244>; 355 min-residency-us = <2207>; 356 local-timer-stop; 357 }; 358 359 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "big-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <526>; 364 exit-latency-us = <1854>; 365 min-residency-us = <5555>; 366 local-timer-stop; 367 }; 368 369 CLUSTER_SLEEP_0: cluster-sleep-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "cluster-power-down"; 372 arm,psci-suspend-param = <0x40003444>; 373 entry-latency-us = <3263>; 374 exit-latency-us = <6562>; 375 min-residency-us = <9926>; 376 local-timer-stop; 377 }; 378 }; 379 }; 380 381 memory@80000000 { 382 device_type = "memory"; 383 /* We expect the bootloader to fill in the size */ 384 reg = <0 0x80000000 0 0>; 385 }; 386 387 firmware { 388 scm { 389 compatible = "qcom,scm-sc7280", "qcom,scm"; 390 }; 391 }; 392 393 clk_virt: interconnect { 394 compatible = "qcom,sc7280-clk-virt"; 395 #interconnect-cells = <2>; 396 qcom,bcm-voters = <&apps_bcm_voter>; 397 }; 398 399 smem { 400 compatible = "qcom,smem"; 401 memory-region = <&smem_mem>; 402 hwlocks = <&tcsr_mutex 3>; 403 }; 404 405 smp2p-adsp { 406 compatible = "qcom,smp2p"; 407 qcom,smem = <443>, <429>; 408 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 409 IPCC_MPROC_SIGNAL_SMP2P 410 IRQ_TYPE_EDGE_RISING>; 411 mboxes = <&ipcc IPCC_CLIENT_LPASS 412 IPCC_MPROC_SIGNAL_SMP2P>; 413 414 qcom,local-pid = <0>; 415 qcom,remote-pid = <2>; 416 417 adsp_smp2p_out: master-kernel { 418 qcom,entry-name = "master-kernel"; 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 adsp_smp2p_in: slave-kernel { 423 qcom,entry-name = "slave-kernel"; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 }; 428 429 smp2p-cdsp { 430 compatible = "qcom,smp2p"; 431 qcom,smem = <94>, <432>; 432 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 433 IPCC_MPROC_SIGNAL_SMP2P 434 IRQ_TYPE_EDGE_RISING>; 435 mboxes = <&ipcc IPCC_CLIENT_CDSP 436 IPCC_MPROC_SIGNAL_SMP2P>; 437 438 qcom,local-pid = <0>; 439 qcom,remote-pid = <5>; 440 441 cdsp_smp2p_out: master-kernel { 442 qcom,entry-name = "master-kernel"; 443 #qcom,smem-state-cells = <1>; 444 }; 445 446 cdsp_smp2p_in: slave-kernel { 447 qcom,entry-name = "slave-kernel"; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 }; 451 }; 452 453 smp2p-mpss { 454 compatible = "qcom,smp2p"; 455 qcom,smem = <435>, <428>; 456 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 457 IPCC_MPROC_SIGNAL_SMP2P 458 IRQ_TYPE_EDGE_RISING>; 459 mboxes = <&ipcc IPCC_CLIENT_MPSS 460 IPCC_MPROC_SIGNAL_SMP2P>; 461 462 qcom,local-pid = <0>; 463 qcom,remote-pid = <1>; 464 465 modem_smp2p_out: master-kernel { 466 qcom,entry-name = "master-kernel"; 467 #qcom,smem-state-cells = <1>; 468 }; 469 470 modem_smp2p_in: slave-kernel { 471 qcom,entry-name = "slave-kernel"; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 }; 475 476 ipa_smp2p_out: ipa-ap-to-modem { 477 qcom,entry-name = "ipa"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 ipa_smp2p_in: ipa-modem-to-ap { 482 qcom,entry-name = "ipa"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 smp2p-wpss { 489 compatible = "qcom,smp2p"; 490 qcom,smem = <617>, <616>; 491 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 492 IPCC_MPROC_SIGNAL_SMP2P 493 IRQ_TYPE_EDGE_RISING>; 494 mboxes = <&ipcc IPCC_CLIENT_WPSS 495 IPCC_MPROC_SIGNAL_SMP2P>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <13>; 499 500 wpss_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 wpss_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 pmu { 513 compatible = "arm,armv8-pmuv3"; 514 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 515 }; 516 517 psci { 518 compatible = "arm,psci-1.0"; 519 method = "smc"; 520 }; 521 522 qspi_opp_table: qspi-opp-table { 523 compatible = "operating-points-v2"; 524 525 opp-75000000 { 526 opp-hz = /bits/ 64 <75000000>; 527 required-opps = <&rpmhpd_opp_low_svs>; 528 }; 529 530 opp-150000000 { 531 opp-hz = /bits/ 64 <150000000>; 532 required-opps = <&rpmhpd_opp_svs>; 533 }; 534 535 opp-200000000 { 536 opp-hz = /bits/ 64 <200000000>; 537 required-opps = <&rpmhpd_opp_svs_l1>; 538 }; 539 540 opp-300000000 { 541 opp-hz = /bits/ 64 <300000000>; 542 required-opps = <&rpmhpd_opp_nom>; 543 }; 544 }; 545 546 qup_opp_table: qup-opp-table { 547 compatible = "operating-points-v2"; 548 549 opp-75000000 { 550 opp-hz = /bits/ 64 <75000000>; 551 required-opps = <&rpmhpd_opp_low_svs>; 552 }; 553 554 opp-100000000 { 555 opp-hz = /bits/ 64 <100000000>; 556 required-opps = <&rpmhpd_opp_svs>; 557 }; 558 559 opp-128000000 { 560 opp-hz = /bits/ 64 <128000000>; 561 required-opps = <&rpmhpd_opp_nom>; 562 }; 563 }; 564 565 soc: soc@0 { 566 #address-cells = <2>; 567 #size-cells = <2>; 568 ranges = <0 0 0 0 0x10 0>; 569 dma-ranges = <0 0 0 0 0x10 0>; 570 compatible = "simple-bus"; 571 572 gcc: clock-controller@100000 { 573 compatible = "qcom,gcc-sc7280"; 574 reg = <0 0x00100000 0 0x1f0000>; 575 clocks = <&rpmhcc RPMH_CXO_CLK>, 576 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 577 <0>, <0>, <0>, <0>, <0>, <0>; 578 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 579 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 580 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 581 "ufs_phy_tx_symbol_0_clk", 582 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 583 #clock-cells = <1>; 584 #reset-cells = <1>; 585 #power-domain-cells = <1>; 586 }; 587 588 ipcc: mailbox@408000 { 589 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 590 reg = <0 0x00408000 0 0x1000>; 591 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-controller; 593 #interrupt-cells = <3>; 594 #mbox-cells = <2>; 595 }; 596 597 qfprom: efuse@784000 { 598 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 599 reg = <0 0x00784000 0 0xa20>, 600 <0 0x00780000 0 0xa20>, 601 <0 0x00782000 0 0x120>, 602 <0 0x00786000 0 0x1fff>; 603 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 604 clock-names = "core"; 605 power-domains = <&rpmhpd SC7280_MX>; 606 #address-cells = <1>; 607 #size-cells = <1>; 608 }; 609 610 sdhc_1: sdhci@7c4000 { 611 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 612 status = "disabled"; 613 614 reg = <0 0x007c4000 0 0x1000>, 615 <0 0x007c5000 0 0x1000>; 616 reg-names = "hc", "cqhci"; 617 618 iommus = <&apps_smmu 0xc0 0x0>; 619 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "hc_irq", "pwr_irq"; 622 623 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 624 <&gcc GCC_SDCC1_AHB_CLK>, 625 <&rpmhcc RPMH_CXO_CLK>; 626 clock-names = "core", "iface", "xo"; 627 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 628 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 629 interconnect-names = "sdhc-ddr","cpu-sdhc"; 630 power-domains = <&rpmhpd SC7280_CX>; 631 operating-points-v2 = <&sdhc1_opp_table>; 632 633 bus-width = <8>; 634 supports-cqe; 635 636 qcom,dll-config = <0x0007642c>; 637 qcom,ddr-config = <0x80040868>; 638 639 mmc-ddr-1_8v; 640 mmc-hs200-1_8v; 641 mmc-hs400-1_8v; 642 mmc-hs400-enhanced-strobe; 643 644 sdhc1_opp_table: opp-table { 645 compatible = "operating-points-v2"; 646 647 opp-100000000 { 648 opp-hz = /bits/ 64 <100000000>; 649 required-opps = <&rpmhpd_opp_low_svs>; 650 opp-peak-kBps = <1800000 400000>; 651 opp-avg-kBps = <100000 0>; 652 }; 653 654 opp-384000000 { 655 opp-hz = /bits/ 64 <384000000>; 656 required-opps = <&rpmhpd_opp_nom>; 657 opp-peak-kBps = <5400000 1600000>; 658 opp-avg-kBps = <390000 0>; 659 }; 660 }; 661 662 }; 663 664 qupv3_id_0: geniqup@9c0000 { 665 compatible = "qcom,geni-se-qup"; 666 reg = <0 0x009c0000 0 0x2000>; 667 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 668 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 669 clock-names = "m-ahb", "s-ahb"; 670 #address-cells = <2>; 671 #size-cells = <2>; 672 ranges; 673 iommus = <&apps_smmu 0x123 0x0>; 674 status = "disabled"; 675 676 i2c0: i2c@980000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0 0x00980000 0 0x4000>; 679 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 680 clock-names = "se"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_i2c0_data_clk>; 683 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 687 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 688 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 689 interconnect-names = "qup-core", "qup-config", 690 "qup-memory"; 691 status = "disabled"; 692 }; 693 694 spi0: spi@980000 { 695 compatible = "qcom,geni-spi"; 696 reg = <0 0x00980000 0 0x4000>; 697 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 698 clock-names = "se"; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 701 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 power-domains = <&rpmhpd SC7280_CX>; 705 operating-points-v2 = <&qup_opp_table>; 706 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 707 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 708 interconnect-names = "qup-core", "qup-config"; 709 status = "disabled"; 710 }; 711 712 uart0: serial@980000 { 713 compatible = "qcom,geni-uart"; 714 reg = <0 0x00980000 0 0x4000>; 715 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 716 clock-names = "se"; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 719 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 720 power-domains = <&rpmhpd SC7280_CX>; 721 operating-points-v2 = <&qup_opp_table>; 722 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 723 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 724 interconnect-names = "qup-core", "qup-config"; 725 status = "disabled"; 726 }; 727 728 i2c1: i2c@984000 { 729 compatible = "qcom,geni-i2c"; 730 reg = <0 0x00984000 0 0x4000>; 731 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 732 clock-names = "se"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&qup_i2c1_data_clk>; 735 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 739 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 740 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 741 interconnect-names = "qup-core", "qup-config", 742 "qup-memory"; 743 status = "disabled"; 744 }; 745 746 spi1: spi@984000 { 747 compatible = "qcom,geni-spi"; 748 reg = <0 0x00984000 0 0x4000>; 749 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 750 clock-names = "se"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 753 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 power-domains = <&rpmhpd SC7280_CX>; 757 operating-points-v2 = <&qup_opp_table>; 758 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 760 interconnect-names = "qup-core", "qup-config"; 761 status = "disabled"; 762 }; 763 764 uart1: serial@984000 { 765 compatible = "qcom,geni-uart"; 766 reg = <0 0x00984000 0 0x4000>; 767 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 768 clock-names = "se"; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 771 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 772 power-domains = <&rpmhpd SC7280_CX>; 773 operating-points-v2 = <&qup_opp_table>; 774 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 775 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 776 interconnect-names = "qup-core", "qup-config"; 777 status = "disabled"; 778 }; 779 780 i2c2: i2c@988000 { 781 compatible = "qcom,geni-i2c"; 782 reg = <0 0x00988000 0 0x4000>; 783 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 784 clock-names = "se"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&qup_i2c2_data_clk>; 787 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 791 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 792 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 793 interconnect-names = "qup-core", "qup-config", 794 "qup-memory"; 795 status = "disabled"; 796 }; 797 798 spi2: spi@988000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0 0x00988000 0 0x4000>; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 802 clock-names = "se"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 805 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 power-domains = <&rpmhpd SC7280_CX>; 809 operating-points-v2 = <&qup_opp_table>; 810 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 811 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 812 interconnect-names = "qup-core", "qup-config"; 813 status = "disabled"; 814 }; 815 816 uart2: serial@988000 { 817 compatible = "qcom,geni-uart"; 818 reg = <0 0x00988000 0 0x4000>; 819 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 820 clock-names = "se"; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 823 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 824 power-domains = <&rpmhpd SC7280_CX>; 825 operating-points-v2 = <&qup_opp_table>; 826 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 828 interconnect-names = "qup-core", "qup-config"; 829 status = "disabled"; 830 }; 831 832 i2c3: i2c@98c000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x0098c000 0 0x4000>; 835 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 836 clock-names = "se"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c3_data_clk>; 839 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 843 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 844 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", 846 "qup-memory"; 847 status = "disabled"; 848 }; 849 850 spi3: spi@98c000 { 851 compatible = "qcom,geni-spi"; 852 reg = <0 0x0098c000 0 0x4000>; 853 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 854 clock-names = "se"; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 857 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 power-domains = <&rpmhpd SC7280_CX>; 861 operating-points-v2 = <&qup_opp_table>; 862 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 863 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 864 interconnect-names = "qup-core", "qup-config"; 865 status = "disabled"; 866 }; 867 868 uart3: serial@98c000 { 869 compatible = "qcom,geni-uart"; 870 reg = <0 0x0098c000 0 0x4000>; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 872 clock-names = "se"; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 875 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 876 power-domains = <&rpmhpd SC7280_CX>; 877 operating-points-v2 = <&qup_opp_table>; 878 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 879 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 880 interconnect-names = "qup-core", "qup-config"; 881 status = "disabled"; 882 }; 883 884 i2c4: i2c@990000 { 885 compatible = "qcom,geni-i2c"; 886 reg = <0 0x00990000 0 0x4000>; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 888 clock-names = "se"; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&qup_i2c4_data_clk>; 891 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 895 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 896 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 897 interconnect-names = "qup-core", "qup-config", 898 "qup-memory"; 899 status = "disabled"; 900 }; 901 902 spi4: spi@990000 { 903 compatible = "qcom,geni-spi"; 904 reg = <0 0x00990000 0 0x4000>; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 906 clock-names = "se"; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 909 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 power-domains = <&rpmhpd SC7280_CX>; 913 operating-points-v2 = <&qup_opp_table>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 915 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 status = "disabled"; 918 }; 919 920 uart4: serial@990000 { 921 compatible = "qcom,geni-uart"; 922 reg = <0 0x00990000 0 0x4000>; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 924 clock-names = "se"; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 927 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 928 power-domains = <&rpmhpd SC7280_CX>; 929 operating-points-v2 = <&qup_opp_table>; 930 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 931 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 932 interconnect-names = "qup-core", "qup-config"; 933 status = "disabled"; 934 }; 935 936 i2c5: i2c@994000 { 937 compatible = "qcom,geni-i2c"; 938 reg = <0 0x00994000 0 0x4000>; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 940 clock-names = "se"; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&qup_i2c5_data_clk>; 943 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 947 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 948 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 949 interconnect-names = "qup-core", "qup-config", 950 "qup-memory"; 951 status = "disabled"; 952 }; 953 954 spi5: spi@994000 { 955 compatible = "qcom,geni-spi"; 956 reg = <0 0x00994000 0 0x4000>; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 958 clock-names = "se"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 961 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 power-domains = <&rpmhpd SC7280_CX>; 965 operating-points-v2 = <&qup_opp_table>; 966 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 967 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 968 interconnect-names = "qup-core", "qup-config"; 969 status = "disabled"; 970 }; 971 972 uart5: serial@994000 { 973 compatible = "qcom,geni-uart"; 974 reg = <0 0x00994000 0 0x4000>; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 976 clock-names = "se"; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 979 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 980 power-domains = <&rpmhpd SC7280_CX>; 981 operating-points-v2 = <&qup_opp_table>; 982 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 983 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 984 interconnect-names = "qup-core", "qup-config"; 985 status = "disabled"; 986 }; 987 988 i2c6: i2c@998000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x00998000 0 0x4000>; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 992 clock-names = "se"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_i2c6_data_clk>; 995 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 999 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1000 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1001 interconnect-names = "qup-core", "qup-config", 1002 "qup-memory"; 1003 status = "disabled"; 1004 }; 1005 1006 spi6: spi@998000 { 1007 compatible = "qcom,geni-spi"; 1008 reg = <0 0x00998000 0 0x4000>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1010 clock-names = "se"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1013 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 power-domains = <&rpmhpd SC7280_CX>; 1017 operating-points-v2 = <&qup_opp_table>; 1018 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1019 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1020 interconnect-names = "qup-core", "qup-config"; 1021 status = "disabled"; 1022 }; 1023 1024 uart6: serial@998000 { 1025 compatible = "qcom,geni-uart"; 1026 reg = <0 0x00998000 0 0x4000>; 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1028 clock-names = "se"; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1031 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1032 power-domains = <&rpmhpd SC7280_CX>; 1033 operating-points-v2 = <&qup_opp_table>; 1034 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1036 interconnect-names = "qup-core", "qup-config"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c7: i2c@99c000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0 0x0099c000 0 0x4000>; 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1044 clock-names = "se"; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c7_data_clk>; 1047 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1052 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1053 interconnect-names = "qup-core", "qup-config", 1054 "qup-memory"; 1055 status = "disabled"; 1056 }; 1057 1058 spi7: spi@99c000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x0099c000 0 0x4000>; 1061 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1062 clock-names = "se"; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1065 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 power-domains = <&rpmhpd SC7280_CX>; 1069 operating-points-v2 = <&qup_opp_table>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1071 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1072 interconnect-names = "qup-core", "qup-config"; 1073 status = "disabled"; 1074 }; 1075 1076 uart7: serial@99c000 { 1077 compatible = "qcom,geni-uart"; 1078 reg = <0 0x0099c000 0 0x4000>; 1079 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1080 clock-names = "se"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1083 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1084 power-domains = <&rpmhpd SC7280_CX>; 1085 operating-points-v2 = <&qup_opp_table>; 1086 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1087 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1088 interconnect-names = "qup-core", "qup-config"; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 qupv3_id_1: geniqup@ac0000 { 1094 compatible = "qcom,geni-se-qup"; 1095 reg = <0 0x00ac0000 0 0x2000>; 1096 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1097 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1098 clock-names = "m-ahb", "s-ahb"; 1099 #address-cells = <2>; 1100 #size-cells = <2>; 1101 ranges; 1102 iommus = <&apps_smmu 0x43 0x0>; 1103 status = "disabled"; 1104 1105 i2c8: i2c@a80000 { 1106 compatible = "qcom,geni-i2c"; 1107 reg = <0 0x00a80000 0 0x4000>; 1108 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1109 clock-names = "se"; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_i2c8_data_clk>; 1112 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1117 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1118 interconnect-names = "qup-core", "qup-config", 1119 "qup-memory"; 1120 status = "disabled"; 1121 }; 1122 1123 spi8: spi@a80000 { 1124 compatible = "qcom,geni-spi"; 1125 reg = <0 0x00a80000 0 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1127 clock-names = "se"; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1130 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 power-domains = <&rpmhpd SC7280_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1136 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1137 interconnect-names = "qup-core", "qup-config"; 1138 status = "disabled"; 1139 }; 1140 1141 uart8: serial@a80000 { 1142 compatible = "qcom,geni-uart"; 1143 reg = <0 0x00a80000 0 0x4000>; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1145 clock-names = "se"; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1148 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1149 power-domains = <&rpmhpd SC7280_CX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1152 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1153 interconnect-names = "qup-core", "qup-config"; 1154 status = "disabled"; 1155 }; 1156 1157 i2c9: i2c@a84000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x00a84000 0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1161 clock-names = "se"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c9_data_clk>; 1164 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1169 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1170 interconnect-names = "qup-core", "qup-config", 1171 "qup-memory"; 1172 status = "disabled"; 1173 }; 1174 1175 spi9: spi@a84000 { 1176 compatible = "qcom,geni-spi"; 1177 reg = <0 0x00a84000 0 0x4000>; 1178 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1179 clock-names = "se"; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1182 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 power-domains = <&rpmhpd SC7280_CX>; 1186 operating-points-v2 = <&qup_opp_table>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1188 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1189 interconnect-names = "qup-core", "qup-config"; 1190 status = "disabled"; 1191 }; 1192 1193 uart9: serial@a84000 { 1194 compatible = "qcom,geni-uart"; 1195 reg = <0 0x00a84000 0 0x4000>; 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1197 clock-names = "se"; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1201 power-domains = <&rpmhpd SC7280_CX>; 1202 operating-points-v2 = <&qup_opp_table>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1205 interconnect-names = "qup-core", "qup-config"; 1206 status = "disabled"; 1207 }; 1208 1209 i2c10: i2c@a88000 { 1210 compatible = "qcom,geni-i2c"; 1211 reg = <0 0x00a88000 0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1213 clock-names = "se"; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_i2c10_data_clk>; 1216 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1221 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1222 interconnect-names = "qup-core", "qup-config", 1223 "qup-memory"; 1224 status = "disabled"; 1225 }; 1226 1227 spi10: spi@a88000 { 1228 compatible = "qcom,geni-spi"; 1229 reg = <0 0x00a88000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1234 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 power-domains = <&rpmhpd SC7280_CX>; 1238 operating-points-v2 = <&qup_opp_table>; 1239 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1240 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1241 interconnect-names = "qup-core", "qup-config"; 1242 status = "disabled"; 1243 }; 1244 1245 uart10: serial@a88000 { 1246 compatible = "qcom,geni-uart"; 1247 reg = <0 0x00a88000 0 0x4000>; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1249 clock-names = "se"; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1252 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1253 power-domains = <&rpmhpd SC7280_CX>; 1254 operating-points-v2 = <&qup_opp_table>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1256 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1257 interconnect-names = "qup-core", "qup-config"; 1258 status = "disabled"; 1259 }; 1260 1261 i2c11: i2c@a8c000 { 1262 compatible = "qcom,geni-i2c"; 1263 reg = <0 0x00a8c000 0 0x4000>; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1265 clock-names = "se"; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_i2c11_data_clk>; 1268 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1272 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1273 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1274 interconnect-names = "qup-core", "qup-config", 1275 "qup-memory"; 1276 status = "disabled"; 1277 }; 1278 1279 spi11: spi@a8c000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x00a8c000 0 0x4000>; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1283 clock-names = "se"; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1286 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 power-domains = <&rpmhpd SC7280_CX>; 1290 operating-points-v2 = <&qup_opp_table>; 1291 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1292 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1293 interconnect-names = "qup-core", "qup-config"; 1294 status = "disabled"; 1295 }; 1296 1297 uart11: serial@a8c000 { 1298 compatible = "qcom,geni-uart"; 1299 reg = <0 0x00a8c000 0 0x4000>; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1301 clock-names = "se"; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1304 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1305 power-domains = <&rpmhpd SC7280_CX>; 1306 operating-points-v2 = <&qup_opp_table>; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1308 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c12: i2c@a90000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x00a90000 0 0x4000>; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1317 clock-names = "se"; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_i2c12_data_clk>; 1320 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1325 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1326 interconnect-names = "qup-core", "qup-config", 1327 "qup-memory"; 1328 status = "disabled"; 1329 }; 1330 1331 spi12: spi@a90000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0 0x00a90000 0 0x4000>; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1335 clock-names = "se"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1338 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 power-domains = <&rpmhpd SC7280_CX>; 1342 operating-points-v2 = <&qup_opp_table>; 1343 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1344 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1345 interconnect-names = "qup-core", "qup-config"; 1346 status = "disabled"; 1347 }; 1348 1349 uart12: serial@a90000 { 1350 compatible = "qcom,geni-uart"; 1351 reg = <0 0x00a90000 0 0x4000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1353 clock-names = "se"; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1356 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1357 power-domains = <&rpmhpd SC7280_CX>; 1358 operating-points-v2 = <&qup_opp_table>; 1359 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1360 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1361 interconnect-names = "qup-core", "qup-config"; 1362 status = "disabled"; 1363 }; 1364 1365 i2c13: i2c@a94000 { 1366 compatible = "qcom,geni-i2c"; 1367 reg = <0 0x00a94000 0 0x4000>; 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1369 clock-names = "se"; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_i2c13_data_clk>; 1372 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1376 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1377 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1378 interconnect-names = "qup-core", "qup-config", 1379 "qup-memory"; 1380 status = "disabled"; 1381 }; 1382 1383 spi13: spi@a94000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0 0x00a94000 0 0x4000>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1387 clock-names = "se"; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1390 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 power-domains = <&rpmhpd SC7280_CX>; 1394 operating-points-v2 = <&qup_opp_table>; 1395 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1396 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1397 interconnect-names = "qup-core", "qup-config"; 1398 status = "disabled"; 1399 }; 1400 1401 uart13: serial@a94000 { 1402 compatible = "qcom,geni-uart"; 1403 reg = <0 0x00a94000 0 0x4000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1405 clock-names = "se"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1408 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC7280_CX>; 1410 operating-points-v2 = <&qup_opp_table>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1413 interconnect-names = "qup-core", "qup-config"; 1414 status = "disabled"; 1415 }; 1416 1417 i2c14: i2c@a98000 { 1418 compatible = "qcom,geni-i2c"; 1419 reg = <0 0x00a98000 0 0x4000>; 1420 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1421 clock-names = "se"; 1422 pinctrl-names = "default"; 1423 pinctrl-0 = <&qup_i2c14_data_clk>; 1424 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1428 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1429 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1430 interconnect-names = "qup-core", "qup-config", 1431 "qup-memory"; 1432 status = "disabled"; 1433 }; 1434 1435 spi14: spi@a98000 { 1436 compatible = "qcom,geni-spi"; 1437 reg = <0 0x00a98000 0 0x4000>; 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1439 clock-names = "se"; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1442 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 power-domains = <&rpmhpd SC7280_CX>; 1446 operating-points-v2 = <&qup_opp_table>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 status = "disabled"; 1451 }; 1452 1453 uart14: serial@a98000 { 1454 compatible = "qcom,geni-uart"; 1455 reg = <0 0x00a98000 0 0x4000>; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1457 clock-names = "se"; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1460 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1461 power-domains = <&rpmhpd SC7280_CX>; 1462 operating-points-v2 = <&qup_opp_table>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1465 interconnect-names = "qup-core", "qup-config"; 1466 status = "disabled"; 1467 }; 1468 1469 i2c15: i2c@a9c000 { 1470 compatible = "qcom,geni-i2c"; 1471 reg = <0 0x00a9c000 0 0x4000>; 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1473 clock-names = "se"; 1474 pinctrl-names = "default"; 1475 pinctrl-0 = <&qup_i2c15_data_clk>; 1476 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1481 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", 1483 "qup-memory"; 1484 status = "disabled"; 1485 }; 1486 1487 spi15: spi@a9c000 { 1488 compatible = "qcom,geni-spi"; 1489 reg = <0 0x00a9c000 0 0x4000>; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1491 clock-names = "se"; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1494 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 power-domains = <&rpmhpd SC7280_CX>; 1498 operating-points-v2 = <&qup_opp_table>; 1499 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1500 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1501 interconnect-names = "qup-core", "qup-config"; 1502 status = "disabled"; 1503 }; 1504 1505 uart15: serial@a9c000 { 1506 compatible = "qcom,geni-uart"; 1507 reg = <0 0x00a9c000 0 0x4000>; 1508 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1509 clock-names = "se"; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1512 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1513 power-domains = <&rpmhpd SC7280_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1516 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1517 interconnect-names = "qup-core", "qup-config"; 1518 status = "disabled"; 1519 }; 1520 }; 1521 1522 cnoc2: interconnect@1500000 { 1523 reg = <0 0x01500000 0 0x1000>; 1524 compatible = "qcom,sc7280-cnoc2"; 1525 #interconnect-cells = <2>; 1526 qcom,bcm-voters = <&apps_bcm_voter>; 1527 }; 1528 1529 cnoc3: interconnect@1502000 { 1530 reg = <0 0x01502000 0 0x1000>; 1531 compatible = "qcom,sc7280-cnoc3"; 1532 #interconnect-cells = <2>; 1533 qcom,bcm-voters = <&apps_bcm_voter>; 1534 }; 1535 1536 mc_virt: interconnect@1580000 { 1537 reg = <0 0x01580000 0 0x4>; 1538 compatible = "qcom,sc7280-mc-virt"; 1539 #interconnect-cells = <2>; 1540 qcom,bcm-voters = <&apps_bcm_voter>; 1541 }; 1542 1543 system_noc: interconnect@1680000 { 1544 reg = <0 0x01680000 0 0x15480>; 1545 compatible = "qcom,sc7280-system-noc"; 1546 #interconnect-cells = <2>; 1547 qcom,bcm-voters = <&apps_bcm_voter>; 1548 }; 1549 1550 aggre1_noc: interconnect@16e0000 { 1551 compatible = "qcom,sc7280-aggre1-noc"; 1552 reg = <0 0x016e0000 0 0x1c080>; 1553 #interconnect-cells = <2>; 1554 qcom,bcm-voters = <&apps_bcm_voter>; 1555 }; 1556 1557 aggre2_noc: interconnect@1700000 { 1558 reg = <0 0x01700000 0 0x2b080>; 1559 compatible = "qcom,sc7280-aggre2-noc"; 1560 #interconnect-cells = <2>; 1561 qcom,bcm-voters = <&apps_bcm_voter>; 1562 }; 1563 1564 mmss_noc: interconnect@1740000 { 1565 reg = <0 0x01740000 0 0x1e080>; 1566 compatible = "qcom,sc7280-mmss-noc"; 1567 #interconnect-cells = <2>; 1568 qcom,bcm-voters = <&apps_bcm_voter>; 1569 }; 1570 1571 ipa: ipa@1e40000 { 1572 compatible = "qcom,sc7280-ipa"; 1573 1574 iommus = <&apps_smmu 0x480 0x0>, 1575 <&apps_smmu 0x482 0x0>; 1576 reg = <0 0x1e40000 0 0x8000>, 1577 <0 0x1e50000 0 0x4ad0>, 1578 <0 0x1e04000 0 0x23000>; 1579 reg-names = "ipa-reg", 1580 "ipa-shared", 1581 "gsi"; 1582 1583 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 1584 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1585 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1586 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1587 interrupt-names = "ipa", 1588 "gsi", 1589 "ipa-clock-query", 1590 "ipa-setup-ready"; 1591 1592 clocks = <&rpmhcc RPMH_IPA_CLK>; 1593 clock-names = "core"; 1594 1595 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1596 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 1597 interconnect-names = "memory", 1598 "config"; 1599 1600 qcom,smem-states = <&ipa_smp2p_out 0>, 1601 <&ipa_smp2p_out 1>; 1602 qcom,smem-state-names = "ipa-clock-enabled-valid", 1603 "ipa-clock-enabled"; 1604 1605 status = "disabled"; 1606 }; 1607 1608 tcsr_mutex: hwlock@1f40000 { 1609 compatible = "qcom,tcsr-mutex", "syscon"; 1610 reg = <0 0x01f40000 0 0x40000>; 1611 #hwlock-cells = <1>; 1612 }; 1613 1614 tcsr: syscon@1fc0000 { 1615 compatible = "qcom,sc7280-tcsr", "syscon"; 1616 reg = <0 0x01fc0000 0 0x30000>; 1617 }; 1618 1619 lpasscc: lpasscc@3000000 { 1620 compatible = "qcom,sc7280-lpasscc"; 1621 reg = <0 0x03000000 0 0x40>, 1622 <0 0x03c04000 0 0x4>, 1623 <0 0x03389000 0 0x24>; 1624 reg-names = "qdsp6ss", "top_cc", "cc"; 1625 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 1626 clock-names = "iface"; 1627 #clock-cells = <1>; 1628 }; 1629 1630 lpass_ag_noc: interconnect@3c40000 { 1631 reg = <0 0x03c40000 0 0xf080>; 1632 compatible = "qcom,sc7280-lpass-ag-noc"; 1633 #interconnect-cells = <2>; 1634 qcom,bcm-voters = <&apps_bcm_voter>; 1635 }; 1636 1637 gpu: gpu@3d00000 { 1638 compatible = "qcom,adreno-635.0", "qcom,adreno"; 1639 #stream-id-cells = <16>; 1640 reg = <0 0x03d00000 0 0x40000>, 1641 <0 0x03d9e000 0 0x1000>, 1642 <0 0x03d61000 0 0x800>; 1643 reg-names = "kgsl_3d0_reg_memory", 1644 "cx_mem", 1645 "cx_dbgc"; 1646 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1647 iommus = <&adreno_smmu 0 0x401>; 1648 operating-points-v2 = <&gpu_opp_table>; 1649 qcom,gmu = <&gmu>; 1650 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1651 interconnect-names = "gfx-mem"; 1652 #cooling-cells = <2>; 1653 1654 gpu_opp_table: opp-table { 1655 compatible = "operating-points-v2"; 1656 1657 opp-315000000 { 1658 opp-hz = /bits/ 64 <315000000>; 1659 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1660 opp-peak-kBps = <1804000>; 1661 }; 1662 1663 opp-450000000 { 1664 opp-hz = /bits/ 64 <450000000>; 1665 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1666 opp-peak-kBps = <4068000>; 1667 }; 1668 1669 opp-550000000 { 1670 opp-hz = /bits/ 64 <550000000>; 1671 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1672 opp-peak-kBps = <6832000>; 1673 }; 1674 }; 1675 }; 1676 1677 gmu: gmu@3d69000 { 1678 compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 1679 reg = <0 0x03d6a000 0 0x34000>, 1680 <0 0x3de0000 0 0x10000>, 1681 <0 0x0b290000 0 0x10000>; 1682 reg-names = "gmu", "rscc", "gmu_pdc"; 1683 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1685 interrupt-names = "hfi", "gmu"; 1686 clocks = <&gpucc 5>, 1687 <&gpucc 8>, 1688 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1689 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1690 <&gpucc 2>, 1691 <&gpucc 15>, 1692 <&gpucc 11>; 1693 clock-names = "gmu", 1694 "cxo", 1695 "axi", 1696 "memnoc", 1697 "ahb", 1698 "hub", 1699 "smmu_vote"; 1700 power-domains = <&gpucc 0>, 1701 <&gpucc 1>; 1702 power-domain-names = "cx", 1703 "gx"; 1704 iommus = <&adreno_smmu 5 0x400>; 1705 operating-points-v2 = <&gmu_opp_table>; 1706 1707 gmu_opp_table: opp-table { 1708 compatible = "operating-points-v2"; 1709 1710 opp-200000000 { 1711 opp-hz = /bits/ 64 <200000000>; 1712 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1713 }; 1714 }; 1715 }; 1716 1717 gpucc: clock-controller@3d90000 { 1718 compatible = "qcom,sc7280-gpucc"; 1719 reg = <0 0x03d90000 0 0x9000>; 1720 clocks = <&rpmhcc RPMH_CXO_CLK>, 1721 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1722 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1723 clock-names = "bi_tcxo", 1724 "gcc_gpu_gpll0_clk_src", 1725 "gcc_gpu_gpll0_div_clk_src"; 1726 #clock-cells = <1>; 1727 #reset-cells = <1>; 1728 #power-domain-cells = <1>; 1729 }; 1730 1731 adreno_smmu: iommu@3da0000 { 1732 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 1733 reg = <0 0x03da0000 0 0x20000>; 1734 #iommu-cells = <2>; 1735 #global-interrupts = <2>; 1736 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1748 1749 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1750 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1751 <&gpucc 2>, 1752 <&gpucc 11>, 1753 <&gpucc 5>, 1754 <&gpucc 15>, 1755 <&gpucc 13>; 1756 clock-names = "gcc_gpu_memnoc_gfx_clk", 1757 "gcc_gpu_snoc_dvm_gfx_clk", 1758 "gpu_cc_ahb_clk", 1759 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1760 "gpu_cc_cx_gmu_clk", 1761 "gpu_cc_hub_cx_int_clk", 1762 "gpu_cc_hub_aon_clk"; 1763 1764 power-domains = <&gpucc 0>; 1765 }; 1766 1767 remoteproc_mpss: remoteproc@4080000 { 1768 compatible = "qcom,sc7280-mpss-pas"; 1769 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 1770 reg-names = "qdsp6", "rmb"; 1771 1772 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1773 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1774 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1775 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1776 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1777 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1778 interrupt-names = "wdog", "fatal", "ready", "handover", 1779 "stop-ack", "shutdown-ack"; 1780 1781 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1782 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 1783 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1784 <&rpmhcc RPMH_PKA_CLK>, 1785 <&rpmhcc RPMH_CXO_CLK>; 1786 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 1787 1788 power-domains = <&rpmhpd SC7280_CX>, 1789 <&rpmhpd SC7280_MSS>; 1790 power-domain-names = "cx", "mss"; 1791 1792 memory-region = <&mpss_mem>; 1793 1794 qcom,qmp = <&aoss_qmp>; 1795 1796 qcom,smem-states = <&modem_smp2p_out 0>; 1797 qcom,smem-state-names = "stop"; 1798 1799 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1800 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1801 reset-names = "mss_restart", "pdc_reset"; 1802 1803 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; 1804 qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; 1805 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; 1806 1807 status = "disabled"; 1808 1809 glink-edge { 1810 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1811 IPCC_MPROC_SIGNAL_GLINK_QMP 1812 IRQ_TYPE_EDGE_RISING>; 1813 mboxes = <&ipcc IPCC_CLIENT_MPSS 1814 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1815 label = "modem"; 1816 qcom,remote-pid = <1>; 1817 }; 1818 }; 1819 1820 stm@6002000 { 1821 compatible = "arm,coresight-stm", "arm,primecell"; 1822 reg = <0 0x06002000 0 0x1000>, 1823 <0 0x16280000 0 0x180000>; 1824 reg-names = "stm-base", "stm-stimulus-base"; 1825 1826 clocks = <&aoss_qmp>; 1827 clock-names = "apb_pclk"; 1828 1829 out-ports { 1830 port { 1831 stm_out: endpoint { 1832 remote-endpoint = <&funnel0_in7>; 1833 }; 1834 }; 1835 }; 1836 }; 1837 1838 funnel@6041000 { 1839 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1840 reg = <0 0x06041000 0 0x1000>; 1841 1842 clocks = <&aoss_qmp>; 1843 clock-names = "apb_pclk"; 1844 1845 out-ports { 1846 port { 1847 funnel0_out: endpoint { 1848 remote-endpoint = <&merge_funnel_in0>; 1849 }; 1850 }; 1851 }; 1852 1853 in-ports { 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 1857 port@7 { 1858 reg = <7>; 1859 funnel0_in7: endpoint { 1860 remote-endpoint = <&stm_out>; 1861 }; 1862 }; 1863 }; 1864 }; 1865 1866 funnel@6042000 { 1867 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1868 reg = <0 0x06042000 0 0x1000>; 1869 1870 clocks = <&aoss_qmp>; 1871 clock-names = "apb_pclk"; 1872 1873 out-ports { 1874 port { 1875 funnel1_out: endpoint { 1876 remote-endpoint = <&merge_funnel_in1>; 1877 }; 1878 }; 1879 }; 1880 1881 in-ports { 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 1885 port@4 { 1886 reg = <4>; 1887 funnel1_in4: endpoint { 1888 remote-endpoint = <&apss_merge_funnel_out>; 1889 }; 1890 }; 1891 }; 1892 }; 1893 1894 funnel@6045000 { 1895 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1896 reg = <0 0x06045000 0 0x1000>; 1897 1898 clocks = <&aoss_qmp>; 1899 clock-names = "apb_pclk"; 1900 1901 out-ports { 1902 port { 1903 merge_funnel_out: endpoint { 1904 remote-endpoint = <&swao_funnel_in>; 1905 }; 1906 }; 1907 }; 1908 1909 in-ports { 1910 #address-cells = <1>; 1911 #size-cells = <0>; 1912 1913 port@0 { 1914 reg = <0>; 1915 merge_funnel_in0: endpoint { 1916 remote-endpoint = <&funnel0_out>; 1917 }; 1918 }; 1919 1920 port@1 { 1921 reg = <1>; 1922 merge_funnel_in1: endpoint { 1923 remote-endpoint = <&funnel1_out>; 1924 }; 1925 }; 1926 }; 1927 }; 1928 1929 replicator@6046000 { 1930 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1931 reg = <0 0x06046000 0 0x1000>; 1932 1933 clocks = <&aoss_qmp>; 1934 clock-names = "apb_pclk"; 1935 1936 out-ports { 1937 port { 1938 replicator_out: endpoint { 1939 remote-endpoint = <&etr_in>; 1940 }; 1941 }; 1942 }; 1943 1944 in-ports { 1945 port { 1946 replicator_in: endpoint { 1947 remote-endpoint = <&swao_replicator_out>; 1948 }; 1949 }; 1950 }; 1951 }; 1952 1953 etr@6048000 { 1954 compatible = "arm,coresight-tmc", "arm,primecell"; 1955 reg = <0 0x06048000 0 0x1000>; 1956 iommus = <&apps_smmu 0x04c0 0>; 1957 1958 clocks = <&aoss_qmp>; 1959 clock-names = "apb_pclk"; 1960 arm,scatter-gather; 1961 1962 in-ports { 1963 port { 1964 etr_in: endpoint { 1965 remote-endpoint = <&replicator_out>; 1966 }; 1967 }; 1968 }; 1969 }; 1970 1971 funnel@6b04000 { 1972 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1973 reg = <0 0x06b04000 0 0x1000>; 1974 1975 clocks = <&aoss_qmp>; 1976 clock-names = "apb_pclk"; 1977 1978 out-ports { 1979 port { 1980 swao_funnel_out: endpoint { 1981 remote-endpoint = <&etf_in>; 1982 }; 1983 }; 1984 }; 1985 1986 in-ports { 1987 #address-cells = <1>; 1988 #size-cells = <0>; 1989 1990 port@7 { 1991 reg = <7>; 1992 swao_funnel_in: endpoint { 1993 remote-endpoint = <&merge_funnel_out>; 1994 }; 1995 }; 1996 }; 1997 }; 1998 1999 etf@6b05000 { 2000 compatible = "arm,coresight-tmc", "arm,primecell"; 2001 reg = <0 0x06b05000 0 0x1000>; 2002 2003 clocks = <&aoss_qmp>; 2004 clock-names = "apb_pclk"; 2005 2006 out-ports { 2007 port { 2008 etf_out: endpoint { 2009 remote-endpoint = <&swao_replicator_in>; 2010 }; 2011 }; 2012 }; 2013 2014 in-ports { 2015 port { 2016 etf_in: endpoint { 2017 remote-endpoint = <&swao_funnel_out>; 2018 }; 2019 }; 2020 }; 2021 }; 2022 2023 replicator@6b06000 { 2024 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2025 reg = <0 0x06b06000 0 0x1000>; 2026 2027 clocks = <&aoss_qmp>; 2028 clock-names = "apb_pclk"; 2029 qcom,replicator-loses-context; 2030 2031 out-ports { 2032 port { 2033 swao_replicator_out: endpoint { 2034 remote-endpoint = <&replicator_in>; 2035 }; 2036 }; 2037 }; 2038 2039 in-ports { 2040 port { 2041 swao_replicator_in: endpoint { 2042 remote-endpoint = <&etf_out>; 2043 }; 2044 }; 2045 }; 2046 }; 2047 2048 etm@7040000 { 2049 compatible = "arm,coresight-etm4x", "arm,primecell"; 2050 reg = <0 0x07040000 0 0x1000>; 2051 2052 cpu = <&CPU0>; 2053 2054 clocks = <&aoss_qmp>; 2055 clock-names = "apb_pclk"; 2056 arm,coresight-loses-context-with-cpu; 2057 qcom,skip-power-up; 2058 2059 out-ports { 2060 port { 2061 etm0_out: endpoint { 2062 remote-endpoint = <&apss_funnel_in0>; 2063 }; 2064 }; 2065 }; 2066 }; 2067 2068 etm@7140000 { 2069 compatible = "arm,coresight-etm4x", "arm,primecell"; 2070 reg = <0 0x07140000 0 0x1000>; 2071 2072 cpu = <&CPU1>; 2073 2074 clocks = <&aoss_qmp>; 2075 clock-names = "apb_pclk"; 2076 arm,coresight-loses-context-with-cpu; 2077 qcom,skip-power-up; 2078 2079 out-ports { 2080 port { 2081 etm1_out: endpoint { 2082 remote-endpoint = <&apss_funnel_in1>; 2083 }; 2084 }; 2085 }; 2086 }; 2087 2088 etm@7240000 { 2089 compatible = "arm,coresight-etm4x", "arm,primecell"; 2090 reg = <0 0x07240000 0 0x1000>; 2091 2092 cpu = <&CPU2>; 2093 2094 clocks = <&aoss_qmp>; 2095 clock-names = "apb_pclk"; 2096 arm,coresight-loses-context-with-cpu; 2097 qcom,skip-power-up; 2098 2099 out-ports { 2100 port { 2101 etm2_out: endpoint { 2102 remote-endpoint = <&apss_funnel_in2>; 2103 }; 2104 }; 2105 }; 2106 }; 2107 2108 etm@7340000 { 2109 compatible = "arm,coresight-etm4x", "arm,primecell"; 2110 reg = <0 0x07340000 0 0x1000>; 2111 2112 cpu = <&CPU3>; 2113 2114 clocks = <&aoss_qmp>; 2115 clock-names = "apb_pclk"; 2116 arm,coresight-loses-context-with-cpu; 2117 qcom,skip-power-up; 2118 2119 out-ports { 2120 port { 2121 etm3_out: endpoint { 2122 remote-endpoint = <&apss_funnel_in3>; 2123 }; 2124 }; 2125 }; 2126 }; 2127 2128 etm@7440000 { 2129 compatible = "arm,coresight-etm4x", "arm,primecell"; 2130 reg = <0 0x07440000 0 0x1000>; 2131 2132 cpu = <&CPU4>; 2133 2134 clocks = <&aoss_qmp>; 2135 clock-names = "apb_pclk"; 2136 arm,coresight-loses-context-with-cpu; 2137 qcom,skip-power-up; 2138 2139 out-ports { 2140 port { 2141 etm4_out: endpoint { 2142 remote-endpoint = <&apss_funnel_in4>; 2143 }; 2144 }; 2145 }; 2146 }; 2147 2148 etm@7540000 { 2149 compatible = "arm,coresight-etm4x", "arm,primecell"; 2150 reg = <0 0x07540000 0 0x1000>; 2151 2152 cpu = <&CPU5>; 2153 2154 clocks = <&aoss_qmp>; 2155 clock-names = "apb_pclk"; 2156 arm,coresight-loses-context-with-cpu; 2157 qcom,skip-power-up; 2158 2159 out-ports { 2160 port { 2161 etm5_out: endpoint { 2162 remote-endpoint = <&apss_funnel_in5>; 2163 }; 2164 }; 2165 }; 2166 }; 2167 2168 etm@7640000 { 2169 compatible = "arm,coresight-etm4x", "arm,primecell"; 2170 reg = <0 0x07640000 0 0x1000>; 2171 2172 cpu = <&CPU6>; 2173 2174 clocks = <&aoss_qmp>; 2175 clock-names = "apb_pclk"; 2176 arm,coresight-loses-context-with-cpu; 2177 qcom,skip-power-up; 2178 2179 out-ports { 2180 port { 2181 etm6_out: endpoint { 2182 remote-endpoint = <&apss_funnel_in6>; 2183 }; 2184 }; 2185 }; 2186 }; 2187 2188 etm@7740000 { 2189 compatible = "arm,coresight-etm4x", "arm,primecell"; 2190 reg = <0 0x07740000 0 0x1000>; 2191 2192 cpu = <&CPU7>; 2193 2194 clocks = <&aoss_qmp>; 2195 clock-names = "apb_pclk"; 2196 arm,coresight-loses-context-with-cpu; 2197 qcom,skip-power-up; 2198 2199 out-ports { 2200 port { 2201 etm7_out: endpoint { 2202 remote-endpoint = <&apss_funnel_in7>; 2203 }; 2204 }; 2205 }; 2206 }; 2207 2208 funnel@7800000 { /* APSS Funnel */ 2209 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2210 reg = <0 0x07800000 0 0x1000>; 2211 2212 clocks = <&aoss_qmp>; 2213 clock-names = "apb_pclk"; 2214 2215 out-ports { 2216 port { 2217 apss_funnel_out: endpoint { 2218 remote-endpoint = <&apss_merge_funnel_in>; 2219 }; 2220 }; 2221 }; 2222 2223 in-ports { 2224 #address-cells = <1>; 2225 #size-cells = <0>; 2226 2227 port@0 { 2228 reg = <0>; 2229 apss_funnel_in0: endpoint { 2230 remote-endpoint = <&etm0_out>; 2231 }; 2232 }; 2233 2234 port@1 { 2235 reg = <1>; 2236 apss_funnel_in1: endpoint { 2237 remote-endpoint = <&etm1_out>; 2238 }; 2239 }; 2240 2241 port@2 { 2242 reg = <2>; 2243 apss_funnel_in2: endpoint { 2244 remote-endpoint = <&etm2_out>; 2245 }; 2246 }; 2247 2248 port@3 { 2249 reg = <3>; 2250 apss_funnel_in3: endpoint { 2251 remote-endpoint = <&etm3_out>; 2252 }; 2253 }; 2254 2255 port@4 { 2256 reg = <4>; 2257 apss_funnel_in4: endpoint { 2258 remote-endpoint = <&etm4_out>; 2259 }; 2260 }; 2261 2262 port@5 { 2263 reg = <5>; 2264 apss_funnel_in5: endpoint { 2265 remote-endpoint = <&etm5_out>; 2266 }; 2267 }; 2268 2269 port@6 { 2270 reg = <6>; 2271 apss_funnel_in6: endpoint { 2272 remote-endpoint = <&etm6_out>; 2273 }; 2274 }; 2275 2276 port@7 { 2277 reg = <7>; 2278 apss_funnel_in7: endpoint { 2279 remote-endpoint = <&etm7_out>; 2280 }; 2281 }; 2282 }; 2283 }; 2284 2285 funnel@7810000 { 2286 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2287 reg = <0 0x07810000 0 0x1000>; 2288 2289 clocks = <&aoss_qmp>; 2290 clock-names = "apb_pclk"; 2291 2292 out-ports { 2293 port { 2294 apss_merge_funnel_out: endpoint { 2295 remote-endpoint = <&funnel1_in4>; 2296 }; 2297 }; 2298 }; 2299 2300 in-ports { 2301 port { 2302 apss_merge_funnel_in: endpoint { 2303 remote-endpoint = <&apss_funnel_out>; 2304 }; 2305 }; 2306 }; 2307 }; 2308 2309 sdhc_2: sdhci@8804000 { 2310 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 2311 status = "disabled"; 2312 2313 reg = <0 0x08804000 0 0x1000>; 2314 2315 iommus = <&apps_smmu 0x100 0x0>; 2316 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2317 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2318 interrupt-names = "hc_irq", "pwr_irq"; 2319 2320 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2321 <&gcc GCC_SDCC2_AHB_CLK>, 2322 <&rpmhcc RPMH_CXO_CLK>; 2323 clock-names = "core", "iface", "xo"; 2324 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2325 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 2326 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2327 power-domains = <&rpmhpd SC7280_CX>; 2328 operating-points-v2 = <&sdhc2_opp_table>; 2329 2330 bus-width = <4>; 2331 2332 qcom,dll-config = <0x0007642c>; 2333 2334 sdhc2_opp_table: opp-table { 2335 compatible = "operating-points-v2"; 2336 2337 opp-100000000 { 2338 opp-hz = /bits/ 64 <100000000>; 2339 required-opps = <&rpmhpd_opp_low_svs>; 2340 opp-peak-kBps = <1800000 400000>; 2341 opp-avg-kBps = <100000 0>; 2342 }; 2343 2344 opp-202000000 { 2345 opp-hz = /bits/ 64 <202000000>; 2346 required-opps = <&rpmhpd_opp_nom>; 2347 opp-peak-kBps = <5400000 1600000>; 2348 opp-avg-kBps = <200000 0>; 2349 }; 2350 }; 2351 2352 }; 2353 2354 usb_1_hsphy: phy@88e3000 { 2355 compatible = "qcom,sc7280-usb-hs-phy", 2356 "qcom,usb-snps-hs-7nm-phy"; 2357 reg = <0 0x088e3000 0 0x400>; 2358 status = "disabled"; 2359 #phy-cells = <0>; 2360 2361 clocks = <&rpmhcc RPMH_CXO_CLK>; 2362 clock-names = "ref"; 2363 2364 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2365 }; 2366 2367 usb_2_hsphy: phy@88e4000 { 2368 compatible = "qcom,sc7280-usb-hs-phy", 2369 "qcom,usb-snps-hs-7nm-phy"; 2370 reg = <0 0x088e4000 0 0x400>; 2371 status = "disabled"; 2372 #phy-cells = <0>; 2373 2374 clocks = <&rpmhcc RPMH_CXO_CLK>; 2375 clock-names = "ref"; 2376 2377 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2378 }; 2379 2380 usb_1_qmpphy: phy-wrapper@88e9000 { 2381 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 2382 "qcom,sm8250-qmp-usb3-dp-phy"; 2383 reg = <0 0x088e9000 0 0x200>, 2384 <0 0x088e8000 0 0x40>, 2385 <0 0x088ea000 0 0x200>; 2386 status = "disabled"; 2387 #address-cells = <2>; 2388 #size-cells = <2>; 2389 ranges; 2390 2391 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2392 <&rpmhcc RPMH_CXO_CLK>, 2393 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2394 clock-names = "aux", "ref_clk_src", "com_aux"; 2395 2396 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2397 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2398 reset-names = "phy", "common"; 2399 2400 usb_1_ssphy: usb3-phy@88e9200 { 2401 reg = <0 0x088e9200 0 0x200>, 2402 <0 0x088e9400 0 0x200>, 2403 <0 0x088e9c00 0 0x400>, 2404 <0 0x088e9600 0 0x200>, 2405 <0 0x088e9800 0 0x200>, 2406 <0 0x088e9a00 0 0x100>; 2407 #clock-cells = <0>; 2408 #phy-cells = <0>; 2409 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2410 clock-names = "pipe0"; 2411 clock-output-names = "usb3_phy_pipe_clk_src"; 2412 }; 2413 2414 dp_phy: dp-phy@88ea200 { 2415 reg = <0 0x088ea200 0 0x200>, 2416 <0 0x088ea400 0 0x200>, 2417 <0 0x088eaa00 0 0x200>, 2418 <0 0x088ea600 0 0x200>, 2419 <0 0x088ea800 0 0x200>; 2420 #phy-cells = <0>; 2421 #clock-cells = <1>; 2422 }; 2423 }; 2424 2425 usb_2: usb@8cf8800 { 2426 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2427 reg = <0 0x08cf8800 0 0x400>; 2428 status = "disabled"; 2429 #address-cells = <2>; 2430 #size-cells = <2>; 2431 ranges; 2432 dma-ranges; 2433 2434 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2435 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2436 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2437 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2438 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2439 clock-names = "cfg_noc", "core", "iface","mock_utmi", 2440 "sleep"; 2441 2442 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2443 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2444 assigned-clock-rates = <19200000>, <200000000>; 2445 2446 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 2447 <&pdc 13 IRQ_TYPE_EDGE_RISING>, 2448 <&pdc 12 IRQ_TYPE_EDGE_RISING>; 2449 interrupt-names = "hs_phy_irq", 2450 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2451 2452 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 2453 2454 resets = <&gcc GCC_USB30_SEC_BCR>; 2455 2456 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2457 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 2458 interconnect-names = "usb-ddr", "apps-usb"; 2459 2460 usb_2_dwc3: usb@8c00000 { 2461 compatible = "snps,dwc3"; 2462 reg = <0 0x08c00000 0 0xe000>; 2463 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2464 iommus = <&apps_smmu 0xa0 0x0>; 2465 snps,dis_u2_susphy_quirk; 2466 snps,dis_enblslpm_quirk; 2467 phys = <&usb_2_hsphy>; 2468 phy-names = "usb2-phy"; 2469 maximum-speed = "high-speed"; 2470 }; 2471 }; 2472 2473 qspi: spi@88dc000 { 2474 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 2475 reg = <0 0x088dc000 0 0x1000>; 2476 #address-cells = <1>; 2477 #size-cells = <0>; 2478 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2479 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2480 <&gcc GCC_QSPI_CORE_CLK>; 2481 clock-names = "iface", "core"; 2482 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2483 &cnoc2 SLAVE_QSPI_0 0>; 2484 interconnect-names = "qspi-config"; 2485 power-domains = <&rpmhpd SC7280_CX>; 2486 operating-points-v2 = <&qspi_opp_table>; 2487 status = "disabled"; 2488 }; 2489 2490 dc_noc: interconnect@90e0000 { 2491 reg = <0 0x090e0000 0 0x5080>; 2492 compatible = "qcom,sc7280-dc-noc"; 2493 #interconnect-cells = <2>; 2494 qcom,bcm-voters = <&apps_bcm_voter>; 2495 }; 2496 2497 gem_noc: interconnect@9100000 { 2498 reg = <0 0x9100000 0 0xe2200>; 2499 compatible = "qcom,sc7280-gem-noc"; 2500 #interconnect-cells = <2>; 2501 qcom,bcm-voters = <&apps_bcm_voter>; 2502 }; 2503 2504 system-cache-controller@9200000 { 2505 compatible = "qcom,sc7280-llcc"; 2506 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 2507 reg-names = "llcc_base", "llcc_broadcast_base"; 2508 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2509 }; 2510 2511 nsp_noc: interconnect@a0c0000 { 2512 reg = <0 0x0a0c0000 0 0x10000>; 2513 compatible = "qcom,sc7280-nsp-noc"; 2514 #interconnect-cells = <2>; 2515 qcom,bcm-voters = <&apps_bcm_voter>; 2516 }; 2517 2518 usb_1: usb@a6f8800 { 2519 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 2520 reg = <0 0x0a6f8800 0 0x400>; 2521 status = "disabled"; 2522 #address-cells = <2>; 2523 #size-cells = <2>; 2524 ranges; 2525 dma-ranges; 2526 2527 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2528 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2529 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2530 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2531 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2532 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2533 "sleep"; 2534 2535 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2536 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2537 assigned-clock-rates = <19200000>, <200000000>; 2538 2539 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2540 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2541 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2542 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2543 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2544 "dm_hs_phy_irq", "ss_phy_irq"; 2545 2546 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2547 2548 resets = <&gcc GCC_USB30_PRIM_BCR>; 2549 2550 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2551 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 2552 interconnect-names = "usb-ddr", "apps-usb"; 2553 2554 usb_1_dwc3: usb@a600000 { 2555 compatible = "snps,dwc3"; 2556 reg = <0 0x0a600000 0 0xe000>; 2557 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2558 iommus = <&apps_smmu 0xe0 0x0>; 2559 snps,dis_u2_susphy_quirk; 2560 snps,dis_enblslpm_quirk; 2561 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2562 phy-names = "usb2-phy", "usb3-phy"; 2563 maximum-speed = "super-speed"; 2564 }; 2565 }; 2566 2567 videocc: clock-controller@aaf0000 { 2568 compatible = "qcom,sc7280-videocc"; 2569 reg = <0 0xaaf0000 0 0x10000>; 2570 clocks = <&rpmhcc RPMH_CXO_CLK>, 2571 <&rpmhcc RPMH_CXO_CLK_A>; 2572 clock-names = "bi_tcxo", "bi_tcxo_ao"; 2573 #clock-cells = <1>; 2574 #reset-cells = <1>; 2575 #power-domain-cells = <1>; 2576 }; 2577 2578 dispcc: clock-controller@af00000 { 2579 compatible = "qcom,sc7280-dispcc"; 2580 reg = <0 0xaf00000 0 0x20000>; 2581 clocks = <&rpmhcc RPMH_CXO_CLK>, 2582 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2583 <0>, <0>, <0>, <0>, <0>, <0>; 2584 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 2585 "dsi0_phy_pll_out_byteclk", 2586 "dsi0_phy_pll_out_dsiclk", 2587 "dp_phy_pll_link_clk", 2588 "dp_phy_pll_vco_div_clk", 2589 "edp_phy_pll_link_clk", 2590 "edp_phy_pll_vco_div_clk"; 2591 #clock-cells = <1>; 2592 #reset-cells = <1>; 2593 #power-domain-cells = <1>; 2594 }; 2595 2596 pdc: interrupt-controller@b220000 { 2597 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 2598 reg = <0 0x0b220000 0 0x30000>; 2599 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 2600 <55 306 4>, <59 312 3>, <62 374 2>, 2601 <64 434 2>, <66 438 3>, <69 86 1>, 2602 <70 520 54>, <124 609 31>, <155 63 1>, 2603 <156 716 12>; 2604 #interrupt-cells = <2>; 2605 interrupt-parent = <&intc>; 2606 interrupt-controller; 2607 }; 2608 2609 pdc_reset: reset-controller@b5e0000 { 2610 compatible = "qcom,sc7280-pdc-global"; 2611 reg = <0 0x0b5e0000 0 0x20000>; 2612 #reset-cells = <1>; 2613 }; 2614 2615 tsens0: thermal-sensor@c263000 { 2616 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2617 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2618 <0 0x0c222000 0 0x1ff>; /* SROT */ 2619 #qcom,sensors = <15>; 2620 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2622 interrupt-names = "uplow","critical"; 2623 #thermal-sensor-cells = <1>; 2624 }; 2625 2626 tsens1: thermal-sensor@c265000 { 2627 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 2628 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2629 <0 0x0c223000 0 0x1ff>; /* SROT */ 2630 #qcom,sensors = <12>; 2631 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2632 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2633 interrupt-names = "uplow","critical"; 2634 #thermal-sensor-cells = <1>; 2635 }; 2636 2637 aoss_reset: reset-controller@c2a0000 { 2638 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 2639 reg = <0 0x0c2a0000 0 0x31000>; 2640 #reset-cells = <1>; 2641 }; 2642 2643 aoss_qmp: power-controller@c300000 { 2644 compatible = "qcom,sc7280-aoss-qmp"; 2645 reg = <0 0x0c300000 0 0x400>; 2646 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2647 IPCC_MPROC_SIGNAL_GLINK_QMP 2648 IRQ_TYPE_EDGE_RISING>; 2649 mboxes = <&ipcc IPCC_CLIENT_AOP 2650 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2651 2652 #clock-cells = <0>; 2653 }; 2654 2655 sram@c3f0000 { 2656 compatible = "qcom,rpmh-stats"; 2657 reg = <0 0x0c3f0000 0 0x400>; 2658 }; 2659 2660 spmi_bus: spmi@c440000 { 2661 compatible = "qcom,spmi-pmic-arb"; 2662 reg = <0 0x0c440000 0 0x1100>, 2663 <0 0x0c600000 0 0x2000000>, 2664 <0 0x0e600000 0 0x100000>, 2665 <0 0x0e700000 0 0xa0000>, 2666 <0 0x0c40a000 0 0x26000>; 2667 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2668 interrupt-names = "periph_irq"; 2669 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2670 qcom,ee = <0>; 2671 qcom,channel = <0>; 2672 #address-cells = <1>; 2673 #size-cells = <1>; 2674 interrupt-controller; 2675 #interrupt-cells = <4>; 2676 }; 2677 2678 tlmm: pinctrl@f100000 { 2679 compatible = "qcom,sc7280-pinctrl"; 2680 reg = <0 0x0f100000 0 0x300000>; 2681 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2682 gpio-controller; 2683 #gpio-cells = <2>; 2684 interrupt-controller; 2685 #interrupt-cells = <2>; 2686 gpio-ranges = <&tlmm 0 0 175>; 2687 wakeup-parent = <&pdc>; 2688 2689 qspi_clk: qspi-clk { 2690 pins = "gpio14"; 2691 function = "qspi_clk"; 2692 }; 2693 2694 qspi_cs0: qspi-cs0 { 2695 pins = "gpio15"; 2696 function = "qspi_cs"; 2697 }; 2698 2699 qspi_cs1: qspi-cs1 { 2700 pins = "gpio19"; 2701 function = "qspi_cs"; 2702 }; 2703 2704 qspi_data01: qspi-data01 { 2705 pins = "gpio12", "gpio13"; 2706 function = "qspi_data"; 2707 }; 2708 2709 qspi_data12: qspi-data12 { 2710 pins = "gpio16", "gpio17"; 2711 function = "qspi_data"; 2712 }; 2713 2714 qup_i2c0_data_clk: qup-i2c0-data-clk { 2715 pins = "gpio0", "gpio1"; 2716 function = "qup00"; 2717 }; 2718 2719 qup_i2c1_data_clk: qup-i2c1-data-clk { 2720 pins = "gpio4", "gpio5"; 2721 function = "qup01"; 2722 }; 2723 2724 qup_i2c2_data_clk: qup-i2c2-data-clk { 2725 pins = "gpio8", "gpio9"; 2726 function = "qup02"; 2727 }; 2728 2729 qup_i2c3_data_clk: qup-i2c3-data-clk { 2730 pins = "gpio12", "gpio13"; 2731 function = "qup03"; 2732 }; 2733 2734 qup_i2c4_data_clk: qup-i2c4-data-clk { 2735 pins = "gpio16", "gpio17"; 2736 function = "qup04"; 2737 }; 2738 2739 qup_i2c5_data_clk: qup-i2c5-data-clk { 2740 pins = "gpio20", "gpio21"; 2741 function = "qup05"; 2742 }; 2743 2744 qup_i2c6_data_clk: qup-i2c6-data-clk { 2745 pins = "gpio24", "gpio25"; 2746 function = "qup06"; 2747 }; 2748 2749 qup_i2c7_data_clk: qup-i2c7-data-clk { 2750 pins = "gpio28", "gpio29"; 2751 function = "qup07"; 2752 }; 2753 2754 qup_i2c8_data_clk: qup-i2c8-data-clk { 2755 pins = "gpio32", "gpio33"; 2756 function = "qup10"; 2757 }; 2758 2759 qup_i2c9_data_clk: qup-i2c9-data-clk { 2760 pins = "gpio36", "gpio37"; 2761 function = "qup11"; 2762 }; 2763 2764 qup_i2c10_data_clk: qup-i2c10-data-clk { 2765 pins = "gpio40", "gpio41"; 2766 function = "qup12"; 2767 }; 2768 2769 qup_i2c11_data_clk: qup-i2c11-data-clk { 2770 pins = "gpio44", "gpio45"; 2771 function = "qup13"; 2772 }; 2773 2774 qup_i2c12_data_clk: qup-i2c12-data-clk { 2775 pins = "gpio48", "gpio49"; 2776 function = "qup14"; 2777 }; 2778 2779 qup_i2c13_data_clk: qup-i2c13-data-clk { 2780 pins = "gpio52", "gpio53"; 2781 function = "qup15"; 2782 }; 2783 2784 qup_i2c14_data_clk: qup-i2c14-data-clk { 2785 pins = "gpio56", "gpio57"; 2786 function = "qup16"; 2787 }; 2788 2789 qup_i2c15_data_clk: qup-i2c15-data-clk { 2790 pins = "gpio60", "gpio61"; 2791 function = "qup17"; 2792 }; 2793 2794 qup_spi0_data_clk: qup-spi0-data-clk { 2795 pins = "gpio0", "gpio1", "gpio2"; 2796 function = "qup00"; 2797 }; 2798 2799 qup_spi0_cs: qup-spi0-cs { 2800 pins = "gpio3"; 2801 function = "qup00"; 2802 }; 2803 2804 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 2805 pins = "gpio3"; 2806 function = "gpio"; 2807 }; 2808 2809 qup_spi1_data_clk: qup-spi1-data-clk { 2810 pins = "gpio4", "gpio5", "gpio6"; 2811 function = "qup01"; 2812 }; 2813 2814 qup_spi1_cs: qup-spi1-cs { 2815 pins = "gpio7"; 2816 function = "qup01"; 2817 }; 2818 2819 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 2820 pins = "gpio7"; 2821 function = "gpio"; 2822 }; 2823 2824 qup_spi2_data_clk: qup-spi2-data-clk { 2825 pins = "gpio8", "gpio9", "gpio10"; 2826 function = "qup02"; 2827 }; 2828 2829 qup_spi2_cs: qup-spi2-cs { 2830 pins = "gpio11"; 2831 function = "qup02"; 2832 }; 2833 2834 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 2835 pins = "gpio11"; 2836 function = "gpio"; 2837 }; 2838 2839 qup_spi3_data_clk: qup-spi3-data-clk { 2840 pins = "gpio12", "gpio13", "gpio14"; 2841 function = "qup03"; 2842 }; 2843 2844 qup_spi3_cs: qup-spi3-cs { 2845 pins = "gpio15"; 2846 function = "qup03"; 2847 }; 2848 2849 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 2850 pins = "gpio15"; 2851 function = "gpio"; 2852 }; 2853 2854 qup_spi4_data_clk: qup-spi4-data-clk { 2855 pins = "gpio16", "gpio17", "gpio18"; 2856 function = "qup04"; 2857 }; 2858 2859 qup_spi4_cs: qup-spi4-cs { 2860 pins = "gpio19"; 2861 function = "qup04"; 2862 }; 2863 2864 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 2865 pins = "gpio19"; 2866 function = "gpio"; 2867 }; 2868 2869 qup_spi5_data_clk: qup-spi5-data-clk { 2870 pins = "gpio20", "gpio21", "gpio22"; 2871 function = "qup05"; 2872 }; 2873 2874 qup_spi5_cs: qup-spi5-cs { 2875 pins = "gpio23"; 2876 function = "qup05"; 2877 }; 2878 2879 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 2880 pins = "gpio23"; 2881 function = "gpio"; 2882 }; 2883 2884 qup_spi6_data_clk: qup-spi6-data-clk { 2885 pins = "gpio24", "gpio25", "gpio26"; 2886 function = "qup06"; 2887 }; 2888 2889 qup_spi6_cs: qup-spi6-cs { 2890 pins = "gpio27"; 2891 function = "qup06"; 2892 }; 2893 2894 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 2895 pins = "gpio27"; 2896 function = "gpio"; 2897 }; 2898 2899 qup_spi7_data_clk: qup-spi7-data-clk { 2900 pins = "gpio28", "gpio29", "gpio30"; 2901 function = "qup07"; 2902 }; 2903 2904 qup_spi7_cs: qup-spi7-cs { 2905 pins = "gpio31"; 2906 function = "qup07"; 2907 }; 2908 2909 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 2910 pins = "gpio31"; 2911 function = "gpio"; 2912 }; 2913 2914 qup_spi8_data_clk: qup-spi8-data-clk { 2915 pins = "gpio32", "gpio33", "gpio34"; 2916 function = "qup10"; 2917 }; 2918 2919 qup_spi8_cs: qup-spi8-cs { 2920 pins = "gpio35"; 2921 function = "qup10"; 2922 }; 2923 2924 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 2925 pins = "gpio35"; 2926 function = "gpio"; 2927 }; 2928 2929 qup_spi9_data_clk: qup-spi9-data-clk { 2930 pins = "gpio36", "gpio37", "gpio38"; 2931 function = "qup11"; 2932 }; 2933 2934 qup_spi9_cs: qup-spi9-cs { 2935 pins = "gpio39"; 2936 function = "qup11"; 2937 }; 2938 2939 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 2940 pins = "gpio39"; 2941 function = "gpio"; 2942 }; 2943 2944 qup_spi10_data_clk: qup-spi10-data-clk { 2945 pins = "gpio40", "gpio41", "gpio42"; 2946 function = "qup12"; 2947 }; 2948 2949 qup_spi10_cs: qup-spi10-cs { 2950 pins = "gpio43"; 2951 function = "qup12"; 2952 }; 2953 2954 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 2955 pins = "gpio43"; 2956 function = "gpio"; 2957 }; 2958 2959 qup_spi11_data_clk: qup-spi11-data-clk { 2960 pins = "gpio44", "gpio45", "gpio46"; 2961 function = "qup13"; 2962 }; 2963 2964 qup_spi11_cs: qup-spi11-cs { 2965 pins = "gpio47"; 2966 function = "qup13"; 2967 }; 2968 2969 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 2970 pins = "gpio47"; 2971 function = "gpio"; 2972 }; 2973 2974 qup_spi12_data_clk: qup-spi12-data-clk { 2975 pins = "gpio48", "gpio49", "gpio50"; 2976 function = "qup14"; 2977 }; 2978 2979 qup_spi12_cs: qup-spi12-cs { 2980 pins = "gpio51"; 2981 function = "qup14"; 2982 }; 2983 2984 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 2985 pins = "gpio51"; 2986 function = "gpio"; 2987 }; 2988 2989 qup_spi13_data_clk: qup-spi13-data-clk { 2990 pins = "gpio52", "gpio53", "gpio54"; 2991 function = "qup15"; 2992 }; 2993 2994 qup_spi13_cs: qup-spi13-cs { 2995 pins = "gpio55"; 2996 function = "qup15"; 2997 }; 2998 2999 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3000 pins = "gpio55"; 3001 function = "gpio"; 3002 }; 3003 3004 qup_spi14_data_clk: qup-spi14-data-clk { 3005 pins = "gpio56", "gpio57", "gpio58"; 3006 function = "qup16"; 3007 }; 3008 3009 qup_spi14_cs: qup-spi14-cs { 3010 pins = "gpio59"; 3011 function = "qup16"; 3012 }; 3013 3014 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3015 pins = "gpio59"; 3016 function = "gpio"; 3017 }; 3018 3019 qup_spi15_data_clk: qup-spi15-data-clk { 3020 pins = "gpio60", "gpio61", "gpio62"; 3021 function = "qup17"; 3022 }; 3023 3024 qup_spi15_cs: qup-spi15-cs { 3025 pins = "gpio63"; 3026 function = "qup17"; 3027 }; 3028 3029 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3030 pins = "gpio63"; 3031 function = "gpio"; 3032 }; 3033 3034 qup_uart0_cts: qup-uart0-cts { 3035 pins = "gpio0"; 3036 function = "qup00"; 3037 }; 3038 3039 qup_uart0_rts: qup-uart0-rts { 3040 pins = "gpio1"; 3041 function = "qup00"; 3042 }; 3043 3044 qup_uart0_tx: qup-uart0-tx { 3045 pins = "gpio2"; 3046 function = "qup00"; 3047 }; 3048 3049 qup_uart0_rx: qup-uart0-rx { 3050 pins = "gpio3"; 3051 function = "qup00"; 3052 }; 3053 3054 qup_uart1_cts: qup-uart1-cts { 3055 pins = "gpio4"; 3056 function = "qup01"; 3057 }; 3058 3059 qup_uart1_rts: qup-uart1-rts { 3060 pins = "gpio5"; 3061 function = "qup01"; 3062 }; 3063 3064 qup_uart1_tx: qup-uart1-tx { 3065 pins = "gpio6"; 3066 function = "qup01"; 3067 }; 3068 3069 qup_uart1_rx: qup-uart1-rx { 3070 pins = "gpio7"; 3071 function = "qup01"; 3072 }; 3073 3074 qup_uart2_cts: qup-uart2-cts { 3075 pins = "gpio8"; 3076 function = "qup02"; 3077 }; 3078 3079 qup_uart2_rts: qup-uart2-rts { 3080 pins = "gpio9"; 3081 function = "qup02"; 3082 }; 3083 3084 qup_uart2_tx: qup-uart2-tx { 3085 pins = "gpio10"; 3086 function = "qup02"; 3087 }; 3088 3089 qup_uart2_rx: qup-uart2-rx { 3090 pins = "gpio11"; 3091 function = "qup02"; 3092 }; 3093 3094 qup_uart3_cts: qup-uart3-cts { 3095 pins = "gpio12"; 3096 function = "qup03"; 3097 }; 3098 3099 qup_uart3_rts: qup-uart3-rts { 3100 pins = "gpio13"; 3101 function = "qup03"; 3102 }; 3103 3104 qup_uart3_tx: qup-uart3-tx { 3105 pins = "gpio14"; 3106 function = "qup03"; 3107 }; 3108 3109 qup_uart3_rx: qup-uart3-rx { 3110 pins = "gpio15"; 3111 function = "qup03"; 3112 }; 3113 3114 qup_uart4_cts: qup-uart4-cts { 3115 pins = "gpio16"; 3116 function = "qup04"; 3117 }; 3118 3119 qup_uart4_rts: qup-uart4-rts { 3120 pins = "gpio17"; 3121 function = "qup04"; 3122 }; 3123 3124 qup_uart4_tx: qup-uart4-tx { 3125 pins = "gpio18"; 3126 function = "qup04"; 3127 }; 3128 3129 qup_uart4_rx: qup-uart4-rx { 3130 pins = "gpio19"; 3131 function = "qup04"; 3132 }; 3133 3134 qup_uart5_cts: qup-uart5-cts { 3135 pins = "gpio20"; 3136 function = "qup05"; 3137 }; 3138 3139 qup_uart5_rts: qup-uart5-rts { 3140 pins = "gpio21"; 3141 function = "qup05"; 3142 }; 3143 3144 qup_uart5_tx: qup-uart5-tx { 3145 pins = "gpio22"; 3146 function = "qup05"; 3147 }; 3148 3149 qup_uart5_rx: qup-uart5-rx { 3150 pins = "gpio23"; 3151 function = "qup05"; 3152 }; 3153 3154 qup_uart6_cts: qup-uart6-cts { 3155 pins = "gpio24"; 3156 function = "qup06"; 3157 }; 3158 3159 qup_uart6_rts: qup-uart6-rts { 3160 pins = "gpio25"; 3161 function = "qup06"; 3162 }; 3163 3164 qup_uart6_tx: qup-uart6-tx { 3165 pins = "gpio26"; 3166 function = "qup06"; 3167 }; 3168 3169 qup_uart6_rx: qup-uart6-rx { 3170 pins = "gpio27"; 3171 function = "qup06"; 3172 }; 3173 3174 qup_uart7_cts: qup-uart7-cts { 3175 pins = "gpio28"; 3176 function = "qup07"; 3177 }; 3178 3179 qup_uart7_rts: qup-uart7-rts { 3180 pins = "gpio29"; 3181 function = "qup07"; 3182 }; 3183 3184 qup_uart7_tx: qup-uart7-tx { 3185 pins = "gpio30"; 3186 function = "qup07"; 3187 }; 3188 3189 qup_uart7_rx: qup-uart7-rx { 3190 pins = "gpio31"; 3191 function = "qup07"; 3192 }; 3193 3194 sdc1_on: sdc1-on { 3195 clk { 3196 pins = "sdc1_clk"; 3197 }; 3198 3199 cmd { 3200 pins = "sdc1_cmd"; 3201 }; 3202 3203 data { 3204 pins = "sdc1_data"; 3205 }; 3206 3207 rclk { 3208 pins = "sdc1_rclk"; 3209 }; 3210 }; 3211 3212 sdc1_off: sdc1-off { 3213 clk { 3214 pins = "sdc1_clk"; 3215 drive-strength = <2>; 3216 bias-bus-hold; 3217 }; 3218 3219 cmd { 3220 pins = "sdc1_cmd"; 3221 drive-strength = <2>; 3222 bias-bus-hold; 3223 }; 3224 3225 data { 3226 pins = "sdc1_data"; 3227 drive-strength = <2>; 3228 bias-bus-hold; 3229 }; 3230 3231 rclk { 3232 pins = "sdc1_rclk"; 3233 bias-bus-hold; 3234 }; 3235 }; 3236 3237 sdc2_on: sdc2-on { 3238 clk { 3239 pins = "sdc2_clk"; 3240 }; 3241 3242 cmd { 3243 pins = "sdc2_cmd"; 3244 }; 3245 3246 data { 3247 pins = "sdc2_data"; 3248 }; 3249 }; 3250 3251 sdc2_off: sdc2-off { 3252 clk { 3253 pins = "sdc2_clk"; 3254 drive-strength = <2>; 3255 bias-bus-hold; 3256 }; 3257 3258 cmd { 3259 pins ="sdc2_cmd"; 3260 drive-strength = <2>; 3261 bias-bus-hold; 3262 }; 3263 3264 data { 3265 pins ="sdc2_data"; 3266 drive-strength = <2>; 3267 bias-bus-hold; 3268 }; 3269 }; 3270 3271 qup_uart8_cts: qup-uart8-cts { 3272 pins = "gpio32"; 3273 function = "qup10"; 3274 }; 3275 3276 qup_uart8_rts: qup-uart8-rts { 3277 pins = "gpio33"; 3278 function = "qup10"; 3279 }; 3280 3281 qup_uart8_tx: qup-uart8-tx { 3282 pins = "gpio34"; 3283 function = "qup10"; 3284 }; 3285 3286 qup_uart8_rx: qup-uart8-rx { 3287 pins = "gpio35"; 3288 function = "qup10"; 3289 }; 3290 3291 qup_uart9_cts: qup-uart9-cts { 3292 pins = "gpio36"; 3293 function = "qup11"; 3294 }; 3295 3296 qup_uart9_rts: qup-uart9-rts { 3297 pins = "gpio37"; 3298 function = "qup11"; 3299 }; 3300 3301 qup_uart9_tx: qup-uart9-tx { 3302 pins = "gpio38"; 3303 function = "qup11"; 3304 }; 3305 3306 qup_uart9_rx: qup-uart9-rx { 3307 pins = "gpio39"; 3308 function = "qup11"; 3309 }; 3310 3311 qup_uart10_cts: qup-uart10-cts { 3312 pins = "gpio40"; 3313 function = "qup12"; 3314 }; 3315 3316 qup_uart10_rts: qup-uart10-rts { 3317 pins = "gpio41"; 3318 function = "qup12"; 3319 }; 3320 3321 qup_uart10_tx: qup-uart10-tx { 3322 pins = "gpio42"; 3323 function = "qup12"; 3324 }; 3325 3326 qup_uart10_rx: qup-uart10-rx { 3327 pins = "gpio43"; 3328 function = "qup12"; 3329 }; 3330 3331 qup_uart11_cts: qup-uart11-cts { 3332 pins = "gpio44"; 3333 function = "qup13"; 3334 }; 3335 3336 qup_uart11_rts: qup-uart11-rts { 3337 pins = "gpio45"; 3338 function = "qup13"; 3339 }; 3340 3341 qup_uart11_tx: qup-uart11-tx { 3342 pins = "gpio46"; 3343 function = "qup13"; 3344 }; 3345 3346 qup_uart11_rx: qup-uart11-rx { 3347 pins = "gpio47"; 3348 function = "qup13"; 3349 }; 3350 3351 qup_uart12_cts: qup-uart12-cts { 3352 pins = "gpio48"; 3353 function = "qup14"; 3354 }; 3355 3356 qup_uart12_rts: qup-uart12-rts { 3357 pins = "gpio49"; 3358 function = "qup14"; 3359 }; 3360 3361 qup_uart12_tx: qup-uart12-tx { 3362 pins = "gpio50"; 3363 function = "qup14"; 3364 }; 3365 3366 qup_uart12_rx: qup-uart12-rx { 3367 pins = "gpio51"; 3368 function = "qup14"; 3369 }; 3370 3371 qup_uart13_cts: qup-uart13-cts { 3372 pins = "gpio52"; 3373 function = "qup15"; 3374 }; 3375 3376 qup_uart13_rts: qup-uart13-rts { 3377 pins = "gpio53"; 3378 function = "qup15"; 3379 }; 3380 3381 qup_uart13_tx: qup-uart13-tx { 3382 pins = "gpio54"; 3383 function = "qup15"; 3384 }; 3385 3386 qup_uart13_rx: qup-uart13-rx { 3387 pins = "gpio55"; 3388 function = "qup15"; 3389 }; 3390 3391 qup_uart14_cts: qup-uart14-cts { 3392 pins = "gpio56"; 3393 function = "qup16"; 3394 }; 3395 3396 qup_uart14_rts: qup-uart14-rts { 3397 pins = "gpio57"; 3398 function = "qup16"; 3399 }; 3400 3401 qup_uart14_tx: qup-uart14-tx { 3402 pins = "gpio58"; 3403 function = "qup16"; 3404 }; 3405 3406 qup_uart14_rx: qup-uart14-rx { 3407 pins = "gpio59"; 3408 function = "qup16"; 3409 }; 3410 3411 qup_uart15_cts: qup-uart15-cts { 3412 pins = "gpio60"; 3413 function = "qup17"; 3414 }; 3415 3416 qup_uart15_rts: qup-uart15-rts { 3417 pins = "gpio61"; 3418 function = "qup17"; 3419 }; 3420 3421 qup_uart15_tx: qup-uart15-tx { 3422 pins = "gpio62"; 3423 function = "qup17"; 3424 }; 3425 3426 qup_uart15_rx: qup-uart15-rx { 3427 pins = "gpio63"; 3428 function = "qup17"; 3429 }; 3430 }; 3431 3432 imem@146a5000 { 3433 compatible = "qcom,sc7280-imem", "syscon"; 3434 reg = <0 0x146a5000 0 0x6000>; 3435 3436 #address-cells = <1>; 3437 #size-cells = <1>; 3438 3439 ranges = <0 0 0x146a5000 0x6000>; 3440 3441 pil-reloc@594c { 3442 compatible = "qcom,pil-reloc-info"; 3443 reg = <0x594c 0xc8>; 3444 }; 3445 }; 3446 3447 apps_smmu: iommu@15000000 { 3448 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 3449 reg = <0 0x15000000 0 0x100000>; 3450 #iommu-cells = <2>; 3451 #global-interrupts = <1>; 3452 dma-coherent; 3453 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3534 }; 3535 3536 intc: interrupt-controller@17a00000 { 3537 compatible = "arm,gic-v3"; 3538 #address-cells = <2>; 3539 #size-cells = <2>; 3540 ranges; 3541 #interrupt-cells = <3>; 3542 interrupt-controller; 3543 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3544 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3545 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3546 3547 gic-its@17a40000 { 3548 compatible = "arm,gic-v3-its"; 3549 msi-controller; 3550 #msi-cells = <1>; 3551 reg = <0 0x17a40000 0 0x20000>; 3552 status = "disabled"; 3553 }; 3554 }; 3555 3556 watchdog@17c10000 { 3557 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 3558 reg = <0 0x17c10000 0 0x1000>; 3559 clocks = <&sleep_clk>; 3560 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3561 }; 3562 3563 timer@17c20000 { 3564 #address-cells = <2>; 3565 #size-cells = <2>; 3566 ranges; 3567 compatible = "arm,armv7-timer-mem"; 3568 reg = <0 0x17c20000 0 0x1000>; 3569 3570 frame@17c21000 { 3571 frame-number = <0>; 3572 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3574 reg = <0 0x17c21000 0 0x1000>, 3575 <0 0x17c22000 0 0x1000>; 3576 }; 3577 3578 frame@17c23000 { 3579 frame-number = <1>; 3580 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3581 reg = <0 0x17c23000 0 0x1000>; 3582 status = "disabled"; 3583 }; 3584 3585 frame@17c25000 { 3586 frame-number = <2>; 3587 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3588 reg = <0 0x17c25000 0 0x1000>; 3589 status = "disabled"; 3590 }; 3591 3592 frame@17c27000 { 3593 frame-number = <3>; 3594 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3595 reg = <0 0x17c27000 0 0x1000>; 3596 status = "disabled"; 3597 }; 3598 3599 frame@17c29000 { 3600 frame-number = <4>; 3601 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3602 reg = <0 0x17c29000 0 0x1000>; 3603 status = "disabled"; 3604 }; 3605 3606 frame@17c2b000 { 3607 frame-number = <5>; 3608 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3609 reg = <0 0x17c2b000 0 0x1000>; 3610 status = "disabled"; 3611 }; 3612 3613 frame@17c2d000 { 3614 frame-number = <6>; 3615 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3616 reg = <0 0x17c2d000 0 0x1000>; 3617 status = "disabled"; 3618 }; 3619 }; 3620 3621 apps_rsc: rsc@18200000 { 3622 compatible = "qcom,rpmh-rsc"; 3623 reg = <0 0x18200000 0 0x10000>, 3624 <0 0x18210000 0 0x10000>, 3625 <0 0x18220000 0 0x10000>; 3626 reg-names = "drv-0", "drv-1", "drv-2"; 3627 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3630 qcom,tcs-offset = <0xd00>; 3631 qcom,drv-id = <2>; 3632 qcom,tcs-config = <ACTIVE_TCS 2>, 3633 <SLEEP_TCS 3>, 3634 <WAKE_TCS 3>, 3635 <CONTROL_TCS 1>; 3636 3637 apps_bcm_voter: bcm-voter { 3638 compatible = "qcom,bcm-voter"; 3639 }; 3640 3641 rpmhpd: power-controller { 3642 compatible = "qcom,sc7280-rpmhpd"; 3643 #power-domain-cells = <1>; 3644 operating-points-v2 = <&rpmhpd_opp_table>; 3645 3646 rpmhpd_opp_table: opp-table { 3647 compatible = "operating-points-v2"; 3648 3649 rpmhpd_opp_ret: opp1 { 3650 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3651 }; 3652 3653 rpmhpd_opp_low_svs: opp2 { 3654 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3655 }; 3656 3657 rpmhpd_opp_svs: opp3 { 3658 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3659 }; 3660 3661 rpmhpd_opp_svs_l1: opp4 { 3662 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3663 }; 3664 3665 rpmhpd_opp_svs_l2: opp5 { 3666 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3667 }; 3668 3669 rpmhpd_opp_nom: opp6 { 3670 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3671 }; 3672 3673 rpmhpd_opp_nom_l1: opp7 { 3674 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3675 }; 3676 3677 rpmhpd_opp_turbo: opp8 { 3678 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3679 }; 3680 3681 rpmhpd_opp_turbo_l1: opp9 { 3682 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3683 }; 3684 }; 3685 }; 3686 3687 rpmhcc: clock-controller { 3688 compatible = "qcom,sc7280-rpmh-clk"; 3689 clocks = <&xo_board>; 3690 clock-names = "xo"; 3691 #clock-cells = <1>; 3692 }; 3693 }; 3694 3695 cpufreq_hw: cpufreq@18591000 { 3696 compatible = "qcom,cpufreq-epss"; 3697 reg = <0 0x18591100 0 0x900>, 3698 <0 0x18592100 0 0x900>, 3699 <0 0x18593100 0 0x900>; 3700 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3701 clock-names = "xo", "alternate"; 3702 #freq-domain-cells = <1>; 3703 }; 3704 }; 3705 3706 thermal_zones: thermal-zones { 3707 cpu0-thermal { 3708 polling-delay-passive = <250>; 3709 polling-delay = <0>; 3710 3711 thermal-sensors = <&tsens0 1>; 3712 3713 trips { 3714 cpu0_alert0: trip-point0 { 3715 temperature = <90000>; 3716 hysteresis = <2000>; 3717 type = "passive"; 3718 }; 3719 3720 cpu0_alert1: trip-point1 { 3721 temperature = <95000>; 3722 hysteresis = <2000>; 3723 type = "passive"; 3724 }; 3725 3726 cpu0_crit: cpu-crit { 3727 temperature = <110000>; 3728 hysteresis = <0>; 3729 type = "critical"; 3730 }; 3731 }; 3732 3733 cooling-maps { 3734 map0 { 3735 trip = <&cpu0_alert0>; 3736 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3740 }; 3741 map1 { 3742 trip = <&cpu0_alert1>; 3743 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3745 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3747 }; 3748 }; 3749 }; 3750 3751 cpu1-thermal { 3752 polling-delay-passive = <250>; 3753 polling-delay = <0>; 3754 3755 thermal-sensors = <&tsens0 2>; 3756 3757 trips { 3758 cpu1_alert0: trip-point0 { 3759 temperature = <90000>; 3760 hysteresis = <2000>; 3761 type = "passive"; 3762 }; 3763 3764 cpu1_alert1: trip-point1 { 3765 temperature = <95000>; 3766 hysteresis = <2000>; 3767 type = "passive"; 3768 }; 3769 3770 cpu1_crit: cpu-crit { 3771 temperature = <110000>; 3772 hysteresis = <0>; 3773 type = "critical"; 3774 }; 3775 }; 3776 3777 cooling-maps { 3778 map0 { 3779 trip = <&cpu1_alert0>; 3780 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3784 }; 3785 map1 { 3786 trip = <&cpu1_alert1>; 3787 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3788 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3789 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3790 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3791 }; 3792 }; 3793 }; 3794 3795 cpu2-thermal { 3796 polling-delay-passive = <250>; 3797 polling-delay = <0>; 3798 3799 thermal-sensors = <&tsens0 3>; 3800 3801 trips { 3802 cpu2_alert0: trip-point0 { 3803 temperature = <90000>; 3804 hysteresis = <2000>; 3805 type = "passive"; 3806 }; 3807 3808 cpu2_alert1: trip-point1 { 3809 temperature = <95000>; 3810 hysteresis = <2000>; 3811 type = "passive"; 3812 }; 3813 3814 cpu2_crit: cpu-crit { 3815 temperature = <110000>; 3816 hysteresis = <0>; 3817 type = "critical"; 3818 }; 3819 }; 3820 3821 cooling-maps { 3822 map0 { 3823 trip = <&cpu2_alert0>; 3824 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3826 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3828 }; 3829 map1 { 3830 trip = <&cpu2_alert1>; 3831 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3832 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3833 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3834 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3835 }; 3836 }; 3837 }; 3838 3839 cpu3-thermal { 3840 polling-delay-passive = <250>; 3841 polling-delay = <0>; 3842 3843 thermal-sensors = <&tsens0 4>; 3844 3845 trips { 3846 cpu3_alert0: trip-point0 { 3847 temperature = <90000>; 3848 hysteresis = <2000>; 3849 type = "passive"; 3850 }; 3851 3852 cpu3_alert1: trip-point1 { 3853 temperature = <95000>; 3854 hysteresis = <2000>; 3855 type = "passive"; 3856 }; 3857 3858 cpu3_crit: cpu-crit { 3859 temperature = <110000>; 3860 hysteresis = <0>; 3861 type = "critical"; 3862 }; 3863 }; 3864 3865 cooling-maps { 3866 map0 { 3867 trip = <&cpu3_alert0>; 3868 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3869 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3872 }; 3873 map1 { 3874 trip = <&cpu3_alert1>; 3875 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3876 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3877 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3879 }; 3880 }; 3881 }; 3882 3883 cpu4-thermal { 3884 polling-delay-passive = <250>; 3885 polling-delay = <0>; 3886 3887 thermal-sensors = <&tsens0 7>; 3888 3889 trips { 3890 cpu4_alert0: trip-point0 { 3891 temperature = <90000>; 3892 hysteresis = <2000>; 3893 type = "passive"; 3894 }; 3895 3896 cpu4_alert1: trip-point1 { 3897 temperature = <95000>; 3898 hysteresis = <2000>; 3899 type = "passive"; 3900 }; 3901 3902 cpu4_crit: cpu-crit { 3903 temperature = <110000>; 3904 hysteresis = <0>; 3905 type = "critical"; 3906 }; 3907 }; 3908 3909 cooling-maps { 3910 map0 { 3911 trip = <&cpu4_alert0>; 3912 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3914 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3915 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3916 }; 3917 map1 { 3918 trip = <&cpu4_alert1>; 3919 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3923 }; 3924 }; 3925 }; 3926 3927 cpu5-thermal { 3928 polling-delay-passive = <250>; 3929 polling-delay = <0>; 3930 3931 thermal-sensors = <&tsens0 8>; 3932 3933 trips { 3934 cpu5_alert0: trip-point0 { 3935 temperature = <90000>; 3936 hysteresis = <2000>; 3937 type = "passive"; 3938 }; 3939 3940 cpu5_alert1: trip-point1 { 3941 temperature = <95000>; 3942 hysteresis = <2000>; 3943 type = "passive"; 3944 }; 3945 3946 cpu5_crit: cpu-crit { 3947 temperature = <110000>; 3948 hysteresis = <0>; 3949 type = "critical"; 3950 }; 3951 }; 3952 3953 cooling-maps { 3954 map0 { 3955 trip = <&cpu5_alert0>; 3956 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3959 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3960 }; 3961 map1 { 3962 trip = <&cpu5_alert1>; 3963 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3965 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3966 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3967 }; 3968 }; 3969 }; 3970 3971 cpu6-thermal { 3972 polling-delay-passive = <250>; 3973 polling-delay = <0>; 3974 3975 thermal-sensors = <&tsens0 9>; 3976 3977 trips { 3978 cpu6_alert0: trip-point0 { 3979 temperature = <90000>; 3980 hysteresis = <2000>; 3981 type = "passive"; 3982 }; 3983 3984 cpu6_alert1: trip-point1 { 3985 temperature = <95000>; 3986 hysteresis = <2000>; 3987 type = "passive"; 3988 }; 3989 3990 cpu6_crit: cpu-crit { 3991 temperature = <110000>; 3992 hysteresis = <0>; 3993 type = "critical"; 3994 }; 3995 }; 3996 3997 cooling-maps { 3998 map0 { 3999 trip = <&cpu6_alert0>; 4000 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4001 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4002 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4003 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4004 }; 4005 map1 { 4006 trip = <&cpu6_alert1>; 4007 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4009 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4010 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4011 }; 4012 }; 4013 }; 4014 4015 cpu7-thermal { 4016 polling-delay-passive = <250>; 4017 polling-delay = <0>; 4018 4019 thermal-sensors = <&tsens0 10>; 4020 4021 trips { 4022 cpu7_alert0: trip-point0 { 4023 temperature = <90000>; 4024 hysteresis = <2000>; 4025 type = "passive"; 4026 }; 4027 4028 cpu7_alert1: trip-point1 { 4029 temperature = <95000>; 4030 hysteresis = <2000>; 4031 type = "passive"; 4032 }; 4033 4034 cpu7_crit: cpu-crit { 4035 temperature = <110000>; 4036 hysteresis = <0>; 4037 type = "critical"; 4038 }; 4039 }; 4040 4041 cooling-maps { 4042 map0 { 4043 trip = <&cpu7_alert0>; 4044 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4045 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4046 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4047 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4048 }; 4049 map1 { 4050 trip = <&cpu7_alert1>; 4051 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4052 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4053 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4054 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4055 }; 4056 }; 4057 }; 4058 4059 cpu8-thermal { 4060 polling-delay-passive = <250>; 4061 polling-delay = <0>; 4062 4063 thermal-sensors = <&tsens0 11>; 4064 4065 trips { 4066 cpu8_alert0: trip-point0 { 4067 temperature = <90000>; 4068 hysteresis = <2000>; 4069 type = "passive"; 4070 }; 4071 4072 cpu8_alert1: trip-point1 { 4073 temperature = <95000>; 4074 hysteresis = <2000>; 4075 type = "passive"; 4076 }; 4077 4078 cpu8_crit: cpu-crit { 4079 temperature = <110000>; 4080 hysteresis = <0>; 4081 type = "critical"; 4082 }; 4083 }; 4084 4085 cooling-maps { 4086 map0 { 4087 trip = <&cpu8_alert0>; 4088 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4089 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4090 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4091 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4092 }; 4093 map1 { 4094 trip = <&cpu8_alert1>; 4095 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4096 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4097 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4098 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4099 }; 4100 }; 4101 }; 4102 4103 cpu9-thermal { 4104 polling-delay-passive = <250>; 4105 polling-delay = <0>; 4106 4107 thermal-sensors = <&tsens0 12>; 4108 4109 trips { 4110 cpu9_alert0: trip-point0 { 4111 temperature = <90000>; 4112 hysteresis = <2000>; 4113 type = "passive"; 4114 }; 4115 4116 cpu9_alert1: trip-point1 { 4117 temperature = <95000>; 4118 hysteresis = <2000>; 4119 type = "passive"; 4120 }; 4121 4122 cpu9_crit: cpu-crit { 4123 temperature = <110000>; 4124 hysteresis = <0>; 4125 type = "critical"; 4126 }; 4127 }; 4128 4129 cooling-maps { 4130 map0 { 4131 trip = <&cpu9_alert0>; 4132 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4134 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4135 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4136 }; 4137 map1 { 4138 trip = <&cpu9_alert1>; 4139 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4140 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4141 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4142 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4143 }; 4144 }; 4145 }; 4146 4147 cpu10-thermal { 4148 polling-delay-passive = <250>; 4149 polling-delay = <0>; 4150 4151 thermal-sensors = <&tsens0 13>; 4152 4153 trips { 4154 cpu10_alert0: trip-point0 { 4155 temperature = <90000>; 4156 hysteresis = <2000>; 4157 type = "passive"; 4158 }; 4159 4160 cpu10_alert1: trip-point1 { 4161 temperature = <95000>; 4162 hysteresis = <2000>; 4163 type = "passive"; 4164 }; 4165 4166 cpu10_crit: cpu-crit { 4167 temperature = <110000>; 4168 hysteresis = <0>; 4169 type = "critical"; 4170 }; 4171 }; 4172 4173 cooling-maps { 4174 map0 { 4175 trip = <&cpu10_alert0>; 4176 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4177 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4178 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4179 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4180 }; 4181 map1 { 4182 trip = <&cpu10_alert1>; 4183 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4184 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4185 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4186 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4187 }; 4188 }; 4189 }; 4190 4191 cpu11-thermal { 4192 polling-delay-passive = <250>; 4193 polling-delay = <0>; 4194 4195 thermal-sensors = <&tsens0 14>; 4196 4197 trips { 4198 cpu11_alert0: trip-point0 { 4199 temperature = <90000>; 4200 hysteresis = <2000>; 4201 type = "passive"; 4202 }; 4203 4204 cpu11_alert1: trip-point1 { 4205 temperature = <95000>; 4206 hysteresis = <2000>; 4207 type = "passive"; 4208 }; 4209 4210 cpu11_crit: cpu-crit { 4211 temperature = <110000>; 4212 hysteresis = <0>; 4213 type = "critical"; 4214 }; 4215 }; 4216 4217 cooling-maps { 4218 map0 { 4219 trip = <&cpu11_alert0>; 4220 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4221 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4222 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4223 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4224 }; 4225 map1 { 4226 trip = <&cpu11_alert1>; 4227 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4228 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4229 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4230 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4231 }; 4232 }; 4233 }; 4234 4235 aoss0-thermal { 4236 polling-delay-passive = <0>; 4237 polling-delay = <0>; 4238 4239 thermal-sensors = <&tsens0 0>; 4240 4241 trips { 4242 aoss0_alert0: trip-point0 { 4243 temperature = <90000>; 4244 hysteresis = <2000>; 4245 type = "hot"; 4246 }; 4247 4248 aoss0_crit: aoss0-crit { 4249 temperature = <110000>; 4250 hysteresis = <0>; 4251 type = "critical"; 4252 }; 4253 }; 4254 }; 4255 4256 aoss1-thermal { 4257 polling-delay-passive = <0>; 4258 polling-delay = <0>; 4259 4260 thermal-sensors = <&tsens1 0>; 4261 4262 trips { 4263 aoss1_alert0: trip-point0 { 4264 temperature = <90000>; 4265 hysteresis = <2000>; 4266 type = "hot"; 4267 }; 4268 4269 aoss1_crit: aoss1-crit { 4270 temperature = <110000>; 4271 hysteresis = <0>; 4272 type = "critical"; 4273 }; 4274 }; 4275 }; 4276 4277 cpuss0-thermal { 4278 polling-delay-passive = <0>; 4279 polling-delay = <0>; 4280 4281 thermal-sensors = <&tsens0 5>; 4282 4283 trips { 4284 cpuss0_alert0: trip-point0 { 4285 temperature = <90000>; 4286 hysteresis = <2000>; 4287 type = "hot"; 4288 }; 4289 cpuss0_crit: cluster0-crit { 4290 temperature = <110000>; 4291 hysteresis = <0>; 4292 type = "critical"; 4293 }; 4294 }; 4295 }; 4296 4297 cpuss1-thermal { 4298 polling-delay-passive = <0>; 4299 polling-delay = <0>; 4300 4301 thermal-sensors = <&tsens0 6>; 4302 4303 trips { 4304 cpuss1_alert0: trip-point0 { 4305 temperature = <90000>; 4306 hysteresis = <2000>; 4307 type = "hot"; 4308 }; 4309 cpuss1_crit: cluster0-crit { 4310 temperature = <110000>; 4311 hysteresis = <0>; 4312 type = "critical"; 4313 }; 4314 }; 4315 }; 4316 4317 gpuss0-thermal { 4318 polling-delay-passive = <100>; 4319 polling-delay = <0>; 4320 4321 thermal-sensors = <&tsens1 1>; 4322 4323 trips { 4324 gpuss0_alert0: trip-point0 { 4325 temperature = <95000>; 4326 hysteresis = <2000>; 4327 type = "passive"; 4328 }; 4329 4330 gpuss0_crit: gpuss0-crit { 4331 temperature = <110000>; 4332 hysteresis = <0>; 4333 type = "critical"; 4334 }; 4335 }; 4336 4337 cooling-maps { 4338 map0 { 4339 trip = <&gpuss0_alert0>; 4340 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4341 }; 4342 }; 4343 }; 4344 4345 gpuss1-thermal { 4346 polling-delay-passive = <100>; 4347 polling-delay = <0>; 4348 4349 thermal-sensors = <&tsens1 2>; 4350 4351 trips { 4352 gpuss1_alert0: trip-point0 { 4353 temperature = <95000>; 4354 hysteresis = <2000>; 4355 type = "passive"; 4356 }; 4357 4358 gpuss1_crit: gpuss1-crit { 4359 temperature = <110000>; 4360 hysteresis = <0>; 4361 type = "critical"; 4362 }; 4363 }; 4364 4365 cooling-maps { 4366 map0 { 4367 trip = <&gpuss1_alert0>; 4368 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4369 }; 4370 }; 4371 }; 4372 4373 nspss0-thermal { 4374 polling-delay-passive = <0>; 4375 polling-delay = <0>; 4376 4377 thermal-sensors = <&tsens1 3>; 4378 4379 trips { 4380 nspss0_alert0: trip-point0 { 4381 temperature = <90000>; 4382 hysteresis = <2000>; 4383 type = "hot"; 4384 }; 4385 4386 nspss0_crit: nspss0-crit { 4387 temperature = <110000>; 4388 hysteresis = <0>; 4389 type = "critical"; 4390 }; 4391 }; 4392 }; 4393 4394 nspss1-thermal { 4395 polling-delay-passive = <0>; 4396 polling-delay = <0>; 4397 4398 thermal-sensors = <&tsens1 4>; 4399 4400 trips { 4401 nspss1_alert0: trip-point0 { 4402 temperature = <90000>; 4403 hysteresis = <2000>; 4404 type = "hot"; 4405 }; 4406 4407 nspss1_crit: nspss1-crit { 4408 temperature = <110000>; 4409 hysteresis = <0>; 4410 type = "critical"; 4411 }; 4412 }; 4413 }; 4414 4415 video-thermal { 4416 polling-delay-passive = <0>; 4417 polling-delay = <0>; 4418 4419 thermal-sensors = <&tsens1 5>; 4420 4421 trips { 4422 video_alert0: trip-point0 { 4423 temperature = <90000>; 4424 hysteresis = <2000>; 4425 type = "hot"; 4426 }; 4427 4428 video_crit: video-crit { 4429 temperature = <110000>; 4430 hysteresis = <0>; 4431 type = "critical"; 4432 }; 4433 }; 4434 }; 4435 4436 ddr-thermal { 4437 polling-delay-passive = <0>; 4438 polling-delay = <0>; 4439 4440 thermal-sensors = <&tsens1 6>; 4441 4442 trips { 4443 ddr_alert0: trip-point0 { 4444 temperature = <90000>; 4445 hysteresis = <2000>; 4446 type = "hot"; 4447 }; 4448 4449 ddr_crit: ddr-crit { 4450 temperature = <110000>; 4451 hysteresis = <0>; 4452 type = "critical"; 4453 }; 4454 }; 4455 }; 4456 4457 mdmss0-thermal { 4458 polling-delay-passive = <0>; 4459 polling-delay = <0>; 4460 4461 thermal-sensors = <&tsens1 7>; 4462 4463 trips { 4464 mdmss0_alert0: trip-point0 { 4465 temperature = <90000>; 4466 hysteresis = <2000>; 4467 type = "hot"; 4468 }; 4469 4470 mdmss0_crit: mdmss0-crit { 4471 temperature = <110000>; 4472 hysteresis = <0>; 4473 type = "critical"; 4474 }; 4475 }; 4476 }; 4477 4478 mdmss1-thermal { 4479 polling-delay-passive = <0>; 4480 polling-delay = <0>; 4481 4482 thermal-sensors = <&tsens1 8>; 4483 4484 trips { 4485 mdmss1_alert0: trip-point0 { 4486 temperature = <90000>; 4487 hysteresis = <2000>; 4488 type = "hot"; 4489 }; 4490 4491 mdmss1_crit: mdmss1-crit { 4492 temperature = <110000>; 4493 hysteresis = <0>; 4494 type = "critical"; 4495 }; 4496 }; 4497 }; 4498 4499 mdmss2-thermal { 4500 polling-delay-passive = <0>; 4501 polling-delay = <0>; 4502 4503 thermal-sensors = <&tsens1 9>; 4504 4505 trips { 4506 mdmss2_alert0: trip-point0 { 4507 temperature = <90000>; 4508 hysteresis = <2000>; 4509 type = "hot"; 4510 }; 4511 4512 mdmss2_crit: mdmss2-crit { 4513 temperature = <110000>; 4514 hysteresis = <0>; 4515 type = "critical"; 4516 }; 4517 }; 4518 }; 4519 4520 mdmss3-thermal { 4521 polling-delay-passive = <0>; 4522 polling-delay = <0>; 4523 4524 thermal-sensors = <&tsens1 10>; 4525 4526 trips { 4527 mdmss3_alert0: trip-point0 { 4528 temperature = <90000>; 4529 hysteresis = <2000>; 4530 type = "hot"; 4531 }; 4532 4533 mdmss3_crit: mdmss3-crit { 4534 temperature = <110000>; 4535 hysteresis = <0>; 4536 type = "critical"; 4537 }; 4538 }; 4539 }; 4540 4541 camera0-thermal { 4542 polling-delay-passive = <0>; 4543 polling-delay = <0>; 4544 4545 thermal-sensors = <&tsens1 11>; 4546 4547 trips { 4548 camera0_alert0: trip-point0 { 4549 temperature = <90000>; 4550 hysteresis = <2000>; 4551 type = "hot"; 4552 }; 4553 4554 camera0_crit: camera0-crit { 4555 temperature = <110000>; 4556 hysteresis = <0>; 4557 type = "critical"; 4558 }; 4559 }; 4560 }; 4561 }; 4562 4563 timer { 4564 compatible = "arm,armv8-timer"; 4565 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4566 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4567 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4568 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4569 }; 4570}; 4571